[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeMsi.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeMsi.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING    
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "peu_defines.h"

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

	setx    0x00000000cccccccc, %g1, %g2			!!!! Set up MSI32 address -must be 4 byte aligned
	setx	FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR, %g1, %g3
	stx     %g2, [%g3]
	
	setx    0xffffffffffffffff, %g1, %g2			!!!! Enable IMU error Logging
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %g3
	stx     %g2, [%g3]
	
	!setx    0xffffffffffffffff, %g1, %g2			!!!! Enable IMU error Interrupts
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR, %g1, %g3
	stx     %g2, [%g3]

								!!!! Make sure that any status bits are cleared
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR, %g1, %g3
	stx     %g2, [%g3]
	
	ldx     [%g3], %g4			!!! a read should force all writes to complete
	nop
	
MSI32_Evnt:
	nop
	! $EV trig_pc_d(1, @VA(.MAIN.MSI32_Evnt)) -> EnablePCIeIgCmd ("MSI32", 00000000000000ff, 0, 4, 1 )

	! now poll for the MSI event
	
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR, %g1, %g2
	setx	0x, %g1, %g3
	setx	0x020, %g1, %g4

delay_loop1:
	ldx	[%g2], %g5
	cmp     %g3,%g5
	bne	MSI64_Evnt
	nop
	dec	%g4
	brnz	%g4, delay_loop1
	nop
	b       test_failed
	nop

	
MSI64_Evnt:
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR, %g1, %g3
	ldx     [%g3], %g2					!!!! Read the IMU RDS Error Log Register
	
	setx    0xaabbccddeeff3344, %g1, %g2			!!!!  Set up MSI64 address -must be 4 byte aligned
	setx	FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR, %g1, %g3
	stx     %g2, [%g3]
	
	setx    0xffffffffffffffff, %g1, %g2			!!!! Make sure that any status bits are cleared
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR, %g1, %g3
	stx     %g2, [%g3]
	
	ldx     [%g3], %g4			!!! a read should force all writes to complete
	nop

MSI64_Evnt2:
	nop
	! $EV trig_pc_d(1, @VA(.MAIN.MSI64_Evnt2)) -> EnablePCIeIgCmd ("MSI64", 00000000000000ee, 0, 4, 1 )

	! now poll for the MSI event
	
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR, %g1, %g2
	setx	0x, %g1, %g3
	setx	0x020, %g1, %g4

delay_loop2:
	ldx	[%g2], %g5
	cmp     %g3,%g5
	bne	test_passed
	nop
	dec	%g4
	brnz	%g4, delay_loop2
	nop
	b       test_failed
	nop


test_passed:
	setx	FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR, %g1, %g3
	ldx     [%g3], %g2					!!!! Read the IMU RDS Error Log Register
	
	EXIT_GOOD

test_failed:
	EXIT_BAD
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeMsi.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#include "hboot.s"
	42	#include "peu_defines.h"
	43
	44	/************************************************************************
	45	Test case code start
	46	************************************************************************/
	47	.text
	48	.global main
	49
	50	main:
	51	ta T_CHANGE_HPRIV
	52	nop
	53
	54	setx 0x00000000cccccccc, %g1, %g2 !!!! Set up MSI32 address -must be 4 byte aligned
	55	setx FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR, %g1, %g3
	56	stx %g2, [%g3]
	57
	58	setx 0xffffffffffffffff, %g1, %g2 !!!! Enable IMU error Logging
	59	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR, %g1, %g3
	60	stx %g2, [%g3]
	61
	62	!setx 0xffffffffffffffff, %g1, %g2 !!!! Enable IMU error Interrupts
	63	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR, %g1, %g3
	64	stx %g2, [%g3]
65
66	!!!! Make sure that any status bits are cleared
67	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR, %g1, %g3
68	stx %g2, [%g3]
69
70	ldx [%g3], %g4 !!! a read should force all writes to complete
71	nop
72
73	MSI32_Evnt:
74	nop
75	! $EV trig_pc_d(1, @VA(.MAIN.MSI32_Evnt)) -> EnablePCIeIgCmd ("MSI32", 00000000000000ff, 0, 4, 1 )
76
77	! now poll for the MSI event
78
79	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR, %g1, %g2
80	setx 0x, %g1, %g3
81	setx 0x020, %g1, %g4
82
83	delay_loop1:
84	ldx [%g2], %g5
85	cmp %g3,%g5
86	bne MSI64_Evnt
87	nop
88	dec %g4
89	brnz %g4, delay_loop1
90	nop
91	b test_failed
92	nop
93
94
95	MSI64_Evnt:
96	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR, %g1, %g3
97	ldx [%g3], %g2 !!!! Read the IMU RDS Error Log Register
98
99	setx 0xaabbccddeeff3344, %g1, %g2 !!!! Set up MSI64 address -must be 4 byte aligned
100	setx FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR, %g1, %g3
101	stx %g2, [%g3]
102
103	setx 0xffffffffffffffff, %g1, %g2 !!!! Make sure that any status bits are cleared
104	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR, %g1, %g3
105	stx %g2, [%g3]
106
107	ldx [%g3], %g4 !!! a read should force all writes to complete
108	nop
109
110	MSI64_Evnt2:
111	nop
112	! $EV trig_pc_d(1, @VA(.MAIN.MSI64_Evnt2)) -> EnablePCIeIgCmd ("MSI64", 00000000000000ee, 0, 4, 1 )
113
114	! now poll for the MSI event
115
116	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR, %g1, %g2
117	setx 0x, %g1, %g3
118	setx 0x020, %g1, %g4
119
120	delay_loop2:
121	ldx [%g2], %g5
122	cmp %g3,%g5
123	bne test_passed
124	nop
125	dec %g4
126	brnz %g4, delay_loop2
127	nop
128	b test_failed
129	nop
130
131
132	test_passed:
133	setx FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR, %g1, %g3
134	ldx [%g3], %g2 !!!! Read the IMU RDS Error Log Register
135
136	EXIT_GOOD
137
138	test_failed:
139	EXIT_BAD
140
141