[OpenSPARC-T2-DV] / verif / diag / assembly / peu / PCIeReqId.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: PCIeReqId.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define PCIE_MEM64_OFFSET	0xc800000000

#define ENABLE_PCIE_LINK_TRAINING    
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "peu_defines.h"

#define MEM32_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
#define MEM64_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM64_OFFSET_BASE_REG_DATA)

#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) | IO_ACCESS_PA)

! with the Denali endpoint, it seems that bits 8-11 must be in [1..F]	
#define CFG0_RD_ADDR  mpeval(N2_PCIE_BASE_ADDR + 0x100)
#define CFG1_RD_ADDR  mpeval(CFG0_RD_ADDR + CFG1_ACCESS_PA)

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

	setx	FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_ADDR, %g1, %g2
	setx	IO_RD_ADDR, %g1, %g4
	setx	MEM64_ADDR, %g1, %g5
	setx	MEM32_ADDR, %g1, %g6
	setx	CFG0_RD_ADDR, %g1, %g3
	setx	CFG1_RD_ADDR, %g1, %g7

	
	! write "0AAA" into REQ_ID field of "DMC PCI Express Configuration Register".
scenerio1:
	set	0x0AAA, %g1
	stx     %g1, [%g2]
	ldx	[%g2], %g1

	
	! MEM32 load byte
	ldub	[%g6], %l0
	stb	%l0, [%g6 + 16]

	! MEM64 load byte
	ldub	[%g5], %l1
	stb	%l0, [%g5 + 16]

	! IO load byte
	ldub	[%g4], %l2
	stb	%l0, [%g4 + 14]

	! CFG0 load byte
	ldub	[%g3], %l3
	stb	%l0, [%g3 + 13]

	! CFG1 load byte
	ldub	[%g7], %l4
	stb	%l0, [%g7 + 16]


	! write "0555" into REQ_ID field of "DMC PCI Express Configuration Register".
scenerio2:
	set	0x0555, %g1
	stx     %g1, [%g2]
	ldx	[%g2], %g1


	! MEM32 load half-word
	lduh	[%g6 + 2], %l0
	sth	%l0, [%g6 + 18]

	! MEM64 load half-word
	lduh	[%g5 + 2], %l1
	sth	%l0, [%g5 + 18]

	! IO load half-word
	lduh	[%g4 + 2], %l2
	sth	%l0, [%g4 + 18]

	! CFG0 load half-word
	lduh	[%g3 + 2], %l3
	sth	%l0, [%g3 + 18]

	! CFG1 load half-word
	lduh	[%g7 + 2], %l4
	sth	%l0, [%g7 + 18]

	
	! write "ffff" into REQ_ID field of "DMC PCI Express Configuration Register".
scenerio3:
	set	0xffff, %g1
	stx     %g1, [%g2]
	ldx	[%g2], %g1

	! MEM32 Load word
	lduw	[%g6 + 4], %l0
	stw	%l0, [%g6 + 20]

	! MEM64 Load word
	lduw	[%g5 + 4], %l1
	stw	%l0, [%g5 + 20]

	! IO load word
	lduw	[%g4 + 4], %l2
	stw	%l0, [%g4 + 20]

	! CFG0 load word
	lduw	[%g3 + 4], %l3
	stw	%l0, [%g3 + 20]

	! CFG1 load word
	lduw	[%g7 + 4], %l4
	stw	%l0, [%g7 + 20]

	
	! write "012d" into REQ_ID field of "DMC PCI Express Configuration Register".
	! (for strange functional coverage object)
scenerio4:
	set	0x012d, %g1
	stx     %g1, [%g2]
	ldx	[%g2], %g1


	! MEM32 Load dword
	ldx	[%g6 + 8], %l0
	stx	%l0, [%g6 + 24]
	
	! MEM64 Load dword
	ldx	[%g5 + 8], %l1
	stx	%l0, [%g5 + 24]
	
	! IO load word
	lduw	[%g4 + 8], %l2
	stw	%l0, [%g4 + 24]

	! CFG0 load word
	lduw	[%g3 + 8], %l3
	stw	%l0, [%g3 + 24]

	! CFG1 load word
	lduw	[%g7 + 8], %l4
	stw	%l0, [%g7 + 24]

	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD

	
/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=MEM32_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
	.word 0x44556677
	.word 0x8899aabb
	.word 0xccccdddd
	.word 0xeeeeffff

SECTION       .DATA2 DATA_VA=MEM64_ADDR
attr_data {     
      Name = .DATA2,
      hypervisor,
      compressimage
}

.data
	.xword 0x1111111111111111
	.xword 0x2222222222222222
	.xword 0x3333333333333333
	.xword 0x4444444444444444
	.xword 0x5555555555555555
	.xword 0x6666666666666666
	.xword 0x7777777777777777
	.xword 0x8888888888888888


SECTION       .DATA3 DATA_VA=IO_RD_ADDR
attr_data {     
      Name = .DATA3,
      hypervisor,
      compressimage
}

.data
	.xword 0xdeadbeefdeadbeef

	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	
	.xword 0x0202020202020202
	.xword 0x0202020202020202
	.xword 0x0202020202020202
	.xword 0x0202020202020202
	
	.xword 0x0303030303030303		
	.xword 0x0303030303030303
	.xword 0x0303030303030303
	.xword 0x0303030303030303
	
	.xword 0x0404040404040404
	.xword 0x0404040404040404
	.xword 0x0404040404040404
	.xword 0x0404040404040404
		
	.xword 0xdeadbeefdeadbeef


SECTION       .DATA4 DATA_VA=CFG0_RD_ADDR
attr_data {     
      Name = .DATA4,
      hypervisor,
      compressimage
}

.data
	.xword 0xdeadbeefdeadbeef

	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101
	.xword 0x0101010101010101

	
SECTION       .DATA5 DATA_VA=CFG1_RD_ADDR
attr_data {     
      Name = .DATA5,
      hypervisor,
      compressimage
}
	
.data
	.xword	0x0000000000000000
	.xword	0x0000000000000000
	.xword	0x0000000000000000
	.xword	0x0000000000000000

	
/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: PCIeReqId.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define PCIE_MEM64_OFFSET 0xc800000000
	39
	40	#define ENABLE_PCIE_LINK_TRAINING
	41	#define MAIN_PAGE_HV_ALSO
	42
	43	#include "hboot.s"
	44	#include "peu_defines.h"
	45
	46	#define MEM32_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	47	#define MEM64_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM64_OFFSET_BASE_REG_DATA)
	48
	49	#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) \| IO_ACCESS_PA)
	50
	51	! with the Denali endpoint, it seems that bits 8-11 must be in [1..F]
	52	#define CFG0_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + 0x100)
	53	#define CFG1_RD_ADDR mpeval(CFG0_RD_ADDR + CFG1_ACCESS_PA)
	54
	55	/************************************************************************
	56	Test case code start
	57	************************************************************************/
	58	.text
	59	.global main
	60
	61	main:
	62	ta T_CHANGE_HPRIV
	63	nop
	64
65	setx FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_ADDR, %g1, %g2
66	setx IO_RD_ADDR, %g1, %g4
67	setx MEM64_ADDR, %g1, %g5
68	setx MEM32_ADDR, %g1, %g6
69	setx CFG0_RD_ADDR, %g1, %g3
70	setx CFG1_RD_ADDR, %g1, %g7
71
72
73	! write "0AAA" into REQ_ID field of "DMC PCI Express Configuration Register".
74	scenerio1:
75	set 0x0AAA, %g1
76	stx %g1, [%g2]
77	ldx [%g2], %g1
78
79
80	! MEM32 load byte
81	ldub [%g6], %l0
82	stb %l0, [%g6 + 16]
83
84	! MEM64 load byte
85	ldub [%g5], %l1
86	stb %l0, [%g5 + 16]
87
88	! IO load byte
89	ldub [%g4], %l2
90	stb %l0, [%g4 + 14]
91
92	! CFG0 load byte
93	ldub [%g3], %l3
94	stb %l0, [%g3 + 13]
95
96	! CFG1 load byte
97	ldub [%g7], %l4
98	stb %l0, [%g7 + 16]
99
100
101
102	! write "0555" into REQ_ID field of "DMC PCI Express Configuration Register".
103	scenerio2:
104	set 0x0555, %g1
105	stx %g1, [%g2]
106	ldx [%g2], %g1
107
108
109	! MEM32 load half-word
110	lduh [%g6 + 2], %l0
111	sth %l0, [%g6 + 18]
112
113	! MEM64 load half-word
114	lduh [%g5 + 2], %l1
115	sth %l0, [%g5 + 18]
116
117	! IO load half-word
118	lduh [%g4 + 2], %l2
119	sth %l0, [%g4 + 18]
120
121	! CFG0 load half-word
122	lduh [%g3 + 2], %l3
123	sth %l0, [%g3 + 18]
124
125	! CFG1 load half-word
126	lduh [%g7 + 2], %l4
127	sth %l0, [%g7 + 18]
128
129
130	! write "ffff" into REQ_ID field of "DMC PCI Express Configuration Register".
131	scenerio3:
132	set 0xffff, %g1
133	stx %g1, [%g2]
134	ldx [%g2], %g1
135
136	! MEM32 Load word
137	lduw [%g6 + 4], %l0
138	stw %l0, [%g6 + 20]
139
140	! MEM64 Load word
141	lduw [%g5 + 4], %l1
142	stw %l0, [%g5 + 20]
143
144	! IO load word
145	lduw [%g4 + 4], %l2
146	stw %l0, [%g4 + 20]
147
148	! CFG0 load word
149	lduw [%g3 + 4], %l3
150	stw %l0, [%g3 + 20]
151
152	! CFG1 load word
153	lduw [%g7 + 4], %l4
154	stw %l0, [%g7 + 20]
155
156
157	! write "012d" into REQ_ID field of "DMC PCI Express Configuration Register".
158	! (for strange functional coverage object)
159	scenerio4:
160	set 0x012d, %g1
161	stx %g1, [%g2]
162	ldx [%g2], %g1
163
164
165	! MEM32 Load dword
166	ldx [%g6 + 8], %l0
167	stx %l0, [%g6 + 24]
168
169	! MEM64 Load dword
170	ldx [%g5 + 8], %l1
171	stx %l0, [%g5 + 24]
172
173	! IO load word
174	lduw [%g4 + 8], %l2
175	stw %l0, [%g4 + 24]
176
177	! CFG0 load word
178	lduw [%g3 + 8], %l3
179	stw %l0, [%g3 + 24]
180
181	! CFG1 load word
182	lduw [%g7 + 8], %l4
183	stw %l0, [%g7 + 24]
184
185
186	test_passed:
187	EXIT_GOOD
188
189	test_failed:
190	EXIT_BAD
191
192
193	/************************************************************************
194	Test case data start
195	************************************************************************/
196
197	SECTION .DATA DATA_VA=MEM32_ADDR
198	attr_data {
199	Name = .DATA,
200	hypervisor,
201	compressimage
202	}
203
204	.data
205	.word 0x44556677
206	.word 0x8899aabb
207	.word 0xccccdddd
208	.word 0xeeeeffff
209
210	SECTION .DATA2 DATA_VA=MEM64_ADDR
211	attr_data {
212	Name = .DATA2,
213	hypervisor,
214	compressimage
215	}
216
217	.data
218	.xword 0x1111111111111111
219	.xword 0x2222222222222222
220	.xword 0x3333333333333333
221	.xword 0x4444444444444444
222	.xword 0x5555555555555555
223	.xword 0x6666666666666666
224	.xword 0x7777777777777777
225	.xword 0x8888888888888888
226
227
228	SECTION .DATA3 DATA_VA=IO_RD_ADDR
229	attr_data {
230	Name = .DATA3,
231	hypervisor,
232	compressimage
233	}
234
235	.data
236	.xword 0xdeadbeefdeadbeef
237
238	.xword 0x0101010101010101
239	.xword 0x0101010101010101
240	.xword 0x0101010101010101
241	.xword 0x0101010101010101
242
243	.xword 0x0202020202020202
244	.xword 0x0202020202020202
245	.xword 0x0202020202020202
246	.xword 0x0202020202020202
247
248	.xword 0x0303030303030303
249	.xword 0x0303030303030303
250	.xword 0x0303030303030303
251	.xword 0x0303030303030303
252
253	.xword 0x0404040404040404
254	.xword 0x0404040404040404
255	.xword 0x0404040404040404
256	.xword 0x0404040404040404
257
258	.xword 0xdeadbeefdeadbeef
259
260
261	SECTION .DATA4 DATA_VA=CFG0_RD_ADDR
262	attr_data {
263	Name = .DATA4,
264	hypervisor,
265	compressimage
266	}
267
268	.data
269	.xword 0xdeadbeefdeadbeef
270
271	.xword 0x0101010101010101
272	.xword 0x0101010101010101
273	.xword 0x0101010101010101
274	.xword 0x0101010101010101
275
276
277	SECTION .DATA5 DATA_VA=CFG1_RD_ADDR
278	attr_data {
279	Name = .DATA5,
280	hypervisor,
281	compressimage
282	}
283
284	.data
285	.xword 0x0000000000000000
286	.xword 0x0000000000000000
287	.xword 0x0000000000000000
288	.xword 0x0000000000000000
289
290
291	/************************************************************************/