projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: PCIeWrPeuDiagCsr.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define MAIN_PAGE_HV_ALSO | |
| 39 | ||
| 40 | #include "hboot.s" | |
| 41 | #include "peu_defines.h" | |
| 42 | #include "dmu_peu_regs.h" | |
| 43 | #include "rst_defines.h" | |
| 44 | ||
| 45 | .text | |
| 46 | .global main | |
| 47 | ||
| 48 | main: | |
| 49 | ta T_CHANGE_HPRIV | |
| 50 | nop | |
| 51 | ||
| 52 | /************************************************************ | |
| 53 | Write 1 to the RATE_SCALE field of the ILU DIAGNOSTIC CSR | |
| 54 | ************************************************************/ | |
| 55 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR, %g1, %g2 | |
| 56 | ldx [%g2], %g3 | |
| 57 | or %g3, 0x4, %g3 ! RATE SCALE is bits 3:2 | |
| 58 | stx %g3, [%g2] | |
| 59 | ldx [%g2], %g4 | |
| 60 | ||
| 61 | /************************************************************ | |
| 62 | Now do Subsystem RESET | |
| 63 | ************************************************************/ | |
| 64 | do_SSYS_RESET1: | |
| 65 | setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg | |
| 66 | mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data | |
| 67 | stx %g7, [%g5] ! Subsystem Reset | |
| 68 | ||
| 69 | mov 255, %l0 ! loop timeout count | |
| 70 | ||
| 71 | Wait4SsysReset1: | |
| 72 | ldx [%g5], %l7 ! check if reset bit has cleared | |
| 73 | brz %l7, After_Ssys_Reset1 | |
| 74 | nop | |
| 75 | dec %l0 | |
| 76 | brnz %l0, Wait4SsysReset1 | |
| 77 | nop | |
| 78 | ba test_failed ! Subsystem reset should have completed | |
| 79 | nop | |
| 80 | ||
| 81 | /********************************************************************* | |
| 82 | Load the ILU DIAGNOSTIC CSR | |
| 83 | *********************************************************************/ | |
| 84 | After_Ssys_Reset1: | |
| 85 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR, %g1, %g2 | |
| 86 | ldx [%g2], %g3 | |
| 87 | ||
| 88 | /************************************************************ | |
| 89 | Write 2 to the RATE_SCALE field of the ILU DIAGNOSTIC CSR | |
| 90 | ************************************************************/ | |
| 91 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR, %g1, %g2 | |
| 92 | ldx [%g2], %g3 | |
| 93 | or %g0, 0x8, %g3 ! RATE SCALE is bits 3:2 | |
| 94 | stx %g3, [%g2] | |
| 95 | ldx [%g2], %g4 | |
| 96 | ||
| 97 | /************************************************************ | |
| 98 | Now do Subsystem RESET | |
| 99 | ************************************************************/ | |
| 100 | do_SSYS_RESET2: | |
| 101 | setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg | |
| 102 | mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data | |
| 103 | stx %g7, [%g5] ! Subsystem Reset | |
| 104 | ||
| 105 | mov 255, %l0 ! loop timeout count | |
| 106 | ||
| 107 | Wait4SsysReset2: | |
| 108 | ldx [%g5], %l7 ! check if reset bit has cleared | |
| 109 | brz %l7, After_Ssys_Reset2 | |
| 110 | nop | |
| 111 | dec %l0 | |
| 112 | brnz %l0, Wait4SsysReset2 | |
| 113 | nop | |
| 114 | ba test_failed ! Subsystem reset should have completed | |
| 115 | nop | |
| 116 | ||
| 117 | /********************************************************************* | |
| 118 | Load the ILU DIAGNOSTIC CSR | |
| 119 | *********************************************************************/ | |
| 120 | After_Ssys_Reset2: | |
| 121 | setx FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR, %g1, %g2 | |
| 122 | ldx [%g2], %g3 | |
| 123 | ||
| 124 | test_passed: | |
| 125 | EXIT_GOOD | |
| 126 | ||
| 127 | test_failed: | |
| 128 | EXIT_BAD | |
| 129 |