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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / tsotool / n2_8t_ldst1_7.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_8t_ldst1_7.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define N_CPUS 8
39#define REGION_MAPPED_SIZE_RTL 8192
40#define REGION_SIZE_RTL (128 * 1024)
41#define RESULTS_BUF_SIZE_PER_CPU_RTL 1024
42#define PRIVATE_DATA_AREA_PER_CPU_RTL 64
43
44#define ALIGN_PAGE_8K .align 8192
45#define ALIGN_PAGE_64K .align 65536
46#define ALIGN_PAGE_512K .align 524288
47#define ALIGN_PAGE_4M .align 4194304
48#define USER_PAGE_CUSTOM_MAP
49
50SECTION .MY_HYP_SEC TEXT_VA = 0x1100150000
51attr_text {
52 Name=.MY_HYP_SEC,
53 hypervisor
54 }
55.text
56.global intr0x60_custom_trap
57intr0x60_custom_trap:
58 ldxa [%g0] 0x72, %g2;
59 ldxa [%g0] 0x74, %g1;
60 retry;
61
62.global intr0x190_custom_trap
63intr0x190_custom_trap:
64
65.global intr0x190_custom_trap
66intr0x190_custom_trap:
67
68#ifdef SJM
69! programming the JBI - not quite rrugho
70!=====================
71!setx 0x0000000006040012, %g1, %g2
72!setx 0x8503000010, %g1, %g3
73!stx %g2, [%g3]
74!!=====================
75!setx 0x0000000000000003, %g1, %g2
76!setx 0x8500000100, %g1, %g3
77!stx %g2, [%g3]
78!!=====================
79!setx 0x0000000000000000, %g1, %g2
80!setx 0x9800000000, %g1, %g3
81!stx %g2, [%g3]
82!!=====================
83!setx 0x0000000000000000, %g1, %g2
84!setx 0x9800000400, %g1, %g3
85!stx %g2, [%g3]
86!!=====================
87!setx 0x0000000000000003, %g1, %g2
88!setx 0x8500000108, %g1, %g3
89!stx %g2, [%g3]
90!!=====================
91!setx 0x0000000000000101, %g1, %g2
92!setx 0x9800000008, %g1, %g3
93!stx %g2, [%g3]
94!!=====================
95!setx 0x0000000000000000, %g1, %g2
96!setx 0x9800000408, %g1, %g3
97!stx %g2, [%g3]
98!!=====================
99!setx 0x0000000000000003, %g1, %g2
100!setx 0x8500000110, %g1, %g3
101!stx %g2, [%g3]
102!!=====================
103!setx 0x0000000000000202, %g1, %g2
104!setx 0x9800000010, %g1, %g3
105!stx %g2, [%g3]
106!!=====================
107!setx 0x0000000000000000, %g1, %g2
108!setx 0x9800000410, %g1, %g3
109!stx %g2, [%g3]
110!!=====================
111!setx 0x0000000000000003, %g1, %g2
112!setx 0x8500000118, %g1, %g3
113!stx %g2, [%g3]
114!!=====================
115!setx 0x0000000000000303, %g1, %g2
116!setx 0x9800000018, %g1, %g3
117!stx %g2, [%g3]
118!!=====================
119!setx 0x0000000000000000, %g1, %g2
120!setx 0x9800000418, %g1, %g3
121!stx %g2, [%g3]
122!!=====================
123!setx 0x0000000000000003, %g1, %g2
124!setx 0x8500000120, %g1, %g3
125!stx %g2, [%g3]
126!!=====================
127!setx 0x0000000000000404, %g1, %g2
128!setx 0x9800000020, %g1, %g3
129!stx %g2, [%g3]
130!!=====================
131!setx 0x0000000000000000, %g1, %g2
132!setx 0x9800000420, %g1, %g3
133!stx %g2, [%g3]
134!!=====================
135!setx 0x0000000000000003, %g1, %g2
136!setx 0x8500000128, %g1, %g3
137!stx %g2, [%g3]
138!!=====================
139!setx 0x0000000000000505, %g1, %g2
140!setx 0x9800000028, %g1, %g3
141!stx %g2, [%g3]
142!!=====================
143!setx 0x0000000000000000, %g1, %g2
144!setx 0x9800000428, %g1, %g3
145!stx %g2, [%g3]
146!!=====================
147!setx 0x0000000000000003, %g1, %g2
148!setx 0x8500000130, %g1, %g3
149!stx %g2, [%g3]
150!!=====================
151!setx 0x0000000000000606, %g1, %g2
152!setx 0x9800000030, %g1, %g3
153!stx %g2, [%g3]
154!!=====================
155!setx 0x0000000000000000, %g1, %g2
156!setx 0x9800000430, %g1, %g3
157!stx %g2, [%g3]
158!!=====================
159!setx 0x0000000000000003, %g1, %g2
160!setx 0x8500000138, %g1, %g3
161!stx %g2, [%g3]
162!!=====================
163!setx 0x0000000000000707, %g1, %g2
164!setx 0x9800000038, %g1, %g3
165!stx %g2, [%g3]
166!!=====================
167!setx 0x0000000000000000, %g1, %g2
168!setx 0x9800000438, %g1, %g3
169!stx %g2, [%g3]
170!!=====================
171!setx 0x0000000000000003, %g1, %g2
172!setx 0x8500000140, %g1, %g3
173!stx %g2, [%g3]
174!!=====================
175!setx 0x0000000000000808, %g1, %g2
176!setx 0x9800000040, %g1, %g3
177!stx %g2, [%g3]
178!!=====================
179!setx 0x0000000000000000, %g1, %g2
180!setx 0x9800000440, %g1, %g3
181!stx %g2, [%g3]
182!!=====================
183!setx 0x0000000000000003, %g1, %g2
184!setx 0x8500000148, %g1, %g3
185!stx %g2, [%g3]
186!!=====================
187!setx 0x0000000000000909, %g1, %g2
188!setx 0x9800000048, %g1, %g3
189!stx %g2, [%g3]
190!!=====================
191!setx 0x0000000000000000, %g1, %g2
192!setx 0x9800000448, %g1, %g3
193!stx %g2, [%g3]
194!!=====================
195!setx 0x0000000000000003, %g1, %g2
196!setx 0x8500000150, %g1, %g3
197!stx %g2, [%g3]
198!!=====================
199!setx 0x0000000000000a0a, %g1, %g2
200!setx 0x9800000050, %g1, %g3
201!stx %g2, [%g3]
202!!=====================
203!setx 0x0000000000000000, %g1, %g2
204!setx 0x9800000450, %g1, %g3
205!stx %g2, [%g3]
206!!=====================
207!setx 0x0000000000000003, %g1, %g2
208!setx 0x8500000158, %g1, %g3
209!stx %g2, [%g3]
210!!=====================
211!setx 0x0000000000000b0b, %g1, %g2
212!setx 0x9800000058, %g1, %g3
213!stx %g2, [%g3]
214!!=====================
215!setx 0x0000000000000000, %g1, %g2
216!setx 0x9800000458, %g1, %g3
217!stx %g2, [%g3]
218!!=====================
219!setx 0x0000000000000003, %g1, %g2
220!setx 0x8500000160, %g1, %g3
221!stx %g2, [%g3]
222!!=====================
223!setx 0x0000000000000c0c, %g1, %g2
224!setx 0x9800000060, %g1, %g3
225!stx %g2, [%g3]
226!!=====================
227!setx 0x0000000000000000, %g1, %g2
228!setx 0x9800000460, %g1, %g3
229!stx %g2, [%g3]
230!!=====================
231!setx 0x0000000000000003, %g1, %g2
232!setx 0x8500000168, %g1, %g3
233!stx %g2, [%g3]
234!!=====================
235!setx 0x0000000000000d0d, %g1, %g2
236!setx 0x9800000068, %g1, %g3
237!stx %g2, [%g3]
238!!=====================
239!setx 0x0000000000000000, %g1, %g2
240!setx 0x9800000468, %g1, %g3
241!stx %g2, [%g3]
242!!=====================
243!setx 0x0000000000000003, %g1, %g2
244!setx 0x8500000170, %g1, %g3
245!stx %g2, [%g3]
246!!=====================
247!setx 0x0000000000000e0e, %g1, %g2
248!setx 0x9800000070, %g1, %g3
249!stx %g2, [%g3]
250!!=====================
251!setx 0x0000000000000000, %g1, %g2
252!setx 0x9800000470, %g1, %g3
253!stx %g2, [%g3]
254!!=====================
255!setx 0x0000000000000003, %g1, %g2
256!setx 0x8500000178, %g1, %g3
257!stx %g2, [%g3]
258!!=====================
259!setx 0x0000000000000f0f, %g1, %g2
260!setx 0x9800000078, %g1, %g3
261!stx %g2, [%g3]
262!!=====================
263!setx 0x0000000000000000, %g1, %g2
264!setx 0x9800000478, %g1, %g3
265!stx %g2, [%g3]
266!!=====================
267!setx 0x000000000000007f, %g1, %g2
268!setx 0x8503000008, %g1, %g3
269!stx %g2, [%g3]
270!!=====================
271!setx 0x0000000000001010, %g1, %g2
272!setx 0x9800000080, %g1, %g3
273!stx %g2, [%g3]
274!!=====================
275!setx 0x0000000000000000, %g1, %g2
276!setx 0x9800000480, %g1, %g3
277!stx %g2, [%g3]
278!!=====================
279!setx 0x0000000000001111, %g1, %g2
280!setx 0x9800000088, %g1, %g3
281!stx %g2, [%g3]
282!!=====================
283!setx 0x0000000000000000, %g1, %g2
284!setx 0x9800000488, %g1, %g3
285!stx %g2, [%g3]
286!!=====================
287!setx 0x0000000000000000, %g1, %g2
288!setx 0x9300000c00, %g1, %g3
289!stx %g2, [%g3]
290!!=====================
291!setx 0x0000000000000000, %g1, %g2
292!setx 0x9300000e20, %g1, %g3
293!stx %g2, [%g3]
294!!=====================
295!setx 0x0000000000000000, %g1, %g2
296!setx 0x9300000e28, %g1, %g3
297!stx %g2, [%g3]
298!!=====================
299!setx 0x0000000000000000, %g1, %g2
300!setx 0x9300000e38, %g1, %g3
301!stx %g2, [%g3]
302!!=====================
303!setx 0x0000000000000008, %g1, %g2
304!setx 0x8503000018, %g1, %g3
305!stx %g2, [%g3]
306!!=====================
307!setx 0x0000000000000000, %g1, %g2
308!setx 0x9800000828, %g1, %g3
309!stx %g2, [%g3]
310!!=====================
311!setx 0x0000000000000000, %g1, %g2
312!setx 0x8503000028, %g1, %g3
313!stx %g2, [%g3]
314!!=====================
315!setx 0x0000000000000001, %g1, %g2
316!setx 0x8503000020, %g1, %g3
317!stx %g2, [%g3]
318!!=====================
319
320/***********************************************************************
321 Disable L2 Cache Visibility Port
322 ***********************************************************************/
323
324setx 0x0000000000000000, %g1, %g2
325setx 0x9800001800, %g1, %g3
326stx %g2, [%g3]
327!=====================
328setx 0x0000000000000000, %g1, %g2
329setx 0x9800001820, %g1, %g3
330stx %g2, [%g3]
331!=====================
332setx 0x0000000000000000, %g1, %g2
333setx 0x9800001828, %g1, %g3
334stx %g2, [%g3]
335!=====================
336setx 0x0000000000000000, %g1, %g2
337setx 0x9800001830, %g1, %g3
338stx %g2, [%g3]
339!=====================
340setx 0x0000000000000000, %g1, %g2
341setx 0x9800001838, %g1, %g3
342stx %g2, [%g3]
343!=====================
344setx 0x0000000000000000, %g1, %g2
345setx 0x9800001840, %g1, %g3
346stx %g2, [%g3]
347!=====================
348
349/***********************************************************************
350 Disable IOBridge Visibility Ports
351 ***********************************************************************/
352
353setx 0x0000000000000000, %g1, %g2
354setx 0x9800001000, %g1, %g3
355stx %g2, [%g3]
356!=====================
357setx 0x0000000000000000, %g1, %g2
358setx 0x9800002000, %g1, %g3
359stx %g2, [%g3]
360!=====================
361setx 0x0000000000000000, %g1, %g2
362setx 0x9800002008, %g1, %g3
363stx %g2, [%g3]
364!=====================
365setx 0x0000000000000000, %g1, %g2
366setx 0x9800002100, %g1, %g3
367stx %g2, [%g3]
368!=====================
369setx 0x0000000000000000, %g1, %g2
370setx 0x9800002140, %g1, %g3
371stx %g2, [%g3]
372!=====================
373setx 0x0000000000000000, %g1, %g2
374setx 0x9800002160, %g1, %g3
375stx %g2, [%g3]
376!=====================
377setx 0x0000000000000000, %g1, %g2
378setx 0x9800002180, %g1, %g3
379stx %g2, [%g3]
380!=====================
381setx 0x0000000000000000, %g1, %g2
382setx 0x98000021a0, %g1, %g3
383stx %g2, [%g3]
384!=====================
385setx 0x0000000000000000, %g1, %g2
386setx 0x9800002148, %g1, %g3
387stx %g2, [%g3]
388!=====================
389setx 0x0000000000000000, %g1, %g2
390setx 0x9800002168, %g1, %g3
391stx %g2, [%g3]
392!=====================
393setx 0x0000000000000000, %g1, %g2
394setx 0x9800002188, %g1, %g3
395stx %g2, [%g3]
396!=====================
397setx 0x0000000000000000, %g1, %g2
398setx 0x98000021a8, %g1, %g3
399stx %g2, [%g3]
400!=====================
401setx 0x0000000000000000, %g1, %g2
402setx 0x9800002150, %g1, %g3
403stx %g2, [%g3]
404!=====================
405setx 0x0000000000000000, %g1, %g2
406setx 0x9800002170, %g1, %g3
407stx %g2, [%g3]
408!=====================
409setx 0x0000000000000000, %g1, %g2
410setx 0x9800002190, %g1, %g3
411stx %g2, [%g3]
412!=====================
413setx 0x0000000000000000, %g1, %g2
414setx 0x98000021b0, %g1, %g3
415stx %g2, [%g3]
416!=====================
417
418/***********************************************************************
419 Configure jbi controller
420 ***********************************************************************/
421
422setx 0x03fb303e00000001, %g1, %g2
423setx 0x8000000000, %g1, %g3
424stx %g2, [%g3]
425!=====================
426setx 0x000000007033fe0f, %g1, %g2
427setx 0x8000000008, %g1, %g3
428stx %g2, [%g3]
429!=====================
430setx 0x0000003fc0000000, %g1, %g2
431setx 0x80000100a0, %g1, %g3
432stx %g2, [%g3]
433!=====================
434setx 0x00000000fe0003ff, %g1, %g2
435setx 0x8000004100, %g1, %g3
436stx %g2, [%g3]
437!=====================
438
439/***********************************************************************
440 IOSYNC cycles to start sjm
441 ***********************************************************************/
442
443setx 0xdeadbeefdeadbeef, %g1, %g2
444setx 0xcf00beef00, %g1, %g3
445stx %g2, [%g3]
446!=====================
447setx 0xdeadbeefdeadbeef, %g1, %g2
448setx 0xef00beef00, %g1, %g3
449stx %g2, [%g3]
450
451!=============================
452done;
453
454#else
455#ifdef DC_ON_OFF
456
457 and %i0, 0x1, %i0
458 brz %i0, on
459 nop
460
461 mov 0xd, %i0
462 ba finish_dc_on_off
463 stxa %l0, [%g0] 0x45 /* turn D-cache off */
464on:
465 mov 0xf, %i0
466 stxa %i0, [%g0] 0x45 /* turn D-cache back on */
467
468finish_dc_on_off:
469 done
470
471#else
472 stxa %i0, [%g0] 0x73;
473 done;
474#endif
475#endif
476!============================================================================
477
478#define ENABLE_T0_Fp_exception_ieee_754_0x21
479#define ENABLE_T0_Fp_exception_other_0x22
480#define ENABLE_T0_Fp_disabled_0x20
481#define ENABLE_T0_Illegal_instruction_0x10
482#define ENABLE_T1_Illegal_instruction_0x10
483#define ENABLE_HT0_Illegal_instruction_0x10
484#define ENABLE_HT1_Illegal_instruction_0x10
485#define ENABLE_T0_Clean_Window_0x24
486#define MAIN_PAGE_NUCLEUS_ALSO
487#define MAIN_PAGE_HV_ALSO
488#define MAIN_PAGE_VA_IS_RA_ALSO
489
490
491
492
493#define H_T0_Trap_Instruction_0
494#define My_T0_Trap_Instruction_0 \
495 ta 0x90; \
496 done;
497
498#define H_HT0_HTrap_Instruction_0 intr0x190_custom_trap
499#ifdef SJM
500#define My_HT0_HTrap_Instruction_0 \
501 setx intr0x190_custom_trap, %g1, %g2; \
502 jmp %g2; nop
503#else
504#define My_HT0_HTrap_Instruction_0 \
505 stxa %i0, [%g0] 0x73; \
506 done;
507#endif
508
509#define H_HT0_Interrupt_0x60 intr0x60_custom_trap
510#define My_HT0_Interrupt_0x60 \
511 ldxa [%g0] 0x72, %g2; \
512 ldxa [%g0] 0x74, %g1; \
513 retry;
514#define H_HT0_Trap_Instruction_5
515#define My_HT0_Trap_Instruction_5 \
516 ldxa [%g0 + %g0]0x45, %g1; \
517 membar #Sync; \
518 xor %g1, 19, %g1; \
519 stxa %g1, [%g0 + %g0]0x45; \
520 wrpr %g0, 0x200, %pstate;
521 done;
522
523#ifndef THREAD_COUNT
524#define THREAD_COUNT 8
525#endif
526
527#ifndef THREAD_STRIDE
528#define THREAD_STRIDE 1
529#endif
530#define SKIP_TRAPCHECK
531! force ta T_RD_THID to return thread%8 (aka 0-7)
532#define PORTABLE_CORE
533#include "hboot.s"
534
535
536!try later:
537! stxa %l6, [$8] (0x22 | ($2 & 0x9)) ! ASI is randomly set
538!===========
539define(BST_INIT, `
540 add $6, ($7 & 0xfff0), $8 ! 4-byte align the offset
541 stxa %l6, [$8] 0x22 ! ASI is randomly set
542')
543
544!try later:
545!ldda [$8] (0x22 | ($2 & 0x9)), %l6 ! ASI is randomly set
546!===========
547define(BLD_INIT, `
548 add $6, ($7 & 0xfff0), $8 ! 4-byte align the offset
549 ldda [$8] 0x22, %l6 ! ASI is randomly set
550')
551
552define(CHECK_PROC_ID,`
553check_cpu_id:
554
555 wr %g0, 0x4, %fprs /* make sure fef is 1 */
556 mov THREAD_STRIDE, %l2
557 th_fork(thread,%l0)
558
559thread_0:
560#ifdef SJM
561 ta 0x30
562#endif
563 mov 0, %g1
564 udivx %g1, %l2, %g1
565 ba entry_point; nop
566
567
568thread_1:
569 mov 1, %g1
570 udivx %g1, %l2, %g1
571 ba entry_point; nop
572
573thread_2:
574 mov 2, %g1
575 udivx %g1, %l2, %g1
576 ba entry_point; nop
577
578thread_3:
579 mov 3, %g1
580 udivx %g1, %l2, %g1
581 ba entry_point; nop
582
583thread_4:
584 mov 4, %g1
585 udivx %g1, %l2, %g1
586 ba entry_point; nop
587
588thread_5:
589 mov 5, %g1
590 udivx %g1, %l2, %g1
591 ba entry_point; nop
592
593thread_6:
594 mov 6, %g1
595 udivx %g1, %l2, %g1
596 ba entry_point; nop
597
598thread_7:
599 mov 7, %g1
600 udivx %g1, %l2, %g1
601 ba entry_point; nop
602
603thread_8:
604 mov 8, %g1
605 udivx %g1, %l2, %g1
606 ba entry_point; nop
607
608thread_9:
609 mov 9, %g1
610 udivx %g1, %l2, %g1
611 ba entry_point; nop
612
613thread_10:
614 mov 10, %g1
615 udivx %g1, %l2, %g1
616 ba entry_point; nop
617
618thread_11:
619 mov 11, %g1
620 udivx %g1, %l2, %g1
621 ba entry_point; nop
622
623thread_12:
624 mov 12, %g1
625 udivx %g1, %l2, %g1
626 ba entry_point; nop
627
628thread_13:
629 mov 13, %g1
630 udivx %g1, %l2, %g1
631 ba entry_point; nop
632
633thread_14:
634 mov 14, %g1
635 udivx %g1, %l2, %g1
636 ba entry_point; nop
637
638thread_15:
639 mov 15, %g1
640 udivx %g1, %l2, %g1
641 ba entry_point; nop
642
643thread_16:
644 mov 16, %g1
645 udivx %g1, %l2, %g1
646 ba entry_point; nop
647
648thread_17:
649 mov 17, %g1
650 udivx %g1, %l2, %g1
651 ba entry_point; nop
652
653thread_18:
654 mov 18, %g1
655 udivx %g1, %l2, %g1
656 ba entry_point; nop
657
658thread_19:
659 mov 19, %g1
660 udivx %g1, %l2, %g1
661 ba entry_point; nop
662
663thread_20:
664 mov 20, %g1
665 udivx %g1, %l2, %g1
666 ba entry_point; nop
667
668thread_21:
669 mov 21, %g1
670 udivx %g1, %l2, %g1
671 ba entry_point; nop
672
673thread_22:
674 mov 22, %g1
675 udivx %g1, %l2, %g1
676 ba entry_point; nop
677
678thread_23:
679 mov 23, %g1
680 udivx %g1, %l2, %g1
681 ba entry_point; nop
682
683thread_24:
684 mov 24, %g1
685 udivx %g1, %l2, %g1
686 ba entry_point; nop
687
688thread_25:
689 mov 25, %g1
690 udivx %g1, %l2, %g1
691 ba entry_point; nop
692
693thread_26:
694 mov 26, %g1
695 udivx %g1, %l2, %g1
696 ba entry_point; nop
697
698
699thread_27:
700 mov 27, %g1
701 udivx %g1, %l2, %g1
702 ba entry_point; nop
703
704thread_28:
705 mov 28, %g1
706 udivx %g1, %l2, %g1
707 ba entry_point; nop
708
709thread_29:
710 mov 29, %g1
711 udivx %g1, %l2, %g1
712 ba entry_point; nop
713
714thread_30:
715 mov 30, %g1
716 udivx %g1, %l2, %g1
717 ba entry_point; nop
718
719thread_31:
720 mov 31, %g1
721 udivx %g1, %l2, %g1
722 ba entry_point; nop
723
724thread_32:
725 mov 32, %g1
726 udivx %g1, %l2, %g1
727 ba entry_point; nop
728
729thread_33:
730 mov 33, %g1
731 udivx %g1, %l2, %g1
732 ba entry_point; nop
733
734thread_34:
735 mov 34, %g1
736 udivx %g1, %l2, %g1
737 ba entry_point; nop
738
739thread_35:
740 mov 35, %g1
741 udivx %g1, %l2, %g1
742 ba entry_point; nop
743
744thread_36:
745 mov 36, %g1
746 udivx %g1, %l2, %g1
747 ba entry_point; nop
748
749thread_37:
750 mov 37, %g1
751 udivx %g1, %l2, %g1
752 ba entry_point; nop
753
754thread_38:
755 mov 38, %g1
756 udivx %g1, %l2, %g1
757 ba entry_point; nop
758
759thread_39:
760 mov 39, %g1
761 udivx %g1, %l2, %g1
762 ba entry_point; nop
763
764thread_40:
765 mov 40, %g1
766 udivx %g1, %l2, %g1
767 ba entry_point; nop
768
769thread_41:
770 mov 41, %g1
771 udivx %g1, %l2, %g1
772 ba entry_point; nop
773
774thread_42:
775 mov 42, %g1
776 udivx %g1, %l2, %g1
777 ba entry_point; nop
778
779thread_43:
780 mov 43, %g1
781 udivx %g1, %l2, %g1
782 ba entry_point; nop
783
784thread_44:
785 mov 44, %g1
786 udivx %g1, %l2, %g1
787 ba entry_point; nop
788
789thread_45:
790 mov 45, %g1
791 udivx %g1, %l2, %g1
792 ba entry_point; nop
793
794thread_46:
795 mov 46, %g1
796 udivx %g1, %l2, %g1
797 ba entry_point; nop
798
799thread_47:
800 mov 47, %g1
801 udivx %g1, %l2, %g1
802 ba entry_point; nop
803
804thread_48:
805 mov 48, %g1
806 udivx %g1, %l2, %g1
807 ba entry_point; nop
808
809thread_49:
810 mov 49, %g1
811 udivx %g1, %l2, %g1
812 ba entry_point; nop
813
814thread_50:
815 mov 50, %g1
816 udivx %g1, %l2, %g1
817 ba entry_point; nop
818
819thread_51:
820 mov 51, %g1
821 udivx %g1, %l2, %g1
822 ba entry_point; nop
823
824thread_52:
825 mov 52, %g1
826 udivx %g1, %l2, %g1
827 ba entry_point; nop
828
829thread_53:
830 mov 53, %g1
831 udivx %g1, %l2, %g1
832 ba entry_point; nop
833
834thread_54:
835 mov 54, %g1
836 udivx %g1, %l2, %g1
837 ba entry_point; nop
838
839thread_55:
840 mov 55, %g1
841 udivx %g1, %l2, %g1
842 ba entry_point; nop
843
844thread_56:
845 mov 56, %g1
846 udivx %g1, %l2, %g1
847 ba entry_point; nop
848
849thread_57:
850 mov 57, %g1
851 udivx %g1, %l2, %g1
852 ba entry_point; nop
853
854thread_58:
855 mov 58, %g1
856 udivx %g1, %l2, %g1
857 ba entry_point; nop
858
859thread_59:
860 mov 59, %g1
861 udivx %g1, %l2, %g1
862 ba entry_point; nop
863
864thread_60:
865 mov 60, %g1
866 udivx %g1, %l2, %g1
867 ba entry_point; nop
868
869thread_61:
870 mov 61, %g1
871 udivx %g1, %l2, %g1
872 ba entry_point; nop
873
874thread_62:
875 mov 62, %g1
876 udivx %g1, %l2, %g1
877 ba entry_point; nop
878
879thread_63:
880 mov 63, %g1
881 udivx %g1, %l2, %g1
882 ba entry_point; nop
883
884entry_point:
885#ifdef RTGPRIV
886 ta T_CHANGE_PRIV
887#endif
888
889')
890! --- Common Macro Definitions ---
891!
892! macros will be instantiated with these arguments
893! macro_name(P#, rand#, my_cpu#, PA_val, VA_val, VA_reg, VA_offset, \
894! tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3)
895!
896! P# - Pid, just in case one needs unique number
897! rand# - random number
898! my_cpu# - CPU id
899! PA_val - shared memory physisal address value
900! VA_val - shared memory virtual address value
901! VA_reg - register containing VA region base address
902! VA_offset - VA_reg + VA_offset will give correct VA address value
903! tmp_reg0-tmp_reg3 - integer registers for arbitrary use within the macro
904! tmp_reg0 & tmp_reg1 are even-odd register pair
905!
906! VA_val may be incorrect since VA will be determined at compile time by assembler
907! and may not available at diag generation time, but VA_reg+VA_offset is valid
908!
909! ex. SAMPLE(1, 1249, 0, 0x43400100, 0x100, %i1, 0x100, %l6, %l7, %o5, %l3)
910!
911! Sample macro 1:
912! load unsigned byte from the given shared addr into tmp_reg1
913! the given shared addr is 4-byte aligned and we will randomly
914! pick one byte from the 4 bytes.
915!
916! define(SAMPLE, `
917! ldub [$6+$7+($2 mod 4)], $8
918! ')
919!
920! Can also use C-like macro definition format.
921!
922! Sample macro 2:
923! issue an "ldda" instruction to the randomly picked shared location
924! (aligned it to 16-byte boundary first) with a random ASI value among
925! 0x22, 0x23, 0x2a, and 0x2b (utilizing the provided "rand" value).
926!
927! #define BLD_INIT(Pid, rand, my_cpu, PA_val, \
928! VA_val, VA_reg, VA_offset, \
929! tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
930! add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
931! ldda [tmp_reg2] (0x22 | (rand & 0x9)), tmp_reg0;
932!
933! ---
934
935! Macro NOPTRAIN
936! Train of NOPs
937
938#define NOPTRAIN(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
939 nop;\
940 nop;\
941 nop;\
942 nop;
943
944
945! Macro STTRAIN4
946! Train of total 4 of UW stores.
947! Note: doesn't use shared addresses
948
949#define STTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
950 set 5120, tmp_reg1; \
951 add %i0, tmp_reg1, tmp_reg1; \
952 set rand, tmp_reg2; \
953 stw tmp_reg2, [tmp_reg1]; \
954 stw tmp_reg2, [tmp_reg1+4]; \
955 stw tmp_reg2, [tmp_reg1+8]; \
956 stw tmp_reg2, [tmp_reg1+16];
957
958! Macro STTRAIN8
959! Train of total 8 of UW stores
960
961#define STTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
962 set 5120, tmp_reg1; \
963 add %i0, tmp_reg1, tmp_reg1; \
964 set rand, tmp_reg2; \
965 add tmp_reg2, rand % 4096, tmp_reg3; \
966 stw tmp_reg2, [tmp_reg1]; \
967 stw tmp_reg2, [tmp_reg1+4]; \
968 stw tmp_reg2, [tmp_reg1+8]; \
969 stw tmp_reg2, [tmp_reg1+12]; \
970 stw tmp_reg3, [tmp_reg1+4]; \
971 stw tmp_reg3, [tmp_reg1+12]; \
972 stw tmp_reg3, [tmp_reg1]; \
973 stw tmp_reg3, [tmp_reg1+8];
974
975! Macro LDTRAIN4
976! Train of total 4 of UW Loads
977! Note the values of those loads inside the macro will not be analized,
978! even though the accesses are [possibly] made to the shared locations
979
980#define LDTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
981 ld [%i0], tmp_reg1; \
982 ld [%i1+4], tmp_reg1; \
983 ld [%i2+8], tmp_reg1; \
984 ld [%i3+12], tmp_reg1;
985
986! Macro LDTRAIN8
987
988#define LDTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
989 ld [%i3], tmp_reg1; \
990 ld [%i2+4], tmp_reg1; \
991 ld [%i1+8], tmp_reg2; \
992 ld [%i0+12], tmp_reg2; \
993 ld [%i3+4], tmp_reg3; \
994 ld [%i2], tmp_reg3; \
995 ld [%i1+12], tmp_reg4; \
996 ld [%i0+8], tmp_reg4;
997
998! Macro PREFETCHTRAIN4
999
1000#define PREFETCHTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1001 prefetch [%i0+4], 0; \
1002 prefetch [%i1+12], 0; \
1003 prefetch [%i2+8], 0; \
1004 prefetch [%i3], 0;
1005
1006! Macro PREFETCHTRAIN8
1007
1008#define PREFETCHTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1009 prefetch [%i3], 0; \
1010 prefetch [%i2+4], 0; \
1011 prefetch [%i1+8], 0; \
1012 prefetch [%i0+12], 0; \
1013 prefetch [%i3+4], 1; \
1014 prefetch [%i2], 1; \
1015 prefetch [%i1+12], 1; \
1016 prefetch [%i0+8], 1;
1017
1018! Macro CASTRAIN4
1019! This is an interesting macro that will probably create the write congessions
1020! access to the shared locations (offsets from bases have to be adjusted)
1021! the values of the locations are not changed, so it should not affect analysis
1022
1023#define CASTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1024 set 128, tmp_reg1;\
1025 add %i0, tmp_reg1, tmp_reg1;\
1026 set 256, tmp_reg2;\
1027 add %i1, tmp_reg2, tmp_reg2;\
1028 ld [tmp_reg1], tmp_reg3;\
1029 ld [tmp_reg2], tmp_reg4;\
1030 cas [tmp_reg1], tmp_reg3, tmp_reg3;\
1031 cas [tmp_reg1], tmp_reg3, tmp_reg3;\
1032 cas [tmp_reg2], tmp_reg4, tmp_reg4;\
1033 cas [tmp_reg2], tmp_reg4, tmp_reg4;
1034
1035! CASTRAIN8
1036! yet another flavor of cas train theme that actually always use shared locations
1037! given by the specified instance arguments for the first 4 cases
1038! and then follows then with another 4 to a randomized offset
1039
1040#define CASTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1041 add VA_reg, VA_offset, tmp_reg1;\
1042 add VA_reg, (rand&0x0ffc), tmp_reg2;\
1043 ld [tmp_reg1], tmp_reg3;\
1044 cas [tmp_reg1], tmp_reg3, tmp_reg3;\
1045 cas [tmp_reg1], tmp_reg3, tmp_reg3;\
1046 cas [tmp_reg1], tmp_reg3, tmp_reg3;\
1047 cas [tmp_reg1], tmp_reg3, tmp_reg3;\
1048 ld [tmp_reg2], tmp_reg4;\
1049 cas [tmp_reg2], tmp_reg4, tmp_reg4;\
1050 cas [tmp_reg2], tmp_reg4, tmp_reg4;\
1051 cas [tmp_reg2], tmp_reg4, tmp_reg4;\
1052 cas [tmp_reg2], tmp_reg4, tmp_reg4;
1053
1054! Macro ST_BR_ANLD_CAS
1055! this is meant to reproduce NG6025
1056! the scenario is the anulled load in the delay slot of the branch is
1057! not wiped completely, which creates false RAW hazard, and the following cas
1058! is getting screwed
1059! WARNING: there is a store to the %i0+128, which can potentially be a shared
1060! location. When using this macro, make sure that the vicinity of offset 128 in
1061! region 0 is not used
1062
1063#define ST_BR_ANLD_CAS(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1064 set 128, tmp_reg1;\
1065 add %i0, tmp_reg1, tmp_reg1;\
1066 set rand, tmp_reg3;\
1067 stw tmp_reg3, [tmp_reg1];\
1068 ba,a 1;\
1069 cas [tmp_reg1], tmp_reg3, tmp_reg4;
1070
1071#define ASI_BLOCK(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1072 setx 0x060, tmp_reg1, tmp_reg2; \
1073 stxa %g0, [tmp_reg2] 0x38;
1074
1075! Macro SELF_MODIFY
1076! do a read-unmodify-write at address pc + random[0..0x80]
1077! this is targetted to catch bugs due to sharing/modification
1078! of data between D$ and I$. (e.g. Niagara1, Bug #6372)
1079! 1. 0x80 chosen arbitrarily, is another number better
1080! 2. should we include an iflush ?
1081! 3. WT.MACRO.SELF_MODIFY should be given a small non-0 weight by default
1082! 4. Possible variation: a macro which only does a load
1083! from the instruction stream instead of a load-store.
1084! (Niagara1 bug #6372 did not involve stores to instruction
1085! stream, just sharing of unmodified data between I$ and D$.)
1086! 5. this macro needs text segment to be writable. On system runs,
1087! this is achieved by using a special map file for the linker.
1088! - sgh, 25 may 04
1089
1090#define SELF_MODIFY(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1091 rd %pc, tmp_reg0; \
1092 ld [ tmp_reg0 + (rand & 0x7c)], tmp_reg1; \
1093 st tmp_reg1, [ tmp_reg0 + (rand & 0x7c)]
1094
1095#define ASI_BLOCK(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1096 setx 0x060, tmp_reg1, tmp_reg2; \
1097 stxa %g0, [tmp_reg2] 0x38;
1098
1099
1100#define ASI_BLOCK_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1101 setx 0x8559e06ff33bad10, tmp_reg1, tmp_reg2; \
1102 stxa %g0, [tmp_reg2] 0x80;
1103
1104#define PREFETCH_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1105 setx 0x8559e06ff33bad10, tmp_reg1, tmp_reg2; \
1106 prefetch [tmp_reg2], 0; \
1107 prefetch [tmp_reg2+4], 1; \
1108 prefetch [tmp_reg2+8], 2; \
1109 prefetch [tmp_reg2+12], 3; \
1110 prefetch [tmp_reg2+4], 4; \
1111 prefetch [tmp_reg2], 5; \
1112 prefetch [tmp_reg2+12], 6; \
1113 prefetch [tmp_reg2+8], 7;
1114
1115#define LOAD_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1116 setx 0x8559e06ff33bad10, tmp_reg1, tmp_reg2; \
1117 ld [tmp_reg2], tmp_reg1; \
1118 ld [tmp_reg2+4], tmp_reg1; \
1119 ld [tmp_reg2+8], tmp_reg1; \
1120 ld [tmp_reg2+12], tmp_reg1;
1121
1122
1123
1124#define STORE_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1125 setx 0x8559e06ff33bad10, tmp_reg2, tmp_reg1; \
1126 set rand, tmp_reg2; \
1127 add tmp_reg2, rand % 4096, tmp_reg3; \
1128 stw tmp_reg2, [tmp_reg1]; \
1129 stw tmp_reg2, [tmp_reg1+4]; \
1130 stw tmp_reg2, [tmp_reg1+8]; \
1131 stw tmp_reg2, [tmp_reg1+12]; \
1132 stw tmp_reg3, [tmp_reg1+4]; \
1133 stw tmp_reg3, [tmp_reg1+12]; \
1134 stw tmp_reg3, [tmp_reg1]; \
1135 stw tmp_reg3, [tmp_reg1+8];
1136
1137#define CAS_VA_HOLE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1138 setx 0x8559e06ff33bad10, tmp_reg3, tmp_reg1; \
1139 setx 0x8559e06ff33bad10, tmp_reg3, tmp_reg2; \
1140 add tmp_reg2, rand % 4096, tmp_reg3; \
1141 cas [tmp_reg1], tmp_reg3, tmp_reg3;\
1142 cas [tmp_reg2], tmp_reg4, tmp_reg4;
1143
1144#define IDC_FLIP(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1145 ta 0xb5; \
1146 ta T_CHANGE_NONHPRIV;
1147
1148! this macro produce ldda/stda to
1149! ASI_BLOCK_AS_IF_USER_PRIMARY 0x16
1150! ASI_BLOCK_AS_IF_USER_SECONDARY 0x17
1151! ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x1e
1152! ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1f
1153!! hardcode for now since illegal asi not working in RS
1154#define BLD_16(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1155 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1156 ta T_CHANGE_PRIV;\
1157 ta T_CHANGE_HPRIV;\
1158 ldda [tmp_reg3]0x16, tmp_reg0;
1159#define BLD_17(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1160 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1161 ta T_CHANGE_PRIV;\
1162 ta T_CHANGE_HPRIV;\
1163 ldda [tmp_reg3]0x17, tmp_reg0;
1164#define BLD_1e(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1165 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1166 ta T_CHANGE_PRIV;\
1167 ta T_CHANGE_HPRIV;\
1168 ldda [tmp_reg3]0x1e, tmp_reg0;
1169#define BLD_1f(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1170 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1171 ta T_CHANGE_PRIV;\
1172 ta T_CHANGE_HPRIV;\
1173 ldda [tmp_reg3]0x1f, tmp_reg0;
1174
1175#define BST_16(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1176 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1177 ta T_CHANGE_PRIV;\
1178 ta T_CHANGE_HPRIV;\
1179 stda tmp_reg0, [tmp_reg3]0x16;
1180#define BST_17(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1181 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1182 ta T_CHANGE_PRIV;\
1183 ta T_CHANGE_HPRIV;\
1184 stda tmp_reg0, [tmp_reg3]0x17;
1185#define BST_1e(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1186 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1187 ta T_CHANGE_PRIV;\
1188 ta T_CHANGE_HPRIV;\
1189 stda tmp_reg0, [tmp_reg3]0x1e;
1190#define BST_1f(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1191 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1192 ta T_CHANGE_PRIV;\
1193 ta T_CHANGE_HPRIV;\
1194 stda tmp_reg0, [tmp_reg3]0x1f;
1195
1196#define BLD_INIT_2(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1197 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1198 ldda [tmp_reg3] (0x27 | (rand & 0xf)), tmp_reg0;
1199#define BST_INIT_2(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1200 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1201 stda tmp_reg0, [tmp_reg3] (0x27 | (rand & 0xf));
1202#define BLD_INIT_E(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1203 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1204 ldda [tmp_reg3] (0xe2 | (rand & 0xb)), tmp_reg0;
1205#define BST_INIT_E(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1206 add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \
1207 stda tmp_reg0, [tmp_reg3] (0xe2 | (rand & 0xb));
1208#define PREFETCHA(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \
1209 add VA_reg, (VA_offset & 0x00ff), tmp_reg3; \
1210 prefetch [%i1], (rand & 0x1f); \
1211 prefetch [%i1 + ((rand >> 5) & 0x1f)], ((rand >> 5) & 0x1f); \
1212 prefetcha [%i1]((rand >> 5) & 0x1f), (0x0 | ((rand >> 5) & 0x1f));
1213#define STBYTE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1214 add VA_reg, (VA_offset & 0xff00), tmp_reg1; \
1215 set rand, tmp_reg2; \
1216 stb tmp_reg2, [tmp_reg1+(rand & 0x5f)];
1217#define LDBYTE(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1218 add VA_reg, (VA_offset & 0xff00), tmp_reg1; \
1219 ldub [tmp_reg1+(rand & 0x5f)], tmp_reg2;
1220#define STBYTE1(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1221 add VA_reg, (VA_offset & 0xff00), tmp_reg1;\
1222 set 5200, tmp_reg2; \
1223 add tmp_reg2, tmp_reg1, tmp_reg1; \
1224 set rand, tmp_reg2; \
1225 stb tmp_reg2, [tmp_reg1+(rand & 0x5f)];
1226#define STINT(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \
1227 set rand, tmp_reg1; \
1228 stha tmp_reg1,[%g0+%g0](0x73); \
1229 stda tmp_reg1, [%g0+%g0](0x73);
1230define(EN_INTERRUPTS,`
1231nop
1232')
1233
1234define(DIS_INTERRUPTS,`
1235nop
1236')
1237
1238define(CHECK_DISPATCH_STATUS,`
1239nop
1240')
1241
1242define(CHECK_RECEIVE_STATUS,`
1243nop
1244')
1245
1246define(WRITE_INTR_DATA_REGS,`
1247nop
1248')
1249
1250define(INTR_SET_DISPATCH_VECTOR,`
1251add %g0, $3, $4
1252sllx $4, 8, $5 ! DEST ID
1253add %g0, $2, $4 ! VECTOR NUMBER
1254or $5, $4, $5
1255mov %i0, $4
1256mov $5, %i0
1257ta 0x30
1258mov $4, %i0
1259')
1260
1261define(DSPCH_INTERRUPT,`
1262nop
1263')
1264
1265#define REGION0_ALIAS3_O 0x0
1266#define REGION1_ALIAS3_O 0x20000
1267#define REGION2_ALIAS3_O 0x40000
1268#define REGION3_ALIAS3_O 0x60000
1269#define REGION4_ALIAS3_O 0x80000
1270#define REGION5_ALIAS3_O 0xa0000
1271#define REGION6_ALIAS3_O 0xc0000
1272#define REGION7_ALIAS3_O 0xe0000
1273#define REPLACEMENT0_ALIAS3_O 0x100000
1274#define REGION0_ALIAS2_O 0x200000
1275#define REGION1_ALIAS2_O 0x220000
1276#define REGION2_ALIAS2_O 0x240000
1277#define REGION3_ALIAS2_O 0x260000
1278#define REGION4_ALIAS2_O 0x280000
1279#define REGION5_ALIAS2_O 0x2a0000
1280#define REGION6_ALIAS2_O 0x2c0000
1281#define REGION7_ALIAS2_O 0x2e0000
1282#define REPLACEMENT0_ALIAS2_O 0x300000
1283#define REGION0_ALIAS1_O 0x400000
1284#define REGION1_ALIAS1_O 0x420000
1285#define REGION2_ALIAS1_O 0x440000
1286#define REGION3_ALIAS1_O 0x460000
1287#define REGION4_ALIAS1_O 0x480000
1288#define REGION5_ALIAS1_O 0x4a0000
1289#define REGION6_ALIAS1_O 0x4c0000
1290#define REGION7_ALIAS1_O 0x4e0000
1291#define REPLACEMENT0_ALIAS1_O 0x500000
1292#define REGION0_ALIAS0_O 0x600000
1293#define REGION1_ALIAS0_O 0x620000
1294#define REGION2_ALIAS0_O 0x640000
1295#define REGION3_ALIAS0_O 0x660000
1296#define REGION4_ALIAS0_O 0x680000
1297#define REGION5_ALIAS0_O 0x6a0000
1298#define REGION6_ALIAS0_O 0x6c0000
1299#define REGION7_ALIAS0_O 0x6e0000
1300#define REPLACEMENT0_ALIAS0_O 0x700000
1301
1302
1303#define USER_PAGE_CUSTOM_MAP
1304SECTION .MAIN TEXT_VA=0x1000000
1305attr_text {
1306 Name = .MAIN,
1307 VA=0x1000000,
1308 RA=0x130000000,
1309 PA=ra2pa(0x130000000,0),
1310part_0_ctx_nonzero_tsb_config_1,
1311 TTE_EP=1,
1312 TTE_G=1,
1313 TTE_Context=PCONTEXT,
1314 TTE_V=1,
1315 TTE_Size=0,
1316 TTE_SIZE_PTR=0,
1317 TTE_NFO=0,
1318 TTE_IE=0,
1319 TTE_Soft2=0,
1320 TTE_Diag=0,
1321 TTE_Soft=0,
1322 TTE_L=0,
1323 TTE_CP=1,
1324 TTE_CV=1,
1325 TTE_E=0,
1326 TTE_P=0,
1327 TTE_W=0
1328 }
1329
1330attr_text {
1331 Name = .MAIN,
1332 VA=0x1000000,
1333 RA=0x130000000,
1334 PA=ra2pa(0x130000000,0),
1335part_0_ctx_nonzero_tsb_config_0,
1336 TTE_EP=1,
1337 TTE_G=1,
1338 TTE_Context=PCONTEXT,
1339 TTE_V=1,
1340 TTE_Size=0,
1341 TTE_SIZE_PTR=0,
1342 TTE_NFO=0,
1343 TTE_IE=0,
1344 TTE_Soft2=0,
1345 TTE_Diag=0,
1346 TTE_Soft=0,
1347 TTE_L=0,
1348 TTE_CP=1,
1349 TTE_CV=1,
1350 TTE_E=0,
1351 TTE_P=0,
1352 TTE_W=1,
1353 tsbonly
1354 }
1355
1356SECTION tsotool_unshared_data DATA_VA=0x21400000
1357attr_data {
1358 Name = tsotool_unshared_data,
1359 VA=0x21400000,
1360 RA=0x21400000,
1361 PA=ra2pa(0x21400000,0),
1362 part_0_ctx_nonzero_tsb_config_0,
1363 TTE_G=1,
1364 TTE_Context=PCONTEXT,
1365 TTE_V=1,
1366 TTE_Size=0,
1367 TTE_SIZE_PTR=0,
1368 TTE_NFO=0,
1369 TTE_IE=0,
1370 TTE_Soft2=0,
1371 TTE_Diag=0,
1372 TTE_Soft=0,
1373 TTE_L=0,
1374 TTE_CP=1,
1375 TTE_CV=1,
1376 TTE_E=0,
1377 TTE_P=0,
1378 TTE_W=1
1379 }
1380
1381SECTION region0_alias3_4 DATA_VA=0x6000000
1382attr_data {
1383 Name = region0_alias3_4,
1384 VA=0x6000000,
1385 RA=0x43000000,
1386 PA=ra2pa(0x43000000,0),
1387 part_0_ctx_nonzero_tsb_config_0,
1388 TTE_G=0,
1389 TTE_Context=PCONTEXT,
1390 TTE_V=1,
1391 TTE_Size=0,
1392 TTE_SIZE_PTR=0,
1393 TTE_NFO=0,
1394 TTE_IE=0,
1395 TTE_Soft2=0,
1396 TTE_Diag=0,
1397 TTE_Soft=0,
1398 TTE_L=0,
1399 TTE_CP=1,
1400 TTE_CV=0,
1401 TTE_E=0,
1402 TTE_P=0,
1403 TTE_W=1,
1404 tsbonly
1405 }
1406
1407.data
1408.skip 1024
1409
1410SECTION region1_alias3_4 DATA_VA=0x6020000
1411attr_data {
1412 Name = region1_alias3_4,
1413 VA=0x6020000,
1414 RA=0x43800000,
1415 PA=ra2pa(0x43800000,0),
1416 part_0_ctx_nonzero_tsb_config_0,
1417 TTE_G=0,
1418 TTE_Context=PCONTEXT,
1419 TTE_V=1,
1420 TTE_Size=0,
1421 TTE_SIZE_PTR=0,
1422 TTE_NFO=0,
1423 TTE_IE=0,
1424 TTE_Soft2=0,
1425 TTE_Diag=0,
1426 TTE_Soft=0,
1427 TTE_L=0,
1428 TTE_CP=1,
1429 TTE_CV=1,
1430 TTE_E=0,
1431 TTE_P=0,
1432 TTE_W=1,
1433 tsbonly
1434 }
1435
1436.data
1437.skip 1024
1438
1439SECTION region2_alias3_4 DATA_VA=0x6040000
1440attr_data {
1441 Name = region2_alias3_4,
1442 VA=0x6040000,
1443 RA=0x44000000,
1444 PA=ra2pa(0x44000000,0),
1445 part_0_ctx_nonzero_tsb_config_0,
1446 TTE_G=0,
1447 TTE_Context=PCONTEXT,
1448 TTE_V=1,
1449 TTE_Size=0,
1450 TTE_SIZE_PTR=0,
1451 TTE_NFO=0,
1452 TTE_IE=0,
1453 TTE_Soft2=0,
1454 TTE_Diag=0,
1455 TTE_Soft=0,
1456 TTE_L=0,
1457 TTE_CP=1,
1458 TTE_CV=1,
1459 TTE_E=0,
1460 TTE_P=0,
1461 TTE_W=1,
1462 tsbonly
1463 }
1464
1465.data
1466.skip 1024
1467
1468SECTION region3_alias3_4 DATA_VA=0x6060000
1469attr_data {
1470 Name = region3_alias3_4,
1471 VA=0x6060000,
1472 RA=0x44800000,
1473 PA=ra2pa(0x44800000,0),
1474 part_0_ctx_nonzero_tsb_config_0,
1475 TTE_G=0,
1476 TTE_Context=PCONTEXT,
1477 TTE_V=1,
1478 TTE_Size=0,
1479 TTE_SIZE_PTR=0,
1480 TTE_NFO=0,
1481 TTE_IE=0,
1482 TTE_Soft2=0,
1483 TTE_Diag=0,
1484 TTE_Soft=0,
1485 TTE_L=0,
1486 TTE_CP=1,
1487 TTE_CV=1,
1488 TTE_E=0,
1489 TTE_P=0,
1490 TTE_W=1,
1491 tsbonly
1492 }
1493
1494.data
1495.skip 1024
1496
1497SECTION region4_alias3_4 DATA_VA=0x6080000
1498attr_data {
1499 Name = region4_alias3_4,
1500 VA=0x6080000,
1501 RA=0x45000000,
1502 PA=ra2pa(0x45000000,0),
1503 part_0_ctx_nonzero_tsb_config_0,
1504 TTE_G=0,
1505 TTE_Context=PCONTEXT,
1506 TTE_V=1,
1507 TTE_Size=0,
1508 TTE_SIZE_PTR=0,
1509 TTE_NFO=0,
1510 TTE_IE=0,
1511 TTE_Soft2=0,
1512 TTE_Diag=0,
1513 TTE_Soft=0,
1514 TTE_L=0,
1515 TTE_CP=1,
1516 TTE_CV=1,
1517 TTE_E=0,
1518 TTE_P=0,
1519 TTE_W=1,
1520 tsbonly
1521 }
1522
1523.data
1524.skip 1024
1525
1526SECTION region5_alias3_4 DATA_VA=0x60a0000
1527attr_data {
1528 Name = region5_alias3_4,
1529 VA=0x60a0000,
1530 RA=0x45800000,
1531 PA=ra2pa(0x45800000,0),
1532 part_0_ctx_nonzero_tsb_config_0,
1533 TTE_G=0,
1534 TTE_Context=PCONTEXT,
1535 TTE_V=1,
1536 TTE_Size=0,
1537 TTE_SIZE_PTR=0,
1538 TTE_NFO=0,
1539 TTE_IE=0,
1540 TTE_Soft2=0,
1541 TTE_Diag=0,
1542 TTE_Soft=0,
1543 TTE_L=0,
1544 TTE_CP=1,
1545 TTE_CV=1,
1546 TTE_E=0,
1547 TTE_P=0,
1548 TTE_W=1,
1549 tsbonly
1550 }
1551
1552.data
1553.skip 1024
1554
1555SECTION region6_alias3_4 DATA_VA=0x60c0000
1556attr_data {
1557 Name = region6_alias3_4,
1558 VA=0x60c0000,
1559 RA=0x46000000,
1560 PA=ra2pa(0x46000000,0),
1561 part_0_ctx_nonzero_tsb_config_0,
1562 TTE_G=0,
1563 TTE_Context=PCONTEXT,
1564 TTE_V=1,
1565 TTE_Size=0,
1566 TTE_SIZE_PTR=0,
1567 TTE_NFO=0,
1568 TTE_IE=0,
1569 TTE_Soft2=0,
1570 TTE_Diag=0,
1571 TTE_Soft=0,
1572 TTE_L=0,
1573 TTE_CP=1,
1574 TTE_CV=1,
1575 TTE_E=0,
1576 TTE_P=0,
1577 TTE_W=1,
1578 tsbonly
1579 }
1580
1581.data
1582.skip 1024
1583
1584SECTION region7_alias3_4 DATA_VA=0x60e0000
1585attr_data {
1586 Name = region7_alias3_4,
1587 VA=0x60e0000,
1588 RA=0x46800000,
1589 PA=ra2pa(0x46800000,0),
1590 part_0_ctx_nonzero_tsb_config_0,
1591 TTE_G=0,
1592 TTE_Context=PCONTEXT,
1593 TTE_V=1,
1594 TTE_Size=0,
1595 TTE_SIZE_PTR=0,
1596 TTE_NFO=0,
1597 TTE_IE=0,
1598 TTE_Soft2=0,
1599 TTE_Diag=0,
1600 TTE_Soft=0,
1601 TTE_L=0,
1602 TTE_CP=1,
1603 TTE_CV=1,
1604 TTE_E=0,
1605 TTE_P=0,
1606 TTE_W=1,
1607 tsbonly
1608 }
1609
1610.data
1611.skip 1024
1612
1613SECTION replacement0_alias3_4 DATA_VA=0x6100000
1614attr_data {
1615 Name = replacement0_alias3_4,
1616 VA=0x6100000,
1617 RA=0x47000000,
1618 PA=ra2pa(0x47000000,0),
1619 part_0_ctx_nonzero_tsb_config_0,
1620 TTE_G=0,
1621 TTE_Context=PCONTEXT,
1622 TTE_V=1,
1623 TTE_Size=0,
1624 TTE_SIZE_PTR=0,
1625 TTE_NFO=0,
1626 TTE_IE=0,
1627 TTE_Soft2=0,
1628 TTE_Diag=0,
1629 TTE_Soft=0,
1630 TTE_L=0,
1631 TTE_CP=1,
1632 TTE_CV=1,
1633 TTE_E=0,
1634 TTE_P=0,
1635 TTE_W=1,
1636 tsbonly
1637 }
1638
1639.data
1640.skip 1024
1641
1642SECTION replacement1_alias3_4 DATA_VA=0x6120000
1643attr_data {
1644 Name = replacement1_alias3_4,
1645 VA=0x6120000,
1646 RA=0x47800000,
1647 PA=ra2pa(0x47800000,0),
1648 part_0_ctx_nonzero_tsb_config_0,
1649 TTE_G=0,
1650 TTE_Context=PCONTEXT,
1651 TTE_V=1,
1652 TTE_Size=0,
1653 TTE_SIZE_PTR=0,
1654 TTE_NFO=0,
1655 TTE_IE=0,
1656 TTE_Soft2=0,
1657 TTE_Diag=0,
1658 TTE_Soft=0,
1659 TTE_L=0,
1660 TTE_CP=1,
1661 TTE_CV=1,
1662 TTE_E=0,
1663 TTE_P=0,
1664 TTE_W=1,
1665 tsbonly
1666 }
1667
1668.data
1669.skip 1024
1670
1671SECTION replacement2_alias3_4 DATA_VA=0x6140000
1672attr_data {
1673 Name = replacement2_alias3_4,
1674 VA=0x6140000,
1675 RA=0x48000000,
1676 PA=ra2pa(0x48000000,0),
1677 part_0_ctx_nonzero_tsb_config_0,
1678 TTE_G=0,
1679 TTE_Context=PCONTEXT,
1680 TTE_V=1,
1681 TTE_Size=0,
1682 TTE_SIZE_PTR=0,
1683 TTE_NFO=0,
1684 TTE_IE=0,
1685 TTE_Soft2=0,
1686 TTE_Diag=0,
1687 TTE_Soft=0,
1688 TTE_L=0,
1689 TTE_CP=1,
1690 TTE_CV=1,
1691 TTE_E=0,
1692 TTE_P=0,
1693 TTE_W=1,
1694 tsbonly
1695 }
1696
1697.data
1698.skip 1024
1699
1700SECTION replacement3_alias3_4 DATA_VA=0x6160000
1701attr_data {
1702 Name = replacement3_alias3_4,
1703 VA=0x6160000,
1704 RA=0x48800000,
1705 PA=ra2pa(0x48800000,0),
1706 part_0_ctx_nonzero_tsb_config_0,
1707 TTE_G=0,
1708 TTE_Context=PCONTEXT,
1709 TTE_V=1,
1710 TTE_Size=0,
1711 TTE_SIZE_PTR=0,
1712 TTE_NFO=0,
1713 TTE_IE=0,
1714 TTE_Soft2=0,
1715 TTE_Diag=0,
1716 TTE_Soft=0,
1717 TTE_L=0,
1718 TTE_CP=1,
1719 TTE_CV=1,
1720 TTE_E=0,
1721 TTE_P=0,
1722 TTE_W=1,
1723 tsbonly
1724 }
1725
1726.data
1727.skip 1024
1728
1729SECTION replacement4_alias3_4 DATA_VA=0x6180000
1730attr_data {
1731 Name = replacement4_alias3_4,
1732 VA=0x6180000,
1733 RA=0x49000000,
1734 PA=ra2pa(0x49000000,0),
1735 part_0_ctx_nonzero_tsb_config_0,
1736 TTE_G=0,
1737 TTE_Context=PCONTEXT,
1738 TTE_V=1,
1739 TTE_Size=0,
1740 TTE_SIZE_PTR=0,
1741 TTE_NFO=0,
1742 TTE_IE=0,
1743 TTE_Soft2=0,
1744 TTE_Diag=0,
1745 TTE_Soft=0,
1746 TTE_L=0,
1747 TTE_CP=1,
1748 TTE_CV=1,
1749 TTE_E=0,
1750 TTE_P=0,
1751 TTE_W=1,
1752 tsbonly
1753 }
1754
1755.data
1756.skip 1024
1757
1758SECTION replacement5_alias3_4 DATA_VA=0x61a0000
1759attr_data {
1760 Name = replacement5_alias3_4,
1761 VA=0x61a0000,
1762 RA=0x49800000,
1763 PA=ra2pa(0x49800000,0),
1764 part_0_ctx_nonzero_tsb_config_0,
1765 TTE_G=0,
1766 TTE_Context=PCONTEXT,
1767 TTE_V=1,
1768 TTE_Size=0,
1769 TTE_SIZE_PTR=0,
1770 TTE_NFO=0,
1771 TTE_IE=0,
1772 TTE_Soft2=0,
1773 TTE_Diag=0,
1774 TTE_Soft=0,
1775 TTE_L=0,
1776 TTE_CP=1,
1777 TTE_CV=1,
1778 TTE_E=0,
1779 TTE_P=0,
1780 TTE_W=1,
1781 tsbonly
1782 }
1783
1784.data
1785.skip 1024
1786
1787SECTION replacement6_alias3_4 DATA_VA=0x61c0000
1788attr_data {
1789 Name = replacement6_alias3_4,
1790 VA=0x61c0000,
1791 RA=0x4a000000,
1792 PA=ra2pa(0x4a000000,0),
1793 part_0_ctx_nonzero_tsb_config_0,
1794 TTE_G=0,
1795 TTE_Context=PCONTEXT,
1796 TTE_V=1,
1797 TTE_Size=0,
1798 TTE_SIZE_PTR=0,
1799 TTE_NFO=0,
1800 TTE_IE=0,
1801 TTE_Soft2=0,
1802 TTE_Diag=0,
1803 TTE_Soft=0,
1804 TTE_L=0,
1805 TTE_CP=1,
1806 TTE_CV=1,
1807 TTE_E=0,
1808 TTE_P=0,
1809 TTE_W=1,
1810 tsbonly
1811 }
1812
1813.data
1814.skip 1024
1815
1816SECTION replacement7_alias3_4 DATA_VA=0x61e0000
1817attr_data {
1818 Name = replacement7_alias3_4,
1819 VA=0x61e0000,
1820 RA=0x4a800000,
1821 PA=ra2pa(0x4a800000,0),
1822 part_0_ctx_nonzero_tsb_config_0,
1823 TTE_G=0,
1824 TTE_Context=PCONTEXT,
1825 TTE_V=1,
1826 TTE_Size=0,
1827 TTE_SIZE_PTR=0,
1828 TTE_NFO=0,
1829 TTE_IE=0,
1830 TTE_Soft2=0,
1831 TTE_Diag=0,
1832 TTE_Soft=0,
1833 TTE_L=0,
1834 TTE_CP=1,
1835 TTE_CV=1,
1836 TTE_E=0,
1837 TTE_P=0,
1838 TTE_W=1,
1839 tsbonly
1840 }
1841
1842.data
1843.skip 1024
1844
1845SECTION region0_alias2_4 DATA_VA=0x6200000
1846attr_data {
1847 Name = region0_alias2_4,
1848 VA=0x6200000,
1849 RA=0x43000000,
1850 PA=ra2pa(0x43000000,0),
1851 part_0_ctx_nonzero_tsb_config_0,
1852 TTE_G=0,
1853 TTE_Context=PCONTEXT,
1854 TTE_V=1,
1855 TTE_Size=0,
1856 TTE_SIZE_PTR=0,
1857 TTE_NFO=0,
1858 TTE_IE=0,
1859 TTE_Soft2=0,
1860 TTE_Diag=0,
1861 TTE_Soft=0,
1862 TTE_L=0,
1863 TTE_CP=1,
1864 TTE_CV=0,
1865 TTE_E=0,
1866 TTE_P=0,
1867 TTE_W=1,
1868 tsbonly
1869 }
1870
1871.data
1872.skip 1024
1873
1874SECTION region1_alias2_4 DATA_VA=0x6220000
1875attr_data {
1876 Name = region1_alias2_4,
1877 VA=0x6220000,
1878 RA=0x43800000,
1879 PA=ra2pa(0x43800000,0),
1880 part_0_ctx_nonzero_tsb_config_0,
1881 TTE_G=0,
1882 TTE_Context=PCONTEXT,
1883 TTE_V=1,
1884 TTE_Size=0,
1885 TTE_SIZE_PTR=0,
1886 TTE_NFO=0,
1887 TTE_IE=0,
1888 TTE_Soft2=0,
1889 TTE_Diag=0,
1890 TTE_Soft=0,
1891 TTE_L=0,
1892 TTE_CP=1,
1893 TTE_CV=1,
1894 TTE_E=0,
1895 TTE_P=0,
1896 TTE_W=1,
1897 tsbonly
1898 }
1899
1900.data
1901.skip 1024
1902
1903SECTION region2_alias2_4 DATA_VA=0x6240000
1904attr_data {
1905 Name = region2_alias2_4,
1906 VA=0x6240000,
1907 RA=0x44000000,
1908 PA=ra2pa(0x44000000,0),
1909 part_0_ctx_nonzero_tsb_config_0,
1910 TTE_G=0,
1911 TTE_Context=PCONTEXT,
1912 TTE_V=1,
1913 TTE_Size=0,
1914 TTE_SIZE_PTR=0,
1915 TTE_NFO=0,
1916 TTE_IE=0,
1917 TTE_Soft2=0,
1918 TTE_Diag=0,
1919 TTE_Soft=0,
1920 TTE_L=0,
1921 TTE_CP=1,
1922 TTE_CV=1,
1923 TTE_E=0,
1924 TTE_P=0,
1925 TTE_W=1,
1926 tsbonly
1927 }
1928
1929.data
1930.skip 1024
1931
1932SECTION region3_alias2_4 DATA_VA=0x6260000
1933attr_data {
1934 Name = region3_alias2_4,
1935 VA=0x6260000,
1936 RA=0x44800000,
1937 PA=ra2pa(0x44800000,0),
1938 part_0_ctx_nonzero_tsb_config_0,
1939 TTE_G=0,
1940 TTE_Context=PCONTEXT,
1941 TTE_V=1,
1942 TTE_Size=0,
1943 TTE_SIZE_PTR=0,
1944 TTE_NFO=0,
1945 TTE_IE=0,
1946 TTE_Soft2=0,
1947 TTE_Diag=0,
1948 TTE_Soft=0,
1949 TTE_L=0,
1950 TTE_CP=1,
1951 TTE_CV=1,
1952 TTE_E=0,
1953 TTE_P=0,
1954 TTE_W=1,
1955 tsbonly
1956 }
1957
1958.data
1959.skip 1024
1960
1961SECTION region4_alias2_4 DATA_VA=0x6280000
1962attr_data {
1963 Name = region4_alias2_4,
1964 VA=0x6280000,
1965 RA=0x45000000,
1966 PA=ra2pa(0x45000000,0),
1967 part_0_ctx_nonzero_tsb_config_0,
1968 TTE_G=0,
1969 TTE_Context=PCONTEXT,
1970 TTE_V=1,
1971 TTE_Size=0,
1972 TTE_SIZE_PTR=0,
1973 TTE_NFO=0,
1974 TTE_IE=0,
1975 TTE_Soft2=0,
1976 TTE_Diag=0,
1977 TTE_Soft=0,
1978 TTE_L=0,
1979 TTE_CP=1,
1980 TTE_CV=1,
1981 TTE_E=0,
1982 TTE_P=0,
1983 TTE_W=1,
1984 tsbonly
1985 }
1986
1987.data
1988.skip 1024
1989
1990SECTION region5_alias2_4 DATA_VA=0x62a0000
1991attr_data {
1992 Name = region5_alias2_4,
1993 VA=0x62a0000,
1994 RA=0x45800000,
1995 PA=ra2pa(0x45800000,0),
1996 part_0_ctx_nonzero_tsb_config_0,
1997 TTE_G=0,
1998 TTE_Context=PCONTEXT,
1999 TTE_V=1,
2000 TTE_Size=0,
2001 TTE_SIZE_PTR=0,
2002 TTE_NFO=0,
2003 TTE_IE=0,
2004 TTE_Soft2=0,
2005 TTE_Diag=0,
2006 TTE_Soft=0,
2007 TTE_L=0,
2008 TTE_CP=1,
2009 TTE_CV=1,
2010 TTE_E=0,
2011 TTE_P=0,
2012 TTE_W=1,
2013 tsbonly
2014 }
2015
2016.data
2017.skip 1024
2018
2019SECTION region6_alias2_4 DATA_VA=0x62c0000
2020attr_data {
2021 Name = region6_alias2_4,
2022 VA=0x62c0000,
2023 RA=0x46000000,
2024 PA=ra2pa(0x46000000,0),
2025 part_0_ctx_nonzero_tsb_config_0,
2026 TTE_G=0,
2027 TTE_Context=PCONTEXT,
2028 TTE_V=1,
2029 TTE_Size=0,
2030 TTE_SIZE_PTR=0,
2031 TTE_NFO=0,
2032 TTE_IE=0,
2033 TTE_Soft2=0,
2034 TTE_Diag=0,
2035 TTE_Soft=0,
2036 TTE_L=0,
2037 TTE_CP=1,
2038 TTE_CV=1,
2039 TTE_E=0,
2040 TTE_P=0,
2041 TTE_W=1,
2042 tsbonly
2043 }
2044
2045.data
2046.skip 1024
2047
2048SECTION region7_alias2_4 DATA_VA=0x62e0000
2049attr_data {
2050 Name = region7_alias2_4,
2051 VA=0x62e0000,
2052 RA=0x46800000,
2053 PA=ra2pa(0x46800000,0),
2054 part_0_ctx_nonzero_tsb_config_0,
2055 TTE_G=0,
2056 TTE_Context=PCONTEXT,
2057 TTE_V=1,
2058 TTE_Size=0,
2059 TTE_SIZE_PTR=0,
2060 TTE_NFO=0,
2061 TTE_IE=0,
2062 TTE_Soft2=0,
2063 TTE_Diag=0,
2064 TTE_Soft=0,
2065 TTE_L=0,
2066 TTE_CP=1,
2067 TTE_CV=1,
2068 TTE_E=0,
2069 TTE_P=0,
2070 TTE_W=1,
2071 tsbonly
2072 }
2073
2074.data
2075.skip 1024
2076
2077SECTION replacement0_alias2_4 DATA_VA=0x6300000
2078attr_data {
2079 Name = replacement0_alias2_4,
2080 VA=0x6300000,
2081 RA=0x47000000,
2082 PA=ra2pa(0x47000000,0),
2083 part_0_ctx_nonzero_tsb_config_0,
2084 TTE_G=0,
2085 TTE_Context=PCONTEXT,
2086 TTE_V=1,
2087 TTE_Size=0,
2088 TTE_SIZE_PTR=0,
2089 TTE_NFO=0,
2090 TTE_IE=0,
2091 TTE_Soft2=0,
2092 TTE_Diag=0,
2093 TTE_Soft=0,
2094 TTE_L=0,
2095 TTE_CP=1,
2096 TTE_CV=1,
2097 TTE_E=0,
2098 TTE_P=0,
2099 TTE_W=1,
2100 tsbonly
2101 }
2102
2103.data
2104.skip 1024
2105
2106SECTION replacement1_alias2_4 DATA_VA=0x6320000
2107attr_data {
2108 Name = replacement1_alias2_4,
2109 VA=0x6320000,
2110 RA=0x47800000,
2111 PA=ra2pa(0x47800000,0),
2112 part_0_ctx_nonzero_tsb_config_0,
2113 TTE_G=0,
2114 TTE_Context=PCONTEXT,
2115 TTE_V=1,
2116 TTE_Size=0,
2117 TTE_SIZE_PTR=0,
2118 TTE_NFO=0,
2119 TTE_IE=0,
2120 TTE_Soft2=0,
2121 TTE_Diag=0,
2122 TTE_Soft=0,
2123 TTE_L=0,
2124 TTE_CP=1,
2125 TTE_CV=1,
2126 TTE_E=0,
2127 TTE_P=0,
2128 TTE_W=1,
2129 tsbonly
2130 }
2131
2132.data
2133.skip 1024
2134
2135SECTION replacement2_alias2_4 DATA_VA=0x6340000
2136attr_data {
2137 Name = replacement2_alias2_4,
2138 VA=0x6340000,
2139 RA=0x48000000,
2140 PA=ra2pa(0x48000000,0),
2141 part_0_ctx_nonzero_tsb_config_0,
2142 TTE_G=0,
2143 TTE_Context=PCONTEXT,
2144 TTE_V=1,
2145 TTE_Size=0,
2146 TTE_SIZE_PTR=0,
2147 TTE_NFO=0,
2148 TTE_IE=0,
2149 TTE_Soft2=0,
2150 TTE_Diag=0,
2151 TTE_Soft=0,
2152 TTE_L=0,
2153 TTE_CP=1,
2154 TTE_CV=1,
2155 TTE_E=0,
2156 TTE_P=0,
2157 TTE_W=1,
2158 tsbonly
2159 }
2160
2161.data
2162.skip 1024
2163
2164SECTION replacement3_alias2_4 DATA_VA=0x6360000
2165attr_data {
2166 Name = replacement3_alias2_4,
2167 VA=0x6360000,
2168 RA=0x48800000,
2169 PA=ra2pa(0x48800000,0),
2170 part_0_ctx_nonzero_tsb_config_0,
2171 TTE_G=0,
2172 TTE_Context=PCONTEXT,
2173 TTE_V=1,
2174 TTE_Size=0,
2175 TTE_SIZE_PTR=0,
2176 TTE_NFO=0,
2177 TTE_IE=0,
2178 TTE_Soft2=0,
2179 TTE_Diag=0,
2180 TTE_Soft=0,
2181 TTE_L=0,
2182 TTE_CP=1,
2183 TTE_CV=1,
2184 TTE_E=0,
2185 TTE_P=0,
2186 TTE_W=1,
2187 tsbonly
2188 }
2189
2190.data
2191.skip 1024
2192
2193SECTION replacement4_alias2_4 DATA_VA=0x6380000
2194attr_data {
2195 Name = replacement4_alias2_4,
2196 VA=0x6380000,
2197 RA=0x49000000,
2198 PA=ra2pa(0x49000000,0),
2199 part_0_ctx_nonzero_tsb_config_0,
2200 TTE_G=0,
2201 TTE_Context=PCONTEXT,
2202 TTE_V=1,
2203 TTE_Size=0,
2204 TTE_SIZE_PTR=0,
2205 TTE_NFO=0,
2206 TTE_IE=0,
2207 TTE_Soft2=0,
2208 TTE_Diag=0,
2209 TTE_Soft=0,
2210 TTE_L=0,
2211 TTE_CP=1,
2212 TTE_CV=1,
2213 TTE_E=0,
2214 TTE_P=0,
2215 TTE_W=1,
2216 tsbonly
2217 }
2218
2219.data
2220.skip 1024
2221
2222SECTION replacement5_alias2_4 DATA_VA=0x63a0000
2223attr_data {
2224 Name = replacement5_alias2_4,
2225 VA=0x63a0000,
2226 RA=0x49800000,
2227 PA=ra2pa(0x49800000,0),
2228 part_0_ctx_nonzero_tsb_config_0,
2229 TTE_G=0,
2230 TTE_Context=PCONTEXT,
2231 TTE_V=1,
2232 TTE_Size=0,
2233 TTE_SIZE_PTR=0,
2234 TTE_NFO=0,
2235 TTE_IE=0,
2236 TTE_Soft2=0,
2237 TTE_Diag=0,
2238 TTE_Soft=0,
2239 TTE_L=0,
2240 TTE_CP=1,
2241 TTE_CV=1,
2242 TTE_E=0,
2243 TTE_P=0,
2244 TTE_W=1,
2245 tsbonly
2246 }
2247
2248.data
2249.skip 1024
2250
2251SECTION replacement6_alias2_4 DATA_VA=0x63c0000
2252attr_data {
2253 Name = replacement6_alias2_4,
2254 VA=0x63c0000,
2255 RA=0x4a000000,
2256 PA=ra2pa(0x4a000000,0),
2257 part_0_ctx_nonzero_tsb_config_0,
2258 TTE_G=0,
2259 TTE_Context=PCONTEXT,
2260 TTE_V=1,
2261 TTE_Size=0,
2262 TTE_SIZE_PTR=0,
2263 TTE_NFO=0,
2264 TTE_IE=0,
2265 TTE_Soft2=0,
2266 TTE_Diag=0,
2267 TTE_Soft=0,
2268 TTE_L=0,
2269 TTE_CP=1,
2270 TTE_CV=1,
2271 TTE_E=0,
2272 TTE_P=0,
2273 TTE_W=1,
2274 tsbonly
2275 }
2276
2277.data
2278.skip 1024
2279
2280SECTION replacement7_alias2_4 DATA_VA=0x63e0000
2281attr_data {
2282 Name = replacement7_alias2_4,
2283 VA=0x63e0000,
2284 RA=0x4a800000,
2285 PA=ra2pa(0x4a800000,0),
2286 part_0_ctx_nonzero_tsb_config_0,
2287 TTE_G=0,
2288 TTE_Context=PCONTEXT,
2289 TTE_V=1,
2290 TTE_Size=0,
2291 TTE_SIZE_PTR=0,
2292 TTE_NFO=0,
2293 TTE_IE=0,
2294 TTE_Soft2=0,
2295 TTE_Diag=0,
2296 TTE_Soft=0,
2297 TTE_L=0,
2298 TTE_CP=1,
2299 TTE_CV=1,
2300 TTE_E=0,
2301 TTE_P=0,
2302 TTE_W=1,
2303 tsbonly
2304 }
2305
2306.data
2307.skip 1024
2308
2309SECTION region0_alias1_4 DATA_VA=0x6400000
2310attr_data {
2311 Name = region0_alias1_4,
2312 VA=0x6400000,
2313 RA=0x43000000,
2314 PA=ra2pa(0x43000000,0),
2315 part_0_ctx_nonzero_tsb_config_0,
2316 TTE_G=0,
2317 TTE_Context=PCONTEXT,
2318 TTE_V=1,
2319 TTE_Size=0,
2320 TTE_SIZE_PTR=0,
2321 TTE_NFO=0,
2322 TTE_IE=0,
2323 TTE_Soft2=0,
2324 TTE_Diag=0,
2325 TTE_Soft=0,
2326 TTE_L=0,
2327 TTE_CP=1,
2328 TTE_CV=0,
2329 TTE_E=0,
2330 TTE_P=0,
2331 TTE_W=1,
2332 tsbonly
2333 }
2334
2335.data
2336.skip 1024
2337
2338SECTION region1_alias1_4 DATA_VA=0x6420000
2339attr_data {
2340 Name = region1_alias1_4,
2341 VA=0x6420000,
2342 RA=0x43800000,
2343 PA=ra2pa(0x43800000,0),
2344 part_0_ctx_nonzero_tsb_config_0,
2345 TTE_G=0,
2346 TTE_Context=PCONTEXT,
2347 TTE_V=1,
2348 TTE_Size=0,
2349 TTE_SIZE_PTR=0,
2350 TTE_NFO=0,
2351 TTE_IE=0,
2352 TTE_Soft2=0,
2353 TTE_Diag=0,
2354 TTE_Soft=0,
2355 TTE_L=0,
2356 TTE_CP=1,
2357 TTE_CV=1,
2358 TTE_E=0,
2359 TTE_P=0,
2360 TTE_W=1,
2361 tsbonly
2362 }
2363
2364.data
2365.skip 1024
2366
2367SECTION region2_alias1_4 DATA_VA=0x6440000
2368attr_data {
2369 Name = region2_alias1_4,
2370 VA=0x6440000,
2371 RA=0x44000000,
2372 PA=ra2pa(0x44000000,0),
2373 part_0_ctx_nonzero_tsb_config_0,
2374 TTE_G=0,
2375 TTE_Context=PCONTEXT,
2376 TTE_V=1,
2377 TTE_Size=0,
2378 TTE_SIZE_PTR=0,
2379 TTE_NFO=0,
2380 TTE_IE=0,
2381 TTE_Soft2=0,
2382 TTE_Diag=0,
2383 TTE_Soft=0,
2384 TTE_L=0,
2385 TTE_CP=1,
2386 TTE_CV=1,
2387 TTE_E=0,
2388 TTE_P=0,
2389 TTE_W=1,
2390 tsbonly
2391 }
2392
2393.data
2394.skip 1024
2395
2396SECTION region3_alias1_4 DATA_VA=0x6460000
2397attr_data {
2398 Name = region3_alias1_4,
2399 VA=0x6460000,
2400 RA=0x44800000,
2401 PA=ra2pa(0x44800000,0),
2402 part_0_ctx_nonzero_tsb_config_0,
2403 TTE_G=0,
2404 TTE_Context=PCONTEXT,
2405 TTE_V=1,
2406 TTE_Size=0,
2407 TTE_SIZE_PTR=0,
2408 TTE_NFO=0,
2409 TTE_IE=0,
2410 TTE_Soft2=0,
2411 TTE_Diag=0,
2412 TTE_Soft=0,
2413 TTE_L=0,
2414 TTE_CP=1,
2415 TTE_CV=1,
2416 TTE_E=0,
2417 TTE_P=0,
2418 TTE_W=1,
2419 tsbonly
2420 }
2421
2422.data
2423.skip 1024
2424
2425SECTION region4_alias1_4 DATA_VA=0x6480000
2426attr_data {
2427 Name = region4_alias1_4,
2428 VA=0x6480000,
2429 RA=0x45000000,
2430 PA=ra2pa(0x45000000,0),
2431 part_0_ctx_nonzero_tsb_config_0,
2432 TTE_G=0,
2433 TTE_Context=PCONTEXT,
2434 TTE_V=1,
2435 TTE_Size=0,
2436 TTE_SIZE_PTR=0,
2437 TTE_NFO=0,
2438 TTE_IE=0,
2439 TTE_Soft2=0,
2440 TTE_Diag=0,
2441 TTE_Soft=0,
2442 TTE_L=0,
2443 TTE_CP=1,
2444 TTE_CV=1,
2445 TTE_E=0,
2446 TTE_P=0,
2447 TTE_W=1,
2448 tsbonly
2449 }
2450
2451.data
2452.skip 1024
2453
2454SECTION region5_alias1_4 DATA_VA=0x64a0000
2455attr_data {
2456 Name = region5_alias1_4,
2457 VA=0x64a0000,
2458 RA=0x45800000,
2459 PA=ra2pa(0x45800000,0),
2460 part_0_ctx_nonzero_tsb_config_0,
2461 TTE_G=0,
2462 TTE_Context=PCONTEXT,
2463 TTE_V=1,
2464 TTE_Size=0,
2465 TTE_SIZE_PTR=0,
2466 TTE_NFO=0,
2467 TTE_IE=0,
2468 TTE_Soft2=0,
2469 TTE_Diag=0,
2470 TTE_Soft=0,
2471 TTE_L=0,
2472 TTE_CP=1,
2473 TTE_CV=1,
2474 TTE_E=0,
2475 TTE_P=0,
2476 TTE_W=1,
2477 tsbonly
2478 }
2479
2480.data
2481.skip 1024
2482
2483SECTION region6_alias1_4 DATA_VA=0x64c0000
2484attr_data {
2485 Name = region6_alias1_4,
2486 VA=0x64c0000,
2487 RA=0x46000000,
2488 PA=ra2pa(0x46000000,0),
2489 part_0_ctx_nonzero_tsb_config_0,
2490 TTE_G=0,
2491 TTE_Context=PCONTEXT,
2492 TTE_V=1,
2493 TTE_Size=0,
2494 TTE_SIZE_PTR=0,
2495 TTE_NFO=0,
2496 TTE_IE=0,
2497 TTE_Soft2=0,
2498 TTE_Diag=0,
2499 TTE_Soft=0,
2500 TTE_L=0,
2501 TTE_CP=1,
2502 TTE_CV=1,
2503 TTE_E=0,
2504 TTE_P=0,
2505 TTE_W=1,
2506 tsbonly
2507 }
2508
2509.data
2510.skip 1024
2511
2512SECTION region7_alias1_4 DATA_VA=0x64e0000
2513attr_data {
2514 Name = region7_alias1_4,
2515 VA=0x64e0000,
2516 RA=0x46800000,
2517 PA=ra2pa(0x46800000,0),
2518 part_0_ctx_nonzero_tsb_config_0,
2519 TTE_G=0,
2520 TTE_Context=PCONTEXT,
2521 TTE_V=1,
2522 TTE_Size=0,
2523 TTE_SIZE_PTR=0,
2524 TTE_NFO=0,
2525 TTE_IE=0,
2526 TTE_Soft2=0,
2527 TTE_Diag=0,
2528 TTE_Soft=0,
2529 TTE_L=0,
2530 TTE_CP=1,
2531 TTE_CV=1,
2532 TTE_E=0,
2533 TTE_P=0,
2534 TTE_W=1,
2535 tsbonly
2536 }
2537
2538.data
2539.skip 1024
2540
2541SECTION replacement0_alias1_4 DATA_VA=0x6500000
2542attr_data {
2543 Name = replacement0_alias1_4,
2544 VA=0x6500000,
2545 RA=0x47000000,
2546 PA=ra2pa(0x47000000,0),
2547 part_0_ctx_nonzero_tsb_config_0,
2548 TTE_G=0,
2549 TTE_Context=PCONTEXT,
2550 TTE_V=1,
2551 TTE_Size=0,
2552 TTE_SIZE_PTR=0,
2553 TTE_NFO=0,
2554 TTE_IE=0,
2555 TTE_Soft2=0,
2556 TTE_Diag=0,
2557 TTE_Soft=0,
2558 TTE_L=0,
2559 TTE_CP=1,
2560 TTE_CV=1,
2561 TTE_E=0,
2562 TTE_P=0,
2563 TTE_W=1,
2564 tsbonly
2565 }
2566
2567.data
2568.skip 1024
2569
2570SECTION replacement1_alias1_4 DATA_VA=0x6520000
2571attr_data {
2572 Name = replacement1_alias1_4,
2573 VA=0x6520000,
2574 RA=0x47800000,
2575 PA=ra2pa(0x47800000,0),
2576 part_0_ctx_nonzero_tsb_config_0,
2577 TTE_G=0,
2578 TTE_Context=PCONTEXT,
2579 TTE_V=1,
2580 TTE_Size=0,
2581 TTE_SIZE_PTR=0,
2582 TTE_NFO=0,
2583 TTE_IE=0,
2584 TTE_Soft2=0,
2585 TTE_Diag=0,
2586 TTE_Soft=0,
2587 TTE_L=0,
2588 TTE_CP=1,
2589 TTE_CV=1,
2590 TTE_E=0,
2591 TTE_P=0,
2592 TTE_W=1,
2593 tsbonly
2594 }
2595
2596.data
2597.skip 1024
2598
2599SECTION replacement2_alias1_4 DATA_VA=0x6540000
2600attr_data {
2601 Name = replacement2_alias1_4,
2602 VA=0x6540000,
2603 RA=0x48000000,
2604 PA=ra2pa(0x48000000,0),
2605 part_0_ctx_nonzero_tsb_config_0,
2606 TTE_G=0,
2607 TTE_Context=PCONTEXT,
2608 TTE_V=1,
2609 TTE_Size=0,
2610 TTE_SIZE_PTR=0,
2611 TTE_NFO=0,
2612 TTE_IE=0,
2613 TTE_Soft2=0,
2614 TTE_Diag=0,
2615 TTE_Soft=0,
2616 TTE_L=0,
2617 TTE_CP=1,
2618 TTE_CV=1,
2619 TTE_E=0,
2620 TTE_P=0,
2621 TTE_W=1,
2622 tsbonly
2623 }
2624
2625.data
2626.skip 1024
2627
2628SECTION replacement3_alias1_4 DATA_VA=0x6560000
2629attr_data {
2630 Name = replacement3_alias1_4,
2631 VA=0x6560000,
2632 RA=0x48800000,
2633 PA=ra2pa(0x48800000,0),
2634 part_0_ctx_nonzero_tsb_config_0,
2635 TTE_G=0,
2636 TTE_Context=PCONTEXT,
2637 TTE_V=1,
2638 TTE_Size=0,
2639 TTE_SIZE_PTR=0,
2640 TTE_NFO=0,
2641 TTE_IE=0,
2642 TTE_Soft2=0,
2643 TTE_Diag=0,
2644 TTE_Soft=0,
2645 TTE_L=0,
2646 TTE_CP=1,
2647 TTE_CV=1,
2648 TTE_E=0,
2649 TTE_P=0,
2650 TTE_W=1,
2651 tsbonly
2652 }
2653
2654.data
2655.skip 1024
2656
2657SECTION replacement4_alias1_4 DATA_VA=0x6580000
2658attr_data {
2659 Name = replacement4_alias1_4,
2660 VA=0x6580000,
2661 RA=0x49000000,
2662 PA=ra2pa(0x49000000,0),
2663 part_0_ctx_nonzero_tsb_config_0,
2664 TTE_G=0,
2665 TTE_Context=PCONTEXT,
2666 TTE_V=1,
2667 TTE_Size=0,
2668 TTE_SIZE_PTR=0,
2669 TTE_NFO=0,
2670 TTE_IE=0,
2671 TTE_Soft2=0,
2672 TTE_Diag=0,
2673 TTE_Soft=0,
2674 TTE_L=0,
2675 TTE_CP=1,
2676 TTE_CV=1,
2677 TTE_E=0,
2678 TTE_P=0,
2679 TTE_W=1,
2680 tsbonly
2681 }
2682
2683.data
2684.skip 1024
2685
2686SECTION replacement5_alias1_4 DATA_VA=0x65a0000
2687attr_data {
2688 Name = replacement5_alias1_4,
2689 VA=0x65a0000,
2690 RA=0x49800000,
2691 PA=ra2pa(0x49800000,0),
2692 part_0_ctx_nonzero_tsb_config_0,
2693 TTE_G=0,
2694 TTE_Context=PCONTEXT,
2695 TTE_V=1,
2696 TTE_Size=0,
2697 TTE_SIZE_PTR=0,
2698 TTE_NFO=0,
2699 TTE_IE=0,
2700 TTE_Soft2=0,
2701 TTE_Diag=0,
2702 TTE_Soft=0,
2703 TTE_L=0,
2704 TTE_CP=1,
2705 TTE_CV=1,
2706 TTE_E=0,
2707 TTE_P=0,
2708 TTE_W=1,
2709 tsbonly
2710 }
2711
2712.data
2713.skip 1024
2714
2715SECTION replacement6_alias1_4 DATA_VA=0x65c0000
2716attr_data {
2717 Name = replacement6_alias1_4,
2718 VA=0x65c0000,
2719 RA=0x4a000000,
2720 PA=ra2pa(0x4a000000,0),
2721 part_0_ctx_nonzero_tsb_config_0,
2722 TTE_G=0,
2723 TTE_Context=PCONTEXT,
2724 TTE_V=1,
2725 TTE_Size=0,
2726 TTE_SIZE_PTR=0,
2727 TTE_NFO=0,
2728 TTE_IE=0,
2729 TTE_Soft2=0,
2730 TTE_Diag=0,
2731 TTE_Soft=0,
2732 TTE_L=0,
2733 TTE_CP=1,
2734 TTE_CV=1,
2735 TTE_E=0,
2736 TTE_P=0,
2737 TTE_W=1,
2738 tsbonly
2739 }
2740
2741.data
2742.skip 1024
2743
2744SECTION replacement7_alias1_4 DATA_VA=0x65e0000
2745attr_data {
2746 Name = replacement7_alias1_4,
2747 VA=0x65e0000,
2748 RA=0x4a800000,
2749 PA=ra2pa(0x4a800000,0),
2750 part_0_ctx_nonzero_tsb_config_0,
2751 TTE_G=0,
2752 TTE_Context=PCONTEXT,
2753 TTE_V=1,
2754 TTE_Size=0,
2755 TTE_SIZE_PTR=0,
2756 TTE_NFO=0,
2757 TTE_IE=0,
2758 TTE_Soft2=0,
2759 TTE_Diag=0,
2760 TTE_Soft=0,
2761 TTE_L=0,
2762 TTE_CP=1,
2763 TTE_CV=1,
2764 TTE_E=0,
2765 TTE_P=0,
2766 TTE_W=1,
2767 tsbonly
2768 }
2769
2770.data
2771.skip 1024
2772
2773SECTION region0_alias0 DATA_VA=0x6600000
2774attr_data {
2775 Name = region0_alias0,
2776 VA=0x6600000,
2777 RA=0x43000000,
2778 PA=ra2pa(0x43000000,0),
2779 part_0_ctx_nonzero_tsb_config_0,
2780 TTE_G=0,
2781 TTE_Context=PCONTEXT,
2782 TTE_V=1,
2783 TTE_Size=0,
2784 TTE_SIZE_PTR=0,
2785 TTE_NFO=0,
2786 TTE_IE=0,
2787 TTE_Soft2=0,
2788 TTE_Diag=0,
2789 TTE_Soft=0,
2790 TTE_L=0,
2791 TTE_CP=1,
2792 TTE_CV=0,
2793 TTE_E=0,
2794 TTE_P=0,
2795 TTE_W=1
2796 }
2797
2798SECTION region1_alias0 DATA_VA=0x6620000
2799attr_data {
2800 Name = region1_alias0,
2801 VA=0x6620000,
2802 RA=0x43800000,
2803 PA=ra2pa(0x43800000,0),
2804 part_0_ctx_nonzero_tsb_config_0,
2805 TTE_G=0,
2806 TTE_Context=PCONTEXT,
2807 TTE_V=1,
2808 TTE_Size=0,
2809 TTE_SIZE_PTR=0,
2810 TTE_NFO=0,
2811 TTE_IE=0,
2812 TTE_Soft2=0,
2813 TTE_Diag=0,
2814 TTE_Soft=0,
2815 TTE_L=0,
2816 TTE_CP=1,
2817 TTE_CV=1,
2818 TTE_E=0,
2819 TTE_P=0,
2820 TTE_W=1
2821 }
2822
2823SECTION region2_alias0 DATA_VA=0x6640000
2824attr_data {
2825 Name = region2_alias0,
2826 VA=0x6640000,
2827 RA=0x44000000,
2828 PA=ra2pa(0x44000000,0),
2829 part_0_ctx_nonzero_tsb_config_0,
2830 TTE_G=0,
2831 TTE_Context=PCONTEXT,
2832 TTE_V=1,
2833 TTE_Size=0,
2834 TTE_SIZE_PTR=0,
2835 TTE_NFO=0,
2836 TTE_IE=0,
2837 TTE_Soft2=0,
2838 TTE_Diag=0,
2839 TTE_Soft=0,
2840 TTE_L=0,
2841 TTE_CP=1,
2842 TTE_CV=1,
2843 TTE_E=0,
2844 TTE_P=0,
2845 TTE_W=1
2846 }
2847
2848SECTION region3_alias0 DATA_VA=0x6660000
2849attr_data {
2850 Name = region3_alias0,
2851 VA=0x6660000,
2852 RA=0x44800000,
2853 PA=ra2pa(0x44800000,0),
2854 part_0_ctx_nonzero_tsb_config_0,
2855 TTE_G=0,
2856 TTE_Context=PCONTEXT,
2857 TTE_V=1,
2858 TTE_Size=0,
2859 TTE_SIZE_PTR=0,
2860 TTE_NFO=0,
2861 TTE_IE=0,
2862 TTE_Soft2=0,
2863 TTE_Diag=0,
2864 TTE_Soft=0,
2865 TTE_L=0,
2866 TTE_CP=1,
2867 TTE_CV=1,
2868 TTE_E=0,
2869 TTE_P=0,
2870 TTE_W=1
2871 }
2872
2873SECTION region4_alias0 DATA_VA=0x6680000
2874attr_data {
2875 Name = region4_alias0,
2876 VA=0x6680000,
2877 RA=0x45000000,
2878 PA=ra2pa(0x45000000,0),
2879 part_0_ctx_nonzero_tsb_config_0,
2880 TTE_G=0,
2881 TTE_Context=PCONTEXT,
2882 TTE_V=1,
2883 TTE_Size=0,
2884 TTE_SIZE_PTR=0,
2885 TTE_NFO=0,
2886 TTE_IE=0,
2887 TTE_Soft2=0,
2888 TTE_Diag=0,
2889 TTE_Soft=0,
2890 TTE_L=0,
2891 TTE_CP=1,
2892 TTE_CV=1,
2893 TTE_E=0,
2894 TTE_P=0,
2895 TTE_W=1
2896 }
2897
2898SECTION region5_alias0 DATA_VA=0x66a0000
2899attr_data {
2900 Name = region5_alias0,
2901 VA=0x66a0000,
2902 RA=0x45800000,
2903 PA=ra2pa(0x45800000,0),
2904 part_0_ctx_nonzero_tsb_config_0,
2905 TTE_G=0,
2906 TTE_Context=PCONTEXT,
2907 TTE_V=1,
2908 TTE_Size=0,
2909 TTE_SIZE_PTR=0,
2910 TTE_NFO=0,
2911 TTE_IE=0,
2912 TTE_Soft2=0,
2913 TTE_Diag=0,
2914 TTE_Soft=0,
2915 TTE_L=0,
2916 TTE_CP=1,
2917 TTE_CV=1,
2918 TTE_E=0,
2919 TTE_P=0,
2920 TTE_W=1
2921 }
2922
2923SECTION region6_alias0 DATA_VA=0x66c0000
2924attr_data {
2925 Name = region6_alias0,
2926 VA=0x66c0000,
2927 RA=0x46000000,
2928 PA=ra2pa(0x46000000,0),
2929 part_0_ctx_nonzero_tsb_config_0,
2930 TTE_G=0,
2931 TTE_Context=PCONTEXT,
2932 TTE_V=1,
2933 TTE_Size=0,
2934 TTE_SIZE_PTR=0,
2935 TTE_NFO=0,
2936 TTE_IE=0,
2937 TTE_Soft2=0,
2938 TTE_Diag=0,
2939 TTE_Soft=0,
2940 TTE_L=0,
2941 TTE_CP=1,
2942 TTE_CV=1,
2943 TTE_E=0,
2944 TTE_P=0,
2945 TTE_W=1
2946 }
2947
2948SECTION region7_alias0 DATA_VA=0x66e0000
2949attr_data {
2950 Name = region7_alias0,
2951 VA=0x66e0000,
2952 RA=0x46800000,
2953 PA=ra2pa(0x46800000,0),
2954 part_0_ctx_nonzero_tsb_config_0,
2955 TTE_G=0,
2956 TTE_Context=PCONTEXT,
2957 TTE_V=1,
2958 TTE_Size=0,
2959 TTE_SIZE_PTR=0,
2960 TTE_NFO=0,
2961 TTE_IE=0,
2962 TTE_Soft2=0,
2963 TTE_Diag=0,
2964 TTE_Soft=0,
2965 TTE_L=0,
2966 TTE_CP=1,
2967 TTE_CV=1,
2968 TTE_E=0,
2969 TTE_P=0,
2970 TTE_W=1
2971 }
2972
2973SECTION replacement0_alias0 DATA_VA=0x6700000
2974attr_data {
2975 Name = replacement0_alias0,
2976 VA=0x6700000,
2977 RA=0x47000000,
2978 PA=ra2pa(0x47000000,0),
2979 part_0_ctx_nonzero_tsb_config_0,
2980 TTE_G=0,
2981 TTE_Context=PCONTEXT,
2982 TTE_V=1,
2983 TTE_Size=0,
2984 TTE_SIZE_PTR=0,
2985 TTE_NFO=0,
2986 TTE_IE=0,
2987 TTE_Soft2=0,
2988 TTE_Diag=0,
2989 TTE_Soft=0,
2990 TTE_L=0,
2991 TTE_CP=1,
2992 TTE_CV=1,
2993 TTE_E=0,
2994 TTE_P=0,
2995 TTE_W=1
2996 }
2997
2998SECTION replacement1_alias0 DATA_VA=0x6720000
2999attr_data {
3000 Name = replacement1_alias0,
3001 VA=0x6720000,
3002 RA=0x47800000,
3003 PA=ra2pa(0x47800000,0),
3004 part_0_ctx_nonzero_tsb_config_0,
3005 TTE_G=0,
3006 TTE_Context=PCONTEXT,
3007 TTE_V=1,
3008 TTE_Size=0,
3009 TTE_SIZE_PTR=0,
3010 TTE_NFO=0,
3011 TTE_IE=0,
3012 TTE_Soft2=0,
3013 TTE_Diag=0,
3014 TTE_Soft=0,
3015 TTE_L=0,
3016 TTE_CP=1,
3017 TTE_CV=1,
3018 TTE_E=0,
3019 TTE_P=0,
3020 TTE_W=1
3021 }
3022
3023SECTION replacement2_alias0 DATA_VA=0x6740000
3024attr_data {
3025 Name = replacement2_alias0,
3026 VA=0x6740000,
3027 RA=0x48000000,
3028 PA=ra2pa(0x48000000,0),
3029 part_0_ctx_nonzero_tsb_config_0,
3030 TTE_G=0,
3031 TTE_Context=PCONTEXT,
3032 TTE_V=1,
3033 TTE_Size=0,
3034 TTE_SIZE_PTR=0,
3035 TTE_NFO=0,
3036 TTE_IE=0,
3037 TTE_Soft2=0,
3038 TTE_Diag=0,
3039 TTE_Soft=0,
3040 TTE_L=0,
3041 TTE_CP=1,
3042 TTE_CV=1,
3043 TTE_E=0,
3044 TTE_P=0,
3045 TTE_W=1
3046 }
3047
3048SECTION replacement3_alias0 DATA_VA=0x6760000
3049attr_data {
3050 Name = replacement3_alias0,
3051 VA=0x6760000,
3052 RA=0x48800000,
3053 PA=ra2pa(0x48800000,0),
3054 part_0_ctx_nonzero_tsb_config_0,
3055 TTE_G=0,
3056 TTE_Context=PCONTEXT,
3057 TTE_V=1,
3058 TTE_Size=0,
3059 TTE_SIZE_PTR=0,
3060 TTE_NFO=0,
3061 TTE_IE=0,
3062 TTE_Soft2=0,
3063 TTE_Diag=0,
3064 TTE_Soft=0,
3065 TTE_L=0,
3066 TTE_CP=1,
3067 TTE_CV=1,
3068 TTE_E=0,
3069 TTE_P=0,
3070 TTE_W=1
3071 }
3072
3073SECTION replacement4_alias0 DATA_VA=0x6780000
3074attr_data {
3075 Name = replacement4_alias0,
3076 VA=0x6780000,
3077 RA=0x49000000,
3078 PA=ra2pa(0x49000000,0),
3079 part_0_ctx_nonzero_tsb_config_0,
3080 TTE_G=0,
3081 TTE_Context=PCONTEXT,
3082 TTE_V=1,
3083 TTE_Size=0,
3084 TTE_SIZE_PTR=0,
3085 TTE_NFO=0,
3086 TTE_IE=0,
3087 TTE_Soft2=0,
3088 TTE_Diag=0,
3089 TTE_Soft=0,
3090 TTE_L=0,
3091 TTE_CP=1,
3092 TTE_CV=1,
3093 TTE_E=0,
3094 TTE_P=0,
3095 TTE_W=1
3096 }
3097
3098SECTION replacement5_alias0 DATA_VA=0x67a0000
3099attr_data {
3100 Name = replacement5_alias0,
3101 VA=0x67a0000,
3102 RA=0x49800000,
3103 PA=ra2pa(0x49800000,0),
3104 part_0_ctx_nonzero_tsb_config_0,
3105 TTE_G=0,
3106 TTE_Context=PCONTEXT,
3107 TTE_V=1,
3108 TTE_Size=0,
3109 TTE_SIZE_PTR=0,
3110 TTE_NFO=0,
3111 TTE_IE=0,
3112 TTE_Soft2=0,
3113 TTE_Diag=0,
3114 TTE_Soft=0,
3115 TTE_L=0,
3116 TTE_CP=1,
3117 TTE_CV=1,
3118 TTE_E=0,
3119 TTE_P=0,
3120 TTE_W=1
3121 }
3122
3123SECTION replacement6_alias0 DATA_VA=0x67c0000
3124attr_data {
3125 Name = replacement6_alias0,
3126 VA=0x67c0000,
3127 RA=0x4a000000,
3128 PA=ra2pa(0x4a000000,0),
3129 part_0_ctx_nonzero_tsb_config_0,
3130 TTE_G=0,
3131 TTE_Context=PCONTEXT,
3132 TTE_V=1,
3133 TTE_Size=0,
3134 TTE_SIZE_PTR=0,
3135 TTE_NFO=0,
3136 TTE_IE=0,
3137 TTE_Soft2=0,
3138 TTE_Diag=0,
3139 TTE_Soft=0,
3140 TTE_L=0,
3141 TTE_CP=1,
3142 TTE_CV=1,
3143 TTE_E=0,
3144 TTE_P=0,
3145 TTE_W=1
3146 }
3147
3148SECTION replacement7_alias0 DATA_VA=0x67e0000
3149attr_data {
3150 Name = replacement7_alias0,
3151 VA=0x67e0000,
3152 RA=0x4a800000,
3153 PA=ra2pa(0x4a800000,0),
3154 part_0_ctx_nonzero_tsb_config_0,
3155 TTE_G=0,
3156 TTE_Context=PCONTEXT,
3157 TTE_V=1,
3158 TTE_Size=0,
3159 TTE_SIZE_PTR=0,
3160 TTE_NFO=0,
3161 TTE_IE=0,
3162 TTE_Soft2=0,
3163 TTE_Diag=0,
3164 TTE_Soft=0,
3165 TTE_L=0,
3166 TTE_CP=1,
3167 TTE_CV=1,
3168 TTE_E=0,
3169 TTE_P=0,
3170 TTE_W=1
3171 }
3172
3173SECTION non_fault_area_4 DATA_VA=0x0
3174attr_data {
3175 Name = non_fault_area_4,
3176 VA=0x0,
3177 RA=0x47002000,
3178 PA=ra2pa(0x47002000,0),
3179 part_0_ctx_nonzero_tsb_config_0,
3180 TTE_G=0,
3181 TTE_Context=PCONTEXT,
3182 TTE_V=1,
3183 TTE_Size=0,
3184 TTE_SIZE_PTR=0,
3185 TTE_NFO=1,
3186 TTE_IE=0,
3187 TTE_Soft2=0,
3188 TTE_Diag=0,
3189 TTE_Soft=0,
3190 TTE_L=1,
3191 TTE_CP=1,
3192 TTE_CV=1,
3193 TTE_E=0,
3194 TTE_P=0,
3195 TTE_W=1,
3196 tsbonly
3197 }
3198
3199.data
3200.skip 1024
3201
3202SECTION region0_alias3_0 DATA_VA=0x6000000
3203attr_data {
3204 Name = region0_alias3_0,
3205 VA=0x6000000,
3206 RA=0x43000000,
3207 PA=ra2pa(0x43000000,0),
3208part_0_ctx_zero_tsb_config_2,
3209 TTE_G=0,
3210 TTE_Context=0,
3211 TTE_V=1,
3212 TTE_Size=0,
3213 TTE_SIZE_PTR=0,
3214 TTE_NFO=0,
3215 TTE_IE=0,
3216 TTE_Soft2=0,
3217 TTE_Diag=0,
3218 TTE_Soft=0,
3219 TTE_L=0,
3220 TTE_CP=1,
3221 TTE_CV=0,
3222 TTE_E=0,
3223 TTE_P=0,
3224 TTE_W=1,
3225 tsbonly
3226 }
3227
3228.data
3229.skip 1024
3230
3231SECTION region1_alias3_0 DATA_VA=0x6020000
3232attr_data {
3233 Name = region1_alias3_0,
3234 VA=0x6020000,
3235 RA=0x43800000,
3236 PA=ra2pa(0x43800000,0),
3237part_0_ctx_zero_tsb_config_2,
3238 TTE_G=0,
3239 TTE_Context=0,
3240 TTE_V=1,
3241 TTE_Size=0,
3242 TTE_SIZE_PTR=0,
3243 TTE_NFO=0,
3244 TTE_IE=0,
3245 TTE_Soft2=0,
3246 TTE_Diag=0,
3247 TTE_Soft=0,
3248 TTE_L=0,
3249 TTE_CP=1,
3250 TTE_CV=1,
3251 TTE_E=0,
3252 TTE_P=0,
3253 TTE_W=1,
3254 tsbonly
3255 }
3256
3257.data
3258.skip 1024
3259
3260SECTION region2_alias3_0 DATA_VA=0x6040000
3261attr_data {
3262 Name = region2_alias3_0,
3263 VA=0x6040000,
3264 RA=0x44000000,
3265 PA=ra2pa(0x44000000,0),
3266part_0_ctx_zero_tsb_config_2,
3267 TTE_G=0,
3268 TTE_Context=0,
3269 TTE_V=1,
3270 TTE_Size=0,
3271 TTE_SIZE_PTR=0,
3272 TTE_NFO=0,
3273 TTE_IE=0,
3274 TTE_Soft2=0,
3275 TTE_Diag=0,
3276 TTE_Soft=0,
3277 TTE_L=0,
3278 TTE_CP=1,
3279 TTE_CV=1,
3280 TTE_E=0,
3281 TTE_P=0,
3282 TTE_W=1,
3283 tsbonly
3284 }
3285
3286.data
3287.skip 1024
3288
3289SECTION region3_alias3_0 DATA_VA=0x6060000
3290attr_data {
3291 Name = region3_alias3_0,
3292 VA=0x6060000,
3293 RA=0x44800000,
3294 PA=ra2pa(0x44800000,0),
3295part_0_ctx_zero_tsb_config_2,
3296 TTE_G=0,
3297 TTE_Context=0,
3298 TTE_V=1,
3299 TTE_Size=0,
3300 TTE_SIZE_PTR=0,
3301 TTE_NFO=0,
3302 TTE_IE=0,
3303 TTE_Soft2=0,
3304 TTE_Diag=0,
3305 TTE_Soft=0,
3306 TTE_L=0,
3307 TTE_CP=1,
3308 TTE_CV=1,
3309 TTE_E=0,
3310 TTE_P=0,
3311 TTE_W=1,
3312 tsbonly
3313 }
3314
3315.data
3316.skip 1024
3317
3318SECTION region4_alias3_0 DATA_VA=0x6080000
3319attr_data {
3320 Name = region4_alias3_0,
3321 VA=0x6080000,
3322 RA=0x45000000,
3323 PA=ra2pa(0x45000000,0),
3324part_0_ctx_zero_tsb_config_2,
3325 TTE_G=0,
3326 TTE_Context=0,
3327 TTE_V=1,
3328 TTE_Size=0,
3329 TTE_SIZE_PTR=0,
3330 TTE_NFO=0,
3331 TTE_IE=0,
3332 TTE_Soft2=0,
3333 TTE_Diag=0,
3334 TTE_Soft=0,
3335 TTE_L=0,
3336 TTE_CP=1,
3337 TTE_CV=1,
3338 TTE_E=0,
3339 TTE_P=0,
3340 TTE_W=1,
3341 tsbonly
3342 }
3343
3344.data
3345.skip 1024
3346
3347SECTION region5_alias3_0 DATA_VA=0x60a0000
3348attr_data {
3349 Name = region5_alias3_0,
3350 VA=0x60a0000,
3351 RA=0x45800000,
3352 PA=ra2pa(0x45800000,0),
3353part_0_ctx_zero_tsb_config_2,
3354 TTE_G=0,
3355 TTE_Context=0,
3356 TTE_V=1,
3357 TTE_Size=0,
3358 TTE_SIZE_PTR=0,
3359 TTE_NFO=0,
3360 TTE_IE=0,
3361 TTE_Soft2=0,
3362 TTE_Diag=0,
3363 TTE_Soft=0,
3364 TTE_L=0,
3365 TTE_CP=1,
3366 TTE_CV=1,
3367 TTE_E=0,
3368 TTE_P=0,
3369 TTE_W=1,
3370 tsbonly
3371 }
3372
3373.data
3374.skip 1024
3375
3376SECTION region6_alias3_0 DATA_VA=0x60c0000
3377attr_data {
3378 Name = region6_alias3_0,
3379 VA=0x60c0000,
3380 RA=0x46000000,
3381 PA=ra2pa(0x46000000,0),
3382part_0_ctx_zero_tsb_config_2,
3383 TTE_G=0,
3384 TTE_Context=0,
3385 TTE_V=1,
3386 TTE_Size=0,
3387 TTE_SIZE_PTR=0,
3388 TTE_NFO=0,
3389 TTE_IE=0,
3390 TTE_Soft2=0,
3391 TTE_Diag=0,
3392 TTE_Soft=0,
3393 TTE_L=0,
3394 TTE_CP=1,
3395 TTE_CV=1,
3396 TTE_E=0,
3397 TTE_P=0,
3398 TTE_W=1,
3399 tsbonly
3400 }
3401
3402.data
3403.skip 1024
3404
3405SECTION region7_alias3_0 DATA_VA=0x60e0000
3406attr_data {
3407 Name = region7_alias3_0,
3408 VA=0x60e0000,
3409 RA=0x46800000,
3410 PA=ra2pa(0x46800000,0),
3411part_0_ctx_zero_tsb_config_2,
3412 TTE_G=0,
3413 TTE_Context=0,
3414 TTE_V=1,
3415 TTE_Size=0,
3416 TTE_SIZE_PTR=0,
3417 TTE_NFO=0,
3418 TTE_IE=0,
3419 TTE_Soft2=0,
3420 TTE_Diag=0,
3421 TTE_Soft=0,
3422 TTE_L=0,
3423 TTE_CP=1,
3424 TTE_CV=1,
3425 TTE_E=0,
3426 TTE_P=0,
3427 TTE_W=1,
3428 tsbonly
3429 }
3430
3431.data
3432.skip 1024
3433
3434SECTION replacement0_alias3_0 DATA_VA=0x6100000
3435attr_data {
3436 Name = replacement0_alias3_0,
3437 VA=0x6100000,
3438 RA=0x47000000,
3439 PA=ra2pa(0x47000000,0),
3440part_0_ctx_zero_tsb_config_2,
3441 TTE_G=0,
3442 TTE_Context=0,
3443 TTE_V=1,
3444 TTE_Size=0,
3445 TTE_SIZE_PTR=0,
3446 TTE_NFO=0,
3447 TTE_IE=0,
3448 TTE_Soft2=0,
3449 TTE_Diag=0,
3450 TTE_Soft=0,
3451 TTE_L=0,
3452 TTE_CP=1,
3453 TTE_CV=1,
3454 TTE_E=0,
3455 TTE_P=0,
3456 TTE_W=1,
3457 tsbonly
3458 }
3459
3460.data
3461.skip 1024
3462
3463SECTION replacement1_alias3_0 DATA_VA=0x6120000
3464attr_data {
3465 Name = replacement1_alias3_0,
3466 VA=0x6120000,
3467 RA=0x47800000,
3468 PA=ra2pa(0x47800000,0),
3469part_0_ctx_zero_tsb_config_2,
3470 TTE_G=0,
3471 TTE_Context=0,
3472 TTE_V=1,
3473 TTE_Size=0,
3474 TTE_SIZE_PTR=0,
3475 TTE_NFO=0,
3476 TTE_IE=0,
3477 TTE_Soft2=0,
3478 TTE_Diag=0,
3479 TTE_Soft=0,
3480 TTE_L=0,
3481 TTE_CP=1,
3482 TTE_CV=1,
3483 TTE_E=0,
3484 TTE_P=0,
3485 TTE_W=1,
3486 tsbonly
3487 }
3488
3489.data
3490.skip 1024
3491
3492SECTION replacement2_alias3_0 DATA_VA=0x6140000
3493attr_data {
3494 Name = replacement2_alias3_0,
3495 VA=0x6140000,
3496 RA=0x48000000,
3497 PA=ra2pa(0x48000000,0),
3498part_0_ctx_zero_tsb_config_2,
3499 TTE_G=0,
3500 TTE_Context=0,
3501 TTE_V=1,
3502 TTE_Size=0,
3503 TTE_SIZE_PTR=0,
3504 TTE_NFO=0,
3505 TTE_IE=0,
3506 TTE_Soft2=0,
3507 TTE_Diag=0,
3508 TTE_Soft=0,
3509 TTE_L=0,
3510 TTE_CP=1,
3511 TTE_CV=1,
3512 TTE_E=0,
3513 TTE_P=0,
3514 TTE_W=1,
3515 tsbonly
3516 }
3517
3518.data
3519.skip 1024
3520
3521SECTION replacement3_alias3_0 DATA_VA=0x6160000
3522attr_data {
3523 Name = replacement3_alias3_0,
3524 VA=0x6160000,
3525 RA=0x48800000,
3526 PA=ra2pa(0x48800000,0),
3527part_0_ctx_zero_tsb_config_2,
3528 TTE_G=0,
3529 TTE_Context=0,
3530 TTE_V=1,
3531 TTE_Size=0,
3532 TTE_SIZE_PTR=0,
3533 TTE_NFO=0,
3534 TTE_IE=0,
3535 TTE_Soft2=0,
3536 TTE_Diag=0,
3537 TTE_Soft=0,
3538 TTE_L=0,
3539 TTE_CP=1,
3540 TTE_CV=1,
3541 TTE_E=0,
3542 TTE_P=0,
3543 TTE_W=1,
3544 tsbonly
3545 }
3546
3547.data
3548.skip 1024
3549
3550SECTION replacement4_alias3_0 DATA_VA=0x6180000
3551attr_data {
3552 Name = replacement4_alias3_0,
3553 VA=0x6180000,
3554 RA=0x49000000,
3555 PA=ra2pa(0x49000000,0),
3556part_0_ctx_zero_tsb_config_2,
3557 TTE_G=0,
3558 TTE_Context=0,
3559 TTE_V=1,
3560 TTE_Size=0,
3561 TTE_SIZE_PTR=0,
3562 TTE_NFO=0,
3563 TTE_IE=0,
3564 TTE_Soft2=0,
3565 TTE_Diag=0,
3566 TTE_Soft=0,
3567 TTE_L=0,
3568 TTE_CP=1,
3569 TTE_CV=1,
3570 TTE_E=0,
3571 TTE_P=0,
3572 TTE_W=1,
3573 tsbonly
3574 }
3575
3576.data
3577.skip 1024
3578
3579SECTION replacement5_alias3_0 DATA_VA=0x61a0000
3580attr_data {
3581 Name = replacement5_alias3_0,
3582 VA=0x61a0000,
3583 RA=0x49800000,
3584 PA=ra2pa(0x49800000,0),
3585part_0_ctx_zero_tsb_config_2,
3586 TTE_G=0,
3587 TTE_Context=0,
3588 TTE_V=1,
3589 TTE_Size=0,
3590 TTE_SIZE_PTR=0,
3591 TTE_NFO=0,
3592 TTE_IE=0,
3593 TTE_Soft2=0,
3594 TTE_Diag=0,
3595 TTE_Soft=0,
3596 TTE_L=0,
3597 TTE_CP=1,
3598 TTE_CV=1,
3599 TTE_E=0,
3600 TTE_P=0,
3601 TTE_W=1,
3602 tsbonly
3603 }
3604
3605.data
3606.skip 1024
3607
3608SECTION replacement6_alias3_0 DATA_VA=0x61c0000
3609attr_data {
3610 Name = replacement6_alias3_0,
3611 VA=0x61c0000,
3612 RA=0x4a000000,
3613 PA=ra2pa(0x4a000000,0),
3614part_0_ctx_zero_tsb_config_2,
3615 TTE_G=0,
3616 TTE_Context=0,
3617 TTE_V=1,
3618 TTE_Size=0,
3619 TTE_SIZE_PTR=0,
3620 TTE_NFO=0,
3621 TTE_IE=0,
3622 TTE_Soft2=0,
3623 TTE_Diag=0,
3624 TTE_Soft=0,
3625 TTE_L=0,
3626 TTE_CP=1,
3627 TTE_CV=1,
3628 TTE_E=0,
3629 TTE_P=0,
3630 TTE_W=1,
3631 tsbonly
3632 }
3633
3634.data
3635.skip 1024
3636
3637SECTION replacement7_alias3_0 DATA_VA=0x61e0000
3638attr_data {
3639 Name = replacement7_alias3_0,
3640 VA=0x61e0000,
3641 RA=0x4a800000,
3642 PA=ra2pa(0x4a800000,0),
3643part_0_ctx_zero_tsb_config_2,
3644 TTE_G=0,
3645 TTE_Context=0,
3646 TTE_V=1,
3647 TTE_Size=0,
3648 TTE_SIZE_PTR=0,
3649 TTE_NFO=0,
3650 TTE_IE=0,
3651 TTE_Soft2=0,
3652 TTE_Diag=0,
3653 TTE_Soft=0,
3654 TTE_L=0,
3655 TTE_CP=1,
3656 TTE_CV=1,
3657 TTE_E=0,
3658 TTE_P=0,
3659 TTE_W=1,
3660 tsbonly
3661 }
3662
3663.data
3664.skip 1024
3665
3666SECTION region0_alias2_0 DATA_VA=0x6200000
3667attr_data {
3668 Name = region0_alias2_0,
3669 VA=0x6200000,
3670 RA=0x43000000,
3671 PA=ra2pa(0x43000000,0),
3672part_0_ctx_zero_tsb_config_2,
3673 TTE_G=0,
3674 TTE_Context=0,
3675 TTE_V=1,
3676 TTE_Size=0,
3677 TTE_SIZE_PTR=0,
3678 TTE_NFO=0,
3679 TTE_IE=0,
3680 TTE_Soft2=0,
3681 TTE_Diag=0,
3682 TTE_Soft=0,
3683 TTE_L=0,
3684 TTE_CP=1,
3685 TTE_CV=0,
3686 TTE_E=0,
3687 TTE_P=0,
3688 TTE_W=1,
3689 tsbonly
3690 }
3691
3692.data
3693.skip 1024
3694
3695SECTION region1_alias2_0 DATA_VA=0x6220000
3696attr_data {
3697 Name = region1_alias2_0,
3698 VA=0x6220000,
3699 RA=0x43800000,
3700 PA=ra2pa(0x43800000,0),
3701part_0_ctx_zero_tsb_config_2,
3702 TTE_G=0,
3703 TTE_Context=0,
3704 TTE_V=1,
3705 TTE_Size=0,
3706 TTE_SIZE_PTR=0,
3707 TTE_NFO=0,
3708 TTE_IE=0,
3709 TTE_Soft2=0,
3710 TTE_Diag=0,
3711 TTE_Soft=0,
3712 TTE_L=0,
3713 TTE_CP=1,
3714 TTE_CV=1,
3715 TTE_E=0,
3716 TTE_P=0,
3717 TTE_W=1,
3718 tsbonly
3719 }
3720
3721.data
3722.skip 1024
3723
3724SECTION region2_alias2_0 DATA_VA=0x6240000
3725attr_data {
3726 Name = region2_alias2_0,
3727 VA=0x6240000,
3728 RA=0x44000000,
3729 PA=ra2pa(0x44000000,0),
3730part_0_ctx_zero_tsb_config_2,
3731 TTE_G=0,
3732 TTE_Context=0,
3733 TTE_V=1,
3734 TTE_Size=0,
3735 TTE_SIZE_PTR=0,
3736 TTE_NFO=0,
3737 TTE_IE=0,
3738 TTE_Soft2=0,
3739 TTE_Diag=0,
3740 TTE_Soft=0,
3741 TTE_L=0,
3742 TTE_CP=1,
3743 TTE_CV=1,
3744 TTE_E=0,
3745 TTE_P=0,
3746 TTE_W=1,
3747 tsbonly
3748 }
3749
3750.data
3751.skip 1024
3752
3753SECTION region3_alias2_0 DATA_VA=0x6260000
3754attr_data {
3755 Name = region3_alias2_0,
3756 VA=0x6260000,
3757 RA=0x44800000,
3758 PA=ra2pa(0x44800000,0),
3759part_0_ctx_zero_tsb_config_2,
3760 TTE_G=0,
3761 TTE_Context=0,
3762 TTE_V=1,
3763 TTE_Size=0,
3764 TTE_SIZE_PTR=0,
3765 TTE_NFO=0,
3766 TTE_IE=0,
3767 TTE_Soft2=0,
3768 TTE_Diag=0,
3769 TTE_Soft=0,
3770 TTE_L=0,
3771 TTE_CP=1,
3772 TTE_CV=1,
3773 TTE_E=0,
3774 TTE_P=0,
3775 TTE_W=1,
3776 tsbonly
3777 }
3778
3779.data
3780.skip 1024
3781
3782SECTION region4_alias2_0 DATA_VA=0x6280000
3783attr_data {
3784 Name = region4_alias2_0,
3785 VA=0x6280000,
3786 RA=0x45000000,
3787 PA=ra2pa(0x45000000,0),
3788part_0_ctx_zero_tsb_config_2,
3789 TTE_G=0,
3790 TTE_Context=0,
3791 TTE_V=1,
3792 TTE_Size=0,
3793 TTE_SIZE_PTR=0,
3794 TTE_NFO=0,
3795 TTE_IE=0,
3796 TTE_Soft2=0,
3797 TTE_Diag=0,
3798 TTE_Soft=0,
3799 TTE_L=0,
3800 TTE_CP=1,
3801 TTE_CV=1,
3802 TTE_E=0,
3803 TTE_P=0,
3804 TTE_W=1,
3805 tsbonly
3806 }
3807
3808.data
3809.skip 1024
3810
3811SECTION region5_alias2_0 DATA_VA=0x62a0000
3812attr_data {
3813 Name = region5_alias2_0,
3814 VA=0x62a0000,
3815 RA=0x45800000,
3816 PA=ra2pa(0x45800000,0),
3817part_0_ctx_zero_tsb_config_2,
3818 TTE_G=0,
3819 TTE_Context=0,
3820 TTE_V=1,
3821 TTE_Size=0,
3822 TTE_SIZE_PTR=0,
3823 TTE_NFO=0,
3824 TTE_IE=0,
3825 TTE_Soft2=0,
3826 TTE_Diag=0,
3827 TTE_Soft=0,
3828 TTE_L=0,
3829 TTE_CP=1,
3830 TTE_CV=1,
3831 TTE_E=0,
3832 TTE_P=0,
3833 TTE_W=1,
3834 tsbonly
3835 }
3836
3837.data
3838.skip 1024
3839
3840SECTION region6_alias2_0 DATA_VA=0x62c0000
3841attr_data {
3842 Name = region6_alias2_0,
3843 VA=0x62c0000,
3844 RA=0x46000000,
3845 PA=ra2pa(0x46000000,0),
3846part_0_ctx_zero_tsb_config_2,
3847 TTE_G=0,
3848 TTE_Context=0,
3849 TTE_V=1,
3850 TTE_Size=0,
3851 TTE_SIZE_PTR=0,
3852 TTE_NFO=0,
3853 TTE_IE=0,
3854 TTE_Soft2=0,
3855 TTE_Diag=0,
3856 TTE_Soft=0,
3857 TTE_L=0,
3858 TTE_CP=1,
3859 TTE_CV=1,
3860 TTE_E=0,
3861 TTE_P=0,
3862 TTE_W=1,
3863 tsbonly
3864 }
3865
3866.data
3867.skip 1024
3868
3869SECTION region7_alias2_0 DATA_VA=0x62e0000
3870attr_data {
3871 Name = region7_alias2_0,
3872 VA=0x62e0000,
3873 RA=0x46800000,
3874 PA=ra2pa(0x46800000,0),
3875part_0_ctx_zero_tsb_config_2,
3876 TTE_G=0,
3877 TTE_Context=0,
3878 TTE_V=1,
3879 TTE_Size=0,
3880 TTE_SIZE_PTR=0,
3881 TTE_NFO=0,
3882 TTE_IE=0,
3883 TTE_Soft2=0,
3884 TTE_Diag=0,
3885 TTE_Soft=0,
3886 TTE_L=0,
3887 TTE_CP=1,
3888 TTE_CV=1,
3889 TTE_E=0,
3890 TTE_P=0,
3891 TTE_W=1,
3892 tsbonly
3893 }
3894
3895.data
3896.skip 1024
3897
3898SECTION replacement0_alias2_0 DATA_VA=0x6300000
3899attr_data {
3900 Name = replacement0_alias2_0,
3901 VA=0x6300000,
3902 RA=0x47000000,
3903 PA=ra2pa(0x47000000,0),
3904part_0_ctx_zero_tsb_config_2,
3905 TTE_G=0,
3906 TTE_Context=0,
3907 TTE_V=1,
3908 TTE_Size=0,
3909 TTE_SIZE_PTR=0,
3910 TTE_NFO=0,
3911 TTE_IE=0,
3912 TTE_Soft2=0,
3913 TTE_Diag=0,
3914 TTE_Soft=0,
3915 TTE_L=0,
3916 TTE_CP=1,
3917 TTE_CV=1,
3918 TTE_E=0,
3919 TTE_P=0,
3920 TTE_W=1,
3921 tsbonly
3922 }
3923
3924.data
3925.skip 1024
3926
3927SECTION replacement1_alias2_0 DATA_VA=0x6320000
3928attr_data {
3929 Name = replacement1_alias2_0,
3930 VA=0x6320000,
3931 RA=0x47800000,
3932 PA=ra2pa(0x47800000,0),
3933part_0_ctx_zero_tsb_config_2,
3934 TTE_G=0,
3935 TTE_Context=0,
3936 TTE_V=1,
3937 TTE_Size=0,
3938 TTE_SIZE_PTR=0,
3939 TTE_NFO=0,
3940 TTE_IE=0,
3941 TTE_Soft2=0,
3942 TTE_Diag=0,
3943 TTE_Soft=0,
3944 TTE_L=0,
3945 TTE_CP=1,
3946 TTE_CV=1,
3947 TTE_E=0,
3948 TTE_P=0,
3949 TTE_W=1,
3950 tsbonly
3951 }
3952
3953.data
3954.skip 1024
3955
3956SECTION replacement2_alias2_0 DATA_VA=0x6340000
3957attr_data {
3958 Name = replacement2_alias2_0,
3959 VA=0x6340000,
3960 RA=0x48000000,
3961 PA=ra2pa(0x48000000,0),
3962part_0_ctx_zero_tsb_config_2,
3963 TTE_G=0,
3964 TTE_Context=0,
3965 TTE_V=1,
3966 TTE_Size=0,
3967 TTE_SIZE_PTR=0,
3968 TTE_NFO=0,
3969 TTE_IE=0,
3970 TTE_Soft2=0,
3971 TTE_Diag=0,
3972 TTE_Soft=0,
3973 TTE_L=0,
3974 TTE_CP=1,
3975 TTE_CV=1,
3976 TTE_E=0,
3977 TTE_P=0,
3978 TTE_W=1,
3979 tsbonly
3980 }
3981
3982.data
3983.skip 1024
3984
3985SECTION replacement3_alias2_0 DATA_VA=0x6360000
3986attr_data {
3987 Name = replacement3_alias2_0,
3988 VA=0x6360000,
3989 RA=0x48800000,
3990 PA=ra2pa(0x48800000,0),
3991part_0_ctx_zero_tsb_config_2,
3992 TTE_G=0,
3993 TTE_Context=0,
3994 TTE_V=1,
3995 TTE_Size=0,
3996 TTE_SIZE_PTR=0,
3997 TTE_NFO=0,
3998 TTE_IE=0,
3999 TTE_Soft2=0,
4000 TTE_Diag=0,
4001 TTE_Soft=0,
4002 TTE_L=0,
4003 TTE_CP=1,
4004 TTE_CV=1,
4005 TTE_E=0,
4006 TTE_P=0,
4007 TTE_W=1,
4008 tsbonly
4009 }
4010
4011.data
4012.skip 1024
4013
4014SECTION replacement4_alias2_0 DATA_VA=0x6380000
4015attr_data {
4016 Name = replacement4_alias2_0,
4017 VA=0x6380000,
4018 RA=0x49000000,
4019 PA=ra2pa(0x49000000,0),
4020part_0_ctx_zero_tsb_config_2,
4021 TTE_G=0,
4022 TTE_Context=0,
4023 TTE_V=1,
4024 TTE_Size=0,
4025 TTE_SIZE_PTR=0,
4026 TTE_NFO=0,
4027 TTE_IE=0,
4028 TTE_Soft2=0,
4029 TTE_Diag=0,
4030 TTE_Soft=0,
4031 TTE_L=0,
4032 TTE_CP=1,
4033 TTE_CV=1,
4034 TTE_E=0,
4035 TTE_P=0,
4036 TTE_W=1,
4037 tsbonly
4038 }
4039
4040.data
4041.skip 1024
4042
4043SECTION replacement5_alias2_0 DATA_VA=0x63a0000
4044attr_data {
4045 Name = replacement5_alias2_0,
4046 VA=0x63a0000,
4047 RA=0x49800000,
4048 PA=ra2pa(0x49800000,0),
4049part_0_ctx_zero_tsb_config_2,
4050 TTE_G=0,
4051 TTE_Context=0,
4052 TTE_V=1,
4053 TTE_Size=0,
4054 TTE_SIZE_PTR=0,
4055 TTE_NFO=0,
4056 TTE_IE=0,
4057 TTE_Soft2=0,
4058 TTE_Diag=0,
4059 TTE_Soft=0,
4060 TTE_L=0,
4061 TTE_CP=1,
4062 TTE_CV=1,
4063 TTE_E=0,
4064 TTE_P=0,
4065 TTE_W=1,
4066 tsbonly
4067 }
4068
4069.data
4070.skip 1024
4071
4072SECTION replacement6_alias2_0 DATA_VA=0x63c0000
4073attr_data {
4074 Name = replacement6_alias2_0,
4075 VA=0x63c0000,
4076 RA=0x4a000000,
4077 PA=ra2pa(0x4a000000,0),
4078part_0_ctx_zero_tsb_config_2,
4079 TTE_G=0,
4080 TTE_Context=0,
4081 TTE_V=1,
4082 TTE_Size=0,
4083 TTE_SIZE_PTR=0,
4084 TTE_NFO=0,
4085 TTE_IE=0,
4086 TTE_Soft2=0,
4087 TTE_Diag=0,
4088 TTE_Soft=0,
4089 TTE_L=0,
4090 TTE_CP=1,
4091 TTE_CV=1,
4092 TTE_E=0,
4093 TTE_P=0,
4094 TTE_W=1,
4095 tsbonly
4096 }
4097
4098.data
4099.skip 1024
4100
4101SECTION replacement7_alias2_0 DATA_VA=0x63e0000
4102attr_data {
4103 Name = replacement7_alias2_0,
4104 VA=0x63e0000,
4105 RA=0x4a800000,
4106 PA=ra2pa(0x4a800000,0),
4107part_0_ctx_zero_tsb_config_2,
4108 TTE_G=0,
4109 TTE_Context=0,
4110 TTE_V=1,
4111 TTE_Size=0,
4112 TTE_SIZE_PTR=0,
4113 TTE_NFO=0,
4114 TTE_IE=0,
4115 TTE_Soft2=0,
4116 TTE_Diag=0,
4117 TTE_Soft=0,
4118 TTE_L=0,
4119 TTE_CP=1,
4120 TTE_CV=1,
4121 TTE_E=0,
4122 TTE_P=0,
4123 TTE_W=1,
4124 tsbonly
4125 }
4126
4127.data
4128.skip 1024
4129
4130SECTION region0_alias1_0 DATA_VA=0x6400000
4131attr_data {
4132 Name = region0_alias1_0,
4133 VA=0x6400000,
4134 RA=0x43000000,
4135 PA=ra2pa(0x43000000,0),
4136part_0_ctx_zero_tsb_config_2,
4137 TTE_G=0,
4138 TTE_Context=0,
4139 TTE_V=1,
4140 TTE_Size=0,
4141 TTE_SIZE_PTR=0,
4142 TTE_NFO=0,
4143 TTE_IE=0,
4144 TTE_Soft2=0,
4145 TTE_Diag=0,
4146 TTE_Soft=0,
4147 TTE_L=0,
4148 TTE_CP=1,
4149 TTE_CV=0,
4150 TTE_E=0,
4151 TTE_P=0,
4152 TTE_W=1,
4153 tsbonly
4154 }
4155
4156.data
4157.skip 1024
4158
4159SECTION region1_alias1_0 DATA_VA=0x6420000
4160attr_data {
4161 Name = region1_alias1_0,
4162 VA=0x6420000,
4163 RA=0x43800000,
4164 PA=ra2pa(0x43800000,0),
4165part_0_ctx_zero_tsb_config_2,
4166 TTE_G=0,
4167 TTE_Context=0,
4168 TTE_V=1,
4169 TTE_Size=0,
4170 TTE_SIZE_PTR=0,
4171 TTE_NFO=0,
4172 TTE_IE=0,
4173 TTE_Soft2=0,
4174 TTE_Diag=0,
4175 TTE_Soft=0,
4176 TTE_L=0,
4177 TTE_CP=1,
4178 TTE_CV=1,
4179 TTE_E=0,
4180 TTE_P=0,
4181 TTE_W=1,
4182 tsbonly
4183 }
4184
4185.data
4186.skip 1024
4187
4188SECTION region2_alias1_0 DATA_VA=0x6440000
4189attr_data {
4190 Name = region2_alias1_0,
4191 VA=0x6440000,
4192 RA=0x44000000,
4193 PA=ra2pa(0x44000000,0),
4194part_0_ctx_zero_tsb_config_2,
4195 TTE_G=0,
4196 TTE_Context=0,
4197 TTE_V=1,
4198 TTE_Size=0,
4199 TTE_SIZE_PTR=0,
4200 TTE_NFO=0,
4201 TTE_IE=0,
4202 TTE_Soft2=0,
4203 TTE_Diag=0,
4204 TTE_Soft=0,
4205 TTE_L=0,
4206 TTE_CP=1,
4207 TTE_CV=1,
4208 TTE_E=0,
4209 TTE_P=0,
4210 TTE_W=1,
4211 tsbonly
4212 }
4213
4214.data
4215.skip 1024
4216
4217SECTION region3_alias1_0 DATA_VA=0x6460000
4218attr_data {
4219 Name = region3_alias1_0,
4220 VA=0x6460000,
4221 RA=0x44800000,
4222 PA=ra2pa(0x44800000,0),
4223part_0_ctx_zero_tsb_config_2,
4224 TTE_G=0,
4225 TTE_Context=0,
4226 TTE_V=1,
4227 TTE_Size=0,
4228 TTE_SIZE_PTR=0,
4229 TTE_NFO=0,
4230 TTE_IE=0,
4231 TTE_Soft2=0,
4232 TTE_Diag=0,
4233 TTE_Soft=0,
4234 TTE_L=0,
4235 TTE_CP=1,
4236 TTE_CV=1,
4237 TTE_E=0,
4238 TTE_P=0,
4239 TTE_W=1,
4240 tsbonly
4241 }
4242
4243.data
4244.skip 1024
4245
4246SECTION region4_alias1_0 DATA_VA=0x6480000
4247attr_data {
4248 Name = region4_alias1_0,
4249 VA=0x6480000,
4250 RA=0x45000000,
4251 PA=ra2pa(0x45000000,0),
4252part_0_ctx_zero_tsb_config_2,
4253 TTE_G=0,
4254 TTE_Context=0,
4255 TTE_V=1,
4256 TTE_Size=0,
4257 TTE_SIZE_PTR=0,
4258 TTE_NFO=0,
4259 TTE_IE=0,
4260 TTE_Soft2=0,
4261 TTE_Diag=0,
4262 TTE_Soft=0,
4263 TTE_L=0,
4264 TTE_CP=1,
4265 TTE_CV=1,
4266 TTE_E=0,
4267 TTE_P=0,
4268 TTE_W=1,
4269 tsbonly
4270 }
4271
4272.data
4273.skip 1024
4274
4275SECTION region5_alias1_0 DATA_VA=0x64a0000
4276attr_data {
4277 Name = region5_alias1_0,
4278 VA=0x64a0000,
4279 RA=0x45800000,
4280 PA=ra2pa(0x45800000,0),
4281part_0_ctx_zero_tsb_config_2,
4282 TTE_G=0,
4283 TTE_Context=0,
4284 TTE_V=1,
4285 TTE_Size=0,
4286 TTE_SIZE_PTR=0,
4287 TTE_NFO=0,
4288 TTE_IE=0,
4289 TTE_Soft2=0,
4290 TTE_Diag=0,
4291 TTE_Soft=0,
4292 TTE_L=0,
4293 TTE_CP=1,
4294 TTE_CV=1,
4295 TTE_E=0,
4296 TTE_P=0,
4297 TTE_W=1,
4298 tsbonly
4299 }
4300
4301.data
4302.skip 1024
4303
4304SECTION region6_alias1_0 DATA_VA=0x64c0000
4305attr_data {
4306 Name = region6_alias1_0,
4307 VA=0x64c0000,
4308 RA=0x46000000,
4309 PA=ra2pa(0x46000000,0),
4310part_0_ctx_zero_tsb_config_2,
4311 TTE_G=0,
4312 TTE_Context=0,
4313 TTE_V=1,
4314 TTE_Size=0,
4315 TTE_SIZE_PTR=0,
4316 TTE_NFO=0,
4317 TTE_IE=0,
4318 TTE_Soft2=0,
4319 TTE_Diag=0,
4320 TTE_Soft=0,
4321 TTE_L=0,
4322 TTE_CP=1,
4323 TTE_CV=1,
4324 TTE_E=0,
4325 TTE_P=0,
4326 TTE_W=1,
4327 tsbonly
4328 }
4329
4330.data
4331.skip 1024
4332
4333SECTION region7_alias1_0 DATA_VA=0x64e0000
4334attr_data {
4335 Name = region7_alias1_0,
4336 VA=0x64e0000,
4337 RA=0x46800000,
4338 PA=ra2pa(0x46800000,0),
4339part_0_ctx_zero_tsb_config_2,
4340 TTE_G=0,
4341 TTE_Context=0,
4342 TTE_V=1,
4343 TTE_Size=0,
4344 TTE_SIZE_PTR=0,
4345 TTE_NFO=0,
4346 TTE_IE=0,
4347 TTE_Soft2=0,
4348 TTE_Diag=0,
4349 TTE_Soft=0,
4350 TTE_L=0,
4351 TTE_CP=1,
4352 TTE_CV=1,
4353 TTE_E=0,
4354 TTE_P=0,
4355 TTE_W=1,
4356 tsbonly
4357 }
4358
4359.data
4360.skip 1024
4361
4362SECTION replacement0_alias1_0 DATA_VA=0x6500000
4363attr_data {
4364 Name = replacement0_alias1_0,
4365 VA=0x6500000,
4366 RA=0x47000000,
4367 PA=ra2pa(0x47000000,0),
4368part_0_ctx_zero_tsb_config_2,
4369 TTE_G=0,
4370 TTE_Context=0,
4371 TTE_V=1,
4372 TTE_Size=0,
4373 TTE_SIZE_PTR=0,
4374 TTE_NFO=0,
4375 TTE_IE=0,
4376 TTE_Soft2=0,
4377 TTE_Diag=0,
4378 TTE_Soft=0,
4379 TTE_L=0,
4380 TTE_CP=1,
4381 TTE_CV=1,
4382 TTE_E=0,
4383 TTE_P=0,
4384 TTE_W=1,
4385 tsbonly
4386 }
4387
4388.data
4389.skip 1024
4390
4391SECTION replacement1_alias1_0 DATA_VA=0x6520000
4392attr_data {
4393 Name = replacement1_alias1_0,
4394 VA=0x6520000,
4395 RA=0x47800000,
4396 PA=ra2pa(0x47800000,0),
4397part_0_ctx_zero_tsb_config_2,
4398 TTE_G=0,
4399 TTE_Context=0,
4400 TTE_V=1,
4401 TTE_Size=0,
4402 TTE_SIZE_PTR=0,
4403 TTE_NFO=0,
4404 TTE_IE=0,
4405 TTE_Soft2=0,
4406 TTE_Diag=0,
4407 TTE_Soft=0,
4408 TTE_L=0,
4409 TTE_CP=1,
4410 TTE_CV=1,
4411 TTE_E=0,
4412 TTE_P=0,
4413 TTE_W=1,
4414 tsbonly
4415 }
4416
4417.data
4418.skip 1024
4419
4420SECTION replacement2_alias1_0 DATA_VA=0x6540000
4421attr_data {
4422 Name = replacement2_alias1_0,
4423 VA=0x6540000,
4424 RA=0x48000000,
4425 PA=ra2pa(0x48000000,0),
4426part_0_ctx_zero_tsb_config_2,
4427 TTE_G=0,
4428 TTE_Context=0,
4429 TTE_V=1,
4430 TTE_Size=0,
4431 TTE_SIZE_PTR=0,
4432 TTE_NFO=0,
4433 TTE_IE=0,
4434 TTE_Soft2=0,
4435 TTE_Diag=0,
4436 TTE_Soft=0,
4437 TTE_L=0,
4438 TTE_CP=1,
4439 TTE_CV=1,
4440 TTE_E=0,
4441 TTE_P=0,
4442 TTE_W=1,
4443 tsbonly
4444 }
4445
4446.data
4447.skip 1024
4448
4449SECTION replacement3_alias1_0 DATA_VA=0x6560000
4450attr_data {
4451 Name = replacement3_alias1_0,
4452 VA=0x6560000,
4453 RA=0x48800000,
4454 PA=ra2pa(0x48800000,0),
4455part_0_ctx_zero_tsb_config_2,
4456 TTE_G=0,
4457 TTE_Context=0,
4458 TTE_V=1,
4459 TTE_Size=0,
4460 TTE_SIZE_PTR=0,
4461 TTE_NFO=0,
4462 TTE_IE=0,
4463 TTE_Soft2=0,
4464 TTE_Diag=0,
4465 TTE_Soft=0,
4466 TTE_L=0,
4467 TTE_CP=1,
4468 TTE_CV=1,
4469 TTE_E=0,
4470 TTE_P=0,
4471 TTE_W=1,
4472 tsbonly
4473 }
4474
4475.data
4476.skip 1024
4477
4478SECTION replacement4_alias1_0 DATA_VA=0x6580000
4479attr_data {
4480 Name = replacement4_alias1_0,
4481 VA=0x6580000,
4482 RA=0x49000000,
4483 PA=ra2pa(0x49000000,0),
4484part_0_ctx_zero_tsb_config_2,
4485 TTE_G=0,
4486 TTE_Context=0,
4487 TTE_V=1,
4488 TTE_Size=0,
4489 TTE_SIZE_PTR=0,
4490 TTE_NFO=0,
4491 TTE_IE=0,
4492 TTE_Soft2=0,
4493 TTE_Diag=0,
4494 TTE_Soft=0,
4495 TTE_L=0,
4496 TTE_CP=1,
4497 TTE_CV=1,
4498 TTE_E=0,
4499 TTE_P=0,
4500 TTE_W=1,
4501 tsbonly
4502 }
4503
4504.data
4505.skip 1024
4506
4507SECTION replacement5_alias1_0 DATA_VA=0x65a0000
4508attr_data {
4509 Name = replacement5_alias1_0,
4510 VA=0x65a0000,
4511 RA=0x49800000,
4512 PA=ra2pa(0x49800000,0),
4513part_0_ctx_zero_tsb_config_2,
4514 TTE_G=0,
4515 TTE_Context=0,
4516 TTE_V=1,
4517 TTE_Size=0,
4518 TTE_SIZE_PTR=0,
4519 TTE_NFO=0,
4520 TTE_IE=0,
4521 TTE_Soft2=0,
4522 TTE_Diag=0,
4523 TTE_Soft=0,
4524 TTE_L=0,
4525 TTE_CP=1,
4526 TTE_CV=1,
4527 TTE_E=0,
4528 TTE_P=0,
4529 TTE_W=1,
4530 tsbonly
4531 }
4532
4533.data
4534.skip 1024
4535
4536SECTION replacement6_alias1_0 DATA_VA=0x65c0000
4537attr_data {
4538 Name = replacement6_alias1_0,
4539 VA=0x65c0000,
4540 RA=0x4a000000,
4541 PA=ra2pa(0x4a000000,0),
4542part_0_ctx_zero_tsb_config_2,
4543 TTE_G=0,
4544 TTE_Context=0,
4545 TTE_V=1,
4546 TTE_Size=0,
4547 TTE_SIZE_PTR=0,
4548 TTE_NFO=0,
4549 TTE_IE=0,
4550 TTE_Soft2=0,
4551 TTE_Diag=0,
4552 TTE_Soft=0,
4553 TTE_L=0,
4554 TTE_CP=1,
4555 TTE_CV=1,
4556 TTE_E=0,
4557 TTE_P=0,
4558 TTE_W=1,
4559 tsbonly
4560 }
4561
4562.data
4563.skip 1024
4564
4565SECTION replacement7_alias1_0 DATA_VA=0x65e0000
4566attr_data {
4567 Name = replacement7_alias1_0,
4568 VA=0x65e0000,
4569 RA=0x4a800000,
4570 PA=ra2pa(0x4a800000,0),
4571part_0_ctx_zero_tsb_config_2,
4572 TTE_G=0,
4573 TTE_Context=0,
4574 TTE_V=1,
4575 TTE_Size=0,
4576 TTE_SIZE_PTR=0,
4577 TTE_NFO=0,
4578 TTE_IE=0,
4579 TTE_Soft2=0,
4580 TTE_Diag=0,
4581 TTE_Soft=0,
4582 TTE_L=0,
4583 TTE_CP=1,
4584 TTE_CV=1,
4585 TTE_E=0,
4586 TTE_P=0,
4587 TTE_W=1,
4588 tsbonly
4589 }
4590
4591.data
4592.skip 1024
4593
4594SECTION region0_alias0_0 DATA_VA=0x6600000
4595attr_data {
4596 Name = region0_alias0_0,
4597 VA=0x6600000,
4598 RA=0x43000000,
4599 PA=ra2pa(0x43000000,0),
4600part_0_ctx_zero_tsb_config_2,
4601 TTE_G=0,
4602 TTE_Context=0,
4603 TTE_V=1,
4604 TTE_Size=0,
4605 TTE_SIZE_PTR=0,
4606 TTE_NFO=0,
4607 TTE_IE=0,
4608 TTE_Soft2=0,
4609 TTE_Diag=0,
4610 TTE_Soft=0,
4611 TTE_L=0,
4612 TTE_CP=1,
4613 TTE_CV=0,
4614 TTE_E=0,
4615 TTE_P=0,
4616 TTE_W=1,
4617 tsbonly
4618 }
4619
4620.data
4621.skip 1024
4622
4623SECTION region1_alias0_0 DATA_VA=0x6620000
4624attr_data {
4625 Name = region1_alias0_0,
4626 VA=0x6620000,
4627 RA=0x43800000,
4628 PA=ra2pa(0x43800000,0),
4629part_0_ctx_zero_tsb_config_2,
4630 TTE_G=0,
4631 TTE_Context=0,
4632 TTE_V=1,
4633 TTE_Size=0,
4634 TTE_SIZE_PTR=0,
4635 TTE_NFO=0,
4636 TTE_IE=0,
4637 TTE_Soft2=0,
4638 TTE_Diag=0,
4639 TTE_Soft=0,
4640 TTE_L=0,
4641 TTE_CP=1,
4642 TTE_CV=1,
4643 TTE_E=0,
4644 TTE_P=0,
4645 TTE_W=1,
4646 tsbonly
4647 }
4648
4649.data
4650.skip 1024
4651
4652SECTION region2_alias0_0 DATA_VA=0x6640000
4653attr_data {
4654 Name = region2_alias0_0,
4655 VA=0x6640000,
4656 RA=0x44000000,
4657 PA=ra2pa(0x44000000,0),
4658part_0_ctx_zero_tsb_config_2,
4659 TTE_G=0,
4660 TTE_Context=0,
4661 TTE_V=1,
4662 TTE_Size=0,
4663 TTE_SIZE_PTR=0,
4664 TTE_NFO=0,
4665 TTE_IE=0,
4666 TTE_Soft2=0,
4667 TTE_Diag=0,
4668 TTE_Soft=0,
4669 TTE_L=0,
4670 TTE_CP=1,
4671 TTE_CV=1,
4672 TTE_E=0,
4673 TTE_P=0,
4674 TTE_W=1,
4675 tsbonly
4676 }
4677
4678.data
4679.skip 1024
4680
4681SECTION region3_alias0_0 DATA_VA=0x6660000
4682attr_data {
4683 Name = region3_alias0_0,
4684 VA=0x6660000,
4685 RA=0x44800000,
4686 PA=ra2pa(0x44800000,0),
4687part_0_ctx_zero_tsb_config_2,
4688 TTE_G=0,
4689 TTE_Context=0,
4690 TTE_V=1,
4691 TTE_Size=0,
4692 TTE_SIZE_PTR=0,
4693 TTE_NFO=0,
4694 TTE_IE=0,
4695 TTE_Soft2=0,
4696 TTE_Diag=0,
4697 TTE_Soft=0,
4698 TTE_L=0,
4699 TTE_CP=1,
4700 TTE_CV=1,
4701 TTE_E=0,
4702 TTE_P=0,
4703 TTE_W=1,
4704 tsbonly
4705 }
4706
4707.data
4708.skip 1024
4709
4710SECTION region4_alias0_0 DATA_VA=0x6680000
4711attr_data {
4712 Name = region4_alias0_0,
4713 VA=0x6680000,
4714 RA=0x45000000,
4715 PA=ra2pa(0x45000000,0),
4716part_0_ctx_zero_tsb_config_2,
4717 TTE_G=0,
4718 TTE_Context=0,
4719 TTE_V=1,
4720 TTE_Size=0,
4721 TTE_SIZE_PTR=0,
4722 TTE_NFO=0,
4723 TTE_IE=0,
4724 TTE_Soft2=0,
4725 TTE_Diag=0,
4726 TTE_Soft=0,
4727 TTE_L=0,
4728 TTE_CP=1,
4729 TTE_CV=1,
4730 TTE_E=0,
4731 TTE_P=0,
4732 TTE_W=1,
4733 tsbonly
4734 }
4735
4736.data
4737.skip 1024
4738
4739SECTION region5_alias0_0 DATA_VA=0x66a0000
4740attr_data {
4741 Name = region5_alias0_0,
4742 VA=0x66a0000,
4743 RA=0x45800000,
4744 PA=ra2pa(0x45800000,0),
4745part_0_ctx_zero_tsb_config_2,
4746 TTE_G=0,
4747 TTE_Context=0,
4748 TTE_V=1,
4749 TTE_Size=0,
4750 TTE_SIZE_PTR=0,
4751 TTE_NFO=0,
4752 TTE_IE=0,
4753 TTE_Soft2=0,
4754 TTE_Diag=0,
4755 TTE_Soft=0,
4756 TTE_L=0,
4757 TTE_CP=1,
4758 TTE_CV=1,
4759 TTE_E=0,
4760 TTE_P=0,
4761 TTE_W=1,
4762 tsbonly
4763 }
4764
4765.data
4766.skip 1024
4767
4768SECTION region6_alias0_0 DATA_VA=0x66c0000
4769attr_data {
4770 Name = region6_alias0_0,
4771 VA=0x66c0000,
4772 RA=0x46000000,
4773 PA=ra2pa(0x46000000,0),
4774part_0_ctx_zero_tsb_config_2,
4775 TTE_G=0,
4776 TTE_Context=0,
4777 TTE_V=1,
4778 TTE_Size=0,
4779 TTE_SIZE_PTR=0,
4780 TTE_NFO=0,
4781 TTE_IE=0,
4782 TTE_Soft2=0,
4783 TTE_Diag=0,
4784 TTE_Soft=0,
4785 TTE_L=0,
4786 TTE_CP=1,
4787 TTE_CV=1,
4788 TTE_E=0,
4789 TTE_P=0,
4790 TTE_W=1,
4791 tsbonly
4792 }
4793
4794.data
4795.skip 1024
4796
4797SECTION region7_alias0_0 DATA_VA=0x66e0000
4798attr_data {
4799 Name = region7_alias0_0,
4800 VA=0x66e0000,
4801 RA=0x46800000,
4802 PA=ra2pa(0x46800000,0),
4803part_0_ctx_zero_tsb_config_2,
4804 TTE_G=0,
4805 TTE_Context=0,
4806 TTE_V=1,
4807 TTE_Size=0,
4808 TTE_SIZE_PTR=0,
4809 TTE_NFO=0,
4810 TTE_IE=0,
4811 TTE_Soft2=0,
4812 TTE_Diag=0,
4813 TTE_Soft=0,
4814 TTE_L=0,
4815 TTE_CP=1,
4816 TTE_CV=1,
4817 TTE_E=0,
4818 TTE_P=0,
4819 TTE_W=1,
4820 tsbonly
4821 }
4822
4823.data
4824.skip 1024
4825
4826SECTION replacement0_alias0_0 DATA_VA=0x6700000
4827attr_data {
4828 Name = replacement0_alias0_0,
4829 VA=0x6700000,
4830 RA=0x47000000,
4831 PA=ra2pa(0x47000000,0),
4832part_0_ctx_zero_tsb_config_2,
4833 TTE_G=0,
4834 TTE_Context=0,
4835 TTE_V=1,
4836 TTE_Size=0,
4837 TTE_SIZE_PTR=0,
4838 TTE_NFO=0,
4839 TTE_IE=0,
4840 TTE_Soft2=0,
4841 TTE_Diag=0,
4842 TTE_Soft=0,
4843 TTE_L=0,
4844 TTE_CP=1,
4845 TTE_CV=1,
4846 TTE_E=0,
4847 TTE_P=0,
4848 TTE_W=1,
4849 tsbonly
4850 }
4851
4852.data
4853.skip 1024
4854
4855SECTION replacement1_alias0_0 DATA_VA=0x6720000
4856attr_data {
4857 Name = replacement1_alias0_0,
4858 VA=0x6720000,
4859 RA=0x47800000,
4860 PA=ra2pa(0x47800000,0),
4861part_0_ctx_zero_tsb_config_2,
4862 TTE_G=0,
4863 TTE_Context=0,
4864 TTE_V=1,
4865 TTE_Size=0,
4866 TTE_SIZE_PTR=0,
4867 TTE_NFO=0,
4868 TTE_IE=0,
4869 TTE_Soft2=0,
4870 TTE_Diag=0,
4871 TTE_Soft=0,
4872 TTE_L=0,
4873 TTE_CP=1,
4874 TTE_CV=1,
4875 TTE_E=0,
4876 TTE_P=0,
4877 TTE_W=1,
4878 tsbonly
4879 }
4880
4881.data
4882.skip 1024
4883
4884SECTION replacement2_alias0_0 DATA_VA=0x6740000
4885attr_data {
4886 Name = replacement2_alias0_0,
4887 VA=0x6740000,
4888 RA=0x48000000,
4889 PA=ra2pa(0x48000000,0),
4890part_0_ctx_zero_tsb_config_2,
4891 TTE_G=0,
4892 TTE_Context=0,
4893 TTE_V=1,
4894 TTE_Size=0,
4895 TTE_SIZE_PTR=0,
4896 TTE_NFO=0,
4897 TTE_IE=0,
4898 TTE_Soft2=0,
4899 TTE_Diag=0,
4900 TTE_Soft=0,
4901 TTE_L=0,
4902 TTE_CP=1,
4903 TTE_CV=1,
4904 TTE_E=0,
4905 TTE_P=0,
4906 TTE_W=1,
4907 tsbonly
4908 }
4909
4910.data
4911.skip 1024
4912
4913SECTION replacement3_alias0_0 DATA_VA=0x6760000
4914attr_data {
4915 Name = replacement3_alias0_0,
4916 VA=0x6760000,
4917 RA=0x48800000,
4918 PA=ra2pa(0x48800000,0),
4919part_0_ctx_zero_tsb_config_2,
4920 TTE_G=0,
4921 TTE_Context=0,
4922 TTE_V=1,
4923 TTE_Size=0,
4924 TTE_SIZE_PTR=0,
4925 TTE_NFO=0,
4926 TTE_IE=0,
4927 TTE_Soft2=0,
4928 TTE_Diag=0,
4929 TTE_Soft=0,
4930 TTE_L=0,
4931 TTE_CP=1,
4932 TTE_CV=1,
4933 TTE_E=0,
4934 TTE_P=0,
4935 TTE_W=1,
4936 tsbonly
4937 }
4938
4939.data
4940.skip 1024
4941
4942SECTION replacement4_alias0_0 DATA_VA=0x6780000
4943attr_data {
4944 Name = replacement4_alias0_0,
4945 VA=0x6780000,
4946 RA=0x49000000,
4947 PA=ra2pa(0x49000000,0),
4948part_0_ctx_zero_tsb_config_2,
4949 TTE_G=0,
4950 TTE_Context=0,
4951 TTE_V=1,
4952 TTE_Size=0,
4953 TTE_SIZE_PTR=0,
4954 TTE_NFO=0,
4955 TTE_IE=0,
4956 TTE_Soft2=0,
4957 TTE_Diag=0,
4958 TTE_Soft=0,
4959 TTE_L=0,
4960 TTE_CP=1,
4961 TTE_CV=1,
4962 TTE_E=0,
4963 TTE_P=0,
4964 TTE_W=1,
4965 tsbonly
4966 }
4967
4968.data
4969.skip 1024
4970
4971SECTION replacement5_alias0_0 DATA_VA=0x67a0000
4972attr_data {
4973 Name = replacement5_alias0_0,
4974 VA=0x67a0000,
4975 RA=0x49800000,
4976 PA=ra2pa(0x49800000,0),
4977part_0_ctx_zero_tsb_config_2,
4978 TTE_G=0,
4979 TTE_Context=0,
4980 TTE_V=1,
4981 TTE_Size=0,
4982 TTE_SIZE_PTR=0,
4983 TTE_NFO=0,
4984 TTE_IE=0,
4985 TTE_Soft2=0,
4986 TTE_Diag=0,
4987 TTE_Soft=0,
4988 TTE_L=0,
4989 TTE_CP=1,
4990 TTE_CV=1,
4991 TTE_E=0,
4992 TTE_P=0,
4993 TTE_W=1,
4994 tsbonly
4995 }
4996
4997.data
4998.skip 1024
4999
5000SECTION replacement6_alias0_0 DATA_VA=0x67c0000
5001attr_data {
5002 Name = replacement6_alias0_0,
5003 VA=0x67c0000,
5004 RA=0x4a000000,
5005 PA=ra2pa(0x4a000000,0),
5006part_0_ctx_zero_tsb_config_2,
5007 TTE_G=0,
5008 TTE_Context=0,
5009 TTE_V=1,
5010 TTE_Size=0,
5011 TTE_SIZE_PTR=0,
5012 TTE_NFO=0,
5013 TTE_IE=0,
5014 TTE_Soft2=0,
5015 TTE_Diag=0,
5016 TTE_Soft=0,
5017 TTE_L=0,
5018 TTE_CP=1,
5019 TTE_CV=1,
5020 TTE_E=0,
5021 TTE_P=0,
5022 TTE_W=1,
5023 tsbonly
5024 }
5025
5026.data
5027.skip 1024
5028
5029SECTION replacement7_alias0_0 DATA_VA=0x67e0000
5030attr_data {
5031 Name = replacement7_alias0_0,
5032 VA=0x67e0000,
5033 RA=0x4a800000,
5034 PA=ra2pa(0x4a800000,0),
5035part_0_ctx_zero_tsb_config_2,
5036 TTE_G=0,
5037 TTE_Context=0,
5038 TTE_V=1,
5039 TTE_Size=0,
5040 TTE_SIZE_PTR=0,
5041 TTE_NFO=0,
5042 TTE_IE=0,
5043 TTE_Soft2=0,
5044 TTE_Diag=0,
5045 TTE_Soft=0,
5046 TTE_L=0,
5047 TTE_CP=1,
5048 TTE_CV=1,
5049 TTE_E=0,
5050 TTE_P=0,
5051 TTE_W=1,
5052 tsbonly
5053 }
5054
5055.data
5056.skip 1024
5057
5058
5059!------------------------------------------------------------------------
5060
5061SECTION tsotool_unshared_data
5062.global tsotool_unshared_data_start
5063.global res_buf_fp_p_0
5064.global res_buf_int_p_0
5065.global private_data_p0
5066.global stack_top_p0:
5067.global res_buf_fp_p_1
5068.global res_buf_int_p_1
5069.global private_data_p1
5070.global stack_top_p1:
5071.global res_buf_fp_p_2
5072.global res_buf_int_p_2
5073.global private_data_p2
5074.global stack_top_p2:
5075.global res_buf_fp_p_3
5076.global res_buf_int_p_3
5077.global private_data_p3
5078.global stack_top_p3:
5079.global res_buf_fp_p_4
5080.global res_buf_int_p_4
5081.global private_data_p4
5082.global stack_top_p4:
5083.global res_buf_fp_p_5
5084.global res_buf_int_p_5
5085.global private_data_p5
5086.global stack_top_p5:
5087.global res_buf_fp_p_6
5088.global res_buf_int_p_6
5089.global private_data_p6
5090.global stack_top_p6:
5091.global res_buf_fp_p_7
5092.global res_buf_int_p_7
5093.global private_data_p7
5094.global stack_top_p7:
5095.data
5096ALIGN_PAGE_512K
5097tsotool_unshared_data_start:
5098!-- label names of res_buf must match with extract_loads_m64.pl --
5099.align 64 ! for self bcopy()
5100res_buf_fp_p_0:
5101 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5102.align 64 ! for self bcopy()
5103res_buf_int_p_0:
5104 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5105.align 64 ! for self bcopy()
5106res_buf_fp_p_1:
5107 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5108.align 64 ! for self bcopy()
5109res_buf_int_p_1:
5110 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5111.align 64 ! for self bcopy()
5112res_buf_fp_p_2:
5113 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5114.align 64 ! for self bcopy()
5115res_buf_int_p_2:
5116 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5117.align 64 ! for self bcopy()
5118res_buf_fp_p_3:
5119 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5120.align 64 ! for self bcopy()
5121res_buf_int_p_3:
5122 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5123.align 64 ! for self bcopy()
5124res_buf_fp_p_4:
5125 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5126.align 64 ! for self bcopy()
5127res_buf_int_p_4:
5128 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5129.align 64 ! for self bcopy()
5130res_buf_fp_p_5:
5131 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5132.align 64 ! for self bcopy()
5133res_buf_int_p_5:
5134 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5135.align 64 ! for self bcopy()
5136res_buf_fp_p_6:
5137 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5138.align 64 ! for self bcopy()
5139res_buf_int_p_6:
5140 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5141.align 64 ! for self bcopy()
5142res_buf_fp_p_7:
5143 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5144.align 64 ! for self bcopy()
5145res_buf_int_p_7:
5146 .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2
5147private_data_p0:
5148 .skip PRIVATE_DATA_AREA_PER_CPU_RTL
5149private_data_p1:
5150 .skip PRIVATE_DATA_AREA_PER_CPU_RTL
5151private_data_p2:
5152 .skip PRIVATE_DATA_AREA_PER_CPU_RTL
5153private_data_p3:
5154 .skip PRIVATE_DATA_AREA_PER_CPU_RTL
5155private_data_p4:
5156 .skip PRIVATE_DATA_AREA_PER_CPU_RTL
5157private_data_p5:
5158 .skip PRIVATE_DATA_AREA_PER_CPU_RTL
5159private_data_p6:
5160 .skip PRIVATE_DATA_AREA_PER_CPU_RTL
5161private_data_p7:
5162 .skip PRIVATE_DATA_AREA_PER_CPU_RTL
5163stack_top_p0:
5164 .skip 2048
5165stack_top_p1:
5166 .skip 2048
5167stack_top_p2:
5168 .skip 2048
5169stack_top_p3:
5170 .skip 2048
5171stack_top_p4:
5172 .skip 2048
5173stack_top_p5:
5174 .skip 2048
5175stack_top_p6:
5176 .skip 2048
5177stack_top_p7:
5178 .skip 2048
5179tsotool_unshared_data_end:
5180ALIGN_PAGE_512K
5181! to prevent VAs from running over from this section into shared regions
5182
5183!------------------------------------------------------------------------
5184
5185.seg "data"
5186! 8 shared memory regions, 3 alias(es) each (Alias 0 is normal VA)
5187
5188
5189SECTION region0_alias0
5190.global REGION0_ALIAS0_START
5191.data
5192ALIGN_PAGE_8K
5193REGION0_ALIAS0_START:
5194 .skip REGION_MAPPED_SIZE_RTL
5195REGION0_ALIAS0_END:
5196 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5197
5198
5199SECTION region1_alias0
5200.global REGION1_ALIAS0_START
5201.data
5202ALIGN_PAGE_8K
5203REGION1_ALIAS0_START:
5204 .skip REGION_MAPPED_SIZE_RTL
5205REGION1_ALIAS0_END:
5206 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5207
5208
5209SECTION region2_alias0
5210.global REGION2_ALIAS0_START
5211.data
5212ALIGN_PAGE_8K
5213REGION2_ALIAS0_START:
5214 .skip REGION_MAPPED_SIZE_RTL
5215REGION2_ALIAS0_END:
5216 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5217
5218
5219SECTION region3_alias0
5220.global REGION3_ALIAS0_START
5221.data
5222ALIGN_PAGE_8K
5223REGION3_ALIAS0_START:
5224 .skip REGION_MAPPED_SIZE_RTL
5225REGION3_ALIAS0_END:
5226 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5227
5228
5229SECTION region4_alias0
5230.global REGION4_ALIAS0_START
5231.data
5232ALIGN_PAGE_8K
5233REGION4_ALIAS0_START:
5234 .skip REGION_MAPPED_SIZE_RTL
5235REGION4_ALIAS0_END:
5236 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5237
5238
5239SECTION region5_alias0
5240.global REGION5_ALIAS0_START
5241.data
5242ALIGN_PAGE_8K
5243REGION5_ALIAS0_START:
5244 .skip REGION_MAPPED_SIZE_RTL
5245REGION5_ALIAS0_END:
5246 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5247
5248
5249SECTION region6_alias0
5250.global REGION6_ALIAS0_START
5251.data
5252ALIGN_PAGE_8K
5253REGION6_ALIAS0_START:
5254 .skip REGION_MAPPED_SIZE_RTL
5255REGION6_ALIAS0_END:
5256 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5257
5258
5259SECTION region7_alias0
5260.global REGION7_ALIAS0_START
5261.data
5262ALIGN_PAGE_8K
5263REGION7_ALIAS0_START:
5264 .skip REGION_MAPPED_SIZE_RTL
5265REGION7_ALIAS0_END:
5266 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5267
5268
5269SECTION replacement0_alias0
5270.global REPLACEMENT0_ALIAS0_START
5271.data
5272ALIGN_PAGE_8K
5273REPLACEMENT0_ALIAS0_START:
5274 .skip REGION_MAPPED_SIZE_RTL
5275REPLACEMENT0_ALIAS0_END:
5276 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5277
5278
5279SECTION replacement1_alias0
5280.global REPLACEMENT1_ALIAS0_START
5281.data
5282ALIGN_PAGE_8K
5283REPLACEMENT1_ALIAS0_START:
5284 .skip REGION_MAPPED_SIZE_RTL
5285REPLACEMENT1_ALIAS0_END:
5286 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5287
5288
5289SECTION replacement2_alias0
5290.global REPLACEMENT2_ALIAS0_START
5291.data
5292ALIGN_PAGE_8K
5293REPLACEMENT2_ALIAS0_START:
5294 .skip REGION_MAPPED_SIZE_RTL
5295REPLACEMENT2_ALIAS0_END:
5296 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5297
5298
5299SECTION replacement3_alias0
5300.global REPLACEMENT3_ALIAS0_START
5301.data
5302ALIGN_PAGE_8K
5303REPLACEMENT3_ALIAS0_START:
5304 .skip REGION_MAPPED_SIZE_RTL
5305REPLACEMENT3_ALIAS0_END:
5306 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5307
5308
5309SECTION replacement4_alias0
5310.global REPLACEMENT4_ALIAS0_START
5311.data
5312ALIGN_PAGE_8K
5313REPLACEMENT4_ALIAS0_START:
5314 .skip REGION_MAPPED_SIZE_RTL
5315REPLACEMENT4_ALIAS0_END:
5316 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5317
5318
5319SECTION replacement5_alias0
5320.global REPLACEMENT5_ALIAS0_START
5321.data
5322ALIGN_PAGE_8K
5323REPLACEMENT5_ALIAS0_START:
5324 .skip REGION_MAPPED_SIZE_RTL
5325REPLACEMENT5_ALIAS0_END:
5326 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5327
5328
5329SECTION replacement6_alias0
5330.global REPLACEMENT6_ALIAS0_START
5331.data
5332ALIGN_PAGE_8K
5333REPLACEMENT6_ALIAS0_START:
5334 .skip REGION_MAPPED_SIZE_RTL
5335REPLACEMENT6_ALIAS0_END:
5336 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5337
5338
5339SECTION replacement7_alias0
5340.global REPLACEMENT7_ALIAS0_START
5341.data
5342ALIGN_PAGE_8K
5343REPLACEMENT7_ALIAS0_START:
5344 .skip REGION_MAPPED_SIZE_RTL
5345REPLACEMENT7_ALIAS0_END:
5346 .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL
5347
5348SECTION .MAIN
5349.global local_trap_handlers_start
5350.global local_trap_handlers_end.global extern_interrupt_handler
5351.text
5352ALIGN_PAGE_8K
5353local_trap_handlers_start:
5354
5355.align 64
5356extern_interrupt_handler:
5357stxa %g0, [%g0]ASI_INTR_RECEIVE
5358retry
5359
5360local_trap_handlers_end:
5361
5362SECTION .MAIN
5363.global main
5364.global tsotool_text_start
5365.global irepl_text_start
5366.text
5367ba user_text_start
5368nop
5369ALIGN_PAGE_64K
5370irepl_text_start:
5371 jmpl %g1+8, %g1
5372 nop
5373 .skip 24
5374 jmpl %g1+8, %g1
5375 nop
5376 .skip 24
5377 jmpl %g1+8, %g1
5378 nop
5379 .skip 24
5380 jmpl %g1+8, %g1
5381 nop
5382 .skip 24
5383 jmpl %g1+8, %g1
5384 nop
5385 .skip 24
5386 jmpl %g1+8, %g1
5387 nop
5388 .skip 24
5389 jmpl %g1+8, %g1
5390 nop
5391 .skip 24
5392 jmpl %g1+8, %g1
5393 nop
5394 .skip 24
5395 jmpl %g1+8, %g1
5396 nop
5397 .skip 24
5398 jmpl %g1+8, %g1
5399 nop
5400 .skip 24
5401 jmpl %g1+8, %g1
5402 nop
5403 .skip 24
5404 jmpl %g1+8, %g1
5405 nop
5406 .skip 24
5407 jmpl %g1+8, %g1
5408 nop
5409 .skip 24
5410 jmpl %g1+8, %g1
5411 nop
5412 .skip 24
5413 jmpl %g1+8, %g1
5414 nop
5415 .skip 24
5416 jmpl %g1+8, %g1
5417 nop
5418 .skip 24
5419 jmpl %g1+8, %g1
5420 nop
5421 .skip 24
5422 jmpl %g1+8, %g1
5423 nop
5424 .skip 24
5425 jmpl %g1+8, %g1
5426 nop
5427 .skip 24
5428 jmpl %g1+8, %g1
5429 nop
5430 .skip 24
5431 jmpl %g1+8, %g1
5432 nop
5433 .skip 24
5434 jmpl %g1+8, %g1
5435 nop
5436 .skip 24
5437 jmpl %g1+8, %g1
5438 nop
5439 .skip 24
5440 jmpl %g1+8, %g1
5441 nop
5442 .skip 24
5443 jmpl %g1+8, %g1
5444 nop
5445 .skip 24
5446 jmpl %g1+8, %g1
5447 nop
5448 .skip 24
5449 jmpl %g1+8, %g1
5450 nop
5451 .skip 24
5452 jmpl %g1+8, %g1
5453 nop
5454 .skip 24
5455 jmpl %g1+8, %g1
5456 nop
5457 .skip 24
5458 jmpl %g1+8, %g1
5459 nop
5460 .skip 24
5461 jmpl %g1+8, %g1
5462 nop
5463 .skip 24
5464 jmpl %g1+8, %g1
5465 nop
5466 .skip 24
5467 jmpl %g1+8, %g1
5468 nop
5469 .skip 24
5470 jmpl %g1+8, %g1
5471 nop
5472 .skip 24
5473 jmpl %g1+8, %g1
5474 nop
5475 .skip 24
5476 jmpl %g1+8, %g1
5477 nop
5478 .skip 24
5479 jmpl %g1+8, %g1
5480 nop
5481 .skip 24
5482 jmpl %g1+8, %g1
5483 nop
5484 .skip 24
5485 jmpl %g1+8, %g1
5486 nop
5487 .skip 24
5488 jmpl %g1+8, %g1
5489 nop
5490 .skip 24
5491 jmpl %g1+8, %g1
5492 nop
5493 .skip 24
5494 jmpl %g1+8, %g1
5495 nop
5496 .skip 24
5497 jmpl %g1+8, %g1
5498 nop
5499 .skip 24
5500 jmpl %g1+8, %g1
5501 nop
5502 .skip 24
5503 jmpl %g1+8, %g1
5504 nop
5505 .skip 24
5506 jmpl %g1+8, %g1
5507 nop
5508 .skip 24
5509 jmpl %g1+8, %g1
5510 nop
5511 .skip 24
5512 jmpl %g1+8, %g1
5513 nop
5514 .skip 24
5515 jmpl %g1+8, %g1
5516 nop
5517 .skip 24
5518 jmpl %g1+8, %g1
5519 nop
5520 .skip 24
5521 jmpl %g1+8, %g1
5522 nop
5523 .skip 24
5524 jmpl %g1+8, %g1
5525 nop
5526 .skip 24
5527 jmpl %g1+8, %g1
5528 nop
5529 .skip 24
5530 jmpl %g1+8, %g1
5531 nop
5532 .skip 24
5533 jmpl %g1+8, %g1
5534 nop
5535 .skip 24
5536 jmpl %g1+8, %g1
5537 nop
5538 .skip 24
5539 jmpl %g1+8, %g1
5540 nop
5541 .skip 24
5542 jmpl %g1+8, %g1
5543 nop
5544 .skip 24
5545 jmpl %g1+8, %g1
5546 nop
5547 .skip 24
5548 jmpl %g1+8, %g1
5549 nop
5550 .skip 24
5551 jmpl %g1+8, %g1
5552 nop
5553 .skip 24
5554 jmpl %g1+8, %g1
5555 nop
5556 .skip 24
5557 jmpl %g1+8, %g1
5558 nop
5559 .skip 24
5560 jmpl %g1+8, %g1
5561 nop
5562 .skip 24
5563 jmpl %g1+8, %g1
5564 nop
5565 .skip 24
5566 jmpl %g1+8, %g1
5567 nop
5568 .skip 24
5569 jmpl %g1+8, %g1
5570 nop
5571 .skip 24
5572 jmpl %g1+8, %g1
5573 nop
5574 .skip 24
5575 jmpl %g1+8, %g1
5576 nop
5577 .skip 24
5578 jmpl %g1+8, %g1
5579 nop
5580 .skip 24
5581 jmpl %g1+8, %g1
5582 nop
5583 .skip 24
5584 jmpl %g1+8, %g1
5585 nop
5586 .skip 24
5587 jmpl %g1+8, %g1
5588 nop
5589 .skip 24
5590 jmpl %g1+8, %g1
5591 nop
5592 .skip 24
5593 jmpl %g1+8, %g1
5594 nop
5595 .skip 24
5596 jmpl %g1+8, %g1
5597 nop
5598 .skip 24
5599 jmpl %g1+8, %g1
5600 nop
5601 .skip 24
5602 jmpl %g1+8, %g1
5603 nop
5604 .skip 24
5605 jmpl %g1+8, %g1
5606 nop
5607 .skip 24
5608 jmpl %g1+8, %g1
5609 nop
5610 .skip 24
5611 jmpl %g1+8, %g1
5612 nop
5613 .skip 24
5614 jmpl %g1+8, %g1
5615 nop
5616 .skip 24
5617 jmpl %g1+8, %g1
5618 nop
5619 .skip 24
5620 jmpl %g1+8, %g1
5621 nop
5622 .skip 24
5623 jmpl %g1+8, %g1
5624 nop
5625 .skip 24
5626 jmpl %g1+8, %g1
5627 nop
5628 .skip 24
5629 jmpl %g1+8, %g1
5630 nop
5631 .skip 24
5632 jmpl %g1+8, %g1
5633 nop
5634 .skip 24
5635 jmpl %g1+8, %g1
5636 nop
5637 .skip 24
5638 jmpl %g1+8, %g1
5639 nop
5640 .skip 24
5641 jmpl %g1+8, %g1
5642 nop
5643 .skip 24
5644 jmpl %g1+8, %g1
5645 nop
5646 .skip 24
5647 jmpl %g1+8, %g1
5648 nop
5649 .skip 24
5650 jmpl %g1+8, %g1
5651 nop
5652 .skip 24
5653 jmpl %g1+8, %g1
5654 nop
5655 .skip 24
5656 jmpl %g1+8, %g1
5657 nop
5658 .skip 24
5659 jmpl %g1+8, %g1
5660 nop
5661 .skip 24
5662 jmpl %g1+8, %g1
5663 nop
5664 .skip 24
5665 jmpl %g1+8, %g1
5666 nop
5667 .skip 24
5668 jmpl %g1+8, %g1
5669 nop
5670 .skip 24
5671 jmpl %g1+8, %g1
5672 nop
5673 .skip 24
5674 jmpl %g1+8, %g1
5675 nop
5676 .skip 24
5677 jmpl %g1+8, %g1
5678 nop
5679 .skip 24
5680 jmpl %g1+8, %g1
5681 nop
5682 .skip 24
5683 jmpl %g1+8, %g1
5684 nop
5685 .skip 24
5686 jmpl %g1+8, %g1
5687 nop
5688 .skip 24
5689 jmpl %g1+8, %g1
5690 nop
5691 .skip 24
5692 jmpl %g1+8, %g1
5693 nop
5694 .skip 24
5695 jmpl %g1+8, %g1
5696 nop
5697 .skip 24
5698 jmpl %g1+8, %g1
5699 nop
5700 .skip 24
5701 jmpl %g1+8, %g1
5702 nop
5703 .skip 24
5704 jmpl %g1+8, %g1
5705 nop
5706 .skip 24
5707 jmpl %g1+8, %g1
5708 nop
5709 .skip 24
5710 jmpl %g1+8, %g1
5711 nop
5712 .skip 24
5713 jmpl %g1+8, %g1
5714 nop
5715 .skip 24
5716 jmpl %g1+8, %g1
5717 nop
5718 .skip 24
5719 jmpl %g1+8, %g1
5720 nop
5721 .skip 24
5722 jmpl %g1+8, %g1
5723 nop
5724 .skip 24
5725 jmpl %g1+8, %g1
5726 nop
5727 .skip 24
5728 jmpl %g1+8, %g1
5729 nop
5730 .skip 24
5731 jmpl %g1+8, %g1
5732 nop
5733 .skip 24
5734 jmpl %g1+8, %g1
5735 nop
5736 .skip 24
5737 jmpl %g1+8, %g1
5738 nop
5739 .skip 24
5740 jmpl %g1+8, %g1
5741 nop
5742 .skip 24
5743 jmpl %g1+8, %g1
5744 nop
5745 .skip 24
5746 jmpl %g1+8, %g1
5747 nop
5748 .skip 24
5749 jmpl %g1+8, %g1
5750 nop
5751 .skip 24
5752 jmpl %g1+8, %g1
5753 nop
5754 .skip 24
5755 jmpl %g1+8, %g1
5756 nop
5757 .skip 24
5758ALIGN_PAGE_64K
5759user_text_start:
5760ba main
5761nop
5762user_text_end:
5763
5764ALIGN_PAGE_64K
5765tsotool_text_start:
5766main:
5767 mov 0, %o0
5768 mov 0, %o1
5769 CHECK_PROC_ID
5770! at this point, g1 should have CPU id (0, 1, 2, ...)
5771 set REGION0_ALIAS0_START, %o0 ! shared address 0
5772 set REGION1_ALIAS0_START, %o1 ! shared address 1
5773 cmp %g1, 0x7
5774 be setup_p7
5775 nop
5776 cmp %g1, 0x6
5777 be setup_p6
5778 nop
5779 cmp %g1, 0x5
5780 be setup_p5
5781 nop
5782 cmp %g1, 0x4
5783 be setup_p4
5784 nop
5785 cmp %g1, 0x3
5786 be setup_p3
5787 nop
5788 cmp %g1, 0x2
5789 be setup_p2
5790 nop
5791 cmp %g1, 0x1
5792 be setup_p1
5793 nop
5794 cmp %g1, 0x0
5795 be setup_p0
5796 nop
5797 EXIT_BAD ! Should never reach here
5798 nop
5799
5800setup_p0:
5801 setx stack_top_p0, %g1, %l1
5802 add %l1, 1024, %sp
5803 setx res_buf_fp_p_0, %g1, %o4
5804 setx private_data_p0, %g1, %o5
5805 setx func0, %g1, %l4
5806 call %l4
5807 nop
5808 EXIT_GOOD
5809 nop
5810
5811setup_p1:
5812 setx stack_top_p1, %g1, %l1
5813 add %l1, 1024, %sp
5814 setx res_buf_fp_p_1, %g1, %o4
5815 setx private_data_p1, %g1, %o5
5816 setx func1, %g1, %l4
5817 call %l4
5818 nop
5819 EXIT_GOOD
5820 nop
5821
5822setup_p2:
5823 setx stack_top_p2, %g1, %l1
5824 add %l1, 1024, %sp
5825 setx res_buf_fp_p_2, %g1, %o4
5826 setx private_data_p2, %g1, %o5
5827 setx func2, %g1, %l4
5828 call %l4
5829 nop
5830 EXIT_GOOD
5831 nop
5832
5833setup_p3:
5834 setx stack_top_p3, %g1, %l1
5835 add %l1, 1024, %sp
5836 setx res_buf_fp_p_3, %g1, %o4
5837 setx private_data_p3, %g1, %o5
5838 setx func3, %g1, %l4
5839 call %l4
5840 nop
5841 EXIT_GOOD
5842 nop
5843
5844setup_p4:
5845 setx stack_top_p4, %g1, %l1
5846 add %l1, 1024, %sp
5847 setx res_buf_fp_p_4, %g1, %o4
5848 setx private_data_p4, %g1, %o5
5849 setx func4, %g1, %l4
5850 call %l4
5851 nop
5852 EXIT_GOOD
5853 nop
5854
5855setup_p5:
5856 setx stack_top_p5, %g1, %l1
5857 add %l1, 1024, %sp
5858 setx res_buf_fp_p_5, %g1, %o4
5859 setx private_data_p5, %g1, %o5
5860 setx func5, %g1, %l4
5861 call %l4
5862 nop
5863 EXIT_GOOD
5864 nop
5865
5866setup_p6:
5867 setx stack_top_p6, %g1, %l1
5868 add %l1, 1024, %sp
5869 setx res_buf_fp_p_6, %g1, %o4
5870 setx private_data_p6, %g1, %o5
5871 setx func6, %g1, %l4
5872 call %l4
5873 nop
5874 EXIT_GOOD
5875 nop
5876
5877setup_p7:
5878 setx stack_top_p7, %g1, %l1
5879 add %l1, 1024, %sp
5880 setx res_buf_fp_p_7, %g1, %o4
5881 setx private_data_p7, %g1, %o5
5882 setx func7, %g1, %l4
5883 call %l4
5884 nop
5885 EXIT_GOOD
5886 nop
5887#define NO_REAL_CPUS_MINUS_1 7
5888
5889!-----------------
5890
5891! register usage:
5892! %i0 %i1 : base registers for first 2 regions
5893! %i2 %i3 : cache registers for 8 regions
5894! %i4 fixed pointer to per-cpu results area
5895! %l1 moving pointer to per-cpu FP results area
5896! %o7 moving pointer to per-cpu integer results area
5897! %i5 pointer to per-cpu private area
5898! %l0 holds lfsr, used as source of random bits
5899! %l2 loop count register
5900! %f16 running counter for unique fp store values
5901! %f17 holds increment value for fp counter
5902! %l4 running counter for unique integer store values (increment value is always 1)
5903! %l5 move-to register for load values (simulation only)
5904! %f30 move-to register for FP values (simulation only)
5905! %i4 holds the instructions count which is used for interrupt ordering
5906! %i4 holds the thread_id (OBP only)
5907! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage
5908! %l3 %l6 %l7 %o5 : 4 temporary registers
5909! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
5910! %f0-f15 FP results buffer registers
5911! %f32-f47 FP block load/store registers
5912
5913func0:
5914! instruction sequence begins
5915save %sp, -192, %sp
5916
5917! Force %i0-%i3 to be 64-byte aligned
5918add %i0, 63, %i0
5919andn %i0, 63, %i0
5920
5921add %i1, 63, %i1
5922andn %i1, 63, %i1
5923
5924add %i2, 63, %i2
5925andn %i2, 63, %i2
5926
5927add %i3, 63, %i3
5928andn %i3, 63, %i3
5929
5930add %i4, 63, %i4
5931andn %i4, 63, %i4
5932
5933add %i5, 63, %i5
5934andn %i5, 63, %i5
5935
5936
5937! Initialize pointer to FP load results area
5938mov %i4, %l1
5939
5940! Initialize pointer to integer load results area
5941sethi %hi(0x80000), %o7
5942or %o7, %lo(0x80000), %o7
5943add %o7, %l1, %o7
5944
5945! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info
5946mov 0x0, %i4
5947
5948! Initialize %f0-%f62 to 0xdeadbee0deadbee1
5949sethi %hi(0xdeadbee0), %l6
5950or %l6, %lo(0xdeadbee0), %l6
5951stw %l6, [%i5]
5952sethi %hi(0xdeadbee1), %l6
5953or %l6, %lo(0xdeadbee1), %l6
5954stw %l6, [%i5+4]
5955ldd [%i5], %f0
5956fmovd %f0, %f2
5957fmovd %f0, %f4
5958fmovd %f0, %f6
5959fmovd %f0, %f8
5960fmovd %f0, %f10
5961fmovd %f0, %f12
5962fmovd %f0, %f14
5963fmovd %f0, %f16
5964fmovd %f0, %f18
5965fmovd %f0, %f20
5966fmovd %f0, %f22
5967fmovd %f0, %f24
5968fmovd %f0, %f26
5969fmovd %f0, %f28
5970fmovd %f0, %f30
5971fmovd %f0, %f32
5972fmovd %f0, %f34
5973fmovd %f0, %f36
5974fmovd %f0, %f38
5975fmovd %f0, %f40
5976fmovd %f0, %f42
5977fmovd %f0, %f44
5978fmovd %f0, %f46
5979fmovd %f0, %f48
5980fmovd %f0, %f50
5981fmovd %f0, %f52
5982fmovd %f0, %f54
5983fmovd %f0, %f56
5984fmovd %f0, %f58
5985fmovd %f0, %f60
5986fmovd %f0, %f62
5987
5988! Signature for extract_loads script to start extracting load values for this stream
5989sethi %hi(0x00deade1), %l6
5990or %l6, %lo(0x00deade1), %l6
5991stw %l6, [%i5]
5992ld [%i5], %f16
5993
5994! Initialize running integer counter in register %l4
5995sethi %hi(0x1), %l4
5996or %l4, %lo(0x1), %l4
5997
5998! Initialize running FP counter in register %f16
5999sethi %hi(0x3f800001), %l6
6000or %l6, %lo(0x3f800001), %l6
6001stw %l6, [%i5]
6002ld [%i5], %f16
6003
6004! Initialize FP counter increment value in register %f17 (constant)
6005sethi %hi(0x34000000), %l6
6006or %l6, %lo(0x34000000), %l6
6007stw %l6, [%i5]
6008ld [%i5], %f17
6009
6010! Initialize LFSR to 0x2bbb^4
6011sethi %hi(0x2bbb), %l0
6012or %l0, %lo(0x2bbb), %l0
6013mulx %l0, %l0, %l0
6014mulx %l0, %l0, %l0
6015
6016BEGIN_NODES0: ! Test instruction sequence for ISTREAM 0 begins
6017
6018P1: !_DWLD [6] (Int) (Loop entry) (Branch target of P176)
6019sethi %hi(0x1), %l2
6020or %l2, %lo(0x1), %l2
6021loop_entry_0_0:
6022sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
6023add %i0, %i3, %i3
6024ldx [%i3 + 0], %o0
6025! move %o0(upper) -> %o0(upper)
6026! move %o0(lower) -> %o0(lower)
6027ba P2
6028nop
6029
6030TARGET176:
6031ba RET176
6032nop
6033
6034
6035P2: !_MEMBAR (FP) (CBR)
6036
6037! cbranch
6038andcc %l0, 1, %g0
6039be,pn %xcc, TARGET2
6040nop
6041RET2:
6042
6043! lfsr step begin
6044srlx %l0, 1, %l3
6045xnor %l3, %l0, %l3
6046sllx %l3, 63, %l3
6047or %l3, %l0, %l0
6048srlx %l0, 1, %l0
6049
6050
6051P3: !_BSTC [4] (maybe <- 0x3f800001) (FP)
6052wr %g0, 0xe0, %asi
6053! preparing store val #0, next val will be in f32
6054fmovs %f16, %f20
6055fadds %f16, %f17, %f16
6056! preparing store val #1, next val will be in f33
6057fmovs %f16, %f21
6058fadds %f16, %f17, %f16
6059! preparing store val #2, next val will be in f35
6060fmovd %f20, %f32
6061fmovs %f16, %f21
6062fadds %f16, %f17, %f16
6063fmovd %f20, %f34
6064membar #Sync
6065stda %f32, [%i1 + 0 ] %asi
6066
6067P4: !_MEMBAR (FP)
6068membar #StoreLoad
6069
6070P5: !_DWLD [13] (Int)
6071sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
6072add %i0, %i2, %i2
6073ldx [%i2 + 0], %o1
6074! move %o1(upper) -> %o1(upper)
6075! move %o1(lower) -> %o1(lower)
6076
6077P6: !_DWLD [18] (Int)
6078sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
6079add %i0, %i3, %i3
6080ldx [%i3 + 0], %o2
6081! move %o2(upper) -> %o2(upper)
6082! move %o2(lower) -> %o2(lower)
6083
6084P7: !_MEMBAR (FP)
6085
6086P8: !_BST [6] (maybe <- 0x3f800004) (FP)
6087wr %g0, 0xf0, %asi
6088sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
6089add %i0, %i2, %i2
6090! preparing store val #0, next val will be in f32
6091fmovs %f16, %f20
6092fadds %f16, %f17, %f16
6093! preparing store val #1, next val will be in f33
6094fmovs %f16, %f21
6095fadds %f16, %f17, %f16
6096! preparing store val #2, next val will be in f35
6097fmovd %f20, %f32
6098fmovs %f16, %f21
6099fadds %f16, %f17, %f16
6100fmovd %f20, %f34
6101membar #Sync
6102stda %f32, [%i2 + 0 ] %asi
6103
6104P9: !_MEMBAR (FP)
6105membar #StoreLoad
6106
6107P10: !_LD [10] (Int)
6108sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
6109add %i0, %i3, %i3
6110lduw [%i3 + 4], %o3
6111! move %o3(lower) -> %o3(upper)
6112sllx %o3, 32, %o3
6113
6114P11: !_LD [11] (Int)
6115lduw [%i3 + 12], %l7
6116! move %l7(lower) -> %o3(lower)
6117or %l7, %o3, %o3
6118
6119P12: !_DWST_BINIT [8] (maybe <- 0x1) (Int)
6120wr %g0, 0xe2, %asi
6121mov %l4, %o5
6122stxa %o5, [%i2 + 8] %asi
6123add %l4, 1, %l4
6124
6125P13: !_MEMBAR (Int)
6126membar #StoreLoad
6127
6128P14: !_DWST_BINIT [8] (maybe <- 0x2) (Int)
6129wr %g0, 0xe2, %asi
6130mov %l4, %l7
6131stxa %l7, [%i2 + 8] %asi
6132add %l4, 1, %l4
6133
6134P15: !_MEMBAR (Int)
6135membar #StoreLoad
6136
6137P16: !_DWST [17] (maybe <- 0x3) (Int)
6138sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
6139add %i0, %i2, %i2
6140mov %l4, %l6
6141stx %l6, [%i2 + 8]
6142add %l4, 1, %l4
6143
6144P17: !_SWAP [20] (maybe <- 0x4) (Int)
6145sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
6146add %i0, %i3, %i3
6147mov %l4, %o4
6148swap [%i3 + 12], %o4
6149! move %o4(lower) -> %o4(upper)
6150sllx %o4, 32, %o4
6151add %l4, 1, %l4
6152
6153P18: !_ST [5] (maybe <- 0x5) (Int)
6154stw %l4, [%i1 + 12 ]
6155add %l4, 1, %l4
6156
6157P19: !_CAS [8] (maybe <- 0x6) (Int) (Branch target of P129)
6158sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
6159add %i0, %i2, %i2
6160add %i2, 12, %o5
6161lduw [%o5], %l6
6162mov %l6, %l7
6163! move %l7(lower) -> %o4(lower)
6164or %l7, %o4, %o4
6165!---- flushing int results buffer----
6166mov %o0, %l5
6167mov %o1, %l5
6168mov %o2, %l5
6169mov %o3, %l5
6170mov %o4, %l5
6171mov %l4, %o0
6172cas [%o5], %l7, %o0
6173! move %o0(lower) -> %o0(upper)
6174sllx %o0, 32, %o0
6175add %l4, 1, %l4
6176ba P20
6177nop
6178
6179TARGET129:
6180ba RET129
6181nop
6182
6183
6184P20: !_MEMBAR (FP)
6185
6186P21: !_BSTC [8] (maybe <- 0x3f800007) (FP)
6187wr %g0, 0xe0, %asi
6188! preparing store val #0, next val will be in f32
6189fmovs %f16, %f20
6190fadds %f16, %f17, %f16
6191! preparing store val #1, next val will be in f33
6192fmovs %f16, %f21
6193fadds %f16, %f17, %f16
6194! preparing store val #2, next val will be in f35
6195fmovd %f20, %f32
6196fmovs %f16, %f21
6197fadds %f16, %f17, %f16
6198fmovd %f20, %f34
6199membar #Sync
6200stda %f32, [%i2 + 0 ] %asi
6201
6202P22: !_MEMBAR (FP)
6203membar #StoreLoad
6204
6205P23: !_BLD [5] (FP) (CBR)
6206wr %g0, 0xf0, %asi
6207ldda [%i1 + 0] %asi, %f0
6208membar #Sync
6209! 3 addresses covered
6210fmovs %f3, %f2
6211
6212! cbranch
6213andcc %l0, 1, %g0
6214be,pn %xcc, TARGET23
6215nop
6216RET23:
6217
6218! lfsr step begin
6219srlx %l0, 1, %l6
6220xnor %l6, %l0, %l6
6221sllx %l6, 63, %l6
6222or %l6, %l0, %l0
6223srlx %l0, 1, %l0
6224
6225
6226P24: !_MEMBAR (FP)
6227
6228P25: !_BSTC [23] (maybe <- 0x3f80000a) (FP)
6229wr %g0, 0xe0, %asi
6230sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
6231add %i0, %i3, %i3
6232! preparing store val #0, next val will be in f32
6233fmovs %f16, %f20
6234fadds %f16, %f17, %f16
6235! preparing store val #1, next val will be in f33
6236fmovs %f16, %f21
6237fadds %f16, %f17, %f16
6238! preparing store val #2, next val will be in f35
6239fmovd %f20, %f32
6240fmovs %f16, %f21
6241fadds %f16, %f17, %f16
6242fmovd %f20, %f34
6243membar #Sync
6244stda %f32, [%i3 + 0 ] %asi
6245
6246P26: !_MEMBAR (FP)
6247membar #StoreLoad
6248
6249P27: !_PREFETCH [6] (Int)
6250prefetch [%i2 + 0], 22
6251
6252P28: !_MEMBAR (FP)
6253
6254P29: !_BST [23] (maybe <- 0x3f80000d) (FP)
6255wr %g0, 0xf0, %asi
6256! preparing store val #0, next val will be in f32
6257fmovs %f16, %f20
6258fadds %f16, %f17, %f16
6259! preparing store val #1, next val will be in f33
6260fmovs %f16, %f21
6261fadds %f16, %f17, %f16
6262! preparing store val #2, next val will be in f35
6263fmovd %f20, %f32
6264fmovs %f16, %f21
6265fadds %f16, %f17, %f16
6266fmovd %f20, %f34
6267membar #Sync
6268stda %f32, [%i3 + 0 ] %asi
6269
6270P30: !_MEMBAR (FP)
6271membar #StoreLoad
6272
6273P31: !_LD [8] (Int)
6274lduw [%i2 + 12], %l6
6275! move %l6(lower) -> %o0(lower)
6276or %l6, %o0, %o0
6277
6278P32: !_PREFETCH [14] (Int)
6279sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
6280add %i0, %i2, %i2
6281prefetch [%i2 + 12], 4
6282
6283P33: !_LDD [15] (Int)
6284sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
6285add %i0, %i3, %i3
6286ldd [%i3 + 0], %l6
6287! move %l6(lower) -> %o1(upper)
6288sllx %l6, 32, %o1
6289! move %l7(lower) -> %o1(lower)
6290or %l7, %o1, %o1
6291
6292P34: !_MEMBAR (FP)
6293membar #StoreLoad
6294
6295P35: !_BLD [7] (FP)
6296wr %g0, 0xf0, %asi
6297sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
6298add %i0, %i2, %i2
6299ldda [%i2 + 0] %asi, %f32
6300membar #Sync
6301! 3 addresses covered
6302fmovd %f32, %f18
6303fmovs %f18, %f3
6304fmovs %f19, %f4
6305fmovd %f34, %f18
6306fmovs %f19, %f5
6307
6308P36: !_MEMBAR (FP)
6309
6310P37: !_DWLD [8] (Int)
6311ldx [%i2 + 8], %o2
6312! move %o2(lower) -> %o2(upper)
6313sllx %o2, 32, %o2
6314
6315P38: !_SWAP [17] (maybe <- 0x7) (Int)
6316mov %l4, %l3
6317swap [%i3 + 12], %l3
6318! move %l3(lower) -> %o2(lower)
6319srl %l3, 0, %l7
6320or %l7, %o2, %o2
6321add %l4, 1, %l4
6322
6323P39: !_CASX [18] (maybe <- 0x8) (Int)
6324sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
6325add %i0, %i3, %i3
6326ldx [%i3], %o3
6327! move %o3(upper) -> %o3(upper)
6328! move %o3(lower) -> %o3(lower)
6329mov %o3, %l6
6330sllx %l4, 32, %o4
6331add %l4, 1, %l4
6332or %l4, %o4, %o4
6333casx [%i3], %l6, %o4
6334! move %o4(upper) -> %o4(upper)
6335! move %o4(lower) -> %o4(lower)
6336!---- flushing int results buffer----
6337mov %o0, %l5
6338mov %o1, %l5
6339mov %o2, %l5
6340mov %o3, %l5
6341mov %o4, %l5
6342add %l4, 1, %l4
6343
6344P40: !_SWAP [23] (maybe <- 0xa) (Int)
6345sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
6346add %i0, %i2, %i2
6347mov %l4, %o0
6348swap [%i2 + 12], %o0
6349! move %o0(lower) -> %o0(upper)
6350sllx %o0, 32, %o0
6351add %l4, 1, %l4
6352
6353P41: !_CASX [1] (maybe <- 0xb) (Int)
6354ldx [%i0], %o5
6355! move %o5(upper) -> %o0(lower)
6356srlx %o5, 32, %l3
6357or %l3, %o0, %o0
6358! move %o5(lower) -> %o1(upper)
6359sllx %o5, 32, %o1
6360mov %o5, %l3
6361sllx %l4, 32, %o5
6362add %l4, 1, %l4
6363or %l4, %o5, %o5
6364casx [%i0], %l3, %o5
6365! move %o5(upper) -> %o1(lower)
6366srlx %o5, 32, %l3
6367or %l3, %o1, %o1
6368! move %o5(lower) -> %o2(upper)
6369sllx %o5, 32, %o2
6370add %l4, 1, %l4
6371
6372P42: !_CAS [16] (maybe <- 0xd) (Int)
6373sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
6374add %i0, %i3, %i3
6375add %i3, 4, %l6
6376lduw [%l6], %o5
6377mov %o5, %l3
6378! move %l3(lower) -> %o2(lower)
6379or %l3, %o2, %o2
6380mov %l4, %o3
6381cas [%l6], %l3, %o3
6382! move %o3(lower) -> %o3(upper)
6383sllx %o3, 32, %o3
6384add %l4, 1, %l4
6385
6386P43: !_LDD [18] (Int)
6387sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
6388add %i0, %i2, %i2
6389ldd [%i2 + 0], %l6
6390! move %l6(lower) -> %o3(lower)
6391or %l6, %o3, %o3
6392! move %l7(lower) -> %o4(upper)
6393sllx %l7, 32, %o4
6394
6395P44: !_LD [13] (Int)
6396sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
6397add %i0, %i3, %i3
6398lduw [%i3 + 4], %l6
6399! move %l6(lower) -> %o4(lower)
6400or %l6, %o4, %o4
6401!---- flushing int results buffer----
6402mov %o0, %l5
6403mov %o1, %l5
6404mov %o2, %l5
6405mov %o3, %l5
6406mov %o4, %l5
6407
6408P45: !_MEMBAR (FP)
6409
6410P46: !_BST [9] (maybe <- 0x3f800010) (FP)
6411wr %g0, 0xf0, %asi
6412sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
6413add %i0, %i2, %i2
6414! preparing store val #0, next val will be in f32
6415fmovs %f16, %f20
6416fadds %f16, %f17, %f16
6417! preparing store val #1, next val will be in f33
6418fmovs %f16, %f21
6419fadds %f16, %f17, %f16
6420! preparing store val #2, next val will be in f35
6421fmovd %f20, %f32
6422fmovs %f16, %f21
6423fadds %f16, %f17, %f16
6424fmovd %f20, %f34
6425membar #Sync
6426stda %f32, [%i2 + 0 ] %asi
6427
6428P47: !_MEMBAR (FP)
6429membar #StoreLoad
6430
6431P48: !_DWST [8] (maybe <- 0xe) (Int)
6432sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
6433add %i0, %i3, %i3
6434mov %l4, %l6
6435stx %l6, [%i3 + 8]
6436add %l4, 1, %l4
6437
6438P49: !_MEMBAR (FP)
6439
6440P50: !_BST [9] (maybe <- 0x3f800013) (FP)
6441wr %g0, 0xf0, %asi
6442! preparing store val #0, next val will be in f32
6443fmovs %f16, %f20
6444fadds %f16, %f17, %f16
6445! preparing store val #1, next val will be in f33
6446fmovs %f16, %f21
6447fadds %f16, %f17, %f16
6448! preparing store val #2, next val will be in f35
6449fmovd %f20, %f32
6450fmovs %f16, %f21
6451fadds %f16, %f17, %f16
6452fmovd %f20, %f34
6453membar #Sync
6454stda %f32, [%i2 + 0 ] %asi
6455
6456P51: !_MEMBAR (FP)
6457membar #StoreLoad
6458
6459P52: !_DWST_BINIT [3] (maybe <- 0xf) (Int)
6460wr %g0, 0xe2, %asi
6461sllx %l4, 32, %o5
6462add %l4, 1, %l4
6463or %o5, %l4, %o5
6464stxa %o5, [%i1 + 0] %asi
6465add %l4, 1, %l4
6466
6467P53: !_MEMBAR (Int)
6468
6469P54: !_BSTC [2] (maybe <- 0x3f800016) (FP)
6470wr %g0, 0xe0, %asi
6471! preparing store val #0, next val will be in f32
6472fmovs %f16, %f20
6473fadds %f16, %f17, %f16
6474! preparing store val #1, next val will be in f33
6475fmovs %f16, %f21
6476fadds %f16, %f17, %f16
6477! preparing store val #2, next val will be in f35
6478fmovd %f20, %f32
6479fmovs %f16, %f21
6480fadds %f16, %f17, %f16
6481fmovd %f20, %f34
6482membar #Sync
6483stda %f32, [%i0 + 0 ] %asi
6484
6485P55: !_MEMBAR (FP)
6486
6487P56: !_BSTC [14] (maybe <- 0x3f800019) (FP)
6488wr %g0, 0xe0, %asi
6489sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
6490add %i0, %i2, %i2
6491! preparing store val #0, next val will be in f32
6492fmovs %f16, %f20
6493fadds %f16, %f17, %f16
6494! preparing store val #1, next val will be in f33
6495fmovs %f16, %f21
6496fadds %f16, %f17, %f16
6497! preparing store val #2, next val will be in f35
6498fmovd %f20, %f32
6499fmovs %f16, %f21
6500fadds %f16, %f17, %f16
6501fmovd %f20, %f34
6502membar #Sync
6503stda %f32, [%i2 + 0 ] %asi
6504
6505P57: !_MEMBAR (FP)
6506membar #StoreLoad
6507
6508P58: !_BLD [8] (FP)
6509wr %g0, 0xf0, %asi
6510ldda [%i3 + 0] %asi, %f32
6511membar #Sync
6512! 3 addresses covered
6513fmovd %f32, %f6
6514fmovd %f34, %f18
6515fmovs %f19, %f8
6516
6517P59: !_MEMBAR (FP)
6518
6519P60: !_PREFETCH [18] (Int)
6520sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
6521add %i0, %i3, %i3
6522prefetch [%i3 + 0], 3
6523
6524P61: !_REPLACEMENT [20] (Int)
6525sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
6526sub %i0, %i2, %i2
6527sethi %hi(0x20000), %l3
6528ld [%i2+12], %l7
6529st %l7, [%i2+12]
6530add %i2, %l3, %l6
6531ld [%l6+12], %l7
6532st %l7, [%l6+12]
6533add %l6, %l3, %l6
6534ld [%l6+12], %l7
6535st %l7, [%l6+12]
6536add %l6, %l3, %l6
6537ld [%l6+12], %l7
6538st %l7, [%l6+12]
6539add %l6, %l3, %l6
6540ld [%l6+12], %l7
6541st %l7, [%l6+12]
6542add %l6, %l3, %l6
6543ld [%l6+12], %l7
6544st %l7, [%l6+12]
6545add %l6, %l3, %l6
6546ld [%l6+12], %l7
6547st %l7, [%l6+12]
6548add %l6, %l3, %l6
6549ld [%l6+12], %l7
6550st %l7, [%l6+12]
6551
6552P62: !_MEMBAR (FP)
6553
6554P63: !_BST [12] (maybe <- 0x3f80001c) (FP)
6555wr %g0, 0xf0, %asi
6556sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
6557add %i0, %i3, %i3
6558! preparing store val #0, next val will be in f32
6559fmovs %f16, %f20
6560fadds %f16, %f17, %f16
6561! preparing store val #1, next val will be in f33
6562fmovs %f16, %f21
6563fadds %f16, %f17, %f16
6564! preparing store val #2, next val will be in f35
6565fmovd %f20, %f32
6566fmovs %f16, %f21
6567fadds %f16, %f17, %f16
6568fmovd %f20, %f34
6569membar #Sync
6570stda %f32, [%i3 + 0 ] %asi
6571
6572P64: !_MEMBAR (FP)
6573membar #StoreLoad
6574
6575P65: !_DWST_BINIT [23] (maybe <- 0x11) (Int)
6576wr %g0, 0xe2, %asi
6577sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
6578add %i0, %i2, %i2
6579mov %l4, %o5
6580stxa %o5, [%i2 + 8] %asi
6581add %l4, 1, %l4
6582
6583P66: !_MEMBAR (Int)
6584membar #StoreLoad
6585
6586P67: !_CAS [4] (maybe <- 0x12) (Int)
6587add %i1, 4, %o5
6588lduw [%o5], %o0
6589mov %o0, %l7
6590! move %l7(lower) -> %o0(upper)
6591sllx %l7, 32, %o0
6592mov %l4, %l6
6593cas [%o5], %l7, %l6
6594! move %l6(lower) -> %o0(lower)
6595srl %l6, 0, %l7
6596or %l7, %o0, %o0
6597add %l4, 1, %l4
6598
6599P68: !_ST [3] (maybe <- 0x13) (Int)
6600stw %l4, [%i1 + 0 ]
6601add %l4, 1, %l4
6602
6603P69: !_REPLACEMENT [4] (Int)
6604sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
6605sub %i0, %i3, %i3
6606sethi %hi(0x20000), %l6
6607ld [%i3+4], %o5
6608st %o5, [%i3+4]
6609add %i3, %l6, %l7
6610ld [%l7+4], %o5
6611st %o5, [%l7+4]
6612add %l7, %l6, %l7
6613ld [%l7+4], %o5
6614st %o5, [%l7+4]
6615add %l7, %l6, %l7
6616ld [%l7+4], %o5
6617st %o5, [%l7+4]
6618add %l7, %l6, %l7
6619ld [%l7+4], %o5
6620st %o5, [%l7+4]
6621add %l7, %l6, %l7
6622ld [%l7+4], %o5
6623st %o5, [%l7+4]
6624add %l7, %l6, %l7
6625ld [%l7+4], %o5
6626st %o5, [%l7+4]
6627add %l7, %l6, %l7
6628ld [%l7+4], %o5
6629st %o5, [%l7+4]
6630
6631P70: !_MEMBAR (FP)
6632membar #StoreLoad
6633
6634P71: !_BLD [3] (FP)
6635wr %g0, 0xf0, %asi
6636ldda [%i1 + 0] %asi, %f32
6637membar #Sync
6638! 3 addresses covered
6639fmovd %f32, %f18
6640fmovs %f18, %f9
6641fmovs %f19, %f10
6642fmovd %f34, %f18
6643fmovs %f19, %f11
6644
6645P72: !_MEMBAR (FP)
6646
6647P73: !_ST [7] (maybe <- 0x14) (Int) (LE)
6648wr %g0, 0x88, %asi
6649sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
6650add %i0, %i2, %i2
6651! Change single-word-level endianess (big endian <-> little endian)
6652sethi %hi(0xff00ff00), %l6
6653or %l6, %lo(0xff00ff00), %l6
6654and %l4, %l6, %l7
6655srl %l7, 8, %l7
6656sll %l4, 8, %l3
6657and %l3, %l6, %l3
6658or %l3, %l7, %l3
6659srl %l3, 16, %l7
6660sll %l3, 16, %l3
6661srl %l3, 0, %l3
6662or %l3, %l7, %l3
6663stwa %l3, [%i2 + 4] %asi
6664add %l4, 1, %l4
6665
6666P74: !_DWST [0] (maybe <- 0x15) (Int)
6667sllx %l4, 32, %o5
6668add %l4, 1, %l4
6669or %o5, %l4, %o5
6670stx %o5, [%i0 + 0]
6671add %l4, 1, %l4
6672
6673P75: !_CASX [8] (maybe <- 0x17) (Int)
6674add %i2, 8, %o5
6675ldx [%o5], %o1
6676! move %o1(upper) -> %o1(upper)
6677! move %o1(lower) -> %o1(lower)
6678mov %o1, %l7
6679mov %l4, %o2
6680casx [%o5], %l7, %o2
6681! move %o2(upper) -> %o2(upper)
6682! move %o2(lower) -> %o2(lower)
6683add %l4, 1, %l4
6684
6685P76: !_SWAP [11] (maybe <- 0x18) (Int)
6686sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
6687add %i0, %i3, %i3
6688mov %l4, %o3
6689swap [%i3 + 12], %o3
6690! move %o3(lower) -> %o3(upper)
6691sllx %o3, 32, %o3
6692add %l4, 1, %l4
6693
6694P77: !_LD [19] (Int)
6695sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
6696add %i0, %i2, %i2
6697lduw [%i2 + 4], %l7
6698! move %l7(lower) -> %o3(lower)
6699or %l7, %o3, %o3
6700
6701P78: !_SWAP [1] (maybe <- 0x19) (Int)
6702mov %l4, %o4
6703swap [%i0 + 4], %o4
6704! move %o4(lower) -> %o4(upper)
6705sllx %o4, 32, %o4
6706add %l4, 1, %l4
6707
6708P79: !_DWST [0] (maybe <- 0x1a) (Int)
6709sllx %l4, 32, %l7
6710add %l4, 1, %l4
6711or %l7, %l4, %l7
6712stx %l7, [%i0 + 0]
6713add %l4, 1, %l4
6714
6715P80: !_CAS [0] (maybe <- 0x1c) (Int)
6716lduw [%i0], %l3
6717mov %l3, %l6
6718! move %l6(lower) -> %o4(lower)
6719or %l6, %o4, %o4
6720!---- flushing int results buffer----
6721mov %o0, %l5
6722mov %o1, %l5
6723mov %o2, %l5
6724mov %o3, %l5
6725mov %o4, %l5
6726mov %l4, %o0
6727cas [%i0], %l6, %o0
6728! move %o0(lower) -> %o0(upper)
6729sllx %o0, 32, %o0
6730add %l4, 1, %l4
6731
6732P81: !_ST_BINIT [23] (maybe <- 0x1d) (Int)
6733wr %g0, 0xe2, %asi
6734sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
6735add %i0, %i3, %i3
6736stwa %l4, [%i3 + 12] %asi
6737add %l4, 1, %l4
6738
6739P82: !_MEMBAR (Int)
6740membar #StoreLoad
6741
6742P83: !_CAS [6] (maybe <- 0x1e) (Int)
6743sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
6744add %i0, %i2, %i2
6745lduw [%i2], %o5
6746mov %o5, %l3
6747! move %l3(lower) -> %o0(lower)
6748or %l3, %o0, %o0
6749mov %l4, %o1
6750cas [%i2], %l3, %o1
6751! move %o1(lower) -> %o1(upper)
6752sllx %o1, 32, %o1
6753add %l4, 1, %l4
6754
6755P84: !_CASX [6] (maybe <- 0x1f) (Int)
6756ldx [%i2], %o5
6757! move %o5(upper) -> %o1(lower)
6758srlx %o5, 32, %l3
6759or %l3, %o1, %o1
6760! move %o5(lower) -> %o2(upper)
6761sllx %o5, 32, %o2
6762mov %o5, %l3
6763sllx %l4, 32, %o5
6764add %l4, 1, %l4
6765or %l4, %o5, %o5
6766casx [%i2], %l3, %o5
6767! move %o5(upper) -> %o2(lower)
6768srlx %o5, 32, %l3
6769or %l3, %o2, %o2
6770! move %o5(lower) -> %o3(upper)
6771sllx %o5, 32, %o3
6772add %l4, 1, %l4
6773
6774P85: !_DWLD [7] (Int)
6775ldx [%i2 + 0], %l6
6776! move %l6(upper) -> %o3(lower)
6777srlx %l6, 32, %l3
6778or %l3, %o3, %o3
6779! move %l6(lower) -> %o4(upper)
6780sllx %l6, 32, %o4
6781
6782P86: !_MEMBAR (FP)
6783
6784P87: !_BST [7] (maybe <- 0x3f80001f) (FP)
6785wr %g0, 0xf0, %asi
6786! preparing store val #0, next val will be in f32
6787fmovs %f16, %f20
6788fadds %f16, %f17, %f16
6789! preparing store val #1, next val will be in f33
6790fmovs %f16, %f21
6791fadds %f16, %f17, %f16
6792! preparing store val #2, next val will be in f35
6793fmovd %f20, %f32
6794fmovs %f16, %f21
6795fadds %f16, %f17, %f16
6796fmovd %f20, %f34
6797membar #Sync
6798stda %f32, [%i2 + 0 ] %asi
6799
6800P88: !_MEMBAR (FP)
6801membar #StoreLoad
6802
6803P89: !_BLD [7] (FP)
6804wr %g0, 0xf0, %asi
6805ldda [%i2 + 0] %asi, %f32
6806membar #Sync
6807! 3 addresses covered
6808fmovd %f32, %f12
6809fmovd %f34, %f18
6810fmovs %f19, %f14
6811
6812P90: !_MEMBAR (FP)
6813
6814P91: !_BST [21] (maybe <- 0x3f800022) (FP)
6815wr %g0, 0xf0, %asi
6816! preparing store val #0, next val will be in f32
6817fmovs %f16, %f20
6818fadds %f16, %f17, %f16
6819! preparing store val #1, next val will be in f33
6820fmovs %f16, %f21
6821fadds %f16, %f17, %f16
6822! preparing store val #2, next val will be in f35
6823fmovd %f20, %f32
6824fmovs %f16, %f21
6825fadds %f16, %f17, %f16
6826fmovd %f20, %f34
6827membar #Sync
6828stda %f32, [%i3 + 0 ] %asi
6829
6830P92: !_MEMBAR (FP)
6831membar #StoreLoad
6832
6833P93: !_LDD [23] (Int)
6834ldd [%i3 + 8], %l6
6835! move %l7(lower) -> %o4(lower)
6836or %l7, %o4, %o4
6837!---- flushing int results buffer----
6838mov %o0, %l5
6839mov %o1, %l5
6840mov %o2, %l5
6841mov %o3, %l5
6842mov %o4, %l5
6843
6844P94: !_LD [23] (Int) (LE)
6845wr %g0, 0x88, %asi
6846lduwa [%i3 + 12] %asi, %o0
6847! move %o0(lower) -> %o0(upper)
6848sllx %o0, 32, %o0
6849
6850P95: !_MEMBAR (FP) (Branch target of P846)
6851ba P96
6852nop
6853
6854TARGET846:
6855ba RET846
6856nop
6857
6858
6859P96: !_BST [4] (maybe <- 0x3f800025) (FP)
6860wr %g0, 0xf0, %asi
6861! preparing store val #0, next val will be in f32
6862fmovs %f16, %f20
6863fadds %f16, %f17, %f16
6864! preparing store val #1, next val will be in f33
6865fmovs %f16, %f21
6866fadds %f16, %f17, %f16
6867! preparing store val #2, next val will be in f35
6868fmovd %f20, %f32
6869fmovs %f16, %f21
6870fadds %f16, %f17, %f16
6871fmovd %f20, %f34
6872membar #Sync
6873stda %f32, [%i1 + 0 ] %asi
6874
6875P97: !_MEMBAR (FP)
6876membar #StoreLoad
6877
6878P98: !_ST_BINIT [0] (maybe <- 0x21) (Int)
6879wr %g0, 0xe2, %asi
6880stwa %l4, [%i0 + 0] %asi
6881add %l4, 1, %l4
6882
6883P99: !_MEMBAR (Int)
6884membar #StoreLoad
6885
6886P100: !_DWST [15] (maybe <- 0x22) (Int)
6887sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
6888add %i0, %i3, %i3
6889sllx %l4, 32, %l3
6890add %l4, 1, %l4
6891or %l3, %l4, %l3
6892stx %l3, [%i3 + 0]
6893add %l4, 1, %l4
6894
6895P101: !_DWST [23] (maybe <- 0x24) (Int) (LE)
6896wr %g0, 0x88, %asi
6897sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
6898add %i0, %i2, %i2
6899! Change single-word-level endianess (big endian <-> little endian)
6900sethi %hi(0xff00ff00), %o5
6901or %o5, %lo(0xff00ff00), %o5
6902and %l4, %o5, %l6
6903srl %l6, 8, %l6
6904sll %l4, 8, %l3
6905and %l3, %o5, %l3
6906or %l3, %l6, %l3
6907srl %l3, 16, %l6
6908sll %l3, 16, %l3
6909srl %l3, 0, %l3
6910or %l3, %l6, %l3
6911sllx %l3, 32, %l3
6912stxa %l3, [%i2 + 8 ] %asi
6913add %l4, 1, %l4
6914
6915P102: !_ST [16] (maybe <- 0x25) (Int)
6916stw %l4, [%i3 + 4 ]
6917add %l4, 1, %l4
6918
6919P103: !_PREFETCH [13] (Int)
6920sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
6921add %i0, %i3, %i3
6922prefetch [%i3 + 4], 23
6923
6924P104: !_SWAP [18] (maybe <- 0x26) (Int)
6925sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
6926add %i0, %i2, %i2
6927mov %l4, %o5
6928swap [%i2 + 0], %o5
6929! move %o5(lower) -> %o0(lower)
6930srl %o5, 0, %l6
6931or %l6, %o0, %o0
6932add %l4, 1, %l4
6933
6934P105: !_ST [2] (maybe <- 0x27) (Int)
6935stw %l4, [%i0 + 12 ]
6936add %l4, 1, %l4
6937
6938P106: !_DWST [20] (maybe <- 0x28) (Int)
6939mov %l4, %o5
6940stx %o5, [%i2 + 8]
6941add %l4, 1, %l4
6942
6943P107: !_DWST_BINIT [5] (maybe <- 0x29) (Int)
6944wr %g0, 0xe2, %asi
6945mov %l4, %l7
6946stxa %l7, [%i1 + 8] %asi
6947add %l4, 1, %l4
6948
6949P108: !_MEMBAR (Int)
6950membar #StoreLoad
6951
6952P109: !_ST [5] (maybe <- 0x2a) (Int)
6953stw %l4, [%i1 + 12 ]
6954add %l4, 1, %l4
6955
6956P110: !_ST [16] (maybe <- 0x2b) (Int)
6957sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
6958add %i0, %i3, %i3
6959stw %l4, [%i3 + 4 ]
6960add %l4, 1, %l4
6961
6962P111: !_REPLACEMENT [11] (Int)
6963sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
6964sub %i0, %i2, %i2
6965sethi %hi(0x20000), %o5
6966ld [%i2+12], %l6
6967st %l6, [%i2+12]
6968add %i2, %o5, %l3
6969ld [%l3+12], %l6
6970st %l6, [%l3+12]
6971add %l3, %o5, %l3
6972ld [%l3+12], %l6
6973st %l6, [%l3+12]
6974add %l3, %o5, %l3
6975ld [%l3+12], %l6
6976st %l6, [%l3+12]
6977add %l3, %o5, %l3
6978ld [%l3+12], %l6
6979st %l6, [%l3+12]
6980add %l3, %o5, %l3
6981ld [%l3+12], %l6
6982st %l6, [%l3+12]
6983add %l3, %o5, %l3
6984ld [%l3+12], %l6
6985st %l6, [%l3+12]
6986add %l3, %o5, %l3
6987ld [%l3+12], %l6
6988st %l6, [%l3+12]
6989
6990P112: !_PREFETCH [1] (Int) (CBR)
6991prefetch [%i0 + 4], 22
6992
6993! cbranch
6994andcc %l0, 1, %g0
6995be,pn %xcc, TARGET112
6996nop
6997RET112:
6998
6999! lfsr step begin
7000srlx %l0, 1, %l7
7001xnor %l7, %l0, %l7
7002sllx %l7, 63, %l7
7003or %l7, %l0, %l0
7004srlx %l0, 1, %l0
7005
7006
7007P113: !_DWST [22] (maybe <- 0x2c) (Int)
7008sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
7009add %i0, %i3, %i3
7010sllx %l4, 32, %o5
7011add %l4, 1, %l4
7012or %o5, %l4, %o5
7013stx %o5, [%i3 + 0]
7014add %l4, 1, %l4
7015
7016P114: !_CAS [2] (maybe <- 0x2e) (Int)
7017add %i0, 12, %o5
7018lduw [%o5], %o1
7019mov %o1, %l7
7020! move %l7(lower) -> %o1(upper)
7021sllx %l7, 32, %o1
7022mov %l4, %l6
7023cas [%o5], %l7, %l6
7024! move %l6(lower) -> %o1(lower)
7025srl %l6, 0, %l7
7026or %l7, %o1, %o1
7027add %l4, 1, %l4
7028
7029P115: !_ST_BINIT [21] (maybe <- 0x2f) (Int) (CBR)
7030wr %g0, 0xe2, %asi
7031stwa %l4, [%i3 + 0] %asi
7032add %l4, 1, %l4
7033
7034! cbranch
7035andcc %l0, 1, %g0
7036be,pn %xcc, TARGET115
7037nop
7038RET115:
7039
7040! lfsr step begin
7041srlx %l0, 1, %l6
7042xnor %l6, %l0, %l6
7043sllx %l6, 63, %l6
7044or %l6, %l0, %l0
7045srlx %l0, 1, %l0
7046
7047
7048P116: !_MEMBAR (Int)
7049membar #StoreLoad
7050
7051P117: !_CAS [13] (maybe <- 0x30) (Int)
7052sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
7053add %i0, %i2, %i2
7054add %i2, 4, %o5
7055lduw [%o5], %o2
7056mov %o2, %l7
7057! move %l7(lower) -> %o2(upper)
7058sllx %l7, 32, %o2
7059mov %l4, %l6
7060cas [%o5], %l7, %l6
7061! move %l6(lower) -> %o2(lower)
7062srl %l6, 0, %l7
7063or %l7, %o2, %o2
7064add %l4, 1, %l4
7065
7066P118: !_CAS [6] (maybe <- 0x31) (Int)
7067sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
7068add %i0, %i3, %i3
7069lduw [%i3], %o3
7070mov %o3, %l7
7071! move %l7(lower) -> %o3(upper)
7072sllx %l7, 32, %o3
7073mov %l4, %l6
7074cas [%i3], %l7, %l6
7075! move %l6(lower) -> %o3(lower)
7076srl %l6, 0, %l7
7077or %l7, %o3, %o3
7078add %l4, 1, %l4
7079
7080P119: !_CAS [1] (maybe <- 0x32) (Int) (LE)
7081! Change single-word-level endianess (big endian <-> little endian)
7082sethi %hi(0xff00ff00), %o5
7083or %o5, %lo(0xff00ff00), %o5
7084and %l4, %o5, %l7
7085srl %l7, 8, %l7
7086sll %l4, 8, %l3
7087and %l3, %o5, %l3
7088or %l3, %l7, %l3
7089srl %l3, 16, %l7
7090sll %l3, 16, %l3
7091srl %l3, 0, %l3
7092or %l3, %l7, %l3
7093wr %g0, 0x88, %asi
7094add %i0, 4, %o5
7095lduwa [%o5] %asi, %o4
7096mov %o4, %l7
7097! move %l7(lower) -> %o4(upper)
7098sllx %l7, 32, %o4
7099mov %l3, %l6
7100casa [%o5] %asi, %l7, %l6
7101! move %l6(lower) -> %o4(lower)
7102srl %l6, 0, %l7
7103or %l7, %o4, %o4
7104!---- flushing int results buffer----
7105mov %o0, %l5
7106mov %o1, %l5
7107mov %o2, %l5
7108mov %o3, %l5
7109mov %o4, %l5
7110add %l4, 1, %l4
7111
7112P120: !_SWAP [21] (maybe <- 0x33) (Int)
7113sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
7114add %i0, %i2, %i2
7115mov %l4, %o0
7116swap [%i2 + 0], %o0
7117! move %o0(lower) -> %o0(upper)
7118sllx %o0, 32, %o0
7119add %l4, 1, %l4
7120
7121P121: !_SWAP [2] (maybe <- 0x34) (Int)
7122mov %l4, %o5
7123swap [%i0 + 12], %o5
7124! move %o5(lower) -> %o0(lower)
7125srl %o5, 0, %l6
7126or %l6, %o0, %o0
7127add %l4, 1, %l4
7128
7129P122: !_CASX [15] (maybe <- 0x35) (Int) (LE)
7130sllx %l4, 32, %l6
7131add %l4, 1, %l4
7132or %l4, %l6, %l6
7133! Change double-word-level endianess (big endian <-> little endian)
7134sethi %hi(0xff00ff00), %l3
7135or %l3, %lo(0xff00ff00), %l3
7136sllx %l3, 32, %l7
7137or %l3, %l7, %l3
7138and %l6, %l3, %l7
7139srlx %l7, 8, %l7
7140sllx %l6, 8, %l6
7141and %l6, %l3, %l6
7142or %l6, %l7, %l6
7143sethi %hi(0xffff0000), %l3
7144srlx %l6, 16, %l7
7145andn %l7, %l3, %l7
7146andn %l6, %l3, %l6
7147sllx %l6, 16, %l6
7148or %l6, %l7, %l6
7149srlx %l6, 32, %l7
7150sllx %l6, 32, %l6
7151or %l6, %l7, %l7
7152wr %g0, 0x88, %asi
7153sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
7154add %i0, %i3, %i3
7155ldxa [%i3] %asi, %o5
7156! move %o5(lower) -> %o1(upper)
7157sllx %o5, 32, %o1
7158! move %o5(upper) -> %o1(lower)
7159srlx %o5, 32, %l3
7160or %l3, %o1, %o1
7161mov %o5, %l3
7162mov %l7, %o5
7163casxa [%i3] %asi, %l3, %o5
7164! move %o5(lower) -> %o2(upper)
7165sllx %o5, 32, %o2
7166! move %o5(upper) -> %o2(lower)
7167srlx %o5, 32, %l3
7168or %l3, %o2, %o2
7169add %l4, 1, %l4
7170
7171P123: !_SWAP [15] (maybe <- 0x37) (Int)
7172mov %l4, %o3
7173swap [%i3 + 0], %o3
7174! move %o3(lower) -> %o3(upper)
7175sllx %o3, 32, %o3
7176add %l4, 1, %l4
7177
7178P124: !_LDD [10] (Int)
7179sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
7180add %i0, %i2, %i2
7181ldd [%i2 + 0], %l6
7182! move %l6(lower) -> %o3(lower)
7183or %l6, %o3, %o3
7184! move %l7(lower) -> %o4(upper)
7185sllx %l7, 32, %o4
7186
7187P125: !_CASX [14] (maybe <- 0x38) (Int)
7188sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
7189add %i0, %i3, %i3
7190add %i3, 8, %l6
7191ldx [%l6], %o5
7192! move %o5(upper) -> %o4(lower)
7193srlx %o5, 32, %l3
7194or %l3, %o4, %o4
7195!---- flushing int results buffer----
7196mov %o0, %l5
7197mov %o1, %l5
7198mov %o2, %l5
7199mov %o3, %l5
7200mov %o4, %l5
7201! move %o5(lower) -> %o0(upper)
7202sllx %o5, 32, %o0
7203mov %o5, %l3
7204mov %l4, %o5
7205casx [%l6], %l3, %o5
7206! move %o5(upper) -> %o0(lower)
7207srlx %o5, 32, %l3
7208or %l3, %o0, %o0
7209! move %o5(lower) -> %o1(upper)
7210sllx %o5, 32, %o1
7211add %l4, 1, %l4
7212
7213P126: !_DWLD [1] (Int)
7214ldx [%i0 + 0], %l6
7215! move %l6(upper) -> %o1(lower)
7216srlx %l6, 32, %l3
7217or %l3, %o1, %o1
7218! move %l6(lower) -> %o2(upper)
7219sllx %l6, 32, %o2
7220
7221P127: !_CAS [18] (maybe <- 0x39) (Int) (LE)
7222! Change single-word-level endianess (big endian <-> little endian)
7223sethi %hi(0xff00ff00), %o5
7224or %o5, %lo(0xff00ff00), %o5
7225and %l4, %o5, %l7
7226srl %l7, 8, %l7
7227sll %l4, 8, %l3
7228and %l3, %o5, %l3
7229or %l3, %l7, %l3
7230srl %l3, 16, %l7
7231sll %l3, 16, %l3
7232srl %l3, 0, %l3
7233or %l3, %l7, %l3
7234wr %g0, 0x88, %asi
7235sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
7236add %i0, %i2, %i2
7237lduwa [%i2] %asi, %l6
7238mov %l6, %l7
7239! move %l7(lower) -> %o2(lower)
7240or %l7, %o2, %o2
7241mov %l3, %o3
7242casa [%i2] %asi, %l7, %o3
7243! move %o3(lower) -> %o3(upper)
7244sllx %o3, 32, %o3
7245add %l4, 1, %l4
7246
7247P128: !_CASX [4] (maybe <- 0x3a) (Int)
7248!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
7249!Logical addr: 4
7250
7251sethi %hi(0x200000), %l7
7252sub %i1, %l7, %i1
7253ldx [%i1], %l7
7254! move %l7(upper) -> %o3(lower)
7255srlx %l7, 32, %o5
7256or %o5, %o3, %o3
7257! move %l7(lower) -> %o4(upper)
7258sllx %l7, 32, %o4
7259mov %l7, %o5
7260sllx %l4, 32, %l7
7261add %l4, 1, %l4
7262or %l4, %l7, %l7
7263casx [%i1], %o5, %l7
7264! move %l7(upper) -> %o4(lower)
7265srlx %l7, 32, %o5
7266or %o5, %o4, %o4
7267!---- flushing int results buffer----
7268mov %o0, %l5
7269mov %o1, %l5
7270mov %o2, %l5
7271mov %o3, %l5
7272mov %o4, %l5
7273! move %l7(lower) -> %o0(upper)
7274sllx %l7, 32, %o0
7275add %l4, 1, %l4
7276
7277P129: !_CASX [3] (maybe <- 0x3c) (Int) (CBR)
7278ldx [%i1], %l7
7279! move %l7(upper) -> %o0(lower)
7280srlx %l7, 32, %o5
7281or %o5, %o0, %o0
7282! move %l7(lower) -> %o1(upper)
7283sllx %l7, 32, %o1
7284mov %l7, %o5
7285sllx %l4, 32, %l7
7286add %l4, 1, %l4
7287or %l4, %l7, %l7
7288casx [%i1], %o5, %l7
7289! move %l7(upper) -> %o1(lower)
7290srlx %l7, 32, %o5
7291or %o5, %o1, %o1
7292! move %l7(lower) -> %o2(upper)
7293sllx %l7, 32, %o2
7294add %l4, 1, %l4
7295
7296! cbranch
7297andcc %l0, 1, %g0
7298be,pn %xcc, TARGET129
7299nop
7300RET129:
7301
7302! lfsr step begin
7303srlx %l0, 1, %o5
7304xnor %o5, %l0, %o5
7305sllx %o5, 63, %o5
7306or %o5, %l0, %l0
7307srlx %l0, 1, %l0
7308
7309
7310P130: !_CAS [2] (maybe <- 0x3e) (Int)
7311add %i0, 12, %l6
7312lduw [%l6], %o5
7313mov %o5, %l3
7314! move %l3(lower) -> %o2(lower)
7315or %l3, %o2, %o2
7316mov %l4, %o3
7317cas [%l6], %l3, %o3
7318! move %o3(lower) -> %o3(upper)
7319sllx %o3, 32, %o3
7320add %l4, 1, %l4
7321
7322P131: !_ST_BINIT [6] (maybe <- 0x3f) (Int) (Branch target of P597)
7323wr %g0, 0xe2, %asi
7324sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
7325add %i0, %i3, %i3
7326stwa %l4, [%i3 + 0] %asi
7327add %l4, 1, %l4
7328ba P132
7329nop
7330
7331TARGET597:
7332ba RET597
7333nop
7334
7335
7336P132: !_MEMBAR (Int) (Branch target of P995)
7337membar #StoreLoad
7338ba P133
7339nop
7340
7341TARGET995:
7342ba RET995
7343nop
7344
7345
7346P133: !_PREFETCH [23] (Int) (CBR)
7347sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
7348add %i0, %i2, %i2
7349prefetch [%i2 + 12], 20
7350
7351! cbranch
7352andcc %l0, 1, %g0
7353be,pt %xcc, TARGET133
7354nop
7355RET133:
7356
7357! lfsr step begin
7358srlx %l0, 1, %o5
7359xnor %o5, %l0, %o5
7360sllx %o5, 63, %o5
7361or %o5, %l0, %l0
7362srlx %l0, 1, %l0
7363
7364
7365P134: !_MEMBAR (FP)
7366
7367P135: !_BSTC [8] (maybe <- 0x3f800028) (FP)
7368wr %g0, 0xe0, %asi
7369! preparing store val #0, next val will be in f32
7370fmovs %f16, %f20
7371fadds %f16, %f17, %f16
7372! preparing store val #1, next val will be in f33
7373fmovs %f16, %f21
7374fadds %f16, %f17, %f16
7375! preparing store val #2, next val will be in f35
7376fmovd %f20, %f32
7377fmovs %f16, %f21
7378fadds %f16, %f17, %f16
7379fmovd %f20, %f34
7380membar #Sync
7381stda %f32, [%i3 + 0 ] %asi
7382
7383P136: !_MEMBAR (FP)
7384membar #StoreLoad
7385
7386P137: !_LD [21] (Int)
7387lduw [%i2 + 0], %l3
7388! move %l3(lower) -> %o3(lower)
7389or %l3, %o3, %o3
7390
7391P138: !_MEMBAR (FP) (CBR)
7392
7393! cbranch
7394andcc %l0, 1, %g0
7395be,pt %xcc, TARGET138
7396nop
7397RET138:
7398
7399! lfsr step begin
7400srlx %l0, 1, %l6
7401xnor %l6, %l0, %l6
7402sllx %l6, 63, %l6
7403or %l6, %l0, %l0
7404srlx %l0, 1, %l0
7405
7406
7407P139: !_BSTC [22] (maybe <- 0x3f80002b) (FP)
7408wr %g0, 0xe0, %asi
7409! preparing store val #0, next val will be in f32
7410fmovs %f16, %f20
7411fadds %f16, %f17, %f16
7412! preparing store val #1, next val will be in f33
7413fmovs %f16, %f21
7414fadds %f16, %f17, %f16
7415! preparing store val #2, next val will be in f35
7416fmovd %f20, %f32
7417fmovs %f16, %f21
7418fadds %f16, %f17, %f16
7419fmovd %f20, %f34
7420membar #Sync
7421stda %f32, [%i2 + 0 ] %asi
7422
7423P140: !_MEMBAR (FP)
7424membar #StoreLoad
7425
7426P141: !_ST [6] (maybe <- 0x40) (Int)
7427stw %l4, [%i3 + 0 ]
7428add %l4, 1, %l4
7429
7430P142: !_ST [8] (maybe <- 0x41) (Int) (LE)
7431wr %g0, 0x88, %asi
7432! Change single-word-level endianess (big endian <-> little endian)
7433sethi %hi(0xff00ff00), %l6
7434or %l6, %lo(0xff00ff00), %l6
7435and %l4, %l6, %l7
7436srl %l7, 8, %l7
7437sll %l4, 8, %l3
7438and %l3, %l6, %l3
7439or %l3, %l7, %l3
7440srl %l3, 16, %l7
7441sll %l3, 16, %l3
7442srl %l3, 0, %l3
7443or %l3, %l7, %l3
7444stwa %l3, [%i3 + 12] %asi
7445add %l4, 1, %l4
7446
7447P143: !_SWAP [18] (maybe <- 0x42) (Int)
7448sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
7449add %i0, %i3, %i3
7450mov %l4, %o4
7451swap [%i3 + 0], %o4
7452! move %o4(lower) -> %o4(upper)
7453sllx %o4, 32, %o4
7454add %l4, 1, %l4
7455
7456P144: !_SWAP [2] (maybe <- 0x43) (Int)
7457mov %l4, %l3
7458swap [%i0 + 12], %l3
7459! move %l3(lower) -> %o4(lower)
7460srl %l3, 0, %l7
7461or %l7, %o4, %o4
7462!---- flushing int results buffer----
7463mov %o0, %l5
7464mov %o1, %l5
7465mov %o2, %l5
7466mov %o3, %l5
7467mov %o4, %l5
7468add %l4, 1, %l4
7469
7470P145: !_DWLD [3] (Int)
7471ldx [%i1 + 0], %o0
7472! move %o0(upper) -> %o0(upper)
7473! move %o0(lower) -> %o0(lower)
7474
7475P146: !_PREFETCH [12] (Int) (Branch target of P930)
7476sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
7477add %i0, %i2, %i2
7478prefetch [%i2 + 0], 22
7479ba P147
7480nop
7481
7482TARGET930:
7483ba RET930
7484nop
7485
7486
7487P147: !_CASX [22] (maybe <- 0x44) (Int)
7488sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
7489add %i0, %i3, %i3
7490ldx [%i3], %o1
7491! move %o1(upper) -> %o1(upper)
7492! move %o1(lower) -> %o1(lower)
7493mov %o1, %o5
7494sllx %l4, 32, %o2
7495add %l4, 1, %l4
7496or %l4, %o2, %o2
7497casx [%i3], %o5, %o2
7498! move %o2(upper) -> %o2(upper)
7499! move %o2(lower) -> %o2(lower)
7500add %l4, 1, %l4
7501
7502P148: !_ST [21] (maybe <- 0x46) (Int) (LE)
7503wr %g0, 0x88, %asi
7504! Change single-word-level endianess (big endian <-> little endian)
7505sethi %hi(0xff00ff00), %l3
7506or %l3, %lo(0xff00ff00), %l3
7507and %l4, %l3, %l6
7508srl %l6, 8, %l6
7509sll %l4, 8, %o5
7510and %o5, %l3, %o5
7511or %o5, %l6, %o5
7512srl %o5, 16, %l6
7513sll %o5, 16, %o5
7514srl %o5, 0, %o5
7515or %o5, %l6, %o5
7516stwa %o5, [%i3 + 0] %asi
7517add %l4, 1, %l4
7518
7519P149: !_MEMBAR (FP)
7520
7521P150: !_BST [19] (maybe <- 0x3f80002e) (FP)
7522wr %g0, 0xf0, %asi
7523sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
7524add %i0, %i2, %i2
7525! preparing store val #0, next val will be in f32
7526fmovs %f16, %f20
7527fadds %f16, %f17, %f16
7528! preparing store val #1, next val will be in f33
7529fmovs %f16, %f21
7530fadds %f16, %f17, %f16
7531! preparing store val #2, next val will be in f35
7532fmovd %f20, %f32
7533fmovs %f16, %f21
7534fadds %f16, %f17, %f16
7535fmovd %f20, %f34
7536membar #Sync
7537stda %f32, [%i2 + 0 ] %asi
7538
7539P151: !_MEMBAR (FP)
7540membar #StoreLoad
7541
7542P152: !_CAS [1] (maybe <- 0x47) (Int)
7543add %i0, 4, %l7
7544lduw [%l7], %o3
7545mov %o3, %l6
7546! move %l6(lower) -> %o3(upper)
7547sllx %l6, 32, %o3
7548mov %l4, %l3
7549cas [%l7], %l6, %l3
7550! move %l3(lower) -> %o3(lower)
7551srl %l3, 0, %l6
7552or %l6, %o3, %o3
7553add %l4, 1, %l4
7554
7555P153: !_CAS [9] (maybe <- 0x48) (Int)
7556sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
7557add %i0, %i3, %i3
7558lduw [%i3], %o4
7559mov %o4, %l6
7560! move %l6(lower) -> %o4(upper)
7561sllx %l6, 32, %o4
7562mov %l4, %l3
7563cas [%i3], %l6, %l3
7564! move %l3(lower) -> %o4(lower)
7565srl %l3, 0, %l6
7566or %l6, %o4, %o4
7567!---- flushing int results buffer----
7568mov %o0, %l5
7569mov %o1, %l5
7570mov %o2, %l5
7571mov %o3, %l5
7572mov %o4, %l5
7573add %l4, 1, %l4
7574
7575P154: !_ST_BINIT [20] (maybe <- 0x49) (Int)
7576wr %g0, 0xe2, %asi
7577stwa %l4, [%i2 + 12] %asi
7578add %l4, 1, %l4
7579
7580P155: !_MEMBAR (Int)
7581membar #StoreLoad
7582
7583P156: !_SWAP [19] (maybe <- 0x4a) (Int)
7584mov %l4, %o0
7585swap [%i2 + 4], %o0
7586! move %o0(lower) -> %o0(upper)
7587sllx %o0, 32, %o0
7588add %l4, 1, %l4
7589
7590P157: !_MEMBAR (FP)
7591
7592P158: !_BST [18] (maybe <- 0x3f800031) (FP)
7593wr %g0, 0xf0, %asi
7594! preparing store val #0, next val will be in f32
7595fmovs %f16, %f20
7596fadds %f16, %f17, %f16
7597! preparing store val #1, next val will be in f33
7598fmovs %f16, %f21
7599fadds %f16, %f17, %f16
7600! preparing store val #2, next val will be in f35
7601fmovd %f20, %f32
7602fmovs %f16, %f21
7603fadds %f16, %f17, %f16
7604fmovd %f20, %f34
7605membar #Sync
7606stda %f32, [%i2 + 0 ] %asi
7607
7608P159: !_MEMBAR (FP)
7609membar #StoreLoad
7610
7611P160: !_DWST [2] (maybe <- 0x4b) (Int)
7612mov %l4, %l7
7613stx %l7, [%i0 + 8]
7614add %l4, 1, %l4
7615
7616P161: !_LDD [20] (Int)
7617ldd [%i2 + 8], %l6
7618! move %l7(lower) -> %o0(lower)
7619or %l7, %o0, %o0
7620
7621P162: !_MEMBAR (FP)
7622membar #StoreLoad
7623
7624P163: !_BLD [17] (FP)
7625wr %g0, 0xf0, %asi
7626sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
7627add %i0, %i2, %i2
7628ldda [%i2 + 0] %asi, %f32
7629membar #Sync
7630! 3 addresses covered
7631fmovd %f32, %f18
7632fmovs %f18, %f15
7633!---- flushing fp results buffer to %f30 ----
7634fmovd %f0, %f30
7635fmovd %f2, %f30
7636fmovd %f4, %f30
7637fmovd %f6, %f30
7638fmovd %f8, %f30
7639fmovd %f10, %f30
7640fmovd %f12, %f30
7641fmovd %f14, %f30
7642!--
7643fmovs %f19, %f0
7644fmovd %f34, %f18
7645fmovs %f19, %f1
7646
7647P164: !_MEMBAR (FP)
7648
7649P165: !_ST_BINIT [16] (maybe <- 0x4c) (Int)
7650wr %g0, 0xe2, %asi
7651stwa %l4, [%i2 + 4] %asi
7652add %l4, 1, %l4
7653
7654P166: !_MEMBAR (Int)
7655membar #StoreLoad
7656
7657P167: !_BLD [8] (FP)
7658wr %g0, 0xf0, %asi
7659sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
7660add %i0, %i3, %i3
7661ldda [%i3 + 0] %asi, %f32
7662membar #Sync
7663! 3 addresses covered
7664fmovd %f32, %f2
7665fmovd %f34, %f18
7666fmovs %f19, %f4
7667
7668P168: !_MEMBAR (FP)
7669
7670P169: !_DWST [19] (maybe <- 0x4d) (Int)
7671sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
7672add %i0, %i2, %i2
7673sllx %l4, 32, %o5
7674add %l4, 1, %l4
7675or %o5, %l4, %o5
7676stx %o5, [%i2 + 0]
7677add %l4, 1, %l4
7678
7679P170: !_DWST_BINIT [18] (maybe <- 0x4f) (Int)
7680wr %g0, 0xe2, %asi
7681sllx %l4, 32, %l7
7682add %l4, 1, %l4
7683or %l7, %l4, %l7
7684stxa %l7, [%i2 + 0] %asi
7685add %l4, 1, %l4
7686
7687P171: !_MEMBAR (Int)
7688membar #StoreLoad
7689
7690P172: !_DWST [14] (maybe <- 0x51) (Int)
7691sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
7692add %i0, %i3, %i3
7693mov %l4, %l6
7694stx %l6, [%i3 + 8]
7695add %l4, 1, %l4
7696
7697P173: !_LDD [6] (Int)
7698sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
7699add %i0, %i2, %i2
7700ldd [%i2 + 0], %l6
7701! move %l6(lower) -> %o1(upper)
7702sllx %l6, 32, %o1
7703! move %l7(lower) -> %o1(lower)
7704or %l7, %o1, %o1
7705
7706P174: !_DWLD [3] (Int)
7707ldx [%i1 + 0], %o2
7708! move %o2(upper) -> %o2(upper)
7709! move %o2(lower) -> %o2(lower)
7710
7711P175: !_MEMBAR (FP)
7712membar #StoreLoad
7713
7714P176: !_BLD [11] (FP) (CBR)
7715wr %g0, 0xf0, %asi
7716sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
7717add %i0, %i3, %i3
7718ldda [%i3 + 0] %asi, %f32
7719membar #Sync
7720! 3 addresses covered
7721fmovd %f32, %f18
7722fmovs %f18, %f5
7723fmovs %f19, %f6
7724fmovd %f34, %f18
7725fmovs %f19, %f7
7726
7727! cbranch
7728andcc %l0, 1, %g0
7729be,pn %xcc, TARGET176
7730nop
7731RET176:
7732
7733! lfsr step begin
7734srlx %l0, 1, %l7
7735xnor %l7, %l0, %l7
7736sllx %l7, 63, %l7
7737or %l7, %l0, %l0
7738srlx %l0, 1, %l0
7739
7740
7741P177: !_MEMBAR (FP)
7742
7743P178: !_BSTC [18] (maybe <- 0x3f800034) (FP)
7744wr %g0, 0xe0, %asi
7745sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
7746add %i0, %i2, %i2
7747! preparing store val #0, next val will be in f32
7748fmovs %f16, %f20
7749fadds %f16, %f17, %f16
7750! preparing store val #1, next val will be in f33
7751fmovs %f16, %f21
7752fadds %f16, %f17, %f16
7753! preparing store val #2, next val will be in f35
7754fmovd %f20, %f32
7755fmovs %f16, %f21
7756fadds %f16, %f17, %f16
7757fmovd %f20, %f34
7758membar #Sync
7759stda %f32, [%i2 + 0 ] %asi
7760
7761P179: !_MEMBAR (FP)
7762
7763P180: !_BSTC [21] (maybe <- 0x3f800037) (FP)
7764wr %g0, 0xe0, %asi
7765sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
7766add %i0, %i3, %i3
7767! preparing store val #0, next val will be in f32
7768fmovs %f16, %f20
7769fadds %f16, %f17, %f16
7770! preparing store val #1, next val will be in f33
7771fmovs %f16, %f21
7772fadds %f16, %f17, %f16
7773! preparing store val #2, next val will be in f35
7774fmovd %f20, %f32
7775fmovs %f16, %f21
7776fadds %f16, %f17, %f16
7777fmovd %f20, %f34
7778membar #Sync
7779stda %f32, [%i3 + 0 ] %asi
7780
7781P181: !_MEMBAR (FP) (CBR)
7782membar #StoreLoad
7783
7784! cbranch
7785andcc %l0, 1, %g0
7786be,pt %xcc, TARGET181
7787nop
7788RET181:
7789
7790! lfsr step begin
7791srlx %l0, 1, %l6
7792xnor %l6, %l0, %l6
7793sllx %l6, 63, %l6
7794or %l6, %l0, %l0
7795srlx %l0, 1, %l0
7796
7797
7798P182: !_CAS [9] (maybe <- 0x52) (Int)
7799sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
7800add %i0, %i2, %i2
7801lduw [%i2], %o3
7802mov %o3, %l7
7803! move %l7(lower) -> %o3(upper)
7804sllx %l7, 32, %o3
7805mov %l4, %l6
7806cas [%i2], %l7, %l6
7807! move %l6(lower) -> %o3(lower)
7808srl %l6, 0, %l7
7809or %l7, %o3, %o3
7810add %l4, 1, %l4
7811
7812P183: !_CASX [2] (maybe <- 0x53) (Int) (Branch target of P631)
7813add %i0, 8, %o5
7814ldx [%o5], %o4
7815! move %o4(upper) -> %o4(upper)
7816! move %o4(lower) -> %o4(lower)
7817!---- flushing int results buffer----
7818mov %o0, %l5
7819mov %o1, %l5
7820mov %o2, %l5
7821mov %o3, %l5
7822mov %o4, %l5
7823mov %o4, %l7
7824mov %l4, %o0
7825casx [%o5], %l7, %o0
7826! move %o0(upper) -> %o0(upper)
7827! move %o0(lower) -> %o0(lower)
7828add %l4, 1, %l4
7829ba P184
7830nop
7831
7832TARGET631:
7833ba RET631
7834nop
7835
7836
7837P184: !_DWST [13] (maybe <- 0x54) (Int)
7838sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
7839add %i0, %i3, %i3
7840sllx %l4, 32, %l7
7841add %l4, 1, %l4
7842or %l7, %l4, %l7
7843stx %l7, [%i3 + 0]
7844add %l4, 1, %l4
7845
7846P185: !_ST [7] (maybe <- 0x56) (Int)
7847sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
7848add %i0, %i2, %i2
7849stw %l4, [%i2 + 4 ]
7850add %l4, 1, %l4
7851
7852P186: !_DWST_BINIT [4] (maybe <- 0x57) (Int)
7853wr %g0, 0xe2, %asi
7854sllx %l4, 32, %l3
7855add %l4, 1, %l4
7856or %l3, %l4, %l3
7857stxa %l3, [%i1 + 0] %asi
7858add %l4, 1, %l4
7859
7860P187: !_MEMBAR (Int)
7861membar #StoreLoad
7862
7863P188: !_ST_BINIT [9] (maybe <- 0x59) (Int)
7864wr %g0, 0xe2, %asi
7865sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
7866add %i0, %i3, %i3
7867stwa %l4, [%i3 + 0] %asi
7868add %l4, 1, %l4
7869
7870P189: !_MEMBAR (Int)
7871membar #StoreLoad
7872
7873P190: !_PREFETCH [3] (Int) (Branch target of P112)
7874prefetch [%i1 + 0], 22
7875ba P191
7876nop
7877
7878TARGET112:
7879ba RET112
7880nop
7881
7882
7883P191: !_CAS [13] (maybe <- 0x5a) (Int)
7884sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
7885add %i0, %i2, %i2
7886add %i2, 4, %o5
7887lduw [%o5], %o1
7888mov %o1, %l7
7889! move %l7(lower) -> %o1(upper)
7890sllx %l7, 32, %o1
7891mov %l4, %l6
7892cas [%o5], %l7, %l6
7893! move %l6(lower) -> %o1(lower)
7894srl %l6, 0, %l7
7895or %l7, %o1, %o1
7896add %l4, 1, %l4
7897
7898P192: !_DWST_BINIT [16] (maybe <- 0x5b) (Int)
7899wr %g0, 0xe2, %asi
7900sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
7901sub %i0, %i3, %i3
7902sllx %l4, 32, %o5
7903add %l4, 1, %l4
7904or %o5, %l4, %o5
7905stxa %o5, [%i3 + 0] %asi
7906add %l4, 1, %l4
7907
7908P193: !_MEMBAR (Int) (Branch target of P281)
7909membar #StoreLoad
7910ba P194
7911nop
7912
7913TARGET281:
7914ba RET281
7915nop
7916
7917
7918P194: !_ST_BINIT [14] (maybe <- 0x5d) (Int)
7919wr %g0, 0xe2, %asi
7920stwa %l4, [%i2 + 12] %asi
7921add %l4, 1, %l4
7922
7923P195: !_MEMBAR (Int) (CBR)
7924membar #StoreLoad
7925
7926! cbranch
7927andcc %l0, 1, %g0
7928be,pt %xcc, TARGET195
7929nop
7930RET195:
7931
7932! lfsr step begin
7933srlx %l0, 1, %l6
7934xnor %l6, %l0, %l6
7935sllx %l6, 63, %l6
7936or %l6, %l0, %l0
7937srlx %l0, 1, %l0
7938
7939
7940P196: !_LD [12] (FP)
7941ld [%i2 + 0], %f8
7942! 1 addresses covered
7943
7944P197: !_MEMBAR (FP) (CBR)
7945membar #StoreLoad
7946
7947! cbranch
7948andcc %l0, 1, %g0
7949be,pt %xcc, TARGET197
7950nop
7951RET197:
7952
7953! lfsr step begin
7954srlx %l0, 1, %l7
7955xnor %l7, %l0, %l7
7956sllx %l7, 63, %l7
7957or %l7, %l0, %l0
7958srlx %l0, 1, %l0
7959
7960
7961P198: !_BLD [3] (FP)
7962wr %g0, 0xf0, %asi
7963ldda [%i1 + 0] %asi, %f32
7964membar #Sync
7965! 3 addresses covered
7966fmovd %f32, %f18
7967fmovs %f18, %f9
7968fmovs %f19, %f10
7969fmovd %f34, %f18
7970fmovs %f19, %f11
7971
7972P199: !_MEMBAR (FP)
7973
7974P200: !_BSTC [1] (maybe <- 0x3f80003a) (FP)
7975wr %g0, 0xe0, %asi
7976! preparing store val #0, next val will be in f32
7977fmovs %f16, %f20
7978fadds %f16, %f17, %f16
7979! preparing store val #1, next val will be in f33
7980fmovs %f16, %f21
7981fadds %f16, %f17, %f16
7982! preparing store val #2, next val will be in f35
7983fmovd %f20, %f32
7984fmovs %f16, %f21
7985fadds %f16, %f17, %f16
7986fmovd %f20, %f34
7987membar #Sync
7988stda %f32, [%i0 + 0 ] %asi
7989
7990P201: !_MEMBAR (FP)
7991membar #StoreLoad
7992
7993P202: !_LD [2] (Int)
7994lduw [%i0 + 12], %o2
7995! move %o2(lower) -> %o2(upper)
7996sllx %o2, 32, %o2
7997
7998P203: !_REPLACEMENT [15] (Int)
7999sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
8000sub %i0, %i2, %i2
8001sethi %hi(0x20000), %l3
8002ld [%i2+0], %l7
8003st %l7, [%i2+0]
8004add %i2, %l3, %l6
8005ld [%l6+0], %l7
8006st %l7, [%l6+0]
8007add %l6, %l3, %l6
8008ld [%l6+0], %l7
8009st %l7, [%l6+0]
8010add %l6, %l3, %l6
8011ld [%l6+0], %l7
8012st %l7, [%l6+0]
8013add %l6, %l3, %l6
8014ld [%l6+0], %l7
8015st %l7, [%l6+0]
8016add %l6, %l3, %l6
8017ld [%l6+0], %l7
8018st %l7, [%l6+0]
8019add %l6, %l3, %l6
8020ld [%l6+0], %l7
8021st %l7, [%l6+0]
8022add %l6, %l3, %l6
8023ld [%l6+0], %l7
8024st %l7, [%l6+0]
8025
8026P204: !_DWST [18] (maybe <- 0x5e) (Int)
8027sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
8028add %i0, %i3, %i3
8029sllx %l4, 32, %o5
8030add %l4, 1, %l4
8031or %o5, %l4, %o5
8032stx %o5, [%i3 + 0]
8033add %l4, 1, %l4
8034
8035P205: !_ST [17] (maybe <- 0x60) (Int) (CBR)
8036sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
8037sub %i0, %i2, %i2
8038stw %l4, [%i2 + 12 ]
8039add %l4, 1, %l4
8040
8041! cbranch
8042andcc %l0, 1, %g0
8043be,pt %xcc, TARGET205
8044nop
8045RET205:
8046
8047! lfsr step begin
8048srlx %l0, 1, %l6
8049xnor %l6, %l0, %l6
8050sllx %l6, 63, %l6
8051or %l6, %l0, %l0
8052srlx %l0, 1, %l0
8053
8054
8055P206: !_MEMBAR (FP)
8056
8057P207: !_BSTC [11] (maybe <- 0x3f80003d) (FP)
8058wr %g0, 0xe0, %asi
8059sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
8060add %i0, %i3, %i3
8061! preparing store val #0, next val will be in f32
8062fmovs %f16, %f20
8063fadds %f16, %f17, %f16
8064! preparing store val #1, next val will be in f33
8065fmovs %f16, %f21
8066fadds %f16, %f17, %f16
8067! preparing store val #2, next val will be in f35
8068fmovd %f20, %f32
8069fmovs %f16, %f21
8070fadds %f16, %f17, %f16
8071fmovd %f20, %f34
8072membar #Sync
8073stda %f32, [%i3 + 0 ] %asi
8074
8075P208: !_MEMBAR (FP)
8076membar #StoreLoad
8077
8078P209: !_DWST [11] (maybe <- 0x61) (Int)
8079mov %l4, %l6
8080stx %l6, [%i3 + 8]
8081add %l4, 1, %l4
8082
8083P210: !_ST [12] (maybe <- 0x3f800040) (FP)
8084sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
8085add %i0, %i2, %i2
8086! preparing store val #0, next val will be in f20
8087fmovs %f16, %f20
8088fadds %f16, %f17, %f16
8089st %f20, [%i2 + 0 ]
8090
8091P211: !_MEMBAR (FP)
8092
8093P212: !_BSTC [18] (maybe <- 0x3f800041) (FP)
8094wr %g0, 0xe0, %asi
8095sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
8096add %i0, %i3, %i3
8097! preparing store val #0, next val will be in f32
8098fmovs %f16, %f20
8099fadds %f16, %f17, %f16
8100! preparing store val #1, next val will be in f33
8101fmovs %f16, %f21
8102fadds %f16, %f17, %f16
8103! preparing store val #2, next val will be in f35
8104fmovd %f20, %f32
8105fmovs %f16, %f21
8106fadds %f16, %f17, %f16
8107fmovd %f20, %f34
8108membar #Sync
8109stda %f32, [%i3 + 0 ] %asi
8110
8111P213: !_MEMBAR (FP)
8112membar #StoreLoad
8113
8114P214: !_CAS [7] (maybe <- 0x62) (Int)
8115sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
8116add %i0, %i2, %i2
8117add %i2, 4, %o5
8118lduw [%o5], %l6
8119mov %l6, %l7
8120! move %l7(lower) -> %o2(lower)
8121or %l7, %o2, %o2
8122mov %l4, %o3
8123cas [%o5], %l7, %o3
8124! move %o3(lower) -> %o3(upper)
8125sllx %o3, 32, %o3
8126add %l4, 1, %l4
8127
8128P215: !_CASX [13] (maybe <- 0x63) (Int)
8129sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
8130add %i0, %i3, %i3
8131ldx [%i3], %l6
8132! move %l6(upper) -> %o3(lower)
8133srlx %l6, 32, %l7
8134or %l7, %o3, %o3
8135! move %l6(lower) -> %o4(upper)
8136sllx %l6, 32, %o4
8137mov %l6, %l7
8138sllx %l4, 32, %l6
8139add %l4, 1, %l4
8140or %l4, %l6, %l6
8141casx [%i3], %l7, %l6
8142! move %l6(upper) -> %o4(lower)
8143srlx %l6, 32, %l7
8144or %l7, %o4, %o4
8145!---- flushing int results buffer----
8146mov %o0, %l5
8147mov %o1, %l5
8148mov %o2, %l5
8149mov %o3, %l5
8150mov %o4, %l5
8151! move %l6(lower) -> %o0(upper)
8152sllx %l6, 32, %o0
8153add %l4, 1, %l4
8154
8155P216: !_DWLD [19] (Int)
8156sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
8157add %i0, %i2, %i2
8158ldx [%i2 + 0], %o5
8159! move %o5(upper) -> %o0(lower)
8160srlx %o5, 32, %l7
8161or %l7, %o0, %o0
8162! move %o5(lower) -> %o1(upper)
8163sllx %o5, 32, %o1
8164
8165P217: !_ST_BINIT [8] (maybe <- 0x65) (Int)
8166wr %g0, 0xe2, %asi
8167sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
8168add %i0, %i3, %i3
8169stwa %l4, [%i3 + 12] %asi
8170add %l4, 1, %l4
8171
8172P218: !_MEMBAR (Int)
8173membar #StoreLoad
8174
8175P219: !_SWAP [18] (maybe <- 0x66) (Int)
8176mov %l4, %l6
8177swap [%i2 + 0], %l6
8178! move %l6(lower) -> %o1(lower)
8179srl %l6, 0, %o5
8180or %o5, %o1, %o1
8181add %l4, 1, %l4
8182
8183P220: !_MEMBAR (FP)
8184membar #StoreLoad
8185
8186P221: !_BLD [20] (FP)
8187wr %g0, 0xf0, %asi
8188ldda [%i2 + 0] %asi, %f32
8189membar #Sync
8190! 3 addresses covered
8191fmovd %f32, %f12
8192fmovd %f34, %f18
8193fmovs %f19, %f14
8194
8195P222: !_MEMBAR (FP)
8196
8197P223: !_BSTC [10] (maybe <- 0x3f800044) (FP)
8198wr %g0, 0xe0, %asi
8199sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
8200add %i0, %i2, %i2
8201! preparing store val #0, next val will be in f32
8202fmovs %f16, %f20
8203fadds %f16, %f17, %f16
8204! preparing store val #1, next val will be in f33
8205fmovs %f16, %f21
8206fadds %f16, %f17, %f16
8207! preparing store val #2, next val will be in f35
8208fmovd %f20, %f32
8209fmovs %f16, %f21
8210fadds %f16, %f17, %f16
8211fmovd %f20, %f34
8212membar #Sync
8213stda %f32, [%i2 + 0 ] %asi
8214
8215P224: !_MEMBAR (FP)
8216membar #StoreLoad
8217
8218P225: !_SWAP [23] (maybe <- 0x67) (Int)
8219sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
8220add %i0, %i3, %i3
8221mov %l4, %o2
8222swap [%i3 + 12], %o2
8223! move %o2(lower) -> %o2(upper)
8224sllx %o2, 32, %o2
8225add %l4, 1, %l4
8226
8227P226: !_DWST_BINIT [20] (maybe <- 0x68) (Int)
8228wr %g0, 0xe2, %asi
8229sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
8230add %i0, %i2, %i2
8231mov %l4, %l3
8232stxa %l3, [%i2 + 8] %asi
8233add %l4, 1, %l4
8234
8235P227: !_MEMBAR (Int)
8236membar #StoreLoad
8237
8238P228: !_DWST_BINIT [0] (maybe <- 0x69) (Int)
8239wr %g0, 0xe2, %asi
8240sllx %l4, 32, %o5
8241add %l4, 1, %l4
8242or %o5, %l4, %o5
8243stxa %o5, [%i0 + 0] %asi
8244add %l4, 1, %l4
8245
8246P229: !_MEMBAR (Int)
8247membar #StoreLoad
8248
8249P230: !_BLD [9] (FP)
8250wr %g0, 0xf0, %asi
8251sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
8252add %i0, %i3, %i3
8253ldda [%i3 + 0] %asi, %f32
8254membar #Sync
8255! 3 addresses covered
8256fmovd %f32, %f18
8257fmovs %f18, %f15
8258!---- flushing fp results buffer to %f30 ----
8259fmovd %f0, %f30
8260fmovd %f2, %f30
8261fmovd %f4, %f30
8262fmovd %f6, %f30
8263fmovd %f8, %f30
8264fmovd %f10, %f30
8265fmovd %f12, %f30
8266fmovd %f14, %f30
8267!--
8268fmovs %f19, %f0
8269fmovd %f34, %f18
8270fmovs %f19, %f1
8271
8272P231: !_MEMBAR (FP)
8273
8274P232: !_CAS [23] (maybe <- 0x6b) (Int)
8275sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
8276add %i0, %i2, %i2
8277add %i2, 12, %o5
8278lduw [%o5], %l6
8279mov %l6, %l7
8280! move %l7(lower) -> %o2(lower)
8281or %l7, %o2, %o2
8282mov %l4, %o3
8283cas [%o5], %l7, %o3
8284! move %o3(lower) -> %o3(upper)
8285sllx %o3, 32, %o3
8286add %l4, 1, %l4
8287
8288P233: !_CAS [21] (maybe <- 0x6c) (Int)
8289lduw [%i2], %l6
8290mov %l6, %l7
8291! move %l7(lower) -> %o3(lower)
8292or %l7, %o3, %o3
8293mov %l4, %o4
8294cas [%i2], %l7, %o4
8295! move %o4(lower) -> %o4(upper)
8296sllx %o4, 32, %o4
8297add %l4, 1, %l4
8298
8299P234: !_CASX [19] (maybe <- 0x6d) (Int)
8300sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
8301add %i0, %i3, %i3
8302ldx [%i3], %l6
8303! move %l6(upper) -> %o4(lower)
8304srlx %l6, 32, %l7
8305or %l7, %o4, %o4
8306!---- flushing int results buffer----
8307mov %o0, %l5
8308mov %o1, %l5
8309mov %o2, %l5
8310mov %o3, %l5
8311mov %o4, %l5
8312! move %l6(lower) -> %o0(upper)
8313sllx %l6, 32, %o0
8314mov %l6, %l7
8315sllx %l4, 32, %l6
8316add %l4, 1, %l4
8317or %l4, %l6, %l6
8318casx [%i3], %l7, %l6
8319! move %l6(upper) -> %o0(lower)
8320srlx %l6, 32, %l7
8321or %l7, %o0, %o0
8322! move %l6(lower) -> %o1(upper)
8323sllx %l6, 32, %o1
8324add %l4, 1, %l4
8325
8326P235: !_MEMBAR (FP)
8327
8328P236: !_BST [1] (maybe <- 0x3f800047) (FP)
8329wr %g0, 0xf0, %asi
8330! preparing store val #0, next val will be in f32
8331fmovs %f16, %f20
8332fadds %f16, %f17, %f16
8333! preparing store val #1, next val will be in f33
8334fmovs %f16, %f21
8335fadds %f16, %f17, %f16
8336! preparing store val #2, next val will be in f35
8337fmovd %f20, %f32
8338fmovs %f16, %f21
8339fadds %f16, %f17, %f16
8340fmovd %f20, %f34
8341membar #Sync
8342stda %f32, [%i0 + 0 ] %asi
8343
8344P237: !_MEMBAR (FP)
8345membar #StoreLoad
8346
8347P238: !_PREFETCH [2] (Int)
8348prefetch [%i0 + 12], 21
8349
8350P239: !_CASX [20] (maybe <- 0x6f) (Int)
8351add %i3, 8, %l7
8352ldx [%l7], %l3
8353! move %l3(upper) -> %o1(lower)
8354srlx %l3, 32, %l6
8355or %l6, %o1, %o1
8356! move %l3(lower) -> %o2(upper)
8357sllx %l3, 32, %o2
8358mov %l3, %l6
8359mov %l4, %l3
8360casx [%l7], %l6, %l3
8361! move %l3(upper) -> %o2(lower)
8362srlx %l3, 32, %l6
8363or %l6, %o2, %o2
8364! move %l3(lower) -> %o3(upper)
8365sllx %l3, 32, %o3
8366add %l4, 1, %l4
8367
8368P240: !_MEMBAR (FP)
8369membar #StoreLoad
8370
8371P241: !_BLD [1] (FP)
8372wr %g0, 0xf0, %asi
8373ldda [%i0 + 0] %asi, %f32
8374membar #Sync
8375! 3 addresses covered
8376fmovd %f32, %f2
8377fmovd %f34, %f18
8378fmovs %f19, %f4
8379
8380P242: !_MEMBAR (FP)
8381
8382P243: !_CAS [3] (maybe <- 0x70) (Int) (CBR)
8383lduw [%i1], %l3
8384mov %l3, %l6
8385! move %l6(lower) -> %o3(lower)
8386or %l6, %o3, %o3
8387mov %l4, %o4
8388cas [%i1], %l6, %o4
8389! move %o4(lower) -> %o4(upper)
8390sllx %o4, 32, %o4
8391add %l4, 1, %l4
8392
8393! cbranch
8394andcc %l0, 1, %g0
8395be,pn %xcc, TARGET243
8396nop
8397RET243:
8398
8399! lfsr step begin
8400srlx %l0, 1, %l6
8401xnor %l6, %l0, %l6
8402sllx %l6, 63, %l6
8403or %l6, %l0, %l0
8404srlx %l0, 1, %l0
8405
8406
8407P244: !_DWLD [22] (Int) (LE) (Branch target of P2)
8408wr %g0, 0x88, %asi
8409ldxa [%i2 + 0] %asi, %o5
8410! move %o5(lower) -> %o4(lower)
8411srl %o5, 0, %l7
8412or %l7, %o4, %o4
8413!---- flushing int results buffer----
8414mov %o0, %l5
8415mov %o1, %l5
8416mov %o2, %l5
8417mov %o3, %l5
8418mov %o4, %l5
8419! move %o5(upper) -> %o0(upper)
8420or %o5, %g0, %o0
8421ba P245
8422nop
8423
8424TARGET2:
8425ba RET2
8426nop
8427
8428
8429P245: !_ST_BINIT [2] (maybe <- 0x71) (Int)
8430wr %g0, 0xe2, %asi
8431stwa %l4, [%i0 + 12] %asi
8432add %l4, 1, %l4
8433
8434P246: !_MEMBAR (Int)
8435membar #StoreLoad
8436
8437P247: !_BLD [13] (FP)
8438wr %g0, 0xf0, %asi
8439sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
8440add %i0, %i2, %i2
8441ldda [%i2 + 0] %asi, %f32
8442membar #Sync
8443! 3 addresses covered
8444fmovd %f32, %f18
8445fmovs %f18, %f5
8446fmovs %f19, %f6
8447fmovd %f34, %f18
8448fmovs %f19, %f7
8449
8450P248: !_MEMBAR (FP)
8451
8452P249: !_ST_BINIT [16] (maybe <- 0x72) (Int)
8453wr %g0, 0xe2, %asi
8454sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
8455sub %i0, %i3, %i3
8456stwa %l4, [%i3 + 4] %asi
8457add %l4, 1, %l4
8458
8459P250: !_MEMBAR (Int)
8460membar #StoreLoad
8461
8462P251: !_ST_BINIT [4] (maybe <- 0x73) (Int)
8463wr %g0, 0xe2, %asi
8464stwa %l4, [%i1 + 4] %asi
8465add %l4, 1, %l4
8466
8467P252: !_MEMBAR (Int)
8468
8469P253: !_BSTC [17] (maybe <- 0x3f80004a) (FP)
8470wr %g0, 0xe0, %asi
8471! preparing store val #0, next val will be in f32
8472fmovs %f16, %f20
8473fadds %f16, %f17, %f16
8474! preparing store val #1, next val will be in f33
8475fmovs %f16, %f21
8476fadds %f16, %f17, %f16
8477! preparing store val #2, next val will be in f35
8478fmovd %f20, %f32
8479fmovs %f16, %f21
8480fadds %f16, %f17, %f16
8481fmovd %f20, %f34
8482membar #Sync
8483stda %f32, [%i3 + 0 ] %asi
8484
8485P254: !_MEMBAR (FP)
8486membar #StoreLoad
8487
8488P255: !_SWAP [19] (maybe <- 0x74) (Int) (CBR)
8489sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
8490add %i0, %i2, %i2
8491mov %l4, %l7
8492swap [%i2 + 4], %l7
8493! move %l7(lower) -> %o0(lower)
8494srlx %o0, 32, %o0
8495sllx %o0, 32, %o0
8496srl %l7, 0, %l3
8497or %l3, %o0, %o0
8498add %l4, 1, %l4
8499
8500! cbranch
8501andcc %l0, 1, %g0
8502be,pt %xcc, TARGET255
8503nop
8504RET255:
8505
8506! lfsr step begin
8507srlx %l0, 1, %o5
8508xnor %o5, %l0, %o5
8509sllx %o5, 63, %o5
8510or %o5, %l0, %l0
8511srlx %l0, 1, %l0
8512
8513
8514P256: !_CAS [23] (maybe <- 0x75) (Int)
8515sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
8516sub %i0, %i3, %i3
8517add %i3, 12, %l7
8518lduw [%l7], %o1
8519mov %o1, %l6
8520! move %l6(lower) -> %o1(upper)
8521sllx %l6, 32, %o1
8522mov %l4, %l3
8523cas [%l7], %l6, %l3
8524! move %l3(lower) -> %o1(lower)
8525srl %l3, 0, %l6
8526or %l6, %o1, %o1
8527add %l4, 1, %l4
8528
8529P257: !_MEMBAR (FP)
8530
8531P258: !_BST [4] (maybe <- 0x3f80004d) (FP) (CBR)
8532wr %g0, 0xf0, %asi
8533! preparing store val #0, next val will be in f32
8534fmovs %f16, %f20
8535fadds %f16, %f17, %f16
8536! preparing store val #1, next val will be in f33
8537fmovs %f16, %f21
8538fadds %f16, %f17, %f16
8539! preparing store val #2, next val will be in f35
8540fmovd %f20, %f32
8541fmovs %f16, %f21
8542fadds %f16, %f17, %f16
8543fmovd %f20, %f34
8544membar #Sync
8545stda %f32, [%i1 + 0 ] %asi
8546
8547! cbranch
8548andcc %l0, 1, %g0
8549be,pt %xcc, TARGET258
8550nop
8551RET258:
8552
8553! lfsr step begin
8554srlx %l0, 1, %l3
8555xnor %l3, %l0, %l3
8556sllx %l3, 63, %l3
8557or %l3, %l0, %l0
8558srlx %l0, 1, %l0
8559
8560
8561P259: !_MEMBAR (FP) (Branch target of P530)
8562membar #StoreLoad
8563ba P260
8564nop
8565
8566TARGET530:
8567ba RET530
8568nop
8569
8570
8571P260: !_PREFETCH [3] (Int)
8572prefetch [%i1 + 0], 21
8573
8574P261: !_SWAP [21] (maybe <- 0x76) (Int)
8575mov %l4, %o2
8576swap [%i3 + 0], %o2
8577! move %o2(lower) -> %o2(upper)
8578sllx %o2, 32, %o2
8579add %l4, 1, %l4
8580
8581P262: !_ST_BINIT [19] (maybe <- 0x77) (Int)
8582wr %g0, 0xe2, %asi
8583stwa %l4, [%i2 + 4] %asi
8584add %l4, 1, %l4
8585
8586P263: !_MEMBAR (Int)
8587
8588P264: !_BSTC [22] (maybe <- 0x3f800050) (FP)
8589wr %g0, 0xe0, %asi
8590! preparing store val #0, next val will be in f32
8591fmovs %f16, %f20
8592fadds %f16, %f17, %f16
8593! preparing store val #1, next val will be in f33
8594fmovs %f16, %f21
8595fadds %f16, %f17, %f16
8596! preparing store val #2, next val will be in f35
8597fmovd %f20, %f32
8598fmovs %f16, %f21
8599fadds %f16, %f17, %f16
8600fmovd %f20, %f34
8601membar #Sync
8602stda %f32, [%i3 + 0 ] %asi
8603
8604P265: !_MEMBAR (FP)
8605membar #StoreLoad
8606
8607P266: !_BLD [6] (FP) (Branch target of P609)
8608wr %g0, 0xf0, %asi
8609sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
8610add %i0, %i2, %i2
8611ldda [%i2 + 0] %asi, %f32
8612membar #Sync
8613! 3 addresses covered
8614fmovd %f32, %f8
8615fmovd %f34, %f18
8616fmovs %f19, %f10
8617ba P267
8618nop
8619
8620TARGET609:
8621ba RET609
8622nop
8623
8624
8625P267: !_MEMBAR (FP)
8626
8627P268: !_DWST [12] (maybe <- 0x78) (Int)
8628sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
8629add %i0, %i3, %i3
8630sllx %l4, 32, %l7
8631add %l4, 1, %l4
8632or %l7, %l4, %l7
8633stx %l7, [%i3 + 0]
8634add %l4, 1, %l4
8635
8636P269: !_CASX [0] (maybe <- 0x7a) (Int)
8637ldx [%i0], %l3
8638! move %l3(upper) -> %o2(lower)
8639srlx %l3, 32, %l6
8640or %l6, %o2, %o2
8641! move %l3(lower) -> %o3(upper)
8642sllx %l3, 32, %o3
8643mov %l3, %l6
8644sllx %l4, 32, %l3
8645add %l4, 1, %l4
8646or %l4, %l3, %l3
8647casx [%i0], %l6, %l3
8648! move %l3(upper) -> %o3(lower)
8649srlx %l3, 32, %l6
8650or %l6, %o3, %o3
8651! move %l3(lower) -> %o4(upper)
8652sllx %l3, 32, %o4
8653add %l4, 1, %l4
8654
8655P270: !_LD [20] (Int)
8656sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
8657add %i0, %i2, %i2
8658lduw [%i2 + 12], %l7
8659! move %l7(lower) -> %o4(lower)
8660or %l7, %o4, %o4
8661!---- flushing int results buffer----
8662mov %o0, %l5
8663mov %o1, %l5
8664mov %o2, %l5
8665mov %o3, %l5
8666mov %o4, %l5
8667
8668P271: !_ST_BINIT [11] (maybe <- 0x7c) (Int)
8669wr %g0, 0xe2, %asi
8670sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
8671add %i0, %i3, %i3
8672stwa %l4, [%i3 + 12] %asi
8673add %l4, 1, %l4
8674
8675P272: !_MEMBAR (Int)
8676membar #StoreLoad
8677
8678P273: !_PREFETCH [11] (Int)
8679prefetch [%i3 + 12], 21
8680
8681P274: !_CAS [2] (maybe <- 0x7d) (Int) (LE)
8682! Change single-word-level endianess (big endian <-> little endian)
8683sethi %hi(0xff00ff00), %o5
8684or %o5, %lo(0xff00ff00), %o5
8685and %l4, %o5, %l7
8686srl %l7, 8, %l7
8687sll %l4, 8, %l3
8688and %l3, %o5, %l3
8689or %l3, %l7, %l3
8690srl %l3, 16, %l7
8691sll %l3, 16, %l3
8692srl %l3, 0, %l3
8693or %l3, %l7, %l3
8694wr %g0, 0x88, %asi
8695add %i0, 12, %o5
8696lduwa [%o5] %asi, %o0
8697mov %o0, %l7
8698! move %l7(lower) -> %o0(upper)
8699sllx %l7, 32, %o0
8700mov %l3, %l6
8701casa [%o5] %asi, %l7, %l6
8702! move %l6(lower) -> %o0(lower)
8703srl %l6, 0, %l7
8704or %l7, %o0, %o0
8705add %l4, 1, %l4
8706
8707P275: !_ST_BINIT [15] (maybe <- 0x7e) (Int)
8708wr %g0, 0xe2, %asi
8709sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
8710sub %i0, %i2, %i2
8711stwa %l4, [%i2 + 0] %asi
8712add %l4, 1, %l4
8713
8714P276: !_MEMBAR (Int)
8715membar #StoreLoad
8716
8717P277: !_DWST_BINIT [7] (maybe <- 0x7f) (Int)
8718wr %g0, 0xe2, %asi
8719sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
8720add %i0, %i3, %i3
8721sllx %l4, 32, %l6
8722add %l4, 1, %l4
8723or %l6, %l4, %l6
8724stxa %l6, [%i3 + 0] %asi
8725add %l4, 1, %l4
8726
8727P278: !_MEMBAR (Int)
8728membar #StoreLoad
8729
8730P279: !_REPLACEMENT [6] (Int)
8731sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
8732sub %i0, %i2, %i2
8733sethi %hi(0x20000), %l3
8734ld [%i2+0], %l7
8735st %l7, [%i2+0]
8736add %i2, %l3, %l6
8737ld [%l6+0], %l7
8738st %l7, [%l6+0]
8739add %l6, %l3, %l6
8740ld [%l6+0], %l7
8741st %l7, [%l6+0]
8742add %l6, %l3, %l6
8743ld [%l6+0], %l7
8744st %l7, [%l6+0]
8745add %l6, %l3, %l6
8746ld [%l6+0], %l7
8747st %l7, [%l6+0]
8748add %l6, %l3, %l6
8749ld [%l6+0], %l7
8750st %l7, [%l6+0]
8751add %l6, %l3, %l6
8752ld [%l6+0], %l7
8753st %l7, [%l6+0]
8754add %l6, %l3, %l6
8755ld [%l6+0], %l7
8756st %l7, [%l6+0]
8757
8758P280: !_LDD [4] (Int)
8759ldd [%i1 + 0], %l6
8760! move %l6(lower) -> %o1(upper)
8761sllx %l6, 32, %o1
8762! move %l7(lower) -> %o1(lower)
8763or %l7, %o1, %o1
8764
8765P281: !_LD [22] (Int) (CBR)
8766sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
8767sub %i0, %i3, %i3
8768lduw [%i3 + 4], %o2
8769! move %o2(lower) -> %o2(upper)
8770sllx %o2, 32, %o2
8771
8772! cbranch
8773andcc %l0, 1, %g0
8774be,pt %xcc, TARGET281
8775nop
8776RET281:
8777
8778! lfsr step begin
8779srlx %l0, 1, %l7
8780xnor %l7, %l0, %l7
8781sllx %l7, 63, %l7
8782or %l7, %l0, %l0
8783srlx %l0, 1, %l0
8784
8785
8786P282: !_LD [6] (Int) (LE)
8787wr %g0, 0x88, %asi
8788sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
8789add %i0, %i2, %i2
8790lduwa [%i2 + 0] %asi, %l3
8791! move %l3(lower) -> %o2(lower)
8792or %l3, %o2, %o2
8793
8794P283: !_CASX [10] (maybe <- 0x81) (Int)
8795sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
8796add %i0, %i3, %i3
8797ldx [%i3], %o3
8798! move %o3(upper) -> %o3(upper)
8799! move %o3(lower) -> %o3(lower)
8800mov %o3, %l6
8801sllx %l4, 32, %o4
8802add %l4, 1, %l4
8803or %l4, %o4, %o4
8804casx [%i3], %l6, %o4
8805! move %o4(upper) -> %o4(upper)
8806! move %o4(lower) -> %o4(lower)
8807!---- flushing int results buffer----
8808mov %o0, %l5
8809mov %o1, %l5
8810mov %o2, %l5
8811mov %o3, %l5
8812mov %o4, %l5
8813add %l4, 1, %l4
8814
8815P284: !_DWLD [4] (Int)
8816ldx [%i1 + 0], %o0
8817! move %o0(upper) -> %o0(upper)
8818! move %o0(lower) -> %o0(lower)
8819
8820P285: !_CASX [10] (maybe <- 0x83) (Int)
8821ldx [%i3], %o1
8822! move %o1(upper) -> %o1(upper)
8823! move %o1(lower) -> %o1(lower)
8824mov %o1, %o5
8825sllx %l4, 32, %o2
8826add %l4, 1, %l4
8827or %l4, %o2, %o2
8828casx [%i3], %o5, %o2
8829! move %o2(upper) -> %o2(upper)
8830! move %o2(lower) -> %o2(lower)
8831add %l4, 1, %l4
8832
8833P286: !_MEMBAR (FP)
8834
8835P287: !_BSTC [0] (maybe <- 0x3f800053) (FP)
8836wr %g0, 0xe0, %asi
8837! preparing store val #0, next val will be in f32
8838fmovs %f16, %f20
8839fadds %f16, %f17, %f16
8840! preparing store val #1, next val will be in f33
8841fmovs %f16, %f21
8842fadds %f16, %f17, %f16
8843! preparing store val #2, next val will be in f35
8844fmovd %f20, %f32
8845fmovs %f16, %f21
8846fadds %f16, %f17, %f16
8847fmovd %f20, %f34
8848membar #Sync
8849stda %f32, [%i0 + 0 ] %asi
8850
8851P288: !_MEMBAR (FP)
8852
8853P289: !_BSTC [21] (maybe <- 0x3f800056) (FP)
8854wr %g0, 0xe0, %asi
8855sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
8856sub %i0, %i2, %i2
8857! preparing store val #0, next val will be in f32
8858fmovs %f16, %f20
8859fadds %f16, %f17, %f16
8860! preparing store val #1, next val will be in f33
8861fmovs %f16, %f21
8862fadds %f16, %f17, %f16
8863! preparing store val #2, next val will be in f35
8864fmovd %f20, %f32
8865fmovs %f16, %f21
8866fadds %f16, %f17, %f16
8867fmovd %f20, %f34
8868membar #Sync
8869stda %f32, [%i2 + 0 ] %asi
8870
8871P290: !_MEMBAR (FP)
8872membar #StoreLoad
8873
8874P291: !_BLD [16] (FP)
8875wr %g0, 0xf0, %asi
8876sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
8877sub %i0, %i3, %i3
8878ldda [%i3 + 0] %asi, %f32
8879membar #Sync
8880! 3 addresses covered
8881fmovd %f32, %f18
8882fmovs %f18, %f11
8883fmovs %f19, %f12
8884fmovd %f34, %f18
8885fmovs %f19, %f13
8886
8887P292: !_MEMBAR (FP)
8888
8889P293: !_BSTC [16] (maybe <- 0x3f800059) (FP) (CBR)
8890wr %g0, 0xe0, %asi
8891! preparing store val #0, next val will be in f32
8892fmovs %f16, %f20
8893fadds %f16, %f17, %f16
8894! preparing store val #1, next val will be in f33
8895fmovs %f16, %f21
8896fadds %f16, %f17, %f16
8897! preparing store val #2, next val will be in f35
8898fmovd %f20, %f32
8899fmovs %f16, %f21
8900fadds %f16, %f17, %f16
8901fmovd %f20, %f34
8902membar #Sync
8903stda %f32, [%i3 + 0 ] %asi
8904
8905! cbranch
8906andcc %l0, 1, %g0
8907be,pt %xcc, TARGET293
8908nop
8909RET293:
8910
8911! lfsr step begin
8912srlx %l0, 1, %l3
8913xnor %l3, %l0, %l3
8914sllx %l3, 63, %l3
8915or %l3, %l0, %l0
8916srlx %l0, 1, %l0
8917
8918
8919P294: !_MEMBAR (FP)
8920membar #StoreLoad
8921
8922P295: !_ST [4] (maybe <- 0x85) (Int)
8923stw %l4, [%i1 + 4 ]
8924add %l4, 1, %l4
8925
8926P296: !_CAS [10] (maybe <- 0x86) (Int) (LE)
8927! Change single-word-level endianess (big endian <-> little endian)
8928sethi %hi(0xff00ff00), %l6
8929or %l6, %lo(0xff00ff00), %l6
8930and %l4, %l6, %l3
8931srl %l3, 8, %l3
8932sll %l4, 8, %l7
8933and %l7, %l6, %l7
8934or %l7, %l3, %l7
8935srl %l7, 16, %l3
8936sll %l7, 16, %l7
8937srl %l7, 0, %l7
8938or %l7, %l3, %l7
8939wr %g0, 0x88, %asi
8940sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
8941add %i0, %i2, %i2
8942add %i2, 4, %l6
8943lduwa [%l6] %asi, %o3
8944mov %o3, %l3
8945! move %l3(lower) -> %o3(upper)
8946sllx %l3, 32, %o3
8947mov %l7, %o5
8948casa [%l6] %asi, %l3, %o5
8949! move %o5(lower) -> %o3(lower)
8950srl %o5, 0, %l3
8951or %l3, %o3, %o3
8952add %l4, 1, %l4
8953
8954P297: !_ST_BINIT [16] (maybe <- 0x87) (Int)
8955wr %g0, 0xe2, %asi
8956stwa %l4, [%i3 + 4] %asi
8957add %l4, 1, %l4
8958
8959P298: !_MEMBAR (Int) (Branch target of P197)
8960ba P299
8961nop
8962
8963TARGET197:
8964ba RET197
8965nop
8966
8967
8968P299: !_BST [13] (maybe <- 0x3f80005c) (FP) (Branch target of P964)
8969wr %g0, 0xf0, %asi
8970sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
8971add %i0, %i3, %i3
8972! preparing store val #0, next val will be in f32
8973fmovs %f16, %f20
8974fadds %f16, %f17, %f16
8975! preparing store val #1, next val will be in f33
8976fmovs %f16, %f21
8977fadds %f16, %f17, %f16
8978! preparing store val #2, next val will be in f35
8979fmovd %f20, %f32
8980fmovs %f16, %f21
8981fadds %f16, %f17, %f16
8982fmovd %f20, %f34
8983membar #Sync
8984stda %f32, [%i3 + 0 ] %asi
8985ba P300
8986nop
8987
8988TARGET964:
8989ba RET964
8990nop
8991
8992
8993P300: !_MEMBAR (FP)
8994membar #StoreLoad
8995
8996P301: !_PREFETCH [6] (Int)
8997sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
8998add %i0, %i2, %i2
8999prefetch [%i2 + 0], 20
9000
9001P302: !_LD [7] (Int)
9002lduw [%i2 + 4], %o4
9003! move %o4(lower) -> %o4(upper)
9004sllx %o4, 32, %o4
9005
9006P303: !_REPLACEMENT [18] (Int)
9007sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
9008sub %i0, %i3, %i3
9009sethi %hi(0x20000), %l3
9010ld [%i3+0], %l7
9011st %l7, [%i3+0]
9012add %i3, %l3, %l6
9013ld [%l6+0], %l7
9014st %l7, [%l6+0]
9015add %l6, %l3, %l6
9016ld [%l6+0], %l7
9017st %l7, [%l6+0]
9018add %l6, %l3, %l6
9019ld [%l6+0], %l7
9020st %l7, [%l6+0]
9021add %l6, %l3, %l6
9022ld [%l6+0], %l7
9023st %l7, [%l6+0]
9024add %l6, %l3, %l6
9025ld [%l6+0], %l7
9026st %l7, [%l6+0]
9027add %l6, %l3, %l6
9028ld [%l6+0], %l7
9029st %l7, [%l6+0]
9030add %l6, %l3, %l6
9031ld [%l6+0], %l7
9032st %l7, [%l6+0]
9033
9034P304: !_CAS [16] (maybe <- 0x88) (Int)
9035sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
9036sub %i0, %i2, %i2
9037add %i2, 4, %l3
9038lduw [%l3], %l7
9039mov %l7, %o5
9040! move %o5(lower) -> %o4(lower)
9041or %o5, %o4, %o4
9042!---- flushing int results buffer----
9043mov %o0, %l5
9044mov %o1, %l5
9045mov %o2, %l5
9046mov %o3, %l5
9047mov %o4, %l5
9048mov %l4, %o0
9049cas [%l3], %o5, %o0
9050! move %o0(lower) -> %o0(upper)
9051sllx %o0, 32, %o0
9052add %l4, 1, %l4
9053
9054P305: !_CASX [14] (maybe <- 0x89) (Int)
9055sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
9056add %i0, %i3, %i3
9057add %i3, 8, %l3
9058ldx [%l3], %l7
9059! move %l7(upper) -> %o0(lower)
9060srlx %l7, 32, %o5
9061or %o5, %o0, %o0
9062! move %l7(lower) -> %o1(upper)
9063sllx %l7, 32, %o1
9064mov %l7, %o5
9065mov %l4, %l7
9066casx [%l3], %o5, %l7
9067! move %l7(upper) -> %o1(lower)
9068srlx %l7, 32, %o5
9069or %o5, %o1, %o1
9070! move %l7(lower) -> %o2(upper)
9071sllx %l7, 32, %o2
9072add %l4, 1, %l4
9073
9074P306: !_LD [22] (Int)
9075sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
9076sub %i0, %i2, %i2
9077lduw [%i2 + 4], %l3
9078! move %l3(lower) -> %o2(lower)
9079or %l3, %o2, %o2
9080
9081P307: !_DWST_BINIT [6] (maybe <- 0x8a) (Int)
9082wr %g0, 0xe2, %asi
9083sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
9084add %i0, %i3, %i3
9085sllx %l4, 32, %l6
9086add %l4, 1, %l4
9087or %l6, %l4, %l6
9088stxa %l6, [%i3 + 0] %asi
9089add %l4, 1, %l4
9090
9091P308: !_MEMBAR (Int)
9092membar #StoreLoad
9093
9094P309: !_BLD [8] (FP)
9095wr %g0, 0xf0, %asi
9096ldda [%i3 + 0] %asi, %f32
9097membar #Sync
9098! 3 addresses covered
9099fmovd %f32, %f14
9100!---- flushing fp results buffer to %f30 ----
9101fmovd %f0, %f30
9102fmovd %f2, %f30
9103fmovd %f4, %f30
9104fmovd %f6, %f30
9105fmovd %f8, %f30
9106fmovd %f10, %f30
9107fmovd %f12, %f30
9108fmovd %f14, %f30
9109!--
9110fmovd %f34, %f18
9111fmovs %f19, %f0
9112
9113P310: !_MEMBAR (FP) (Branch target of P195)
9114ba P311
9115nop
9116
9117TARGET195:
9118ba RET195
9119nop
9120
9121
9122P311: !_BST [19] (maybe <- 0x3f80005f) (FP)
9123wr %g0, 0xf0, %asi
9124sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
9125add %i0, %i2, %i2
9126! preparing store val #0, next val will be in f32
9127fmovs %f16, %f20
9128fadds %f16, %f17, %f16
9129! preparing store val #1, next val will be in f33
9130fmovs %f16, %f21
9131fadds %f16, %f17, %f16
9132! preparing store val #2, next val will be in f35
9133fmovd %f20, %f32
9134fmovs %f16, %f21
9135fadds %f16, %f17, %f16
9136fmovd %f20, %f34
9137membar #Sync
9138stda %f32, [%i2 + 0 ] %asi
9139
9140P312: !_MEMBAR (FP)
9141membar #StoreLoad
9142
9143P313: !_CASX [14] (maybe <- 0x8c) (Int)
9144sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
9145add %i0, %i3, %i3
9146add %i3, 8, %l3
9147ldx [%l3], %o3
9148! move %o3(upper) -> %o3(upper)
9149! move %o3(lower) -> %o3(lower)
9150mov %o3, %o5
9151mov %l4, %o4
9152casx [%l3], %o5, %o4
9153! move %o4(upper) -> %o4(upper)
9154! move %o4(lower) -> %o4(lower)
9155!---- flushing int results buffer----
9156mov %o0, %l5
9157mov %o1, %l5
9158mov %o2, %l5
9159mov %o3, %l5
9160mov %o4, %l5
9161add %l4, 1, %l4
9162
9163P314: !_MEMBAR (FP)
9164
9165P315: !_BST [23] (maybe <- 0x3f800062) (FP)
9166wr %g0, 0xf0, %asi
9167sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
9168sub %i0, %i2, %i2
9169! preparing store val #0, next val will be in f32
9170fmovs %f16, %f20
9171fadds %f16, %f17, %f16
9172! preparing store val #1, next val will be in f33
9173fmovs %f16, %f21
9174fadds %f16, %f17, %f16
9175! preparing store val #2, next val will be in f35
9176fmovd %f20, %f32
9177fmovs %f16, %f21
9178fadds %f16, %f17, %f16
9179fmovd %f20, %f34
9180membar #Sync
9181stda %f32, [%i2 + 0 ] %asi
9182
9183P316: !_MEMBAR (FP)
9184membar #StoreLoad
9185
9186P317: !_SWAP [17] (maybe <- 0x8d) (Int)
9187sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
9188sub %i0, %i3, %i3
9189mov %l4, %o0
9190swap [%i3 + 12], %o0
9191! move %o0(lower) -> %o0(upper)
9192sllx %o0, 32, %o0
9193add %l4, 1, %l4
9194
9195P318: !_DWST_BINIT [20] (maybe <- 0x8e) (Int)
9196wr %g0, 0xe2, %asi
9197sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
9198add %i0, %i2, %i2
9199mov %l4, %l6
9200stxa %l6, [%i2 + 8] %asi
9201add %l4, 1, %l4
9202
9203P319: !_MEMBAR (Int)
9204membar #StoreLoad
9205
9206P320: !_DWST_BINIT [7] (maybe <- 0x8f) (Int)
9207wr %g0, 0xe2, %asi
9208sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
9209sub %i0, %i3, %i3
9210sllx %l4, 32, %l6
9211add %l4, 1, %l4
9212or %l6, %l4, %l6
9213stxa %l6, [%i3 + 0] %asi
9214add %l4, 1, %l4
9215
9216P321: !_MEMBAR (Int)
9217
9218P322: !_BST [21] (maybe <- 0x3f800065) (FP)
9219wr %g0, 0xf0, %asi
9220sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
9221sub %i0, %i2, %i2
9222! preparing store val #0, next val will be in f32
9223fmovs %f16, %f20
9224fadds %f16, %f17, %f16
9225! preparing store val #1, next val will be in f33
9226fmovs %f16, %f21
9227fadds %f16, %f17, %f16
9228! preparing store val #2, next val will be in f35
9229fmovd %f20, %f32
9230fmovs %f16, %f21
9231fadds %f16, %f17, %f16
9232fmovd %f20, %f34
9233membar #Sync
9234stda %f32, [%i2 + 0 ] %asi
9235
9236P323: !_MEMBAR (FP)
9237membar #StoreLoad
9238
9239P324: !_DWLD [18] (Int)
9240sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
9241add %i0, %i3, %i3
9242ldx [%i3 + 0], %l3
9243! move %l3(upper) -> %o0(lower)
9244srlx %l3, 32, %o5
9245or %o5, %o0, %o0
9246! move %l3(lower) -> %o1(upper)
9247sllx %l3, 32, %o1
9248
9249P325: !_PREFETCH [13] (Int)
9250sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
9251add %i0, %i2, %i2
9252prefetch [%i2 + 4], 4
9253
9254P326: !_ST_BINIT [14] (maybe <- 0x91) (Int)
9255wr %g0, 0xe2, %asi
9256stwa %l4, [%i2 + 12] %asi
9257add %l4, 1, %l4
9258
9259P327: !_MEMBAR (Int)
9260
9261P328: !_BSTC [7] (maybe <- 0x3f800068) (FP)
9262wr %g0, 0xe0, %asi
9263sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
9264sub %i0, %i3, %i3
9265! preparing store val #0, next val will be in f32
9266fmovs %f16, %f20
9267fadds %f16, %f17, %f16
9268! preparing store val #1, next val will be in f33
9269fmovs %f16, %f21
9270fadds %f16, %f17, %f16
9271! preparing store val #2, next val will be in f35
9272fmovd %f20, %f32
9273fmovs %f16, %f21
9274fadds %f16, %f17, %f16
9275fmovd %f20, %f34
9276membar #Sync
9277stda %f32, [%i3 + 0 ] %asi
9278
9279P329: !_MEMBAR (FP)
9280membar #StoreLoad
9281
9282P330: !_SWAP [23] (maybe <- 0x92) (Int)
9283sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
9284sub %i0, %i2, %i2
9285mov %l4, %l6
9286swap [%i2 + 12], %l6
9287! move %l6(lower) -> %o1(lower)
9288srl %l6, 0, %o5
9289or %o5, %o1, %o1
9290add %l4, 1, %l4
9291
9292P331: !_DWLD [12] (Int)
9293sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
9294add %i0, %i3, %i3
9295ldx [%i3 + 0], %o2
9296! move %o2(upper) -> %o2(upper)
9297! move %o2(lower) -> %o2(lower)
9298
9299P332: !_DWLD [19] (Int)
9300sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
9301add %i0, %i2, %i2
9302ldx [%i2 + 0], %o3
9303! move %o3(upper) -> %o3(upper)
9304! move %o3(lower) -> %o3(lower)
9305
9306P333: !_LD [2] (Int)
9307lduw [%i0 + 12], %o4
9308! move %o4(lower) -> %o4(upper)
9309sllx %o4, 32, %o4
9310
9311P334: !_SWAP [12] (maybe <- 0x93) (Int)
9312mov %l4, %l7
9313swap [%i3 + 0], %l7
9314! move %l7(lower) -> %o4(lower)
9315srl %l7, 0, %l3
9316or %l3, %o4, %o4
9317!---- flushing int results buffer----
9318mov %o0, %l5
9319mov %o1, %l5
9320mov %o2, %l5
9321mov %o3, %l5
9322mov %o4, %l5
9323add %l4, 1, %l4
9324
9325P335: !_MEMBAR (FP)
9326
9327P336: !_BST [20] (maybe <- 0x3f80006b) (FP)
9328wr %g0, 0xf0, %asi
9329! preparing store val #0, next val will be in f32
9330fmovs %f16, %f20
9331fadds %f16, %f17, %f16
9332! preparing store val #1, next val will be in f33
9333fmovs %f16, %f21
9334fadds %f16, %f17, %f16
9335! preparing store val #2, next val will be in f35
9336fmovd %f20, %f32
9337fmovs %f16, %f21
9338fadds %f16, %f17, %f16
9339fmovd %f20, %f34
9340membar #Sync
9341stda %f32, [%i2 + 0 ] %asi
9342
9343P337: !_MEMBAR (FP)
9344membar #StoreLoad
9345
9346P338: !_LD [8] (Int) (LE)
9347wr %g0, 0x88, %asi
9348sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
9349sub %i0, %i3, %i3
9350lduwa [%i3 + 12] %asi, %o0
9351! move %o0(lower) -> %o0(upper)
9352sllx %o0, 32, %o0
9353
9354P339: !_ST_BINIT [4] (maybe <- 0x94) (Int)
9355wr %g0, 0xe2, %asi
9356stwa %l4, [%i1 + 4] %asi
9357add %l4, 1, %l4
9358
9359P340: !_MEMBAR (Int)
9360membar #StoreLoad
9361
9362P341: !_CAS [2] (maybe <- 0x95) (Int)
9363add %i0, 12, %l3
9364lduw [%l3], %l7
9365mov %l7, %o5
9366! move %o5(lower) -> %o0(lower)
9367or %o5, %o0, %o0
9368mov %l4, %o1
9369cas [%l3], %o5, %o1
9370! move %o1(lower) -> %o1(upper)
9371sllx %o1, 32, %o1
9372add %l4, 1, %l4
9373
9374P342: !_DWST_BINIT [5] (maybe <- 0x96) (Int)
9375wr %g0, 0xe2, %asi
9376mov %l4, %o5
9377stxa %o5, [%i1 + 8] %asi
9378add %l4, 1, %l4
9379
9380P343: !_MEMBAR (Int)
9381
9382P344: !_BST [19] (maybe <- 0x3f80006e) (FP)
9383wr %g0, 0xf0, %asi
9384! preparing store val #0, next val will be in f32
9385fmovs %f16, %f20
9386fadds %f16, %f17, %f16
9387! preparing store val #1, next val will be in f33
9388fmovs %f16, %f21
9389fadds %f16, %f17, %f16
9390! preparing store val #2, next val will be in f35
9391fmovd %f20, %f32
9392fmovs %f16, %f21
9393fadds %f16, %f17, %f16
9394fmovd %f20, %f34
9395membar #Sync
9396stda %f32, [%i2 + 0 ] %asi
9397
9398P345: !_MEMBAR (FP)
9399membar #StoreLoad
9400
9401P346: !_DWST [7] (maybe <- 0x97) (Int) (LE)
9402wr %g0, 0x88, %asi
9403sllx %l4, 32, %l6
9404add %l4, 1, %l4
9405or %l6, %l4, %l7
9406! Change double-word-level endianess (big endian <-> little endian)
9407sethi %hi(0xff00ff00), %o5
9408or %o5, %lo(0xff00ff00), %o5
9409sllx %o5, 32, %l6
9410or %o5, %l6, %o5
9411and %l7, %o5, %l6
9412srlx %l6, 8, %l6
9413sllx %l7, 8, %l7
9414and %l7, %o5, %l7
9415or %l7, %l6, %l7
9416sethi %hi(0xffff0000), %o5
9417srlx %l7, 16, %l6
9418andn %l6, %o5, %l6
9419andn %l7, %o5, %l7
9420sllx %l7, 16, %l7
9421or %l7, %l6, %l7
9422srlx %l7, 32, %l6
9423sllx %l7, 32, %l7
9424or %l7, %l6, %l6
9425stxa %l6, [%i3 + 0 ] %asi
9426add %l4, 1, %l4
9427
9428P347: !_CASX [16] (maybe <- 0x99) (Int)
9429sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
9430sub %i0, %i2, %i2
9431ldx [%i2], %o5
9432! move %o5(upper) -> %o1(lower)
9433srlx %o5, 32, %l3
9434or %l3, %o1, %o1
9435! move %o5(lower) -> %o2(upper)
9436sllx %o5, 32, %o2
9437mov %o5, %l3
9438sllx %l4, 32, %o5
9439add %l4, 1, %l4
9440or %l4, %o5, %o5
9441casx [%i2], %l3, %o5
9442! move %o5(upper) -> %o2(lower)
9443srlx %o5, 32, %l3
9444or %l3, %o2, %o2
9445! move %o5(lower) -> %o3(upper)
9446sllx %o5, 32, %o3
9447add %l4, 1, %l4
9448
9449P348: !_MEMBAR (FP)
9450membar #StoreLoad
9451
9452P349: !_BLD [18] (FP)
9453wr %g0, 0xf0, %asi
9454sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
9455add %i0, %i3, %i3
9456ldda [%i3 + 0] %asi, %f32
9457membar #Sync
9458! 3 addresses covered
9459fmovd %f32, %f18
9460fmovs %f18, %f1
9461fmovs %f19, %f2
9462fmovd %f34, %f18
9463fmovs %f19, %f3
9464
9465P350: !_MEMBAR (FP)
9466
9467P351: !_ST [10] (maybe <- 0x3f800071) (FP)
9468sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
9469add %i0, %i2, %i2
9470! preparing store val #0, next val will be in f20
9471fmovs %f16, %f20
9472fadds %f16, %f17, %f16
9473st %f20, [%i2 + 4 ]
9474
9475P352: !_ST [16] (maybe <- 0x9b) (Int)
9476sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
9477sub %i0, %i3, %i3
9478stw %l4, [%i3 + 4 ]
9479add %l4, 1, %l4
9480
9481P353: !_MEMBAR (FP)
9482
9483P354: !_BSTC [16] (maybe <- 0x3f800072) (FP)
9484wr %g0, 0xe0, %asi
9485! preparing store val #0, next val will be in f32
9486fmovs %f16, %f20
9487fadds %f16, %f17, %f16
9488! preparing store val #1, next val will be in f33
9489fmovs %f16, %f21
9490fadds %f16, %f17, %f16
9491! preparing store val #2, next val will be in f35
9492fmovd %f20, %f32
9493fmovs %f16, %f21
9494fadds %f16, %f17, %f16
9495fmovd %f20, %f34
9496membar #Sync
9497stda %f32, [%i3 + 0 ] %asi
9498
9499P355: !_MEMBAR (FP)
9500membar #StoreLoad
9501
9502P356: !_ST_BINIT [16] (maybe <- 0x9c) (Int)
9503wr %g0, 0xe2, %asi
9504stwa %l4, [%i3 + 4] %asi
9505add %l4, 1, %l4
9506
9507P357: !_MEMBAR (Int)
9508
9509P358: !_BSTC [23] (maybe <- 0x3f800075) (FP) (Branch target of P428)
9510wr %g0, 0xe0, %asi
9511sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
9512sub %i0, %i2, %i2
9513! preparing store val #0, next val will be in f32
9514fmovs %f16, %f20
9515fadds %f16, %f17, %f16
9516! preparing store val #1, next val will be in f33
9517fmovs %f16, %f21
9518fadds %f16, %f17, %f16
9519! preparing store val #2, next val will be in f35
9520fmovd %f20, %f32
9521fmovs %f16, %f21
9522fadds %f16, %f17, %f16
9523fmovd %f20, %f34
9524membar #Sync
9525stda %f32, [%i2 + 0 ] %asi
9526ba P359
9527nop
9528
9529TARGET428:
9530ba RET428
9531nop
9532
9533
9534P359: !_MEMBAR (FP)
9535membar #StoreLoad
9536
9537P360: !_BLD [18] (FP)
9538wr %g0, 0xf0, %asi
9539sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
9540add %i0, %i3, %i3
9541ldda [%i3 + 0] %asi, %f32
9542membar #Sync
9543! 3 addresses covered
9544fmovd %f32, %f4
9545fmovd %f34, %f18
9546fmovs %f19, %f6
9547
9548P361: !_MEMBAR (FP)
9549
9550P362: !_CAS [0] (maybe <- 0x9d) (Int)
9551lduw [%i0], %l7
9552mov %l7, %o5
9553! move %o5(lower) -> %o3(lower)
9554or %o5, %o3, %o3
9555mov %l4, %o4
9556cas [%i0], %o5, %o4
9557! move %o4(lower) -> %o4(upper)
9558sllx %o4, 32, %o4
9559add %l4, 1, %l4
9560
9561P363: !_DWST_BINIT [0] (maybe <- 0x9e) (Int)
9562wr %g0, 0xe2, %asi
9563sllx %l4, 32, %o5
9564add %l4, 1, %l4
9565or %o5, %l4, %o5
9566stxa %o5, [%i0 + 0] %asi
9567add %l4, 1, %l4
9568
9569P364: !_MEMBAR (Int)
9570membar #StoreLoad
9571
9572P365: !_DWST [8] (maybe <- 0xa0) (Int)
9573sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
9574sub %i0, %i2, %i2
9575mov %l4, %l7
9576stx %l7, [%i2 + 8]
9577add %l4, 1, %l4
9578
9579P366: !_PREFETCH [13] (Int)
9580sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
9581add %i0, %i3, %i3
9582prefetch [%i3 + 4], 2
9583
9584P367: !_CAS [9] (maybe <- 0xa1) (Int)
9585sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
9586add %i0, %i2, %i2
9587lduw [%i2], %l3
9588mov %l3, %l6
9589! move %l6(lower) -> %o4(lower)
9590or %l6, %o4, %o4
9591!---- flushing int results buffer----
9592mov %o0, %l5
9593mov %o1, %l5
9594mov %o2, %l5
9595mov %o3, %l5
9596mov %o4, %l5
9597mov %l4, %o0
9598cas [%i2], %l6, %o0
9599! move %o0(lower) -> %o0(upper)
9600sllx %o0, 32, %o0
9601add %l4, 1, %l4
9602
9603P368: !_MEMBAR (FP)
9604
9605P369: !_BST [6] (maybe <- 0x3f800078) (FP)
9606wr %g0, 0xf0, %asi
9607sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
9608sub %i0, %i3, %i3
9609! preparing store val #0, next val will be in f32
9610fmovs %f16, %f20
9611fadds %f16, %f17, %f16
9612! preparing store val #1, next val will be in f33
9613fmovs %f16, %f21
9614fadds %f16, %f17, %f16
9615! preparing store val #2, next val will be in f35
9616fmovd %f20, %f32
9617fmovs %f16, %f21
9618fadds %f16, %f17, %f16
9619fmovd %f20, %f34
9620membar #Sync
9621stda %f32, [%i3 + 0 ] %asi
9622
9623P370: !_MEMBAR (FP)
9624membar #StoreLoad
9625
9626P371: !_BLD [17] (FP)
9627wr %g0, 0xf0, %asi
9628sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
9629sub %i0, %i2, %i2
9630ldda [%i2 + 0] %asi, %f32
9631membar #Sync
9632! 3 addresses covered
9633fmovd %f32, %f18
9634fmovs %f18, %f7
9635fmovs %f19, %f8
9636fmovd %f34, %f18
9637fmovs %f19, %f9
9638
9639P372: !_MEMBAR (FP)
9640
9641P373: !_SWAP [13] (maybe <- 0xa2) (Int)
9642sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
9643add %i0, %i3, %i3
9644mov %l4, %l7
9645swap [%i3 + 4], %l7
9646! move %l7(lower) -> %o0(lower)
9647srl %l7, 0, %l3
9648or %l3, %o0, %o0
9649add %l4, 1, %l4
9650
9651P374: !_LDD [21] (Int) (Branch target of P762)
9652sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
9653sub %i0, %i2, %i2
9654ldd [%i2 + 0], %l6
9655! move %l6(lower) -> %o1(upper)
9656sllx %l6, 32, %o1
9657! move %l7(lower) -> %o1(lower)
9658or %l7, %o1, %o1
9659ba P375
9660nop
9661
9662TARGET762:
9663ba RET762
9664nop
9665
9666
9667P375: !_DWST_BINIT [10] (maybe <- 0xa3) (Int)
9668wr %g0, 0xe2, %asi
9669sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
9670add %i0, %i3, %i3
9671sllx %l4, 32, %l3
9672add %l4, 1, %l4
9673or %l3, %l4, %l3
9674stxa %l3, [%i3 + 0] %asi
9675add %l4, 1, %l4
9676
9677P376: !_MEMBAR (Int)
9678membar #StoreLoad
9679
9680P377: !_ST_BINIT [17] (maybe <- 0xa5) (Int)
9681wr %g0, 0xe2, %asi
9682sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
9683sub %i0, %i2, %i2
9684stwa %l4, [%i2 + 12] %asi
9685add %l4, 1, %l4
9686
9687P378: !_MEMBAR (Int)
9688membar #StoreLoad
9689
9690P379: !_BLD [15] (FP)
9691wr %g0, 0xf0, %asi
9692ldda [%i2 + 0] %asi, %f32
9693membar #Sync
9694! 3 addresses covered
9695fmovd %f32, %f10
9696fmovd %f34, %f18
9697fmovs %f19, %f12
9698
9699P380: !_MEMBAR (FP)
9700
9701P381: !_BLD [21] (FP)
9702wr %g0, 0xf0, %asi
9703sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
9704sub %i0, %i3, %i3
9705ldda [%i3 + 0] %asi, %f32
9706membar #Sync
9707! 3 addresses covered
9708fmovd %f32, %f18
9709fmovs %f18, %f13
9710fmovs %f19, %f14
9711fmovd %f34, %f18
9712fmovs %f19, %f15
9713!---- flushing fp results buffer to %f30 ----
9714fmovd %f0, %f30
9715fmovd %f2, %f30
9716fmovd %f4, %f30
9717fmovd %f6, %f30
9718fmovd %f8, %f30
9719fmovd %f10, %f30
9720fmovd %f12, %f30
9721fmovd %f14, %f30
9722!--
9723
9724P382: !_MEMBAR (FP)
9725
9726P383: !_CAS [13] (maybe <- 0xa6) (Int)
9727sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
9728add %i0, %i2, %i2
9729add %i2, 4, %o5
9730lduw [%o5], %o2
9731mov %o2, %l7
9732! move %l7(lower) -> %o2(upper)
9733sllx %l7, 32, %o2
9734mov %l4, %l6
9735cas [%o5], %l7, %l6
9736! move %l6(lower) -> %o2(lower)
9737srl %l6, 0, %l7
9738or %l7, %o2, %o2
9739add %l4, 1, %l4
9740
9741P384: !_MEMBAR (FP)
9742membar #StoreLoad
9743
9744P385: !_BLD [4] (FP)
9745wr %g0, 0xf0, %asi
9746ldda [%i1 + 0] %asi, %f0
9747membar #Sync
9748! 3 addresses covered
9749fmovs %f3, %f2
9750
9751P386: !_MEMBAR (FP)
9752
9753P387: !_BSTC [2] (maybe <- 0x3f80007b) (FP)
9754wr %g0, 0xe0, %asi
9755! preparing store val #0, next val will be in f32
9756fmovs %f16, %f20
9757fadds %f16, %f17, %f16
9758! preparing store val #1, next val will be in f33
9759fmovs %f16, %f21
9760fadds %f16, %f17, %f16
9761! preparing store val #2, next val will be in f35
9762fmovd %f20, %f32
9763fmovs %f16, %f21
9764fadds %f16, %f17, %f16
9765fmovd %f20, %f34
9766membar #Sync
9767stda %f32, [%i0 + 0 ] %asi
9768
9769P388: !_MEMBAR (FP)
9770membar #StoreLoad
9771
9772P389: !_BLD [4] (FP)
9773wr %g0, 0xf0, %asi
9774ldda [%i1 + 0] %asi, %f32
9775membar #Sync
9776! 3 addresses covered
9777fmovd %f32, %f18
9778fmovs %f18, %f3
9779fmovs %f19, %f4
9780fmovd %f34, %f18
9781fmovs %f19, %f5
9782
9783P390: !_MEMBAR (FP)
9784
9785P391: !_DWST_BINIT [10] (maybe <- 0xa7) (Int)
9786wr %g0, 0xe2, %asi
9787sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
9788add %i0, %i3, %i3
9789sllx %l4, 32, %l7
9790add %l4, 1, %l4
9791or %l7, %l4, %l7
9792stxa %l7, [%i3 + 0] %asi
9793add %l4, 1, %l4
9794
9795P392: !_MEMBAR (Int)
9796membar #StoreLoad
9797
9798P393: !_LDD [3] (Int)
9799ldd [%i1 + 0], %l6
9800! move %l6(lower) -> %o3(upper)
9801sllx %l6, 32, %o3
9802! move %l7(lower) -> %o3(lower)
9803or %l7, %o3, %o3
9804
9805P394: !_CASX [18] (maybe <- 0xa9) (Int)
9806sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
9807add %i0, %i2, %i2
9808ldx [%i2], %o4
9809! move %o4(upper) -> %o4(upper)
9810! move %o4(lower) -> %o4(lower)
9811!---- flushing int results buffer----
9812mov %o0, %l5
9813mov %o1, %l5
9814mov %o2, %l5
9815mov %o3, %l5
9816mov %o4, %l5
9817mov %o4, %l3
9818sllx %l4, 32, %o0
9819add %l4, 1, %l4
9820or %l4, %o0, %o0
9821casx [%i2], %l3, %o0
9822! move %o0(upper) -> %o0(upper)
9823! move %o0(lower) -> %o0(lower)
9824add %l4, 1, %l4
9825
9826P395: !_DWLD [2] (Int)
9827ldx [%i0 + 8], %o1
9828! move %o1(lower) -> %o1(upper)
9829sllx %o1, 32, %o1
9830
9831P396: !_MEMBAR (FP) (CBR)
9832membar #StoreLoad
9833
9834! cbranch
9835andcc %l0, 1, %g0
9836be,pn %xcc, TARGET396
9837nop
9838RET396:
9839
9840! lfsr step begin
9841srlx %l0, 1, %l7
9842xnor %l7, %l0, %l7
9843sllx %l7, 63, %l7
9844or %l7, %l0, %l0
9845srlx %l0, 1, %l0
9846
9847
9848P397: !_BLD [10] (FP)
9849wr %g0, 0xf0, %asi
9850ldda [%i3 + 0] %asi, %f32
9851membar #Sync
9852! 3 addresses covered
9853fmovd %f32, %f6
9854fmovd %f34, %f18
9855fmovs %f19, %f8
9856
9857P398: !_MEMBAR (FP)
9858
9859P399: !_LD [1] (Int)
9860lduw [%i0 + 4], %l3
9861! move %l3(lower) -> %o1(lower)
9862or %l3, %o1, %o1
9863
9864P400: !_DWST_BINIT [22] (maybe <- 0xab) (Int)
9865wr %g0, 0xe2, %asi
9866sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
9867sub %i0, %i3, %i3
9868sllx %l4, 32, %l6
9869add %l4, 1, %l4
9870or %l6, %l4, %l6
9871stxa %l6, [%i3 + 0] %asi
9872add %l4, 1, %l4
9873
9874P401: !_MEMBAR (Int)
9875membar #StoreLoad
9876
9877P402: !_BLD [9] (FP)
9878wr %g0, 0xf0, %asi
9879sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
9880add %i0, %i2, %i2
9881ldda [%i2 + 0] %asi, %f32
9882membar #Sync
9883! 3 addresses covered
9884fmovd %f32, %f18
9885fmovs %f18, %f9
9886fmovs %f19, %f10
9887fmovd %f34, %f18
9888fmovs %f19, %f11
9889
9890P403: !_MEMBAR (FP)
9891
9892P404: !_SWAP [20] (maybe <- 0xad) (Int)
9893sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
9894add %i0, %i3, %i3
9895mov %l4, %o2
9896swap [%i3 + 12], %o2
9897! move %o2(lower) -> %o2(upper)
9898sllx %o2, 32, %o2
9899add %l4, 1, %l4
9900
9901P405: !_PREFETCH [6] (Int)
9902sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
9903sub %i0, %i2, %i2
9904prefetch [%i2 + 0], 17
9905
9906P406: !_LDD [11] (Int)
9907sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
9908add %i0, %i3, %i3
9909ldd [%i3 + 8], %l6
9910! move %l7(lower) -> %o2(lower)
9911or %l7, %o2, %o2
9912
9913P407: !_MEMBAR (FP)
9914
9915P408: !_BSTC [20] (maybe <- 0x3f80007e) (FP)
9916wr %g0, 0xe0, %asi
9917sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
9918add %i0, %i2, %i2
9919! preparing store val #0, next val will be in f32
9920fmovs %f16, %f20
9921fadds %f16, %f17, %f16
9922! preparing store val #1, next val will be in f33
9923fmovs %f16, %f21
9924fadds %f16, %f17, %f16
9925! preparing store val #2, next val will be in f35
9926fmovd %f20, %f32
9927fmovs %f16, %f21
9928fadds %f16, %f17, %f16
9929fmovd %f20, %f34
9930membar #Sync
9931stda %f32, [%i2 + 0 ] %asi
9932
9933P409: !_MEMBAR (FP)
9934membar #StoreLoad
9935
9936P410: !_LD [12] (Int)
9937sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
9938add %i0, %i3, %i3
9939lduw [%i3 + 0], %o3
9940! move %o3(lower) -> %o3(upper)
9941sllx %o3, 32, %o3
9942
9943P411: !_SWAP [2] (maybe <- 0xae) (Int)
9944mov %l4, %o5
9945swap [%i0 + 12], %o5
9946! move %o5(lower) -> %o3(lower)
9947srl %o5, 0, %l6
9948or %l6, %o3, %o3
9949add %l4, 1, %l4
9950
9951P412: !_CAS [17] (maybe <- 0xaf) (Int) (Branch target of P181)
9952sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
9953sub %i0, %i2, %i2
9954add %i2, 12, %l6
9955lduw [%l6], %o4
9956mov %o4, %l3
9957! move %l3(lower) -> %o4(upper)
9958sllx %l3, 32, %o4
9959mov %l4, %o5
9960cas [%l6], %l3, %o5
9961! move %o5(lower) -> %o4(lower)
9962srl %o5, 0, %l3
9963or %l3, %o4, %o4
9964!---- flushing int results buffer----
9965mov %o0, %l5
9966mov %o1, %l5
9967mov %o2, %l5
9968mov %o3, %l5
9969mov %o4, %l5
9970add %l4, 1, %l4
9971ba P413
9972nop
9973
9974TARGET181:
9975ba RET181
9976nop
9977
9978
9979P413: !_MEMBAR (FP)
9980
9981P414: !_BSTC [5] (maybe <- 0x3f800081) (FP)
9982wr %g0, 0xe0, %asi
9983! preparing store val #0, next val will be in f32
9984fmovs %f16, %f20
9985fadds %f16, %f17, %f16
9986! preparing store val #1, next val will be in f33
9987fmovs %f16, %f21
9988fadds %f16, %f17, %f16
9989! preparing store val #2, next val will be in f35
9990fmovd %f20, %f32
9991fmovs %f16, %f21
9992fadds %f16, %f17, %f16
9993fmovd %f20, %f34
9994membar #Sync
9995stda %f32, [%i1 + 0 ] %asi
9996
9997P415: !_MEMBAR (FP)
9998membar #StoreLoad
9999
10000P416: !_CASX [20] (maybe <- 0xb0) (Int)
10001sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
10002add %i0, %i3, %i3
10003add %i3, 8, %l3
10004ldx [%l3], %o0
10005! move %o0(upper) -> %o0(upper)
10006! move %o0(lower) -> %o0(lower)
10007mov %o0, %o5
10008mov %l4, %o1
10009casx [%l3], %o5, %o1
10010! move %o1(upper) -> %o1(upper)
10011! move %o1(lower) -> %o1(lower)
10012add %l4, 1, %l4
10013
10014P417: !_MEMBAR (FP)
10015
10016P418: !_BSTC [10] (maybe <- 0x3f800084) (FP)
10017wr %g0, 0xe0, %asi
10018sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
10019add %i0, %i2, %i2
10020! preparing store val #0, next val will be in f32
10021fmovs %f16, %f20
10022fadds %f16, %f17, %f16
10023! preparing store val #1, next val will be in f33
10024fmovs %f16, %f21
10025fadds %f16, %f17, %f16
10026! preparing store val #2, next val will be in f35
10027fmovd %f20, %f32
10028fmovs %f16, %f21
10029fadds %f16, %f17, %f16
10030fmovd %f20, %f34
10031membar #Sync
10032stda %f32, [%i2 + 0 ] %asi
10033
10034P419: !_MEMBAR (FP)
10035membar #StoreLoad
10036
10037P420: !_CAS [19] (maybe <- 0xb1) (Int)
10038add %i3, 4, %o5
10039lduw [%o5], %o2
10040mov %o2, %l7
10041! move %l7(lower) -> %o2(upper)
10042sllx %l7, 32, %o2
10043mov %l4, %l6
10044cas [%o5], %l7, %l6
10045! move %l6(lower) -> %o2(lower)
10046srl %l6, 0, %l7
10047or %l7, %o2, %o2
10048add %l4, 1, %l4
10049
10050P421: !_CASX [13] (maybe <- 0xb2) (Int)
10051sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
10052add %i0, %i3, %i3
10053ldx [%i3], %o3
10054! move %o3(upper) -> %o3(upper)
10055! move %o3(lower) -> %o3(lower)
10056mov %o3, %l7
10057sllx %l4, 32, %o4
10058add %l4, 1, %l4
10059or %l4, %o4, %o4
10060casx [%i3], %l7, %o4
10061! move %o4(upper) -> %o4(upper)
10062! move %o4(lower) -> %o4(lower)
10063!---- flushing int results buffer----
10064mov %o0, %l5
10065mov %o1, %l5
10066mov %o2, %l5
10067mov %o3, %l5
10068mov %o4, %l5
10069add %l4, 1, %l4
10070
10071P422: !_LDD [10] (Int)
10072ldd [%i2 + 0], %l6
10073! move %l6(lower) -> %o0(upper)
10074sllx %l6, 32, %o0
10075! move %l7(lower) -> %o0(lower)
10076or %l7, %o0, %o0
10077
10078P423: !_CAS [22] (maybe <- 0xb4) (Int)
10079sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
10080sub %i0, %i2, %i2
10081add %i2, 4, %l6
10082lduw [%l6], %o1
10083mov %o1, %l3
10084! move %l3(lower) -> %o1(upper)
10085sllx %l3, 32, %o1
10086mov %l4, %o5
10087cas [%l6], %l3, %o5
10088! move %o5(lower) -> %o1(lower)
10089srl %o5, 0, %l3
10090or %l3, %o1, %o1
10091add %l4, 1, %l4
10092
10093P424: !_MEMBAR (FP)
10094membar #StoreLoad
10095
10096P425: !_BLD [8] (FP)
10097wr %g0, 0xf0, %asi
10098sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
10099sub %i0, %i3, %i3
10100ldda [%i3 + 0] %asi, %f32
10101membar #Sync
10102! 3 addresses covered
10103fmovd %f32, %f12
10104fmovd %f34, %f18
10105fmovs %f19, %f14
10106
10107P426: !_MEMBAR (FP)
10108
10109P427: !_CAS [1] (maybe <- 0xb5) (Int)
10110add %i0, 4, %l6
10111lduw [%l6], %o2
10112mov %o2, %l3
10113! move %l3(lower) -> %o2(upper)
10114sllx %l3, 32, %o2
10115mov %l4, %o5
10116cas [%l6], %l3, %o5
10117! move %o5(lower) -> %o2(lower)
10118srl %o5, 0, %l3
10119or %l3, %o2, %o2
10120add %l4, 1, %l4
10121
10122P428: !_SWAP [15] (maybe <- 0xb6) (Int) (CBR)
10123sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
10124sub %i0, %i2, %i2
10125mov %l4, %o3
10126swap [%i2 + 0], %o3
10127! move %o3(lower) -> %o3(upper)
10128sllx %o3, 32, %o3
10129add %l4, 1, %l4
10130
10131! cbranch
10132andcc %l0, 1, %g0
10133be,pt %xcc, TARGET428
10134nop
10135RET428:
10136
10137! lfsr step begin
10138srlx %l0, 1, %o5
10139xnor %o5, %l0, %o5
10140sllx %o5, 63, %o5
10141or %o5, %l0, %l0
10142srlx %l0, 1, %l0
10143
10144
10145P429: !_MEMBAR (FP)
10146
10147P430: !_BSTC [0] (maybe <- 0x3f800087) (FP)
10148wr %g0, 0xe0, %asi
10149! preparing store val #0, next val will be in f32
10150fmovs %f16, %f20
10151fadds %f16, %f17, %f16
10152! preparing store val #1, next val will be in f33
10153fmovs %f16, %f21
10154fadds %f16, %f17, %f16
10155! preparing store val #2, next val will be in f35
10156fmovd %f20, %f32
10157fmovs %f16, %f21
10158fadds %f16, %f17, %f16
10159fmovd %f20, %f34
10160membar #Sync
10161stda %f32, [%i0 + 0 ] %asi
10162
10163P431: !_MEMBAR (FP)
10164membar #StoreLoad
10165
10166P432: !_CASX [12] (maybe <- 0xb7) (Int)
10167sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
10168add %i0, %i3, %i3
10169ldx [%i3], %l7
10170! move %l7(upper) -> %o3(lower)
10171srlx %l7, 32, %o5
10172or %o5, %o3, %o3
10173! move %l7(lower) -> %o4(upper)
10174sllx %l7, 32, %o4
10175mov %l7, %o5
10176sllx %l4, 32, %l7
10177add %l4, 1, %l4
10178or %l4, %l7, %l7
10179casx [%i3], %o5, %l7
10180! move %l7(upper) -> %o4(lower)
10181srlx %l7, 32, %o5
10182or %o5, %o4, %o4
10183!---- flushing int results buffer----
10184mov %o0, %l5
10185mov %o1, %l5
10186mov %o2, %l5
10187mov %o3, %l5
10188mov %o4, %l5
10189! move %l7(lower) -> %o0(upper)
10190sllx %l7, 32, %o0
10191add %l4, 1, %l4
10192
10193P433: !_DWST_BINIT [23] (maybe <- 0xb9) (Int)
10194wr %g0, 0xe2, %asi
10195sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
10196sub %i0, %i2, %i2
10197mov %l4, %o5
10198stxa %o5, [%i2 + 8] %asi
10199add %l4, 1, %l4
10200
10201P434: !_MEMBAR (Int)
10202membar #StoreLoad
10203
10204P435: !_ST_BINIT [13] (maybe <- 0xba) (Int)
10205wr %g0, 0xe2, %asi
10206stwa %l4, [%i3 + 4] %asi
10207add %l4, 1, %l4
10208
10209P436: !_MEMBAR (Int)
10210membar #StoreLoad
10211
10212P437: !_DWST [18] (maybe <- 0xbb) (Int)
10213sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
10214add %i0, %i3, %i3
10215sllx %l4, 32, %l6
10216add %l4, 1, %l4
10217or %l6, %l4, %l6
10218stx %l6, [%i3 + 0]
10219add %l4, 1, %l4
10220
10221P438: !_REPLACEMENT [8] (Int)
10222sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
10223add %i0, %i2, %i2
10224sethi %hi(0x20000), %l3
10225ld [%i2+12], %l7
10226st %l7, [%i2+12]
10227add %i2, %l3, %l6
10228ld [%l6+12], %l7
10229st %l7, [%l6+12]
10230add %l6, %l3, %l6
10231ld [%l6+12], %l7
10232st %l7, [%l6+12]
10233add %l6, %l3, %l6
10234ld [%l6+12], %l7
10235st %l7, [%l6+12]
10236add %l6, %l3, %l6
10237ld [%l6+12], %l7
10238st %l7, [%l6+12]
10239add %l6, %l3, %l6
10240ld [%l6+12], %l7
10241st %l7, [%l6+12]
10242add %l6, %l3, %l6
10243ld [%l6+12], %l7
10244st %l7, [%l6+12]
10245add %l6, %l3, %l6
10246ld [%l6+12], %l7
10247st %l7, [%l6+12]
10248
10249P439: !_DWST [20] (maybe <- 0xbd) (Int)
10250mov %l4, %o5
10251stx %o5, [%i3 + 8]
10252add %l4, 1, %l4
10253
10254P440: !_MEMBAR (FP)
10255membar #StoreLoad
10256
10257P441: !_BLD [22] (FP)
10258wr %g0, 0xf0, %asi
10259sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
10260sub %i0, %i3, %i3
10261ldda [%i3 + 0] %asi, %f32
10262membar #Sync
10263! 3 addresses covered
10264fmovd %f32, %f18
10265fmovs %f18, %f15
10266!---- flushing fp results buffer to %f30 ----
10267fmovd %f0, %f30
10268fmovd %f2, %f30
10269fmovd %f4, %f30
10270fmovd %f6, %f30
10271fmovd %f8, %f30
10272fmovd %f10, %f30
10273fmovd %f12, %f30
10274fmovd %f14, %f30
10275!--
10276fmovs %f19, %f0
10277fmovd %f34, %f18
10278fmovs %f19, %f1
10279
10280P442: !_MEMBAR (FP)
10281
10282P443: !_LD [18] (Int)
10283sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
10284add %i0, %i2, %i2
10285lduw [%i2 + 0], %o5
10286! move %o5(lower) -> %o0(lower)
10287or %o5, %o0, %o0
10288
10289P444: !_CASX [12] (maybe <- 0xbe) (Int)
10290sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
10291add %i0, %i3, %i3
10292ldx [%i3], %o1
10293! move %o1(upper) -> %o1(upper)
10294! move %o1(lower) -> %o1(lower)
10295mov %o1, %l3
10296sllx %l4, 32, %o2
10297add %l4, 1, %l4
10298or %l4, %o2, %o2
10299casx [%i3], %l3, %o2
10300! move %o2(upper) -> %o2(upper)
10301! move %o2(lower) -> %o2(lower)
10302add %l4, 1, %l4
10303
10304P445: !_SWAP [19] (maybe <- 0xc0) (Int)
10305mov %l4, %o3
10306swap [%i2 + 4], %o3
10307! move %o3(lower) -> %o3(upper)
10308sllx %o3, 32, %o3
10309add %l4, 1, %l4
10310
10311P446: !_DWLD [12] (FP)
10312ldd [%i3 + 0], %f2
10313! 2 addresses covered
10314
10315P447: !_LDD [16] (Int)
10316sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
10317sub %i0, %i2, %i2
10318ldd [%i2 + 0], %l6
10319! move %l6(lower) -> %o3(lower)
10320or %l6, %o3, %o3
10321! move %l7(lower) -> %o4(upper)
10322sllx %l7, 32, %o4
10323
10324P448: !_CAS [7] (maybe <- 0xc1) (Int)
10325sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
10326sub %i0, %i3, %i3
10327add %i3, 4, %l7
10328lduw [%l7], %l3
10329mov %l3, %l6
10330! move %l6(lower) -> %o4(lower)
10331or %l6, %o4, %o4
10332!---- flushing int results buffer----
10333mov %o0, %l5
10334mov %o1, %l5
10335mov %o2, %l5
10336mov %o3, %l5
10337mov %o4, %l5
10338mov %l4, %o0
10339cas [%l7], %l6, %o0
10340! move %o0(lower) -> %o0(upper)
10341sllx %o0, 32, %o0
10342add %l4, 1, %l4
10343
10344P449: !_MEMBAR (FP)
10345membar #StoreLoad
10346
10347P450: !_BLD [6] (FP) (CBR)
10348wr %g0, 0xf0, %asi
10349ldda [%i3 + 0] %asi, %f32
10350membar #Sync
10351! 3 addresses covered
10352fmovd %f32, %f4
10353fmovd %f34, %f18
10354fmovs %f19, %f6
10355
10356! cbranch
10357andcc %l0, 1, %g0
10358be,pt %xcc, TARGET450
10359nop
10360RET450:
10361
10362! lfsr step begin
10363srlx %l0, 1, %l6
10364xnor %l6, %l0, %l6
10365sllx %l6, 63, %l6
10366or %l6, %l0, %l0
10367srlx %l0, 1, %l0
10368
10369
10370P451: !_MEMBAR (FP) (CBR)
10371
10372! cbranch
10373andcc %l0, 1, %g0
10374be,pt %xcc, TARGET451
10375nop
10376RET451:
10377
10378! lfsr step begin
10379srlx %l0, 1, %l7
10380xnor %l7, %l0, %l7
10381sllx %l7, 63, %l7
10382or %l7, %l0, %l0
10383srlx %l0, 1, %l0
10384
10385
10386P452: !_DWST [10] (maybe <- 0xc2) (Int)
10387sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
10388add %i0, %i2, %i2
10389sllx %l4, 32, %o5
10390add %l4, 1, %l4
10391or %o5, %l4, %o5
10392stx %o5, [%i2 + 0]
10393add %l4, 1, %l4
10394
10395P453: !_CAS [11] (maybe <- 0xc4) (Int)
10396add %i2, 12, %o5
10397lduw [%o5], %l6
10398mov %l6, %l7
10399! move %l7(lower) -> %o0(lower)
10400or %l7, %o0, %o0
10401mov %l4, %o1
10402cas [%o5], %l7, %o1
10403! move %o1(lower) -> %o1(upper)
10404sllx %o1, 32, %o1
10405add %l4, 1, %l4
10406
10407P454: !_DWLD [10] (Int)
10408ldx [%i2 + 0], %o5
10409! move %o5(upper) -> %o1(lower)
10410srlx %o5, 32, %l7
10411or %l7, %o1, %o1
10412! move %o5(lower) -> %o2(upper)
10413sllx %o5, 32, %o2
10414
10415P455: !_REPLACEMENT [20] (Int)
10416sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
10417sub %i0, %i3, %i3
10418sethi %hi(0x20000), %l3
10419ld [%i3+12], %l7
10420st %l7, [%i3+12]
10421add %i3, %l3, %l6
10422ld [%l6+12], %l7
10423st %l7, [%l6+12]
10424add %l6, %l3, %l6
10425ld [%l6+12], %l7
10426st %l7, [%l6+12]
10427add %l6, %l3, %l6
10428ld [%l6+12], %l7
10429st %l7, [%l6+12]
10430add %l6, %l3, %l6
10431ld [%l6+12], %l7
10432st %l7, [%l6+12]
10433add %l6, %l3, %l6
10434ld [%l6+12], %l7
10435st %l7, [%l6+12]
10436add %l6, %l3, %l6
10437ld [%l6+12], %l7
10438st %l7, [%l6+12]
10439add %l6, %l3, %l6
10440ld [%l6+12], %l7
10441st %l7, [%l6+12]
10442
10443P456: !_DWLD [20] (Int)
10444sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
10445add %i0, %i2, %i2
10446ldx [%i2 + 8], %l3
10447! move %l3(lower) -> %o2(lower)
10448srl %l3, 0, %o5
10449or %o5, %o2, %o2
10450
10451P457: !_DWLD [19] (Int)
10452ldx [%i2 + 0], %o3
10453! move %o3(upper) -> %o3(upper)
10454! move %o3(lower) -> %o3(lower)
10455
10456P458: !_DWLD [11] (Int)
10457sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
10458add %i0, %i3, %i3
10459ldx [%i3 + 8], %o4
10460! move %o4(lower) -> %o4(upper)
10461sllx %o4, 32, %o4
10462
10463P459: !_REPLACEMENT [19] (Int) (Branch target of P255)
10464sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
10465sub %i0, %i2, %i2
10466sethi %hi(0x20000), %l6
10467ld [%i2+4], %o5
10468st %o5, [%i2+4]
10469add %i2, %l6, %l7
10470ld [%l7+4], %o5
10471st %o5, [%l7+4]
10472add %l7, %l6, %l7
10473ld [%l7+4], %o5
10474st %o5, [%l7+4]
10475add %l7, %l6, %l7
10476ld [%l7+4], %o5
10477st %o5, [%l7+4]
10478add %l7, %l6, %l7
10479ld [%l7+4], %o5
10480st %o5, [%l7+4]
10481add %l7, %l6, %l7
10482ld [%l7+4], %o5
10483st %o5, [%l7+4]
10484add %l7, %l6, %l7
10485ld [%l7+4], %o5
10486st %o5, [%l7+4]
10487add %l7, %l6, %l7
10488ld [%l7+4], %o5
10489st %o5, [%l7+4]
10490ba P460
10491nop
10492
10493TARGET255:
10494ba RET255
10495nop
10496
10497
10498P460: !_SWAP [0] (maybe <- 0xc5) (Int)
10499mov %l4, %l7
10500swap [%i0 + 0], %l7
10501! move %l7(lower) -> %o4(lower)
10502srl %l7, 0, %l3
10503or %l3, %o4, %o4
10504!---- flushing int results buffer----
10505mov %o0, %l5
10506mov %o1, %l5
10507mov %o2, %l5
10508mov %o3, %l5
10509mov %o4, %l5
10510add %l4, 1, %l4
10511
10512P461: !_CASX [23] (maybe <- 0xc6) (Int)
10513sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
10514sub %i0, %i3, %i3
10515add %i3, 8, %l3
10516ldx [%l3], %o0
10517! move %o0(upper) -> %o0(upper)
10518! move %o0(lower) -> %o0(lower)
10519mov %o0, %o5
10520mov %l4, %o1
10521casx [%l3], %o5, %o1
10522! move %o1(upper) -> %o1(upper)
10523! move %o1(lower) -> %o1(lower)
10524add %l4, 1, %l4
10525
10526P462: !_DWLD [20] (Int) (LE)
10527wr %g0, 0x88, %asi
10528sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
10529add %i0, %i2, %i2
10530ldxa [%i2 + 8] %asi, %l3
10531! move %l3(upper) -> %o2(upper)
10532or %l3, %g0, %o2
10533
10534P463: !_LD [18] (Int)
10535lduw [%i2 + 0], %l7
10536! move %l7(lower) -> %o2(lower)
10537srlx %o2, 32, %o2
10538sllx %o2, 32, %o2
10539or %l7, %o2, %o2
10540
10541P464: !_CAS [8] (maybe <- 0xc7) (Int)
10542sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
10543sub %i0, %i3, %i3
10544add %i3, 12, %l3
10545lduw [%l3], %o3
10546mov %o3, %o5
10547! move %o5(lower) -> %o3(upper)
10548sllx %o5, 32, %o3
10549mov %l4, %l7
10550cas [%l3], %o5, %l7
10551! move %l7(lower) -> %o3(lower)
10552srl %l7, 0, %o5
10553or %o5, %o3, %o3
10554add %l4, 1, %l4
10555
10556P465: !_ST [9] (maybe <- 0x3f80008a) (FP)
10557sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
10558add %i0, %i2, %i2
10559! preparing store val #0, next val will be in f20
10560fmovs %f16, %f20
10561fadds %f16, %f17, %f16
10562st %f20, [%i2 + 0 ]
10563
10564P466: !_SWAP [1] (maybe <- 0xc8) (Int)
10565mov %l4, %o4
10566swap [%i0 + 4], %o4
10567! move %o4(lower) -> %o4(upper)
10568sllx %o4, 32, %o4
10569add %l4, 1, %l4
10570
10571P467: !_ST_BINIT [8] (maybe <- 0xc9) (Int)
10572wr %g0, 0xe2, %asi
10573stwa %l4, [%i3 + 12] %asi
10574add %l4, 1, %l4
10575
10576P468: !_MEMBAR (Int)
10577membar #StoreLoad
10578
10579P469: !_CASX [23] (maybe <- 0xca) (Int)
10580sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
10581sub %i0, %i3, %i3
10582add %i3, 8, %l6
10583ldx [%l6], %o5
10584! move %o5(upper) -> %o4(lower)
10585srlx %o5, 32, %l3
10586or %l3, %o4, %o4
10587!---- flushing int results buffer----
10588mov %o0, %l5
10589mov %o1, %l5
10590mov %o2, %l5
10591mov %o3, %l5
10592mov %o4, %l5
10593! move %o5(lower) -> %o0(upper)
10594sllx %o5, 32, %o0
10595mov %o5, %l3
10596mov %l4, %o5
10597casx [%l6], %l3, %o5
10598! move %o5(upper) -> %o0(lower)
10599srlx %o5, 32, %l3
10600or %l3, %o0, %o0
10601! move %o5(lower) -> %o1(upper)
10602sllx %o5, 32, %o1
10603add %l4, 1, %l4
10604
10605P470: !_CAS [11] (maybe <- 0xcb) (Int)
10606add %i2, 12, %l6
10607lduw [%l6], %o5
10608mov %o5, %l3
10609! move %l3(lower) -> %o1(lower)
10610or %l3, %o1, %o1
10611mov %l4, %o2
10612cas [%l6], %l3, %o2
10613! move %o2(lower) -> %o2(upper)
10614sllx %o2, 32, %o2
10615add %l4, 1, %l4
10616
10617P471: !_MEMBAR (FP)
10618
10619P472: !_BST [13] (maybe <- 0x3f80008b) (FP)
10620wr %g0, 0xf0, %asi
10621sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
10622add %i0, %i2, %i2
10623! preparing store val #0, next val will be in f32
10624fmovs %f16, %f20
10625fadds %f16, %f17, %f16
10626! preparing store val #1, next val will be in f33
10627fmovs %f16, %f21
10628fadds %f16, %f17, %f16
10629! preparing store val #2, next val will be in f35
10630fmovd %f20, %f32
10631fmovs %f16, %f21
10632fadds %f16, %f17, %f16
10633fmovd %f20, %f34
10634membar #Sync
10635stda %f32, [%i2 + 0 ] %asi
10636
10637P473: !_MEMBAR (FP)
10638membar #StoreLoad
10639
10640P474: !_DWLD [11] (Int)
10641sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
10642add %i0, %i3, %i3
10643ldx [%i3 + 8], %l3
10644! move %l3(lower) -> %o2(lower)
10645srl %l3, 0, %o5
10646or %o5, %o2, %o2
10647
10648P475: !_DWST_BINIT [23] (maybe <- 0xcc) (Int)
10649wr %g0, 0xe2, %asi
10650sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
10651sub %i0, %i2, %i2
10652mov %l4, %l6
10653stxa %l6, [%i2 + 8] %asi
10654add %l4, 1, %l4
10655
10656P476: !_MEMBAR (Int)
10657membar #StoreLoad
10658
10659P477: !_DWST_BINIT [12] (maybe <- 0xcd) (Int)
10660wr %g0, 0xe2, %asi
10661sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
10662add %i0, %i3, %i3
10663sllx %l4, 32, %l3
10664add %l4, 1, %l4
10665or %l3, %l4, %l3
10666stxa %l3, [%i3 + 0] %asi
10667add %l4, 1, %l4
10668
10669P478: !_MEMBAR (Int)
10670membar #StoreLoad
10671
10672P479: !_REPLACEMENT [10] (Int)
10673sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
10674sub %i0, %i2, %i2
10675sethi %hi(0x20000), %o5
10676ld [%i2+4], %l6
10677st %l6, [%i2+4]
10678add %i2, %o5, %l3
10679ld [%l3+4], %l6
10680st %l6, [%l3+4]
10681add %l3, %o5, %l3
10682ld [%l3+4], %l6
10683st %l6, [%l3+4]
10684add %l3, %o5, %l3
10685ld [%l3+4], %l6
10686st %l6, [%l3+4]
10687add %l3, %o5, %l3
10688ld [%l3+4], %l6
10689st %l6, [%l3+4]
10690add %l3, %o5, %l3
10691ld [%l3+4], %l6
10692st %l6, [%l3+4]
10693add %l3, %o5, %l3
10694ld [%l3+4], %l6
10695st %l6, [%l3+4]
10696add %l3, %o5, %l3
10697ld [%l3+4], %l6
10698st %l6, [%l3+4]
10699
10700P480: !_ST_BINIT [18] (maybe <- 0xcf) (Int)
10701wr %g0, 0xe2, %asi
10702sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
10703add %i0, %i3, %i3
10704stwa %l4, [%i3 + 0] %asi
10705add %l4, 1, %l4
10706
10707P481: !_MEMBAR (Int)
10708membar #StoreLoad
10709
10710P482: !_CASX [7] (maybe <- 0xd0) (Int) (CBR)
10711sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
10712sub %i0, %i2, %i2
10713ldx [%i2], %o3
10714! move %o3(upper) -> %o3(upper)
10715! move %o3(lower) -> %o3(lower)
10716mov %o3, %l6
10717sllx %l4, 32, %o4
10718add %l4, 1, %l4
10719or %l4, %o4, %o4
10720casx [%i2], %l6, %o4
10721! move %o4(upper) -> %o4(upper)
10722! move %o4(lower) -> %o4(lower)
10723!---- flushing int results buffer----
10724mov %o0, %l5
10725mov %o1, %l5
10726mov %o2, %l5
10727mov %o3, %l5
10728mov %o4, %l5
10729add %l4, 1, %l4
10730
10731! cbranch
10732andcc %l0, 1, %g0
10733be,pn %xcc, TARGET482
10734nop
10735RET482:
10736
10737! lfsr step begin
10738srlx %l0, 1, %l6
10739xnor %l6, %l0, %l6
10740sllx %l6, 63, %l6
10741or %l6, %l0, %l0
10742srlx %l0, 1, %l0
10743
10744
10745P483: !_MEMBAR (FP)
10746membar #StoreLoad
10747
10748P484: !_BLD [11] (FP)
10749wr %g0, 0xf0, %asi
10750sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
10751add %i0, %i3, %i3
10752ldda [%i3 + 0] %asi, %f32
10753membar #Sync
10754! 3 addresses covered
10755fmovd %f32, %f18
10756fmovs %f18, %f7
10757fmovs %f19, %f8
10758fmovd %f34, %f18
10759fmovs %f19, %f9
10760
10761P485: !_MEMBAR (FP)
10762
10763P486: !_REPLACEMENT [14] (Int)
10764sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
10765sub %i0, %i2, %i2
10766sethi %hi(0x20000), %l7
10767ld [%i2+12], %l3
10768st %l3, [%i2+12]
10769add %i2, %l7, %o5
10770ld [%o5+12], %l3
10771st %l3, [%o5+12]
10772add %o5, %l7, %o5
10773ld [%o5+12], %l3
10774st %l3, [%o5+12]
10775add %o5, %l7, %o5
10776ld [%o5+12], %l3
10777st %l3, [%o5+12]
10778add %o5, %l7, %o5
10779ld [%o5+12], %l3
10780st %l3, [%o5+12]
10781add %o5, %l7, %o5
10782ld [%o5+12], %l3
10783st %l3, [%o5+12]
10784add %o5, %l7, %o5
10785ld [%o5+12], %l3
10786st %l3, [%o5+12]
10787add %o5, %l7, %o5
10788ld [%o5+12], %l3
10789st %l3, [%o5+12]
10790
10791P487: !_SWAP [9] (maybe <- 0xd2) (Int) (CBR)
10792mov %l4, %o0
10793swap [%i3 + 0], %o0
10794! move %o0(lower) -> %o0(upper)
10795sllx %o0, 32, %o0
10796add %l4, 1, %l4
10797
10798! cbranch
10799andcc %l0, 1, %g0
10800be,pn %xcc, TARGET487
10801nop
10802RET487:
10803
10804! lfsr step begin
10805srlx %l0, 1, %l3
10806xnor %l3, %l0, %l3
10807sllx %l3, 63, %l3
10808or %l3, %l0, %l0
10809srlx %l0, 1, %l0
10810
10811
10812P488: !_ST [2] (maybe <- 0xd3) (Int) (LE)
10813wr %g0, 0x88, %asi
10814! Change single-word-level endianess (big endian <-> little endian)
10815sethi %hi(0xff00ff00), %l7
10816or %l7, %lo(0xff00ff00), %l7
10817and %l4, %l7, %o5
10818srl %o5, 8, %o5
10819sll %l4, 8, %l6
10820and %l6, %l7, %l6
10821or %l6, %o5, %l6
10822srl %l6, 16, %o5
10823sll %l6, 16, %l6
10824srl %l6, 0, %l6
10825or %l6, %o5, %l6
10826stwa %l6, [%i0 + 12] %asi
10827add %l4, 1, %l4
10828
10829P489: !_CASX [14] (maybe <- 0xd4) (Int)
10830sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
10831add %i0, %i3, %i3
10832add %i3, 8, %l6
10833ldx [%l6], %o5
10834! move %o5(upper) -> %o0(lower)
10835srlx %o5, 32, %l3
10836or %l3, %o0, %o0
10837! move %o5(lower) -> %o1(upper)
10838sllx %o5, 32, %o1
10839mov %o5, %l3
10840mov %l4, %o5
10841casx [%l6], %l3, %o5
10842! move %o5(upper) -> %o1(lower)
10843srlx %o5, 32, %l3
10844or %l3, %o1, %o1
10845! move %o5(lower) -> %o2(upper)
10846sllx %o5, 32, %o2
10847add %l4, 1, %l4
10848
10849P490: !_MEMBAR (FP)
10850
10851P491: !_BST [19] (maybe <- 0x3f80008e) (FP)
10852wr %g0, 0xf0, %asi
10853sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
10854add %i0, %i2, %i2
10855! preparing store val #0, next val will be in f32
10856fmovs %f16, %f20
10857fadds %f16, %f17, %f16
10858! preparing store val #1, next val will be in f33
10859fmovs %f16, %f21
10860fadds %f16, %f17, %f16
10861! preparing store val #2, next val will be in f35
10862fmovd %f20, %f32
10863fmovs %f16, %f21
10864fadds %f16, %f17, %f16
10865fmovd %f20, %f34
10866membar #Sync
10867stda %f32, [%i2 + 0 ] %asi
10868
10869P492: !_MEMBAR (FP)
10870membar #StoreLoad
10871
10872P493: !_ST [6] (maybe <- 0x3f800091) (FP)
10873sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
10874sub %i0, %i3, %i3
10875! preparing store val #0, next val will be in f20
10876fmovs %f16, %f20
10877fadds %f16, %f17, %f16
10878st %f20, [%i3 + 0 ]
10879
10880P494: !_MEMBAR (FP) (Branch target of P243)
10881ba P495
10882nop
10883
10884TARGET243:
10885ba RET243
10886nop
10887
10888
10889P495: !_BSTC [6] (maybe <- 0x3f800092) (FP)
10890wr %g0, 0xe0, %asi
10891! preparing store val #0, next val will be in f32
10892fmovs %f16, %f20
10893fadds %f16, %f17, %f16
10894! preparing store val #1, next val will be in f33
10895fmovs %f16, %f21
10896fadds %f16, %f17, %f16
10897! preparing store val #2, next val will be in f35
10898fmovd %f20, %f32
10899fmovs %f16, %f21
10900fadds %f16, %f17, %f16
10901fmovd %f20, %f34
10902membar #Sync
10903stda %f32, [%i3 + 0 ] %asi
10904
10905P496: !_MEMBAR (FP)
10906membar #StoreLoad
10907
10908P497: !_LD [4] (Int)
10909lduw [%i1 + 4], %l7
10910! move %l7(lower) -> %o2(lower)
10911or %l7, %o2, %o2
10912
10913P498: !_DWST [4] (maybe <- 0xd5) (Int) (Branch target of P927)
10914sllx %l4, 32, %o5
10915add %l4, 1, %l4
10916or %o5, %l4, %o5
10917stx %o5, [%i1 + 0]
10918add %l4, 1, %l4
10919ba P499
10920nop
10921
10922TARGET927:
10923ba RET927
10924nop
10925
10926
10927P499: !_PREFETCH [6] (Int)
10928prefetch [%i3 + 0], 21
10929
10930P500: !_ST [0] (maybe <- 0xd7) (Int)
10931stw %l4, [%i0 + 0 ]
10932add %l4, 1, %l4
10933
10934P501: !_CAS [13] (maybe <- 0xd8) (Int)
10935sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
10936add %i0, %i2, %i2
10937add %i2, 4, %l7
10938lduw [%l7], %o3
10939mov %o3, %l6
10940! move %l6(lower) -> %o3(upper)
10941sllx %l6, 32, %o3
10942mov %l4, %l3
10943cas [%l7], %l6, %l3
10944! move %l3(lower) -> %o3(lower)
10945srl %l3, 0, %l6
10946or %l6, %o3, %o3
10947add %l4, 1, %l4
10948
10949P502: !_DWLD [4] (Int)
10950ldx [%i1 + 0], %o4
10951! move %o4(upper) -> %o4(upper)
10952! move %o4(lower) -> %o4(lower)
10953!---- flushing int results buffer----
10954mov %o0, %l5
10955mov %o1, %l5
10956mov %o2, %l5
10957mov %o3, %l5
10958mov %o4, %l5
10959
10960P503: !_DWST [14] (maybe <- 0xd9) (Int)
10961mov %l4, %o5
10962stx %o5, [%i2 + 8]
10963add %l4, 1, %l4
10964
10965P504: !_MEMBAR (FP)
10966
10967P505: !_BST [5] (maybe <- 0x3f800095) (FP)
10968wr %g0, 0xf0, %asi
10969! preparing store val #0, next val will be in f32
10970fmovs %f16, %f20
10971fadds %f16, %f17, %f16
10972! preparing store val #1, next val will be in f33
10973fmovs %f16, %f21
10974fadds %f16, %f17, %f16
10975! preparing store val #2, next val will be in f35
10976fmovd %f20, %f32
10977fmovs %f16, %f21
10978fadds %f16, %f17, %f16
10979fmovd %f20, %f34
10980membar #Sync
10981stda %f32, [%i1 + 0 ] %asi
10982
10983P506: !_MEMBAR (FP)
10984membar #StoreLoad
10985
10986P507: !_CAS [16] (maybe <- 0xda) (Int)
10987sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
10988sub %i0, %i3, %i3
10989add %i3, 4, %l7
10990lduw [%l7], %o0
10991mov %o0, %l6
10992! move %l6(lower) -> %o0(upper)
10993sllx %l6, 32, %o0
10994mov %l4, %l3
10995cas [%l7], %l6, %l3
10996! move %l3(lower) -> %o0(lower)
10997srl %l3, 0, %l6
10998or %l6, %o0, %o0
10999add %l4, 1, %l4
11000
11001P508: !_MEMBAR (FP)
11002membar #StoreLoad
11003
11004P509: !_BLD [18] (FP)
11005wr %g0, 0xf0, %asi
11006sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
11007add %i0, %i2, %i2
11008ldda [%i2 + 0] %asi, %f32
11009membar #Sync
11010! 3 addresses covered
11011fmovd %f32, %f10
11012fmovd %f34, %f18
11013fmovs %f19, %f12
11014
11015P510: !_MEMBAR (FP)
11016
11017P511: !_PREFETCH [15] (Int)
11018prefetch [%i3 + 0], 20
11019
11020P512: !_MEMBAR (FP)
11021
11022P513: !_BSTC [15] (maybe <- 0x3f800098) (FP)
11023wr %g0, 0xe0, %asi
11024! preparing store val #0, next val will be in f32
11025fmovs %f16, %f20
11026fadds %f16, %f17, %f16
11027! preparing store val #1, next val will be in f33
11028fmovs %f16, %f21
11029fadds %f16, %f17, %f16
11030! preparing store val #2, next val will be in f35
11031fmovd %f20, %f32
11032fmovs %f16, %f21
11033fadds %f16, %f17, %f16
11034fmovd %f20, %f34
11035membar #Sync
11036stda %f32, [%i3 + 0 ] %asi
11037
11038P514: !_MEMBAR (FP)
11039membar #StoreLoad
11040
11041P515: !_CAS [22] (maybe <- 0xdb) (Int)
11042sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
11043sub %i0, %i3, %i3
11044add %i3, 4, %l7
11045lduw [%l7], %o1
11046mov %o1, %l6
11047! move %l6(lower) -> %o1(upper)
11048sllx %l6, 32, %o1
11049mov %l4, %l3
11050cas [%l7], %l6, %l3
11051! move %l3(lower) -> %o1(lower)
11052srl %l3, 0, %l6
11053or %l6, %o1, %o1
11054add %l4, 1, %l4
11055
11056P516: !_ST [0] (maybe <- 0xdc) (Int)
11057stw %l4, [%i0 + 0 ]
11058add %l4, 1, %l4
11059
11060P517: !_SWAP [6] (maybe <- 0xdd) (Int) (LE)
11061wr %g0, 0x88, %asi
11062sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
11063sub %i0, %i2, %i2
11064mov %l4, %o2
11065! Change single-word-level endianess (big endian <-> little endian)
11066sethi %hi(0xff00ff00), %l3
11067or %l3, %lo(0xff00ff00), %l3
11068and %o2, %l3, %l6
11069srl %l6, 8, %l6
11070sll %o2, 8, %o2
11071and %o2, %l3, %o2
11072or %o2, %l6, %o2
11073srl %o2, 16, %l6
11074sll %o2, 16, %o2
11075srl %o2, 0, %o2
11076or %o2, %l6, %o2
11077swapa [%i2 + 0] %asi, %o2
11078! move %o2(lower) -> %o2(upper)
11079sllx %o2, 32, %o2
11080add %l4, 1, %l4
11081
11082P518: !_SWAP [2] (maybe <- 0xde) (Int)
11083mov %l4, %l6
11084swap [%i0 + 12], %l6
11085! move %l6(lower) -> %o2(lower)
11086srl %l6, 0, %o5
11087or %o5, %o2, %o2
11088add %l4, 1, %l4
11089
11090P519: !_DWLD [0] (Int)
11091ldx [%i0 + 0], %o3
11092! move %o3(upper) -> %o3(upper)
11093! move %o3(lower) -> %o3(lower)
11094
11095P520: !_MEMBAR (FP)
11096
11097P521: !_BSTC [19] (maybe <- 0x3f80009b) (FP)
11098wr %g0, 0xe0, %asi
11099sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
11100add %i0, %i3, %i3
11101! preparing store val #0, next val will be in f32
11102fmovs %f16, %f20
11103fadds %f16, %f17, %f16
11104! preparing store val #1, next val will be in f33
11105fmovs %f16, %f21
11106fadds %f16, %f17, %f16
11107! preparing store val #2, next val will be in f35
11108fmovd %f20, %f32
11109fmovs %f16, %f21
11110fadds %f16, %f17, %f16
11111fmovd %f20, %f34
11112membar #Sync
11113stda %f32, [%i3 + 0 ] %asi
11114
11115P522: !_MEMBAR (FP)
11116membar #StoreLoad
11117
11118P523: !_DWST [18] (maybe <- 0xdf) (Int) (LE)
11119wr %g0, 0x88, %asi
11120sllx %l4, 32, %o5
11121add %l4, 1, %l4
11122or %o5, %l4, %l3
11123! Change double-word-level endianess (big endian <-> little endian)
11124sethi %hi(0xff00ff00), %l6
11125or %l6, %lo(0xff00ff00), %l6
11126sllx %l6, 32, %o5
11127or %l6, %o5, %l6
11128and %l3, %l6, %o5
11129srlx %o5, 8, %o5
11130sllx %l3, 8, %l3
11131and %l3, %l6, %l3
11132or %l3, %o5, %l3
11133sethi %hi(0xffff0000), %l6
11134srlx %l3, 16, %o5
11135andn %o5, %l6, %o5
11136andn %l3, %l6, %l3
11137sllx %l3, 16, %l3
11138or %l3, %o5, %l3
11139srlx %l3, 32, %o5
11140sllx %l3, 32, %l3
11141or %l3, %o5, %o5
11142stxa %o5, [%i3 + 0 ] %asi
11143add %l4, 1, %l4
11144
11145P524: !_DWLD [21] (Int)
11146sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
11147sub %i0, %i2, %i2
11148ldx [%i2 + 0], %o4
11149! move %o4(upper) -> %o4(upper)
11150! move %o4(lower) -> %o4(lower)
11151!---- flushing int results buffer----
11152mov %o0, %l5
11153mov %o1, %l5
11154mov %o2, %l5
11155mov %o3, %l5
11156mov %o4, %l5
11157
11158P525: !_DWLD [9] (Int)
11159sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
11160add %i0, %i3, %i3
11161ldx [%i3 + 0], %o0
11162! move %o0(upper) -> %o0(upper)
11163! move %o0(lower) -> %o0(lower)
11164
11165P526: !_REPLACEMENT [1] (Int)
11166sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
11167sub %i0, %i2, %i2
11168sethi %hi(0x20000), %l7
11169ld [%i2+4], %l3
11170st %l3, [%i2+4]
11171add %i2, %l7, %o5
11172ld [%o5+4], %l3
11173st %l3, [%o5+4]
11174add %o5, %l7, %o5
11175ld [%o5+4], %l3
11176st %l3, [%o5+4]
11177add %o5, %l7, %o5
11178ld [%o5+4], %l3
11179st %l3, [%o5+4]
11180add %o5, %l7, %o5
11181ld [%o5+4], %l3
11182st %l3, [%o5+4]
11183add %o5, %l7, %o5
11184ld [%o5+4], %l3
11185st %l3, [%o5+4]
11186add %o5, %l7, %o5
11187ld [%o5+4], %l3
11188st %l3, [%o5+4]
11189add %o5, %l7, %o5
11190ld [%o5+4], %l3
11191st %l3, [%o5+4]
11192
11193P527: !_CASX [15] (maybe <- 0xe1) (Int)
11194sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
11195sub %i0, %i3, %i3
11196ldx [%i3], %o1
11197! move %o1(upper) -> %o1(upper)
11198! move %o1(lower) -> %o1(lower)
11199mov %o1, %l6
11200sllx %l4, 32, %o2
11201add %l4, 1, %l4
11202or %l4, %o2, %o2
11203casx [%i3], %l6, %o2
11204! move %o2(upper) -> %o2(upper)
11205! move %o2(lower) -> %o2(lower)
11206add %l4, 1, %l4
11207
11208P528: !_ST_BINIT [0] (maybe <- 0xe3) (Int)
11209wr %g0, 0xe2, %asi
11210stwa %l4, [%i0 + 0] %asi
11211add %l4, 1, %l4
11212
11213P529: !_MEMBAR (Int)
11214membar #StoreLoad
11215
11216P530: !_CAS [6] (maybe <- 0xe4) (Int) (CBR)
11217sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
11218sub %i0, %i2, %i2
11219lduw [%i2], %o3
11220mov %o3, %l3
11221! move %l3(lower) -> %o3(upper)
11222sllx %l3, 32, %o3
11223mov %l4, %o5
11224cas [%i2], %l3, %o5
11225! move %o5(lower) -> %o3(lower)
11226srl %o5, 0, %l3
11227or %l3, %o3, %o3
11228add %l4, 1, %l4
11229
11230! cbranch
11231andcc %l0, 1, %g0
11232be,pt %xcc, TARGET530
11233nop
11234RET530:
11235
11236! lfsr step begin
11237srlx %l0, 1, %l3
11238xnor %l3, %l0, %l3
11239sllx %l3, 63, %l3
11240or %l3, %l0, %l0
11241srlx %l0, 1, %l0
11242
11243
11244P531: !_DWST [13] (maybe <- 0xe5) (Int) (LE)
11245wr %g0, 0x88, %asi
11246sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
11247add %i0, %i3, %i3
11248sllx %l4, 32, %l6
11249add %l4, 1, %l4
11250or %l6, %l4, %l7
11251! Change double-word-level endianess (big endian <-> little endian)
11252sethi %hi(0xff00ff00), %o5
11253or %o5, %lo(0xff00ff00), %o5
11254sllx %o5, 32, %l6
11255or %o5, %l6, %o5
11256and %l7, %o5, %l6
11257srlx %l6, 8, %l6
11258sllx %l7, 8, %l7
11259and %l7, %o5, %l7
11260or %l7, %l6, %l7
11261sethi %hi(0xffff0000), %o5
11262srlx %l7, 16, %l6
11263andn %l6, %o5, %l6
11264andn %l7, %o5, %l7
11265sllx %l7, 16, %l7
11266or %l7, %l6, %l7
11267srlx %l7, 32, %l6
11268sllx %l7, 32, %l7
11269or %l7, %l6, %l6
11270stxa %l6, [%i3 + 0 ] %asi
11271add %l4, 1, %l4
11272
11273P532: !_DWST [11] (maybe <- 0xe7) (Int)
11274sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
11275add %i0, %i2, %i2
11276mov %l4, %l3
11277stx %l3, [%i2 + 8]
11278add %l4, 1, %l4
11279
11280P533: !_CASX [16] (maybe <- 0xe8) (Int) (LE)
11281sllx %l4, 32, %l3
11282add %l4, 1, %l4
11283or %l4, %l3, %l3
11284! Change double-word-level endianess (big endian <-> little endian)
11285sethi %hi(0xff00ff00), %o5
11286or %o5, %lo(0xff00ff00), %o5
11287sllx %o5, 32, %l6
11288or %o5, %l6, %o5
11289and %l3, %o5, %l6
11290srlx %l6, 8, %l6
11291sllx %l3, 8, %l3
11292and %l3, %o5, %l3
11293or %l3, %l6, %l3
11294sethi %hi(0xffff0000), %o5
11295srlx %l3, 16, %l6
11296andn %l6, %o5, %l6
11297andn %l3, %o5, %l3
11298sllx %l3, 16, %l3
11299or %l3, %l6, %l3
11300srlx %l3, 32, %l6
11301sllx %l3, 32, %l3
11302or %l3, %l6, %l6
11303wr %g0, 0x88, %asi
11304sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
11305sub %i0, %i3, %i3
11306ldxa [%i3] %asi, %l7
11307! move %l7(lower) -> %o4(upper)
11308sllx %l7, 32, %o4
11309! move %l7(upper) -> %o4(lower)
11310srlx %l7, 32, %o5
11311or %o5, %o4, %o4
11312!---- flushing int results buffer----
11313mov %o0, %l5
11314mov %o1, %l5
11315mov %o2, %l5
11316mov %o3, %l5
11317mov %o4, %l5
11318mov %l7, %o5
11319mov %l6, %l7
11320casxa [%i3] %asi, %o5, %l7
11321! move %l7(lower) -> %o0(upper)
11322sllx %l7, 32, %o0
11323! move %l7(upper) -> %o0(lower)
11324srlx %l7, 32, %o5
11325or %o5, %o0, %o0
11326add %l4, 1, %l4
11327
11328P534: !_ST [21] (maybe <- 0xea) (Int) (Branch target of P396)
11329sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
11330sub %i0, %i2, %i2
11331stw %l4, [%i2 + 0 ]
11332add %l4, 1, %l4
11333ba P535
11334nop
11335
11336TARGET396:
11337ba RET396
11338nop
11339
11340
11341P535: !_DWST_BINIT [19] (maybe <- 0xeb) (Int)
11342wr %g0, 0xe2, %asi
11343sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
11344add %i0, %i3, %i3
11345sllx %l4, 32, %l7
11346add %l4, 1, %l4
11347or %l7, %l4, %l7
11348stxa %l7, [%i3 + 0] %asi
11349add %l4, 1, %l4
11350
11351P536: !_MEMBAR (Int)
11352
11353P537: !_BST [6] (maybe <- 0x3f80009e) (FP)
11354wr %g0, 0xf0, %asi
11355sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
11356sub %i0, %i2, %i2
11357! preparing store val #0, next val will be in f32
11358fmovs %f16, %f20
11359fadds %f16, %f17, %f16
11360! preparing store val #1, next val will be in f33
11361fmovs %f16, %f21
11362fadds %f16, %f17, %f16
11363! preparing store val #2, next val will be in f35
11364fmovd %f20, %f32
11365fmovs %f16, %f21
11366fadds %f16, %f17, %f16
11367fmovd %f20, %f34
11368membar #Sync
11369stda %f32, [%i2 + 0 ] %asi
11370
11371P538: !_MEMBAR (FP)
11372membar #StoreLoad
11373
11374P539: !_SWAP [4] (maybe <- 0xed) (Int) (LE)
11375wr %g0, 0x88, %asi
11376mov %l4, %o1
11377! Change single-word-level endianess (big endian <-> little endian)
11378sethi %hi(0xff00ff00), %l3
11379or %l3, %lo(0xff00ff00), %l3
11380and %o1, %l3, %l6
11381srl %l6, 8, %l6
11382sll %o1, 8, %o1
11383and %o1, %l3, %o1
11384or %o1, %l6, %o1
11385srl %o1, 16, %l6
11386sll %o1, 16, %o1
11387srl %o1, 0, %o1
11388or %o1, %l6, %o1
11389swapa [%i1 + 4] %asi, %o1
11390! move %o1(lower) -> %o1(upper)
11391sllx %o1, 32, %o1
11392add %l4, 1, %l4
11393
11394P540: !_MEMBAR (FP)
11395
11396P541: !_BSTC [18] (maybe <- 0x3f8000a1) (FP)
11397wr %g0, 0xe0, %asi
11398! preparing store val #0, next val will be in f32
11399fmovs %f16, %f20
11400fadds %f16, %f17, %f16
11401! preparing store val #1, next val will be in f33
11402fmovs %f16, %f21
11403fadds %f16, %f17, %f16
11404! preparing store val #2, next val will be in f35
11405fmovd %f20, %f32
11406fmovs %f16, %f21
11407fadds %f16, %f17, %f16
11408fmovd %f20, %f34
11409membar #Sync
11410stda %f32, [%i3 + 0 ] %asi
11411
11412P542: !_MEMBAR (FP) (CBR)
11413membar #StoreLoad
11414
11415! cbranch
11416andcc %l0, 1, %g0
11417be,pn %xcc, TARGET542
11418nop
11419RET542:
11420
11421! lfsr step begin
11422srlx %l0, 1, %l7
11423xnor %l7, %l0, %l7
11424sllx %l7, 63, %l7
11425or %l7, %l0, %l0
11426srlx %l0, 1, %l0
11427
11428
11429P543: !_LDD [3] (Int) (Branch target of P949)
11430ldd [%i1 + 0], %l6
11431! move %l6(lower) -> %o1(lower)
11432or %l6, %o1, %o1
11433! move %l7(lower) -> %o2(upper)
11434sllx %l7, 32, %o2
11435ba P544
11436nop
11437
11438TARGET949:
11439ba RET949
11440nop
11441
11442
11443P544: !_SWAP [16] (maybe <- 0xee) (Int)
11444sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
11445sub %i0, %i3, %i3
11446mov %l4, %l7
11447swap [%i3 + 4], %l7
11448! move %l7(lower) -> %o2(lower)
11449srl %l7, 0, %l3
11450or %l3, %o2, %o2
11451add %l4, 1, %l4
11452
11453P545: !_CAS [23] (maybe <- 0xef) (Int)
11454sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
11455sub %i0, %i2, %i2
11456add %i2, 12, %l3
11457lduw [%l3], %o3
11458mov %o3, %o5
11459! move %o5(lower) -> %o3(upper)
11460sllx %o5, 32, %o3
11461mov %l4, %l7
11462cas [%l3], %o5, %l7
11463! move %l7(lower) -> %o3(lower)
11464srl %l7, 0, %o5
11465or %o5, %o3, %o3
11466add %l4, 1, %l4
11467
11468P546: !_LDD [23] (Int)
11469ldd [%i2 + 8], %l6
11470! move %l7(lower) -> %o4(upper)
11471sllx %l7, 32, %o4
11472
11473P547: !_REPLACEMENT [21] (Int)
11474sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
11475sub %i0, %i3, %i3
11476sethi %hi(0x20000), %l3
11477ld [%i3+0], %l7
11478st %l7, [%i3+0]
11479add %i3, %l3, %l6
11480ld [%l6+0], %l7
11481st %l7, [%l6+0]
11482add %l6, %l3, %l6
11483ld [%l6+0], %l7
11484st %l7, [%l6+0]
11485add %l6, %l3, %l6
11486ld [%l6+0], %l7
11487st %l7, [%l6+0]
11488add %l6, %l3, %l6
11489ld [%l6+0], %l7
11490st %l7, [%l6+0]
11491add %l6, %l3, %l6
11492ld [%l6+0], %l7
11493st %l7, [%l6+0]
11494add %l6, %l3, %l6
11495ld [%l6+0], %l7
11496st %l7, [%l6+0]
11497add %l6, %l3, %l6
11498ld [%l6+0], %l7
11499st %l7, [%l6+0]
11500
11501P548: !_LDD [14] (Int)
11502sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
11503add %i0, %i2, %i2
11504ldd [%i2 + 8], %l6
11505! move %l7(lower) -> %o4(lower)
11506or %l7, %o4, %o4
11507!---- flushing int results buffer----
11508mov %o0, %l5
11509mov %o1, %l5
11510mov %o2, %l5
11511mov %o3, %l5
11512mov %o4, %l5
11513
11514P549: !_MEMBAR (FP)
11515membar #StoreLoad
11516
11517P550: !_BLD [19] (FP)
11518wr %g0, 0xf0, %asi
11519sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
11520add %i0, %i3, %i3
11521ldda [%i3 + 0] %asi, %f32
11522membar #Sync
11523! 3 addresses covered
11524fmovd %f32, %f18
11525fmovs %f18, %f13
11526fmovs %f19, %f14
11527fmovd %f34, %f18
11528fmovs %f19, %f15
11529!---- flushing fp results buffer to %f30 ----
11530fmovd %f0, %f30
11531fmovd %f2, %f30
11532fmovd %f4, %f30
11533fmovd %f6, %f30
11534fmovd %f8, %f30
11535fmovd %f10, %f30
11536fmovd %f12, %f30
11537fmovd %f14, %f30
11538!--
11539
11540P551: !_MEMBAR (FP)
11541
11542P552: !_ST_BINIT [7] (maybe <- 0xf0) (Int)
11543wr %g0, 0xe2, %asi
11544sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
11545sub %i0, %i2, %i2
11546stwa %l4, [%i2 + 4] %asi
11547add %l4, 1, %l4
11548
11549P553: !_MEMBAR (Int)
11550membar #StoreLoad
11551
11552P554: !_BLD [15] (FP)
11553wr %g0, 0xf0, %asi
11554sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
11555sub %i0, %i3, %i3
11556ldda [%i3 + 0] %asi, %f0
11557membar #Sync
11558! 3 addresses covered
11559fmovs %f3, %f2
11560
11561P555: !_MEMBAR (FP)
11562
11563P556: !_DWST_BINIT [18] (maybe <- 0xf1) (Int)
11564wr %g0, 0xe2, %asi
11565sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
11566add %i0, %i2, %i2
11567sllx %l4, 32, %o5
11568add %l4, 1, %l4
11569or %o5, %l4, %o5
11570stxa %o5, [%i2 + 0] %asi
11571add %l4, 1, %l4
11572
11573P557: !_MEMBAR (Int)
11574membar #StoreLoad
11575
11576P558: !_DWST_BINIT [2] (maybe <- 0xf3) (Int)
11577wr %g0, 0xe2, %asi
11578mov %l4, %l7
11579stxa %l7, [%i0 + 8] %asi
11580add %l4, 1, %l4
11581
11582P559: !_MEMBAR (Int)
11583membar #StoreLoad
11584
11585P560: !_DWST_BINIT [3] (maybe <- 0xf4) (Int)
11586wr %g0, 0xe2, %asi
11587sllx %l4, 32, %l6
11588add %l4, 1, %l4
11589or %l6, %l4, %l6
11590stxa %l6, [%i1 + 0] %asi
11591add %l4, 1, %l4
11592
11593P561: !_MEMBAR (Int)
11594membar #StoreLoad
11595
11596P562: !_LDD [12] (Int)
11597sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
11598add %i0, %i3, %i3
11599ldd [%i3 + 0], %l6
11600! move %l6(lower) -> %o0(upper)
11601sllx %l6, 32, %o0
11602! move %l7(lower) -> %o0(lower)
11603or %l7, %o0, %o0
11604
11605P563: !_MEMBAR (FP)
11606
11607P564: !_BSTC [6] (maybe <- 0x3f8000a4) (FP)
11608wr %g0, 0xe0, %asi
11609sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
11610sub %i0, %i2, %i2
11611! preparing store val #0, next val will be in f32
11612fmovs %f16, %f20
11613fadds %f16, %f17, %f16
11614! preparing store val #1, next val will be in f33
11615fmovs %f16, %f21
11616fadds %f16, %f17, %f16
11617! preparing store val #2, next val will be in f35
11618fmovd %f20, %f32
11619fmovs %f16, %f21
11620fadds %f16, %f17, %f16
11621fmovd %f20, %f34
11622membar #Sync
11623stda %f32, [%i2 + 0 ] %asi
11624
11625P565: !_MEMBAR (FP)
11626membar #StoreLoad
11627
11628P566: !_ST_BINIT [6] (maybe <- 0xf6) (Int)
11629wr %g0, 0xe2, %asi
11630stwa %l4, [%i2 + 0] %asi
11631add %l4, 1, %l4
11632
11633P567: !_MEMBAR (Int)
11634membar #StoreLoad
11635
11636P568: !_SWAP [3] (maybe <- 0xf7) (Int)
11637mov %l4, %o1
11638swap [%i1 + 0], %o1
11639! move %o1(lower) -> %o1(upper)
11640sllx %o1, 32, %o1
11641add %l4, 1, %l4
11642
11643P569: !_DWST [6] (maybe <- 0xf8) (Int)
11644sllx %l4, 32, %l6
11645add %l4, 1, %l4
11646or %l6, %l4, %l6
11647stx %l6, [%i2 + 0]
11648add %l4, 1, %l4
11649
11650P570: !_MEMBAR (FP) (Branch target of P482)
11651ba P571
11652nop
11653
11654TARGET482:
11655ba RET482
11656nop
11657
11658
11659P571: !_BST [20] (maybe <- 0x3f8000a7) (FP)
11660wr %g0, 0xf0, %asi
11661sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
11662add %i0, %i3, %i3
11663! preparing store val #0, next val will be in f32
11664fmovs %f16, %f20
11665fadds %f16, %f17, %f16
11666! preparing store val #1, next val will be in f33
11667fmovs %f16, %f21
11668fadds %f16, %f17, %f16
11669! preparing store val #2, next val will be in f35
11670fmovd %f20, %f32
11671fmovs %f16, %f21
11672fadds %f16, %f17, %f16
11673fmovd %f20, %f34
11674membar #Sync
11675stda %f32, [%i3 + 0 ] %asi
11676
11677P572: !_MEMBAR (FP)
11678membar #StoreLoad
11679
11680P573: !_LD [13] (Int)
11681sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
11682add %i0, %i2, %i2
11683lduw [%i2 + 4], %l3
11684! move %l3(lower) -> %o1(lower)
11685or %l3, %o1, %o1
11686
11687P574: !_DWST_BINIT [4] (maybe <- 0xfa) (Int)
11688wr %g0, 0xe2, %asi
11689sllx %l4, 32, %l6
11690add %l4, 1, %l4
11691or %l6, %l4, %l6
11692stxa %l6, [%i1 + 0] %asi
11693add %l4, 1, %l4
11694
11695P575: !_MEMBAR (Int)
11696membar #StoreLoad
11697
11698P576: !_DWST [3] (maybe <- 0xfc) (Int)
11699!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
11700!Logical addr: 3
11701
11702sethi %hi(0x200000), %l3
11703sub %i1, %l3, %i1
11704sllx %l4, 32, %l6
11705add %l4, 1, %l4
11706or %l6, %l4, %l6
11707stx %l6, [%i1 + 0]
11708add %l4, 1, %l4
11709
11710P577: !_MEMBAR (FP)
11711
11712P578: !_BSTC [8] (maybe <- 0x3f8000aa) (FP)
11713wr %g0, 0xe0, %asi
11714sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
11715sub %i0, %i3, %i3
11716! preparing store val #0, next val will be in f32
11717fmovs %f16, %f20
11718fadds %f16, %f17, %f16
11719! preparing store val #1, next val will be in f33
11720fmovs %f16, %f21
11721fadds %f16, %f17, %f16
11722! preparing store val #2, next val will be in f35
11723fmovd %f20, %f32
11724fmovs %f16, %f21
11725fadds %f16, %f17, %f16
11726fmovd %f20, %f34
11727membar #Sync
11728stda %f32, [%i3 + 0 ] %asi
11729
11730P579: !_MEMBAR (FP)
11731membar #StoreLoad
11732
11733P580: !_SWAP [6] (maybe <- 0xfe) (Int)
11734mov %l4, %o2
11735swap [%i3 + 0], %o2
11736! move %o2(lower) -> %o2(upper)
11737sllx %o2, 32, %o2
11738add %l4, 1, %l4
11739
11740P581: !_MEMBAR (FP)
11741
11742P582: !_BST [6] (maybe <- 0x3f8000ad) (FP)
11743wr %g0, 0xf0, %asi
11744! preparing store val #0, next val will be in f32
11745fmovs %f16, %f20
11746fadds %f16, %f17, %f16
11747! preparing store val #1, next val will be in f33
11748fmovs %f16, %f21
11749fadds %f16, %f17, %f16
11750! preparing store val #2, next val will be in f35
11751fmovd %f20, %f32
11752fmovs %f16, %f21
11753fadds %f16, %f17, %f16
11754fmovd %f20, %f34
11755membar #Sync
11756stda %f32, [%i3 + 0 ] %asi
11757
11758P583: !_MEMBAR (FP)
11759membar #StoreLoad
11760
11761P584: !_LDD [19] (Int)
11762sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
11763add %i0, %i2, %i2
11764ldd [%i2 + 0], %l6
11765! move %l6(lower) -> %o2(lower)
11766or %l6, %o2, %o2
11767! move %l7(lower) -> %o3(upper)
11768sllx %l7, 32, %o3
11769
11770P585: !_ST_BINIT [9] (maybe <- 0xff) (Int)
11771wr %g0, 0xe2, %asi
11772sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
11773add %i0, %i3, %i3
11774stwa %l4, [%i3 + 0] %asi
11775add %l4, 1, %l4
11776
11777P586: !_MEMBAR (Int)
11778membar #StoreLoad
11779
11780P587: !_DWST_BINIT [2] (maybe <- 0x100) (Int)
11781wr %g0, 0xe2, %asi
11782mov %l4, %o5
11783stxa %o5, [%i0 + 8] %asi
11784add %l4, 1, %l4
11785
11786P588: !_MEMBAR (Int)
11787membar #StoreLoad
11788
11789P589: !_DWST [0] (maybe <- 0x101) (Int)
11790sllx %l4, 32, %l7
11791add %l4, 1, %l4
11792or %l7, %l4, %l7
11793stx %l7, [%i0 + 0]
11794add %l4, 1, %l4
11795
11796P590: !_ST [2] (maybe <- 0x103) (Int)
11797stw %l4, [%i0 + 12 ]
11798add %l4, 1, %l4
11799
11800P591: !_MEMBAR (FP)
11801
11802P592: !_BST [17] (maybe <- 0x3f8000b0) (FP)
11803wr %g0, 0xf0, %asi
11804sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
11805sub %i0, %i2, %i2
11806! preparing store val #0, next val will be in f32
11807fmovs %f16, %f20
11808fadds %f16, %f17, %f16
11809! preparing store val #1, next val will be in f33
11810fmovs %f16, %f21
11811fadds %f16, %f17, %f16
11812! preparing store val #2, next val will be in f35
11813fmovd %f20, %f32
11814fmovs %f16, %f21
11815fadds %f16, %f17, %f16
11816fmovd %f20, %f34
11817membar #Sync
11818stda %f32, [%i2 + 0 ] %asi
11819
11820P593: !_MEMBAR (FP)
11821membar #StoreLoad
11822
11823P594: !_ST_BINIT [21] (maybe <- 0x104) (Int)
11824wr %g0, 0xe2, %asi
11825sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
11826sub %i0, %i3, %i3
11827stwa %l4, [%i3 + 0] %asi
11828add %l4, 1, %l4
11829
11830P595: !_MEMBAR (Int)
11831membar #StoreLoad
11832
11833P596: !_DWST [12] (maybe <- 0x105) (Int)
11834sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
11835add %i0, %i2, %i2
11836sllx %l4, 32, %l7
11837add %l4, 1, %l4
11838or %l7, %l4, %l7
11839stx %l7, [%i2 + 0]
11840add %l4, 1, %l4
11841
11842P597: !_CASX [3] (maybe <- 0x107) (Int) (CBR)
11843ldx [%i1], %l3
11844! move %l3(upper) -> %o3(lower)
11845srlx %l3, 32, %l6
11846or %l6, %o3, %o3
11847! move %l3(lower) -> %o4(upper)
11848sllx %l3, 32, %o4
11849mov %l3, %l6
11850sllx %l4, 32, %l3
11851add %l4, 1, %l4
11852or %l4, %l3, %l3
11853casx [%i1], %l6, %l3
11854! move %l3(upper) -> %o4(lower)
11855srlx %l3, 32, %l6
11856or %l6, %o4, %o4
11857!---- flushing int results buffer----
11858mov %o0, %l5
11859mov %o1, %l5
11860mov %o2, %l5
11861mov %o3, %l5
11862mov %o4, %l5
11863! move %l3(lower) -> %o0(upper)
11864sllx %l3, 32, %o0
11865add %l4, 1, %l4
11866
11867! cbranch
11868andcc %l0, 1, %g0
11869be,pn %xcc, TARGET597
11870nop
11871RET597:
11872
11873! lfsr step begin
11874srlx %l0, 1, %l6
11875xnor %l6, %l0, %l6
11876sllx %l6, 63, %l6
11877or %l6, %l0, %l0
11878srlx %l0, 1, %l0
11879
11880
11881P598: !_PREFETCH [7] (Int)
11882sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
11883sub %i0, %i3, %i3
11884prefetch [%i3 + 4], 18
11885
11886P599: !_DWLD [10] (Int)
11887sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
11888add %i0, %i2, %i2
11889ldx [%i2 + 0], %o5
11890! move %o5(upper) -> %o0(lower)
11891srlx %o5, 32, %l7
11892or %l7, %o0, %o0
11893! move %o5(lower) -> %o1(upper)
11894sllx %o5, 32, %o1
11895
11896P600: !_CASX [18] (maybe <- 0x109) (Int)
11897sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
11898add %i0, %i3, %i3
11899ldx [%i3], %o5
11900! move %o5(upper) -> %o1(lower)
11901srlx %o5, 32, %l3
11902or %l3, %o1, %o1
11903! move %o5(lower) -> %o2(upper)
11904sllx %o5, 32, %o2
11905mov %o5, %l3
11906sllx %l4, 32, %o5
11907add %l4, 1, %l4
11908or %l4, %o5, %o5
11909casx [%i3], %l3, %o5
11910! move %o5(upper) -> %o2(lower)
11911srlx %o5, 32, %l3
11912or %l3, %o2, %o2
11913! move %o5(lower) -> %o3(upper)
11914sllx %o5, 32, %o3
11915add %l4, 1, %l4
11916
11917P601: !_SWAP [12] (maybe <- 0x10b) (Int) (Branch target of P660)
11918sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
11919add %i0, %i2, %i2
11920mov %l4, %l7
11921swap [%i2 + 0], %l7
11922! move %l7(lower) -> %o3(lower)
11923srl %l7, 0, %l3
11924or %l3, %o3, %o3
11925add %l4, 1, %l4
11926ba P602
11927nop
11928
11929TARGET660:
11930ba RET660
11931nop
11932
11933
11934P602: !_DWLD [8] (Int)
11935sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
11936sub %i0, %i3, %i3
11937ldx [%i3 + 8], %o4
11938! move %o4(lower) -> %o4(upper)
11939sllx %o4, 32, %o4
11940
11941P603: !_MEMBAR (FP)
11942membar #StoreLoad
11943
11944P604: !_BLD [2] (FP)
11945wr %g0, 0xf0, %asi
11946ldda [%i0 + 0] %asi, %f32
11947membar #Sync
11948! 3 addresses covered
11949fmovd %f32, %f18
11950fmovs %f18, %f3
11951fmovs %f19, %f4
11952fmovd %f34, %f18
11953fmovs %f19, %f5
11954
11955P605: !_MEMBAR (FP)
11956
11957P606: !_SWAP [7] (maybe <- 0x10c) (Int)
11958mov %l4, %o5
11959swap [%i3 + 4], %o5
11960! move %o5(lower) -> %o4(lower)
11961srl %o5, 0, %l6
11962or %l6, %o4, %o4
11963!---- flushing int results buffer----
11964mov %o0, %l5
11965mov %o1, %l5
11966mov %o2, %l5
11967mov %o3, %l5
11968mov %o4, %l5
11969add %l4, 1, %l4
11970
11971P607: !_ST_BINIT [18] (maybe <- 0x10d) (Int)
11972wr %g0, 0xe2, %asi
11973sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
11974add %i0, %i2, %i2
11975stwa %l4, [%i2 + 0] %asi
11976add %l4, 1, %l4
11977
11978P608: !_MEMBAR (Int)
11979membar #StoreLoad
11980
11981P609: !_ST [15] (maybe <- 0x10e) (Int) (CBR) (Branch target of P633)
11982sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
11983sub %i0, %i3, %i3
11984stw %l4, [%i3 + 0 ]
11985add %l4, 1, %l4
11986
11987! cbranch
11988andcc %l0, 1, %g0
11989be,pn %xcc, TARGET609
11990nop
11991RET609:
11992
11993! lfsr step begin
11994srlx %l0, 1, %l7
11995xnor %l7, %l0, %l7
11996sllx %l7, 63, %l7
11997or %l7, %l0, %l0
11998srlx %l0, 1, %l0
11999
12000ba P610
12001nop
12002
12003TARGET633:
12004ba RET633
12005nop
12006
12007
12008P610: !_PREFETCH [18] (Int)
12009prefetch [%i2 + 0], 26
12010
12011P611: !_PREFETCH [10] (Int)
12012sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
12013add %i0, %i2, %i2
12014prefetch [%i2 + 4], 22
12015
12016P612: !_ST_BINIT [23] (maybe <- 0x10f) (Int)
12017wr %g0, 0xe2, %asi
12018sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
12019sub %i0, %i3, %i3
12020stwa %l4, [%i3 + 12] %asi
12021add %l4, 1, %l4
12022
12023P613: !_MEMBAR (Int)
12024membar #StoreLoad
12025
12026P614: !_BLD [8] (FP)
12027wr %g0, 0xf0, %asi
12028sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
12029sub %i0, %i2, %i2
12030ldda [%i2 + 0] %asi, %f32
12031membar #Sync
12032! 3 addresses covered
12033fmovd %f32, %f6
12034fmovd %f34, %f18
12035fmovs %f19, %f8
12036
12037P615: !_MEMBAR (FP)
12038
12039P616: !_DWLD [10] (Int)
12040sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
12041add %i0, %i3, %i3
12042ldx [%i3 + 0], %o0
12043! move %o0(upper) -> %o0(upper)
12044! move %o0(lower) -> %o0(lower)
12045
12046P617: !_CASX [5] (maybe <- 0x110) (Int)
12047add %i1, 8, %l6
12048ldx [%l6], %o1
12049! move %o1(upper) -> %o1(upper)
12050! move %o1(lower) -> %o1(lower)
12051mov %o1, %l3
12052mov %l4, %o2
12053casx [%l6], %l3, %o2
12054! move %o2(upper) -> %o2(upper)
12055! move %o2(lower) -> %o2(lower)
12056add %l4, 1, %l4
12057
12058P618: !_MEMBAR (FP)
12059
12060P619: !_BSTC [23] (maybe <- 0x3f8000b3) (FP) (Branch target of P822)
12061wr %g0, 0xe0, %asi
12062sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
12063sub %i0, %i2, %i2
12064! preparing store val #0, next val will be in f32
12065fmovs %f16, %f20
12066fadds %f16, %f17, %f16
12067! preparing store val #1, next val will be in f33
12068fmovs %f16, %f21
12069fadds %f16, %f17, %f16
12070! preparing store val #2, next val will be in f35
12071fmovd %f20, %f32
12072fmovs %f16, %f21
12073fadds %f16, %f17, %f16
12074fmovd %f20, %f34
12075membar #Sync
12076stda %f32, [%i2 + 0 ] %asi
12077ba P620
12078nop
12079
12080TARGET822:
12081ba RET822
12082nop
12083
12084
12085P620: !_MEMBAR (FP)
12086membar #StoreLoad
12087
12088P621: !_ST [20] (maybe <- 0x111) (Int)
12089sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
12090add %i0, %i3, %i3
12091stw %l4, [%i3 + 12 ]
12092add %l4, 1, %l4
12093
12094P622: !_ST_BINIT [15] (maybe <- 0x112) (Int)
12095wr %g0, 0xe2, %asi
12096sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
12097sub %i0, %i2, %i2
12098stwa %l4, [%i2 + 0] %asi
12099add %l4, 1, %l4
12100
12101P623: !_MEMBAR (Int)
12102
12103P624: !_BSTC [21] (maybe <- 0x3f8000b6) (FP)
12104wr %g0, 0xe0, %asi
12105sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
12106sub %i0, %i3, %i3
12107! preparing store val #0, next val will be in f32
12108fmovs %f16, %f20
12109fadds %f16, %f17, %f16
12110! preparing store val #1, next val will be in f33
12111fmovs %f16, %f21
12112fadds %f16, %f17, %f16
12113! preparing store val #2, next val will be in f35
12114fmovd %f20, %f32
12115fmovs %f16, %f21
12116fadds %f16, %f17, %f16
12117fmovd %f20, %f34
12118membar #Sync
12119stda %f32, [%i3 + 0 ] %asi
12120
12121P625: !_MEMBAR (FP)
12122membar #StoreLoad
12123
12124P626: !_DWST_BINIT [0] (maybe <- 0x113) (Int) (LE)
12125wr %g0, 0xea, %asi
12126sllx %l4, 32, %l3
12127add %l4, 1, %l4
12128or %l3, %l4, %l6
12129! Change double-word-level endianess (big endian <-> little endian)
12130sethi %hi(0xff00ff00), %l7
12131or %l7, %lo(0xff00ff00), %l7
12132sllx %l7, 32, %l3
12133or %l7, %l3, %l7
12134and %l6, %l7, %l3
12135srlx %l3, 8, %l3
12136sllx %l6, 8, %l6
12137and %l6, %l7, %l6
12138or %l6, %l3, %l6
12139sethi %hi(0xffff0000), %l7
12140srlx %l6, 16, %l3
12141andn %l3, %l7, %l3
12142andn %l6, %l7, %l6
12143sllx %l6, 16, %l6
12144or %l6, %l3, %l6
12145srlx %l6, 32, %l3
12146sllx %l6, 32, %l6
12147or %l6, %l3, %l3
12148stxa %l3, [%i0 + 0 ] %asi
12149add %l4, 1, %l4
12150
12151P627: !_MEMBAR (Int) (LE)
12152membar #StoreLoad
12153
12154P628: !_DWST_BINIT [11] (maybe <- 0x115) (Int) (LE)
12155wr %g0, 0xea, %asi
12156sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
12157add %i0, %i2, %i2
12158! Change single-word-level endianess (big endian <-> little endian)
12159sethi %hi(0xff00ff00), %o5
12160or %o5, %lo(0xff00ff00), %o5
12161and %l4, %o5, %l6
12162srl %l6, 8, %l6
12163sll %l4, 8, %l3
12164and %l3, %o5, %l3
12165or %l3, %l6, %l3
12166srl %l3, 16, %l6
12167sll %l3, 16, %l3
12168srl %l3, 0, %l3
12169or %l3, %l6, %l3
12170sllx %l3, 32, %l3
12171stxa %l3, [%i2 + 8 ] %asi
12172add %l4, 1, %l4
12173
12174P629: !_MEMBAR (Int) (LE)
12175
12176P630: !_BST [15] (maybe <- 0x3f8000b9) (FP)
12177wr %g0, 0xf0, %asi
12178sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
12179sub %i0, %i3, %i3
12180! preparing store val #0, next val will be in f32
12181fmovs %f16, %f20
12182fadds %f16, %f17, %f16
12183! preparing store val #1, next val will be in f33
12184fmovs %f16, %f21
12185fadds %f16, %f17, %f16
12186! preparing store val #2, next val will be in f35
12187fmovd %f20, %f32
12188fmovs %f16, %f21
12189fadds %f16, %f17, %f16
12190fmovd %f20, %f34
12191membar #Sync
12192stda %f32, [%i3 + 0 ] %asi
12193
12194P631: !_MEMBAR (FP) (CBR)
12195membar #StoreLoad
12196
12197! cbranch
12198andcc %l0, 1, %g0
12199be,pn %xcc, TARGET631
12200nop
12201RET631:
12202
12203! lfsr step begin
12204srlx %l0, 1, %l6
12205xnor %l6, %l0, %l6
12206sllx %l6, 63, %l6
12207or %l6, %l0, %l0
12208srlx %l0, 1, %l0
12209
12210
12211P632: !_CASX [5] (maybe <- 0x116) (Int)
12212add %i1, 8, %o5
12213ldx [%o5], %o3
12214! move %o3(upper) -> %o3(upper)
12215! move %o3(lower) -> %o3(lower)
12216mov %o3, %l7
12217mov %l4, %o4
12218casx [%o5], %l7, %o4
12219! move %o4(upper) -> %o4(upper)
12220! move %o4(lower) -> %o4(lower)
12221!---- flushing int results buffer----
12222mov %o0, %l5
12223mov %o1, %l5
12224mov %o2, %l5
12225mov %o3, %l5
12226mov %o4, %l5
12227add %l4, 1, %l4
12228
12229P633: !_ST [15] (maybe <- 0x117) (Int) (CBR)
12230stw %l4, [%i3 + 0 ]
12231add %l4, 1, %l4
12232
12233! cbranch
12234andcc %l0, 1, %g0
12235be,pt %xcc, TARGET633
12236nop
12237RET633:
12238
12239! lfsr step begin
12240srlx %l0, 1, %l6
12241xnor %l6, %l0, %l6
12242sllx %l6, 63, %l6
12243or %l6, %l0, %l0
12244srlx %l0, 1, %l0
12245
12246
12247P634: !_SWAP [3] (maybe <- 0x118) (Int)
12248mov %l4, %o0
12249swap [%i1 + 0], %o0
12250! move %o0(lower) -> %o0(upper)
12251sllx %o0, 32, %o0
12252add %l4, 1, %l4
12253
12254P635: !_MEMBAR (FP)
12255
12256P636: !_BST [22] (maybe <- 0x3f8000bc) (FP)
12257wr %g0, 0xf0, %asi
12258sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
12259sub %i0, %i2, %i2
12260! preparing store val #0, next val will be in f32
12261fmovs %f16, %f20
12262fadds %f16, %f17, %f16
12263! preparing store val #1, next val will be in f33
12264fmovs %f16, %f21
12265fadds %f16, %f17, %f16
12266! preparing store val #2, next val will be in f35
12267fmovd %f20, %f32
12268fmovs %f16, %f21
12269fadds %f16, %f17, %f16
12270fmovd %f20, %f34
12271membar #Sync
12272stda %f32, [%i2 + 0 ] %asi
12273
12274P637: !_MEMBAR (FP)
12275
12276P638: !_BST [23] (maybe <- 0x3f8000bf) (FP)
12277wr %g0, 0xf0, %asi
12278! preparing store val #0, next val will be in f32
12279fmovs %f16, %f20
12280fadds %f16, %f17, %f16
12281! preparing store val #1, next val will be in f33
12282fmovs %f16, %f21
12283fadds %f16, %f17, %f16
12284! preparing store val #2, next val will be in f35
12285fmovd %f20, %f32
12286fmovs %f16, %f21
12287fadds %f16, %f17, %f16
12288fmovd %f20, %f34
12289membar #Sync
12290stda %f32, [%i2 + 0 ] %asi
12291
12292P639: !_MEMBAR (FP)
12293membar #StoreLoad
12294
12295P640: !_ST [16] (maybe <- 0x119) (Int) (Branch target of P1001)
12296sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
12297sub %i0, %i3, %i3
12298stw %l4, [%i3 + 4 ]
12299add %l4, 1, %l4
12300ba P641
12301nop
12302
12303TARGET1001:
12304ba RET1001
12305nop
12306
12307
12308P641: !_CASX [4] (maybe <- 0x11a) (Int)
12309ldx [%i1], %l7
12310! move %l7(upper) -> %o0(lower)
12311srlx %l7, 32, %o5
12312or %o5, %o0, %o0
12313! move %l7(lower) -> %o1(upper)
12314sllx %l7, 32, %o1
12315mov %l7, %o5
12316sllx %l4, 32, %l7
12317add %l4, 1, %l4
12318or %l4, %l7, %l7
12319casx [%i1], %o5, %l7
12320! move %l7(upper) -> %o1(lower)
12321srlx %l7, 32, %o5
12322or %o5, %o1, %o1
12323! move %l7(lower) -> %o2(upper)
12324sllx %l7, 32, %o2
12325add %l4, 1, %l4
12326
12327P642: !_DWST_BINIT [16] (maybe <- 0x11c) (Int)
12328wr %g0, 0xe2, %asi
12329sllx %l4, 32, %o5
12330add %l4, 1, %l4
12331or %o5, %l4, %o5
12332stxa %o5, [%i3 + 0] %asi
12333add %l4, 1, %l4
12334
12335P643: !_MEMBAR (Int)
12336membar #StoreLoad
12337
12338P644: !_CASX [1] (maybe <- 0x11e) (Int)
12339ldx [%i0], %l6
12340! move %l6(upper) -> %o2(lower)
12341srlx %l6, 32, %l7
12342or %l7, %o2, %o2
12343! move %l6(lower) -> %o3(upper)
12344sllx %l6, 32, %o3
12345mov %l6, %l7
12346sllx %l4, 32, %l6
12347add %l4, 1, %l4
12348or %l4, %l6, %l6
12349casx [%i0], %l7, %l6
12350! move %l6(upper) -> %o3(lower)
12351srlx %l6, 32, %l7
12352or %l7, %o3, %o3
12353! move %l6(lower) -> %o4(upper)
12354sllx %l6, 32, %o4
12355add %l4, 1, %l4
12356
12357P645: !_LDD [3] (Int)
12358ldd [%i1 + 0], %l6
12359! move %l6(lower) -> %o4(lower)
12360or %l6, %o4, %o4
12361!---- flushing int results buffer----
12362mov %o0, %l5
12363mov %o1, %l5
12364mov %o2, %l5
12365mov %o3, %l5
12366mov %o4, %l5
12367! move %l7(lower) -> %o0(upper)
12368sllx %l7, 32, %o0
12369
12370P646: !_PREFETCH [4] (Int)
12371prefetch [%i1 + 4], 22
12372
12373P647: !_CASX [23] (maybe <- 0x120) (Int)
12374add %i2, 8, %l6
12375ldx [%l6], %o5
12376! move %o5(upper) -> %o0(lower)
12377srlx %o5, 32, %l3
12378or %l3, %o0, %o0
12379! move %o5(lower) -> %o1(upper)
12380sllx %o5, 32, %o1
12381mov %o5, %l3
12382mov %l4, %o5
12383casx [%l6], %l3, %o5
12384! move %o5(upper) -> %o1(lower)
12385srlx %o5, 32, %l3
12386or %l3, %o1, %o1
12387! move %o5(lower) -> %o2(upper)
12388sllx %o5, 32, %o2
12389add %l4, 1, %l4
12390
12391P648: !_MEMBAR (FP)
12392
12393P649: !_BSTC [4] (maybe <- 0x3f8000c2) (FP)
12394wr %g0, 0xe0, %asi
12395! preparing store val #0, next val will be in f32
12396fmovs %f16, %f20
12397fadds %f16, %f17, %f16
12398! preparing store val #1, next val will be in f33
12399fmovs %f16, %f21
12400fadds %f16, %f17, %f16
12401! preparing store val #2, next val will be in f35
12402fmovd %f20, %f32
12403fmovs %f16, %f21
12404fadds %f16, %f17, %f16
12405fmovd %f20, %f34
12406membar #Sync
12407stda %f32, [%i1 + 0 ] %asi
12408
12409P650: !_MEMBAR (FP)
12410membar #StoreLoad
12411
12412P651: !_LDD [8] (Int)
12413sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
12414sub %i0, %i2, %i2
12415ldd [%i2 + 8], %l6
12416! move %l7(lower) -> %o2(lower)
12417or %l7, %o2, %o2
12418
12419P652: !_MEMBAR (FP)
12420
12421P653: !_BSTC [4] (maybe <- 0x3f8000c5) (FP)
12422wr %g0, 0xe0, %asi
12423! preparing store val #0, next val will be in f32
12424fmovs %f16, %f20
12425fadds %f16, %f17, %f16
12426! preparing store val #1, next val will be in f33
12427fmovs %f16, %f21
12428fadds %f16, %f17, %f16
12429! preparing store val #2, next val will be in f35
12430fmovd %f20, %f32
12431fmovs %f16, %f21
12432fadds %f16, %f17, %f16
12433fmovd %f20, %f34
12434membar #Sync
12435stda %f32, [%i1 + 0 ] %asi
12436
12437P654: !_MEMBAR (FP)
12438
12439P655: !_BST [11] (maybe <- 0x3f8000c8) (FP)
12440wr %g0, 0xf0, %asi
12441sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
12442add %i0, %i3, %i3
12443! preparing store val #0, next val will be in f32
12444fmovs %f16, %f20
12445fadds %f16, %f17, %f16
12446! preparing store val #1, next val will be in f33
12447fmovs %f16, %f21
12448fadds %f16, %f17, %f16
12449! preparing store val #2, next val will be in f35
12450fmovd %f20, %f32
12451fmovs %f16, %f21
12452fadds %f16, %f17, %f16
12453fmovd %f20, %f34
12454membar #Sync
12455stda %f32, [%i3 + 0 ] %asi
12456
12457P656: !_MEMBAR (FP)
12458membar #StoreLoad
12459
12460P657: !_CASX [19] (maybe <- 0x121) (Int)
12461sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
12462add %i0, %i2, %i2
12463ldx [%i2], %o3
12464! move %o3(upper) -> %o3(upper)
12465! move %o3(lower) -> %o3(lower)
12466mov %o3, %l7
12467sllx %l4, 32, %o4
12468add %l4, 1, %l4
12469or %l4, %o4, %o4
12470casx [%i2], %l7, %o4
12471! move %o4(upper) -> %o4(upper)
12472! move %o4(lower) -> %o4(lower)
12473!---- flushing int results buffer----
12474mov %o0, %l5
12475mov %o1, %l5
12476mov %o2, %l5
12477mov %o3, %l5
12478mov %o4, %l5
12479add %l4, 1, %l4
12480
12481P658: !_CAS [10] (maybe <- 0x123) (Int)
12482add %i3, 4, %o5
12483lduw [%o5], %o0
12484mov %o0, %l7
12485! move %l7(lower) -> %o0(upper)
12486sllx %l7, 32, %o0
12487mov %l4, %l6
12488cas [%o5], %l7, %l6
12489! move %l6(lower) -> %o0(lower)
12490srl %l6, 0, %l7
12491or %l7, %o0, %o0
12492add %l4, 1, %l4
12493
12494P659: !_MEMBAR (FP)
12495
12496P660: !_BSTC [10] (maybe <- 0x3f8000cb) (FP) (CBR)
12497wr %g0, 0xe0, %asi
12498! preparing store val #0, next val will be in f32
12499fmovs %f16, %f20
12500fadds %f16, %f17, %f16
12501! preparing store val #1, next val will be in f33
12502fmovs %f16, %f21
12503fadds %f16, %f17, %f16
12504! preparing store val #2, next val will be in f35
12505fmovd %f20, %f32
12506fmovs %f16, %f21
12507fadds %f16, %f17, %f16
12508fmovd %f20, %f34
12509membar #Sync
12510stda %f32, [%i3 + 0 ] %asi
12511
12512! cbranch
12513andcc %l0, 1, %g0
12514be,pn %xcc, TARGET660
12515nop
12516RET660:
12517
12518! lfsr step begin
12519srlx %l0, 1, %l6
12520xnor %l6, %l0, %l6
12521sllx %l6, 63, %l6
12522or %l6, %l0, %l0
12523srlx %l0, 1, %l0
12524
12525
12526P661: !_MEMBAR (FP)
12527membar #StoreLoad
12528
12529P662: !_BLD [7] (FP)
12530wr %g0, 0xf0, %asi
12531sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
12532sub %i0, %i3, %i3
12533ldda [%i3 + 0] %asi, %f32
12534membar #Sync
12535! 3 addresses covered
12536fmovd %f32, %f18
12537fmovs %f18, %f9
12538fmovs %f19, %f10
12539fmovd %f34, %f18
12540fmovs %f19, %f11
12541
12542P663: !_MEMBAR (FP) (CBR)
12543
12544! cbranch
12545andcc %l0, 1, %g0
12546be,pn %xcc, TARGET663
12547nop
12548RET663:
12549
12550! lfsr step begin
12551srlx %l0, 1, %l7
12552xnor %l7, %l0, %l7
12553sllx %l7, 63, %l7
12554or %l7, %l0, %l0
12555srlx %l0, 1, %l0
12556
12557
12558P664: !_ST_BINIT [8] (maybe <- 0x124) (Int) (LE) (Branch target of P451)
12559wr %g0, 0xea, %asi
12560! Change single-word-level endianess (big endian <-> little endian)
12561sethi %hi(0xff00ff00), %l3
12562or %l3, %lo(0xff00ff00), %l3
12563and %l4, %l3, %l6
12564srl %l6, 8, %l6
12565sll %l4, 8, %o5
12566and %o5, %l3, %o5
12567or %o5, %l6, %o5
12568srl %o5, 16, %l6
12569sll %o5, 16, %o5
12570srl %o5, 0, %o5
12571or %o5, %l6, %o5
12572stwa %o5, [%i3 + 12] %asi
12573add %l4, 1, %l4
12574ba P665
12575nop
12576
12577TARGET451:
12578ba RET451
12579nop
12580
12581
12582P665: !_MEMBAR (Int) (LE)
12583membar #StoreLoad
12584
12585P666: !_LDD [21] (Int)
12586sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
12587sub %i0, %i2, %i2
12588ldd [%i2 + 0], %l6
12589! move %l6(lower) -> %o1(upper)
12590sllx %l6, 32, %o1
12591! move %l7(lower) -> %o1(lower)
12592or %l7, %o1, %o1
12593
12594P667: !_SWAP [2] (maybe <- 0x125) (Int)
12595mov %l4, %o2
12596swap [%i0 + 12], %o2
12597! move %o2(lower) -> %o2(upper)
12598sllx %o2, 32, %o2
12599add %l4, 1, %l4
12600
12601P668: !_MEMBAR (FP)
12602
12603P669: !_BST [15] (maybe <- 0x3f8000ce) (FP)
12604wr %g0, 0xf0, %asi
12605sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
12606sub %i0, %i3, %i3
12607! preparing store val #0, next val will be in f32
12608fmovs %f16, %f20
12609fadds %f16, %f17, %f16
12610! preparing store val #1, next val will be in f33
12611fmovs %f16, %f21
12612fadds %f16, %f17, %f16
12613! preparing store val #2, next val will be in f35
12614fmovd %f20, %f32
12615fmovs %f16, %f21
12616fadds %f16, %f17, %f16
12617fmovd %f20, %f34
12618membar #Sync
12619stda %f32, [%i3 + 0 ] %asi
12620
12621P670: !_MEMBAR (FP)
12622membar #StoreLoad
12623
12624P671: !_PREFETCH [0] (Int) (Branch target of P865)
12625prefetch [%i0 + 0], 20
12626ba P672
12627nop
12628
12629TARGET865:
12630ba RET865
12631nop
12632
12633
12634P672: !_SWAP [22] (maybe <- 0x126) (Int)
12635mov %l4, %l3
12636swap [%i2 + 4], %l3
12637! move %l3(lower) -> %o2(lower)
12638srl %l3, 0, %l7
12639or %l7, %o2, %o2
12640add %l4, 1, %l4
12641
12642P673: !_DWST [16] (maybe <- 0x127) (Int)
12643sllx %l4, 32, %l6
12644add %l4, 1, %l4
12645or %l6, %l4, %l6
12646stx %l6, [%i3 + 0]
12647add %l4, 1, %l4
12648
12649P674: !_LD [11] (Int)
12650sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
12651add %i0, %i2, %i2
12652lduw [%i2 + 12], %o3
12653! move %o3(lower) -> %o3(upper)
12654sllx %o3, 32, %o3
12655
12656P675: !_REPLACEMENT [13] (Int) (Branch target of P988)
12657sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
12658sub %i0, %i3, %i3
12659sethi %hi(0x20000), %l7
12660ld [%i3+4], %l3
12661st %l3, [%i3+4]
12662add %i3, %l7, %o5
12663ld [%o5+4], %l3
12664st %l3, [%o5+4]
12665add %o5, %l7, %o5
12666ld [%o5+4], %l3
12667st %l3, [%o5+4]
12668add %o5, %l7, %o5
12669ld [%o5+4], %l3
12670st %l3, [%o5+4]
12671add %o5, %l7, %o5
12672ld [%o5+4], %l3
12673st %l3, [%o5+4]
12674add %o5, %l7, %o5
12675ld [%o5+4], %l3
12676st %l3, [%o5+4]
12677add %o5, %l7, %o5
12678ld [%o5+4], %l3
12679st %l3, [%o5+4]
12680add %o5, %l7, %o5
12681ld [%o5+4], %l3
12682st %l3, [%o5+4]
12683ba P676
12684nop
12685
12686TARGET988:
12687ba RET988
12688nop
12689
12690
12691P676: !_LDD [4] (Int)
12692ldd [%i1 + 0], %l6
12693! move %l6(lower) -> %o3(lower)
12694or %l6, %o3, %o3
12695! move %l7(lower) -> %o4(upper)
12696sllx %l7, 32, %o4
12697
12698P677: !_DWST_BINIT [19] (maybe <- 0x129) (Int)
12699wr %g0, 0xe2, %asi
12700sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
12701add %i0, %i2, %i2
12702sllx %l4, 32, %l3
12703add %l4, 1, %l4
12704or %l3, %l4, %l3
12705stxa %l3, [%i2 + 0] %asi
12706add %l4, 1, %l4
12707
12708P678: !_MEMBAR (Int)
12709
12710P679: !_BST [11] (maybe <- 0x3f8000d1) (FP)
12711wr %g0, 0xf0, %asi
12712sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
12713add %i0, %i3, %i3
12714! preparing store val #0, next val will be in f32
12715fmovs %f16, %f20
12716fadds %f16, %f17, %f16
12717! preparing store val #1, next val will be in f33
12718fmovs %f16, %f21
12719fadds %f16, %f17, %f16
12720! preparing store val #2, next val will be in f35
12721fmovd %f20, %f32
12722fmovs %f16, %f21
12723fadds %f16, %f17, %f16
12724fmovd %f20, %f34
12725membar #Sync
12726stda %f32, [%i3 + 0 ] %asi
12727
12728P680: !_MEMBAR (FP)
12729membar #StoreLoad
12730
12731P681: !_BLD [6] (FP)
12732wr %g0, 0xf0, %asi
12733sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
12734sub %i0, %i2, %i2
12735ldda [%i2 + 0] %asi, %f32
12736membar #Sync
12737! 3 addresses covered
12738fmovd %f32, %f12
12739fmovd %f34, %f18
12740fmovs %f19, %f14
12741
12742P682: !_MEMBAR (FP)
12743
12744P683: !_BLD [10] (FP)
12745wr %g0, 0xf0, %asi
12746ldda [%i3 + 0] %asi, %f32
12747membar #Sync
12748! 3 addresses covered
12749fmovd %f32, %f18
12750fmovs %f18, %f15
12751!---- flushing fp results buffer to %f30 ----
12752fmovd %f0, %f30
12753fmovd %f2, %f30
12754fmovd %f4, %f30
12755fmovd %f6, %f30
12756fmovd %f8, %f30
12757fmovd %f10, %f30
12758fmovd %f12, %f30
12759fmovd %f14, %f30
12760!--
12761fmovs %f19, %f0
12762fmovd %f34, %f18
12763fmovs %f19, %f1
12764
12765P684: !_MEMBAR (FP)
12766
12767P685: !_PREFETCH [17] (Int)
12768sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
12769sub %i0, %i3, %i3
12770prefetch [%i3 + 12], 16
12771
12772P686: !_MEMBAR (FP)
12773
12774P687: !_BST [2] (maybe <- 0x3f8000d4) (FP)
12775wr %g0, 0xf0, %asi
12776! preparing store val #0, next val will be in f32
12777fmovs %f16, %f20
12778fadds %f16, %f17, %f16
12779! preparing store val #1, next val will be in f33
12780fmovs %f16, %f21
12781fadds %f16, %f17, %f16
12782! preparing store val #2, next val will be in f35
12783fmovd %f20, %f32
12784fmovs %f16, %f21
12785fadds %f16, %f17, %f16
12786fmovd %f20, %f34
12787membar #Sync
12788stda %f32, [%i0 + 0 ] %asi
12789
12790P688: !_MEMBAR (FP)
12791
12792P689: !_BST [3] (maybe <- 0x3f8000d7) (FP) (CBR)
12793wr %g0, 0xf0, %asi
12794! preparing store val #0, next val will be in f32
12795fmovs %f16, %f20
12796fadds %f16, %f17, %f16
12797! preparing store val #1, next val will be in f33
12798fmovs %f16, %f21
12799fadds %f16, %f17, %f16
12800! preparing store val #2, next val will be in f35
12801fmovd %f20, %f32
12802fmovs %f16, %f21
12803fadds %f16, %f17, %f16
12804fmovd %f20, %f34
12805membar #Sync
12806stda %f32, [%i1 + 0 ] %asi
12807
12808! cbranch
12809andcc %l0, 1, %g0
12810be,pt %xcc, TARGET689
12811nop
12812RET689:
12813
12814! lfsr step begin
12815srlx %l0, 1, %l3
12816xnor %l3, %l0, %l3
12817sllx %l3, 63, %l3
12818or %l3, %l0, %l0
12819srlx %l0, 1, %l0
12820
12821
12822P690: !_MEMBAR (FP)
12823membar #StoreLoad
12824
12825P691: !_DWLD [11] (Int)
12826sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
12827add %i0, %i2, %i2
12828ldx [%i2 + 8], %l7
12829! move %l7(lower) -> %o4(lower)
12830srl %l7, 0, %l6
12831or %l6, %o4, %o4
12832!---- flushing int results buffer----
12833mov %o0, %l5
12834mov %o1, %l5
12835mov %o2, %l5
12836mov %o3, %l5
12837mov %o4, %l5
12838
12839P692: !_MEMBAR (FP)
12840membar #StoreLoad
12841
12842P693: !_BLD [5] (FP)
12843wr %g0, 0xf0, %asi
12844ldda [%i1 + 0] %asi, %f32
12845membar #Sync
12846! 3 addresses covered
12847fmovd %f32, %f2
12848fmovd %f34, %f18
12849fmovs %f19, %f4
12850
12851P694: !_MEMBAR (FP)
12852
12853P695: !_DWST_BINIT [21] (maybe <- 0x12b) (Int)
12854wr %g0, 0xe2, %asi
12855sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
12856sub %i0, %i3, %i3
12857sllx %l4, 32, %o5
12858add %l4, 1, %l4
12859or %o5, %l4, %o5
12860stxa %o5, [%i3 + 0] %asi
12861add %l4, 1, %l4
12862
12863P696: !_MEMBAR (Int)
12864membar #StoreLoad
12865
12866P697: !_CAS [14] (maybe <- 0x12d) (Int)
12867sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
12868add %i0, %i2, %i2
12869add %i2, 12, %o5
12870lduw [%o5], %o0
12871mov %o0, %l7
12872! move %l7(lower) -> %o0(upper)
12873sllx %l7, 32, %o0
12874mov %l4, %l6
12875cas [%o5], %l7, %l6
12876! move %l6(lower) -> %o0(lower)
12877srl %l6, 0, %l7
12878or %l7, %o0, %o0
12879add %l4, 1, %l4
12880
12881P698: !_MEMBAR (FP)
12882
12883P699: !_BSTC [15] (maybe <- 0x3f8000da) (FP)
12884wr %g0, 0xe0, %asi
12885sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
12886sub %i0, %i3, %i3
12887! preparing store val #0, next val will be in f32
12888fmovs %f16, %f20
12889fadds %f16, %f17, %f16
12890! preparing store val #1, next val will be in f33
12891fmovs %f16, %f21
12892fadds %f16, %f17, %f16
12893! preparing store val #2, next val will be in f35
12894fmovd %f20, %f32
12895fmovs %f16, %f21
12896fadds %f16, %f17, %f16
12897fmovd %f20, %f34
12898membar #Sync
12899stda %f32, [%i3 + 0 ] %asi
12900
12901P700: !_MEMBAR (FP)
12902membar #StoreLoad
12903
12904P701: !_DWST [20] (maybe <- 0x12e) (Int)
12905sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
12906add %i0, %i2, %i2
12907mov %l4, %l6
12908stx %l6, [%i2 + 8]
12909add %l4, 1, %l4
12910
12911P702: !_DWST [14] (maybe <- 0x12f) (Int)
12912sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
12913add %i0, %i3, %i3
12914mov %l4, %l3
12915stx %l3, [%i3 + 8]
12916add %l4, 1, %l4
12917
12918P703: !_MEMBAR (FP)
12919membar #StoreLoad
12920
12921P704: !_BLD [23] (FP)
12922wr %g0, 0xf0, %asi
12923sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
12924sub %i0, %i2, %i2
12925ldda [%i2 + 0] %asi, %f32
12926membar #Sync
12927! 3 addresses covered
12928fmovd %f32, %f18
12929fmovs %f18, %f5
12930fmovs %f19, %f6
12931fmovd %f34, %f18
12932fmovs %f19, %f7
12933
12934P705: !_MEMBAR (FP)
12935
12936P706: !_PREFETCH [2] (Int)
12937prefetch [%i0 + 12], 22
12938
12939P707: !_LD [3] (Int)
12940lduw [%i1 + 0], %o1
12941! move %o1(lower) -> %o1(upper)
12942sllx %o1, 32, %o1
12943
12944P708: !_DWST [12] (maybe <- 0x130) (Int)
12945sllx %l4, 32, %l7
12946add %l4, 1, %l4
12947or %l7, %l4, %l7
12948stx %l7, [%i3 + 0]
12949add %l4, 1, %l4
12950
12951P709: !_SWAP [5] (maybe <- 0x132) (Int)
12952mov %l4, %o5
12953swap [%i1 + 12], %o5
12954! move %o5(lower) -> %o1(lower)
12955srl %o5, 0, %l6
12956or %l6, %o1, %o1
12957add %l4, 1, %l4
12958
12959P710: !_MEMBAR (FP)
12960
12961P711: !_BST [3] (maybe <- 0x3f8000dd) (FP)
12962wr %g0, 0xf0, %asi
12963! preparing store val #0, next val will be in f32
12964fmovs %f16, %f20
12965fadds %f16, %f17, %f16
12966! preparing store val #1, next val will be in f33
12967fmovs %f16, %f21
12968fadds %f16, %f17, %f16
12969! preparing store val #2, next val will be in f35
12970fmovd %f20, %f32
12971fmovs %f16, %f21
12972fadds %f16, %f17, %f16
12973fmovd %f20, %f34
12974membar #Sync
12975stda %f32, [%i1 + 0 ] %asi
12976
12977P712: !_MEMBAR (FP)
12978membar #StoreLoad
12979
12980P713: !_REPLACEMENT [19] (Int)
12981sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
12982sub %i0, %i3, %i3
12983sethi %hi(0x20000), %o5
12984ld [%i3+4], %l6
12985st %l6, [%i3+4]
12986add %i3, %o5, %l3
12987ld [%l3+4], %l6
12988st %l6, [%l3+4]
12989add %l3, %o5, %l3
12990ld [%l3+4], %l6
12991st %l6, [%l3+4]
12992add %l3, %o5, %l3
12993ld [%l3+4], %l6
12994st %l6, [%l3+4]
12995add %l3, %o5, %l3
12996ld [%l3+4], %l6
12997st %l6, [%l3+4]
12998add %l3, %o5, %l3
12999ld [%l3+4], %l6
13000st %l6, [%l3+4]
13001add %l3, %o5, %l3
13002ld [%l3+4], %l6
13003st %l6, [%l3+4]
13004add %l3, %o5, %l3
13005ld [%l3+4], %l6
13006st %l6, [%l3+4]
13007
13008P714: !_MEMBAR (FP)
13009
13010P715: !_BST [23] (maybe <- 0x3f8000e0) (FP)
13011wr %g0, 0xf0, %asi
13012! preparing store val #0, next val will be in f32
13013fmovs %f16, %f20
13014fadds %f16, %f17, %f16
13015! preparing store val #1, next val will be in f33
13016fmovs %f16, %f21
13017fadds %f16, %f17, %f16
13018! preparing store val #2, next val will be in f35
13019fmovd %f20, %f32
13020fmovs %f16, %f21
13021fadds %f16, %f17, %f16
13022fmovd %f20, %f34
13023membar #Sync
13024stda %f32, [%i2 + 0 ] %asi
13025
13026P716: !_MEMBAR (FP)
13027membar #StoreLoad
13028
13029P717: !_LD [18] (Int)
13030sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
13031add %i0, %i2, %i2
13032lduw [%i2 + 0], %o2
13033! move %o2(lower) -> %o2(upper)
13034sllx %o2, 32, %o2
13035
13036P718: !_LDD [13] (Int)
13037sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
13038add %i0, %i3, %i3
13039ldd [%i3 + 0], %l6
13040! move %l6(lower) -> %o2(lower)
13041or %l6, %o2, %o2
13042! move %l7(lower) -> %o3(upper)
13043sllx %l7, 32, %o3
13044
13045P719: !_ST_BINIT [22] (maybe <- 0x133) (Int) (LE)
13046wr %g0, 0xea, %asi
13047sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
13048sub %i0, %i2, %i2
13049! Change single-word-level endianess (big endian <-> little endian)
13050sethi %hi(0xff00ff00), %l6
13051or %l6, %lo(0xff00ff00), %l6
13052and %l4, %l6, %l7
13053srl %l7, 8, %l7
13054sll %l4, 8, %l3
13055and %l3, %l6, %l3
13056or %l3, %l7, %l3
13057srl %l3, 16, %l7
13058sll %l3, 16, %l3
13059srl %l3, 0, %l3
13060or %l3, %l7, %l3
13061stwa %l3, [%i2 + 4] %asi
13062add %l4, 1, %l4
13063
13064P720: !_MEMBAR (Int) (LE)
13065membar #StoreLoad
13066
13067P721: !_SWAP [13] (maybe <- 0x134) (Int)
13068mov %l4, %l6
13069swap [%i3 + 4], %l6
13070! move %l6(lower) -> %o3(lower)
13071srl %l6, 0, %o5
13072or %o5, %o3, %o3
13073add %l4, 1, %l4
13074
13075P722: !_LD [11] (Int)
13076sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
13077add %i0, %i3, %i3
13078lduw [%i3 + 12], %o4
13079! move %o4(lower) -> %o4(upper)
13080sllx %o4, 32, %o4
13081
13082P723: !_DWLD [23] (FP)
13083ldd [%i2 + 8], %f8
13084! 1 addresses covered
13085fmovs %f9, %f8
13086
13087P724: !_MEMBAR (FP)
13088
13089P725: !_BSTC [4] (maybe <- 0x3f8000e3) (FP)
13090wr %g0, 0xe0, %asi
13091! preparing store val #0, next val will be in f32
13092fmovs %f16, %f20
13093fadds %f16, %f17, %f16
13094! preparing store val #1, next val will be in f33
13095fmovs %f16, %f21
13096fadds %f16, %f17, %f16
13097! preparing store val #2, next val will be in f35
13098fmovd %f20, %f32
13099fmovs %f16, %f21
13100fadds %f16, %f17, %f16
13101fmovd %f20, %f34
13102membar #Sync
13103stda %f32, [%i1 + 0 ] %asi
13104
13105P726: !_MEMBAR (FP)
13106membar #StoreLoad
13107
13108P727: !_SWAP [5] (maybe <- 0x135) (Int)
13109mov %l4, %l6
13110swap [%i1 + 12], %l6
13111! move %l6(lower) -> %o4(lower)
13112srl %l6, 0, %o5
13113or %o5, %o4, %o4
13114!---- flushing int results buffer----
13115mov %o0, %l5
13116mov %o1, %l5
13117mov %o2, %l5
13118mov %o3, %l5
13119mov %o4, %l5
13120add %l4, 1, %l4
13121
13122P728: !_LDD [6] (Int)
13123sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
13124sub %i0, %i2, %i2
13125ldd [%i2 + 0], %l6
13126! move %l6(lower) -> %o0(upper)
13127sllx %l6, 32, %o0
13128! move %l7(lower) -> %o0(lower)
13129or %l7, %o0, %o0
13130
13131P729: !_LDD [2] (Int)
13132ldd [%i0 + 8], %l6
13133! move %l7(lower) -> %o1(upper)
13134sllx %l7, 32, %o1
13135
13136P730: !_ST_BINIT [22] (maybe <- 0x136) (Int)
13137wr %g0, 0xe2, %asi
13138sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
13139sub %i0, %i3, %i3
13140stwa %l4, [%i3 + 4] %asi
13141add %l4, 1, %l4
13142
13143P731: !_MEMBAR (Int)
13144
13145P732: !_BST [5] (maybe <- 0x3f8000e6) (FP)
13146wr %g0, 0xf0, %asi
13147! preparing store val #0, next val will be in f32
13148fmovs %f16, %f20
13149fadds %f16, %f17, %f16
13150! preparing store val #1, next val will be in f33
13151fmovs %f16, %f21
13152fadds %f16, %f17, %f16
13153! preparing store val #2, next val will be in f35
13154fmovd %f20, %f32
13155fmovs %f16, %f21
13156fadds %f16, %f17, %f16
13157fmovd %f20, %f34
13158membar #Sync
13159stda %f32, [%i1 + 0 ] %asi
13160
13161P733: !_MEMBAR (FP)
13162membar #StoreLoad
13163
13164P734: !_ST_BINIT [4] (maybe <- 0x137) (Int)
13165wr %g0, 0xe2, %asi
13166stwa %l4, [%i1 + 4] %asi
13167add %l4, 1, %l4
13168
13169P735: !_MEMBAR (Int)
13170membar #StoreLoad
13171
13172P736: !_LDD [20] (Int)
13173sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
13174add %i0, %i2, %i2
13175ldd [%i2 + 8], %l6
13176! move %l7(lower) -> %o1(lower)
13177or %l7, %o1, %o1
13178
13179P737: !_MEMBAR (FP)
13180
13181P738: !_BSTC [0] (maybe <- 0x3f8000e9) (FP)
13182wr %g0, 0xe0, %asi
13183! preparing store val #0, next val will be in f32
13184fmovs %f16, %f20
13185fadds %f16, %f17, %f16
13186! preparing store val #1, next val will be in f33
13187fmovs %f16, %f21
13188fadds %f16, %f17, %f16
13189! preparing store val #2, next val will be in f35
13190fmovd %f20, %f32
13191fmovs %f16, %f21
13192fadds %f16, %f17, %f16
13193fmovd %f20, %f34
13194membar #Sync
13195stda %f32, [%i0 + 0 ] %asi
13196
13197P739: !_MEMBAR (FP)
13198membar #StoreLoad
13199
13200P740: !_DWST [7] (maybe <- 0x138) (Int)
13201sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
13202sub %i0, %i3, %i3
13203sllx %l4, 32, %o5
13204add %l4, 1, %l4
13205or %o5, %l4, %o5
13206stx %o5, [%i3 + 0]
13207add %l4, 1, %l4
13208
13209P741: !_CAS [20] (maybe <- 0x13a) (Int)
13210add %i2, 12, %o5
13211lduw [%o5], %o2
13212mov %o2, %l7
13213! move %l7(lower) -> %o2(upper)
13214sllx %l7, 32, %o2
13215mov %l4, %l6
13216cas [%o5], %l7, %l6
13217! move %l6(lower) -> %o2(lower)
13218srl %l6, 0, %l7
13219or %l7, %o2, %o2
13220add %l4, 1, %l4
13221
13222P742: !_DWST [8] (maybe <- 0x13b) (Int)
13223mov %l4, %l7
13224stx %l7, [%i3 + 8]
13225add %l4, 1, %l4
13226
13227P743: !_LDD [12] (Int)
13228sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
13229add %i0, %i2, %i2
13230ldd [%i2 + 0], %l6
13231! move %l6(lower) -> %o3(upper)
13232sllx %l6, 32, %o3
13233! move %l7(lower) -> %o3(lower)
13234or %l7, %o3, %o3
13235
13236P744: !_LDD [1] (Int)
13237ldd [%i0 + 0], %l6
13238! move %l6(lower) -> %o4(upper)
13239sllx %l6, 32, %o4
13240! move %l7(lower) -> %o4(lower)
13241or %l7, %o4, %o4
13242!---- flushing int results buffer----
13243mov %o0, %l5
13244mov %o1, %l5
13245mov %o2, %l5
13246mov %o3, %l5
13247mov %o4, %l5
13248
13249P745: !_DWST [13] (maybe <- 0x13c) (Int) (Branch target of P138)
13250sllx %l4, 32, %l3
13251add %l4, 1, %l4
13252or %l3, %l4, %l3
13253stx %l3, [%i2 + 0]
13254add %l4, 1, %l4
13255ba P746
13256nop
13257
13258TARGET138:
13259ba RET138
13260nop
13261
13262
13263P746: !_DWST [17] (maybe <- 0x13e) (Int)
13264sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
13265sub %i0, %i3, %i3
13266mov %l4, %o5
13267stx %o5, [%i3 + 8]
13268add %l4, 1, %l4
13269
13270P747: !_DWLD [11] (Int)
13271sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
13272add %i0, %i2, %i2
13273ldx [%i2 + 8], %o0
13274! move %o0(lower) -> %o0(upper)
13275sllx %o0, 32, %o0
13276
13277P748: !_SWAP [23] (maybe <- 0x13f) (Int)
13278sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
13279sub %i0, %i3, %i3
13280mov %l4, %l7
13281swap [%i3 + 12], %l7
13282! move %l7(lower) -> %o0(lower)
13283srl %l7, 0, %l3
13284or %l3, %o0, %o0
13285add %l4, 1, %l4
13286
13287P749: !_LDD [18] (Int)
13288sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
13289add %i0, %i2, %i2
13290ldd [%i2 + 0], %l6
13291! move %l6(lower) -> %o1(upper)
13292sllx %l6, 32, %o1
13293! move %l7(lower) -> %o1(lower)
13294or %l7, %o1, %o1
13295
13296P750: !_DWST_BINIT [15] (maybe <- 0x140) (Int) (Branch target of P293)
13297wr %g0, 0xe2, %asi
13298sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
13299sub %i0, %i3, %i3
13300sllx %l4, 32, %l3
13301add %l4, 1, %l4
13302or %l3, %l4, %l3
13303stxa %l3, [%i3 + 0] %asi
13304add %l4, 1, %l4
13305ba P751
13306nop
13307
13308TARGET293:
13309ba RET293
13310nop
13311
13312
13313P751: !_MEMBAR (Int)
13314membar #StoreLoad
13315
13316P752: !_CAS [0] (maybe <- 0x142) (Int) (LE)
13317! Change single-word-level endianess (big endian <-> little endian)
13318sethi %hi(0xff00ff00), %l3
13319or %l3, %lo(0xff00ff00), %l3
13320and %l4, %l3, %o5
13321srl %o5, 8, %o5
13322sll %l4, 8, %l6
13323and %l6, %l3, %l6
13324or %l6, %o5, %l6
13325srl %l6, 16, %o5
13326sll %l6, 16, %l6
13327srl %l6, 0, %l6
13328or %l6, %o5, %l6
13329wr %g0, 0x88, %asi
13330lduwa [%i0] %asi, %o2
13331mov %o2, %o5
13332! move %o5(lower) -> %o2(upper)
13333sllx %o5, 32, %o2
13334mov %l6, %l7
13335casa [%i0] %asi, %o5, %l7
13336! move %l7(lower) -> %o2(lower)
13337srl %l7, 0, %o5
13338or %o5, %o2, %o2
13339add %l4, 1, %l4
13340
13341P753: !_CASX [13] (maybe <- 0x143) (Int)
13342sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
13343add %i0, %i2, %i2
13344ldx [%i2], %o3
13345! move %o3(upper) -> %o3(upper)
13346! move %o3(lower) -> %o3(lower)
13347mov %o3, %o5
13348sllx %l4, 32, %o4
13349add %l4, 1, %l4
13350or %l4, %o4, %o4
13351casx [%i2], %o5, %o4
13352! move %o4(upper) -> %o4(upper)
13353! move %o4(lower) -> %o4(lower)
13354!---- flushing int results buffer----
13355mov %o0, %l5
13356mov %o1, %l5
13357mov %o2, %l5
13358mov %o3, %l5
13359mov %o4, %l5
13360add %l4, 1, %l4
13361
13362P754: !_ST_BINIT [7] (maybe <- 0x145) (Int)
13363wr %g0, 0xe2, %asi
13364sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
13365sub %i0, %i3, %i3
13366stwa %l4, [%i3 + 4] %asi
13367add %l4, 1, %l4
13368
13369P755: !_MEMBAR (Int)
13370membar #StoreLoad
13371
13372P756: !_CAS [21] (maybe <- 0x146) (Int)
13373sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
13374sub %i0, %i2, %i2
13375lduw [%i2], %o0
13376mov %o0, %l7
13377! move %l7(lower) -> %o0(upper)
13378sllx %l7, 32, %o0
13379mov %l4, %l6
13380cas [%i2], %l7, %l6
13381! move %l6(lower) -> %o0(lower)
13382srl %l6, 0, %l7
13383or %l7, %o0, %o0
13384add %l4, 1, %l4
13385
13386P757: !_LD [13] (Int)
13387sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
13388add %i0, %i3, %i3
13389lduw [%i3 + 4], %o1
13390! move %o1(lower) -> %o1(upper)
13391sllx %o1, 32, %o1
13392
13393P758: !_DWST [15] (maybe <- 0x147) (Int)
13394sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
13395sub %i0, %i2, %i2
13396sllx %l4, 32, %l3
13397add %l4, 1, %l4
13398or %l3, %l4, %l3
13399stx %l3, [%i2 + 0]
13400add %l4, 1, %l4
13401
13402P759: !_DWLD [1] (Int)
13403ldx [%i0 + 0], %l3
13404! move %l3(upper) -> %o1(lower)
13405srlx %l3, 32, %o5
13406or %o5, %o1, %o1
13407! move %l3(lower) -> %o2(upper)
13408sllx %l3, 32, %o2
13409
13410P760: !_PREFETCH [13] (Int)
13411prefetch [%i3 + 4], 2
13412
13413P761: !_PREFETCH [16] (Int)
13414prefetch [%i2 + 4], 1
13415
13416P762: !_CASX [13] (maybe <- 0x149) (Int) (CBR)
13417ldx [%i3], %l3
13418! move %l3(upper) -> %o2(lower)
13419srlx %l3, 32, %l6
13420or %l6, %o2, %o2
13421! move %l3(lower) -> %o3(upper)
13422sllx %l3, 32, %o3
13423mov %l3, %l6
13424sllx %l4, 32, %l3
13425add %l4, 1, %l4
13426or %l4, %l3, %l3
13427casx [%i3], %l6, %l3
13428! move %l3(upper) -> %o3(lower)
13429srlx %l3, 32, %l6
13430or %l6, %o3, %o3
13431! move %l3(lower) -> %o4(upper)
13432sllx %l3, 32, %o4
13433add %l4, 1, %l4
13434
13435! cbranch
13436andcc %l0, 1, %g0
13437be,pt %xcc, TARGET762
13438nop
13439RET762:
13440
13441! lfsr step begin
13442srlx %l0, 1, %l6
13443xnor %l6, %l0, %l6
13444sllx %l6, 63, %l6
13445or %l6, %l0, %l0
13446srlx %l0, 1, %l0
13447
13448
13449P763: !_SWAP [15] (maybe <- 0x14b) (Int)
13450mov %l4, %l3
13451swap [%i2 + 0], %l3
13452! move %l3(lower) -> %o4(lower)
13453srl %l3, 0, %l7
13454or %l7, %o4, %o4
13455!---- flushing int results buffer----
13456mov %o0, %l5
13457mov %o1, %l5
13458mov %o2, %l5
13459mov %o3, %l5
13460mov %o4, %l5
13461add %l4, 1, %l4
13462
13463P764: !_MEMBAR (FP)
13464membar #StoreLoad
13465
13466P765: !_BLD [15] (FP) (Branch target of P689)
13467wr %g0, 0xf0, %asi
13468ldda [%i2 + 0] %asi, %f32
13469membar #Sync
13470! 3 addresses covered
13471fmovd %f32, %f18
13472fmovs %f18, %f9
13473fmovs %f19, %f10
13474fmovd %f34, %f18
13475fmovs %f19, %f11
13476ba P766
13477nop
13478
13479TARGET689:
13480ba RET689
13481nop
13482
13483
13484P766: !_MEMBAR (FP)
13485
13486P767: !_BLD [1] (FP)
13487wr %g0, 0xf0, %asi
13488ldda [%i0 + 0] %asi, %f32
13489membar #Sync
13490! 3 addresses covered
13491fmovd %f32, %f12
13492fmovd %f34, %f18
13493fmovs %f19, %f14
13494
13495P768: !_MEMBAR (FP)
13496
13497P769: !_ST [6] (maybe <- 0x14c) (Int)
13498sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
13499sub %i0, %i3, %i3
13500stw %l4, [%i3 + 0 ]
13501add %l4, 1, %l4
13502
13503P770: !_LD [0] (Int)
13504lduw [%i0 + 0], %o0
13505! move %o0(lower) -> %o0(upper)
13506sllx %o0, 32, %o0
13507
13508P771: !_MEMBAR (FP)
13509
13510P772: !_BST [9] (maybe <- 0x3f8000ec) (FP)
13511wr %g0, 0xf0, %asi
13512sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
13513add %i0, %i2, %i2
13514! preparing store val #0, next val will be in f32
13515fmovs %f16, %f20
13516fadds %f16, %f17, %f16
13517! preparing store val #1, next val will be in f33
13518fmovs %f16, %f21
13519fadds %f16, %f17, %f16
13520! preparing store val #2, next val will be in f35
13521fmovd %f20, %f32
13522fmovs %f16, %f21
13523fadds %f16, %f17, %f16
13524fmovd %f20, %f34
13525membar #Sync
13526stda %f32, [%i2 + 0 ] %asi
13527
13528P773: !_MEMBAR (FP) (Branch target of P115)
13529membar #StoreLoad
13530ba P774
13531nop
13532
13533TARGET115:
13534ba RET115
13535nop
13536
13537
13538P774: !_ST [5] (maybe <- 0x14d) (Int)
13539stw %l4, [%i1 + 12 ]
13540add %l4, 1, %l4
13541
13542P775: !_ST_BINIT [0] (maybe <- 0x14e) (Int)
13543wr %g0, 0xe2, %asi
13544stwa %l4, [%i0 + 0] %asi
13545add %l4, 1, %l4
13546
13547P776: !_MEMBAR (Int)
13548membar #StoreLoad
13549
13550P777: !_CASX [15] (maybe <- 0x14f) (Int)
13551sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
13552sub %i0, %i3, %i3
13553ldx [%i3], %o5
13554! move %o5(upper) -> %o0(lower)
13555srlx %o5, 32, %l3
13556or %l3, %o0, %o0
13557! move %o5(lower) -> %o1(upper)
13558sllx %o5, 32, %o1
13559mov %o5, %l3
13560sllx %l4, 32, %o5
13561add %l4, 1, %l4
13562or %l4, %o5, %o5
13563casx [%i3], %l3, %o5
13564! move %o5(upper) -> %o1(lower)
13565srlx %o5, 32, %l3
13566or %l3, %o1, %o1
13567! move %o5(lower) -> %o2(upper)
13568sllx %o5, 32, %o2
13569add %l4, 1, %l4
13570
13571P778: !_LD [7] (Int)
13572sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
13573sub %i0, %i2, %i2
13574lduw [%i2 + 4], %l6
13575! move %l6(lower) -> %o2(lower)
13576or %l6, %o2, %o2
13577
13578P779: !_SWAP [12] (maybe <- 0x151) (Int)
13579sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
13580add %i0, %i3, %i3
13581mov %l4, %o3
13582swap [%i3 + 0], %o3
13583! move %o3(lower) -> %o3(upper)
13584sllx %o3, 32, %o3
13585add %l4, 1, %l4
13586
13587P780: !_SWAP [10] (maybe <- 0x152) (Int)
13588sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
13589add %i0, %i2, %i2
13590mov %l4, %o5
13591swap [%i2 + 4], %o5
13592! move %o5(lower) -> %o3(lower)
13593srl %o5, 0, %l6
13594or %l6, %o3, %o3
13595add %l4, 1, %l4
13596
13597P781: !_ST_BINIT [17] (maybe <- 0x153) (Int)
13598wr %g0, 0xe2, %asi
13599sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
13600sub %i0, %i3, %i3
13601stwa %l4, [%i3 + 12] %asi
13602add %l4, 1, %l4
13603
13604P782: !_MEMBAR (Int)
13605membar #StoreLoad
13606
13607P783: !_LDD [10] (Int)
13608ldd [%i2 + 0], %l6
13609! move %l6(lower) -> %o4(upper)
13610sllx %l6, 32, %o4
13611! move %l7(lower) -> %o4(lower)
13612or %l7, %o4, %o4
13613!---- flushing int results buffer----
13614mov %o0, %l5
13615mov %o1, %l5
13616mov %o2, %l5
13617mov %o3, %l5
13618mov %o4, %l5
13619
13620P784: !_CAS [0] (maybe <- 0x154) (Int)
13621lduw [%i0], %o0
13622mov %o0, %l3
13623! move %l3(lower) -> %o0(upper)
13624sllx %l3, 32, %o0
13625mov %l4, %o5
13626cas [%i0], %l3, %o5
13627! move %o5(lower) -> %o0(lower)
13628srl %o5, 0, %l3
13629or %l3, %o0, %o0
13630add %l4, 1, %l4
13631
13632P785: !_DWLD [1] (Int)
13633ldx [%i0 + 0], %o1
13634! move %o1(upper) -> %o1(upper)
13635! move %o1(lower) -> %o1(lower)
13636
13637P786: !_MEMBAR (FP)
13638
13639P787: !_BSTC [19] (maybe <- 0x3f8000ef) (FP)
13640wr %g0, 0xe0, %asi
13641sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
13642add %i0, %i2, %i2
13643! preparing store val #0, next val will be in f32
13644fmovs %f16, %f20
13645fadds %f16, %f17, %f16
13646! preparing store val #1, next val will be in f33
13647fmovs %f16, %f21
13648fadds %f16, %f17, %f16
13649! preparing store val #2, next val will be in f35
13650fmovd %f20, %f32
13651fmovs %f16, %f21
13652fadds %f16, %f17, %f16
13653fmovd %f20, %f34
13654membar #Sync
13655stda %f32, [%i2 + 0 ] %asi
13656
13657P788: !_MEMBAR (FP)
13658membar #StoreLoad
13659
13660P789: !_LD [8] (Int) (LE)
13661wr %g0, 0x88, %asi
13662sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
13663sub %i0, %i3, %i3
13664lduwa [%i3 + 12] %asi, %o2
13665! move %o2(lower) -> %o2(upper)
13666sllx %o2, 32, %o2
13667
13668P790: !_SWAP [4] (maybe <- 0x155) (Int) (LE)
13669wr %g0, 0x88, %asi
13670mov %l4, %l6
13671! Change single-word-level endianess (big endian <-> little endian)
13672sethi %hi(0xff00ff00), %o5
13673or %o5, %lo(0xff00ff00), %o5
13674and %l6, %o5, %l3
13675srl %l3, 8, %l3
13676sll %l6, 8, %l6
13677and %l6, %o5, %l6
13678or %l6, %l3, %l6
13679srl %l6, 16, %l3
13680sll %l6, 16, %l6
13681srl %l6, 0, %l6
13682or %l6, %l3, %l6
13683swapa [%i1 + 4] %asi, %l6
13684! move %l6(lower) -> %o2(lower)
13685srl %l6, 0, %o5
13686or %o5, %o2, %o2
13687add %l4, 1, %l4
13688
13689P791: !_SWAP [12] (maybe <- 0x156) (Int)
13690sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
13691add %i0, %i2, %i2
13692mov %l4, %o3
13693swap [%i2 + 0], %o3
13694! move %o3(lower) -> %o3(upper)
13695sllx %o3, 32, %o3
13696add %l4, 1, %l4
13697
13698P792: !_LD [7] (Int) (LE)
13699wr %g0, 0x88, %asi
13700lduwa [%i3 + 4] %asi, %l7
13701! move %l7(lower) -> %o3(lower)
13702or %l7, %o3, %o3
13703
13704P793: !_ST_BINIT [18] (maybe <- 0x157) (Int)
13705wr %g0, 0xe2, %asi
13706sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
13707add %i0, %i3, %i3
13708stwa %l4, [%i3 + 0] %asi
13709add %l4, 1, %l4
13710
13711P794: !_MEMBAR (Int)
13712membar #StoreLoad
13713
13714P795: !_LD [13] (Int)
13715lduw [%i2 + 4], %o4
13716! move %o4(lower) -> %o4(upper)
13717sllx %o4, 32, %o4
13718
13719P796: !_PREFETCH [11] (Int)
13720sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
13721add %i0, %i2, %i2
13722prefetch [%i2 + 12], 21
13723
13724P797: !_ST_BINIT [19] (maybe <- 0x158) (Int)
13725wr %g0, 0xe2, %asi
13726stwa %l4, [%i3 + 4] %asi
13727add %l4, 1, %l4
13728
13729P798: !_MEMBAR (Int)
13730membar #StoreLoad
13731
13732P799: !_CASX [19] (maybe <- 0x159) (Int)
13733ldx [%i3], %l7
13734! move %l7(upper) -> %o4(lower)
13735srlx %l7, 32, %o5
13736or %o5, %o4, %o4
13737!---- flushing int results buffer----
13738mov %o0, %l5
13739mov %o1, %l5
13740mov %o2, %l5
13741mov %o3, %l5
13742mov %o4, %l5
13743! move %l7(lower) -> %o0(upper)
13744sllx %l7, 32, %o0
13745mov %l7, %o5
13746sllx %l4, 32, %l7
13747add %l4, 1, %l4
13748or %l4, %l7, %l7
13749casx [%i3], %o5, %l7
13750! move %l7(upper) -> %o0(lower)
13751srlx %l7, 32, %o5
13752or %o5, %o0, %o0
13753! move %l7(lower) -> %o1(upper)
13754sllx %l7, 32, %o1
13755add %l4, 1, %l4
13756
13757P800: !_LDD [22] (Int)
13758sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
13759sub %i0, %i3, %i3
13760ldd [%i3 + 0], %l6
13761! move %l6(lower) -> %o1(lower)
13762or %l6, %o1, %o1
13763! move %l7(lower) -> %o2(upper)
13764sllx %l7, 32, %o2
13765
13766P801: !_LDD [18] (Int)
13767sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
13768add %i0, %i2, %i2
13769ldd [%i2 + 0], %l6
13770! move %l6(lower) -> %o2(lower)
13771or %l6, %o2, %o2
13772! move %l7(lower) -> %o3(upper)
13773sllx %l7, 32, %o3
13774
13775P802: !_SWAP [1] (maybe <- 0x15b) (Int)
13776mov %l4, %l7
13777swap [%i0 + 4], %l7
13778! move %l7(lower) -> %o3(lower)
13779srl %l7, 0, %l3
13780or %l3, %o3, %o3
13781add %l4, 1, %l4
13782
13783P803: !_MEMBAR (FP)
13784
13785P804: !_BST [8] (maybe <- 0x3f8000f2) (FP)
13786wr %g0, 0xf0, %asi
13787sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
13788sub %i0, %i3, %i3
13789! preparing store val #0, next val will be in f32
13790fmovs %f16, %f20
13791fadds %f16, %f17, %f16
13792! preparing store val #1, next val will be in f33
13793fmovs %f16, %f21
13794fadds %f16, %f17, %f16
13795! preparing store val #2, next val will be in f35
13796fmovd %f20, %f32
13797fmovs %f16, %f21
13798fadds %f16, %f17, %f16
13799fmovd %f20, %f34
13800membar #Sync
13801stda %f32, [%i3 + 0 ] %asi
13802
13803P805: !_MEMBAR (FP)
13804membar #StoreLoad
13805
13806P806: !_ST_BINIT [7] (maybe <- 0x15c) (Int)
13807wr %g0, 0xe2, %asi
13808stwa %l4, [%i3 + 4] %asi
13809add %l4, 1, %l4
13810
13811P807: !_MEMBAR (Int) (Branch target of P859)
13812membar #StoreLoad
13813ba P808
13814nop
13815
13816TARGET859:
13817ba RET859
13818nop
13819
13820
13821P808: !_REPLACEMENT [8] (Int)
13822sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
13823sub %i0, %i2, %i2
13824sethi %hi(0x20000), %l6
13825ld [%i2+12], %o5
13826st %o5, [%i2+12]
13827add %i2, %l6, %l7
13828ld [%l7+12], %o5
13829st %o5, [%l7+12]
13830add %l7, %l6, %l7
13831ld [%l7+12], %o5
13832st %o5, [%l7+12]
13833add %l7, %l6, %l7
13834ld [%l7+12], %o5
13835st %o5, [%l7+12]
13836add %l7, %l6, %l7
13837ld [%l7+12], %o5
13838st %o5, [%l7+12]
13839add %l7, %l6, %l7
13840ld [%l7+12], %o5
13841st %o5, [%l7+12]
13842add %l7, %l6, %l7
13843ld [%l7+12], %o5
13844st %o5, [%l7+12]
13845add %l7, %l6, %l7
13846ld [%l7+12], %o5
13847st %o5, [%l7+12]
13848
13849P809: !_LD [16] (FP)
13850sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
13851sub %i0, %i3, %i3
13852ld [%i3 + 4], %f15
13853! 1 addresses covered
13854!---- flushing fp results buffer to %f30 ----
13855fmovd %f0, %f30
13856fmovd %f2, %f30
13857fmovd %f4, %f30
13858fmovd %f6, %f30
13859fmovd %f8, %f30
13860fmovd %f10, %f30
13861fmovd %f12, %f30
13862fmovd %f14, %f30
13863!--
13864
13865P810: !_MEMBAR (FP)
13866
13867P811: !_BSTC [13] (maybe <- 0x3f8000f5) (FP)
13868wr %g0, 0xe0, %asi
13869sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
13870add %i0, %i2, %i2
13871! preparing store val #0, next val will be in f32
13872fmovs %f16, %f20
13873fadds %f16, %f17, %f16
13874! preparing store val #1, next val will be in f33
13875fmovs %f16, %f21
13876fadds %f16, %f17, %f16
13877! preparing store val #2, next val will be in f35
13878fmovd %f20, %f32
13879fmovs %f16, %f21
13880fadds %f16, %f17, %f16
13881fmovd %f20, %f34
13882membar #Sync
13883stda %f32, [%i2 + 0 ] %asi
13884
13885P812: !_MEMBAR (FP) (Branch target of P828)
13886ba P813
13887nop
13888
13889TARGET828:
13890ba RET828
13891nop
13892
13893
13894P813: !_BST [9] (maybe <- 0x3f8000f8) (FP)
13895wr %g0, 0xf0, %asi
13896sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
13897add %i0, %i3, %i3
13898! preparing store val #0, next val will be in f32
13899fmovs %f16, %f20
13900fadds %f16, %f17, %f16
13901! preparing store val #1, next val will be in f33
13902fmovs %f16, %f21
13903fadds %f16, %f17, %f16
13904! preparing store val #2, next val will be in f35
13905fmovd %f20, %f32
13906fmovs %f16, %f21
13907fadds %f16, %f17, %f16
13908fmovd %f20, %f34
13909membar #Sync
13910stda %f32, [%i3 + 0 ] %asi
13911
13912P814: !_MEMBAR (FP)
13913membar #StoreLoad
13914
13915P815: !_DWST_BINIT [12] (maybe <- 0x15d) (Int)
13916wr %g0, 0xe2, %asi
13917sllx %l4, 32, %l7
13918add %l4, 1, %l4
13919or %l7, %l4, %l7
13920stxa %l7, [%i2 + 0] %asi
13921add %l4, 1, %l4
13922
13923P816: !_MEMBAR (Int)
13924membar #StoreLoad
13925
13926P817: !_DWLD [12] (Int) (CBR) (Branch target of P886)
13927ldx [%i2 + 0], %o4
13928! move %o4(upper) -> %o4(upper)
13929! move %o4(lower) -> %o4(lower)
13930!---- flushing int results buffer----
13931mov %o0, %l5
13932mov %o1, %l5
13933mov %o2, %l5
13934mov %o3, %l5
13935mov %o4, %l5
13936
13937! cbranch
13938andcc %l0, 1, %g0
13939be,pn %xcc, TARGET817
13940nop
13941RET817:
13942
13943! lfsr step begin
13944srlx %l0, 1, %o5
13945xnor %o5, %l0, %o5
13946sllx %o5, 63, %o5
13947or %o5, %l0, %l0
13948srlx %l0, 1, %l0
13949
13950ba P818
13951nop
13952
13953TARGET886:
13954ba RET886
13955nop
13956
13957
13958P818: !_CASX [8] (maybe <- 0x15f) (Int)
13959sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
13960sub %i0, %i2, %i2
13961add %i2, 8, %l6
13962ldx [%l6], %o0
13963! move %o0(upper) -> %o0(upper)
13964! move %o0(lower) -> %o0(lower)
13965mov %o0, %l3
13966mov %l4, %o1
13967casx [%l6], %l3, %o1
13968! move %o1(upper) -> %o1(upper)
13969! move %o1(lower) -> %o1(lower)
13970add %l4, 1, %l4
13971
13972P819: !_MEMBAR (FP)
13973membar #StoreLoad
13974
13975P820: !_BLD [12] (FP)
13976wr %g0, 0xf0, %asi
13977sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
13978add %i0, %i3, %i3
13979ldda [%i3 + 0] %asi, %f0
13980membar #Sync
13981! 3 addresses covered
13982fmovs %f3, %f2
13983
13984P821: !_MEMBAR (FP)
13985
13986P822: !_BST [8] (maybe <- 0x3f8000fb) (FP) (CBR)
13987wr %g0, 0xf0, %asi
13988! preparing store val #0, next val will be in f32
13989fmovs %f16, %f20
13990fadds %f16, %f17, %f16
13991! preparing store val #1, next val will be in f33
13992fmovs %f16, %f21
13993fadds %f16, %f17, %f16
13994! preparing store val #2, next val will be in f35
13995fmovd %f20, %f32
13996fmovs %f16, %f21
13997fadds %f16, %f17, %f16
13998fmovd %f20, %f34
13999membar #Sync
14000stda %f32, [%i2 + 0 ] %asi
14001
14002! cbranch
14003andcc %l0, 1, %g0
14004be,pn %xcc, TARGET822
14005nop
14006RET822:
14007
14008! lfsr step begin
14009srlx %l0, 1, %o5
14010xnor %o5, %l0, %o5
14011sllx %o5, 63, %o5
14012or %o5, %l0, %l0
14013srlx %l0, 1, %l0
14014
14015
14016P823: !_MEMBAR (FP)
14017membar #StoreLoad
14018
14019P824: !_BLD [18] (FP)
14020wr %g0, 0xf0, %asi
14021sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
14022add %i0, %i2, %i2
14023ldda [%i2 + 0] %asi, %f32
14024membar #Sync
14025! 3 addresses covered
14026fmovd %f32, %f18
14027fmovs %f18, %f3
14028fmovs %f19, %f4
14029fmovd %f34, %f18
14030fmovs %f19, %f5
14031
14032P825: !_MEMBAR (FP)
14033
14034P826: !_CAS [17] (maybe <- 0x160) (Int)
14035sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
14036sub %i0, %i3, %i3
14037add %i3, 12, %l6
14038lduw [%l6], %o2
14039mov %o2, %l3
14040! move %l3(lower) -> %o2(upper)
14041sllx %l3, 32, %o2
14042mov %l4, %o5
14043cas [%l6], %l3, %o5
14044! move %o5(lower) -> %o2(lower)
14045srl %o5, 0, %l3
14046or %l3, %o2, %o2
14047add %l4, 1, %l4
14048
14049P827: !_MEMBAR (FP)
14050
14051P828: !_BSTC [23] (maybe <- 0x3f8000fe) (FP) (CBR)
14052wr %g0, 0xe0, %asi
14053sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
14054sub %i0, %i2, %i2
14055! preparing store val #0, next val will be in f32
14056fmovs %f16, %f20
14057fadds %f16, %f17, %f16
14058! preparing store val #1, next val will be in f33
14059fmovs %f16, %f21
14060fadds %f16, %f17, %f16
14061! preparing store val #2, next val will be in f35
14062fmovd %f20, %f32
14063fmovs %f16, %f21
14064fadds %f16, %f17, %f16
14065fmovd %f20, %f34
14066membar #Sync
14067stda %f32, [%i2 + 0 ] %asi
14068
14069! cbranch
14070andcc %l0, 1, %g0
14071be,pn %xcc, TARGET828
14072nop
14073RET828:
14074
14075! lfsr step begin
14076srlx %l0, 1, %o5
14077xnor %o5, %l0, %o5
14078sllx %o5, 63, %o5
14079or %o5, %l0, %l0
14080srlx %l0, 1, %l0
14081
14082
14083P829: !_MEMBAR (FP)
14084
14085P830: !_BSTC [12] (maybe <- 0x3f800101) (FP)
14086wr %g0, 0xe0, %asi
14087sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
14088add %i0, %i3, %i3
14089! preparing store val #0, next val will be in f32
14090fmovs %f16, %f20
14091fadds %f16, %f17, %f16
14092! preparing store val #1, next val will be in f33
14093fmovs %f16, %f21
14094fadds %f16, %f17, %f16
14095! preparing store val #2, next val will be in f35
14096fmovd %f20, %f32
14097fmovs %f16, %f21
14098fadds %f16, %f17, %f16
14099fmovd %f20, %f34
14100membar #Sync
14101stda %f32, [%i3 + 0 ] %asi
14102
14103P831: !_MEMBAR (FP)
14104membar #StoreLoad
14105
14106P832: !_DWLD [5] (FP)
14107!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #3
14108!Logical addr: 5
14109
14110sethi %hi(0x200000), %o5
14111sub %i1, %o5, %i1
14112ldd [%i1 + 8], %f6
14113! 1 addresses covered
14114fmovs %f7, %f6
14115
14116P833: !_DWST [6] (maybe <- 0x161) (Int)
14117sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
14118sub %i0, %i2, %i2
14119sllx %l4, 32, %l3
14120add %l4, 1, %l4
14121or %l3, %l4, %l3
14122stx %l3, [%i2 + 0]
14123add %l4, 1, %l4
14124
14125P834: !_LD [0] (Int)
14126lduw [%i0 + 0], %o3
14127! move %o3(lower) -> %o3(upper)
14128sllx %o3, 32, %o3
14129
14130P835: !_DWST [15] (maybe <- 0x163) (Int)
14131sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
14132sub %i0, %i3, %i3
14133sllx %l4, 32, %l6
14134add %l4, 1, %l4
14135or %l6, %l4, %l6
14136stx %l6, [%i3 + 0]
14137add %l4, 1, %l4
14138
14139P836: !_MEMBAR (FP)
14140
14141P837: !_BSTC [13] (maybe <- 0x3f800104) (FP)
14142wr %g0, 0xe0, %asi
14143sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
14144add %i0, %i2, %i2
14145! preparing store val #0, next val will be in f32
14146fmovs %f16, %f20
14147fadds %f16, %f17, %f16
14148! preparing store val #1, next val will be in f33
14149fmovs %f16, %f21
14150fadds %f16, %f17, %f16
14151! preparing store val #2, next val will be in f35
14152fmovd %f20, %f32
14153fmovs %f16, %f21
14154fadds %f16, %f17, %f16
14155fmovd %f20, %f34
14156membar #Sync
14157stda %f32, [%i2 + 0 ] %asi
14158
14159P838: !_MEMBAR (FP)
14160membar #StoreLoad
14161
14162P839: !_LD [0] (Int)
14163lduw [%i0 + 0], %l3
14164! move %l3(lower) -> %o3(lower)
14165or %l3, %o3, %o3
14166
14167P840: !_DWST_BINIT [14] (maybe <- 0x165) (Int) (Branch target of P205)
14168wr %g0, 0xe2, %asi
14169mov %l4, %l6
14170stxa %l6, [%i2 + 8] %asi
14171add %l4, 1, %l4
14172ba P841
14173nop
14174
14175TARGET205:
14176ba RET205
14177nop
14178
14179
14180P841: !_MEMBAR (Int)
14181membar #StoreLoad
14182
14183P842: !_CASX [22] (maybe <- 0x166) (Int)
14184sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
14185sub %i0, %i3, %i3
14186ldx [%i3], %o4
14187! move %o4(upper) -> %o4(upper)
14188! move %o4(lower) -> %o4(lower)
14189!---- flushing int results buffer----
14190mov %o0, %l5
14191mov %o1, %l5
14192mov %o2, %l5
14193mov %o3, %l5
14194mov %o4, %l5
14195mov %o4, %l3
14196sllx %l4, 32, %o0
14197add %l4, 1, %l4
14198or %l4, %o0, %o0
14199casx [%i3], %l3, %o0
14200! move %o0(upper) -> %o0(upper)
14201! move %o0(lower) -> %o0(lower)
14202add %l4, 1, %l4
14203
14204P843: !_PREFETCH [6] (Int)
14205sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
14206sub %i0, %i2, %i2
14207prefetch [%i2 + 0], 2
14208
14209P844: !_CASX [14] (maybe <- 0x168) (Int)
14210sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
14211add %i0, %i3, %i3
14212add %i3, 8, %l6
14213ldx [%l6], %o1
14214! move %o1(upper) -> %o1(upper)
14215! move %o1(lower) -> %o1(lower)
14216mov %o1, %l3
14217mov %l4, %o2
14218casx [%l6], %l3, %o2
14219! move %o2(upper) -> %o2(upper)
14220! move %o2(lower) -> %o2(lower)
14221add %l4, 1, %l4
14222
14223P845: !_MEMBAR (FP)
14224
14225P846: !_BST [7] (maybe <- 0x3f800107) (FP) (CBR)
14226wr %g0, 0xf0, %asi
14227! preparing store val #0, next val will be in f32
14228fmovs %f16, %f20
14229fadds %f16, %f17, %f16
14230! preparing store val #1, next val will be in f33
14231fmovs %f16, %f21
14232fadds %f16, %f17, %f16
14233! preparing store val #2, next val will be in f35
14234fmovd %f20, %f32
14235fmovs %f16, %f21
14236fadds %f16, %f17, %f16
14237fmovd %f20, %f34
14238membar #Sync
14239stda %f32, [%i2 + 0 ] %asi
14240
14241! cbranch
14242andcc %l0, 1, %g0
14243be,pt %xcc, TARGET846
14244nop
14245RET846:
14246
14247! lfsr step begin
14248srlx %l0, 1, %o5
14249xnor %o5, %l0, %o5
14250sllx %o5, 63, %o5
14251or %o5, %l0, %l0
14252srlx %l0, 1, %l0
14253
14254
14255P847: !_MEMBAR (FP)
14256
14257P848: !_BSTC [1] (maybe <- 0x3f80010a) (FP)
14258wr %g0, 0xe0, %asi
14259! preparing store val #0, next val will be in f32
14260fmovs %f16, %f20
14261fadds %f16, %f17, %f16
14262! preparing store val #1, next val will be in f33
14263fmovs %f16, %f21
14264fadds %f16, %f17, %f16
14265! preparing store val #2, next val will be in f35
14266fmovd %f20, %f32
14267fmovs %f16, %f21
14268fadds %f16, %f17, %f16
14269fmovd %f20, %f34
14270membar #Sync
14271stda %f32, [%i0 + 0 ] %asi
14272
14273P849: !_MEMBAR (FP)
14274membar #StoreLoad
14275
14276P850: !_SWAP [9] (maybe <- 0x169) (Int)
14277sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
14278add %i0, %i2, %i2
14279mov %l4, %o3
14280swap [%i2 + 0], %o3
14281! move %o3(lower) -> %o3(upper)
14282sllx %o3, 32, %o3
14283add %l4, 1, %l4
14284
14285P851: !_MEMBAR (FP)
14286
14287P852: !_BST [8] (maybe <- 0x3f80010d) (FP)
14288wr %g0, 0xf0, %asi
14289sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
14290sub %i0, %i3, %i3
14291! preparing store val #0, next val will be in f32
14292fmovs %f16, %f20
14293fadds %f16, %f17, %f16
14294! preparing store val #1, next val will be in f33
14295fmovs %f16, %f21
14296fadds %f16, %f17, %f16
14297! preparing store val #2, next val will be in f35
14298fmovd %f20, %f32
14299fmovs %f16, %f21
14300fadds %f16, %f17, %f16
14301fmovd %f20, %f34
14302membar #Sync
14303stda %f32, [%i3 + 0 ] %asi
14304
14305P853: !_MEMBAR (FP)
14306membar #StoreLoad
14307
14308P854: !_DWST [7] (maybe <- 0x16a) (Int)
14309sllx %l4, 32, %l6
14310add %l4, 1, %l4
14311or %l6, %l4, %l6
14312stx %l6, [%i3 + 0]
14313add %l4, 1, %l4
14314
14315P855: !_SWAP [9] (maybe <- 0x16c) (Int)
14316mov %l4, %l7
14317swap [%i2 + 0], %l7
14318! move %l7(lower) -> %o3(lower)
14319srl %l7, 0, %l3
14320or %l3, %o3, %o3
14321add %l4, 1, %l4
14322
14323P856: !_ST [21] (maybe <- 0x16d) (Int)
14324sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
14325sub %i0, %i2, %i2
14326stw %l4, [%i2 + 0 ]
14327add %l4, 1, %l4
14328
14329P857: !_DWST_BINIT [0] (maybe <- 0x16e) (Int)
14330wr %g0, 0xe2, %asi
14331sllx %l4, 32, %l7
14332add %l4, 1, %l4
14333or %l7, %l4, %l7
14334stxa %l7, [%i0 + 0] %asi
14335add %l4, 1, %l4
14336
14337P858: !_MEMBAR (Int) (Branch target of P133)
14338membar #StoreLoad
14339ba P859
14340nop
14341
14342TARGET133:
14343ba RET133
14344nop
14345
14346
14347P859: !_DWLD [15] (Int) (CBR)
14348sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
14349sub %i0, %i3, %i3
14350ldx [%i3 + 0], %o4
14351! move %o4(upper) -> %o4(upper)
14352! move %o4(lower) -> %o4(lower)
14353!---- flushing int results buffer----
14354mov %o0, %l5
14355mov %o1, %l5
14356mov %o2, %l5
14357mov %o3, %l5
14358mov %o4, %l5
14359
14360! cbranch
14361andcc %l0, 1, %g0
14362be,pt %xcc, TARGET859
14363nop
14364RET859:
14365
14366! lfsr step begin
14367srlx %l0, 1, %o5
14368xnor %o5, %l0, %o5
14369sllx %o5, 63, %o5
14370or %o5, %l0, %l0
14371srlx %l0, 1, %l0
14372
14373
14374P860: !_DWST [9] (maybe <- 0x170) (Int)
14375sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
14376add %i0, %i2, %i2
14377sllx %l4, 32, %l3
14378add %l4, 1, %l4
14379or %l3, %l4, %l3
14380stx %l3, [%i2 + 0]
14381add %l4, 1, %l4
14382
14383P861: !_DWST_BINIT [22] (maybe <- 0x172) (Int) (Branch target of P663)
14384wr %g0, 0xe2, %asi
14385sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
14386sub %i0, %i3, %i3
14387sllx %l4, 32, %o5
14388add %l4, 1, %l4
14389or %o5, %l4, %o5
14390stxa %o5, [%i3 + 0] %asi
14391add %l4, 1, %l4
14392ba P862
14393nop
14394
14395TARGET663:
14396ba RET663
14397nop
14398
14399
14400P862: !_MEMBAR (Int)
14401membar #StoreLoad
14402
14403P863: !_BLD [9] (FP)
14404wr %g0, 0xf0, %asi
14405ldda [%i2 + 0] %asi, %f32
14406membar #Sync
14407! 3 addresses covered
14408fmovd %f32, %f18
14409fmovs %f18, %f7
14410fmovs %f19, %f8
14411fmovd %f34, %f18
14412fmovs %f19, %f9
14413
14414P864: !_MEMBAR (FP)
14415
14416P865: !_BST [19] (maybe <- 0x3f800110) (FP) (CBR)
14417wr %g0, 0xf0, %asi
14418sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
14419add %i0, %i2, %i2
14420! preparing store val #0, next val will be in f32
14421fmovs %f16, %f20
14422fadds %f16, %f17, %f16
14423! preparing store val #1, next val will be in f33
14424fmovs %f16, %f21
14425fadds %f16, %f17, %f16
14426! preparing store val #2, next val will be in f35
14427fmovd %f20, %f32
14428fmovs %f16, %f21
14429fadds %f16, %f17, %f16
14430fmovd %f20, %f34
14431membar #Sync
14432stda %f32, [%i2 + 0 ] %asi
14433
14434! cbranch
14435andcc %l0, 1, %g0
14436be,pn %xcc, TARGET865
14437nop
14438RET865:
14439
14440! lfsr step begin
14441srlx %l0, 1, %l6
14442xnor %l6, %l0, %l6
14443sllx %l6, 63, %l6
14444or %l6, %l0, %l0
14445srlx %l0, 1, %l0
14446
14447
14448P866: !_MEMBAR (FP)
14449membar #StoreLoad
14450
14451P867: !_DWLD [18] (FP)
14452ldd [%i2 + 0], %f10
14453! 2 addresses covered
14454
14455P868: !_CASX [18] (maybe <- 0x174) (Int)
14456ldx [%i2], %o0
14457! move %o0(upper) -> %o0(upper)
14458! move %o0(lower) -> %o0(lower)
14459mov %o0, %l7
14460sllx %l4, 32, %o1
14461add %l4, 1, %l4
14462or %l4, %o1, %o1
14463casx [%i2], %l7, %o1
14464! move %o1(upper) -> %o1(upper)
14465! move %o1(lower) -> %o1(lower)
14466add %l4, 1, %l4
14467
14468P869: !_CASX [3] (maybe <- 0x176) (Int)
14469ldx [%i1], %o2
14470! move %o2(upper) -> %o2(upper)
14471! move %o2(lower) -> %o2(lower)
14472mov %o2, %l7
14473sllx %l4, 32, %o3
14474add %l4, 1, %l4
14475or %l4, %o3, %o3
14476casx [%i1], %l7, %o3
14477! move %o3(upper) -> %o3(upper)
14478! move %o3(lower) -> %o3(lower)
14479add %l4, 1, %l4
14480
14481P870: !_LDD [3] (Int)
14482ldd [%i1 + 0], %l6
14483! move %l6(lower) -> %o4(upper)
14484sllx %l6, 32, %o4
14485! move %l7(lower) -> %o4(lower)
14486or %l7, %o4, %o4
14487!---- flushing int results buffer----
14488mov %o0, %l5
14489mov %o1, %l5
14490mov %o2, %l5
14491mov %o3, %l5
14492mov %o4, %l5
14493
14494P871: !_LDD [12] (Int)
14495sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
14496add %i0, %i3, %i3
14497ldd [%i3 + 0], %l6
14498! move %l6(lower) -> %o0(upper)
14499sllx %l6, 32, %o0
14500! move %l7(lower) -> %o0(lower)
14501or %l7, %o0, %o0
14502
14503P872: !_PREFETCH [8] (Int)
14504sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
14505sub %i0, %i2, %i2
14506prefetch [%i2 + 12], 28
14507
14508P873: !_MEMBAR (FP)
14509
14510P874: !_BST [3] (maybe <- 0x3f800113) (FP)
14511wr %g0, 0xf0, %asi
14512! preparing store val #0, next val will be in f32
14513fmovs %f16, %f20
14514fadds %f16, %f17, %f16
14515! preparing store val #1, next val will be in f33
14516fmovs %f16, %f21
14517fadds %f16, %f17, %f16
14518! preparing store val #2, next val will be in f35
14519fmovd %f20, %f32
14520fmovs %f16, %f21
14521fadds %f16, %f17, %f16
14522fmovd %f20, %f34
14523membar #Sync
14524stda %f32, [%i1 + 0 ] %asi
14525
14526P875: !_MEMBAR (FP)
14527membar #StoreLoad
14528
14529P876: !_CAS [4] (maybe <- 0x178) (Int)
14530add %i1, 4, %l3
14531lduw [%l3], %o1
14532mov %o1, %o5
14533! move %o5(lower) -> %o1(upper)
14534sllx %o5, 32, %o1
14535mov %l4, %l7
14536cas [%l3], %o5, %l7
14537! move %l7(lower) -> %o1(lower)
14538srl %l7, 0, %o5
14539or %o5, %o1, %o1
14540add %l4, 1, %l4
14541
14542P877: !_MEMBAR (FP) (CBR)
14543
14544! cbranch
14545andcc %l0, 1, %g0
14546be,pt %xcc, TARGET877
14547nop
14548RET877:
14549
14550! lfsr step begin
14551srlx %l0, 1, %o5
14552xnor %o5, %l0, %o5
14553sllx %o5, 63, %o5
14554or %o5, %l0, %l0
14555srlx %l0, 1, %l0
14556
14557
14558P878: !_BST [0] (maybe <- 0x3f800116) (FP)
14559wr %g0, 0xf0, %asi
14560! preparing store val #0, next val will be in f32
14561fmovs %f16, %f20
14562fadds %f16, %f17, %f16
14563! preparing store val #1, next val will be in f33
14564fmovs %f16, %f21
14565fadds %f16, %f17, %f16
14566! preparing store val #2, next val will be in f35
14567fmovd %f20, %f32
14568fmovs %f16, %f21
14569fadds %f16, %f17, %f16
14570fmovd %f20, %f34
14571membar #Sync
14572stda %f32, [%i0 + 0 ] %asi
14573
14574P879: !_MEMBAR (FP)
14575membar #StoreLoad
14576
14577P880: !_DWST [19] (maybe <- 0x179) (Int)
14578sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
14579add %i0, %i3, %i3
14580sllx %l4, 32, %o5
14581add %l4, 1, %l4
14582or %o5, %l4, %o5
14583stx %o5, [%i3 + 0]
14584add %l4, 1, %l4
14585
14586P881: !_DWST_BINIT [8] (maybe <- 0x17b) (Int)
14587wr %g0, 0xe2, %asi
14588mov %l4, %l7
14589stxa %l7, [%i2 + 8] %asi
14590add %l4, 1, %l4
14591
14592P882: !_MEMBAR (Int)
14593membar #StoreLoad
14594
14595P883: !_DWST_BINIT [18] (maybe <- 0x17c) (Int)
14596wr %g0, 0xe2, %asi
14597sllx %l4, 32, %l6
14598add %l4, 1, %l4
14599or %l6, %l4, %l6
14600stxa %l6, [%i3 + 0] %asi
14601add %l4, 1, %l4
14602
14603P884: !_MEMBAR (Int)
14604membar #StoreLoad
14605
14606P885: !_ST_BINIT [6] (maybe <- 0x17e) (Int)
14607wr %g0, 0xe2, %asi
14608stwa %l4, [%i2 + 0] %asi
14609add %l4, 1, %l4
14610
14611P886: !_MEMBAR (Int) (CBR)
14612
14613! cbranch
14614andcc %l0, 1, %g0
14615be,pt %xcc, TARGET886
14616nop
14617RET886:
14618
14619! lfsr step begin
14620srlx %l0, 1, %o5
14621xnor %o5, %l0, %o5
14622sllx %o5, 63, %o5
14623or %o5, %l0, %l0
14624srlx %l0, 1, %l0
14625
14626
14627P887: !_BSTC [12] (maybe <- 0x3f800119) (FP)
14628wr %g0, 0xe0, %asi
14629sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
14630add %i0, %i2, %i2
14631! preparing store val #0, next val will be in f32
14632fmovs %f16, %f20
14633fadds %f16, %f17, %f16
14634! preparing store val #1, next val will be in f33
14635fmovs %f16, %f21
14636fadds %f16, %f17, %f16
14637! preparing store val #2, next val will be in f35
14638fmovd %f20, %f32
14639fmovs %f16, %f21
14640fadds %f16, %f17, %f16
14641fmovd %f20, %f34
14642membar #Sync
14643stda %f32, [%i2 + 0 ] %asi
14644
14645P888: !_MEMBAR (FP)
14646membar #StoreLoad
14647
14648P889: !_ST [14] (maybe <- 0x17f) (Int)
14649stw %l4, [%i2 + 12 ]
14650add %l4, 1, %l4
14651
14652P890: !_CAS [23] (maybe <- 0x180) (Int)
14653sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
14654sub %i0, %i3, %i3
14655add %i3, 12, %o5
14656lduw [%o5], %o2
14657mov %o2, %l7
14658! move %l7(lower) -> %o2(upper)
14659sllx %l7, 32, %o2
14660mov %l4, %l6
14661cas [%o5], %l7, %l6
14662! move %l6(lower) -> %o2(lower)
14663srl %l6, 0, %l7
14664or %l7, %o2, %o2
14665add %l4, 1, %l4
14666
14667P891: !_DWST [21] (maybe <- 0x181) (Int)
14668sllx %l4, 32, %l7
14669add %l4, 1, %l4
14670or %l7, %l4, %l7
14671stx %l7, [%i3 + 0]
14672add %l4, 1, %l4
14673
14674P892: !_ST_BINIT [18] (maybe <- 0x183) (Int)
14675wr %g0, 0xe2, %asi
14676sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
14677add %i0, %i2, %i2
14678stwa %l4, [%i2 + 0] %asi
14679add %l4, 1, %l4
14680
14681P893: !_MEMBAR (Int)
14682membar #StoreLoad
14683
14684P894: !_DWST [0] (maybe <- 0x184) (Int)
14685sllx %l4, 32, %l3
14686add %l4, 1, %l4
14687or %l3, %l4, %l3
14688stx %l3, [%i0 + 0]
14689add %l4, 1, %l4
14690
14691P895: !_MEMBAR (FP)
14692membar #StoreLoad
14693
14694P896: !_BLD [3] (FP)
14695!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #0
14696!Logical addr: 3
14697
14698sethi %hi(0x600000), %o5
14699add %i1, %o5, %i1
14700wr %g0, 0xf0, %asi
14701ldda [%i1 + 0] %asi, %f32
14702membar #Sync
14703! 3 addresses covered
14704fmovd %f32, %f12
14705fmovd %f34, %f18
14706fmovs %f19, %f14
14707
14708P897: !_MEMBAR (FP) (Branch target of P542)
14709ba P898
14710nop
14711
14712TARGET542:
14713ba RET542
14714nop
14715
14716
14717P898: !_PREFETCH [0] (Int)
14718prefetch [%i0 + 0], 3
14719
14720P899: !_DWLD [19] (FP)
14721ldd [%i2 + 0], %f18
14722! 2 addresses covered
14723fmovs %f18, %f15
14724!---- flushing fp results buffer to %f30 ----
14725fmovd %f0, %f30
14726fmovd %f2, %f30
14727fmovd %f4, %f30
14728fmovd %f6, %f30
14729fmovd %f8, %f30
14730fmovd %f10, %f30
14731fmovd %f12, %f30
14732fmovd %f14, %f30
14733!--
14734fmovs %f19, %f0
14735
14736P900: !_MEMBAR (FP)
14737
14738P901: !_BSTC [1] (maybe <- 0x3f80011c) (FP)
14739wr %g0, 0xe0, %asi
14740! preparing store val #0, next val will be in f32
14741fmovs %f16, %f20
14742fadds %f16, %f17, %f16
14743! preparing store val #1, next val will be in f33
14744fmovs %f16, %f21
14745fadds %f16, %f17, %f16
14746! preparing store val #2, next val will be in f35
14747fmovd %f20, %f32
14748fmovs %f16, %f21
14749fadds %f16, %f17, %f16
14750fmovd %f20, %f34
14751membar #Sync
14752stda %f32, [%i0 + 0 ] %asi
14753
14754P902: !_MEMBAR (FP)
14755membar #StoreLoad
14756
14757P903: !_CAS [1] (maybe <- 0x186) (Int)
14758add %i0, 4, %l3
14759lduw [%l3], %o3
14760mov %o3, %o5
14761! move %o5(lower) -> %o3(upper)
14762sllx %o5, 32, %o3
14763mov %l4, %l7
14764cas [%l3], %o5, %l7
14765! move %l7(lower) -> %o3(lower)
14766srl %l7, 0, %o5
14767or %o5, %o3, %o3
14768add %l4, 1, %l4
14769
14770P904: !_MEMBAR (FP)
14771
14772P905: !_BST [1] (maybe <- 0x3f80011f) (FP)
14773wr %g0, 0xf0, %asi
14774! preparing store val #0, next val will be in f32
14775fmovs %f16, %f20
14776fadds %f16, %f17, %f16
14777! preparing store val #1, next val will be in f33
14778fmovs %f16, %f21
14779fadds %f16, %f17, %f16
14780! preparing store val #2, next val will be in f35
14781fmovd %f20, %f32
14782fmovs %f16, %f21
14783fadds %f16, %f17, %f16
14784fmovd %f20, %f34
14785membar #Sync
14786stda %f32, [%i0 + 0 ] %asi
14787
14788P906: !_MEMBAR (FP)
14789membar #StoreLoad
14790
14791P907: !_BLD [11] (FP)
14792wr %g0, 0xf0, %asi
14793sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
14794add %i0, %i3, %i3
14795ldda [%i3 + 0] %asi, %f32
14796membar #Sync
14797! 3 addresses covered
14798fmovd %f32, %f18
14799fmovs %f18, %f1
14800fmovs %f19, %f2
14801fmovd %f34, %f18
14802fmovs %f19, %f3
14803
14804P908: !_MEMBAR (FP)
14805
14806P909: !_SWAP [16] (maybe <- 0x187) (Int)
14807sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
14808sub %i0, %i2, %i2
14809mov %l4, %o4
14810swap [%i2 + 4], %o4
14811! move %o4(lower) -> %o4(upper)
14812sllx %o4, 32, %o4
14813add %l4, 1, %l4
14814
14815P910: !_LDD [0] (Int) (Branch target of P487)
14816ldd [%i0 + 0], %l6
14817! move %l6(lower) -> %o4(lower)
14818or %l6, %o4, %o4
14819!---- flushing int results buffer----
14820mov %o0, %l5
14821mov %o1, %l5
14822mov %o2, %l5
14823mov %o3, %l5
14824mov %o4, %l5
14825! move %l7(lower) -> %o0(upper)
14826sllx %l7, 32, %o0
14827ba P911
14828nop
14829
14830TARGET487:
14831ba RET487
14832nop
14833
14834
14835P911: !_LD [10] (Int)
14836lduw [%i3 + 4], %l6
14837! move %l6(lower) -> %o0(lower)
14838or %l6, %o0, %o0
14839
14840P912: !_SWAP [9] (maybe <- 0x188) (Int)
14841mov %l4, %o1
14842swap [%i3 + 0], %o1
14843! move %o1(lower) -> %o1(upper)
14844sllx %o1, 32, %o1
14845add %l4, 1, %l4
14846
14847P913: !_CASX [1] (maybe <- 0x189) (Int)
14848ldx [%i0], %l3
14849! move %l3(upper) -> %o1(lower)
14850srlx %l3, 32, %l6
14851or %l6, %o1, %o1
14852! move %l3(lower) -> %o2(upper)
14853sllx %l3, 32, %o2
14854mov %l3, %l6
14855sllx %l4, 32, %l3
14856add %l4, 1, %l4
14857or %l4, %l3, %l3
14858casx [%i0], %l6, %l3
14859! move %l3(upper) -> %o2(lower)
14860srlx %l3, 32, %l6
14861or %l6, %o2, %o2
14862! move %l3(lower) -> %o3(upper)
14863sllx %l3, 32, %o3
14864add %l4, 1, %l4
14865
14866P914: !_ST [23] (maybe <- 0x18b) (Int)
14867sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
14868sub %i0, %i3, %i3
14869stw %l4, [%i3 + 12 ]
14870add %l4, 1, %l4
14871
14872P915: !_DWST [11] (maybe <- 0x18c) (Int) (Branch target of P23)
14873sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
14874add %i0, %i2, %i2
14875mov %l4, %l3
14876stx %l3, [%i2 + 8]
14877add %l4, 1, %l4
14878ba P916
14879nop
14880
14881TARGET23:
14882ba RET23
14883nop
14884
14885
14886P916: !_ST [17] (maybe <- 0x18d) (Int)
14887sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
14888sub %i0, %i3, %i3
14889stw %l4, [%i3 + 12 ]
14890add %l4, 1, %l4
14891
14892P917: !_CASX [18] (maybe <- 0x18e) (Int)
14893sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
14894add %i0, %i2, %i2
14895ldx [%i2], %l6
14896! move %l6(upper) -> %o3(lower)
14897srlx %l6, 32, %l7
14898or %l7, %o3, %o3
14899! move %l6(lower) -> %o4(upper)
14900sllx %l6, 32, %o4
14901mov %l6, %l7
14902sllx %l4, 32, %l6
14903add %l4, 1, %l4
14904or %l4, %l6, %l6
14905casx [%i2], %l7, %l6
14906! move %l6(upper) -> %o4(lower)
14907srlx %l6, 32, %l7
14908or %l7, %o4, %o4
14909!---- flushing int results buffer----
14910mov %o0, %l5
14911mov %o1, %l5
14912mov %o2, %l5
14913mov %o3, %l5
14914mov %o4, %l5
14915! move %l6(lower) -> %o0(upper)
14916sllx %l6, 32, %o0
14917add %l4, 1, %l4
14918
14919P918: !_ST_BINIT [11] (maybe <- 0x190) (Int) (LE)
14920wr %g0, 0xea, %asi
14921sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
14922add %i0, %i3, %i3
14923! Change single-word-level endianess (big endian <-> little endian)
14924sethi %hi(0xff00ff00), %o5
14925or %o5, %lo(0xff00ff00), %o5
14926and %l4, %o5, %l3
14927srl %l3, 8, %l3
14928sll %l4, 8, %l7
14929and %l7, %o5, %l7
14930or %l7, %l3, %l7
14931srl %l7, 16, %l3
14932sll %l7, 16, %l7
14933srl %l7, 0, %l7
14934or %l7, %l3, %l7
14935stwa %l7, [%i3 + 12] %asi
14936add %l4, 1, %l4
14937
14938P919: !_MEMBAR (Int) (LE)
14939membar #StoreLoad
14940
14941P920: !_CASX [20] (maybe <- 0x191) (Int)
14942add %i2, 8, %l7
14943ldx [%l7], %l3
14944! move %l3(upper) -> %o0(lower)
14945srlx %l3, 32, %l6
14946or %l6, %o0, %o0
14947! move %l3(lower) -> %o1(upper)
14948sllx %l3, 32, %o1
14949mov %l3, %l6
14950mov %l4, %l3
14951casx [%l7], %l6, %l3
14952! move %l3(upper) -> %o1(lower)
14953srlx %l3, 32, %l6
14954or %l6, %o1, %o1
14955! move %l3(lower) -> %o2(upper)
14956sllx %l3, 32, %o2
14957add %l4, 1, %l4
14958
14959P921: !_DWLD [17] (Int)
14960sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
14961sub %i0, %i2, %i2
14962ldx [%i2 + 8], %l7
14963! move %l7(lower) -> %o2(lower)
14964srl %l7, 0, %l6
14965or %l6, %o2, %o2
14966
14967P922: !_CAS [16] (maybe <- 0x192) (Int)
14968add %i2, 4, %l3
14969lduw [%l3], %o3
14970mov %o3, %o5
14971! move %o5(lower) -> %o3(upper)
14972sllx %o5, 32, %o3
14973mov %l4, %l7
14974cas [%l3], %o5, %l7
14975! move %l7(lower) -> %o3(lower)
14976srl %l7, 0, %o5
14977or %o5, %o3, %o3
14978add %l4, 1, %l4
14979
14980P923: !_LD [6] (Int)
14981sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
14982sub %i0, %i3, %i3
14983lduw [%i3 + 0], %o4
14984! move %o4(lower) -> %o4(upper)
14985sllx %o4, 32, %o4
14986
14987P924: !_LD [7] (Int)
14988lduw [%i3 + 4], %l7
14989! move %l7(lower) -> %o4(lower)
14990or %l7, %o4, %o4
14991!---- flushing int results buffer----
14992mov %o0, %l5
14993mov %o1, %l5
14994mov %o2, %l5
14995mov %o3, %l5
14996mov %o4, %l5
14997
14998P925: !_DWLD [0] (Int)
14999ldx [%i0 + 0], %o0
15000! move %o0(upper) -> %o0(upper)
15001! move %o0(lower) -> %o0(lower)
15002
15003P926: !_MEMBAR (FP)
15004membar #StoreLoad
15005
15006P927: !_BLD [14] (FP) (CBR)
15007wr %g0, 0xf0, %asi
15008sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
15009add %i0, %i2, %i2
15010ldda [%i2 + 0] %asi, %f32
15011membar #Sync
15012! 3 addresses covered
15013fmovd %f32, %f4
15014fmovd %f34, %f18
15015fmovs %f19, %f6
15016
15017! cbranch
15018andcc %l0, 1, %g0
15019be,pt %xcc, TARGET927
15020nop
15021RET927:
15022
15023! lfsr step begin
15024srlx %l0, 1, %l6
15025xnor %l6, %l0, %l6
15026sllx %l6, 63, %l6
15027or %l6, %l0, %l0
15028srlx %l0, 1, %l0
15029
15030
15031P928: !_MEMBAR (FP)
15032
15033P929: !_CASX [20] (maybe <- 0x193) (Int)
15034sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
15035add %i0, %i3, %i3
15036add %i3, 8, %o5
15037ldx [%o5], %o1
15038! move %o1(upper) -> %o1(upper)
15039! move %o1(lower) -> %o1(lower)
15040mov %o1, %l7
15041mov %l4, %o2
15042casx [%o5], %l7, %o2
15043! move %o2(upper) -> %o2(upper)
15044! move %o2(lower) -> %o2(lower)
15045add %l4, 1, %l4
15046
15047P930: !_ST_BINIT [20] (maybe <- 0x194) (Int) (CBR)
15048wr %g0, 0xe2, %asi
15049stwa %l4, [%i3 + 12] %asi
15050add %l4, 1, %l4
15051
15052! cbranch
15053andcc %l0, 1, %g0
15054be,pn %xcc, TARGET930
15055nop
15056RET930:
15057
15058! lfsr step begin
15059srlx %l0, 1, %l6
15060xnor %l6, %l0, %l6
15061sllx %l6, 63, %l6
15062or %l6, %l0, %l0
15063srlx %l0, 1, %l0
15064
15065
15066P931: !_MEMBAR (Int)
15067membar #StoreLoad
15068
15069P932: !_DWLD [5] (Int)
15070ldx [%i1 + 8], %o3
15071! move %o3(lower) -> %o3(upper)
15072sllx %o3, 32, %o3
15073
15074P933: !_ST_BINIT [9] (maybe <- 0x195) (Int)
15075wr %g0, 0xe2, %asi
15076sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
15077add %i0, %i2, %i2
15078stwa %l4, [%i2 + 0] %asi
15079add %l4, 1, %l4
15080
15081P934: !_MEMBAR (Int)
15082membar #StoreLoad
15083
15084P935: !_ST_BINIT [0] (maybe <- 0x196) (Int)
15085wr %g0, 0xe2, %asi
15086stwa %l4, [%i0 + 0] %asi
15087add %l4, 1, %l4
15088
15089P936: !_MEMBAR (Int)
15090membar #StoreLoad
15091
15092P937: !_DWST_BINIT [1] (maybe <- 0x197) (Int)
15093wr %g0, 0xe2, %asi
15094sllx %l4, 32, %l7
15095add %l4, 1, %l4
15096or %l7, %l4, %l7
15097stxa %l7, [%i0 + 0] %asi
15098add %l4, 1, %l4
15099
15100P938: !_MEMBAR (Int)
15101membar #StoreLoad
15102
15103P939: !_ST_BINIT [21] (maybe <- 0x199) (Int)
15104wr %g0, 0xe2, %asi
15105sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
15106sub %i0, %i3, %i3
15107stwa %l4, [%i3 + 0] %asi
15108add %l4, 1, %l4
15109
15110P940: !_MEMBAR (Int)
15111membar #StoreLoad
15112
15113P941: !_PREFETCH [3] (Int)
15114prefetch [%i1 + 0], 20
15115
15116P942: !_MEMBAR (FP)
15117membar #StoreLoad
15118
15119P943: !_BLD [2] (FP) (Branch target of P258)
15120wr %g0, 0xf0, %asi
15121ldda [%i0 + 0] %asi, %f32
15122membar #Sync
15123! 3 addresses covered
15124fmovd %f32, %f18
15125fmovs %f18, %f7
15126fmovs %f19, %f8
15127fmovd %f34, %f18
15128fmovs %f19, %f9
15129ba P944
15130nop
15131
15132TARGET258:
15133ba RET258
15134nop
15135
15136
15137P944: !_MEMBAR (FP) (Branch target of P817)
15138ba P945
15139nop
15140
15141TARGET817:
15142ba RET817
15143nop
15144
15145
15146P945: !_CASX [7] (maybe <- 0x19a) (Int)
15147sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
15148sub %i0, %i2, %i2
15149ldx [%i2], %o5
15150! move %o5(upper) -> %o3(lower)
15151srlx %o5, 32, %l3
15152or %l3, %o3, %o3
15153! move %o5(lower) -> %o4(upper)
15154sllx %o5, 32, %o4
15155mov %o5, %l3
15156sllx %l4, 32, %o5
15157add %l4, 1, %l4
15158or %l4, %o5, %o5
15159casx [%i2], %l3, %o5
15160! move %o5(upper) -> %o4(lower)
15161srlx %o5, 32, %l3
15162or %l3, %o4, %o4
15163!---- flushing int results buffer----
15164mov %o0, %l5
15165mov %o1, %l5
15166mov %o2, %l5
15167mov %o3, %l5
15168mov %o4, %l5
15169! move %o5(lower) -> %o0(upper)
15170sllx %o5, 32, %o0
15171add %l4, 1, %l4
15172
15173P946: !_ST_BINIT [9] (maybe <- 0x19c) (Int)
15174wr %g0, 0xe2, %asi
15175sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
15176add %i0, %i3, %i3
15177stwa %l4, [%i3 + 0] %asi
15178add %l4, 1, %l4
15179
15180P947: !_MEMBAR (Int)
15181membar #StoreLoad
15182
15183P948: !_BLD [9] (FP)
15184wr %g0, 0xf0, %asi
15185ldda [%i3 + 0] %asi, %f32
15186membar #Sync
15187! 3 addresses covered
15188fmovd %f32, %f10
15189fmovd %f34, %f18
15190fmovs %f19, %f12
15191
15192P949: !_MEMBAR (FP) (CBR)
15193
15194! cbranch
15195andcc %l0, 1, %g0
15196be,pt %xcc, TARGET949
15197nop
15198RET949:
15199
15200! lfsr step begin
15201srlx %l0, 1, %o5
15202xnor %o5, %l0, %o5
15203sllx %o5, 63, %o5
15204or %o5, %l0, %l0
15205srlx %l0, 1, %l0
15206
15207
15208P950: !_ST_BINIT [3] (maybe <- 0x19d) (Int)
15209wr %g0, 0xe2, %asi
15210stwa %l4, [%i1 + 0] %asi
15211add %l4, 1, %l4
15212
15213P951: !_MEMBAR (Int)
15214membar #StoreLoad
15215
15216P952: !_PREFETCH [18] (Int) (Branch target of P450)
15217sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
15218add %i0, %i2, %i2
15219prefetch [%i2 + 0], 2
15220ba P953
15221nop
15222
15223TARGET450:
15224ba RET450
15225nop
15226
15227
15228P953: !_DWLD [3] (Int)
15229ldx [%i1 + 0], %l3
15230! move %l3(upper) -> %o0(lower)
15231srlx %l3, 32, %o5
15232or %o5, %o0, %o0
15233! move %l3(lower) -> %o1(upper)
15234sllx %l3, 32, %o1
15235
15236P954: !_ST_BINIT [15] (maybe <- 0x19e) (Int)
15237wr %g0, 0xe2, %asi
15238sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
15239sub %i0, %i3, %i3
15240stwa %l4, [%i3 + 0] %asi
15241add %l4, 1, %l4
15242
15243P955: !_MEMBAR (Int)
15244membar #StoreLoad
15245
15246P956: !_DWST_BINIT [15] (maybe <- 0x19f) (Int)
15247wr %g0, 0xe2, %asi
15248sllx %l4, 32, %l3
15249add %l4, 1, %l4
15250or %l3, %l4, %l3
15251stxa %l3, [%i3 + 0] %asi
15252add %l4, 1, %l4
15253
15254P957: !_MEMBAR (Int)
15255membar #StoreLoad
15256
15257P958: !_ST_BINIT [11] (maybe <- 0x1a1) (Int)
15258wr %g0, 0xe2, %asi
15259sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
15260add %i0, %i2, %i2
15261stwa %l4, [%i2 + 12] %asi
15262add %l4, 1, %l4
15263
15264P959: !_MEMBAR (Int)
15265membar #StoreLoad
15266
15267P960: !_DWLD [0] (Int)
15268ldx [%i0 + 0], %l3
15269! move %l3(upper) -> %o1(lower)
15270srlx %l3, 32, %o5
15271or %o5, %o1, %o1
15272! move %l3(lower) -> %o2(upper)
15273sllx %l3, 32, %o2
15274
15275P961: !_LD [1] (Int)
15276lduw [%i0 + 4], %l7
15277! move %l7(lower) -> %o2(lower)
15278or %l7, %o2, %o2
15279
15280P962: !_CASX [19] (maybe <- 0x1a2) (Int)
15281sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
15282add %i0, %i3, %i3
15283ldx [%i3], %o3
15284! move %o3(upper) -> %o3(upper)
15285! move %o3(lower) -> %o3(lower)
15286mov %o3, %o5
15287sllx %l4, 32, %o4
15288add %l4, 1, %l4
15289or %l4, %o4, %o4
15290casx [%i3], %o5, %o4
15291! move %o4(upper) -> %o4(upper)
15292! move %o4(lower) -> %o4(lower)
15293!---- flushing int results buffer----
15294mov %o0, %l5
15295mov %o1, %l5
15296mov %o2, %l5
15297mov %o3, %l5
15298mov %o4, %l5
15299add %l4, 1, %l4
15300
15301P963: !_REPLACEMENT [20] (Int)
15302sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
15303sub %i0, %i2, %i2
15304sethi %hi(0x20000), %o5
15305ld [%i2+12], %l6
15306st %l6, [%i2+12]
15307add %i2, %o5, %l3
15308ld [%l3+12], %l6
15309st %l6, [%l3+12]
15310add %l3, %o5, %l3
15311ld [%l3+12], %l6
15312st %l6, [%l3+12]
15313add %l3, %o5, %l3
15314ld [%l3+12], %l6
15315st %l6, [%l3+12]
15316add %l3, %o5, %l3
15317ld [%l3+12], %l6
15318st %l6, [%l3+12]
15319add %l3, %o5, %l3
15320ld [%l3+12], %l6
15321st %l6, [%l3+12]
15322add %l3, %o5, %l3
15323ld [%l3+12], %l6
15324st %l6, [%l3+12]
15325add %l3, %o5, %l3
15326ld [%l3+12], %l6
15327st %l6, [%l3+12]
15328
15329P964: !_DWLD [10] (Int) (CBR)
15330sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
15331add %i0, %i3, %i3
15332ldx [%i3 + 0], %o0
15333! move %o0(upper) -> %o0(upper)
15334! move %o0(lower) -> %o0(lower)
15335
15336! cbranch
15337andcc %l0, 1, %g0
15338be,pt %xcc, TARGET964
15339nop
15340RET964:
15341
15342! lfsr step begin
15343srlx %l0, 1, %l3
15344xnor %l3, %l0, %l3
15345sllx %l3, 63, %l3
15346or %l3, %l0, %l0
15347srlx %l0, 1, %l0
15348
15349
15350P965: !_SWAP [9] (maybe <- 0x1a4) (Int)
15351mov %l4, %o1
15352swap [%i3 + 0], %o1
15353! move %o1(lower) -> %o1(upper)
15354sllx %o1, 32, %o1
15355add %l4, 1, %l4
15356
15357P966: !_ST [13] (maybe <- 0x1a5) (Int)
15358sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
15359add %i0, %i2, %i2
15360stw %l4, [%i2 + 4 ]
15361add %l4, 1, %l4
15362
15363P967: !_ST [5] (maybe <- 0x1a6) (Int)
15364stw %l4, [%i1 + 12 ]
15365add %l4, 1, %l4
15366
15367P968: !_CAS [4] (maybe <- 0x1a7) (Int)
15368add %i1, 4, %o5
15369lduw [%o5], %l6
15370mov %l6, %l7
15371! move %l7(lower) -> %o1(lower)
15372or %l7, %o1, %o1
15373mov %l4, %o2
15374cas [%o5], %l7, %o2
15375! move %o2(lower) -> %o2(upper)
15376sllx %o2, 32, %o2
15377add %l4, 1, %l4
15378
15379P969: !_CAS [20] (maybe <- 0x1a8) (Int)
15380sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
15381add %i0, %i3, %i3
15382add %i3, 12, %o5
15383lduw [%o5], %l6
15384mov %l6, %l7
15385! move %l7(lower) -> %o2(lower)
15386or %l7, %o2, %o2
15387mov %l4, %o3
15388cas [%o5], %l7, %o3
15389! move %o3(lower) -> %o3(upper)
15390sllx %o3, 32, %o3
15391add %l4, 1, %l4
15392
15393P970: !_REPLACEMENT [5] (Int)
15394sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
15395sub %i0, %i2, %i2
15396sethi %hi(0x20000), %l7
15397ld [%i2+12], %l3
15398st %l3, [%i2+12]
15399add %i2, %l7, %o5
15400ld [%o5+12], %l3
15401st %l3, [%o5+12]
15402add %o5, %l7, %o5
15403ld [%o5+12], %l3
15404st %l3, [%o5+12]
15405add %o5, %l7, %o5
15406ld [%o5+12], %l3
15407st %l3, [%o5+12]
15408add %o5, %l7, %o5
15409ld [%o5+12], %l3
15410st %l3, [%o5+12]
15411add %o5, %l7, %o5
15412ld [%o5+12], %l3
15413st %l3, [%o5+12]
15414add %o5, %l7, %o5
15415ld [%o5+12], %l3
15416st %l3, [%o5+12]
15417add %o5, %l7, %o5
15418ld [%o5+12], %l3
15419st %l3, [%o5+12]
15420
15421P971: !_DWLD [3] (Int)
15422ldx [%i1 + 0], %l7
15423! move %l7(upper) -> %o3(lower)
15424srlx %l7, 32, %l6
15425or %l6, %o3, %o3
15426! move %l7(lower) -> %o4(upper)
15427sllx %l7, 32, %o4
15428
15429P972: !_LDD [20] (Int)
15430ldd [%i3 + 8], %l6
15431! move %l7(lower) -> %o4(lower)
15432or %l7, %o4, %o4
15433!---- flushing int results buffer----
15434mov %o0, %l5
15435mov %o1, %l5
15436mov %o2, %l5
15437mov %o3, %l5
15438mov %o4, %l5
15439
15440P973: !_ST [18] (maybe <- 0x3f800122) (FP)
15441! preparing store val #0, next val will be in f20
15442fmovs %f16, %f20
15443fadds %f16, %f17, %f16
15444st %f20, [%i3 + 0 ]
15445
15446P974: !_PREFETCH [17] (Int)
15447sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
15448sub %i0, %i3, %i3
15449prefetch [%i3 + 12], 21
15450
15451P975: !_SWAP [17] (maybe <- 0x1a9) (Int)
15452mov %l4, %o0
15453swap [%i3 + 12], %o0
15454! move %o0(lower) -> %o0(upper)
15455sllx %o0, 32, %o0
15456add %l4, 1, %l4
15457
15458P976: !_PREFETCH [20] (Int)
15459sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
15460add %i0, %i2, %i2
15461prefetch [%i2 + 12], 20
15462
15463P977: !_DWLD [12] (Int) (Branch target of P877)
15464sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
15465add %i0, %i3, %i3
15466ldx [%i3 + 0], %o5
15467! move %o5(upper) -> %o0(lower)
15468srlx %o5, 32, %l7
15469or %l7, %o0, %o0
15470! move %o5(lower) -> %o1(upper)
15471sllx %o5, 32, %o1
15472ba P978
15473nop
15474
15475TARGET877:
15476ba RET877
15477nop
15478
15479
15480P978: !_ST [0] (maybe <- 0x1aa) (Int)
15481stw %l4, [%i0 + 0 ]
15482add %l4, 1, %l4
15483
15484P979: !_DWLD [2] (Int)
15485ldx [%i0 + 8], %l3
15486! move %l3(lower) -> %o1(lower)
15487srl %l3, 0, %o5
15488or %o5, %o1, %o1
15489
15490P980: !_LD [1] (Int)
15491lduw [%i0 + 4], %o2
15492! move %o2(lower) -> %o2(upper)
15493sllx %o2, 32, %o2
15494
15495P981: !_MEMBAR (FP)
15496
15497P982: !_BST [7] (maybe <- 0x3f800123) (FP)
15498wr %g0, 0xf0, %asi
15499sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
15500sub %i0, %i2, %i2
15501! preparing store val #0, next val will be in f32
15502fmovs %f16, %f20
15503fadds %f16, %f17, %f16
15504! preparing store val #1, next val will be in f33
15505fmovs %f16, %f21
15506fadds %f16, %f17, %f16
15507! preparing store val #2, next val will be in f35
15508fmovd %f20, %f32
15509fmovs %f16, %f21
15510fadds %f16, %f17, %f16
15511fmovd %f20, %f34
15512membar #Sync
15513stda %f32, [%i2 + 0 ] %asi
15514
15515P983: !_MEMBAR (FP)
15516membar #StoreLoad
15517
15518P984: !_DWST_BINIT [16] (maybe <- 0x1ab) (Int)
15519wr %g0, 0xe2, %asi
15520sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
15521sub %i0, %i3, %i3
15522sllx %l4, 32, %l7
15523add %l4, 1, %l4
15524or %l7, %l4, %l7
15525stxa %l7, [%i3 + 0] %asi
15526add %l4, 1, %l4
15527
15528P985: !_MEMBAR (Int)
15529membar #StoreLoad
15530
15531P986: !_DWST_BINIT [19] (maybe <- 0x1ad) (Int)
15532wr %g0, 0xe2, %asi
15533sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
15534add %i0, %i2, %i2
15535sllx %l4, 32, %l6
15536add %l4, 1, %l4
15537or %l6, %l4, %l6
15538stxa %l6, [%i2 + 0] %asi
15539add %l4, 1, %l4
15540
15541P987: !_MEMBAR (Int)
15542membar #StoreLoad
15543
15544P988: !_DWLD [9] (Int) (CBR)
15545sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
15546add %i0, %i3, %i3
15547ldx [%i3 + 0], %l6
15548! move %l6(upper) -> %o2(lower)
15549srlx %l6, 32, %l3
15550or %l3, %o2, %o2
15551! move %l6(lower) -> %o3(upper)
15552sllx %l6, 32, %o3
15553
15554! cbranch
15555andcc %l0, 1, %g0
15556be,pt %xcc, TARGET988
15557nop
15558RET988:
15559
15560! lfsr step begin
15561srlx %l0, 1, %l7
15562xnor %l7, %l0, %l7
15563sllx %l7, 63, %l7
15564or %l7, %l0, %l0
15565srlx %l0, 1, %l0
15566
15567
15568P989: !_DWST [19] (maybe <- 0x1af) (Int)
15569sllx %l4, 32, %o5
15570add %l4, 1, %l4
15571or %o5, %l4, %o5
15572stx %o5, [%i2 + 0]
15573add %l4, 1, %l4
15574
15575P990: !_DWLD [14] (Int)
15576sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
15577add %i0, %i2, %i2
15578ldx [%i2 + 8], %o5
15579! move %o5(lower) -> %o3(lower)
15580srl %o5, 0, %l7
15581or %l7, %o3, %o3
15582
15583P991: !_LDD [20] (Int)
15584sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
15585add %i0, %i3, %i3
15586ldd [%i3 + 8], %l6
15587! move %l7(lower) -> %o4(upper)
15588sllx %l7, 32, %o4
15589
15590P992: !_MEMBAR (FP)
15591
15592P993: !_BSTC [6] (maybe <- 0x3f800126) (FP)
15593wr %g0, 0xe0, %asi
15594sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
15595sub %i0, %i2, %i2
15596! preparing store val #0, next val will be in f32
15597fmovs %f16, %f20
15598fadds %f16, %f17, %f16
15599! preparing store val #1, next val will be in f33
15600fmovs %f16, %f21
15601fadds %f16, %f17, %f16
15602! preparing store val #2, next val will be in f35
15603fmovd %f20, %f32
15604fmovs %f16, %f21
15605fadds %f16, %f17, %f16
15606fmovd %f20, %f34
15607membar #Sync
15608stda %f32, [%i2 + 0 ] %asi
15609
15610P994: !_MEMBAR (FP)
15611membar #StoreLoad
15612
15613P995: !_BLD [11] (FP) (CBR)
15614wr %g0, 0xf0, %asi
15615sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
15616add %i0, %i3, %i3
15617ldda [%i3 + 0] %asi, %f32
15618membar #Sync
15619! 3 addresses covered
15620fmovd %f32, %f18
15621fmovs %f18, %f13
15622fmovs %f19, %f14
15623fmovd %f34, %f18
15624fmovs %f19, %f15
15625!---- flushing fp results buffer to %f30 ----
15626fmovd %f0, %f30
15627fmovd %f2, %f30
15628fmovd %f4, %f30
15629fmovd %f6, %f30
15630fmovd %f8, %f30
15631fmovd %f10, %f30
15632fmovd %f12, %f30
15633fmovd %f14, %f30
15634!--
15635
15636! cbranch
15637andcc %l0, 1, %g0
15638be,pn %xcc, TARGET995
15639nop
15640RET995:
15641
15642! lfsr step begin
15643srlx %l0, 1, %o5
15644xnor %o5, %l0, %o5
15645sllx %o5, 63, %o5
15646or %o5, %l0, %l0
15647srlx %l0, 1, %l0
15648
15649
15650P996: !_MEMBAR (FP)
15651
15652P997: !_BSTC [9] (maybe <- 0x3f800129) (FP)
15653wr %g0, 0xe0, %asi
15654! preparing store val #0, next val will be in f32
15655fmovs %f16, %f20
15656fadds %f16, %f17, %f16
15657! preparing store val #1, next val will be in f33
15658fmovs %f16, %f21
15659fadds %f16, %f17, %f16
15660! preparing store val #2, next val will be in f35
15661fmovd %f20, %f32
15662fmovs %f16, %f21
15663fadds %f16, %f17, %f16
15664fmovd %f20, %f34
15665membar #Sync
15666stda %f32, [%i3 + 0 ] %asi
15667
15668P998: !_MEMBAR (FP)
15669membar #StoreLoad
15670
15671P999: !_DWLD [11] (Int)
15672ldx [%i3 + 8], %l3
15673! move %l3(lower) -> %o4(lower)
15674srl %l3, 0, %o5
15675or %o5, %o4, %o4
15676!---- flushing int results buffer----
15677mov %o0, %l5
15678mov %o1, %l5
15679mov %o2, %l5
15680mov %o3, %l5
15681mov %o4, %l5
15682
15683P1000: !_PREFETCH [12] (Int) (Loop exit)
15684sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
15685add %i0, %i2, %i2
15686prefetch [%i2 + 0], 22
15687loop_exit_0_0:
15688sub %l2, 1, %l2
15689cmp %l2, 0
15690bg loop_entry_0_0
15691nop
15692
15693P1001: !_MEMBAR (Int) (CBR)
15694membar #StoreLoad
15695
15696! cbranch
15697andcc %l0, 1, %g0
15698be,pt %xcc, TARGET1001
15699nop
15700RET1001:
15701
15702! lfsr step begin
15703srlx %l0, 1, %l7
15704xnor %l7, %l0, %l7
15705sllx %l7, 63, %l7
15706or %l7, %l0, %l0
15707srlx %l0, 1, %l0
15708
15709
15710END_NODES0: ! Test instruction sequence for CPU 0 ends
15711sethi %hi(0xdead0e0f), %o5
15712or %o5, %lo(0xdead0e0f), %o5
15713! move %o5(lower) -> %o0(upper)
15714sllx %o5, 32, %o0
15715sethi %hi(0xdead0e0f), %o5
15716or %o5, %lo(0xdead0e0f), %o5
15717stw %o5, [%i5]
15718ld [%i5], %f0
15719!---- flushing int results buffer----
15720mov %o0, %l5
15721!---- flushing fp results buffer to %f30 ----
15722fmovs %f0, %f30
15723!--
15724
15725restore
15726retl
15727nop
15728!-----------------
15729
15730! register usage:
15731! %i0 %i1 : base registers for first 2 regions
15732! %i2 %i3 : cache registers for 8 regions
15733! %i4 fixed pointer to per-cpu results area
15734! %l1 moving pointer to per-cpu FP results area
15735! %o7 moving pointer to per-cpu integer results area
15736! %i5 pointer to per-cpu private area
15737! %l0 holds lfsr, used as source of random bits
15738! %l2 loop count register
15739! %f16 running counter for unique fp store values
15740! %f17 holds increment value for fp counter
15741! %l4 running counter for unique integer store values (increment value is always 1)
15742! %l5 move-to register for load values (simulation only)
15743! %f30 move-to register for FP values (simulation only)
15744! %i4 holds the instructions count which is used for interrupt ordering
15745! %i4 holds the thread_id (OBP only)
15746! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage
15747! %l3 %l6 %l7 %o5 : 4 temporary registers
15748! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
15749! %f0-f15 FP results buffer registers
15750! %f32-f47 FP block load/store registers
15751
15752func1:
15753! instruction sequence begins
15754save %sp, -192, %sp
15755
15756! Force %i0-%i3 to be 64-byte aligned
15757add %i0, 63, %i0
15758andn %i0, 63, %i0
15759
15760add %i1, 63, %i1
15761andn %i1, 63, %i1
15762
15763add %i2, 63, %i2
15764andn %i2, 63, %i2
15765
15766add %i3, 63, %i3
15767andn %i3, 63, %i3
15768
15769add %i4, 63, %i4
15770andn %i4, 63, %i4
15771
15772add %i5, 63, %i5
15773andn %i5, 63, %i5
15774
15775
15776! Initialize pointer to FP load results area
15777mov %i4, %l1
15778
15779! Initialize pointer to integer load results area
15780sethi %hi(0x80000), %o7
15781or %o7, %lo(0x80000), %o7
15782add %o7, %l1, %o7
15783
15784! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info
15785mov 0x0, %i4
15786
15787! Initialize %f0-%f62 to 0xdeadbee0deadbee1
15788sethi %hi(0xdeadbee0), %l7
15789or %l7, %lo(0xdeadbee0), %l7
15790stw %l7, [%i5]
15791sethi %hi(0xdeadbee1), %l7
15792or %l7, %lo(0xdeadbee1), %l7
15793stw %l7, [%i5+4]
15794ldd [%i5], %f0
15795fmovd %f0, %f2
15796fmovd %f0, %f4
15797fmovd %f0, %f6
15798fmovd %f0, %f8
15799fmovd %f0, %f10
15800fmovd %f0, %f12
15801fmovd %f0, %f14
15802fmovd %f0, %f16
15803fmovd %f0, %f18
15804fmovd %f0, %f20
15805fmovd %f0, %f22
15806fmovd %f0, %f24
15807fmovd %f0, %f26
15808fmovd %f0, %f28
15809fmovd %f0, %f30
15810fmovd %f0, %f32
15811fmovd %f0, %f34
15812fmovd %f0, %f36
15813fmovd %f0, %f38
15814fmovd %f0, %f40
15815fmovd %f0, %f42
15816fmovd %f0, %f44
15817fmovd %f0, %f46
15818fmovd %f0, %f48
15819fmovd %f0, %f50
15820fmovd %f0, %f52
15821fmovd %f0, %f54
15822fmovd %f0, %f56
15823fmovd %f0, %f58
15824fmovd %f0, %f60
15825fmovd %f0, %f62
15826
15827! Signature for extract_loads script to start extracting load values for this stream
15828sethi %hi(0x01deade1), %l7
15829or %l7, %lo(0x01deade1), %l7
15830stw %l7, [%i5]
15831ld [%i5], %f16
15832
15833! Initialize running integer counter in register %l4
15834sethi %hi(0x800001), %l4
15835or %l4, %lo(0x800001), %l4
15836
15837! Initialize running FP counter in register %f16
15838sethi %hi(0x40000001), %l7
15839or %l7, %lo(0x40000001), %l7
15840stw %l7, [%i5]
15841ld [%i5], %f16
15842
15843! Initialize FP counter increment value in register %f17 (constant)
15844sethi %hi(0x34800000), %l7
15845or %l7, %lo(0x34800000), %l7
15846stw %l7, [%i5]
15847ld [%i5], %f17
15848
15849! Initialize LFSR to 0x6f2^4
15850sethi %hi(0x6f2), %l0
15851or %l0, %lo(0x6f2), %l0
15852mulx %l0, %l0, %l0
15853mulx %l0, %l0, %l0
15854
15855BEGIN_NODES1: ! Test instruction sequence for ISTREAM 1 begins
15856
15857P1002: !_LD [9] (Int) (Loop entry)
15858sethi %hi(0x1), %l2
15859or %l2, %lo(0x1), %l2
15860loop_entry_1_0:
15861sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
15862add %i0, %i3, %i3
15863lduw [%i3 + 0], %o0
15864! move %o0(lower) -> %o0(upper)
15865sllx %o0, 32, %o0
15866
15867P1003: !_MEMBAR (FP)
15868membar #StoreLoad
15869
15870P1004: !_BLD [23] (FP)
15871wr %g0, 0xf0, %asi
15872sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
15873sub %i0, %i2, %i2
15874ldda [%i2 + 0] %asi, %f0
15875membar #Sync
15876! 3 addresses covered
15877fmovs %f3, %f2
15878
15879P1005: !_MEMBAR (FP)
15880
15881P1006: !_CAS [9] (maybe <- 0x800001) (Int) (Branch target of P1673)
15882lduw [%i3], %l3
15883mov %l3, %l6
15884! move %l6(lower) -> %o0(lower)
15885or %l6, %o0, %o0
15886mov %l4, %o1
15887cas [%i3], %l6, %o1
15888! move %o1(lower) -> %o1(upper)
15889sllx %o1, 32, %o1
15890add %l4, 1, %l4
15891ba P1007
15892nop
15893
15894TARGET1673:
15895ba RET1673
15896nop
15897
15898
15899P1007: !_LDD [10] (Int)
15900ldd [%i3 + 0], %l6
15901! move %l6(lower) -> %o1(lower)
15902or %l6, %o1, %o1
15903! move %l7(lower) -> %o2(upper)
15904sllx %l7, 32, %o2
15905
15906P1008: !_MEMBAR (FP)
15907
15908P1009: !_BST [0] (maybe <- 0x40000001) (FP) (CBR)
15909wr %g0, 0xf0, %asi
15910! preparing store val #0, next val will be in f32
15911fmovs %f16, %f20
15912fadds %f16, %f17, %f16
15913! preparing store val #1, next val will be in f33
15914fmovs %f16, %f21
15915fadds %f16, %f17, %f16
15916! preparing store val #2, next val will be in f35
15917fmovd %f20, %f32
15918fmovs %f16, %f21
15919fadds %f16, %f17, %f16
15920fmovd %f20, %f34
15921membar #Sync
15922stda %f32, [%i0 + 0 ] %asi
15923
15924! cbranch
15925andcc %l0, 1, %g0
15926be,pt %xcc, TARGET1009
15927nop
15928RET1009:
15929
15930! lfsr step begin
15931srlx %l0, 1, %o5
15932xnor %o5, %l0, %o5
15933sllx %o5, 63, %o5
15934or %o5, %l0, %l0
15935srlx %l0, 1, %l0
15936
15937
15938P1010: !_MEMBAR (FP)
15939membar #StoreLoad
15940
15941P1011: !_DWST_BINIT [22] (maybe <- 0x800002) (Int)
15942wr %g0, 0xe2, %asi
15943sllx %l4, 32, %l3
15944add %l4, 1, %l4
15945or %l3, %l4, %l3
15946stxa %l3, [%i2 + 0] %asi
15947add %l4, 1, %l4
15948
15949P1012: !_MEMBAR (Int)
15950
15951P1013: !_BST [17] (maybe <- 0x40000004) (FP)
15952wr %g0, 0xf0, %asi
15953sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
15954sub %i0, %i3, %i3
15955! preparing store val #0, next val will be in f32
15956fmovs %f16, %f20
15957fadds %f16, %f17, %f16
15958! preparing store val #1, next val will be in f33
15959fmovs %f16, %f21
15960fadds %f16, %f17, %f16
15961! preparing store val #2, next val will be in f35
15962fmovd %f20, %f32
15963fmovs %f16, %f21
15964fadds %f16, %f17, %f16
15965fmovd %f20, %f34
15966membar #Sync
15967stda %f32, [%i3 + 0 ] %asi
15968
15969P1014: !_MEMBAR (FP)
15970membar #StoreLoad
15971
15972P1015: !_ST_BINIT [0] (maybe <- 0x800004) (Int)
15973wr %g0, 0xe2, %asi
15974stwa %l4, [%i0 + 0] %asi
15975add %l4, 1, %l4
15976
15977P1016: !_MEMBAR (Int)
15978membar #StoreLoad
15979
15980P1017: !_ST [0] (maybe <- 0x40000007) (FP)
15981! preparing store val #0, next val will be in f20
15982fmovs %f16, %f20
15983fadds %f16, %f17, %f16
15984st %f20, [%i0 + 0 ]
15985
15986P1018: !_PREFETCH [0] (Int)
15987prefetch [%i0 + 0], 22
15988
15989P1019: !_DWLD [2] (Int)
15990ldx [%i0 + 8], %l6
15991! move %l6(lower) -> %o2(lower)
15992srl %l6, 0, %l3
15993or %l3, %o2, %o2
15994
15995P1020: !_SWAP [13] (maybe <- 0x800005) (Int) (LE)
15996wr %g0, 0x88, %asi
15997sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
15998add %i0, %i2, %i2
15999mov %l4, %o3
16000! Change single-word-level endianess (big endian <-> little endian)
16001sethi %hi(0xff00ff00), %l7
16002or %l7, %lo(0xff00ff00), %l7
16003and %o3, %l7, %o5
16004srl %o5, 8, %o5
16005sll %o3, 8, %o3
16006and %o3, %l7, %o3
16007or %o3, %o5, %o3
16008srl %o3, 16, %o5
16009sll %o3, 16, %o3
16010srl %o3, 0, %o3
16011or %o3, %o5, %o3
16012swapa [%i2 + 4] %asi, %o3
16013! move %o3(lower) -> %o3(upper)
16014sllx %o3, 32, %o3
16015add %l4, 1, %l4
16016
16017P1021: !_DWST_BINIT [7] (maybe <- 0x800006) (Int)
16018wr %g0, 0xe2, %asi
16019sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
16020sub %i0, %i3, %i3
16021sllx %l4, 32, %l6
16022add %l4, 1, %l4
16023or %l6, %l4, %l6
16024stxa %l6, [%i3 + 0] %asi
16025add %l4, 1, %l4
16026
16027P1022: !_MEMBAR (Int)
16028membar #StoreLoad
16029
16030P1023: !_CASX [7] (maybe <- 0x800008) (Int)
16031ldx [%i3], %o5
16032! move %o5(upper) -> %o3(lower)
16033srlx %o5, 32, %l3
16034or %l3, %o3, %o3
16035! move %o5(lower) -> %o4(upper)
16036sllx %o5, 32, %o4
16037mov %o5, %l3
16038sllx %l4, 32, %o5
16039add %l4, 1, %l4
16040or %l4, %o5, %o5
16041casx [%i3], %l3, %o5
16042! move %o5(upper) -> %o4(lower)
16043srlx %o5, 32, %l3
16044or %l3, %o4, %o4
16045!---- flushing int results buffer----
16046mov %o0, %l5
16047mov %o1, %l5
16048mov %o2, %l5
16049mov %o3, %l5
16050mov %o4, %l5
16051! move %o5(lower) -> %o0(upper)
16052sllx %o5, 32, %o0
16053add %l4, 1, %l4
16054
16055P1024: !_CAS [8] (maybe <- 0x80000a) (Int)
16056add %i3, 12, %l6
16057lduw [%l6], %o5
16058mov %o5, %l3
16059! move %l3(lower) -> %o0(lower)
16060or %l3, %o0, %o0
16061mov %l4, %o1
16062cas [%l6], %l3, %o1
16063! move %o1(lower) -> %o1(upper)
16064sllx %o1, 32, %o1
16065add %l4, 1, %l4
16066
16067P1025: !_MEMBAR (FP)
16068
16069P1026: !_BSTC [7] (maybe <- 0x40000008) (FP)
16070wr %g0, 0xe0, %asi
16071! preparing store val #0, next val will be in f32
16072fmovs %f16, %f20
16073fadds %f16, %f17, %f16
16074! preparing store val #1, next val will be in f33
16075fmovs %f16, %f21
16076fadds %f16, %f17, %f16
16077! preparing store val #2, next val will be in f35
16078fmovd %f20, %f32
16079fmovs %f16, %f21
16080fadds %f16, %f17, %f16
16081fmovd %f20, %f34
16082membar #Sync
16083stda %f32, [%i3 + 0 ] %asi
16084
16085P1027: !_MEMBAR (FP)
16086membar #StoreLoad
16087
16088P1028: !_LD [8] (Int) (Branch target of P1763)
16089lduw [%i3 + 12], %l3
16090! move %l3(lower) -> %o1(lower)
16091or %l3, %o1, %o1
16092ba P1029
16093nop
16094
16095TARGET1763:
16096ba RET1763
16097nop
16098
16099
16100P1029: !_LD [23] (Int) (LE)
16101wr %g0, 0x88, %asi
16102sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
16103sub %i0, %i2, %i2
16104lduwa [%i2 + 12] %asi, %o2
16105! move %o2(lower) -> %o2(upper)
16106sllx %o2, 32, %o2
16107
16108P1030: !_LDD [23] (Int)
16109ldd [%i2 + 8], %l6
16110! move %l7(lower) -> %o2(lower)
16111or %l7, %o2, %o2
16112
16113P1031: !_ST_BINIT [21] (maybe <- 0x80000b) (Int)
16114wr %g0, 0xe2, %asi
16115stwa %l4, [%i2 + 0] %asi
16116add %l4, 1, %l4
16117
16118P1032: !_MEMBAR (Int)
16119membar #StoreLoad
16120
16121P1033: !_BLD [14] (FP)
16122wr %g0, 0xf0, %asi
16123sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
16124add %i0, %i3, %i3
16125ldda [%i3 + 0] %asi, %f32
16126membar #Sync
16127! 3 addresses covered
16128fmovd %f32, %f18
16129fmovs %f18, %f3
16130fmovs %f19, %f4
16131fmovd %f34, %f18
16132fmovs %f19, %f5
16133
16134P1034: !_MEMBAR (FP)
16135
16136P1035: !_BSTC [11] (maybe <- 0x4000000b) (FP)
16137wr %g0, 0xe0, %asi
16138sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
16139add %i0, %i2, %i2
16140! preparing store val #0, next val will be in f32
16141fmovs %f16, %f20
16142fadds %f16, %f17, %f16
16143! preparing store val #1, next val will be in f33
16144fmovs %f16, %f21
16145fadds %f16, %f17, %f16
16146! preparing store val #2, next val will be in f35
16147fmovd %f20, %f32
16148fmovs %f16, %f21
16149fadds %f16, %f17, %f16
16150fmovd %f20, %f34
16151membar #Sync
16152stda %f32, [%i2 + 0 ] %asi
16153
16154P1036: !_MEMBAR (FP)
16155membar #StoreLoad
16156
16157P1037: !_CASX [5] (maybe <- 0x80000c) (Int)
16158add %i1, 8, %o5
16159ldx [%o5], %o3
16160! move %o3(upper) -> %o3(upper)
16161! move %o3(lower) -> %o3(lower)
16162mov %o3, %l7
16163mov %l4, %o4
16164casx [%o5], %l7, %o4
16165! move %o4(upper) -> %o4(upper)
16166! move %o4(lower) -> %o4(lower)
16167!---- flushing int results buffer----
16168mov %o0, %l5
16169mov %o1, %l5
16170mov %o2, %l5
16171mov %o3, %l5
16172mov %o4, %l5
16173add %l4, 1, %l4
16174
16175P1038: !_ST_BINIT [7] (maybe <- 0x80000d) (Int)
16176wr %g0, 0xe2, %asi
16177sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
16178sub %i0, %i3, %i3
16179stwa %l4, [%i3 + 4] %asi
16180add %l4, 1, %l4
16181
16182P1039: !_MEMBAR (Int)
16183membar #StoreLoad
16184
16185P1040: !_CASX [6] (maybe <- 0x80000e) (Int)
16186ldx [%i3], %o0
16187! move %o0(upper) -> %o0(upper)
16188! move %o0(lower) -> %o0(lower)
16189mov %o0, %l6
16190sllx %l4, 32, %o1
16191add %l4, 1, %l4
16192or %l4, %o1, %o1
16193casx [%i3], %l6, %o1
16194! move %o1(upper) -> %o1(upper)
16195! move %o1(lower) -> %o1(lower)
16196add %l4, 1, %l4
16197
16198P1041: !_ST_BINIT [1] (maybe <- 0x800010) (Int)
16199wr %g0, 0xe2, %asi
16200stwa %l4, [%i0 + 4] %asi
16201add %l4, 1, %l4
16202
16203P1042: !_MEMBAR (Int)
16204membar #StoreLoad
16205
16206P1043: !_LDD [13] (Int)
16207sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
16208add %i0, %i2, %i2
16209ldd [%i2 + 0], %l6
16210! move %l6(lower) -> %o2(upper)
16211sllx %l6, 32, %o2
16212! move %l7(lower) -> %o2(lower)
16213or %l7, %o2, %o2
16214
16215P1044: !_REPLACEMENT [7] (Int)
16216sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
16217sub %i0, %i3, %i3
16218sethi %hi(0x20000), %l3
16219ld [%i3+4], %l7
16220st %l7, [%i3+4]
16221add %i3, %l3, %l6
16222ld [%l6+4], %l7
16223st %l7, [%l6+4]
16224add %l6, %l3, %l6
16225ld [%l6+4], %l7
16226st %l7, [%l6+4]
16227add %l6, %l3, %l6
16228ld [%l6+4], %l7
16229st %l7, [%l6+4]
16230add %l6, %l3, %l6
16231ld [%l6+4], %l7
16232st %l7, [%l6+4]
16233add %l6, %l3, %l6
16234ld [%l6+4], %l7
16235st %l7, [%l6+4]
16236add %l6, %l3, %l6
16237ld [%l6+4], %l7
16238st %l7, [%l6+4]
16239add %l6, %l3, %l6
16240ld [%l6+4], %l7
16241st %l7, [%l6+4]
16242
16243P1045: !_CASX [4] (maybe <- 0x800011) (Int)
16244ldx [%i1], %o3
16245! move %o3(upper) -> %o3(upper)
16246! move %o3(lower) -> %o3(lower)
16247mov %o3, %o5
16248sllx %l4, 32, %o4
16249add %l4, 1, %l4
16250or %l4, %o4, %o4
16251casx [%i1], %o5, %o4
16252! move %o4(upper) -> %o4(upper)
16253! move %o4(lower) -> %o4(lower)
16254!---- flushing int results buffer----
16255mov %o0, %l5
16256mov %o1, %l5
16257mov %o2, %l5
16258mov %o3, %l5
16259mov %o4, %l5
16260add %l4, 1, %l4
16261
16262P1046: !_CASX [6] (maybe <- 0x800013) (Int) (LE)
16263sllx %l4, 32, %l3
16264add %l4, 1, %l4
16265or %l4, %l3, %l3
16266! Change double-word-level endianess (big endian <-> little endian)
16267sethi %hi(0xff00ff00), %o5
16268or %o5, %lo(0xff00ff00), %o5
16269sllx %o5, 32, %l6
16270or %o5, %l6, %o5
16271and %l3, %o5, %l6
16272srlx %l6, 8, %l6
16273sllx %l3, 8, %l3
16274and %l3, %o5, %l3
16275or %l3, %l6, %l3
16276sethi %hi(0xffff0000), %o5
16277srlx %l3, 16, %l6
16278andn %l6, %o5, %l6
16279andn %l3, %o5, %l3
16280sllx %l3, 16, %l3
16281or %l3, %l6, %l3
16282srlx %l3, 32, %l6
16283sllx %l3, 32, %l3
16284or %l3, %l6, %l6
16285wr %g0, 0x88, %asi
16286sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
16287sub %i0, %i2, %i2
16288ldxa [%i2] %asi, %l7
16289! move %l7(lower) -> %o0(upper)
16290sllx %l7, 32, %o0
16291! move %l7(upper) -> %o0(lower)
16292srlx %l7, 32, %o5
16293or %o5, %o0, %o0
16294mov %l7, %o5
16295mov %l6, %l7
16296casxa [%i2] %asi, %o5, %l7
16297! move %l7(lower) -> %o1(upper)
16298sllx %l7, 32, %o1
16299! move %l7(upper) -> %o1(lower)
16300srlx %l7, 32, %o5
16301or %o5, %o1, %o1
16302add %l4, 1, %l4
16303
16304P1047: !_ST_BINIT [11] (maybe <- 0x800015) (Int) (LE)
16305wr %g0, 0xea, %asi
16306sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
16307add %i0, %i3, %i3
16308! Change single-word-level endianess (big endian <-> little endian)
16309sethi %hi(0xff00ff00), %l3
16310or %l3, %lo(0xff00ff00), %l3
16311and %l4, %l3, %l6
16312srl %l6, 8, %l6
16313sll %l4, 8, %o5
16314and %o5, %l3, %o5
16315or %o5, %l6, %o5
16316srl %o5, 16, %l6
16317sll %o5, 16, %o5
16318srl %o5, 0, %o5
16319or %o5, %l6, %o5
16320stwa %o5, [%i3 + 12] %asi
16321add %l4, 1, %l4
16322
16323P1048: !_MEMBAR (Int) (LE)
16324membar #StoreLoad
16325
16326P1049: !_LDD [9] (Int)
16327ldd [%i3 + 0], %l6
16328! move %l6(lower) -> %o2(upper)
16329sllx %l6, 32, %o2
16330! move %l7(lower) -> %o2(lower)
16331or %l7, %o2, %o2
16332
16333P1050: !_MEMBAR (FP) (Branch target of P1234)
16334ba P1051
16335nop
16336
16337TARGET1234:
16338ba RET1234
16339nop
16340
16341
16342P1051: !_BSTC [6] (maybe <- 0x4000000e) (FP)
16343wr %g0, 0xe0, %asi
16344! preparing store val #0, next val will be in f32
16345fmovs %f16, %f20
16346fadds %f16, %f17, %f16
16347! preparing store val #1, next val will be in f33
16348fmovs %f16, %f21
16349fadds %f16, %f17, %f16
16350! preparing store val #2, next val will be in f35
16351fmovd %f20, %f32
16352fmovs %f16, %f21
16353fadds %f16, %f17, %f16
16354fmovd %f20, %f34
16355membar #Sync
16356stda %f32, [%i2 + 0 ] %asi
16357
16358P1052: !_MEMBAR (FP)
16359membar #StoreLoad
16360
16361P1053: !_PREFETCH [19] (Int)
16362sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
16363add %i0, %i2, %i2
16364prefetch [%i2 + 4], 3
16365
16366P1054: !_CAS [7] (maybe <- 0x800016) (Int)
16367sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
16368sub %i0, %i3, %i3
16369add %i3, 4, %l3
16370lduw [%l3], %o3
16371mov %o3, %o5
16372! move %o5(lower) -> %o3(upper)
16373sllx %o5, 32, %o3
16374mov %l4, %l7
16375cas [%l3], %o5, %l7
16376! move %l7(lower) -> %o3(lower)
16377srl %l7, 0, %o5
16378or %o5, %o3, %o3
16379add %l4, 1, %l4
16380
16381P1055: !_LDD [12] (Int)
16382sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
16383add %i0, %i2, %i2
16384ldd [%i2 + 0], %l6
16385! move %l6(lower) -> %o4(upper)
16386sllx %l6, 32, %o4
16387! move %l7(lower) -> %o4(lower)
16388or %l7, %o4, %o4
16389!---- flushing int results buffer----
16390mov %o0, %l5
16391mov %o1, %l5
16392mov %o2, %l5
16393mov %o3, %l5
16394mov %o4, %l5
16395
16396P1056: !_DWST [6] (maybe <- 0x40000011) (FP)
16397! preparing store val #0, next val will be in f20
16398fmovs %f16, %f20
16399fadds %f16, %f17, %f16
16400! preparing store val #1, next val will be in f21
16401fmovs %f16, %f21
16402fadds %f16, %f17, %f16
16403std %f20, [%i3 + 0]
16404
16405P1057: !_PREFETCH [8] (Int)
16406prefetch [%i3 + 12], 4
16407
16408P1058: !_CASX [20] (maybe <- 0x800017) (Int)
16409sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
16410add %i0, %i3, %i3
16411add %i3, 8, %l3
16412ldx [%l3], %o0
16413! move %o0(upper) -> %o0(upper)
16414! move %o0(lower) -> %o0(lower)
16415mov %o0, %o5
16416mov %l4, %o1
16417casx [%l3], %o5, %o1
16418! move %o1(upper) -> %o1(upper)
16419! move %o1(lower) -> %o1(lower)
16420add %l4, 1, %l4
16421
16422P1059: !_PREFETCH [3] (Int)
16423prefetch [%i1 + 0], 2
16424
16425P1060: !_DWST [2] (maybe <- 0x800018) (Int)
16426mov %l4, %o5
16427stx %o5, [%i0 + 8]
16428add %l4, 1, %l4
16429
16430P1061: !_SWAP [19] (maybe <- 0x800019) (Int)
16431mov %l4, %o2
16432swap [%i3 + 4], %o2
16433! move %o2(lower) -> %o2(upper)
16434sllx %o2, 32, %o2
16435add %l4, 1, %l4
16436
16437P1062: !_DWST_BINIT [18] (maybe <- 0x80001a) (Int)
16438wr %g0, 0xe2, %asi
16439sllx %l4, 32, %l6
16440add %l4, 1, %l4
16441or %l6, %l4, %l6
16442stxa %l6, [%i3 + 0] %asi
16443add %l4, 1, %l4
16444
16445P1063: !_MEMBAR (Int)
16446membar #StoreLoad
16447
16448P1064: !_ST_BINIT [18] (maybe <- 0x80001c) (Int)
16449wr %g0, 0xe2, %asi
16450stwa %l4, [%i3 + 0] %asi
16451add %l4, 1, %l4
16452
16453P1065: !_MEMBAR (Int)
16454membar #StoreLoad
16455
16456P1066: !_BLD [10] (FP)
16457wr %g0, 0xf0, %asi
16458sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
16459add %i0, %i2, %i2
16460ldda [%i2 + 0] %asi, %f32
16461membar #Sync
16462! 3 addresses covered
16463fmovd %f32, %f6
16464fmovd %f34, %f18
16465fmovs %f19, %f8
16466
16467P1067: !_MEMBAR (FP)
16468
16469P1068: !_LD [17] (FP)
16470sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
16471sub %i0, %i3, %i3
16472ld [%i3 + 12], %f9
16473! 1 addresses covered
16474
16475P1069: !_ST_BINIT [6] (maybe <- 0x80001d) (Int) (Branch target of P1652)
16476wr %g0, 0xe2, %asi
16477sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
16478sub %i0, %i2, %i2
16479stwa %l4, [%i2 + 0] %asi
16480add %l4, 1, %l4
16481ba P1070
16482nop
16483
16484TARGET1652:
16485ba RET1652
16486nop
16487
16488
16489P1070: !_MEMBAR (Int)
16490membar #StoreLoad
16491
16492P1071: !_LD [22] (Int)
16493sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
16494sub %i0, %i3, %i3
16495lduw [%i3 + 4], %l3
16496! move %l3(lower) -> %o2(lower)
16497or %l3, %o2, %o2
16498
16499P1072: !_SWAP [7] (maybe <- 0x80001e) (Int) (LE)
16500wr %g0, 0x88, %asi
16501mov %l4, %o3
16502! Change single-word-level endianess (big endian <-> little endian)
16503sethi %hi(0xff00ff00), %l6
16504or %l6, %lo(0xff00ff00), %l6
16505and %o3, %l6, %l7
16506srl %l7, 8, %l7
16507sll %o3, 8, %o3
16508and %o3, %l6, %o3
16509or %o3, %l7, %o3
16510srl %o3, 16, %l7
16511sll %o3, 16, %o3
16512srl %o3, 0, %o3
16513or %o3, %l7, %o3
16514swapa [%i2 + 4] %asi, %o3
16515! move %o3(lower) -> %o3(upper)
16516sllx %o3, 32, %o3
16517add %l4, 1, %l4
16518
16519P1073: !_ST [17] (maybe <- 0x80001f) (Int) (Branch target of P1311)
16520sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
16521sub %i0, %i2, %i2
16522stw %l4, [%i2 + 12 ]
16523add %l4, 1, %l4
16524ba P1074
16525nop
16526
16527TARGET1311:
16528ba RET1311
16529nop
16530
16531
16532P1074: !_ST [20] (maybe <- 0x800020) (Int) (LE)
16533wr %g0, 0x88, %asi
16534sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
16535add %i0, %i3, %i3
16536! Change single-word-level endianess (big endian <-> little endian)
16537sethi %hi(0xff00ff00), %l3
16538or %l3, %lo(0xff00ff00), %l3
16539and %l4, %l3, %l6
16540srl %l6, 8, %l6
16541sll %l4, 8, %o5
16542and %o5, %l3, %o5
16543or %o5, %l6, %o5
16544srl %o5, 16, %l6
16545sll %o5, 16, %o5
16546srl %o5, 0, %o5
16547or %o5, %l6, %o5
16548stwa %o5, [%i3 + 12] %asi
16549add %l4, 1, %l4
16550
16551P1075: !_LDD [8] (Int)
16552sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
16553sub %i0, %i2, %i2
16554ldd [%i2 + 8], %l6
16555! move %l7(lower) -> %o3(lower)
16556or %l7, %o3, %o3
16557
16558P1076: !_MEMBAR (FP)
16559
16560P1077: !_BSTC [10] (maybe <- 0x40000013) (FP)
16561wr %g0, 0xe0, %asi
16562sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
16563add %i0, %i3, %i3
16564! preparing store val #0, next val will be in f32
16565fmovs %f16, %f20
16566fadds %f16, %f17, %f16
16567! preparing store val #1, next val will be in f33
16568fmovs %f16, %f21
16569fadds %f16, %f17, %f16
16570! preparing store val #2, next val will be in f35
16571fmovd %f20, %f32
16572fmovs %f16, %f21
16573fadds %f16, %f17, %f16
16574fmovd %f20, %f34
16575membar #Sync
16576stda %f32, [%i3 + 0 ] %asi
16577
16578P1078: !_MEMBAR (FP)
16579membar #StoreLoad
16580
16581P1079: !_DWST [3] (maybe <- 0x800021) (Int)
16582sllx %l4, 32, %o5
16583add %l4, 1, %l4
16584or %o5, %l4, %o5
16585stx %o5, [%i1 + 0]
16586add %l4, 1, %l4
16587
16588P1080: !_CAS [16] (maybe <- 0x800023) (Int)
16589sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
16590sub %i0, %i2, %i2
16591add %i2, 4, %o5
16592lduw [%o5], %o4
16593mov %o4, %l7
16594! move %l7(lower) -> %o4(upper)
16595sllx %l7, 32, %o4
16596mov %l4, %l6
16597cas [%o5], %l7, %l6
16598! move %l6(lower) -> %o4(lower)
16599srl %l6, 0, %l7
16600or %l7, %o4, %o4
16601!---- flushing int results buffer----
16602mov %o0, %l5
16603mov %o1, %l5
16604mov %o2, %l5
16605mov %o3, %l5
16606mov %o4, %l5
16607add %l4, 1, %l4
16608
16609P1081: !_LD [22] (Int)
16610sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
16611sub %i0, %i3, %i3
16612lduw [%i3 + 4], %o0
16613! move %o0(lower) -> %o0(upper)
16614sllx %o0, 32, %o0
16615
16616P1082: !_CASX [17] (maybe <- 0x800024) (Int)
16617add %i2, 8, %l6
16618ldx [%l6], %o5
16619! move %o5(upper) -> %o0(lower)
16620srlx %o5, 32, %l3
16621or %l3, %o0, %o0
16622! move %o5(lower) -> %o1(upper)
16623sllx %o5, 32, %o1
16624mov %o5, %l3
16625mov %l4, %o5
16626casx [%l6], %l3, %o5
16627! move %o5(upper) -> %o1(lower)
16628srlx %o5, 32, %l3
16629or %l3, %o1, %o1
16630! move %o5(lower) -> %o2(upper)
16631sllx %o5, 32, %o2
16632add %l4, 1, %l4
16633
16634P1083: !_DWST_BINIT [7] (maybe <- 0x800025) (Int)
16635wr %g0, 0xe2, %asi
16636sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
16637sub %i0, %i2, %i2
16638sllx %l4, 32, %l3
16639add %l4, 1, %l4
16640or %l3, %l4, %l3
16641stxa %l3, [%i2 + 0] %asi
16642add %l4, 1, %l4
16643
16644P1084: !_MEMBAR (Int)
16645membar #StoreLoad
16646
16647P1085: !_CAS [9] (maybe <- 0x800027) (Int)
16648sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
16649add %i0, %i3, %i3
16650lduw [%i3], %l7
16651mov %l7, %o5
16652! move %o5(lower) -> %o2(lower)
16653or %o5, %o2, %o2
16654mov %l4, %o3
16655cas [%i3], %o5, %o3
16656! move %o3(lower) -> %o3(upper)
16657sllx %o3, 32, %o3
16658add %l4, 1, %l4
16659
16660P1086: !_SWAP [19] (maybe <- 0x800028) (Int)
16661sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
16662add %i0, %i2, %i2
16663mov %l4, %l6
16664swap [%i2 + 4], %l6
16665! move %l6(lower) -> %o3(lower)
16666srl %l6, 0, %o5
16667or %o5, %o3, %o3
16668add %l4, 1, %l4
16669
16670P1087: !_MEMBAR (FP)
16671membar #StoreLoad
16672
16673P1088: !_BLD [23] (FP)
16674wr %g0, 0xf0, %asi
16675sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
16676sub %i0, %i3, %i3
16677ldda [%i3 + 0] %asi, %f32
16678membar #Sync
16679! 3 addresses covered
16680fmovd %f32, %f10
16681fmovd %f34, %f18
16682fmovs %f19, %f12
16683
16684P1089: !_MEMBAR (FP) (Branch target of P1908)
16685ba P1090
16686nop
16687
16688TARGET1908:
16689ba RET1908
16690nop
16691
16692
16693P1090: !_DWLD [17] (Int)
16694sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
16695sub %i0, %i2, %i2
16696ldx [%i2 + 8], %o4
16697! move %o4(lower) -> %o4(upper)
16698sllx %o4, 32, %o4
16699
16700P1091: !_LD [19] (Int)
16701sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
16702add %i0, %i3, %i3
16703lduw [%i3 + 4], %l6
16704! move %l6(lower) -> %o4(lower)
16705or %l6, %o4, %o4
16706!---- flushing int results buffer----
16707mov %o0, %l5
16708mov %o1, %l5
16709mov %o2, %l5
16710mov %o3, %l5
16711mov %o4, %l5
16712
16713P1092: !_MEMBAR (FP)
16714membar #StoreLoad
16715
16716P1093: !_BLD [13] (FP)
16717wr %g0, 0xf0, %asi
16718sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
16719add %i0, %i2, %i2
16720ldda [%i2 + 0] %asi, %f32
16721membar #Sync
16722! 3 addresses covered
16723fmovd %f32, %f18
16724fmovs %f18, %f13
16725fmovs %f19, %f14
16726fmovd %f34, %f18
16727fmovs %f19, %f15
16728!---- flushing fp results buffer to %f30 ----
16729fmovd %f0, %f30
16730fmovd %f2, %f30
16731fmovd %f4, %f30
16732fmovd %f6, %f30
16733fmovd %f8, %f30
16734fmovd %f10, %f30
16735fmovd %f12, %f30
16736fmovd %f14, %f30
16737!--
16738
16739P1094: !_MEMBAR (FP)
16740
16741P1095: !_DWLD [19] (Int)
16742ldx [%i3 + 0], %o0
16743! move %o0(upper) -> %o0(upper)
16744! move %o0(lower) -> %o0(lower)
16745
16746P1096: !_MEMBAR (FP) (CBR)
16747
16748! cbranch
16749andcc %l0, 1, %g0
16750be,pn %xcc, TARGET1096
16751nop
16752RET1096:
16753
16754! lfsr step begin
16755srlx %l0, 1, %l3
16756xnor %l3, %l0, %l3
16757sllx %l3, 63, %l3
16758or %l3, %l0, %l0
16759srlx %l0, 1, %l0
16760
16761
16762P1097: !_BST [3] (maybe <- 0x40000016) (FP)
16763wr %g0, 0xf0, %asi
16764! preparing store val #0, next val will be in f32
16765fmovs %f16, %f20
16766fadds %f16, %f17, %f16
16767! preparing store val #1, next val will be in f33
16768fmovs %f16, %f21
16769fadds %f16, %f17, %f16
16770! preparing store val #2, next val will be in f35
16771fmovd %f20, %f32
16772fmovs %f16, %f21
16773fadds %f16, %f17, %f16
16774fmovd %f20, %f34
16775membar #Sync
16776stda %f32, [%i1 + 0 ] %asi
16777
16778P1098: !_MEMBAR (FP)
16779membar #StoreLoad
16780
16781P1099: !_CASX [23] (maybe <- 0x800029) (Int)
16782sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
16783sub %i0, %i3, %i3
16784add %i3, 8, %l6
16785ldx [%l6], %o1
16786! move %o1(upper) -> %o1(upper)
16787! move %o1(lower) -> %o1(lower)
16788mov %o1, %l3
16789mov %l4, %o2
16790casx [%l6], %l3, %o2
16791! move %o2(upper) -> %o2(upper)
16792! move %o2(lower) -> %o2(lower)
16793add %l4, 1, %l4
16794
16795P1100: !_LDD [7] (Int)
16796sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
16797sub %i0, %i2, %i2
16798ldd [%i2 + 0], %l6
16799! move %l6(lower) -> %o3(upper)
16800sllx %l6, 32, %o3
16801! move %l7(lower) -> %o3(lower)
16802or %l7, %o3, %o3
16803
16804P1101: !_PREFETCH [9] (Int)
16805sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
16806add %i0, %i3, %i3
16807prefetch [%i3 + 0], 23
16808
16809P1102: !_LDD [21] (Int)
16810sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
16811sub %i0, %i2, %i2
16812ldd [%i2 + 0], %l6
16813! move %l6(lower) -> %o4(upper)
16814sllx %l6, 32, %o4
16815! move %l7(lower) -> %o4(lower)
16816or %l7, %o4, %o4
16817!---- flushing int results buffer----
16818mov %o0, %l5
16819mov %o1, %l5
16820mov %o2, %l5
16821mov %o3, %l5
16822mov %o4, %l5
16823
16824P1103: !_CASX [6] (maybe <- 0x80002a) (Int)
16825sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
16826sub %i0, %i3, %i3
16827ldx [%i3], %o0
16828! move %o0(upper) -> %o0(upper)
16829! move %o0(lower) -> %o0(lower)
16830mov %o0, %l3
16831sllx %l4, 32, %o1
16832add %l4, 1, %l4
16833or %l4, %o1, %o1
16834casx [%i3], %l3, %o1
16835! move %o1(upper) -> %o1(upper)
16836! move %o1(lower) -> %o1(lower)
16837add %l4, 1, %l4
16838
16839P1104: !_DWST_BINIT [8] (maybe <- 0x80002c) (Int)
16840wr %g0, 0xe2, %asi
16841mov %l4, %l3
16842stxa %l3, [%i3 + 8] %asi
16843add %l4, 1, %l4
16844
16845P1105: !_MEMBAR (Int)
16846membar #StoreLoad
16847
16848P1106: !_DWLD [12] (Int)
16849sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
16850add %i0, %i2, %i2
16851ldx [%i2 + 0], %o2
16852! move %o2(upper) -> %o2(upper)
16853! move %o2(lower) -> %o2(lower)
16854
16855P1107: !_CAS [17] (maybe <- 0x80002d) (Int)
16856sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
16857sub %i0, %i3, %i3
16858add %i3, 12, %l7
16859lduw [%l7], %o3
16860mov %o3, %l6
16861! move %l6(lower) -> %o3(upper)
16862sllx %l6, 32, %o3
16863mov %l4, %l3
16864cas [%l7], %l6, %l3
16865! move %l3(lower) -> %o3(lower)
16866srl %l3, 0, %l6
16867or %l6, %o3, %o3
16868add %l4, 1, %l4
16869
16870P1108: !_DWST_BINIT [0] (maybe <- 0x80002e) (Int)
16871wr %g0, 0xe2, %asi
16872sllx %l4, 32, %l6
16873add %l4, 1, %l4
16874or %l6, %l4, %l6
16875stxa %l6, [%i0 + 0] %asi
16876add %l4, 1, %l4
16877
16878P1109: !_MEMBAR (Int)
16879membar #StoreLoad
16880
16881P1110: !_DWLD [9] (FP) (Branch target of P1800)
16882sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
16883add %i0, %i2, %i2
16884ldd [%i2 + 0], %f0
16885! 2 addresses covered
16886ba P1111
16887nop
16888
16889TARGET1800:
16890ba RET1800
16891nop
16892
16893
16894P1111: !_DWST_BINIT [12] (maybe <- 0x800030) (Int)
16895wr %g0, 0xe2, %asi
16896sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
16897add %i0, %i3, %i3
16898sllx %l4, 32, %l3
16899add %l4, 1, %l4
16900or %l3, %l4, %l3
16901stxa %l3, [%i3 + 0] %asi
16902add %l4, 1, %l4
16903
16904P1112: !_MEMBAR (Int)
16905
16906P1113: !_BST [18] (maybe <- 0x40000019) (FP)
16907wr %g0, 0xf0, %asi
16908sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
16909add %i0, %i2, %i2
16910! preparing store val #0, next val will be in f32
16911fmovs %f16, %f20
16912fadds %f16, %f17, %f16
16913! preparing store val #1, next val will be in f33
16914fmovs %f16, %f21
16915fadds %f16, %f17, %f16
16916! preparing store val #2, next val will be in f35
16917fmovd %f20, %f32
16918fmovs %f16, %f21
16919fadds %f16, %f17, %f16
16920fmovd %f20, %f34
16921membar #Sync
16922stda %f32, [%i2 + 0 ] %asi
16923
16924P1114: !_MEMBAR (FP)
16925membar #StoreLoad
16926
16927P1115: !_DWLD [17] (Int)
16928sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
16929sub %i0, %i3, %i3
16930ldx [%i3 + 8], %o4
16931! move %o4(lower) -> %o4(upper)
16932sllx %o4, 32, %o4
16933
16934P1116: !_CAS [15] (maybe <- 0x800032) (Int)
16935lduw [%i3], %o5
16936mov %o5, %l3
16937! move %l3(lower) -> %o4(lower)
16938or %l3, %o4, %o4
16939!---- flushing int results buffer----
16940mov %o0, %l5
16941mov %o1, %l5
16942mov %o2, %l5
16943mov %o3, %l5
16944mov %o4, %l5
16945mov %l4, %o0
16946cas [%i3], %l3, %o0
16947! move %o0(lower) -> %o0(upper)
16948sllx %o0, 32, %o0
16949add %l4, 1, %l4
16950
16951P1117: !_CASX [15] (maybe <- 0x800033) (Int)
16952ldx [%i3], %o5
16953! move %o5(upper) -> %o0(lower)
16954srlx %o5, 32, %l3
16955or %l3, %o0, %o0
16956! move %o5(lower) -> %o1(upper)
16957sllx %o5, 32, %o1
16958mov %o5, %l3
16959sllx %l4, 32, %o5
16960add %l4, 1, %l4
16961or %l4, %o5, %o5
16962casx [%i3], %l3, %o5
16963! move %o5(upper) -> %o1(lower)
16964srlx %o5, 32, %l3
16965or %l3, %o1, %o1
16966! move %o5(lower) -> %o2(upper)
16967sllx %o5, 32, %o2
16968add %l4, 1, %l4
16969
16970P1118: !_LD [12] (Int)
16971sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
16972add %i0, %i2, %i2
16973lduw [%i2 + 0], %l6
16974! move %l6(lower) -> %o2(lower)
16975or %l6, %o2, %o2
16976
16977P1119: !_SWAP [4] (maybe <- 0x800035) (Int) (LE)
16978wr %g0, 0x88, %asi
16979mov %l4, %o3
16980! Change single-word-level endianess (big endian <-> little endian)
16981sethi %hi(0xff00ff00), %l7
16982or %l7, %lo(0xff00ff00), %l7
16983and %o3, %l7, %o5
16984srl %o5, 8, %o5
16985sll %o3, 8, %o3
16986and %o3, %l7, %o3
16987or %o3, %o5, %o3
16988srl %o3, 16, %o5
16989sll %o3, 16, %o3
16990srl %o3, 0, %o3
16991or %o3, %o5, %o3
16992swapa [%i1 + 4] %asi, %o3
16993! move %o3(lower) -> %o3(upper)
16994sllx %o3, 32, %o3
16995add %l4, 1, %l4
16996
16997P1120: !_ST [10] (maybe <- 0x800036) (Int)
16998sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
16999add %i0, %i3, %i3
17000stw %l4, [%i3 + 4 ]
17001add %l4, 1, %l4
17002
17003P1121: !_LD [0] (Int)
17004lduw [%i0 + 0], %l6
17005! move %l6(lower) -> %o3(lower)
17006or %l6, %o3, %o3
17007
17008P1122: !_LDD [10] (Int)
17009ldd [%i3 + 0], %l6
17010! move %l6(lower) -> %o4(upper)
17011sllx %l6, 32, %o4
17012! move %l7(lower) -> %o4(lower)
17013or %l7, %o4, %o4
17014!---- flushing int results buffer----
17015mov %o0, %l5
17016mov %o1, %l5
17017mov %o2, %l5
17018mov %o3, %l5
17019mov %o4, %l5
17020
17021P1123: !_MEMBAR (FP)
17022
17023P1124: !_BST [7] (maybe <- 0x4000001c) (FP)
17024wr %g0, 0xf0, %asi
17025sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
17026sub %i0, %i2, %i2
17027! preparing store val #0, next val will be in f32
17028fmovs %f16, %f20
17029fadds %f16, %f17, %f16
17030! preparing store val #1, next val will be in f33
17031fmovs %f16, %f21
17032fadds %f16, %f17, %f16
17033! preparing store val #2, next val will be in f35
17034fmovd %f20, %f32
17035fmovs %f16, %f21
17036fadds %f16, %f17, %f16
17037fmovd %f20, %f34
17038membar #Sync
17039stda %f32, [%i2 + 0 ] %asi
17040
17041P1125: !_MEMBAR (FP)
17042membar #StoreLoad
17043
17044P1126: !_DWLD [15] (Int)
17045sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
17046sub %i0, %i3, %i3
17047ldx [%i3 + 0], %o0
17048! move %o0(upper) -> %o0(upper)
17049! move %o0(lower) -> %o0(lower)
17050
17051P1127: !_LDD [9] (Int)
17052sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
17053add %i0, %i2, %i2
17054ldd [%i2 + 0], %l6
17055! move %l6(lower) -> %o1(upper)
17056sllx %l6, 32, %o1
17057! move %l7(lower) -> %o1(lower)
17058or %l7, %o1, %o1
17059
17060P1128: !_MEMBAR (FP)
17061membar #StoreLoad
17062
17063P1129: !_BLD [19] (FP)
17064wr %g0, 0xf0, %asi
17065sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
17066sub %i0, %i3, %i3
17067ldda [%i3 + 0] %asi, %f32
17068membar #Sync
17069! 3 addresses covered
17070fmovd %f32, %f2
17071fmovd %f34, %f18
17072fmovs %f19, %f4
17073
17074P1130: !_MEMBAR (FP)
17075
17076P1131: !_BLD [9] (FP)
17077wr %g0, 0xf0, %asi
17078ldda [%i2 + 0] %asi, %f32
17079membar #Sync
17080! 3 addresses covered
17081fmovd %f32, %f18
17082fmovs %f18, %f5
17083fmovs %f19, %f6
17084fmovd %f34, %f18
17085fmovs %f19, %f7
17086
17087P1132: !_MEMBAR (FP)
17088
17089P1133: !_BLD [7] (FP)
17090wr %g0, 0xf0, %asi
17091sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
17092sub %i0, %i2, %i2
17093ldda [%i2 + 0] %asi, %f32
17094membar #Sync
17095! 3 addresses covered
17096fmovd %f32, %f8
17097fmovd %f34, %f18
17098fmovs %f19, %f10
17099
17100P1134: !_MEMBAR (FP)
17101
17102P1135: !_SWAP [11] (maybe <- 0x800037) (Int)
17103sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
17104add %i0, %i3, %i3
17105mov %l4, %o2
17106swap [%i3 + 12], %o2
17107! move %o2(lower) -> %o2(upper)
17108sllx %o2, 32, %o2
17109add %l4, 1, %l4
17110
17111P1136: !_CASX [10] (maybe <- 0x800038) (Int)
17112ldx [%i3], %o5
17113! move %o5(upper) -> %o2(lower)
17114srlx %o5, 32, %l3
17115or %l3, %o2, %o2
17116! move %o5(lower) -> %o3(upper)
17117sllx %o5, 32, %o3
17118mov %o5, %l3
17119sllx %l4, 32, %o5
17120add %l4, 1, %l4
17121or %l4, %o5, %o5
17122casx [%i3], %l3, %o5
17123! move %o5(upper) -> %o3(lower)
17124srlx %o5, 32, %l3
17125or %l3, %o3, %o3
17126! move %o5(lower) -> %o4(upper)
17127sllx %o5, 32, %o4
17128add %l4, 1, %l4
17129
17130P1137: !_DWST_BINIT [15] (maybe <- 0x80003a) (Int)
17131wr %g0, 0xe2, %asi
17132sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
17133sub %i0, %i2, %i2
17134sllx %l4, 32, %l3
17135add %l4, 1, %l4
17136or %l3, %l4, %l3
17137stxa %l3, [%i2 + 0] %asi
17138add %l4, 1, %l4
17139
17140P1138: !_MEMBAR (Int)
17141membar #StoreLoad
17142
17143P1139: !_DWLD [6] (Int)
17144sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
17145sub %i0, %i3, %i3
17146ldx [%i3 + 0], %l3
17147! move %l3(upper) -> %o4(lower)
17148srlx %l3, 32, %o5
17149or %o5, %o4, %o4
17150!---- flushing int results buffer----
17151mov %o0, %l5
17152mov %o1, %l5
17153mov %o2, %l5
17154mov %o3, %l5
17155mov %o4, %l5
17156! move %l3(lower) -> %o0(upper)
17157sllx %l3, 32, %o0
17158
17159P1140: !_LD [16] (Int)
17160lduw [%i2 + 4], %l7
17161! move %l7(lower) -> %o0(lower)
17162or %l7, %o0, %o0
17163
17164P1141: !_DWST_BINIT [13] (maybe <- 0x80003c) (Int)
17165wr %g0, 0xe2, %asi
17166sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
17167add %i0, %i2, %i2
17168sllx %l4, 32, %o5
17169add %l4, 1, %l4
17170or %o5, %l4, %o5
17171stxa %o5, [%i2 + 0] %asi
17172add %l4, 1, %l4
17173
17174P1142: !_MEMBAR (Int)
17175membar #StoreLoad
17176
17177P1143: !_DWST [4] (maybe <- 0x80003e) (Int)
17178sllx %l4, 32, %l7
17179add %l4, 1, %l4
17180or %l7, %l4, %l7
17181stx %l7, [%i1 + 0]
17182add %l4, 1, %l4
17183
17184P1144: !_CASX [10] (maybe <- 0x800040) (Int) (Branch target of P1265)
17185sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
17186add %i0, %i3, %i3
17187ldx [%i3], %o1
17188! move %o1(upper) -> %o1(upper)
17189! move %o1(lower) -> %o1(lower)
17190mov %o1, %l6
17191sllx %l4, 32, %o2
17192add %l4, 1, %l4
17193or %l4, %o2, %o2
17194casx [%i3], %l6, %o2
17195! move %o2(upper) -> %o2(upper)
17196! move %o2(lower) -> %o2(lower)
17197add %l4, 1, %l4
17198ba P1145
17199nop
17200
17201TARGET1265:
17202ba RET1265
17203nop
17204
17205
17206P1145: !_DWLD [15] (Int)
17207sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
17208sub %i0, %i2, %i2
17209ldx [%i2 + 0], %o3
17210! move %o3(upper) -> %o3(upper)
17211! move %o3(lower) -> %o3(lower)
17212
17213P1146: !_LD [4] (Int)
17214lduw [%i1 + 4], %o4
17215! move %o4(lower) -> %o4(upper)
17216sllx %o4, 32, %o4
17217
17218P1147: !_DWST [1] (maybe <- 0x4000001f) (FP)
17219! preparing store val #0, next val will be in f20
17220fmovs %f16, %f20
17221fadds %f16, %f17, %f16
17222! preparing store val #1, next val will be in f21
17223fmovs %f16, %f21
17224fadds %f16, %f17, %f16
17225std %f20, [%i0 + 0]
17226
17227P1148: !_LDD [7] (Int)
17228sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
17229sub %i0, %i3, %i3
17230ldd [%i3 + 0], %l6
17231! move %l6(lower) -> %o4(lower)
17232or %l6, %o4, %o4
17233!---- flushing int results buffer----
17234mov %o0, %l5
17235mov %o1, %l5
17236mov %o2, %l5
17237mov %o3, %l5
17238mov %o4, %l5
17239! move %l7(lower) -> %o0(upper)
17240sllx %l7, 32, %o0
17241
17242P1149: !_CASX [13] (maybe <- 0x800042) (Int)
17243sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
17244add %i0, %i2, %i2
17245ldx [%i2], %o5
17246! move %o5(upper) -> %o0(lower)
17247srlx %o5, 32, %l3
17248or %l3, %o0, %o0
17249! move %o5(lower) -> %o1(upper)
17250sllx %o5, 32, %o1
17251mov %o5, %l3
17252sllx %l4, 32, %o5
17253add %l4, 1, %l4
17254or %l4, %o5, %o5
17255casx [%i2], %l3, %o5
17256! move %o5(upper) -> %o1(lower)
17257srlx %o5, 32, %l3
17258or %l3, %o1, %o1
17259! move %o5(lower) -> %o2(upper)
17260sllx %o5, 32, %o2
17261add %l4, 1, %l4
17262
17263P1150: !_LDD [12] (Int)
17264ldd [%i2 + 0], %l6
17265! move %l6(lower) -> %o2(lower)
17266or %l6, %o2, %o2
17267! move %l7(lower) -> %o3(upper)
17268sllx %l7, 32, %o3
17269
17270P1151: !_MEMBAR (FP)
17271
17272P1152: !_BSTC [9] (maybe <- 0x40000021) (FP)
17273wr %g0, 0xe0, %asi
17274sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
17275add %i0, %i3, %i3
17276! preparing store val #0, next val will be in f32
17277fmovs %f16, %f20
17278fadds %f16, %f17, %f16
17279! preparing store val #1, next val will be in f33
17280fmovs %f16, %f21
17281fadds %f16, %f17, %f16
17282! preparing store val #2, next val will be in f35
17283fmovd %f20, %f32
17284fmovs %f16, %f21
17285fadds %f16, %f17, %f16
17286fmovd %f20, %f34
17287membar #Sync
17288stda %f32, [%i3 + 0 ] %asi
17289
17290P1153: !_MEMBAR (FP)
17291
17292P1154: !_BSTC [11] (maybe <- 0x40000024) (FP)
17293wr %g0, 0xe0, %asi
17294! preparing store val #0, next val will be in f32
17295fmovs %f16, %f20
17296fadds %f16, %f17, %f16
17297! preparing store val #1, next val will be in f33
17298fmovs %f16, %f21
17299fadds %f16, %f17, %f16
17300! preparing store val #2, next val will be in f35
17301fmovd %f20, %f32
17302fmovs %f16, %f21
17303fadds %f16, %f17, %f16
17304fmovd %f20, %f34
17305membar #Sync
17306stda %f32, [%i3 + 0 ] %asi
17307
17308P1155: !_MEMBAR (FP)
17309
17310P1156: !_BST [18] (maybe <- 0x40000027) (FP)
17311wr %g0, 0xf0, %asi
17312sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
17313sub %i0, %i2, %i2
17314! preparing store val #0, next val will be in f32
17315fmovs %f16, %f20
17316fadds %f16, %f17, %f16
17317! preparing store val #1, next val will be in f33
17318fmovs %f16, %f21
17319fadds %f16, %f17, %f16
17320! preparing store val #2, next val will be in f35
17321fmovd %f20, %f32
17322fmovs %f16, %f21
17323fadds %f16, %f17, %f16
17324fmovd %f20, %f34
17325membar #Sync
17326stda %f32, [%i2 + 0 ] %asi
17327
17328P1157: !_MEMBAR (FP) (CBR)
17329membar #StoreLoad
17330
17331! cbranch
17332andcc %l0, 1, %g0
17333be,pt %xcc, TARGET1157
17334nop
17335RET1157:
17336
17337! lfsr step begin
17338srlx %l0, 1, %l6
17339xnor %l6, %l0, %l6
17340sllx %l6, 63, %l6
17341or %l6, %l0, %l0
17342srlx %l0, 1, %l0
17343
17344
17345P1158: !_LDD [7] (Int)
17346sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
17347sub %i0, %i3, %i3
17348ldd [%i3 + 0], %l6
17349! move %l6(lower) -> %o3(lower)
17350or %l6, %o3, %o3
17351! move %l7(lower) -> %o4(upper)
17352sllx %l7, 32, %o4
17353
17354P1159: !_MEMBAR (FP)
17355
17356P1160: !_BST [11] (maybe <- 0x4000002a) (FP)
17357wr %g0, 0xf0, %asi
17358sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
17359add %i0, %i2, %i2
17360! preparing store val #0, next val will be in f32
17361fmovs %f16, %f20
17362fadds %f16, %f17, %f16
17363! preparing store val #1, next val will be in f33
17364fmovs %f16, %f21
17365fadds %f16, %f17, %f16
17366! preparing store val #2, next val will be in f35
17367fmovd %f20, %f32
17368fmovs %f16, %f21
17369fadds %f16, %f17, %f16
17370fmovd %f20, %f34
17371membar #Sync
17372stda %f32, [%i2 + 0 ] %asi
17373
17374P1161: !_MEMBAR (FP)
17375
17376P1162: !_BST [14] (maybe <- 0x4000002d) (FP)
17377wr %g0, 0xf0, %asi
17378sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
17379add %i0, %i3, %i3
17380! preparing store val #0, next val will be in f32
17381fmovs %f16, %f20
17382fadds %f16, %f17, %f16
17383! preparing store val #1, next val will be in f33
17384fmovs %f16, %f21
17385fadds %f16, %f17, %f16
17386! preparing store val #2, next val will be in f35
17387fmovd %f20, %f32
17388fmovs %f16, %f21
17389fadds %f16, %f17, %f16
17390fmovd %f20, %f34
17391membar #Sync
17392stda %f32, [%i3 + 0 ] %asi
17393
17394P1163: !_MEMBAR (FP)
17395
17396P1164: !_BST [8] (maybe <- 0x40000030) (FP)
17397wr %g0, 0xf0, %asi
17398sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
17399sub %i0, %i2, %i2
17400! preparing store val #0, next val will be in f32
17401fmovs %f16, %f20
17402fadds %f16, %f17, %f16
17403! preparing store val #1, next val will be in f33
17404fmovs %f16, %f21
17405fadds %f16, %f17, %f16
17406! preparing store val #2, next val will be in f35
17407fmovd %f20, %f32
17408fmovs %f16, %f21
17409fadds %f16, %f17, %f16
17410fmovd %f20, %f34
17411membar #Sync
17412stda %f32, [%i2 + 0 ] %asi
17413
17414P1165: !_MEMBAR (FP) (CBR)
17415membar #StoreLoad
17416
17417! cbranch
17418andcc %l0, 1, %g0
17419be,pn %xcc, TARGET1165
17420nop
17421RET1165:
17422
17423! lfsr step begin
17424srlx %l0, 1, %l6
17425xnor %l6, %l0, %l6
17426sllx %l6, 63, %l6
17427or %l6, %l0, %l0
17428srlx %l0, 1, %l0
17429
17430
17431P1166: !_DWST_BINIT [18] (maybe <- 0x800044) (Int)
17432wr %g0, 0xe2, %asi
17433sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
17434sub %i0, %i3, %i3
17435sllx %l4, 32, %l7
17436add %l4, 1, %l4
17437or %l7, %l4, %l7
17438stxa %l7, [%i3 + 0] %asi
17439add %l4, 1, %l4
17440
17441P1167: !_MEMBAR (Int)
17442membar #StoreLoad
17443
17444P1168: !_DWLD [23] (FP)
17445sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
17446sub %i0, %i2, %i2
17447ldd [%i2 + 8], %f18
17448! 1 addresses covered
17449fmovs %f19, %f11
17450
17451P1169: !_CASX [15] (maybe <- 0x800046) (Int)
17452sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
17453sub %i0, %i3, %i3
17454ldx [%i3], %l3
17455! move %l3(upper) -> %o4(lower)
17456srlx %l3, 32, %l6
17457or %l6, %o4, %o4
17458!---- flushing int results buffer----
17459mov %o0, %l5
17460mov %o1, %l5
17461mov %o2, %l5
17462mov %o3, %l5
17463mov %o4, %l5
17464! move %l3(lower) -> %o0(upper)
17465sllx %l3, 32, %o0
17466mov %l3, %l6
17467sllx %l4, 32, %l3
17468add %l4, 1, %l4
17469or %l4, %l3, %l3
17470casx [%i3], %l6, %l3
17471! move %l3(upper) -> %o0(lower)
17472srlx %l3, 32, %l6
17473or %l6, %o0, %o0
17474! move %l3(lower) -> %o1(upper)
17475sllx %l3, 32, %o1
17476add %l4, 1, %l4
17477
17478P1170: !_DWST [8] (maybe <- 0x40000033) (FP)
17479sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
17480sub %i0, %i2, %i2
17481! preparing store val #0, next val will be in f21
17482fmovs %f16, %f21
17483fadds %f16, %f17, %f16
17484std %f20, [%i2 + 8]
17485
17486P1171: !_ST [2] (maybe <- 0x800048) (Int)
17487stw %l4, [%i0 + 12 ]
17488add %l4, 1, %l4
17489
17490P1172: !_MEMBAR (FP)
17491
17492P1173: !_BST [6] (maybe <- 0x40000034) (FP)
17493wr %g0, 0xf0, %asi
17494! preparing store val #0, next val will be in f32
17495fmovs %f16, %f20
17496fadds %f16, %f17, %f16
17497! preparing store val #1, next val will be in f33
17498fmovs %f16, %f21
17499fadds %f16, %f17, %f16
17500! preparing store val #2, next val will be in f35
17501fmovd %f20, %f32
17502fmovs %f16, %f21
17503fadds %f16, %f17, %f16
17504fmovd %f20, %f34
17505membar #Sync
17506stda %f32, [%i2 + 0 ] %asi
17507
17508P1174: !_MEMBAR (FP) (Branch target of P1278)
17509membar #StoreLoad
17510ba P1175
17511nop
17512
17513TARGET1278:
17514ba RET1278
17515nop
17516
17517
17518P1175: !_ST_BINIT [10] (maybe <- 0x800049) (Int)
17519wr %g0, 0xe2, %asi
17520sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
17521add %i0, %i3, %i3
17522stwa %l4, [%i3 + 4] %asi
17523add %l4, 1, %l4
17524
17525P1176: !_MEMBAR (Int)
17526membar #StoreLoad
17527
17528P1177: !_SWAP [17] (maybe <- 0x80004a) (Int)
17529sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
17530sub %i0, %i2, %i2
17531mov %l4, %o5
17532swap [%i2 + 12], %o5
17533! move %o5(lower) -> %o1(lower)
17534srl %o5, 0, %l6
17535or %l6, %o1, %o1
17536add %l4, 1, %l4
17537
17538P1178: !_MEMBAR (FP) (Branch target of P1351)
17539ba P1179
17540nop
17541
17542TARGET1351:
17543ba RET1351
17544nop
17545
17546
17547P1179: !_BSTC [10] (maybe <- 0x40000037) (FP)
17548wr %g0, 0xe0, %asi
17549! preparing store val #0, next val will be in f32
17550fmovs %f16, %f20
17551fadds %f16, %f17, %f16
17552! preparing store val #1, next val will be in f33
17553fmovs %f16, %f21
17554fadds %f16, %f17, %f16
17555! preparing store val #2, next val will be in f35
17556fmovd %f20, %f32
17557fmovs %f16, %f21
17558fadds %f16, %f17, %f16
17559fmovd %f20, %f34
17560membar #Sync
17561stda %f32, [%i3 + 0 ] %asi
17562
17563P1180: !_MEMBAR (FP)
17564membar #StoreLoad
17565
17566P1181: !_DWST [10] (maybe <- 0x80004b) (Int)
17567sllx %l4, 32, %o5
17568add %l4, 1, %l4
17569or %o5, %l4, %o5
17570stx %o5, [%i3 + 0]
17571add %l4, 1, %l4
17572
17573P1182: !_PREFETCH [5] (Int)
17574prefetch [%i1 + 12], 0
17575
17576P1183: !_CASX [11] (maybe <- 0x80004d) (Int)
17577add %i3, 8, %o5
17578ldx [%o5], %o2
17579! move %o2(upper) -> %o2(upper)
17580! move %o2(lower) -> %o2(lower)
17581mov %o2, %l7
17582mov %l4, %o3
17583casx [%o5], %l7, %o3
17584! move %o3(upper) -> %o3(upper)
17585! move %o3(lower) -> %o3(lower)
17586add %l4, 1, %l4
17587
17588P1184: !_LD [20] (Int)
17589sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
17590sub %i0, %i3, %i3
17591lduw [%i3 + 12], %o4
17592! move %o4(lower) -> %o4(upper)
17593sllx %o4, 32, %o4
17594
17595P1185: !_DWST_BINIT [14] (maybe <- 0x80004e) (Int)
17596wr %g0, 0xe2, %asi
17597sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
17598add %i0, %i2, %i2
17599mov %l4, %l3
17600stxa %l3, [%i2 + 8] %asi
17601add %l4, 1, %l4
17602
17603P1186: !_MEMBAR (Int)
17604membar #StoreLoad
17605
17606P1187: !_PREFETCH [18] (Int)
17607prefetch [%i3 + 0], 4
17608
17609P1188: !_CAS [4] (maybe <- 0x80004f) (Int)
17610add %i1, 4, %l3
17611lduw [%l3], %l7
17612mov %l7, %o5
17613! move %o5(lower) -> %o4(lower)
17614or %o5, %o4, %o4
17615!---- flushing int results buffer----
17616mov %o0, %l5
17617mov %o1, %l5
17618mov %o2, %l5
17619mov %o3, %l5
17620mov %o4, %l5
17621mov %l4, %o0
17622cas [%l3], %o5, %o0
17623! move %o0(lower) -> %o0(upper)
17624sllx %o0, 32, %o0
17625add %l4, 1, %l4
17626
17627P1189: !_MEMBAR (FP)
17628membar #StoreLoad
17629
17630P1190: !_BLD [19] (FP) (Branch target of P1215)
17631wr %g0, 0xf0, %asi
17632ldda [%i3 + 0] %asi, %f32
17633membar #Sync
17634! 3 addresses covered
17635fmovd %f32, %f12
17636fmovd %f34, %f18
17637fmovs %f19, %f14
17638ba P1191
17639nop
17640
17641TARGET1215:
17642ba RET1215
17643nop
17644
17645
17646P1191: !_MEMBAR (FP)
17647
17648P1192: !_BLD [4] (FP)
17649wr %g0, 0xf0, %asi
17650ldda [%i1 + 0] %asi, %f32
17651membar #Sync
17652! 3 addresses covered
17653fmovd %f32, %f18
17654fmovs %f18, %f15
17655!---- flushing fp results buffer to %f30 ----
17656fmovd %f0, %f30
17657fmovd %f2, %f30
17658fmovd %f4, %f30
17659fmovd %f6, %f30
17660fmovd %f8, %f30
17661fmovd %f10, %f30
17662fmovd %f12, %f30
17663fmovd %f14, %f30
17664!--
17665fmovs %f19, %f0
17666fmovd %f34, %f18
17667fmovs %f19, %f1
17668
17669P1193: !_MEMBAR (FP) (CBR)
17670
17671! cbranch
17672andcc %l0, 1, %g0
17673be,pt %xcc, TARGET1193
17674nop
17675RET1193:
17676
17677! lfsr step begin
17678srlx %l0, 1, %l3
17679xnor %l3, %l0, %l3
17680sllx %l3, 63, %l3
17681or %l3, %l0, %l0
17682srlx %l0, 1, %l0
17683
17684
17685P1194: !_LD [2] (FP)
17686ld [%i0 + 12], %f2
17687! 1 addresses covered
17688
17689P1195: !_REPLACEMENT [13] (Int)
17690sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
17691add %i0, %i3, %i3
17692sethi %hi(0x20000), %l6
17693ld [%i3+4], %o5
17694st %o5, [%i3+4]
17695add %i3, %l6, %l7
17696ld [%l7+4], %o5
17697st %o5, [%l7+4]
17698add %l7, %l6, %l7
17699ld [%l7+4], %o5
17700st %o5, [%l7+4]
17701add %l7, %l6, %l7
17702ld [%l7+4], %o5
17703st %o5, [%l7+4]
17704add %l7, %l6, %l7
17705ld [%l7+4], %o5
17706st %o5, [%l7+4]
17707add %l7, %l6, %l7
17708ld [%l7+4], %o5
17709st %o5, [%l7+4]
17710add %l7, %l6, %l7
17711ld [%l7+4], %o5
17712st %o5, [%l7+4]
17713add %l7, %l6, %l7
17714ld [%l7+4], %o5
17715st %o5, [%l7+4]
17716
17717P1196: !_LD [22] (Int)
17718sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
17719sub %i0, %i2, %i2
17720lduw [%i2 + 4], %l6
17721! move %l6(lower) -> %o0(lower)
17722or %l6, %o0, %o0
17723
17724P1197: !_CAS [20] (maybe <- 0x800050) (Int)
17725sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
17726sub %i0, %i3, %i3
17727add %i3, 12, %o5
17728lduw [%o5], %o1
17729mov %o1, %l7
17730! move %l7(lower) -> %o1(upper)
17731sllx %l7, 32, %o1
17732mov %l4, %l6
17733cas [%o5], %l7, %l6
17734! move %l6(lower) -> %o1(lower)
17735srl %l6, 0, %l7
17736or %l7, %o1, %o1
17737add %l4, 1, %l4
17738
17739P1198: !_SWAP [21] (maybe <- 0x800051) (Int)
17740mov %l4, %o2
17741swap [%i2 + 0], %o2
17742! move %o2(lower) -> %o2(upper)
17743sllx %o2, 32, %o2
17744add %l4, 1, %l4
17745
17746P1199: !_ST [13] (maybe <- 0x800052) (Int)
17747sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
17748add %i0, %i2, %i2
17749stw %l4, [%i2 + 4 ]
17750add %l4, 1, %l4
17751
17752P1200: !_DWST_BINIT [8] (maybe <- 0x800053) (Int)
17753wr %g0, 0xe2, %asi
17754sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
17755sub %i0, %i3, %i3
17756mov %l4, %l3
17757stxa %l3, [%i3 + 8] %asi
17758add %l4, 1, %l4
17759
17760P1201: !_MEMBAR (Int)
17761membar #StoreLoad
17762
17763P1202: !_PREFETCH [0] (Int)
17764prefetch [%i0 + 0], 20
17765
17766P1203: !_SWAP [23] (maybe <- 0x800054) (Int)
17767sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
17768sub %i0, %i2, %i2
17769mov %l4, %l6
17770swap [%i2 + 12], %l6
17771! move %l6(lower) -> %o2(lower)
17772srl %l6, 0, %o5
17773or %o5, %o2, %o2
17774add %l4, 1, %l4
17775
17776P1204: !_SWAP [4] (maybe <- 0x800055) (Int)
17777mov %l4, %o3
17778swap [%i1 + 4], %o3
17779! move %o3(lower) -> %o3(upper)
17780sllx %o3, 32, %o3
17781add %l4, 1, %l4
17782
17783P1205: !_CASX [5] (maybe <- 0x800056) (Int)
17784add %i1, 8, %l7
17785ldx [%l7], %l3
17786! move %l3(upper) -> %o3(lower)
17787srlx %l3, 32, %l6
17788or %l6, %o3, %o3
17789! move %l3(lower) -> %o4(upper)
17790sllx %l3, 32, %o4
17791mov %l3, %l6
17792mov %l4, %l3
17793casx [%l7], %l6, %l3
17794! move %l3(upper) -> %o4(lower)
17795srlx %l3, 32, %l6
17796or %l6, %o4, %o4
17797!---- flushing int results buffer----
17798mov %o0, %l5
17799mov %o1, %l5
17800mov %o2, %l5
17801mov %o3, %l5
17802mov %o4, %l5
17803! move %l3(lower) -> %o0(upper)
17804sllx %l3, 32, %o0
17805add %l4, 1, %l4
17806
17807P1206: !_MEMBAR (FP)
17808
17809P1207: !_BSTC [10] (maybe <- 0x4000003a) (FP)
17810wr %g0, 0xe0, %asi
17811sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
17812add %i0, %i3, %i3
17813! preparing store val #0, next val will be in f32
17814fmovs %f16, %f20
17815fadds %f16, %f17, %f16
17816! preparing store val #1, next val will be in f33
17817fmovs %f16, %f21
17818fadds %f16, %f17, %f16
17819! preparing store val #2, next val will be in f35
17820fmovd %f20, %f32
17821fmovs %f16, %f21
17822fadds %f16, %f17, %f16
17823fmovd %f20, %f34
17824membar #Sync
17825stda %f32, [%i3 + 0 ] %asi
17826
17827P1208: !_MEMBAR (FP)
17828
17829P1209: !_BST [15] (maybe <- 0x4000003d) (FP)
17830wr %g0, 0xf0, %asi
17831sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
17832sub %i0, %i2, %i2
17833! preparing store val #0, next val will be in f32
17834fmovs %f16, %f20
17835fadds %f16, %f17, %f16
17836! preparing store val #1, next val will be in f33
17837fmovs %f16, %f21
17838fadds %f16, %f17, %f16
17839! preparing store val #2, next val will be in f35
17840fmovd %f20, %f32
17841fmovs %f16, %f21
17842fadds %f16, %f17, %f16
17843fmovd %f20, %f34
17844membar #Sync
17845stda %f32, [%i2 + 0 ] %asi
17846
17847P1210: !_MEMBAR (FP) (CBR)
17848membar #StoreLoad
17849
17850! cbranch
17851andcc %l0, 1, %g0
17852be,pt %xcc, TARGET1210
17853nop
17854RET1210:
17855
17856! lfsr step begin
17857srlx %l0, 1, %o5
17858xnor %o5, %l0, %o5
17859sllx %o5, 63, %o5
17860or %o5, %l0, %l0
17861srlx %l0, 1, %l0
17862
17863
17864P1211: !_DWST [18] (maybe <- 0x800057) (Int)
17865sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
17866sub %i0, %i3, %i3
17867sllx %l4, 32, %l3
17868add %l4, 1, %l4
17869or %l3, %l4, %l3
17870stx %l3, [%i3 + 0]
17871add %l4, 1, %l4
17872
17873P1212: !_DWST_BINIT [20] (maybe <- 0x800059) (Int)
17874wr %g0, 0xe2, %asi
17875mov %l4, %o5
17876stxa %o5, [%i3 + 8] %asi
17877add %l4, 1, %l4
17878
17879P1213: !_MEMBAR (Int)
17880membar #StoreLoad
17881
17882P1214: !_DWLD [3] (Int)
17883ldx [%i1 + 0], %o5
17884! move %o5(upper) -> %o0(lower)
17885srlx %o5, 32, %l7
17886or %l7, %o0, %o0
17887! move %o5(lower) -> %o1(upper)
17888sllx %o5, 32, %o1
17889
17890P1215: !_CAS [17] (maybe <- 0x80005a) (Int) (CBR)
17891add %i2, 12, %l6
17892lduw [%l6], %o5
17893mov %o5, %l3
17894! move %l3(lower) -> %o1(lower)
17895or %l3, %o1, %o1
17896mov %l4, %o2
17897cas [%l6], %l3, %o2
17898! move %o2(lower) -> %o2(upper)
17899sllx %o2, 32, %o2
17900add %l4, 1, %l4
17901
17902! cbranch
17903andcc %l0, 1, %g0
17904be,pn %xcc, TARGET1215
17905nop
17906RET1215:
17907
17908! lfsr step begin
17909srlx %l0, 1, %l3
17910xnor %l3, %l0, %l3
17911sllx %l3, 63, %l3
17912or %l3, %l0, %l0
17913srlx %l0, 1, %l0
17914
17915
17916P1216: !_DWST_BINIT [10] (maybe <- 0x80005b) (Int)
17917wr %g0, 0xe2, %asi
17918sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
17919add %i0, %i2, %i2
17920sllx %l4, 32, %l6
17921add %l4, 1, %l4
17922or %l6, %l4, %l6
17923stxa %l6, [%i2 + 0] %asi
17924add %l4, 1, %l4
17925
17926P1217: !_MEMBAR (Int) (Branch target of P1738)
17927ba P1218
17928nop
17929
17930TARGET1738:
17931ba RET1738
17932nop
17933
17934
17935P1218: !_BST [23] (maybe <- 0x40000040) (FP)
17936wr %g0, 0xf0, %asi
17937sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
17938sub %i0, %i3, %i3
17939! preparing store val #0, next val will be in f32
17940fmovs %f16, %f20
17941fadds %f16, %f17, %f16
17942! preparing store val #1, next val will be in f33
17943fmovs %f16, %f21
17944fadds %f16, %f17, %f16
17945! preparing store val #2, next val will be in f35
17946fmovd %f20, %f32
17947fmovs %f16, %f21
17948fadds %f16, %f17, %f16
17949fmovd %f20, %f34
17950membar #Sync
17951stda %f32, [%i3 + 0 ] %asi
17952
17953P1219: !_MEMBAR (FP)
17954membar #StoreLoad
17955
17956P1220: !_DWST [12] (maybe <- 0x80005d) (Int)
17957sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
17958add %i0, %i2, %i2
17959sllx %l4, 32, %o5
17960add %l4, 1, %l4
17961or %o5, %l4, %o5
17962stx %o5, [%i2 + 0]
17963add %l4, 1, %l4
17964
17965P1221: !_MEMBAR (FP)
17966
17967P1222: !_BST [7] (maybe <- 0x40000043) (FP)
17968wr %g0, 0xf0, %asi
17969sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
17970sub %i0, %i3, %i3
17971! preparing store val #0, next val will be in f32
17972fmovs %f16, %f20
17973fadds %f16, %f17, %f16
17974! preparing store val #1, next val will be in f33
17975fmovs %f16, %f21
17976fadds %f16, %f17, %f16
17977! preparing store val #2, next val will be in f35
17978fmovd %f20, %f32
17979fmovs %f16, %f21
17980fadds %f16, %f17, %f16
17981fmovd %f20, %f34
17982membar #Sync
17983stda %f32, [%i3 + 0 ] %asi
17984
17985P1223: !_MEMBAR (FP)
17986membar #StoreLoad
17987
17988P1224: !_PREFETCH [13] (Int)
17989prefetch [%i2 + 4], 0
17990
17991P1225: !_REPLACEMENT [20] (Int)
17992sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
17993sub %i0, %i2, %i2
17994sethi %hi(0x20000), %l6
17995ld [%i2+12], %o5
17996st %o5, [%i2+12]
17997add %i2, %l6, %l7
17998ld [%l7+12], %o5
17999st %o5, [%l7+12]
18000add %l7, %l6, %l7
18001ld [%l7+12], %o5
18002st %o5, [%l7+12]
18003add %l7, %l6, %l7
18004ld [%l7+12], %o5
18005st %o5, [%l7+12]
18006add %l7, %l6, %l7
18007ld [%l7+12], %o5
18008st %o5, [%l7+12]
18009add %l7, %l6, %l7
18010ld [%l7+12], %o5
18011st %o5, [%l7+12]
18012add %l7, %l6, %l7
18013ld [%l7+12], %o5
18014st %o5, [%l7+12]
18015add %l7, %l6, %l7
18016ld [%l7+12], %o5
18017st %o5, [%l7+12]
18018
18019P1226: !_ST [6] (maybe <- 0x80005f) (Int)
18020stw %l4, [%i3 + 0 ]
18021add %l4, 1, %l4
18022
18023P1227: !_SWAP [15] (maybe <- 0x800060) (Int)
18024sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
18025sub %i0, %i3, %i3
18026mov %l4, %l6
18027swap [%i3 + 0], %l6
18028! move %l6(lower) -> %o2(lower)
18029srl %l6, 0, %o5
18030or %o5, %o2, %o2
18031add %l4, 1, %l4
18032
18033P1228: !_ST [1] (maybe <- 0x800061) (Int)
18034stw %l4, [%i0 + 4 ]
18035add %l4, 1, %l4
18036
18037P1229: !_REPLACEMENT [21] (Int)
18038sethi %hi(0x20000), %l6
18039ld [%i2+0], %o5
18040st %o5, [%i2+0]
18041add %i2, %l6, %l7
18042ld [%l7+0], %o5
18043st %o5, [%l7+0]
18044add %l7, %l6, %l7
18045ld [%l7+0], %o5
18046st %o5, [%l7+0]
18047add %l7, %l6, %l7
18048ld [%l7+0], %o5
18049st %o5, [%l7+0]
18050add %l7, %l6, %l7
18051ld [%l7+0], %o5
18052st %o5, [%l7+0]
18053add %l7, %l6, %l7
18054ld [%l7+0], %o5
18055st %o5, [%l7+0]
18056add %l7, %l6, %l7
18057ld [%l7+0], %o5
18058st %o5, [%l7+0]
18059add %l7, %l6, %l7
18060ld [%l7+0], %o5
18061st %o5, [%l7+0]
18062
18063P1230: !_SWAP [20] (maybe <- 0x800062) (Int)
18064sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
18065sub %i0, %i2, %i2
18066mov %l4, %o3
18067swap [%i2 + 12], %o3
18068! move %o3(lower) -> %o3(upper)
18069sllx %o3, 32, %o3
18070add %l4, 1, %l4
18071
18072P1231: !_LD [13] (Int) (LE) (Branch target of P1334)
18073wr %g0, 0x88, %asi
18074sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
18075add %i0, %i3, %i3
18076lduwa [%i3 + 4] %asi, %l3
18077! move %l3(lower) -> %o3(lower)
18078or %l3, %o3, %o3
18079ba P1232
18080nop
18081
18082TARGET1334:
18083ba RET1334
18084nop
18085
18086
18087P1232: !_MEMBAR (FP)
18088
18089P1233: !_BST [6] (maybe <- 0x40000046) (FP)
18090wr %g0, 0xf0, %asi
18091sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
18092sub %i0, %i2, %i2
18093! preparing store val #0, next val will be in f32
18094fmovs %f16, %f20
18095fadds %f16, %f17, %f16
18096! preparing store val #1, next val will be in f33
18097fmovs %f16, %f21
18098fadds %f16, %f17, %f16
18099! preparing store val #2, next val will be in f35
18100fmovd %f20, %f32
18101fmovs %f16, %f21
18102fadds %f16, %f17, %f16
18103fmovd %f20, %f34
18104membar #Sync
18105stda %f32, [%i2 + 0 ] %asi
18106
18107P1234: !_MEMBAR (FP) (CBR)
18108membar #StoreLoad
18109
18110! cbranch
18111andcc %l0, 1, %g0
18112be,pn %xcc, TARGET1234
18113nop
18114RET1234:
18115
18116! lfsr step begin
18117srlx %l0, 1, %l3
18118xnor %l3, %l0, %l3
18119sllx %l3, 63, %l3
18120or %l3, %l0, %l0
18121srlx %l0, 1, %l0
18122
18123
18124P1235: !_DWST_BINIT [0] (maybe <- 0x800063) (Int)
18125wr %g0, 0xe2, %asi
18126sllx %l4, 32, %l6
18127add %l4, 1, %l4
18128or %l6, %l4, %l6
18129stxa %l6, [%i0 + 0] %asi
18130add %l4, 1, %l4
18131
18132P1236: !_MEMBAR (Int)
18133membar #StoreLoad
18134
18135P1237: !_PREFETCH [22] (Int) (LE)
18136wr %g0, 0x88, %asi
18137sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
18138sub %i0, %i3, %i3
18139prefetcha [%i3 + 4] %asi, 1
18140
18141P1238: !_MEMBAR (FP)
18142membar #StoreLoad
18143
18144P1239: !_BLD [0] (FP)
18145wr %g0, 0xf0, %asi
18146ldda [%i0 + 0] %asi, %f32
18147membar #Sync
18148! 3 addresses covered
18149fmovd %f32, %f18
18150fmovs %f18, %f3
18151fmovs %f19, %f4
18152fmovd %f34, %f18
18153fmovs %f19, %f5
18154
18155P1240: !_MEMBAR (FP)
18156
18157P1241: !_ST [21] (maybe <- 0x800065) (Int)
18158stw %l4, [%i3 + 0 ]
18159add %l4, 1, %l4
18160
18161P1242: !_DWST_BINIT [1] (maybe <- 0x800066) (Int)
18162wr %g0, 0xe2, %asi
18163sllx %l4, 32, %o5
18164add %l4, 1, %l4
18165or %o5, %l4, %o5
18166stxa %o5, [%i0 + 0] %asi
18167add %l4, 1, %l4
18168
18169P1243: !_MEMBAR (Int)
18170membar #StoreLoad
18171
18172P1244: !_DWST_BINIT [16] (maybe <- 0x800068) (Int) (Branch target of P1942)
18173wr %g0, 0xe2, %asi
18174sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
18175sub %i0, %i2, %i2
18176sllx %l4, 32, %l7
18177add %l4, 1, %l4
18178or %l7, %l4, %l7
18179stxa %l7, [%i2 + 0] %asi
18180add %l4, 1, %l4
18181ba P1245
18182nop
18183
18184TARGET1942:
18185ba RET1942
18186nop
18187
18188
18189P1245: !_MEMBAR (Int)
18190membar #StoreLoad
18191
18192P1246: !_PREFETCH [23] (Int)
18193prefetch [%i3 + 12], 23
18194
18195P1247: !_MEMBAR (FP)
18196
18197P1248: !_BST [3] (maybe <- 0x40000049) (FP) (Branch target of P1982)
18198wr %g0, 0xf0, %asi
18199! preparing store val #0, next val will be in f32
18200fmovs %f16, %f20
18201fadds %f16, %f17, %f16
18202! preparing store val #1, next val will be in f33
18203fmovs %f16, %f21
18204fadds %f16, %f17, %f16
18205! preparing store val #2, next val will be in f35
18206fmovd %f20, %f32
18207fmovs %f16, %f21
18208fadds %f16, %f17, %f16
18209fmovd %f20, %f34
18210membar #Sync
18211stda %f32, [%i1 + 0 ] %asi
18212ba P1249
18213nop
18214
18215TARGET1982:
18216ba RET1982
18217nop
18218
18219
18220P1249: !_MEMBAR (FP)
18221membar #StoreLoad
18222
18223P1250: !_SWAP [21] (maybe <- 0x80006a) (Int)
18224mov %l4, %o4
18225swap [%i3 + 0], %o4
18226! move %o4(lower) -> %o4(upper)
18227sllx %o4, 32, %o4
18228add %l4, 1, %l4
18229
18230P1251: !_LD [23] (Int)
18231lduw [%i3 + 12], %l3
18232! move %l3(lower) -> %o4(lower)
18233or %l3, %o4, %o4
18234!---- flushing int results buffer----
18235mov %o0, %l5
18236mov %o1, %l5
18237mov %o2, %l5
18238mov %o3, %l5
18239mov %o4, %l5
18240
18241P1252: !_ST [23] (maybe <- 0x80006b) (Int)
18242stw %l4, [%i3 + 12 ]
18243add %l4, 1, %l4
18244
18245P1253: !_REPLACEMENT [19] (Int)
18246sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
18247sub %i0, %i3, %i3
18248sethi %hi(0x20000), %l3
18249ld [%i3+4], %l7
18250st %l7, [%i3+4]
18251add %i3, %l3, %l6
18252ld [%l6+4], %l7
18253st %l7, [%l6+4]
18254add %l6, %l3, %l6
18255ld [%l6+4], %l7
18256st %l7, [%l6+4]
18257add %l6, %l3, %l6
18258ld [%l6+4], %l7
18259st %l7, [%l6+4]
18260add %l6, %l3, %l6
18261ld [%l6+4], %l7
18262st %l7, [%l6+4]
18263add %l6, %l3, %l6
18264ld [%l6+4], %l7
18265st %l7, [%l6+4]
18266add %l6, %l3, %l6
18267ld [%l6+4], %l7
18268st %l7, [%l6+4]
18269add %l6, %l3, %l6
18270ld [%l6+4], %l7
18271st %l7, [%l6+4]
18272
18273P1254: !_LDD [19] (Int)
18274sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
18275sub %i0, %i2, %i2
18276ldd [%i2 + 0], %l6
18277! move %l6(lower) -> %o0(upper)
18278sllx %l6, 32, %o0
18279! move %l7(lower) -> %o0(lower)
18280or %l7, %o0, %o0
18281
18282P1255: !_ST_BINIT [11] (maybe <- 0x80006c) (Int)
18283wr %g0, 0xe2, %asi
18284sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
18285add %i0, %i3, %i3
18286stwa %l4, [%i3 + 12] %asi
18287add %l4, 1, %l4
18288
18289P1256: !_MEMBAR (Int)
18290membar #StoreLoad
18291
18292P1257: !_CAS [22] (maybe <- 0x80006d) (Int)
18293sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
18294sub %i0, %i2, %i2
18295add %i2, 4, %l6
18296lduw [%l6], %o1
18297mov %o1, %l3
18298! move %l3(lower) -> %o1(upper)
18299sllx %l3, 32, %o1
18300mov %l4, %o5
18301cas [%l6], %l3, %o5
18302! move %o5(lower) -> %o1(lower)
18303srl %o5, 0, %l3
18304or %l3, %o1, %o1
18305add %l4, 1, %l4
18306
18307P1258: !_ST [17] (maybe <- 0x4000004c) (FP)
18308sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
18309sub %i0, %i3, %i3
18310! preparing store val #0, next val will be in f20
18311fmovs %f16, %f20
18312fadds %f16, %f17, %f16
18313st %f20, [%i3 + 12 ]
18314
18315P1259: !_PREFETCH [13] (Int) (CBR)
18316sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
18317add %i0, %i2, %i2
18318prefetch [%i2 + 4], 21
18319
18320! cbranch
18321andcc %l0, 1, %g0
18322be,pt %xcc, TARGET1259
18323nop
18324RET1259:
18325
18326! lfsr step begin
18327srlx %l0, 1, %o5
18328xnor %o5, %l0, %o5
18329sllx %o5, 63, %o5
18330or %o5, %l0, %l0
18331srlx %l0, 1, %l0
18332
18333
18334P1260: !_ST [8] (maybe <- 0x80006e) (Int)
18335sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
18336sub %i0, %i3, %i3
18337stw %l4, [%i3 + 12 ]
18338add %l4, 1, %l4
18339
18340P1261: !_CAS [15] (maybe <- 0x80006f) (Int)
18341sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
18342sub %i0, %i2, %i2
18343lduw [%i2], %o2
18344mov %o2, %o5
18345! move %o5(lower) -> %o2(upper)
18346sllx %o5, 32, %o2
18347mov %l4, %l7
18348cas [%i2], %o5, %l7
18349! move %l7(lower) -> %o2(lower)
18350srl %l7, 0, %o5
18351or %o5, %o2, %o2
18352add %l4, 1, %l4
18353
18354P1262: !_DWLD [14] (Int)
18355sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
18356add %i0, %i3, %i3
18357ldx [%i3 + 8], %o3
18358! move %o3(lower) -> %o3(upper)
18359sllx %o3, 32, %o3
18360
18361P1263: !_DWST [6] (maybe <- 0x800070) (Int)
18362sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
18363sub %i0, %i2, %i2
18364sllx %l4, 32, %l6
18365add %l4, 1, %l4
18366or %l6, %l4, %l6
18367stx %l6, [%i2 + 0]
18368add %l4, 1, %l4
18369
18370P1264: !_LDD [10] (Int)
18371sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
18372add %i0, %i3, %i3
18373ldd [%i3 + 0], %l6
18374! move %l6(lower) -> %o3(lower)
18375or %l6, %o3, %o3
18376! move %l7(lower) -> %o4(upper)
18377sllx %l7, 32, %o4
18378
18379P1265: !_CASX [13] (maybe <- 0x800072) (Int) (CBR)
18380sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
18381add %i0, %i2, %i2
18382ldx [%i2], %o5
18383! move %o5(upper) -> %o4(lower)
18384srlx %o5, 32, %l3
18385or %l3, %o4, %o4
18386!---- flushing int results buffer----
18387mov %o0, %l5
18388mov %o1, %l5
18389mov %o2, %l5
18390mov %o3, %l5
18391mov %o4, %l5
18392! move %o5(lower) -> %o0(upper)
18393sllx %o5, 32, %o0
18394mov %o5, %l3
18395sllx %l4, 32, %o5
18396add %l4, 1, %l4
18397or %l4, %o5, %o5
18398casx [%i2], %l3, %o5
18399! move %o5(upper) -> %o0(lower)
18400srlx %o5, 32, %l3
18401or %l3, %o0, %o0
18402! move %o5(lower) -> %o1(upper)
18403sllx %o5, 32, %o1
18404add %l4, 1, %l4
18405
18406! cbranch
18407andcc %l0, 1, %g0
18408be,pn %xcc, TARGET1265
18409nop
18410RET1265:
18411
18412! lfsr step begin
18413srlx %l0, 1, %l3
18414xnor %l3, %l0, %l3
18415sllx %l3, 63, %l3
18416or %l3, %l0, %l0
18417srlx %l0, 1, %l0
18418
18419
18420P1266: !_REPLACEMENT [22] (Int)
18421sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
18422add %i0, %i3, %i3
18423sethi %hi(0x20000), %l6
18424ld [%i3+4], %o5
18425st %o5, [%i3+4]
18426add %i3, %l6, %l7
18427ld [%l7+4], %o5
18428st %o5, [%l7+4]
18429add %l7, %l6, %l7
18430ld [%l7+4], %o5
18431st %o5, [%l7+4]
18432add %l7, %l6, %l7
18433ld [%l7+4], %o5
18434st %o5, [%l7+4]
18435add %l7, %l6, %l7
18436ld [%l7+4], %o5
18437st %o5, [%l7+4]
18438add %l7, %l6, %l7
18439ld [%l7+4], %o5
18440st %o5, [%l7+4]
18441add %l7, %l6, %l7
18442ld [%l7+4], %o5
18443st %o5, [%l7+4]
18444add %l7, %l6, %l7
18445ld [%l7+4], %o5
18446st %o5, [%l7+4]
18447
18448P1267: !_PREFETCH [7] (Int)
18449sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
18450sub %i0, %i2, %i2
18451prefetch [%i2 + 4], 2
18452
18453P1268: !_LDD [10] (Int)
18454sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
18455add %i0, %i3, %i3
18456ldd [%i3 + 0], %l6
18457! move %l6(lower) -> %o1(lower)
18458or %l6, %o1, %o1
18459! move %l7(lower) -> %o2(upper)
18460sllx %l7, 32, %o2
18461
18462P1269: !_SWAP [23] (maybe <- 0x800074) (Int)
18463sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
18464sub %i0, %i2, %i2
18465mov %l4, %l7
18466swap [%i2 + 12], %l7
18467! move %l7(lower) -> %o2(lower)
18468srl %l7, 0, %l3
18469or %l3, %o2, %o2
18470add %l4, 1, %l4
18471
18472P1270: !_SWAP [15] (maybe <- 0x800075) (Int)
18473sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
18474sub %i0, %i3, %i3
18475mov %l4, %o3
18476swap [%i3 + 0], %o3
18477! move %o3(lower) -> %o3(upper)
18478sllx %o3, 32, %o3
18479add %l4, 1, %l4
18480
18481P1271: !_DWLD [18] (Int)
18482sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
18483sub %i0, %i2, %i2
18484ldx [%i2 + 0], %o5
18485! move %o5(upper) -> %o3(lower)
18486srlx %o5, 32, %l7
18487or %l7, %o3, %o3
18488! move %o5(lower) -> %o4(upper)
18489sllx %o5, 32, %o4
18490
18491P1272: !_SWAP [12] (maybe <- 0x800076) (Int) (Branch target of P1513)
18492sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
18493add %i0, %i3, %i3
18494mov %l4, %l7
18495swap [%i3 + 0], %l7
18496! move %l7(lower) -> %o4(lower)
18497srl %l7, 0, %l3
18498or %l3, %o4, %o4
18499!---- flushing int results buffer----
18500mov %o0, %l5
18501mov %o1, %l5
18502mov %o2, %l5
18503mov %o3, %l5
18504mov %o4, %l5
18505add %l4, 1, %l4
18506ba P1273
18507nop
18508
18509TARGET1513:
18510ba RET1513
18511nop
18512
18513
18514P1273: !_DWST [4] (maybe <- 0x800077) (Int)
18515sllx %l4, 32, %o5
18516add %l4, 1, %l4
18517or %o5, %l4, %o5
18518stx %o5, [%i1 + 0]
18519add %l4, 1, %l4
18520
18521P1274: !_DWST [1] (maybe <- 0x800079) (Int)
18522sllx %l4, 32, %l7
18523add %l4, 1, %l4
18524or %l7, %l4, %l7
18525stx %l7, [%i0 + 0]
18526add %l4, 1, %l4
18527
18528P1275: !_CAS [15] (maybe <- 0x80007b) (Int)
18529sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
18530sub %i0, %i2, %i2
18531lduw [%i2], %o0
18532mov %o0, %l6
18533! move %l6(lower) -> %o0(upper)
18534sllx %l6, 32, %o0
18535mov %l4, %l3
18536cas [%i2], %l6, %l3
18537! move %l3(lower) -> %o0(lower)
18538srl %l3, 0, %l6
18539or %l6, %o0, %o0
18540add %l4, 1, %l4
18541
18542P1276: !_LDD [8] (Int) (Branch target of P1780)
18543sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
18544sub %i0, %i3, %i3
18545ldd [%i3 + 8], %l6
18546! move %l7(lower) -> %o1(upper)
18547sllx %l7, 32, %o1
18548ba P1277
18549nop
18550
18551TARGET1780:
18552ba RET1780
18553nop
18554
18555
18556P1277: !_MEMBAR (FP)
18557
18558P1278: !_BSTC [8] (maybe <- 0x4000004d) (FP) (CBR)
18559wr %g0, 0xe0, %asi
18560! preparing store val #0, next val will be in f32
18561fmovs %f16, %f20
18562fadds %f16, %f17, %f16
18563! preparing store val #1, next val will be in f33
18564fmovs %f16, %f21
18565fadds %f16, %f17, %f16
18566! preparing store val #2, next val will be in f35
18567fmovd %f20, %f32
18568fmovs %f16, %f21
18569fadds %f16, %f17, %f16
18570fmovd %f20, %f34
18571membar #Sync
18572stda %f32, [%i3 + 0 ] %asi
18573
18574! cbranch
18575andcc %l0, 1, %g0
18576be,pn %xcc, TARGET1278
18577nop
18578RET1278:
18579
18580! lfsr step begin
18581srlx %l0, 1, %o5
18582xnor %o5, %l0, %o5
18583sllx %o5, 63, %o5
18584or %o5, %l0, %l0
18585srlx %l0, 1, %l0
18586
18587
18588P1279: !_MEMBAR (FP)
18589membar #StoreLoad
18590
18591P1280: !_LD [20] (Int)
18592sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
18593sub %i0, %i2, %i2
18594lduw [%i2 + 12], %l6
18595! move %l6(lower) -> %o1(lower)
18596or %l6, %o1, %o1
18597
18598P1281: !_MEMBAR (FP)
18599
18600P1282: !_BST [21] (maybe <- 0x40000050) (FP)
18601wr %g0, 0xf0, %asi
18602sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
18603sub %i0, %i3, %i3
18604! preparing store val #0, next val will be in f32
18605fmovs %f16, %f20
18606fadds %f16, %f17, %f16
18607! preparing store val #1, next val will be in f33
18608fmovs %f16, %f21
18609fadds %f16, %f17, %f16
18610! preparing store val #2, next val will be in f35
18611fmovd %f20, %f32
18612fmovs %f16, %f21
18613fadds %f16, %f17, %f16
18614fmovd %f20, %f34
18615membar #Sync
18616stda %f32, [%i3 + 0 ] %asi
18617
18618P1283: !_MEMBAR (FP)
18619
18620P1284: !_BST [23] (maybe <- 0x40000053) (FP)
18621wr %g0, 0xf0, %asi
18622! preparing store val #0, next val will be in f32
18623fmovs %f16, %f20
18624fadds %f16, %f17, %f16
18625! preparing store val #1, next val will be in f33
18626fmovs %f16, %f21
18627fadds %f16, %f17, %f16
18628! preparing store val #2, next val will be in f35
18629fmovd %f20, %f32
18630fmovs %f16, %f21
18631fadds %f16, %f17, %f16
18632fmovd %f20, %f34
18633membar #Sync
18634stda %f32, [%i3 + 0 ] %asi
18635
18636P1285: !_MEMBAR (FP)
18637
18638P1286: !_BSTC [6] (maybe <- 0x40000056) (FP)
18639wr %g0, 0xe0, %asi
18640sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
18641sub %i0, %i2, %i2
18642! preparing store val #0, next val will be in f32
18643fmovs %f16, %f20
18644fadds %f16, %f17, %f16
18645! preparing store val #1, next val will be in f33
18646fmovs %f16, %f21
18647fadds %f16, %f17, %f16
18648! preparing store val #2, next val will be in f35
18649fmovd %f20, %f32
18650fmovs %f16, %f21
18651fadds %f16, %f17, %f16
18652fmovd %f20, %f34
18653membar #Sync
18654stda %f32, [%i2 + 0 ] %asi
18655
18656P1287: !_MEMBAR (FP)
18657membar #StoreLoad
18658
18659P1288: !_BLD [18] (FP)
18660wr %g0, 0xf0, %asi
18661sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
18662sub %i0, %i3, %i3
18663ldda [%i3 + 0] %asi, %f32
18664membar #Sync
18665! 3 addresses covered
18666fmovd %f32, %f6
18667fmovd %f34, %f18
18668fmovs %f19, %f8
18669
18670P1289: !_MEMBAR (FP)
18671
18672P1290: !_BSTC [7] (maybe <- 0x40000059) (FP) (CBR)
18673wr %g0, 0xe0, %asi
18674! preparing store val #0, next val will be in f32
18675fmovs %f16, %f20
18676fadds %f16, %f17, %f16
18677! preparing store val #1, next val will be in f33
18678fmovs %f16, %f21
18679fadds %f16, %f17, %f16
18680! preparing store val #2, next val will be in f35
18681fmovd %f20, %f32
18682fmovs %f16, %f21
18683fadds %f16, %f17, %f16
18684fmovd %f20, %f34
18685membar #Sync
18686stda %f32, [%i2 + 0 ] %asi
18687
18688! cbranch
18689andcc %l0, 1, %g0
18690be,pt %xcc, TARGET1290
18691nop
18692RET1290:
18693
18694! lfsr step begin
18695srlx %l0, 1, %l7
18696xnor %l7, %l0, %l7
18697sllx %l7, 63, %l7
18698or %l7, %l0, %l0
18699srlx %l0, 1, %l0
18700
18701
18702P1291: !_MEMBAR (FP)
18703membar #StoreLoad
18704
18705P1292: !_ST_BINIT [21] (maybe <- 0x80007c) (Int)
18706wr %g0, 0xe2, %asi
18707sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
18708sub %i0, %i2, %i2
18709stwa %l4, [%i2 + 0] %asi
18710add %l4, 1, %l4
18711
18712P1293: !_MEMBAR (Int)
18713membar #StoreLoad
18714
18715P1294: !_ST_BINIT [23] (maybe <- 0x80007d) (Int)
18716wr %g0, 0xe2, %asi
18717stwa %l4, [%i2 + 12] %asi
18718add %l4, 1, %l4
18719
18720P1295: !_MEMBAR (Int)
18721
18722P1296: !_BSTC [10] (maybe <- 0x4000005c) (FP)
18723wr %g0, 0xe0, %asi
18724sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
18725add %i0, %i3, %i3
18726! preparing store val #0, next val will be in f32
18727fmovs %f16, %f20
18728fadds %f16, %f17, %f16
18729! preparing store val #1, next val will be in f33
18730fmovs %f16, %f21
18731fadds %f16, %f17, %f16
18732! preparing store val #2, next val will be in f35
18733fmovd %f20, %f32
18734fmovs %f16, %f21
18735fadds %f16, %f17, %f16
18736fmovd %f20, %f34
18737membar #Sync
18738stda %f32, [%i3 + 0 ] %asi
18739
18740P1297: !_MEMBAR (FP)
18741membar #StoreLoad
18742
18743P1298: !_LDD [13] (Int)
18744sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
18745add %i0, %i2, %i2
18746ldd [%i2 + 0], %l6
18747! move %l6(lower) -> %o2(upper)
18748sllx %l6, 32, %o2
18749! move %l7(lower) -> %o2(lower)
18750or %l7, %o2, %o2
18751
18752P1299: !_CAS [17] (maybe <- 0x80007e) (Int)
18753sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
18754sub %i0, %i3, %i3
18755add %i3, 12, %l6
18756lduw [%l6], %o3
18757mov %o3, %l3
18758! move %l3(lower) -> %o3(upper)
18759sllx %l3, 32, %o3
18760mov %l4, %o5
18761cas [%l6], %l3, %o5
18762! move %o5(lower) -> %o3(lower)
18763srl %o5, 0, %l3
18764or %l3, %o3, %o3
18765add %l4, 1, %l4
18766
18767P1300: !_DWLD [7] (Int)
18768sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
18769sub %i0, %i2, %i2
18770ldx [%i2 + 0], %o4
18771! move %o4(upper) -> %o4(upper)
18772! move %o4(lower) -> %o4(lower)
18773!---- flushing int results buffer----
18774mov %o0, %l5
18775mov %o1, %l5
18776mov %o2, %l5
18777mov %o3, %l5
18778mov %o4, %l5
18779
18780P1301: !_CASX [22] (maybe <- 0x80007f) (Int)
18781sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
18782sub %i0, %i3, %i3
18783ldx [%i3], %o0
18784! move %o0(upper) -> %o0(upper)
18785! move %o0(lower) -> %o0(lower)
18786mov %o0, %l7
18787sllx %l4, 32, %o1
18788add %l4, 1, %l4
18789or %l4, %o1, %o1
18790casx [%i3], %l7, %o1
18791! move %o1(upper) -> %o1(upper)
18792! move %o1(lower) -> %o1(lower)
18793add %l4, 1, %l4
18794
18795P1302: !_MEMBAR (FP)
18796
18797P1303: !_BSTC [2] (maybe <- 0x4000005f) (FP)
18798wr %g0, 0xe0, %asi
18799! preparing store val #0, next val will be in f32
18800fmovs %f16, %f20
18801fadds %f16, %f17, %f16
18802! preparing store val #1, next val will be in f33
18803fmovs %f16, %f21
18804fadds %f16, %f17, %f16
18805! preparing store val #2, next val will be in f35
18806fmovd %f20, %f32
18807fmovs %f16, %f21
18808fadds %f16, %f17, %f16
18809fmovd %f20, %f34
18810membar #Sync
18811stda %f32, [%i0 + 0 ] %asi
18812
18813P1304: !_MEMBAR (FP)
18814membar #StoreLoad
18815
18816P1305: !_PREFETCH [5] (Int)
18817prefetch [%i1 + 12], 19
18818
18819P1306: !_LDD [9] (Int)
18820sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
18821add %i0, %i2, %i2
18822ldd [%i2 + 0], %l6
18823! move %l6(lower) -> %o2(upper)
18824sllx %l6, 32, %o2
18825! move %l7(lower) -> %o2(lower)
18826or %l7, %o2, %o2
18827
18828P1307: !_CAS [16] (maybe <- 0x800081) (Int)
18829sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
18830sub %i0, %i3, %i3
18831add %i3, 4, %l6
18832lduw [%l6], %o3
18833mov %o3, %l3
18834! move %l3(lower) -> %o3(upper)
18835sllx %l3, 32, %o3
18836mov %l4, %o5
18837cas [%l6], %l3, %o5
18838! move %o5(lower) -> %o3(lower)
18839srl %o5, 0, %l3
18840or %l3, %o3, %o3
18841add %l4, 1, %l4
18842
18843P1308: !_DWLD [10] (Int)
18844ldx [%i2 + 0], %o4
18845! move %o4(upper) -> %o4(upper)
18846! move %o4(lower) -> %o4(lower)
18847!---- flushing int results buffer----
18848mov %o0, %l5
18849mov %o1, %l5
18850mov %o2, %l5
18851mov %o3, %l5
18852mov %o4, %l5
18853
18854P1309: !_MEMBAR (FP)
18855membar #StoreLoad
18856
18857P1310: !_BLD [1] (FP)
18858wr %g0, 0xf0, %asi
18859ldda [%i0 + 0] %asi, %f32
18860membar #Sync
18861! 3 addresses covered
18862fmovd %f32, %f18
18863fmovs %f18, %f9
18864fmovs %f19, %f10
18865fmovd %f34, %f18
18866fmovs %f19, %f11
18867
18868P1311: !_MEMBAR (FP) (CBR)
18869
18870! cbranch
18871andcc %l0, 1, %g0
18872be,pt %xcc, TARGET1311
18873nop
18874RET1311:
18875
18876! lfsr step begin
18877srlx %l0, 1, %l7
18878xnor %l7, %l0, %l7
18879sllx %l7, 63, %l7
18880or %l7, %l0, %l0
18881srlx %l0, 1, %l0
18882
18883
18884P1312: !_ST_BINIT [2] (maybe <- 0x800082) (Int)
18885wr %g0, 0xe2, %asi
18886stwa %l4, [%i0 + 12] %asi
18887add %l4, 1, %l4
18888
18889P1313: !_MEMBAR (Int)
18890membar #StoreLoad
18891
18892P1314: !_DWST_BINIT [20] (maybe <- 0x800083) (Int)
18893wr %g0, 0xe2, %asi
18894sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
18895sub %i0, %i2, %i2
18896mov %l4, %l7
18897stxa %l7, [%i2 + 8] %asi
18898add %l4, 1, %l4
18899
18900P1315: !_MEMBAR (Int)
18901membar #StoreLoad
18902
18903P1316: !_DWST [14] (maybe <- 0x800084) (Int)
18904sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
18905add %i0, %i3, %i3
18906mov %l4, %l6
18907stx %l6, [%i3 + 8]
18908add %l4, 1, %l4
18909
18910P1317: !_LDD [15] (Int)
18911sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
18912sub %i0, %i2, %i2
18913ldd [%i2 + 0], %l6
18914! move %l6(lower) -> %o0(upper)
18915sllx %l6, 32, %o0
18916! move %l7(lower) -> %o0(lower)
18917or %l7, %o0, %o0
18918
18919P1318: !_MEMBAR (FP)
18920
18921P1319: !_BSTC [19] (maybe <- 0x40000062) (FP)
18922wr %g0, 0xe0, %asi
18923sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
18924sub %i0, %i3, %i3
18925! preparing store val #0, next val will be in f32
18926fmovs %f16, %f20
18927fadds %f16, %f17, %f16
18928! preparing store val #1, next val will be in f33
18929fmovs %f16, %f21
18930fadds %f16, %f17, %f16
18931! preparing store val #2, next val will be in f35
18932fmovd %f20, %f32
18933fmovs %f16, %f21
18934fadds %f16, %f17, %f16
18935fmovd %f20, %f34
18936membar #Sync
18937stda %f32, [%i3 + 0 ] %asi
18938
18939P1320: !_MEMBAR (FP)
18940membar #StoreLoad
18941
18942P1321: !_BLD [5] (FP)
18943!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
18944!Logical addr: 5
18945
18946sethi %hi(0x200000), %o5
18947sub %i1, %o5, %i1
18948wr %g0, 0xf0, %asi
18949ldda [%i1 + 0] %asi, %f32
18950membar #Sync
18951! 3 addresses covered
18952fmovd %f32, %f12
18953fmovd %f34, %f18
18954fmovs %f19, %f14
18955
18956P1322: !_MEMBAR (FP)
18957
18958P1323: !_BSTC [15] (maybe <- 0x40000065) (FP)
18959wr %g0, 0xe0, %asi
18960! preparing store val #0, next val will be in f32
18961fmovs %f16, %f20
18962fadds %f16, %f17, %f16
18963! preparing store val #1, next val will be in f33
18964fmovs %f16, %f21
18965fadds %f16, %f17, %f16
18966! preparing store val #2, next val will be in f35
18967fmovd %f20, %f32
18968fmovs %f16, %f21
18969fadds %f16, %f17, %f16
18970fmovd %f20, %f34
18971membar #Sync
18972stda %f32, [%i2 + 0 ] %asi
18973
18974P1324: !_MEMBAR (FP)
18975membar #StoreLoad
18976
18977P1325: !_BLD [17] (FP)
18978wr %g0, 0xf0, %asi
18979ldda [%i2 + 0] %asi, %f32
18980membar #Sync
18981! 3 addresses covered
18982fmovd %f32, %f18
18983fmovs %f18, %f15
18984!---- flushing fp results buffer to %f30 ----
18985fmovd %f0, %f30
18986fmovd %f2, %f30
18987fmovd %f4, %f30
18988fmovd %f6, %f30
18989fmovd %f8, %f30
18990fmovd %f10, %f30
18991fmovd %f12, %f30
18992fmovd %f14, %f30
18993!--
18994fmovs %f19, %f0
18995fmovd %f34, %f18
18996fmovs %f19, %f1
18997
18998P1326: !_MEMBAR (FP)
18999
19000P1327: !_ST_BINIT [1] (maybe <- 0x800085) (Int)
19001wr %g0, 0xe2, %asi
19002stwa %l4, [%i0 + 4] %asi
19003add %l4, 1, %l4
19004
19005P1328: !_MEMBAR (Int)
19006membar #StoreLoad
19007
19008P1329: !_DWST [14] (maybe <- 0x800086) (Int)
19009sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
19010add %i0, %i2, %i2
19011mov %l4, %l7
19012stx %l7, [%i2 + 8]
19013add %l4, 1, %l4
19014
19015P1330: !_CASX [4] (maybe <- 0x800087) (Int)
19016ldx [%i1], %o1
19017! move %o1(upper) -> %o1(upper)
19018! move %o1(lower) -> %o1(lower)
19019mov %o1, %l6
19020sllx %l4, 32, %o2
19021add %l4, 1, %l4
19022or %l4, %o2, %o2
19023casx [%i1], %l6, %o2
19024! move %o2(upper) -> %o2(upper)
19025! move %o2(lower) -> %o2(lower)
19026add %l4, 1, %l4
19027
19028P1331: !_ST [21] (maybe <- 0x800089) (Int)
19029sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
19030sub %i0, %i3, %i3
19031stw %l4, [%i3 + 0 ]
19032add %l4, 1, %l4
19033
19034P1332: !_CAS [21] (maybe <- 0x80008a) (Int)
19035lduw [%i3], %o3
19036mov %o3, %l3
19037! move %l3(lower) -> %o3(upper)
19038sllx %l3, 32, %o3
19039mov %l4, %o5
19040cas [%i3], %l3, %o5
19041! move %o5(lower) -> %o3(lower)
19042srl %o5, 0, %l3
19043or %l3, %o3, %o3
19044add %l4, 1, %l4
19045
19046P1333: !_SWAP [11] (maybe <- 0x80008b) (Int) (Branch target of P1427)
19047sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
19048add %i0, %i2, %i2
19049mov %l4, %o4
19050swap [%i2 + 12], %o4
19051! move %o4(lower) -> %o4(upper)
19052sllx %o4, 32, %o4
19053add %l4, 1, %l4
19054ba P1334
19055nop
19056
19057TARGET1427:
19058ba RET1427
19059nop
19060
19061
19062P1334: !_DWLD [11] (FP) (CBR)
19063ldd [%i2 + 8], %f2
19064! 1 addresses covered
19065fmovs %f3, %f2
19066
19067! cbranch
19068andcc %l0, 1, %g0
19069be,pt %xcc, TARGET1334
19070nop
19071RET1334:
19072
19073! lfsr step begin
19074srlx %l0, 1, %o5
19075xnor %o5, %l0, %o5
19076sllx %o5, 63, %o5
19077or %o5, %l0, %l0
19078srlx %l0, 1, %l0
19079
19080
19081P1335: !_LD [3] (Int)
19082lduw [%i1 + 0], %l6
19083! move %l6(lower) -> %o4(lower)
19084or %l6, %o4, %o4
19085!---- flushing int results buffer----
19086mov %o0, %l5
19087mov %o1, %l5
19088mov %o2, %l5
19089mov %o3, %l5
19090mov %o4, %l5
19091
19092P1336: !_REPLACEMENT [15] (Int)
19093sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
19094sub %i0, %i3, %i3
19095sethi %hi(0x20000), %l7
19096ld [%i3+0], %l3
19097st %l3, [%i3+0]
19098add %i3, %l7, %o5
19099ld [%o5+0], %l3
19100st %l3, [%o5+0]
19101add %o5, %l7, %o5
19102ld [%o5+0], %l3
19103st %l3, [%o5+0]
19104add %o5, %l7, %o5
19105ld [%o5+0], %l3
19106st %l3, [%o5+0]
19107add %o5, %l7, %o5
19108ld [%o5+0], %l3
19109st %l3, [%o5+0]
19110add %o5, %l7, %o5
19111ld [%o5+0], %l3
19112st %l3, [%o5+0]
19113add %o5, %l7, %o5
19114ld [%o5+0], %l3
19115st %l3, [%o5+0]
19116add %o5, %l7, %o5
19117ld [%o5+0], %l3
19118st %l3, [%o5+0]
19119
19120P1337: !_CAS [8] (maybe <- 0x80008c) (Int)
19121sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
19122sub %i0, %i2, %i2
19123add %i2, 12, %l7
19124lduw [%l7], %o0
19125mov %o0, %l6
19126! move %l6(lower) -> %o0(upper)
19127sllx %l6, 32, %o0
19128mov %l4, %l3
19129cas [%l7], %l6, %l3
19130! move %l3(lower) -> %o0(lower)
19131srl %l3, 0, %l6
19132or %l6, %o0, %o0
19133add %l4, 1, %l4
19134
19135P1338: !_DWST_BINIT [15] (maybe <- 0x80008d) (Int)
19136wr %g0, 0xe2, %asi
19137sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
19138sub %i0, %i3, %i3
19139sllx %l4, 32, %l6
19140add %l4, 1, %l4
19141or %l6, %l4, %l6
19142stxa %l6, [%i3 + 0] %asi
19143add %l4, 1, %l4
19144
19145P1339: !_MEMBAR (Int)
19146membar #StoreLoad
19147
19148P1340: !_DWST [5] (maybe <- 0x40000068) (FP)
19149! preparing store val #0, next val will be in f21
19150fmovs %f16, %f21
19151fadds %f16, %f17, %f16
19152std %f20, [%i1 + 8]
19153
19154P1341: !_SWAP [17] (maybe <- 0x80008f) (Int)
19155mov %l4, %o1
19156swap [%i3 + 12], %o1
19157! move %o1(lower) -> %o1(upper)
19158sllx %o1, 32, %o1
19159add %l4, 1, %l4
19160
19161P1342: !_DWST_BINIT [22] (maybe <- 0x800090) (Int)
19162wr %g0, 0xe2, %asi
19163sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
19164sub %i0, %i2, %i2
19165sllx %l4, 32, %l7
19166add %l4, 1, %l4
19167or %l7, %l4, %l7
19168stxa %l7, [%i2 + 0] %asi
19169add %l4, 1, %l4
19170
19171P1343: !_MEMBAR (Int)
19172membar #StoreLoad
19173
19174P1344: !_LD [11] (Int)
19175sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
19176add %i0, %i3, %i3
19177lduw [%i3 + 12], %l7
19178! move %l7(lower) -> %o1(lower)
19179or %l7, %o1, %o1
19180
19181P1345: !_MEMBAR (FP)
19182membar #StoreLoad
19183
19184P1346: !_BLD [11] (FP)
19185wr %g0, 0xf0, %asi
19186ldda [%i3 + 0] %asi, %f32
19187membar #Sync
19188! 3 addresses covered
19189fmovd %f32, %f18
19190fmovs %f18, %f3
19191fmovs %f19, %f4
19192fmovd %f34, %f18
19193fmovs %f19, %f5
19194
19195P1347: !_MEMBAR (FP)
19196
19197P1348: !_LD [0] (Int)
19198lduw [%i0 + 0], %o2
19199! move %o2(lower) -> %o2(upper)
19200sllx %o2, 32, %o2
19201
19202P1349: !_LDD [7] (Int)
19203sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
19204sub %i0, %i2, %i2
19205ldd [%i2 + 0], %l6
19206! move %l6(lower) -> %o2(lower)
19207or %l6, %o2, %o2
19208! move %l7(lower) -> %o3(upper)
19209sllx %l7, 32, %o3
19210
19211P1350: !_CAS [2] (maybe <- 0x800092) (Int)
19212add %i0, 12, %l6
19213lduw [%l6], %o5
19214mov %o5, %l3
19215! move %l3(lower) -> %o3(lower)
19216or %l3, %o3, %o3
19217mov %l4, %o4
19218cas [%l6], %l3, %o4
19219! move %o4(lower) -> %o4(upper)
19220sllx %o4, 32, %o4
19221add %l4, 1, %l4
19222
19223P1351: !_MEMBAR (FP) (CBR)
19224
19225! cbranch
19226andcc %l0, 1, %g0
19227be,pn %xcc, TARGET1351
19228nop
19229RET1351:
19230
19231! lfsr step begin
19232srlx %l0, 1, %l3
19233xnor %l3, %l0, %l3
19234sllx %l3, 63, %l3
19235or %l3, %l0, %l0
19236srlx %l0, 1, %l0
19237
19238
19239P1352: !_BSTC [19] (maybe <- 0x40000069) (FP)
19240wr %g0, 0xe0, %asi
19241sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
19242sub %i0, %i3, %i3
19243! preparing store val #0, next val will be in f32
19244fmovs %f16, %f20
19245fadds %f16, %f17, %f16
19246! preparing store val #1, next val will be in f33
19247fmovs %f16, %f21
19248fadds %f16, %f17, %f16
19249! preparing store val #2, next val will be in f35
19250fmovd %f20, %f32
19251fmovs %f16, %f21
19252fadds %f16, %f17, %f16
19253fmovd %f20, %f34
19254membar #Sync
19255stda %f32, [%i3 + 0 ] %asi
19256
19257P1353: !_MEMBAR (FP)
19258membar #StoreLoad
19259
19260P1354: !_SWAP [15] (maybe <- 0x800093) (Int)
19261sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
19262sub %i0, %i2, %i2
19263mov %l4, %l7
19264swap [%i2 + 0], %l7
19265! move %l7(lower) -> %o4(lower)
19266srl %l7, 0, %l3
19267or %l3, %o4, %o4
19268!---- flushing int results buffer----
19269mov %o0, %l5
19270mov %o1, %l5
19271mov %o2, %l5
19272mov %o3, %l5
19273mov %o4, %l5
19274add %l4, 1, %l4
19275
19276P1355: !_SWAP [23] (maybe <- 0x800094) (Int)
19277sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
19278sub %i0, %i3, %i3
19279mov %l4, %o0
19280swap [%i3 + 12], %o0
19281! move %o0(lower) -> %o0(upper)
19282sllx %o0, 32, %o0
19283add %l4, 1, %l4
19284
19285P1356: !_DWLD [8] (Int)
19286sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
19287sub %i0, %i2, %i2
19288ldx [%i2 + 8], %o5
19289! move %o5(lower) -> %o0(lower)
19290srl %o5, 0, %l7
19291or %l7, %o0, %o0
19292
19293P1357: !_PREFETCH [10] (Int)
19294sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
19295add %i0, %i3, %i3
19296prefetch [%i3 + 4], 4
19297
19298P1358: !_MEMBAR (FP)
19299
19300P1359: !_BST [12] (maybe <- 0x4000006c) (FP)
19301wr %g0, 0xf0, %asi
19302sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
19303add %i0, %i2, %i2
19304! preparing store val #0, next val will be in f32
19305fmovs %f16, %f20
19306fadds %f16, %f17, %f16
19307! preparing store val #1, next val will be in f33
19308fmovs %f16, %f21
19309fadds %f16, %f17, %f16
19310! preparing store val #2, next val will be in f35
19311fmovd %f20, %f32
19312fmovs %f16, %f21
19313fadds %f16, %f17, %f16
19314fmovd %f20, %f34
19315membar #Sync
19316stda %f32, [%i2 + 0 ] %asi
19317
19318P1360: !_MEMBAR (FP)
19319membar #StoreLoad
19320
19321P1361: !_LDD [22] (Int) (LE)
19322wr %g0, 0x88, %asi
19323sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
19324sub %i0, %i3, %i3
19325ldda [%i3 + 0] %asi, %l6
19326! move %l6(lower) -> %o1(upper)
19327sllx %l6, 32, %o1
19328! move %l7(lower) -> %o1(lower)
19329or %l7, %o1, %o1
19330
19331P1362: !_ST [6] (maybe <- 0x800095) (Int)
19332sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
19333sub %i0, %i2, %i2
19334stw %l4, [%i2 + 0 ]
19335add %l4, 1, %l4
19336
19337P1363: !_PREFETCH [3] (Int)
19338prefetch [%i1 + 0], 31
19339
19340P1364: !_DWST_BINIT [15] (maybe <- 0x800096) (Int)
19341wr %g0, 0xe2, %asi
19342sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
19343sub %i0, %i3, %i3
19344sllx %l4, 32, %o5
19345add %l4, 1, %l4
19346or %o5, %l4, %o5
19347stxa %o5, [%i3 + 0] %asi
19348add %l4, 1, %l4
19349
19350P1365: !_MEMBAR (Int)
19351membar #StoreLoad
19352
19353P1366: !_DWLD [4] (Int)
19354ldx [%i1 + 0], %o2
19355! move %o2(upper) -> %o2(upper)
19356! move %o2(lower) -> %o2(lower)
19357
19358P1367: !_CAS [1] (maybe <- 0x800098) (Int)
19359add %i0, 4, %l6
19360lduw [%l6], %o3
19361mov %o3, %l3
19362! move %l3(lower) -> %o3(upper)
19363sllx %l3, 32, %o3
19364mov %l4, %o5
19365cas [%l6], %l3, %o5
19366! move %o5(lower) -> %o3(lower)
19367srl %o5, 0, %l3
19368or %l3, %o3, %o3
19369add %l4, 1, %l4
19370
19371P1368: !_DWLD [15] (FP)
19372ldd [%i3 + 0], %f6
19373! 2 addresses covered
19374
19375P1369: !_ST_BINIT [11] (maybe <- 0x800099) (Int)
19376wr %g0, 0xe2, %asi
19377sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
19378add %i0, %i2, %i2
19379stwa %l4, [%i2 + 12] %asi
19380add %l4, 1, %l4
19381
19382P1370: !_MEMBAR (Int)
19383
19384P1371: !_BST [14] (maybe <- 0x4000006f) (FP)
19385wr %g0, 0xf0, %asi
19386sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
19387add %i0, %i3, %i3
19388! preparing store val #0, next val will be in f32
19389fmovs %f16, %f20
19390fadds %f16, %f17, %f16
19391! preparing store val #1, next val will be in f33
19392fmovs %f16, %f21
19393fadds %f16, %f17, %f16
19394! preparing store val #2, next val will be in f35
19395fmovd %f20, %f32
19396fmovs %f16, %f21
19397fadds %f16, %f17, %f16
19398fmovd %f20, %f34
19399membar #Sync
19400stda %f32, [%i3 + 0 ] %asi
19401
19402P1372: !_MEMBAR (FP)
19403membar #StoreLoad
19404
19405P1373: !_CAS [6] (maybe <- 0x80009a) (Int)
19406sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
19407sub %i0, %i2, %i2
19408lduw [%i2], %o4
19409mov %o4, %l7
19410! move %l7(lower) -> %o4(upper)
19411sllx %l7, 32, %o4
19412mov %l4, %l6
19413cas [%i2], %l7, %l6
19414! move %l6(lower) -> %o4(lower)
19415srl %l6, 0, %l7
19416or %l7, %o4, %o4
19417!---- flushing int results buffer----
19418mov %o0, %l5
19419mov %o1, %l5
19420mov %o2, %l5
19421mov %o3, %l5
19422mov %o4, %l5
19423add %l4, 1, %l4
19424
19425P1374: !_SWAP [15] (maybe <- 0x80009b) (Int)
19426sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
19427sub %i0, %i3, %i3
19428mov %l4, %o0
19429swap [%i3 + 0], %o0
19430! move %o0(lower) -> %o0(upper)
19431sllx %o0, 32, %o0
19432add %l4, 1, %l4
19433
19434P1375: !_REPLACEMENT [23] (Int)
19435sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
19436sub %i0, %i2, %i2
19437sethi %hi(0x20000), %l6
19438ld [%i2+12], %o5
19439st %o5, [%i2+12]
19440add %i2, %l6, %l7
19441ld [%l7+12], %o5
19442st %o5, [%l7+12]
19443add %l7, %l6, %l7
19444ld [%l7+12], %o5
19445st %o5, [%l7+12]
19446add %l7, %l6, %l7
19447ld [%l7+12], %o5
19448st %o5, [%l7+12]
19449add %l7, %l6, %l7
19450ld [%l7+12], %o5
19451st %o5, [%l7+12]
19452add %l7, %l6, %l7
19453ld [%l7+12], %o5
19454st %o5, [%l7+12]
19455add %l7, %l6, %l7
19456ld [%l7+12], %o5
19457st %o5, [%l7+12]
19458add %l7, %l6, %l7
19459ld [%l7+12], %o5
19460st %o5, [%l7+12]
19461
19462P1376: !_ST_BINIT [22] (maybe <- 0x80009c) (Int)
19463wr %g0, 0xe2, %asi
19464sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
19465sub %i0, %i3, %i3
19466stwa %l4, [%i3 + 4] %asi
19467add %l4, 1, %l4
19468
19469P1377: !_MEMBAR (Int)
19470membar #StoreLoad
19471
19472P1378: !_DWST_BINIT [21] (maybe <- 0x80009d) (Int)
19473wr %g0, 0xe2, %asi
19474sllx %l4, 32, %o5
19475add %l4, 1, %l4
19476or %o5, %l4, %o5
19477stxa %o5, [%i3 + 0] %asi
19478add %l4, 1, %l4
19479
19480P1379: !_MEMBAR (Int)
19481membar #StoreLoad
19482
19483P1380: !_DWLD [9] (Int)
19484sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
19485add %i0, %i2, %i2
19486ldx [%i2 + 0], %o5
19487! move %o5(upper) -> %o0(lower)
19488srlx %o5, 32, %l7
19489or %l7, %o0, %o0
19490! move %o5(lower) -> %o1(upper)
19491sllx %o5, 32, %o1
19492
19493P1381: !_ST [0] (maybe <- 0x80009f) (Int)
19494stw %l4, [%i0 + 0 ]
19495add %l4, 1, %l4
19496
19497P1382: !_ST_BINIT [22] (maybe <- 0x8000a0) (Int)
19498wr %g0, 0xe2, %asi
19499stwa %l4, [%i3 + 4] %asi
19500add %l4, 1, %l4
19501
19502P1383: !_MEMBAR (Int)
19503membar #StoreLoad
19504
19505P1384: !_ST [18] (maybe <- 0x8000a1) (Int)
19506sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
19507sub %i0, %i3, %i3
19508stw %l4, [%i3 + 0 ]
19509add %l4, 1, %l4
19510
19511P1385: !_MEMBAR (FP)
19512
19513P1386: !_BSTC [0] (maybe <- 0x40000072) (FP)
19514wr %g0, 0xe0, %asi
19515! preparing store val #0, next val will be in f32
19516fmovs %f16, %f20
19517fadds %f16, %f17, %f16
19518! preparing store val #1, next val will be in f33
19519fmovs %f16, %f21
19520fadds %f16, %f17, %f16
19521! preparing store val #2, next val will be in f35
19522fmovd %f20, %f32
19523fmovs %f16, %f21
19524fadds %f16, %f17, %f16
19525fmovd %f20, %f34
19526membar #Sync
19527stda %f32, [%i0 + 0 ] %asi
19528
19529P1387: !_MEMBAR (FP)
19530membar #StoreLoad
19531
19532P1388: !_ST [12] (maybe <- 0x8000a2) (Int)
19533sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
19534add %i0, %i2, %i2
19535stw %l4, [%i2 + 0 ]
19536add %l4, 1, %l4
19537
19538P1389: !_MEMBAR (FP)
19539
19540P1390: !_BST [0] (maybe <- 0x40000075) (FP)
19541wr %g0, 0xf0, %asi
19542! preparing store val #0, next val will be in f32
19543fmovs %f16, %f20
19544fadds %f16, %f17, %f16
19545! preparing store val #1, next val will be in f33
19546fmovs %f16, %f21
19547fadds %f16, %f17, %f16
19548! preparing store val #2, next val will be in f35
19549fmovd %f20, %f32
19550fmovs %f16, %f21
19551fadds %f16, %f17, %f16
19552fmovd %f20, %f34
19553membar #Sync
19554stda %f32, [%i0 + 0 ] %asi
19555
19556P1391: !_MEMBAR (FP)
19557membar #StoreLoad
19558
19559P1392: !_LD [2] (Int)
19560lduw [%i0 + 12], %l3
19561! move %l3(lower) -> %o1(lower)
19562or %l3, %o1, %o1
19563
19564P1393: !_CAS [15] (maybe <- 0x8000a3) (Int)
19565sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
19566sub %i0, %i3, %i3
19567lduw [%i3], %o2
19568mov %o2, %l6
19569! move %l6(lower) -> %o2(upper)
19570sllx %l6, 32, %o2
19571mov %l4, %l3
19572cas [%i3], %l6, %l3
19573! move %l3(lower) -> %o2(lower)
19574srl %l3, 0, %l6
19575or %l6, %o2, %o2
19576add %l4, 1, %l4
19577
19578P1394: !_LD [12] (Int)
19579lduw [%i2 + 0], %o3
19580! move %o3(lower) -> %o3(upper)
19581sllx %o3, 32, %o3
19582
19583P1395: !_MEMBAR (FP)
19584membar #StoreLoad
19585
19586P1396: !_BLD [8] (FP)
19587wr %g0, 0xf0, %asi
19588sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
19589sub %i0, %i2, %i2
19590ldda [%i2 + 0] %asi, %f32
19591membar #Sync
19592! 3 addresses covered
19593fmovd %f32, %f8
19594fmovd %f34, %f18
19595fmovs %f19, %f10
19596
19597P1397: !_MEMBAR (FP)
19598
19599P1398: !_LDD [6] (Int)
19600ldd [%i2 + 0], %l6
19601! move %l6(lower) -> %o3(lower)
19602or %l6, %o3, %o3
19603! move %l7(lower) -> %o4(upper)
19604sllx %l7, 32, %o4
19605
19606P1399: !_MEMBAR (FP)
19607membar #StoreLoad
19608
19609P1400: !_BLD [21] (FP)
19610wr %g0, 0xf0, %asi
19611sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
19612sub %i0, %i3, %i3
19613ldda [%i3 + 0] %asi, %f32
19614membar #Sync
19615! 3 addresses covered
19616fmovd %f32, %f18
19617fmovs %f18, %f11
19618fmovs %f19, %f12
19619fmovd %f34, %f18
19620fmovs %f19, %f13
19621
19622P1401: !_MEMBAR (FP)
19623
19624P1402: !_SWAP [10] (maybe <- 0x8000a4) (Int)
19625sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
19626add %i0, %i2, %i2
19627mov %l4, %l7
19628swap [%i2 + 4], %l7
19629! move %l7(lower) -> %o4(lower)
19630srl %l7, 0, %l3
19631or %l3, %o4, %o4
19632!---- flushing int results buffer----
19633mov %o0, %l5
19634mov %o1, %l5
19635mov %o2, %l5
19636mov %o3, %l5
19637mov %o4, %l5
19638add %l4, 1, %l4
19639
19640P1403: !_LDD [18] (Int)
19641sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
19642sub %i0, %i3, %i3
19643ldd [%i3 + 0], %l6
19644! move %l6(lower) -> %o0(upper)
19645sllx %l6, 32, %o0
19646! move %l7(lower) -> %o0(lower)
19647or %l7, %o0, %o0
19648
19649P1404: !_CAS [6] (maybe <- 0x8000a5) (Int)
19650sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
19651sub %i0, %i2, %i2
19652lduw [%i2], %o1
19653mov %o1, %l3
19654! move %l3(lower) -> %o1(upper)
19655sllx %l3, 32, %o1
19656mov %l4, %o5
19657cas [%i2], %l3, %o5
19658! move %o5(lower) -> %o1(lower)
19659srl %o5, 0, %l3
19660or %l3, %o1, %o1
19661add %l4, 1, %l4
19662
19663P1405: !_DWST_BINIT [1] (maybe <- 0x8000a6) (Int)
19664wr %g0, 0xe2, %asi
19665sllx %l4, 32, %l3
19666add %l4, 1, %l4
19667or %l3, %l4, %l3
19668stxa %l3, [%i0 + 0] %asi
19669add %l4, 1, %l4
19670
19671P1406: !_MEMBAR (Int)
19672membar #StoreLoad
19673
19674P1407: !_PREFETCH [1] (Int)
19675prefetch [%i0 + 4], 22
19676
19677P1408: !_ST [16] (maybe <- 0x8000a8) (Int)
19678sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
19679sub %i0, %i3, %i3
19680stw %l4, [%i3 + 4 ]
19681add %l4, 1, %l4
19682
19683P1409: !_DWST [3] (maybe <- 0x8000a9) (Int) (CBR)
19684sllx %l4, 32, %l7
19685add %l4, 1, %l4
19686or %l7, %l4, %l7
19687stx %l7, [%i1 + 0]
19688add %l4, 1, %l4
19689
19690! cbranch
19691andcc %l0, 1, %g0
19692be,pn %xcc, TARGET1409
19693nop
19694RET1409:
19695
19696! lfsr step begin
19697srlx %l0, 1, %l6
19698xnor %l6, %l0, %l6
19699sllx %l6, 63, %l6
19700or %l6, %l0, %l0
19701srlx %l0, 1, %l0
19702
19703
19704P1410: !_MEMBAR (FP)
19705membar #StoreLoad
19706
19707P1411: !_BLD [22] (FP)
19708wr %g0, 0xf0, %asi
19709sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
19710sub %i0, %i2, %i2
19711ldda [%i2 + 0] %asi, %f32
19712membar #Sync
19713! 3 addresses covered
19714fmovd %f32, %f14
19715!---- flushing fp results buffer to %f30 ----
19716fmovd %f0, %f30
19717fmovd %f2, %f30
19718fmovd %f4, %f30
19719fmovd %f6, %f30
19720fmovd %f8, %f30
19721fmovd %f10, %f30
19722fmovd %f12, %f30
19723fmovd %f14, %f30
19724!--
19725fmovd %f34, %f18
19726fmovs %f19, %f0
19727
19728P1412: !_MEMBAR (FP)
19729
19730P1413: !_DWST [7] (maybe <- 0x8000ab) (Int)
19731sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
19732sub %i0, %i3, %i3
19733sllx %l4, 32, %l7
19734add %l4, 1, %l4
19735or %l7, %l4, %l7
19736stx %l7, [%i3 + 0]
19737add %l4, 1, %l4
19738
19739P1414: !_SWAP [18] (maybe <- 0x8000ad) (Int)
19740sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
19741sub %i0, %i2, %i2
19742mov %l4, %o2
19743swap [%i2 + 0], %o2
19744! move %o2(lower) -> %o2(upper)
19745sllx %o2, 32, %o2
19746add %l4, 1, %l4
19747
19748P1415: !_ST [1] (maybe <- 0x8000ae) (Int)
19749stw %l4, [%i0 + 4 ]
19750add %l4, 1, %l4
19751
19752P1416: !_ST [12] (maybe <- 0x40000078) (FP)
19753sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
19754add %i0, %i3, %i3
19755! preparing store val #0, next val will be in f20
19756fmovs %f16, %f20
19757fadds %f16, %f17, %f16
19758st %f20, [%i3 + 0 ]
19759
19760P1417: !_ST [22] (maybe <- 0x8000af) (Int)
19761sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
19762sub %i0, %i2, %i2
19763stw %l4, [%i2 + 4 ]
19764add %l4, 1, %l4
19765
19766P1418: !_PREFETCH [10] (Int)
19767sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
19768add %i0, %i3, %i3
19769prefetch [%i3 + 4], 21
19770
19771P1419: !_DWLD [0] (Int)
19772ldx [%i0 + 0], %l7
19773! move %l7(upper) -> %o2(lower)
19774srlx %l7, 32, %l6
19775or %l6, %o2, %o2
19776! move %l7(lower) -> %o3(upper)
19777sllx %l7, 32, %o3
19778
19779P1420: !_CAS [14] (maybe <- 0x8000b0) (Int)
19780sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
19781add %i0, %i2, %i2
19782add %i2, 12, %l3
19783lduw [%l3], %l7
19784mov %l7, %o5
19785! move %o5(lower) -> %o3(lower)
19786or %o5, %o3, %o3
19787mov %l4, %o4
19788cas [%l3], %o5, %o4
19789! move %o4(lower) -> %o4(upper)
19790sllx %o4, 32, %o4
19791add %l4, 1, %l4
19792
19793P1421: !_MEMBAR (FP)
19794
19795P1422: !_BSTC [8] (maybe <- 0x40000079) (FP)
19796wr %g0, 0xe0, %asi
19797sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
19798sub %i0, %i3, %i3
19799! preparing store val #0, next val will be in f32
19800fmovs %f16, %f20
19801fadds %f16, %f17, %f16
19802! preparing store val #1, next val will be in f33
19803fmovs %f16, %f21
19804fadds %f16, %f17, %f16
19805! preparing store val #2, next val will be in f35
19806fmovd %f20, %f32
19807fmovs %f16, %f21
19808fadds %f16, %f17, %f16
19809fmovd %f20, %f34
19810membar #Sync
19811stda %f32, [%i3 + 0 ] %asi
19812
19813P1423: !_MEMBAR (FP)
19814membar #StoreLoad
19815
19816P1424: !_CAS [9] (maybe <- 0x8000b1) (Int)
19817sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
19818add %i0, %i2, %i2
19819lduw [%i2], %l6
19820mov %l6, %l7
19821! move %l7(lower) -> %o4(lower)
19822or %l7, %o4, %o4
19823!---- flushing int results buffer----
19824mov %o0, %l5
19825mov %o1, %l5
19826mov %o2, %l5
19827mov %o3, %l5
19828mov %o4, %l5
19829mov %l4, %o0
19830cas [%i2], %l7, %o0
19831! move %o0(lower) -> %o0(upper)
19832sllx %o0, 32, %o0
19833add %l4, 1, %l4
19834
19835P1425: !_MEMBAR (FP)
19836
19837P1426: !_BST [14] (maybe <- 0x4000007c) (FP)
19838wr %g0, 0xf0, %asi
19839sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
19840add %i0, %i3, %i3
19841! preparing store val #0, next val will be in f32
19842fmovs %f16, %f20
19843fadds %f16, %f17, %f16
19844! preparing store val #1, next val will be in f33
19845fmovs %f16, %f21
19846fadds %f16, %f17, %f16
19847! preparing store val #2, next val will be in f35
19848fmovd %f20, %f32
19849fmovs %f16, %f21
19850fadds %f16, %f17, %f16
19851fmovd %f20, %f34
19852membar #Sync
19853stda %f32, [%i3 + 0 ] %asi
19854
19855P1427: !_MEMBAR (FP) (CBR)
19856membar #StoreLoad
19857
19858! cbranch
19859andcc %l0, 1, %g0
19860be,pt %xcc, TARGET1427
19861nop
19862RET1427:
19863
19864! lfsr step begin
19865srlx %l0, 1, %l6
19866xnor %l6, %l0, %l6
19867sllx %l6, 63, %l6
19868or %l6, %l0, %l0
19869srlx %l0, 1, %l0
19870
19871
19872P1428: !_ST_BINIT [17] (maybe <- 0x8000b2) (Int)
19873wr %g0, 0xe2, %asi
19874sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
19875sub %i0, %i2, %i2
19876stwa %l4, [%i2 + 12] %asi
19877add %l4, 1, %l4
19878
19879P1429: !_MEMBAR (Int)
19880membar #StoreLoad
19881
19882P1430: !_DWLD [19] (Int)
19883sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
19884sub %i0, %i3, %i3
19885ldx [%i3 + 0], %l7
19886! move %l7(upper) -> %o0(lower)
19887srlx %l7, 32, %l6
19888or %l6, %o0, %o0
19889! move %l7(lower) -> %o1(upper)
19890sllx %l7, 32, %o1
19891
19892P1431: !_CASX [11] (maybe <- 0x8000b3) (Int)
19893sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
19894add %i0, %i2, %i2
19895add %i2, 8, %l3
19896ldx [%l3], %l7
19897! move %l7(upper) -> %o1(lower)
19898srlx %l7, 32, %o5
19899or %o5, %o1, %o1
19900! move %l7(lower) -> %o2(upper)
19901sllx %l7, 32, %o2
19902mov %l7, %o5
19903mov %l4, %l7
19904casx [%l3], %o5, %l7
19905! move %l7(upper) -> %o2(lower)
19906srlx %l7, 32, %o5
19907or %o5, %o2, %o2
19908! move %l7(lower) -> %o3(upper)
19909sllx %l7, 32, %o3
19910add %l4, 1, %l4
19911
19912P1432: !_DWLD [9] (FP)
19913ldd [%i2 + 0], %f18
19914! 2 addresses covered
19915fmovs %f18, %f1
19916fmovs %f19, %f2
19917
19918P1433: !_MEMBAR (FP)
19919
19920P1434: !_BST [11] (maybe <- 0x4000007f) (FP)
19921wr %g0, 0xf0, %asi
19922! preparing store val #0, next val will be in f32
19923fmovs %f16, %f20
19924fadds %f16, %f17, %f16
19925! preparing store val #1, next val will be in f33
19926fmovs %f16, %f21
19927fadds %f16, %f17, %f16
19928! preparing store val #2, next val will be in f35
19929fmovd %f20, %f32
19930fmovs %f16, %f21
19931fadds %f16, %f17, %f16
19932fmovd %f20, %f34
19933membar #Sync
19934stda %f32, [%i2 + 0 ] %asi
19935
19936P1435: !_MEMBAR (FP)
19937membar #StoreLoad
19938
19939P1436: !_SWAP [4] (maybe <- 0x8000b4) (Int)
19940mov %l4, %l3
19941swap [%i1 + 4], %l3
19942! move %l3(lower) -> %o3(lower)
19943srl %l3, 0, %l7
19944or %l7, %o3, %o3
19945add %l4, 1, %l4
19946
19947P1437: !_DWLD [1] (Int)
19948ldx [%i0 + 0], %o4
19949! move %o4(upper) -> %o4(upper)
19950! move %o4(lower) -> %o4(lower)
19951!---- flushing int results buffer----
19952mov %o0, %l5
19953mov %o1, %l5
19954mov %o2, %l5
19955mov %o3, %l5
19956mov %o4, %l5
19957
19958P1438: !_ST [17] (maybe <- 0x8000b5) (Int)
19959sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
19960sub %i0, %i3, %i3
19961stw %l4, [%i3 + 12 ]
19962add %l4, 1, %l4
19963
19964P1439: !_REPLACEMENT [18] (Int)
19965sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
19966sub %i0, %i2, %i2
19967sethi %hi(0x20000), %l7
19968ld [%i2+0], %l3
19969st %l3, [%i2+0]
19970add %i2, %l7, %o5
19971ld [%o5+0], %l3
19972st %l3, [%o5+0]
19973add %o5, %l7, %o5
19974ld [%o5+0], %l3
19975st %l3, [%o5+0]
19976add %o5, %l7, %o5
19977ld [%o5+0], %l3
19978st %l3, [%o5+0]
19979add %o5, %l7, %o5
19980ld [%o5+0], %l3
19981st %l3, [%o5+0]
19982add %o5, %l7, %o5
19983ld [%o5+0], %l3
19984st %l3, [%o5+0]
19985add %o5, %l7, %o5
19986ld [%o5+0], %l3
19987st %l3, [%o5+0]
19988add %o5, %l7, %o5
19989ld [%o5+0], %l3
19990st %l3, [%o5+0]
19991
19992P1440: !_MEMBAR (FP)
19993membar #StoreLoad
19994
19995P1441: !_BLD [11] (FP)
19996wr %g0, 0xf0, %asi
19997sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
19998add %i0, %i3, %i3
19999ldda [%i3 + 0] %asi, %f32
20000membar #Sync
20001! 3 addresses covered
20002fmovd %f32, %f18
20003fmovs %f18, %f3
20004fmovs %f19, %f4
20005fmovd %f34, %f18
20006fmovs %f19, %f5
20007
20008P1442: !_MEMBAR (FP)
20009
20010P1443: !_BSTC [22] (maybe <- 0x40000082) (FP)
20011wr %g0, 0xe0, %asi
20012sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
20013sub %i0, %i2, %i2
20014! preparing store val #0, next val will be in f32
20015fmovs %f16, %f20
20016fadds %f16, %f17, %f16
20017! preparing store val #1, next val will be in f33
20018fmovs %f16, %f21
20019fadds %f16, %f17, %f16
20020! preparing store val #2, next val will be in f35
20021fmovd %f20, %f32
20022fmovs %f16, %f21
20023fadds %f16, %f17, %f16
20024fmovd %f20, %f34
20025membar #Sync
20026stda %f32, [%i2 + 0 ] %asi
20027
20028P1444: !_MEMBAR (FP)
20029
20030P1445: !_BST [20] (maybe <- 0x40000085) (FP)
20031wr %g0, 0xf0, %asi
20032sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
20033sub %i0, %i3, %i3
20034! preparing store val #0, next val will be in f32
20035fmovs %f16, %f20
20036fadds %f16, %f17, %f16
20037! preparing store val #1, next val will be in f33
20038fmovs %f16, %f21
20039fadds %f16, %f17, %f16
20040! preparing store val #2, next val will be in f35
20041fmovd %f20, %f32
20042fmovs %f16, %f21
20043fadds %f16, %f17, %f16
20044fmovd %f20, %f34
20045membar #Sync
20046stda %f32, [%i3 + 0 ] %asi
20047
20048P1446: !_MEMBAR (FP)
20049membar #StoreLoad
20050
20051P1447: !_PREFETCH [14] (Int)
20052sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
20053add %i0, %i2, %i2
20054prefetch [%i2 + 12], 20
20055
20056P1448: !_PREFETCH [17] (Int)
20057sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
20058sub %i0, %i3, %i3
20059prefetch [%i3 + 12], 0
20060
20061P1449: !_LDD [0] (Int)
20062ldd [%i0 + 0], %l6
20063! move %l6(lower) -> %o0(upper)
20064sllx %l6, 32, %o0
20065! move %l7(lower) -> %o0(lower)
20066or %l7, %o0, %o0
20067
20068P1450: !_DWST_BINIT [4] (maybe <- 0x8000b6) (Int)
20069wr %g0, 0xe2, %asi
20070sllx %l4, 32, %l3
20071add %l4, 1, %l4
20072or %l3, %l4, %l3
20073stxa %l3, [%i1 + 0] %asi
20074add %l4, 1, %l4
20075
20076P1451: !_MEMBAR (Int) (Branch target of P2003)
20077ba P1452
20078nop
20079
20080TARGET2003:
20081ba RET2003
20082nop
20083
20084
20085P1452: !_BST [8] (maybe <- 0x40000088) (FP)
20086wr %g0, 0xf0, %asi
20087sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
20088sub %i0, %i2, %i2
20089! preparing store val #0, next val will be in f32
20090fmovs %f16, %f20
20091fadds %f16, %f17, %f16
20092! preparing store val #1, next val will be in f33
20093fmovs %f16, %f21
20094fadds %f16, %f17, %f16
20095! preparing store val #2, next val will be in f35
20096fmovd %f20, %f32
20097fmovs %f16, %f21
20098fadds %f16, %f17, %f16
20099fmovd %f20, %f34
20100membar #Sync
20101stda %f32, [%i2 + 0 ] %asi
20102
20103P1453: !_MEMBAR (FP)
20104membar #StoreLoad
20105
20106P1454: !_SWAP [9] (maybe <- 0x8000b8) (Int)
20107sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
20108add %i0, %i3, %i3
20109mov %l4, %o1
20110swap [%i3 + 0], %o1
20111! move %o1(lower) -> %o1(upper)
20112sllx %o1, 32, %o1
20113add %l4, 1, %l4
20114
20115P1455: !_REPLACEMENT [1] (Int)
20116sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
20117sub %i0, %i2, %i2
20118sethi %hi(0x20000), %l6
20119ld [%i2+4], %o5
20120st %o5, [%i2+4]
20121add %i2, %l6, %l7
20122ld [%l7+4], %o5
20123st %o5, [%l7+4]
20124add %l7, %l6, %l7
20125ld [%l7+4], %o5
20126st %o5, [%l7+4]
20127add %l7, %l6, %l7
20128ld [%l7+4], %o5
20129st %o5, [%l7+4]
20130add %l7, %l6, %l7
20131ld [%l7+4], %o5
20132st %o5, [%l7+4]
20133add %l7, %l6, %l7
20134ld [%l7+4], %o5
20135st %o5, [%l7+4]
20136add %l7, %l6, %l7
20137ld [%l7+4], %o5
20138st %o5, [%l7+4]
20139add %l7, %l6, %l7
20140ld [%l7+4], %o5
20141st %o5, [%l7+4]
20142
20143P1456: !_MEMBAR (FP)
20144
20145P1457: !_BST [5] (maybe <- 0x4000008b) (FP)
20146wr %g0, 0xf0, %asi
20147! preparing store val #0, next val will be in f32
20148fmovs %f16, %f20
20149fadds %f16, %f17, %f16
20150! preparing store val #1, next val will be in f33
20151fmovs %f16, %f21
20152fadds %f16, %f17, %f16
20153! preparing store val #2, next val will be in f35
20154fmovd %f20, %f32
20155fmovs %f16, %f21
20156fadds %f16, %f17, %f16
20157fmovd %f20, %f34
20158membar #Sync
20159stda %f32, [%i1 + 0 ] %asi
20160
20161P1458: !_MEMBAR (FP) (CBR)
20162
20163! cbranch
20164andcc %l0, 1, %g0
20165be,pn %xcc, TARGET1458
20166nop
20167RET1458:
20168
20169! lfsr step begin
20170srlx %l0, 1, %o5
20171xnor %o5, %l0, %o5
20172sllx %o5, 63, %o5
20173or %o5, %l0, %l0
20174srlx %l0, 1, %l0
20175
20176
20177P1459: !_BST [1] (maybe <- 0x4000008e) (FP)
20178wr %g0, 0xf0, %asi
20179! preparing store val #0, next val will be in f32
20180fmovs %f16, %f20
20181fadds %f16, %f17, %f16
20182! preparing store val #1, next val will be in f33
20183fmovs %f16, %f21
20184fadds %f16, %f17, %f16
20185! preparing store val #2, next val will be in f35
20186fmovd %f20, %f32
20187fmovs %f16, %f21
20188fadds %f16, %f17, %f16
20189fmovd %f20, %f34
20190membar #Sync
20191stda %f32, [%i0 + 0 ] %asi
20192
20193P1460: !_MEMBAR (FP)
20194membar #StoreLoad
20195
20196P1461: !_LD [6] (Int)
20197sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
20198sub %i0, %i3, %i3
20199lduw [%i3 + 0], %l3
20200! move %l3(lower) -> %o1(lower)
20201or %l3, %o1, %o1
20202
20203P1462: !_MEMBAR (FP)
20204
20205P1463: !_BST [13] (maybe <- 0x40000091) (FP)
20206wr %g0, 0xf0, %asi
20207sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
20208add %i0, %i2, %i2
20209! preparing store val #0, next val will be in f32
20210fmovs %f16, %f20
20211fadds %f16, %f17, %f16
20212! preparing store val #1, next val will be in f33
20213fmovs %f16, %f21
20214fadds %f16, %f17, %f16
20215! preparing store val #2, next val will be in f35
20216fmovd %f20, %f32
20217fmovs %f16, %f21
20218fadds %f16, %f17, %f16
20219fmovd %f20, %f34
20220membar #Sync
20221stda %f32, [%i2 + 0 ] %asi
20222
20223P1464: !_MEMBAR (FP)
20224membar #StoreLoad
20225
20226P1465: !_DWST [9] (maybe <- 0x40000094) (FP)
20227sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
20228add %i0, %i3, %i3
20229! preparing store val #0, next val will be in f20
20230fmovs %f16, %f20
20231fadds %f16, %f17, %f16
20232! preparing store val #1, next val will be in f21
20233fmovs %f16, %f21
20234fadds %f16, %f17, %f16
20235std %f20, [%i3 + 0]
20236
20237P1466: !_MEMBAR (FP)
20238
20239P1467: !_BST [4] (maybe <- 0x40000096) (FP)
20240wr %g0, 0xf0, %asi
20241! preparing store val #0, next val will be in f32
20242fmovs %f16, %f20
20243fadds %f16, %f17, %f16
20244! preparing store val #1, next val will be in f33
20245fmovs %f16, %f21
20246fadds %f16, %f17, %f16
20247! preparing store val #2, next val will be in f35
20248fmovd %f20, %f32
20249fmovs %f16, %f21
20250fadds %f16, %f17, %f16
20251fmovd %f20, %f34
20252membar #Sync
20253stda %f32, [%i1 + 0 ] %asi
20254
20255P1468: !_MEMBAR (FP)
20256membar #StoreLoad
20257
20258P1469: !_PREFETCH [5] (Int)
20259prefetch [%i1 + 12], 22
20260
20261P1470: !_LD [16] (FP)
20262sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
20263sub %i0, %i2, %i2
20264ld [%i2 + 4], %f6
20265! 1 addresses covered
20266
20267P1471: !_SWAP [15] (maybe <- 0x8000b9) (Int)
20268mov %l4, %o2
20269swap [%i2 + 0], %o2
20270! move %o2(lower) -> %o2(upper)
20271sllx %o2, 32, %o2
20272add %l4, 1, %l4
20273
20274P1472: !_SWAP [18] (maybe <- 0x8000ba) (Int)
20275sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
20276sub %i0, %i3, %i3
20277mov %l4, %o5
20278swap [%i3 + 0], %o5
20279! move %o5(lower) -> %o2(lower)
20280srl %o5, 0, %l6
20281or %l6, %o2, %o2
20282add %l4, 1, %l4
20283
20284P1473: !_CASX [17] (maybe <- 0x8000bb) (Int)
20285add %i2, 8, %l6
20286ldx [%l6], %o3
20287! move %o3(upper) -> %o3(upper)
20288! move %o3(lower) -> %o3(lower)
20289mov %o3, %l3
20290mov %l4, %o4
20291casx [%l6], %l3, %o4
20292! move %o4(upper) -> %o4(upper)
20293! move %o4(lower) -> %o4(lower)
20294!---- flushing int results buffer----
20295mov %o0, %l5
20296mov %o1, %l5
20297mov %o2, %l5
20298mov %o3, %l5
20299mov %o4, %l5
20300add %l4, 1, %l4
20301
20302P1474: !_SWAP [14] (maybe <- 0x8000bc) (Int)
20303sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
20304add %i0, %i2, %i2
20305mov %l4, %o0
20306swap [%i2 + 12], %o0
20307! move %o0(lower) -> %o0(upper)
20308sllx %o0, 32, %o0
20309add %l4, 1, %l4
20310
20311P1475: !_DWLD [10] (Int)
20312sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
20313add %i0, %i3, %i3
20314ldx [%i3 + 0], %l3
20315! move %l3(upper) -> %o0(lower)
20316srlx %l3, 32, %o5
20317or %o5, %o0, %o0
20318! move %l3(lower) -> %o1(upper)
20319sllx %l3, 32, %o1
20320
20321P1476: !_DWST [6] (maybe <- 0x8000bd) (Int)
20322sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
20323sub %i0, %i2, %i2
20324sllx %l4, 32, %l6
20325add %l4, 1, %l4
20326or %l6, %l4, %l6
20327stx %l6, [%i2 + 0]
20328add %l4, 1, %l4
20329
20330P1477: !_DWST_BINIT [19] (maybe <- 0x8000bf) (Int)
20331wr %g0, 0xe2, %asi
20332sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
20333sub %i0, %i3, %i3
20334sllx %l4, 32, %l3
20335add %l4, 1, %l4
20336or %l3, %l4, %l3
20337stxa %l3, [%i3 + 0] %asi
20338add %l4, 1, %l4
20339
20340P1478: !_MEMBAR (Int)
20341membar #StoreLoad
20342
20343P1479: !_BLD [8] (FP)
20344wr %g0, 0xf0, %asi
20345ldda [%i2 + 0] %asi, %f32
20346membar #Sync
20347! 3 addresses covered
20348fmovd %f32, %f18
20349fmovs %f18, %f7
20350fmovs %f19, %f8
20351fmovd %f34, %f18
20352fmovs %f19, %f9
20353
20354P1480: !_MEMBAR (FP)
20355
20356P1481: !_CASX [17] (maybe <- 0x8000c1) (Int) (LE)
20357! Change single-word-level endianess (big endian <-> little endian)
20358sethi %hi(0xff00ff00), %l3
20359or %l3, %lo(0xff00ff00), %l3
20360and %l4, %l3, %o5
20361srl %o5, 8, %o5
20362sll %l4, 8, %l6
20363and %l6, %l3, %l6
20364or %l6, %o5, %l6
20365srl %l6, 16, %o5
20366sll %l6, 16, %l6
20367srl %l6, 0, %l6
20368or %l6, %o5, %l6
20369sllx %l6, 32, %l6
20370wr %g0, 0x88, %asi
20371sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
20372sub %i0, %i2, %i2
20373add %i2, 8, %l3
20374ldxa [%l3] %asi, %l7
20375! move %l7(lower) -> %o1(lower)
20376srl %l7, 0, %o5
20377or %o5, %o1, %o1
20378! move %l7(upper) -> %o2(upper)
20379or %l7, %g0, %o2
20380mov %l7, %o5
20381mov %l6, %l7
20382casxa [%l3] %asi, %o5, %l7
20383! move %l7(lower) -> %o2(lower)
20384srlx %o2, 32, %o2
20385sllx %o2, 32, %o2
20386srl %l7, 0, %o5
20387or %o5, %o2, %o2
20388! move %l7(upper) -> %o3(upper)
20389or %l7, %g0, %o3
20390add %l4, 1, %l4
20391
20392P1482: !_REPLACEMENT [3] (Int)
20393sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
20394add %i0, %i3, %i3
20395sethi %hi(0x20000), %o5
20396ld [%i3+0], %l6
20397st %l6, [%i3+0]
20398add %i3, %o5, %l3
20399ld [%l3+0], %l6
20400st %l6, [%l3+0]
20401add %l3, %o5, %l3
20402ld [%l3+0], %l6
20403st %l6, [%l3+0]
20404add %l3, %o5, %l3
20405ld [%l3+0], %l6
20406st %l6, [%l3+0]
20407add %l3, %o5, %l3
20408ld [%l3+0], %l6
20409st %l6, [%l3+0]
20410add %l3, %o5, %l3
20411ld [%l3+0], %l6
20412st %l6, [%l3+0]
20413add %l3, %o5, %l3
20414ld [%l3+0], %l6
20415st %l6, [%l3+0]
20416add %l3, %o5, %l3
20417ld [%l3+0], %l6
20418st %l6, [%l3+0]
20419
20420P1483: !_ST [10] (maybe <- 0x40000099) (FP)
20421sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
20422add %i0, %i2, %i2
20423! preparing store val #0, next val will be in f20
20424fmovs %f16, %f20
20425fadds %f16, %f17, %f16
20426st %f20, [%i2 + 4 ]
20427
20428P1484: !_MEMBAR (FP)
20429membar #StoreLoad
20430
20431P1485: !_BLD [15] (FP)
20432wr %g0, 0xf0, %asi
20433sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
20434sub %i0, %i3, %i3
20435ldda [%i3 + 0] %asi, %f32
20436membar #Sync
20437! 3 addresses covered
20438fmovd %f32, %f10
20439fmovd %f34, %f18
20440fmovs %f19, %f12
20441
20442P1486: !_MEMBAR (FP)
20443
20444P1487: !_CASX [7] (maybe <- 0x8000c2) (Int)
20445sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
20446sub %i0, %i2, %i2
20447ldx [%i2], %l3
20448! move %l3(upper) -> %o3(lower)
20449srlx %o3, 32, %o3
20450sllx %o3, 32, %o3
20451srlx %l3, 32, %l6
20452or %l6, %o3, %o3
20453! move %l3(lower) -> %o4(upper)
20454sllx %l3, 32, %o4
20455mov %l3, %l6
20456sllx %l4, 32, %l3
20457add %l4, 1, %l4
20458or %l4, %l3, %l3
20459casx [%i2], %l6, %l3
20460! move %l3(upper) -> %o4(lower)
20461srlx %l3, 32, %l6
20462or %l6, %o4, %o4
20463!---- flushing int results buffer----
20464mov %o0, %l5
20465mov %o1, %l5
20466mov %o2, %l5
20467mov %o3, %l5
20468mov %o4, %l5
20469! move %l3(lower) -> %o0(upper)
20470sllx %l3, 32, %o0
20471add %l4, 1, %l4
20472
20473P1488: !_ST_BINIT [6] (maybe <- 0x8000c4) (Int)
20474wr %g0, 0xe2, %asi
20475stwa %l4, [%i2 + 0] %asi
20476add %l4, 1, %l4
20477
20478P1489: !_MEMBAR (Int)
20479membar #StoreLoad
20480
20481P1490: !_DWST_BINIT [13] (maybe <- 0x8000c5) (Int)
20482wr %g0, 0xe2, %asi
20483sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
20484add %i0, %i3, %i3
20485sllx %l4, 32, %l3
20486add %l4, 1, %l4
20487or %l3, %l4, %l3
20488stxa %l3, [%i3 + 0] %asi
20489add %l4, 1, %l4
20490
20491P1491: !_MEMBAR (Int)
20492membar #StoreLoad
20493
20494P1492: !_REPLACEMENT [18] (Int)
20495sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
20496sub %i0, %i2, %i2
20497sethi %hi(0x20000), %o5
20498ld [%i2+0], %l6
20499st %l6, [%i2+0]
20500add %i2, %o5, %l3
20501ld [%l3+0], %l6
20502st %l6, [%l3+0]
20503add %l3, %o5, %l3
20504ld [%l3+0], %l6
20505st %l6, [%l3+0]
20506add %l3, %o5, %l3
20507ld [%l3+0], %l6
20508st %l6, [%l3+0]
20509add %l3, %o5, %l3
20510ld [%l3+0], %l6
20511st %l6, [%l3+0]
20512add %l3, %o5, %l3
20513ld [%l3+0], %l6
20514st %l6, [%l3+0]
20515add %l3, %o5, %l3
20516ld [%l3+0], %l6
20517st %l6, [%l3+0]
20518add %l3, %o5, %l3
20519ld [%l3+0], %l6
20520st %l6, [%l3+0]
20521
20522P1493: !_DWLD [8] (Int)
20523sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
20524sub %i0, %i3, %i3
20525ldx [%i3 + 8], %o5
20526! move %o5(lower) -> %o0(lower)
20527srl %o5, 0, %l7
20528or %l7, %o0, %o0
20529
20530P1494: !_MEMBAR (FP)
20531
20532P1495: !_BSTC [18] (maybe <- 0x4000009a) (FP)
20533wr %g0, 0xe0, %asi
20534sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
20535sub %i0, %i2, %i2
20536! preparing store val #0, next val will be in f32
20537fmovs %f16, %f20
20538fadds %f16, %f17, %f16
20539! preparing store val #1, next val will be in f33
20540fmovs %f16, %f21
20541fadds %f16, %f17, %f16
20542! preparing store val #2, next val will be in f35
20543fmovd %f20, %f32
20544fmovs %f16, %f21
20545fadds %f16, %f17, %f16
20546fmovd %f20, %f34
20547membar #Sync
20548stda %f32, [%i2 + 0 ] %asi
20549
20550P1496: !_MEMBAR (FP)
20551membar #StoreLoad
20552
20553P1497: !_ST [19] (maybe <- 0x8000c7) (Int)
20554stw %l4, [%i2 + 4 ]
20555add %l4, 1, %l4
20556
20557P1498: !_ST [12] (maybe <- 0x8000c8) (Int)
20558sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
20559add %i0, %i3, %i3
20560stw %l4, [%i3 + 0 ]
20561add %l4, 1, %l4
20562
20563P1499: !_CASX [5] (maybe <- 0x8000c9) (Int)
20564add %i1, 8, %l7
20565ldx [%l7], %o1
20566! move %o1(upper) -> %o1(upper)
20567! move %o1(lower) -> %o1(lower)
20568mov %o1, %l6
20569mov %l4, %o2
20570casx [%l7], %l6, %o2
20571! move %o2(upper) -> %o2(upper)
20572! move %o2(lower) -> %o2(lower)
20573add %l4, 1, %l4
20574
20575P1500: !_REPLACEMENT [11] (Int)
20576sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
20577sub %i0, %i2, %i2
20578sethi %hi(0x20000), %l6
20579ld [%i2+12], %o5
20580st %o5, [%i2+12]
20581add %i2, %l6, %l7
20582ld [%l7+12], %o5
20583st %o5, [%l7+12]
20584add %l7, %l6, %l7
20585ld [%l7+12], %o5
20586st %o5, [%l7+12]
20587add %l7, %l6, %l7
20588ld [%l7+12], %o5
20589st %o5, [%l7+12]
20590add %l7, %l6, %l7
20591ld [%l7+12], %o5
20592st %o5, [%l7+12]
20593add %l7, %l6, %l7
20594ld [%l7+12], %o5
20595st %o5, [%l7+12]
20596add %l7, %l6, %l7
20597ld [%l7+12], %o5
20598st %o5, [%l7+12]
20599add %l7, %l6, %l7
20600ld [%l7+12], %o5
20601st %o5, [%l7+12]
20602
20603P1501: !_MEMBAR (FP)
20604
20605P1502: !_BST [2] (maybe <- 0x4000009d) (FP)
20606wr %g0, 0xf0, %asi
20607! preparing store val #0, next val will be in f32
20608fmovs %f16, %f20
20609fadds %f16, %f17, %f16
20610! preparing store val #1, next val will be in f33
20611fmovs %f16, %f21
20612fadds %f16, %f17, %f16
20613! preparing store val #2, next val will be in f35
20614fmovd %f20, %f32
20615fmovs %f16, %f21
20616fadds %f16, %f17, %f16
20617fmovd %f20, %f34
20618membar #Sync
20619stda %f32, [%i0 + 0 ] %asi
20620
20621P1503: !_MEMBAR (FP)
20622membar #StoreLoad
20623
20624P1504: !_SWAP [3] (maybe <- 0x8000ca) (Int) (Branch target of P1157)
20625mov %l4, %o3
20626swap [%i1 + 0], %o3
20627! move %o3(lower) -> %o3(upper)
20628sllx %o3, 32, %o3
20629add %l4, 1, %l4
20630ba P1505
20631nop
20632
20633TARGET1157:
20634ba RET1157
20635nop
20636
20637
20638P1505: !_ST_BINIT [10] (maybe <- 0x8000cb) (Int) (Branch target of P1733)
20639wr %g0, 0xe2, %asi
20640sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
20641add %i0, %i3, %i3
20642stwa %l4, [%i3 + 4] %asi
20643add %l4, 1, %l4
20644ba P1506
20645nop
20646
20647TARGET1733:
20648ba RET1733
20649nop
20650
20651
20652P1506: !_MEMBAR (Int)
20653membar #StoreLoad
20654
20655P1507: !_LDD [15] (Int)
20656sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
20657sub %i0, %i2, %i2
20658ldd [%i2 + 0], %l6
20659! move %l6(lower) -> %o3(lower)
20660or %l6, %o3, %o3
20661! move %l7(lower) -> %o4(upper)
20662sllx %l7, 32, %o4
20663
20664P1508: !_DWLD [5] (Int)
20665ldx [%i1 + 8], %l6
20666! move %l6(lower) -> %o4(lower)
20667srl %l6, 0, %l3
20668or %l3, %o4, %o4
20669!---- flushing int results buffer----
20670mov %o0, %l5
20671mov %o1, %l5
20672mov %o2, %l5
20673mov %o3, %l5
20674mov %o4, %l5
20675
20676P1509: !_DWLD [14] (Int)
20677sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
20678add %i0, %i3, %i3
20679ldx [%i3 + 8], %o0
20680! move %o0(lower) -> %o0(upper)
20681sllx %o0, 32, %o0
20682
20683P1510: !_REPLACEMENT [12] (Int)
20684sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
20685sub %i0, %i2, %i2
20686sethi %hi(0x20000), %l3
20687ld [%i2+0], %l7
20688st %l7, [%i2+0]
20689add %i2, %l3, %l6
20690ld [%l6+0], %l7
20691st %l7, [%l6+0]
20692add %l6, %l3, %l6
20693ld [%l6+0], %l7
20694st %l7, [%l6+0]
20695add %l6, %l3, %l6
20696ld [%l6+0], %l7
20697st %l7, [%l6+0]
20698add %l6, %l3, %l6
20699ld [%l6+0], %l7
20700st %l7, [%l6+0]
20701add %l6, %l3, %l6
20702ld [%l6+0], %l7
20703st %l7, [%l6+0]
20704add %l6, %l3, %l6
20705ld [%l6+0], %l7
20706st %l7, [%l6+0]
20707add %l6, %l3, %l6
20708ld [%l6+0], %l7
20709st %l7, [%l6+0]
20710
20711P1511: !_ST [15] (maybe <- 0x8000cc) (Int)
20712sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
20713sub %i0, %i3, %i3
20714stw %l4, [%i3 + 0 ]
20715add %l4, 1, %l4
20716
20717P1512: !_LD [3] (Int)
20718lduw [%i1 + 0], %o5
20719! move %o5(lower) -> %o0(lower)
20720or %o5, %o0, %o0
20721
20722P1513: !_PREFETCH [3] (Int) (CBR)
20723!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
20724!Logical addr: 3
20725
20726sethi %hi(0x200000), %l3
20727sub %i1, %l3, %i1
20728prefetch [%i1 + 0], 22
20729
20730! cbranch
20731andcc %l0, 1, %g0
20732be,pt %xcc, TARGET1513
20733nop
20734RET1513:
20735
20736! lfsr step begin
20737srlx %l0, 1, %l6
20738xnor %l6, %l0, %l6
20739sllx %l6, 63, %l6
20740or %l6, %l0, %l0
20741srlx %l0, 1, %l0
20742
20743
20744P1514: !_MEMBAR (FP)
20745
20746P1515: !_BSTC [2] (maybe <- 0x400000a0) (FP)
20747wr %g0, 0xe0, %asi
20748! preparing store val #0, next val will be in f32
20749fmovs %f16, %f20
20750fadds %f16, %f17, %f16
20751! preparing store val #1, next val will be in f33
20752fmovs %f16, %f21
20753fadds %f16, %f17, %f16
20754! preparing store val #2, next val will be in f35
20755fmovd %f20, %f32
20756fmovs %f16, %f21
20757fadds %f16, %f17, %f16
20758fmovd %f20, %f34
20759membar #Sync
20760stda %f32, [%i0 + 0 ] %asi
20761
20762P1516: !_MEMBAR (FP)
20763
20764P1517: !_BSTC [12] (maybe <- 0x400000a3) (FP)
20765wr %g0, 0xe0, %asi
20766sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
20767add %i0, %i2, %i2
20768! preparing store val #0, next val will be in f32
20769fmovs %f16, %f20
20770fadds %f16, %f17, %f16
20771! preparing store val #1, next val will be in f33
20772fmovs %f16, %f21
20773fadds %f16, %f17, %f16
20774! preparing store val #2, next val will be in f35
20775fmovd %f20, %f32
20776fmovs %f16, %f21
20777fadds %f16, %f17, %f16
20778fmovd %f20, %f34
20779membar #Sync
20780stda %f32, [%i2 + 0 ] %asi
20781
20782P1518: !_MEMBAR (FP)
20783
20784P1519: !_BSTC [3] (maybe <- 0x400000a6) (FP)
20785wr %g0, 0xe0, %asi
20786! preparing store val #0, next val will be in f32
20787fmovs %f16, %f20
20788fadds %f16, %f17, %f16
20789! preparing store val #1, next val will be in f33
20790fmovs %f16, %f21
20791fadds %f16, %f17, %f16
20792! preparing store val #2, next val will be in f35
20793fmovd %f20, %f32
20794fmovs %f16, %f21
20795fadds %f16, %f17, %f16
20796fmovd %f20, %f34
20797membar #Sync
20798stda %f32, [%i1 + 0 ] %asi
20799
20800P1520: !_MEMBAR (FP)
20801membar #StoreLoad
20802
20803P1521: !_ST [2] (maybe <- 0x400000a9) (FP)
20804! preparing store val #0, next val will be in f20
20805fmovs %f16, %f20
20806fadds %f16, %f17, %f16
20807st %f20, [%i0 + 12 ]
20808
20809P1522: !_MEMBAR (FP)
20810membar #StoreLoad
20811
20812P1523: !_BLD [11] (FP)
20813wr %g0, 0xf0, %asi
20814sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
20815add %i0, %i3, %i3
20816ldda [%i3 + 0] %asi, %f32
20817membar #Sync
20818! 3 addresses covered
20819fmovd %f32, %f18
20820fmovs %f18, %f13
20821fmovs %f19, %f14
20822fmovd %f34, %f18
20823fmovs %f19, %f15
20824!---- flushing fp results buffer to %f30 ----
20825fmovd %f0, %f30
20826fmovd %f2, %f30
20827fmovd %f4, %f30
20828fmovd %f6, %f30
20829fmovd %f8, %f30
20830fmovd %f10, %f30
20831fmovd %f12, %f30
20832fmovd %f14, %f30
20833!--
20834
20835P1524: !_MEMBAR (FP) (Branch target of P1096)
20836ba P1525
20837nop
20838
20839TARGET1096:
20840ba RET1096
20841nop
20842
20843
20844P1525: !_ST [21] (maybe <- 0x8000cd) (Int) (Branch target of P1623)
20845sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
20846sub %i0, %i2, %i2
20847stw %l4, [%i2 + 0 ]
20848add %l4, 1, %l4
20849ba P1526
20850nop
20851
20852TARGET1623:
20853ba RET1623
20854nop
20855
20856
20857P1526: !_LDD [12] (Int)
20858sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
20859add %i0, %i3, %i3
20860ldd [%i3 + 0], %l6
20861! move %l6(lower) -> %o1(upper)
20862sllx %l6, 32, %o1
20863! move %l7(lower) -> %o1(lower)
20864or %l7, %o1, %o1
20865
20866P1527: !_MEMBAR (FP) (Branch target of P1723)
20867ba P1528
20868nop
20869
20870TARGET1723:
20871ba RET1723
20872nop
20873
20874
20875P1528: !_BSTC [3] (maybe <- 0x400000aa) (FP)
20876wr %g0, 0xe0, %asi
20877! preparing store val #0, next val will be in f32
20878fmovs %f16, %f20
20879fadds %f16, %f17, %f16
20880! preparing store val #1, next val will be in f33
20881fmovs %f16, %f21
20882fadds %f16, %f17, %f16
20883! preparing store val #2, next val will be in f35
20884fmovd %f20, %f32
20885fmovs %f16, %f21
20886fadds %f16, %f17, %f16
20887fmovd %f20, %f34
20888membar #Sync
20889stda %f32, [%i1 + 0 ] %asi
20890
20891P1529: !_MEMBAR (FP)
20892
20893P1530: !_BST [12] (maybe <- 0x400000ad) (FP)
20894wr %g0, 0xf0, %asi
20895! preparing store val #0, next val will be in f32
20896fmovs %f16, %f20
20897fadds %f16, %f17, %f16
20898! preparing store val #1, next val will be in f33
20899fmovs %f16, %f21
20900fadds %f16, %f17, %f16
20901! preparing store val #2, next val will be in f35
20902fmovd %f20, %f32
20903fmovs %f16, %f21
20904fadds %f16, %f17, %f16
20905fmovd %f20, %f34
20906membar #Sync
20907stda %f32, [%i3 + 0 ] %asi
20908
20909P1531: !_MEMBAR (FP)
20910membar #StoreLoad
20911
20912P1532: !_ST [6] (maybe <- 0x8000ce) (Int)
20913sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
20914sub %i0, %i2, %i2
20915stw %l4, [%i2 + 0 ]
20916add %l4, 1, %l4
20917
20918P1533: !_MEMBAR (FP)
20919membar #StoreLoad
20920
20921P1534: !_BLD [2] (FP)
20922wr %g0, 0xf0, %asi
20923ldda [%i0 + 0] %asi, %f0
20924membar #Sync
20925! 3 addresses covered
20926fmovs %f3, %f2
20927
20928P1535: !_MEMBAR (FP)
20929
20930P1536: !_SWAP [5] (maybe <- 0x8000cf) (Int)
20931mov %l4, %o2
20932swap [%i1 + 12], %o2
20933! move %o2(lower) -> %o2(upper)
20934sllx %o2, 32, %o2
20935add %l4, 1, %l4
20936
20937P1537: !_CASX [18] (maybe <- 0x8000d0) (Int)
20938sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
20939sub %i0, %i3, %i3
20940ldx [%i3], %o5
20941! move %o5(upper) -> %o2(lower)
20942srlx %o5, 32, %l3
20943or %l3, %o2, %o2
20944! move %o5(lower) -> %o3(upper)
20945sllx %o5, 32, %o3
20946mov %o5, %l3
20947sllx %l4, 32, %o5
20948add %l4, 1, %l4
20949or %l4, %o5, %o5
20950casx [%i3], %l3, %o5
20951! move %o5(upper) -> %o3(lower)
20952srlx %o5, 32, %l3
20953or %l3, %o3, %o3
20954! move %o5(lower) -> %o4(upper)
20955sllx %o5, 32, %o4
20956add %l4, 1, %l4
20957
20958P1538: !_ST_BINIT [14] (maybe <- 0x8000d2) (Int)
20959wr %g0, 0xe2, %asi
20960sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
20961add %i0, %i2, %i2
20962stwa %l4, [%i2 + 12] %asi
20963add %l4, 1, %l4
20964
20965P1539: !_MEMBAR (Int)
20966membar #StoreLoad
20967
20968P1540: !_LD [15] (Int)
20969sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
20970sub %i0, %i3, %i3
20971lduw [%i3 + 0], %l3
20972! move %l3(lower) -> %o4(lower)
20973or %l3, %o4, %o4
20974!---- flushing int results buffer----
20975mov %o0, %l5
20976mov %o1, %l5
20977mov %o2, %l5
20978mov %o3, %l5
20979mov %o4, %l5
20980
20981P1541: !_CASX [11] (maybe <- 0x8000d3) (Int)
20982sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
20983add %i0, %i2, %i2
20984add %i2, 8, %l7
20985ldx [%l7], %o0
20986! move %o0(upper) -> %o0(upper)
20987! move %o0(lower) -> %o0(lower)
20988mov %o0, %l6
20989mov %l4, %o1
20990casx [%l7], %l6, %o1
20991! move %o1(upper) -> %o1(upper)
20992! move %o1(lower) -> %o1(lower)
20993add %l4, 1, %l4
20994
20995P1542: !_MEMBAR (FP)
20996
20997P1543: !_BSTC [8] (maybe <- 0x400000b0) (FP)
20998wr %g0, 0xe0, %asi
20999sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
21000sub %i0, %i3, %i3
21001! preparing store val #0, next val will be in f32
21002fmovs %f16, %f20
21003fadds %f16, %f17, %f16
21004! preparing store val #1, next val will be in f33
21005fmovs %f16, %f21
21006fadds %f16, %f17, %f16
21007! preparing store val #2, next val will be in f35
21008fmovd %f20, %f32
21009fmovs %f16, %f21
21010fadds %f16, %f17, %f16
21011fmovd %f20, %f34
21012membar #Sync
21013stda %f32, [%i3 + 0 ] %asi
21014
21015P1544: !_MEMBAR (FP)
21016membar #StoreLoad
21017
21018P1545: !_DWLD [1] (Int)
21019ldx [%i0 + 0], %o2
21020! move %o2(upper) -> %o2(upper)
21021! move %o2(lower) -> %o2(lower)
21022
21023P1546: !_REPLACEMENT [4] (Int)
21024sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
21025sub %i0, %i2, %i2
21026sethi %hi(0x20000), %l7
21027ld [%i2+4], %l3
21028st %l3, [%i2+4]
21029add %i2, %l7, %o5
21030ld [%o5+4], %l3
21031st %l3, [%o5+4]
21032add %o5, %l7, %o5
21033ld [%o5+4], %l3
21034st %l3, [%o5+4]
21035add %o5, %l7, %o5
21036ld [%o5+4], %l3
21037st %l3, [%o5+4]
21038add %o5, %l7, %o5
21039ld [%o5+4], %l3
21040st %l3, [%o5+4]
21041add %o5, %l7, %o5
21042ld [%o5+4], %l3
21043st %l3, [%o5+4]
21044add %o5, %l7, %o5
21045ld [%o5+4], %l3
21046st %l3, [%o5+4]
21047add %o5, %l7, %o5
21048ld [%o5+4], %l3
21049st %l3, [%o5+4]
21050
21051P1547: !_DWST [10] (maybe <- 0x400000b3) (FP)
21052sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
21053add %i0, %i3, %i3
21054! preparing store val #0, next val will be in f20
21055fmovs %f16, %f20
21056fadds %f16, %f17, %f16
21057! preparing store val #1, next val will be in f21
21058fmovs %f16, %f21
21059fadds %f16, %f17, %f16
21060std %f20, [%i3 + 0]
21061
21062P1548: !_MEMBAR (FP)
21063
21064P1549: !_BST [19] (maybe <- 0x400000b5) (FP)
21065wr %g0, 0xf0, %asi
21066sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
21067sub %i0, %i2, %i2
21068! preparing store val #0, next val will be in f32
21069fmovs %f16, %f20
21070fadds %f16, %f17, %f16
21071! preparing store val #1, next val will be in f33
21072fmovs %f16, %f21
21073fadds %f16, %f17, %f16
21074! preparing store val #2, next val will be in f35
21075fmovd %f20, %f32
21076fmovs %f16, %f21
21077fadds %f16, %f17, %f16
21078fmovd %f20, %f34
21079membar #Sync
21080stda %f32, [%i2 + 0 ] %asi
21081
21082P1550: !_MEMBAR (FP)
21083membar #StoreLoad
21084
21085P1551: !_LDD [7] (Int)
21086sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
21087sub %i0, %i3, %i3
21088ldd [%i3 + 0], %l6
21089! move %l6(lower) -> %o3(upper)
21090sllx %l6, 32, %o3
21091! move %l7(lower) -> %o3(lower)
21092or %l7, %o3, %o3
21093
21094P1552: !_MEMBAR (FP)
21095
21096P1553: !_BSTC [18] (maybe <- 0x400000b8) (FP)
21097wr %g0, 0xe0, %asi
21098! preparing store val #0, next val will be in f32
21099fmovs %f16, %f20
21100fadds %f16, %f17, %f16
21101! preparing store val #1, next val will be in f33
21102fmovs %f16, %f21
21103fadds %f16, %f17, %f16
21104! preparing store val #2, next val will be in f35
21105fmovd %f20, %f32
21106fmovs %f16, %f21
21107fadds %f16, %f17, %f16
21108fmovd %f20, %f34
21109membar #Sync
21110stda %f32, [%i2 + 0 ] %asi
21111
21112P1554: !_MEMBAR (FP)
21113
21114P1555: !_BST [3] (maybe <- 0x400000bb) (FP)
21115wr %g0, 0xf0, %asi
21116! preparing store val #0, next val will be in f32
21117fmovs %f16, %f20
21118fadds %f16, %f17, %f16
21119! preparing store val #1, next val will be in f33
21120fmovs %f16, %f21
21121fadds %f16, %f17, %f16
21122! preparing store val #2, next val will be in f35
21123fmovd %f20, %f32
21124fmovs %f16, %f21
21125fadds %f16, %f17, %f16
21126fmovd %f20, %f34
21127membar #Sync
21128stda %f32, [%i1 + 0 ] %asi
21129
21130P1556: !_MEMBAR (FP)
21131membar #StoreLoad
21132
21133P1557: !_LDD [11] (Int)
21134sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
21135add %i0, %i2, %i2
21136ldd [%i2 + 8], %l6
21137! move %l7(lower) -> %o4(upper)
21138sllx %l7, 32, %o4
21139
21140P1558: !_REPLACEMENT [6] (Int) (Branch target of P1193)
21141sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
21142sub %i0, %i3, %i3
21143sethi %hi(0x20000), %l3
21144ld [%i3+0], %l7
21145st %l7, [%i3+0]
21146add %i3, %l3, %l6
21147ld [%l6+0], %l7
21148st %l7, [%l6+0]
21149add %l6, %l3, %l6
21150ld [%l6+0], %l7
21151st %l7, [%l6+0]
21152add %l6, %l3, %l6
21153ld [%l6+0], %l7
21154st %l7, [%l6+0]
21155add %l6, %l3, %l6
21156ld [%l6+0], %l7
21157st %l7, [%l6+0]
21158add %l6, %l3, %l6
21159ld [%l6+0], %l7
21160st %l7, [%l6+0]
21161add %l6, %l3, %l6
21162ld [%l6+0], %l7
21163st %l7, [%l6+0]
21164add %l6, %l3, %l6
21165ld [%l6+0], %l7
21166st %l7, [%l6+0]
21167ba P1559
21168nop
21169
21170TARGET1193:
21171ba RET1193
21172nop
21173
21174
21175P1559: !_MEMBAR (FP) (Branch target of P1409)
21176ba P1560
21177nop
21178
21179TARGET1409:
21180ba RET1409
21181nop
21182
21183
21184P1560: !_BSTC [15] (maybe <- 0x400000be) (FP)
21185wr %g0, 0xe0, %asi
21186sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
21187sub %i0, %i2, %i2
21188! preparing store val #0, next val will be in f32
21189fmovs %f16, %f20
21190fadds %f16, %f17, %f16
21191! preparing store val #1, next val will be in f33
21192fmovs %f16, %f21
21193fadds %f16, %f17, %f16
21194! preparing store val #2, next val will be in f35
21195fmovd %f20, %f32
21196fmovs %f16, %f21
21197fadds %f16, %f17, %f16
21198fmovd %f20, %f34
21199membar #Sync
21200stda %f32, [%i2 + 0 ] %asi
21201
21202P1561: !_MEMBAR (FP)
21203
21204P1562: !_BSTC [13] (maybe <- 0x400000c1) (FP)
21205wr %g0, 0xe0, %asi
21206sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
21207add %i0, %i3, %i3
21208! preparing store val #0, next val will be in f32
21209fmovs %f16, %f20
21210fadds %f16, %f17, %f16
21211! preparing store val #1, next val will be in f33
21212fmovs %f16, %f21
21213fadds %f16, %f17, %f16
21214! preparing store val #2, next val will be in f35
21215fmovd %f20, %f32
21216fmovs %f16, %f21
21217fadds %f16, %f17, %f16
21218fmovd %f20, %f34
21219membar #Sync
21220stda %f32, [%i3 + 0 ] %asi
21221
21222P1563: !_MEMBAR (FP)
21223membar #StoreLoad
21224
21225P1564: !_CAS [9] (maybe <- 0x8000d4) (Int) (Branch target of P1660)
21226sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
21227add %i0, %i2, %i2
21228lduw [%i2], %l3
21229mov %l3, %l6
21230! move %l6(lower) -> %o4(lower)
21231or %l6, %o4, %o4
21232!---- flushing int results buffer----
21233mov %o0, %l5
21234mov %o1, %l5
21235mov %o2, %l5
21236mov %o3, %l5
21237mov %o4, %l5
21238mov %l4, %o0
21239cas [%i2], %l6, %o0
21240! move %o0(lower) -> %o0(upper)
21241sllx %o0, 32, %o0
21242add %l4, 1, %l4
21243ba P1565
21244nop
21245
21246TARGET1660:
21247ba RET1660
21248nop
21249
21250
21251P1565: !_ST [17] (maybe <- 0x8000d5) (Int)
21252sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
21253sub %i0, %i3, %i3
21254stw %l4, [%i3 + 12 ]
21255add %l4, 1, %l4
21256
21257P1566: !_LD [20] (Int)
21258sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
21259sub %i0, %i2, %i2
21260lduw [%i2 + 12], %l6
21261! move %l6(lower) -> %o0(lower)
21262or %l6, %o0, %o0
21263
21264P1567: !_LD [19] (Int)
21265lduw [%i2 + 4], %o1
21266! move %o1(lower) -> %o1(upper)
21267sllx %o1, 32, %o1
21268
21269P1568: !_CASX [1] (maybe <- 0x8000d6) (Int) (CBR)
21270ldx [%i0], %o5
21271! move %o5(upper) -> %o1(lower)
21272srlx %o5, 32, %l3
21273or %l3, %o1, %o1
21274! move %o5(lower) -> %o2(upper)
21275sllx %o5, 32, %o2
21276mov %o5, %l3
21277sllx %l4, 32, %o5
21278add %l4, 1, %l4
21279or %l4, %o5, %o5
21280casx [%i0], %l3, %o5
21281! move %o5(upper) -> %o2(lower)
21282srlx %o5, 32, %l3
21283or %l3, %o2, %o2
21284! move %o5(lower) -> %o3(upper)
21285sllx %o5, 32, %o3
21286add %l4, 1, %l4
21287
21288! cbranch
21289andcc %l0, 1, %g0
21290be,pt %xcc, TARGET1568
21291nop
21292RET1568:
21293
21294! lfsr step begin
21295srlx %l0, 1, %l3
21296xnor %l3, %l0, %l3
21297sllx %l3, 63, %l3
21298or %l3, %l0, %l0
21299srlx %l0, 1, %l0
21300
21301
21302P1569: !_ST_BINIT [11] (maybe <- 0x8000d8) (Int)
21303wr %g0, 0xe2, %asi
21304sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
21305add %i0, %i3, %i3
21306stwa %l4, [%i3 + 12] %asi
21307add %l4, 1, %l4
21308
21309P1570: !_MEMBAR (Int)
21310membar #StoreLoad
21311
21312P1571: !_SWAP [11] (maybe <- 0x8000d9) (Int)
21313mov %l4, %l7
21314swap [%i3 + 12], %l7
21315! move %l7(lower) -> %o3(lower)
21316srl %l7, 0, %l3
21317or %l3, %o3, %o3
21318add %l4, 1, %l4
21319
21320P1572: !_LD [7] (Int)
21321sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
21322sub %i0, %i2, %i2
21323lduw [%i2 + 4], %o4
21324! move %o4(lower) -> %o4(upper)
21325sllx %o4, 32, %o4
21326
21327P1573: !_MEMBAR (FP)
21328membar #StoreLoad
21329
21330P1574: !_BLD [10] (FP)
21331wr %g0, 0xf0, %asi
21332ldda [%i3 + 0] %asi, %f32
21333membar #Sync
21334! 3 addresses covered
21335fmovd %f32, %f18
21336fmovs %f18, %f3
21337fmovs %f19, %f4
21338fmovd %f34, %f18
21339fmovs %f19, %f5
21340
21341P1575: !_MEMBAR (FP)
21342
21343P1576: !_DWLD [18] (FP)
21344sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
21345sub %i0, %i3, %i3
21346ldd [%i3 + 0], %f6
21347! 2 addresses covered
21348
21349P1577: !_ST [1] (maybe <- 0x8000da) (Int)
21350stw %l4, [%i0 + 4 ]
21351add %l4, 1, %l4
21352
21353P1578: !_CAS [8] (maybe <- 0x8000db) (Int)
21354add %i2, 12, %l7
21355lduw [%l7], %l3
21356mov %l3, %l6
21357! move %l6(lower) -> %o4(lower)
21358or %l6, %o4, %o4
21359!---- flushing int results buffer----
21360mov %o0, %l5
21361mov %o1, %l5
21362mov %o2, %l5
21363mov %o3, %l5
21364mov %o4, %l5
21365mov %l4, %o0
21366cas [%l7], %l6, %o0
21367! move %o0(lower) -> %o0(upper)
21368sllx %o0, 32, %o0
21369add %l4, 1, %l4
21370
21371P1579: !_SWAP [16] (maybe <- 0x8000dc) (Int)
21372sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
21373sub %i0, %i2, %i2
21374mov %l4, %o5
21375swap [%i2 + 4], %o5
21376! move %o5(lower) -> %o0(lower)
21377srl %o5, 0, %l6
21378or %l6, %o0, %o0
21379add %l4, 1, %l4
21380
21381P1580: !_ST_BINIT [23] (maybe <- 0x8000dd) (Int)
21382wr %g0, 0xe2, %asi
21383sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
21384sub %i0, %i3, %i3
21385stwa %l4, [%i3 + 12] %asi
21386add %l4, 1, %l4
21387
21388P1581: !_MEMBAR (Int) (Branch target of P1458)
21389membar #StoreLoad
21390ba P1582
21391nop
21392
21393TARGET1458:
21394ba RET1458
21395nop
21396
21397
21398P1582: !_DWLD [1] (Int)
21399ldx [%i0 + 0], %o1
21400! move %o1(upper) -> %o1(upper)
21401! move %o1(lower) -> %o1(lower)
21402
21403P1583: !_PREFETCH [17] (Int)
21404prefetch [%i2 + 12], 21
21405
21406P1584: !_LD [3] (Int) (LE)
21407wr %g0, 0x88, %asi
21408lduwa [%i1 + 0] %asi, %o2
21409! move %o2(lower) -> %o2(upper)
21410sllx %o2, 32, %o2
21411
21412P1585: !_ST [17] (maybe <- 0x8000de) (Int)
21413stw %l4, [%i2 + 12 ]
21414add %l4, 1, %l4
21415
21416P1586: !_CAS [21] (maybe <- 0x8000df) (Int)
21417lduw [%i3], %l6
21418mov %l6, %l7
21419! move %l7(lower) -> %o2(lower)
21420or %l7, %o2, %o2
21421mov %l4, %o3
21422cas [%i3], %l7, %o3
21423! move %o3(lower) -> %o3(upper)
21424sllx %o3, 32, %o3
21425add %l4, 1, %l4
21426
21427P1587: !_MEMBAR (FP)
21428
21429P1588: !_BSTC [3] (maybe <- 0x400000c4) (FP) (Branch target of P1929)
21430wr %g0, 0xe0, %asi
21431! preparing store val #0, next val will be in f32
21432fmovs %f16, %f20
21433fadds %f16, %f17, %f16
21434! preparing store val #1, next val will be in f33
21435fmovs %f16, %f21
21436fadds %f16, %f17, %f16
21437! preparing store val #2, next val will be in f35
21438fmovd %f20, %f32
21439fmovs %f16, %f21
21440fadds %f16, %f17, %f16
21441fmovd %f20, %f34
21442membar #Sync
21443stda %f32, [%i1 + 0 ] %asi
21444ba P1589
21445nop
21446
21447TARGET1929:
21448ba RET1929
21449nop
21450
21451
21452P1589: !_MEMBAR (FP)
21453membar #StoreLoad
21454
21455P1590: !_CAS [15] (maybe <- 0x8000e0) (Int) (CBR)
21456lduw [%i2], %l3
21457mov %l3, %l6
21458! move %l6(lower) -> %o3(lower)
21459or %l6, %o3, %o3
21460mov %l4, %o4
21461cas [%i2], %l6, %o4
21462! move %o4(lower) -> %o4(upper)
21463sllx %o4, 32, %o4
21464add %l4, 1, %l4
21465
21466! cbranch
21467andcc %l0, 1, %g0
21468be,pn %xcc, TARGET1590
21469nop
21470RET1590:
21471
21472! lfsr step begin
21473srlx %l0, 1, %l6
21474xnor %l6, %l0, %l6
21475sllx %l6, 63, %l6
21476or %l6, %l0, %l0
21477srlx %l0, 1, %l0
21478
21479
21480P1591: !_ST_BINIT [7] (maybe <- 0x8000e1) (Int)
21481wr %g0, 0xe2, %asi
21482sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
21483sub %i0, %i2, %i2
21484stwa %l4, [%i2 + 4] %asi
21485add %l4, 1, %l4
21486
21487P1592: !_MEMBAR (Int)
21488membar #StoreLoad
21489
21490P1593: !_BLD [16] (FP)
21491wr %g0, 0xf0, %asi
21492sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
21493sub %i0, %i3, %i3
21494ldda [%i3 + 0] %asi, %f32
21495membar #Sync
21496! 3 addresses covered
21497fmovd %f32, %f8
21498fmovd %f34, %f18
21499fmovs %f19, %f10
21500
21501P1594: !_MEMBAR (FP) (Branch target of P1165)
21502ba P1595
21503nop
21504
21505TARGET1165:
21506ba RET1165
21507nop
21508
21509
21510P1595: !_LDD [9] (Int)
21511sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
21512add %i0, %i2, %i2
21513ldd [%i2 + 0], %l6
21514! move %l6(lower) -> %o4(lower)
21515or %l6, %o4, %o4
21516!---- flushing int results buffer----
21517mov %o0, %l5
21518mov %o1, %l5
21519mov %o2, %l5
21520mov %o3, %l5
21521mov %o4, %l5
21522! move %l7(lower) -> %o0(upper)
21523sllx %l7, 32, %o0
21524
21525P1596: !_ST [22] (maybe <- 0x8000e2) (Int)
21526sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
21527sub %i0, %i3, %i3
21528stw %l4, [%i3 + 4 ]
21529add %l4, 1, %l4
21530
21531P1597: !_CAS [7] (maybe <- 0x8000e3) (Int)
21532sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
21533sub %i0, %i2, %i2
21534add %i2, 4, %l3
21535lduw [%l3], %l7
21536mov %l7, %o5
21537! move %o5(lower) -> %o0(lower)
21538or %o5, %o0, %o0
21539mov %l4, %o1
21540cas [%l3], %o5, %o1
21541! move %o1(lower) -> %o1(upper)
21542sllx %o1, 32, %o1
21543add %l4, 1, %l4
21544
21545P1598: !_CAS [22] (maybe <- 0x8000e4) (Int)
21546add %i3, 4, %l3
21547lduw [%l3], %l7
21548mov %l7, %o5
21549! move %o5(lower) -> %o1(lower)
21550or %o5, %o1, %o1
21551mov %l4, %o2
21552cas [%l3], %o5, %o2
21553! move %o2(lower) -> %o2(upper)
21554sllx %o2, 32, %o2
21555add %l4, 1, %l4
21556
21557P1599: !_LD [12] (Int)
21558sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
21559add %i0, %i3, %i3
21560lduw [%i3 + 0], %l3
21561! move %l3(lower) -> %o2(lower)
21562or %l3, %o2, %o2
21563
21564P1600: !_DWST_BINIT [1] (maybe <- 0x8000e5) (Int)
21565wr %g0, 0xe2, %asi
21566sllx %l4, 32, %l6
21567add %l4, 1, %l4
21568or %l6, %l4, %l6
21569stxa %l6, [%i0 + 0] %asi
21570add %l4, 1, %l4
21571
21572P1601: !_MEMBAR (Int)
21573membar #StoreLoad
21574
21575P1602: !_DWST_BINIT [15] (maybe <- 0x8000e7) (Int) (Branch target of P1840)
21576wr %g0, 0xe2, %asi
21577sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
21578sub %i0, %i2, %i2
21579sllx %l4, 32, %l3
21580add %l4, 1, %l4
21581or %l3, %l4, %l3
21582stxa %l3, [%i2 + 0] %asi
21583add %l4, 1, %l4
21584ba P1603
21585nop
21586
21587TARGET1840:
21588ba RET1840
21589nop
21590
21591
21592P1603: !_MEMBAR (Int)
21593membar #StoreLoad
21594
21595P1604: !_DWST [2] (maybe <- 0x8000e9) (Int)
21596mov %l4, %o5
21597stx %o5, [%i0 + 8]
21598add %l4, 1, %l4
21599
21600P1605: !_MEMBAR (FP)
21601
21602P1606: !_BST [19] (maybe <- 0x400000c7) (FP)
21603wr %g0, 0xf0, %asi
21604sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
21605sub %i0, %i3, %i3
21606! preparing store val #0, next val will be in f32
21607fmovs %f16, %f20
21608fadds %f16, %f17, %f16
21609! preparing store val #1, next val will be in f33
21610fmovs %f16, %f21
21611fadds %f16, %f17, %f16
21612! preparing store val #2, next val will be in f35
21613fmovd %f20, %f32
21614fmovs %f16, %f21
21615fadds %f16, %f17, %f16
21616fmovd %f20, %f34
21617membar #Sync
21618stda %f32, [%i3 + 0 ] %asi
21619
21620P1607: !_MEMBAR (FP)
21621membar #StoreLoad
21622
21623P1608: !_LDD [11] (Int)
21624sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
21625add %i0, %i2, %i2
21626ldd [%i2 + 8], %l6
21627! move %l7(lower) -> %o3(upper)
21628sllx %l7, 32, %o3
21629
21630P1609: !_ST_BINIT [0] (maybe <- 0x8000ea) (Int)
21631wr %g0, 0xe2, %asi
21632stwa %l4, [%i0 + 0] %asi
21633add %l4, 1, %l4
21634
21635P1610: !_MEMBAR (Int)
21636membar #StoreLoad
21637
21638P1611: !_LD [19] (FP)
21639ld [%i3 + 4], %f11
21640! 1 addresses covered
21641
21642P1612: !_PREFETCH [22] (Int)
21643sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
21644sub %i0, %i3, %i3
21645prefetch [%i3 + 4], 2
21646
21647P1613: !_PREFETCH [14] (Int)
21648sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
21649add %i0, %i2, %i2
21650prefetch [%i2 + 12], 2
21651
21652P1614: !_SWAP [7] (maybe <- 0x8000eb) (Int)
21653sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
21654sub %i0, %i3, %i3
21655mov %l4, %l6
21656swap [%i3 + 4], %l6
21657! move %l6(lower) -> %o3(lower)
21658srl %l6, 0, %o5
21659or %o5, %o3, %o3
21660add %l4, 1, %l4
21661
21662P1615: !_DWST_BINIT [7] (maybe <- 0x8000ec) (Int)
21663wr %g0, 0xe2, %asi
21664sllx %l4, 32, %l7
21665add %l4, 1, %l4
21666or %l7, %l4, %l7
21667stxa %l7, [%i3 + 0] %asi
21668add %l4, 1, %l4
21669
21670P1616: !_MEMBAR (Int)
21671membar #StoreLoad
21672
21673P1617: !_DWLD [7] (Int)
21674ldx [%i3 + 0], %o4
21675! move %o4(upper) -> %o4(upper)
21676! move %o4(lower) -> %o4(lower)
21677!---- flushing int results buffer----
21678mov %o0, %l5
21679mov %o1, %l5
21680mov %o2, %l5
21681mov %o3, %l5
21682mov %o4, %l5
21683
21684P1618: !_LDD [5] (Int) (LE)
21685wr %g0, 0x88, %asi
21686ldda [%i1 + 8] %asi, %l6
21687! move %l7(lower) -> %o0(upper)
21688sllx %l7, 32, %o0
21689
21690P1619: !_DWST [4] (maybe <- 0x400000ca) (FP)
21691! preparing store val #0, next val will be in f20
21692fmovs %f16, %f20
21693fadds %f16, %f17, %f16
21694! preparing store val #1, next val will be in f21
21695fmovs %f16, %f21
21696fadds %f16, %f17, %f16
21697std %f20, [%i1 + 0]
21698
21699P1620: !_DWST_BINIT [17] (maybe <- 0x8000ee) (Int)
21700wr %g0, 0xe2, %asi
21701sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
21702sub %i0, %i2, %i2
21703mov %l4, %o5
21704stxa %o5, [%i2 + 8] %asi
21705add %l4, 1, %l4
21706
21707P1621: !_MEMBAR (Int)
21708membar #StoreLoad
21709
21710P1622: !_DWLD [2] (Int)
21711ldx [%i0 + 8], %o5
21712! move %o5(lower) -> %o0(lower)
21713srl %o5, 0, %l7
21714or %l7, %o0, %o0
21715
21716P1623: !_MEMBAR (FP) (CBR)
21717membar #StoreLoad
21718
21719! cbranch
21720andcc %l0, 1, %g0
21721be,pn %xcc, TARGET1623
21722nop
21723RET1623:
21724
21725! lfsr step begin
21726srlx %l0, 1, %l3
21727xnor %l3, %l0, %l3
21728sllx %l3, 63, %l3
21729or %l3, %l0, %l0
21730srlx %l0, 1, %l0
21731
21732
21733P1624: !_BLD [3] (FP)
21734wr %g0, 0xf0, %asi
21735ldda [%i1 + 0] %asi, %f32
21736membar #Sync
21737! 3 addresses covered
21738fmovd %f32, %f12
21739fmovd %f34, %f18
21740fmovs %f19, %f14
21741
21742P1625: !_MEMBAR (FP)
21743
21744P1626: !_LDD [19] (Int)
21745sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
21746sub %i0, %i3, %i3
21747ldd [%i3 + 0], %l6
21748! move %l6(lower) -> %o1(upper)
21749sllx %l6, 32, %o1
21750! move %l7(lower) -> %o1(lower)
21751or %l7, %o1, %o1
21752
21753P1627: !_MEMBAR (FP)
21754
21755P1628: !_BSTC [20] (maybe <- 0x400000cc) (FP) (Branch target of P1568)
21756wr %g0, 0xe0, %asi
21757! preparing store val #0, next val will be in f32
21758fmovs %f16, %f20
21759fadds %f16, %f17, %f16
21760! preparing store val #1, next val will be in f33
21761fmovs %f16, %f21
21762fadds %f16, %f17, %f16
21763! preparing store val #2, next val will be in f35
21764fmovd %f20, %f32
21765fmovs %f16, %f21
21766fadds %f16, %f17, %f16
21767fmovd %f20, %f34
21768membar #Sync
21769stda %f32, [%i3 + 0 ] %asi
21770ba P1629
21771nop
21772
21773TARGET1568:
21774ba RET1568
21775nop
21776
21777
21778P1629: !_MEMBAR (FP)
21779membar #StoreLoad
21780
21781P1630: !_LD [16] (Int)
21782lduw [%i2 + 4], %o2
21783! move %o2(lower) -> %o2(upper)
21784sllx %o2, 32, %o2
21785
21786P1631: !_MEMBAR (FP) (CBR)
21787membar #StoreLoad
21788
21789! cbranch
21790andcc %l0, 1, %g0
21791be,pt %xcc, TARGET1631
21792nop
21793RET1631:
21794
21795! lfsr step begin
21796srlx %l0, 1, %l6
21797xnor %l6, %l0, %l6
21798sllx %l6, 63, %l6
21799or %l6, %l0, %l0
21800srlx %l0, 1, %l0
21801
21802
21803P1632: !_BLD [2] (FP)
21804wr %g0, 0xf0, %asi
21805ldda [%i0 + 0] %asi, %f32
21806membar #Sync
21807! 3 addresses covered
21808fmovd %f32, %f18
21809fmovs %f18, %f15
21810!---- flushing fp results buffer to %f30 ----
21811fmovd %f0, %f30
21812fmovd %f2, %f30
21813fmovd %f4, %f30
21814fmovd %f6, %f30
21815fmovd %f8, %f30
21816fmovd %f10, %f30
21817fmovd %f12, %f30
21818fmovd %f14, %f30
21819!--
21820fmovs %f19, %f0
21821fmovd %f34, %f18
21822fmovs %f19, %f1
21823
21824P1633: !_MEMBAR (FP) (Branch target of P1841)
21825ba P1634
21826nop
21827
21828TARGET1841:
21829ba RET1841
21830nop
21831
21832
21833P1634: !_CAS [4] (maybe <- 0x8000ef) (Int)
21834add %i1, 4, %o5
21835lduw [%o5], %l6
21836mov %l6, %l7
21837! move %l7(lower) -> %o2(lower)
21838or %l7, %o2, %o2
21839mov %l4, %o3
21840cas [%o5], %l7, %o3
21841! move %o3(lower) -> %o3(upper)
21842sllx %o3, 32, %o3
21843add %l4, 1, %l4
21844
21845P1635: !_ST_BINIT [1] (maybe <- 0x8000f0) (Int)
21846wr %g0, 0xe2, %asi
21847stwa %l4, [%i0 + 4] %asi
21848add %l4, 1, %l4
21849
21850P1636: !_MEMBAR (Int)
21851
21852P1637: !_BSTC [9] (maybe <- 0x400000cf) (FP)
21853wr %g0, 0xe0, %asi
21854sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
21855add %i0, %i2, %i2
21856! preparing store val #0, next val will be in f32
21857fmovs %f16, %f20
21858fadds %f16, %f17, %f16
21859! preparing store val #1, next val will be in f33
21860fmovs %f16, %f21
21861fadds %f16, %f17, %f16
21862! preparing store val #2, next val will be in f35
21863fmovd %f20, %f32
21864fmovs %f16, %f21
21865fadds %f16, %f17, %f16
21866fmovd %f20, %f34
21867membar #Sync
21868stda %f32, [%i2 + 0 ] %asi
21869
21870P1638: !_MEMBAR (FP)
21871membar #StoreLoad
21872
21873P1639: !_CASX [6] (maybe <- 0x8000f1) (Int)
21874sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
21875sub %i0, %i3, %i3
21876ldx [%i3], %o5
21877! move %o5(upper) -> %o3(lower)
21878srlx %o5, 32, %l3
21879or %l3, %o3, %o3
21880! move %o5(lower) -> %o4(upper)
21881sllx %o5, 32, %o4
21882mov %o5, %l3
21883sllx %l4, 32, %o5
21884add %l4, 1, %l4
21885or %l4, %o5, %o5
21886casx [%i3], %l3, %o5
21887! move %o5(upper) -> %o4(lower)
21888srlx %o5, 32, %l3
21889or %l3, %o4, %o4
21890!---- flushing int results buffer----
21891mov %o0, %l5
21892mov %o1, %l5
21893mov %o2, %l5
21894mov %o3, %l5
21895mov %o4, %l5
21896! move %o5(lower) -> %o0(upper)
21897sllx %o5, 32, %o0
21898add %l4, 1, %l4
21899
21900P1640: !_PREFETCH [0] (Int)
21901prefetch [%i0 + 0], 19
21902
21903P1641: !_SWAP [1] (maybe <- 0x8000f3) (Int)
21904mov %l4, %o5
21905swap [%i0 + 4], %o5
21906! move %o5(lower) -> %o0(lower)
21907srl %o5, 0, %l6
21908or %l6, %o0, %o0
21909add %l4, 1, %l4
21910
21911P1642: !_MEMBAR (FP)
21912
21913P1643: !_BST [5] (maybe <- 0x400000d2) (FP)
21914wr %g0, 0xf0, %asi
21915! preparing store val #0, next val will be in f32
21916fmovs %f16, %f20
21917fadds %f16, %f17, %f16
21918! preparing store val #1, next val will be in f33
21919fmovs %f16, %f21
21920fadds %f16, %f17, %f16
21921! preparing store val #2, next val will be in f35
21922fmovd %f20, %f32
21923fmovs %f16, %f21
21924fadds %f16, %f17, %f16
21925fmovd %f20, %f34
21926membar #Sync
21927stda %f32, [%i1 + 0 ] %asi
21928
21929P1644: !_MEMBAR (FP)
21930membar #StoreLoad
21931
21932P1645: !_ST [18] (maybe <- 0x8000f4) (Int) (Branch target of P1631)
21933sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
21934sub %i0, %i2, %i2
21935stw %l4, [%i2 + 0 ]
21936add %l4, 1, %l4
21937ba P1646
21938nop
21939
21940TARGET1631:
21941ba RET1631
21942nop
21943
21944
21945P1646: !_PREFETCH [13] (Int) (LE)
21946wr %g0, 0x88, %asi
21947sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
21948add %i0, %i3, %i3
21949prefetcha [%i3 + 4] %asi, 20
21950
21951P1647: !_CASX [18] (maybe <- 0x8000f5) (Int) (LE)
21952sllx %l4, 32, %o5
21953add %l4, 1, %l4
21954or %l4, %o5, %o5
21955! Change double-word-level endianess (big endian <-> little endian)
21956sethi %hi(0xff00ff00), %l7
21957or %l7, %lo(0xff00ff00), %l7
21958sllx %l7, 32, %l3
21959or %l7, %l3, %l7
21960and %o5, %l7, %l3
21961srlx %l3, 8, %l3
21962sllx %o5, 8, %o5
21963and %o5, %l7, %o5
21964or %o5, %l3, %o5
21965sethi %hi(0xffff0000), %l7
21966srlx %o5, 16, %l3
21967andn %l3, %l7, %l3
21968andn %o5, %l7, %o5
21969sllx %o5, 16, %o5
21970or %o5, %l3, %o5
21971srlx %o5, 32, %l3
21972sllx %o5, 32, %o5
21973or %o5, %l3, %l3
21974wr %g0, 0x88, %asi
21975ldxa [%i2] %asi, %l6
21976! move %l6(lower) -> %o1(upper)
21977sllx %l6, 32, %o1
21978! move %l6(upper) -> %o1(lower)
21979srlx %l6, 32, %l7
21980or %l7, %o1, %o1
21981mov %l6, %l7
21982mov %l3, %l6
21983casxa [%i2] %asi, %l7, %l6
21984! move %l6(lower) -> %o2(upper)
21985sllx %l6, 32, %o2
21986! move %l6(upper) -> %o2(lower)
21987srlx %l6, 32, %l7
21988or %l7, %o2, %o2
21989add %l4, 1, %l4
21990
21991P1648: !_DWST [0] (maybe <- 0x8000f7) (Int)
21992sllx %l4, 32, %l7
21993add %l4, 1, %l4
21994or %l7, %l4, %l7
21995stx %l7, [%i0 + 0]
21996add %l4, 1, %l4
21997
21998P1649: !_ST_BINIT [13] (maybe <- 0x8000f9) (Int)
21999wr %g0, 0xe2, %asi
22000stwa %l4, [%i3 + 4] %asi
22001add %l4, 1, %l4
22002
22003P1650: !_MEMBAR (Int)
22004membar #StoreLoad
22005
22006P1651: !_CASX [18] (maybe <- 0x8000fa) (Int)
22007ldx [%i2], %o3
22008! move %o3(upper) -> %o3(upper)
22009! move %o3(lower) -> %o3(lower)
22010mov %o3, %l3
22011sllx %l4, 32, %o4
22012add %l4, 1, %l4
22013or %l4, %o4, %o4
22014casx [%i2], %l3, %o4
22015! move %o4(upper) -> %o4(upper)
22016! move %o4(lower) -> %o4(lower)
22017!---- flushing int results buffer----
22018mov %o0, %l5
22019mov %o1, %l5
22020mov %o2, %l5
22021mov %o3, %l5
22022mov %o4, %l5
22023add %l4, 1, %l4
22024
22025P1652: !_MEMBAR (FP) (CBR)
22026
22027! cbranch
22028andcc %l0, 1, %g0
22029be,pt %xcc, TARGET1652
22030nop
22031RET1652:
22032
22033! lfsr step begin
22034srlx %l0, 1, %l3
22035xnor %l3, %l0, %l3
22036sllx %l3, 63, %l3
22037or %l3, %l0, %l0
22038srlx %l0, 1, %l0
22039
22040
22041P1653: !_BST [12] (maybe <- 0x400000d5) (FP)
22042wr %g0, 0xf0, %asi
22043! preparing store val #0, next val will be in f32
22044fmovs %f16, %f20
22045fadds %f16, %f17, %f16
22046! preparing store val #1, next val will be in f33
22047fmovs %f16, %f21
22048fadds %f16, %f17, %f16
22049! preparing store val #2, next val will be in f35
22050fmovd %f20, %f32
22051fmovs %f16, %f21
22052fadds %f16, %f17, %f16
22053fmovd %f20, %f34
22054membar #Sync
22055stda %f32, [%i3 + 0 ] %asi
22056
22057P1654: !_MEMBAR (FP)
22058membar #StoreLoad
22059
22060P1655: !_ST_BINIT [11] (maybe <- 0x8000fc) (Int)
22061wr %g0, 0xe2, %asi
22062sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
22063add %i0, %i2, %i2
22064stwa %l4, [%i2 + 12] %asi
22065add %l4, 1, %l4
22066
22067P1656: !_MEMBAR (Int)
22068membar #StoreLoad
22069
22070P1657: !_ST_BINIT [14] (maybe <- 0x8000fd) (Int)
22071wr %g0, 0xe2, %asi
22072stwa %l4, [%i3 + 12] %asi
22073add %l4, 1, %l4
22074
22075P1658: !_MEMBAR (Int)
22076membar #StoreLoad
22077
22078P1659: !_ST [21] (maybe <- 0x8000fe) (Int)
22079sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
22080sub %i0, %i3, %i3
22081stw %l4, [%i3 + 0 ]
22082add %l4, 1, %l4
22083
22084P1660: !_REPLACEMENT [12] (Int) (CBR)
22085sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
22086sub %i0, %i2, %i2
22087sethi %hi(0x20000), %l6
22088ld [%i2+0], %o5
22089st %o5, [%i2+0]
22090add %i2, %l6, %l7
22091ld [%l7+0], %o5
22092st %o5, [%l7+0]
22093add %l7, %l6, %l7
22094ld [%l7+0], %o5
22095st %o5, [%l7+0]
22096add %l7, %l6, %l7
22097ld [%l7+0], %o5
22098st %o5, [%l7+0]
22099add %l7, %l6, %l7
22100ld [%l7+0], %o5
22101st %o5, [%l7+0]
22102add %l7, %l6, %l7
22103ld [%l7+0], %o5
22104st %o5, [%l7+0]
22105add %l7, %l6, %l7
22106ld [%l7+0], %o5
22107st %o5, [%l7+0]
22108add %l7, %l6, %l7
22109ld [%l7+0], %o5
22110st %o5, [%l7+0]
22111
22112! cbranch
22113andcc %l0, 1, %g0
22114be,pt %xcc, TARGET1660
22115nop
22116RET1660:
22117
22118! lfsr step begin
22119srlx %l0, 1, %l3
22120xnor %l3, %l0, %l3
22121sllx %l3, 63, %l3
22122or %l3, %l0, %l0
22123srlx %l0, 1, %l0
22124
22125
22126P1661: !_CAS [1] (maybe <- 0x8000ff) (Int)
22127add %i0, 4, %l7
22128lduw [%l7], %o0
22129mov %o0, %l6
22130! move %l6(lower) -> %o0(upper)
22131sllx %l6, 32, %o0
22132mov %l4, %l3
22133cas [%l7], %l6, %l3
22134! move %l3(lower) -> %o0(lower)
22135srl %l3, 0, %l6
22136or %l6, %o0, %o0
22137add %l4, 1, %l4
22138
22139P1662: !_MEMBAR (FP)
22140
22141P1663: !_BSTC [4] (maybe <- 0x400000d8) (FP)
22142wr %g0, 0xe0, %asi
22143! preparing store val #0, next val will be in f32
22144fmovs %f16, %f20
22145fadds %f16, %f17, %f16
22146! preparing store val #1, next val will be in f33
22147fmovs %f16, %f21
22148fadds %f16, %f17, %f16
22149! preparing store val #2, next val will be in f35
22150fmovd %f20, %f32
22151fmovs %f16, %f21
22152fadds %f16, %f17, %f16
22153fmovd %f20, %f34
22154membar #Sync
22155stda %f32, [%i1 + 0 ] %asi
22156
22157P1664: !_MEMBAR (FP)
22158membar #StoreLoad
22159
22160P1665: !_DWLD [15] (Int)
22161sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
22162sub %i0, %i3, %i3
22163ldx [%i3 + 0], %o1
22164! move %o1(upper) -> %o1(upper)
22165! move %o1(lower) -> %o1(lower)
22166
22167P1666: !_LD [3] (Int)
22168lduw [%i1 + 0], %o2
22169! move %o2(lower) -> %o2(upper)
22170sllx %o2, 32, %o2
22171
22172P1667: !_DWST_BINIT [4] (maybe <- 0x800100) (Int)
22173wr %g0, 0xe2, %asi
22174sllx %l4, 32, %l3
22175add %l4, 1, %l4
22176or %l3, %l4, %l3
22177stxa %l3, [%i1 + 0] %asi
22178add %l4, 1, %l4
22179
22180P1668: !_MEMBAR (Int)
22181membar #StoreLoad
22182
22183P1669: !_DWST [3] (maybe <- 0x800102) (Int)
22184sllx %l4, 32, %o5
22185add %l4, 1, %l4
22186or %o5, %l4, %o5
22187stx %o5, [%i1 + 0]
22188add %l4, 1, %l4
22189
22190P1670: !_DWST [1] (maybe <- 0x800104) (Int)
22191sllx %l4, 32, %l7
22192add %l4, 1, %l4
22193or %l7, %l4, %l7
22194stx %l7, [%i0 + 0]
22195add %l4, 1, %l4
22196
22197P1671: !_MEMBAR (FP)
22198
22199P1672: !_BSTC [5] (maybe <- 0x400000db) (FP)
22200wr %g0, 0xe0, %asi
22201! preparing store val #0, next val will be in f32
22202fmovs %f16, %f20
22203fadds %f16, %f17, %f16
22204! preparing store val #1, next val will be in f33
22205fmovs %f16, %f21
22206fadds %f16, %f17, %f16
22207! preparing store val #2, next val will be in f35
22208fmovd %f20, %f32
22209fmovs %f16, %f21
22210fadds %f16, %f17, %f16
22211fmovd %f20, %f34
22212membar #Sync
22213stda %f32, [%i1 + 0 ] %asi
22214
22215P1673: !_MEMBAR (FP) (CBR)
22216membar #StoreLoad
22217
22218! cbranch
22219andcc %l0, 1, %g0
22220be,pn %xcc, TARGET1673
22221nop
22222RET1673:
22223
22224! lfsr step begin
22225srlx %l0, 1, %l3
22226xnor %l3, %l0, %l3
22227sllx %l3, 63, %l3
22228or %l3, %l0, %l0
22229srlx %l0, 1, %l0
22230
22231
22232P1674: !_DWLD [3] (Int)
22233ldx [%i1 + 0], %l7
22234! move %l7(upper) -> %o2(lower)
22235srlx %l7, 32, %l6
22236or %l6, %o2, %o2
22237! move %l7(lower) -> %o3(upper)
22238sllx %l7, 32, %o3
22239
22240P1675: !_DWST_BINIT [2] (maybe <- 0x800106) (Int)
22241wr %g0, 0xe2, %asi
22242mov %l4, %o5
22243stxa %o5, [%i0 + 8] %asi
22244add %l4, 1, %l4
22245
22246P1676: !_MEMBAR (Int) (Branch target of P1813)
22247membar #StoreLoad
22248ba P1677
22249nop
22250
22251TARGET1813:
22252ba RET1813
22253nop
22254
22255
22256P1677: !_ST_BINIT [1] (maybe <- 0x800107) (Int)
22257wr %g0, 0xe2, %asi
22258stwa %l4, [%i0 + 4] %asi
22259add %l4, 1, %l4
22260
22261P1678: !_MEMBAR (Int)
22262membar #StoreLoad
22263
22264P1679: !_LD [3] (Int)
22265lduw [%i1 + 0], %l7
22266! move %l7(lower) -> %o3(lower)
22267or %l7, %o3, %o3
22268
22269P1680: !_MEMBAR (FP)
22270membar #StoreLoad
22271
22272P1681: !_BLD [19] (FP)
22273wr %g0, 0xf0, %asi
22274sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
22275sub %i0, %i2, %i2
22276ldda [%i2 + 0] %asi, %f32
22277membar #Sync
22278! 3 addresses covered
22279fmovd %f32, %f2
22280fmovd %f34, %f18
22281fmovs %f19, %f4
22282
22283P1682: !_MEMBAR (FP)
22284
22285P1683: !_DWLD [18] (Int)
22286ldx [%i2 + 0], %o4
22287! move %o4(upper) -> %o4(upper)
22288! move %o4(lower) -> %o4(lower)
22289!---- flushing int results buffer----
22290mov %o0, %l5
22291mov %o1, %l5
22292mov %o2, %l5
22293mov %o3, %l5
22294mov %o4, %l5
22295
22296P1684: !_LD [5] (Int)
22297lduw [%i1 + 12], %o0
22298! move %o0(lower) -> %o0(upper)
22299sllx %o0, 32, %o0
22300
22301P1685: !_LDD [14] (Int)
22302sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
22303add %i0, %i3, %i3
22304ldd [%i3 + 8], %l6
22305! move %l7(lower) -> %o0(lower)
22306or %l7, %o0, %o0
22307
22308P1686: !_ST [15] (maybe <- 0x800108) (Int)
22309sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
22310sub %i0, %i2, %i2
22311stw %l4, [%i2 + 0 ]
22312add %l4, 1, %l4
22313
22314P1687: !_PREFETCH [13] (Int)
22315prefetch [%i3 + 4], 0
22316
22317P1688: !_ST_BINIT [6] (maybe <- 0x800109) (Int)
22318wr %g0, 0xe2, %asi
22319sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
22320sub %i0, %i3, %i3
22321stwa %l4, [%i3 + 0] %asi
22322add %l4, 1, %l4
22323
22324P1689: !_MEMBAR (Int)
22325membar #StoreLoad
22326
22327P1690: !_DWLD [13] (Int)
22328sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
22329add %i0, %i2, %i2
22330ldx [%i2 + 0], %o1
22331! move %o1(upper) -> %o1(upper)
22332! move %o1(lower) -> %o1(lower)
22333
22334P1691: !_LD [14] (Int)
22335lduw [%i2 + 12], %o2
22336! move %o2(lower) -> %o2(upper)
22337sllx %o2, 32, %o2
22338
22339P1692: !_MEMBAR (FP) (Branch target of P2002)
22340ba P1693
22341nop
22342
22343TARGET2002:
22344ba RET2002
22345nop
22346
22347
22348P1693: !_BST [2] (maybe <- 0x400000de) (FP)
22349wr %g0, 0xf0, %asi
22350! preparing store val #0, next val will be in f32
22351fmovs %f16, %f20
22352fadds %f16, %f17, %f16
22353! preparing store val #1, next val will be in f33
22354fmovs %f16, %f21
22355fadds %f16, %f17, %f16
22356! preparing store val #2, next val will be in f35
22357fmovd %f20, %f32
22358fmovs %f16, %f21
22359fadds %f16, %f17, %f16
22360fmovd %f20, %f34
22361membar #Sync
22362stda %f32, [%i0 + 0 ] %asi
22363
22364P1694: !_MEMBAR (FP)
22365
22366P1695: !_BST [6] (maybe <- 0x400000e1) (FP)
22367wr %g0, 0xf0, %asi
22368! preparing store val #0, next val will be in f32
22369fmovs %f16, %f20
22370fadds %f16, %f17, %f16
22371! preparing store val #1, next val will be in f33
22372fmovs %f16, %f21
22373fadds %f16, %f17, %f16
22374! preparing store val #2, next val will be in f35
22375fmovd %f20, %f32
22376fmovs %f16, %f21
22377fadds %f16, %f17, %f16
22378fmovd %f20, %f34
22379membar #Sync
22380stda %f32, [%i3 + 0 ] %asi
22381
22382P1696: !_MEMBAR (FP)
22383membar #StoreLoad
22384
22385P1697: !_ST [10] (maybe <- 0x80010a) (Int)
22386sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
22387add %i0, %i3, %i3
22388stw %l4, [%i3 + 4 ]
22389add %l4, 1, %l4
22390
22391P1698: !_DWST [5] (maybe <- 0x80010b) (Int)
22392mov %l4, %o5
22393stx %o5, [%i1 + 8]
22394add %l4, 1, %l4
22395
22396P1699: !_DWST [20] (maybe <- 0x80010c) (Int)
22397sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
22398sub %i0, %i2, %i2
22399mov %l4, %l7
22400stx %l7, [%i2 + 8]
22401add %l4, 1, %l4
22402
22403P1700: !_DWST_BINIT [11] (maybe <- 0x80010d) (Int)
22404wr %g0, 0xe2, %asi
22405mov %l4, %l6
22406stxa %l6, [%i3 + 8] %asi
22407add %l4, 1, %l4
22408
22409P1701: !_MEMBAR (Int)
22410
22411P1702: !_BSTC [8] (maybe <- 0x400000e4) (FP)
22412wr %g0, 0xe0, %asi
22413sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
22414sub %i0, %i3, %i3
22415! preparing store val #0, next val will be in f32
22416fmovs %f16, %f20
22417fadds %f16, %f17, %f16
22418! preparing store val #1, next val will be in f33
22419fmovs %f16, %f21
22420fadds %f16, %f17, %f16
22421! preparing store val #2, next val will be in f35
22422fmovd %f20, %f32
22423fmovs %f16, %f21
22424fadds %f16, %f17, %f16
22425fmovd %f20, %f34
22426membar #Sync
22427stda %f32, [%i3 + 0 ] %asi
22428
22429P1703: !_MEMBAR (FP)
22430membar #StoreLoad
22431
22432P1704: !_CAS [2] (maybe <- 0x80010e) (Int)
22433add %i0, 12, %l3
22434lduw [%l3], %l7
22435mov %l7, %o5
22436! move %o5(lower) -> %o2(lower)
22437or %o5, %o2, %o2
22438mov %l4, %o3
22439cas [%l3], %o5, %o3
22440! move %o3(lower) -> %o3(upper)
22441sllx %o3, 32, %o3
22442add %l4, 1, %l4
22443
22444P1705: !_MEMBAR (FP)
22445
22446P1706: !_BST [7] (maybe <- 0x400000e7) (FP)
22447wr %g0, 0xf0, %asi
22448! preparing store val #0, next val will be in f32
22449fmovs %f16, %f20
22450fadds %f16, %f17, %f16
22451! preparing store val #1, next val will be in f33
22452fmovs %f16, %f21
22453fadds %f16, %f17, %f16
22454! preparing store val #2, next val will be in f35
22455fmovd %f20, %f32
22456fmovs %f16, %f21
22457fadds %f16, %f17, %f16
22458fmovd %f20, %f34
22459membar #Sync
22460stda %f32, [%i3 + 0 ] %asi
22461
22462P1707: !_MEMBAR (FP)
22463membar #StoreLoad
22464
22465P1708: !_PREFETCH [1] (Int)
22466prefetch [%i0 + 4], 18
22467
22468P1709: !_SWAP [23] (maybe <- 0x80010f) (Int)
22469sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
22470sub %i0, %i2, %i2
22471mov %l4, %l6
22472swap [%i2 + 12], %l6
22473! move %l6(lower) -> %o3(lower)
22474srl %l6, 0, %o5
22475or %o5, %o3, %o3
22476add %l4, 1, %l4
22477
22478P1710: !_ST_BINIT [4] (maybe <- 0x800110) (Int)
22479wr %g0, 0xe2, %asi
22480stwa %l4, [%i1 + 4] %asi
22481add %l4, 1, %l4
22482
22483P1711: !_MEMBAR (Int)
22484membar #StoreLoad
22485
22486P1712: !_DWST_BINIT [16] (maybe <- 0x800111) (Int)
22487wr %g0, 0xe2, %asi
22488sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
22489sub %i0, %i3, %i3
22490sllx %l4, 32, %l6
22491add %l4, 1, %l4
22492or %l6, %l4, %l6
22493stxa %l6, [%i3 + 0] %asi
22494add %l4, 1, %l4
22495
22496P1713: !_MEMBAR (Int) (CBR)
22497
22498! cbranch
22499andcc %l0, 1, %g0
22500be,pt %xcc, TARGET1713
22501nop
22502RET1713:
22503
22504! lfsr step begin
22505srlx %l0, 1, %l3
22506xnor %l3, %l0, %l3
22507sllx %l3, 63, %l3
22508or %l3, %l0, %l0
22509srlx %l0, 1, %l0
22510
22511
22512P1714: !_BST [7] (maybe <- 0x400000ea) (FP)
22513wr %g0, 0xf0, %asi
22514sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
22515sub %i0, %i2, %i2
22516! preparing store val #0, next val will be in f32
22517fmovs %f16, %f20
22518fadds %f16, %f17, %f16
22519! preparing store val #1, next val will be in f33
22520fmovs %f16, %f21
22521fadds %f16, %f17, %f16
22522! preparing store val #2, next val will be in f35
22523fmovd %f20, %f32
22524fmovs %f16, %f21
22525fadds %f16, %f17, %f16
22526fmovd %f20, %f34
22527membar #Sync
22528stda %f32, [%i2 + 0 ] %asi
22529
22530P1715: !_MEMBAR (FP)
22531membar #StoreLoad
22532
22533P1716: !_LDD [19] (Int)
22534sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
22535sub %i0, %i3, %i3
22536ldd [%i3 + 0], %l6
22537! move %l6(lower) -> %o4(upper)
22538sllx %l6, 32, %o4
22539! move %l7(lower) -> %o4(lower)
22540or %l7, %o4, %o4
22541!---- flushing int results buffer----
22542mov %o0, %l5
22543mov %o1, %l5
22544mov %o2, %l5
22545mov %o3, %l5
22546mov %o4, %l5
22547
22548P1717: !_SWAP [1] (maybe <- 0x800113) (Int)
22549mov %l4, %o0
22550swap [%i0 + 4], %o0
22551! move %o0(lower) -> %o0(upper)
22552sllx %o0, 32, %o0
22553add %l4, 1, %l4
22554
22555P1718: !_MEMBAR (FP)
22556membar #StoreLoad
22557
22558P1719: !_BLD [22] (FP)
22559wr %g0, 0xf0, %asi
22560sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
22561sub %i0, %i2, %i2
22562ldda [%i2 + 0] %asi, %f32
22563membar #Sync
22564! 3 addresses covered
22565fmovd %f32, %f18
22566fmovs %f18, %f5
22567fmovs %f19, %f6
22568fmovd %f34, %f18
22569fmovs %f19, %f7
22570
22571P1720: !_MEMBAR (FP)
22572
22573P1721: !_ST_BINIT [20] (maybe <- 0x800114) (Int)
22574wr %g0, 0xe2, %asi
22575stwa %l4, [%i3 + 12] %asi
22576add %l4, 1, %l4
22577
22578P1722: !_MEMBAR (Int)
22579
22580P1723: !_BSTC [3] (maybe <- 0x400000ed) (FP) (CBR)
22581wr %g0, 0xe0, %asi
22582! preparing store val #0, next val will be in f32
22583fmovs %f16, %f20
22584fadds %f16, %f17, %f16
22585! preparing store val #1, next val will be in f33
22586fmovs %f16, %f21
22587fadds %f16, %f17, %f16
22588! preparing store val #2, next val will be in f35
22589fmovd %f20, %f32
22590fmovs %f16, %f21
22591fadds %f16, %f17, %f16
22592fmovd %f20, %f34
22593membar #Sync
22594stda %f32, [%i1 + 0 ] %asi
22595
22596! cbranch
22597andcc %l0, 1, %g0
22598be,pn %xcc, TARGET1723
22599nop
22600RET1723:
22601
22602! lfsr step begin
22603srlx %l0, 1, %l6
22604xnor %l6, %l0, %l6
22605sllx %l6, 63, %l6
22606or %l6, %l0, %l0
22607srlx %l0, 1, %l0
22608
22609
22610P1724: !_MEMBAR (FP)
22611membar #StoreLoad
22612
22613P1725: !_SWAP [0] (maybe <- 0x800115) (Int)
22614mov %l4, %l3
22615swap [%i0 + 0], %l3
22616! move %l3(lower) -> %o0(lower)
22617srl %l3, 0, %l7
22618or %l7, %o0, %o0
22619add %l4, 1, %l4
22620
22621P1726: !_MEMBAR (FP)
22622
22623P1727: !_BSTC [8] (maybe <- 0x400000f0) (FP)
22624wr %g0, 0xe0, %asi
22625sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
22626sub %i0, %i3, %i3
22627! preparing store val #0, next val will be in f32
22628fmovs %f16, %f20
22629fadds %f16, %f17, %f16
22630! preparing store val #1, next val will be in f33
22631fmovs %f16, %f21
22632fadds %f16, %f17, %f16
22633! preparing store val #2, next val will be in f35
22634fmovd %f20, %f32
22635fmovs %f16, %f21
22636fadds %f16, %f17, %f16
22637fmovd %f20, %f34
22638membar #Sync
22639stda %f32, [%i3 + 0 ] %asi
22640
22641P1728: !_MEMBAR (FP)
22642membar #StoreLoad
22643
22644P1729: !_REPLACEMENT [8] (Int)
22645sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
22646sub %i0, %i2, %i2
22647sethi %hi(0x20000), %l3
22648ld [%i2+12], %l7
22649st %l7, [%i2+12]
22650add %i2, %l3, %l6
22651ld [%l6+12], %l7
22652st %l7, [%l6+12]
22653add %l6, %l3, %l6
22654ld [%l6+12], %l7
22655st %l7, [%l6+12]
22656add %l6, %l3, %l6
22657ld [%l6+12], %l7
22658st %l7, [%l6+12]
22659add %l6, %l3, %l6
22660ld [%l6+12], %l7
22661st %l7, [%l6+12]
22662add %l6, %l3, %l6
22663ld [%l6+12], %l7
22664st %l7, [%l6+12]
22665add %l6, %l3, %l6
22666ld [%l6+12], %l7
22667st %l7, [%l6+12]
22668add %l6, %l3, %l6
22669ld [%l6+12], %l7
22670st %l7, [%l6+12]
22671
22672P1730: !_CAS [21] (maybe <- 0x800116) (Int) (Branch target of P1009)
22673sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
22674sub %i0, %i3, %i3
22675lduw [%i3], %o1
22676mov %o1, %o5
22677! move %o5(lower) -> %o1(upper)
22678sllx %o5, 32, %o1
22679mov %l4, %l7
22680cas [%i3], %o5, %l7
22681! move %l7(lower) -> %o1(lower)
22682srl %l7, 0, %o5
22683or %o5, %o1, %o1
22684add %l4, 1, %l4
22685ba P1731
22686nop
22687
22688TARGET1009:
22689ba RET1009
22690nop
22691
22692
22693P1731: !_DWLD [20] (Int)
22694sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
22695sub %i0, %i2, %i2
22696ldx [%i2 + 8], %o2
22697! move %o2(lower) -> %o2(upper)
22698sllx %o2, 32, %o2
22699
22700P1732: !_DWST [10] (maybe <- 0x800117) (Int)
22701sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
22702add %i0, %i3, %i3
22703sllx %l4, 32, %l6
22704add %l4, 1, %l4
22705or %l6, %l4, %l6
22706stx %l6, [%i3 + 0]
22707add %l4, 1, %l4
22708
22709P1733: !_DWST [20] (maybe <- 0x800119) (Int) (CBR)
22710mov %l4, %l3
22711stx %l3, [%i2 + 8]
22712add %l4, 1, %l4
22713
22714! cbranch
22715andcc %l0, 1, %g0
22716be,pt %xcc, TARGET1733
22717nop
22718RET1733:
22719
22720! lfsr step begin
22721srlx %l0, 1, %o5
22722xnor %o5, %l0, %o5
22723sllx %o5, 63, %o5
22724or %o5, %l0, %l0
22725srlx %l0, 1, %l0
22726
22727
22728P1734: !_DWST_BINIT [21] (maybe <- 0x80011a) (Int)
22729wr %g0, 0xe2, %asi
22730sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
22731sub %i0, %i2, %i2
22732sllx %l4, 32, %l3
22733add %l4, 1, %l4
22734or %l3, %l4, %l3
22735stxa %l3, [%i2 + 0] %asi
22736add %l4, 1, %l4
22737
22738P1735: !_MEMBAR (Int)
22739membar #StoreLoad
22740
22741P1736: !_DWST [18] (maybe <- 0x80011c) (Int)
22742sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
22743sub %i0, %i3, %i3
22744sllx %l4, 32, %o5
22745add %l4, 1, %l4
22746or %o5, %l4, %o5
22747stx %o5, [%i3 + 0]
22748add %l4, 1, %l4
22749
22750P1737: !_DWLD [18] (Int)
22751ldx [%i3 + 0], %o5
22752! move %o5(upper) -> %o2(lower)
22753srlx %o5, 32, %l7
22754or %l7, %o2, %o2
22755! move %o5(lower) -> %o3(upper)
22756sllx %o5, 32, %o3
22757
22758P1738: !_PREFETCH [15] (Int) (CBR)
22759sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
22760sub %i0, %i2, %i2
22761prefetch [%i2 + 0], 3
22762
22763! cbranch
22764andcc %l0, 1, %g0
22765be,pt %xcc, TARGET1738
22766nop
22767RET1738:
22768
22769! lfsr step begin
22770srlx %l0, 1, %l3
22771xnor %l3, %l0, %l3
22772sllx %l3, 63, %l3
22773or %l3, %l0, %l0
22774srlx %l0, 1, %l0
22775
22776
22777P1739: !_MEMBAR (FP)
22778
22779P1740: !_BST [23] (maybe <- 0x400000f3) (FP) (CBR)
22780wr %g0, 0xf0, %asi
22781sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
22782sub %i0, %i3, %i3
22783! preparing store val #0, next val will be in f32
22784fmovs %f16, %f20
22785fadds %f16, %f17, %f16
22786! preparing store val #1, next val will be in f33
22787fmovs %f16, %f21
22788fadds %f16, %f17, %f16
22789! preparing store val #2, next val will be in f35
22790fmovd %f20, %f32
22791fmovs %f16, %f21
22792fadds %f16, %f17, %f16
22793fmovd %f20, %f34
22794membar #Sync
22795stda %f32, [%i3 + 0 ] %asi
22796
22797! cbranch
22798andcc %l0, 1, %g0
22799be,pt %xcc, TARGET1740
22800nop
22801RET1740:
22802
22803! lfsr step begin
22804srlx %l0, 1, %l3
22805xnor %l3, %l0, %l3
22806sllx %l3, 63, %l3
22807or %l3, %l0, %l0
22808srlx %l0, 1, %l0
22809
22810
22811P1741: !_MEMBAR (FP)
22812membar #StoreLoad
22813
22814P1742: !_LDD [16] (Int)
22815ldd [%i2 + 0], %l6
22816! move %l6(lower) -> %o3(lower)
22817or %l6, %o3, %o3
22818! move %l7(lower) -> %o4(upper)
22819sllx %l7, 32, %o4
22820
22821P1743: !_MEMBAR (FP)
22822
22823P1744: !_BSTC [9] (maybe <- 0x400000f6) (FP)
22824wr %g0, 0xe0, %asi
22825sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
22826add %i0, %i2, %i2
22827! preparing store val #0, next val will be in f32
22828fmovs %f16, %f20
22829fadds %f16, %f17, %f16
22830! preparing store val #1, next val will be in f33
22831fmovs %f16, %f21
22832fadds %f16, %f17, %f16
22833! preparing store val #2, next val will be in f35
22834fmovd %f20, %f32
22835fmovs %f16, %f21
22836fadds %f16, %f17, %f16
22837fmovd %f20, %f34
22838membar #Sync
22839stda %f32, [%i2 + 0 ] %asi
22840
22841P1745: !_MEMBAR (FP)
22842membar #StoreLoad
22843
22844P1746: !_BLD [14] (FP)
22845wr %g0, 0xf0, %asi
22846sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
22847add %i0, %i3, %i3
22848ldda [%i3 + 0] %asi, %f32
22849membar #Sync
22850! 3 addresses covered
22851fmovd %f32, %f8
22852fmovd %f34, %f18
22853fmovs %f19, %f10
22854
22855P1747: !_MEMBAR (FP)
22856
22857P1748: !_DWST_BINIT [1] (maybe <- 0x80011e) (Int)
22858wr %g0, 0xe2, %asi
22859sllx %l4, 32, %o5
22860add %l4, 1, %l4
22861or %o5, %l4, %o5
22862stxa %o5, [%i0 + 0] %asi
22863add %l4, 1, %l4
22864
22865P1749: !_MEMBAR (Int) (Branch target of P1713)
22866membar #StoreLoad
22867ba P1750
22868nop
22869
22870TARGET1713:
22871ba RET1713
22872nop
22873
22874
22875P1750: !_DWST [21] (maybe <- 0x800120) (Int)
22876sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
22877sub %i0, %i2, %i2
22878sllx %l4, 32, %l7
22879add %l4, 1, %l4
22880or %l7, %l4, %l7
22881stx %l7, [%i2 + 0]
22882add %l4, 1, %l4
22883
22884P1751: !_MEMBAR (FP)
22885
22886P1752: !_BSTC [0] (maybe <- 0x400000f9) (FP)
22887wr %g0, 0xe0, %asi
22888! preparing store val #0, next val will be in f32
22889fmovs %f16, %f20
22890fadds %f16, %f17, %f16
22891! preparing store val #1, next val will be in f33
22892fmovs %f16, %f21
22893fadds %f16, %f17, %f16
22894! preparing store val #2, next val will be in f35
22895fmovd %f20, %f32
22896fmovs %f16, %f21
22897fadds %f16, %f17, %f16
22898fmovd %f20, %f34
22899membar #Sync
22900stda %f32, [%i0 + 0 ] %asi
22901
22902P1753: !_MEMBAR (FP)
22903membar #StoreLoad
22904
22905P1754: !_PREFETCH [3] (Int)
22906prefetch [%i1 + 0], 4
22907
22908P1755: !_DWST [16] (maybe <- 0x400000fc) (FP)
22909sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
22910sub %i0, %i3, %i3
22911! preparing store val #0, next val will be in f20
22912fmovs %f16, %f20
22913fadds %f16, %f17, %f16
22914! preparing store val #1, next val will be in f21
22915fmovs %f16, %f21
22916fadds %f16, %f17, %f16
22917std %f20, [%i3 + 0]
22918
22919P1756: !_DWST_BINIT [8] (maybe <- 0x800122) (Int)
22920wr %g0, 0xe2, %asi
22921sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
22922sub %i0, %i2, %i2
22923mov %l4, %o5
22924stxa %o5, [%i2 + 8] %asi
22925add %l4, 1, %l4
22926
22927P1757: !_MEMBAR (Int)
22928membar #StoreLoad
22929
22930P1758: !_ST [9] (maybe <- 0x800123) (Int)
22931sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
22932add %i0, %i3, %i3
22933stw %l4, [%i3 + 0 ]
22934add %l4, 1, %l4
22935
22936P1759: !_DWST [6] (maybe <- 0x800124) (Int)
22937sllx %l4, 32, %l6
22938add %l4, 1, %l4
22939or %l6, %l4, %l6
22940stx %l6, [%i2 + 0]
22941add %l4, 1, %l4
22942
22943P1760: !_LD [18] (FP)
22944sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
22945sub %i0, %i2, %i2
22946ld [%i2 + 0], %f11
22947! 1 addresses covered
22948
22949P1761: !_DWST_BINIT [6] (maybe <- 0x800126) (Int)
22950wr %g0, 0xe2, %asi
22951sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
22952sub %i0, %i3, %i3
22953sllx %l4, 32, %l3
22954add %l4, 1, %l4
22955or %l3, %l4, %l3
22956stxa %l3, [%i3 + 0] %asi
22957add %l4, 1, %l4
22958
22959P1762: !_MEMBAR (Int)
22960membar #StoreLoad
22961
22962P1763: !_SWAP [8] (maybe <- 0x800128) (Int) (CBR)
22963mov %l4, %l6
22964swap [%i3 + 12], %l6
22965! move %l6(lower) -> %o4(lower)
22966srl %l6, 0, %o5
22967or %o5, %o4, %o4
22968!---- flushing int results buffer----
22969mov %o0, %l5
22970mov %o1, %l5
22971mov %o2, %l5
22972mov %o3, %l5
22973mov %o4, %l5
22974add %l4, 1, %l4
22975
22976! cbranch
22977andcc %l0, 1, %g0
22978be,pn %xcc, TARGET1763
22979nop
22980RET1763:
22981
22982! lfsr step begin
22983srlx %l0, 1, %l7
22984xnor %l7, %l0, %l7
22985sllx %l7, 63, %l7
22986or %l7, %l0, %l0
22987srlx %l0, 1, %l0
22988
22989
22990P1764: !_ST [23] (maybe <- 0x400000fe) (FP)
22991sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
22992sub %i0, %i2, %i2
22993! preparing store val #0, next val will be in f20
22994fmovs %f16, %f20
22995fadds %f16, %f17, %f16
22996st %f20, [%i2 + 12 ]
22997
22998P1765: !_ST [17] (maybe <- 0x800129) (Int)
22999sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
23000sub %i0, %i3, %i3
23001stw %l4, [%i3 + 12 ]
23002add %l4, 1, %l4
23003
23004P1766: !_SWAP [5] (maybe <- 0x80012a) (Int)
23005mov %l4, %o0
23006swap [%i1 + 12], %o0
23007! move %o0(lower) -> %o0(upper)
23008sllx %o0, 32, %o0
23009add %l4, 1, %l4
23010
23011P1767: !_DWST_BINIT [11] (maybe <- 0x80012b) (Int)
23012wr %g0, 0xe2, %asi
23013sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
23014add %i0, %i2, %i2
23015mov %l4, %l3
23016stxa %l3, [%i2 + 8] %asi
23017add %l4, 1, %l4
23018
23019P1768: !_MEMBAR (Int)
23020
23021P1769: !_BST [23] (maybe <- 0x400000ff) (FP)
23022wr %g0, 0xf0, %asi
23023sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
23024add %i0, %i3, %i3
23025! preparing store val #0, next val will be in f32
23026fmovs %f16, %f20
23027fadds %f16, %f17, %f16
23028! preparing store val #1, next val will be in f33
23029fmovs %f16, %f21
23030fadds %f16, %f17, %f16
23031! preparing store val #2, next val will be in f35
23032fmovd %f20, %f32
23033fmovs %f16, %f21
23034fadds %f16, %f17, %f16
23035fmovd %f20, %f34
23036membar #Sync
23037stda %f32, [%i3 + 0 ] %asi
23038
23039P1770: !_MEMBAR (FP)
23040membar #StoreLoad
23041
23042P1771: !_LDD [11] (Int)
23043ldd [%i2 + 8], %l6
23044! move %l7(lower) -> %o0(lower)
23045or %l7, %o0, %o0
23046
23047P1772: !_CAS [20] (maybe <- 0x80012c) (Int)
23048sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
23049sub %i0, %i2, %i2
23050add %i2, 12, %l6
23051lduw [%l6], %o1
23052mov %o1, %l3
23053! move %l3(lower) -> %o1(upper)
23054sllx %l3, 32, %o1
23055mov %l4, %o5
23056cas [%l6], %l3, %o5
23057! move %o5(lower) -> %o1(lower)
23058srl %o5, 0, %l3
23059or %l3, %o1, %o1
23060add %l4, 1, %l4
23061
23062P1773: !_DWST [0] (maybe <- 0x80012d) (Int)
23063sllx %l4, 32, %l3
23064add %l4, 1, %l4
23065or %l3, %l4, %l3
23066stx %l3, [%i0 + 0]
23067add %l4, 1, %l4
23068
23069P1774: !_LDD [4] (Int)
23070ldd [%i1 + 0], %l6
23071! move %l6(lower) -> %o2(upper)
23072sllx %l6, 32, %o2
23073! move %l7(lower) -> %o2(lower)
23074or %l7, %o2, %o2
23075
23076P1775: !_MEMBAR (FP)
23077
23078P1776: !_BST [13] (maybe <- 0x40000102) (FP)
23079wr %g0, 0xf0, %asi
23080sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
23081add %i0, %i3, %i3
23082! preparing store val #0, next val will be in f32
23083fmovs %f16, %f20
23084fadds %f16, %f17, %f16
23085! preparing store val #1, next val will be in f33
23086fmovs %f16, %f21
23087fadds %f16, %f17, %f16
23088! preparing store val #2, next val will be in f35
23089fmovd %f20, %f32
23090fmovs %f16, %f21
23091fadds %f16, %f17, %f16
23092fmovd %f20, %f34
23093membar #Sync
23094stda %f32, [%i3 + 0 ] %asi
23095
23096P1777: !_MEMBAR (FP)
23097membar #StoreLoad
23098
23099P1778: !_PREFETCH [2] (Int) (Branch target of P1740)
23100prefetch [%i0 + 12], 24
23101ba P1779
23102nop
23103
23104TARGET1740:
23105ba RET1740
23106nop
23107
23108
23109P1779: !_LDD [4] (Int)
23110ldd [%i1 + 0], %l6
23111! move %l6(lower) -> %o3(upper)
23112sllx %l6, 32, %o3
23113! move %l7(lower) -> %o3(lower)
23114or %l7, %o3, %o3
23115
23116P1780: !_MEMBAR (FP) (CBR)
23117
23118! cbranch
23119andcc %l0, 1, %g0
23120be,pt %xcc, TARGET1780
23121nop
23122RET1780:
23123
23124! lfsr step begin
23125srlx %l0, 1, %l3
23126xnor %l3, %l0, %l3
23127sllx %l3, 63, %l3
23128or %l3, %l0, %l0
23129srlx %l0, 1, %l0
23130
23131
23132P1781: !_BST [13] (maybe <- 0x40000105) (FP)
23133wr %g0, 0xf0, %asi
23134! preparing store val #0, next val will be in f32
23135fmovs %f16, %f20
23136fadds %f16, %f17, %f16
23137! preparing store val #1, next val will be in f33
23138fmovs %f16, %f21
23139fadds %f16, %f17, %f16
23140! preparing store val #2, next val will be in f35
23141fmovd %f20, %f32
23142fmovs %f16, %f21
23143fadds %f16, %f17, %f16
23144fmovd %f20, %f34
23145membar #Sync
23146stda %f32, [%i3 + 0 ] %asi
23147
23148P1782: !_MEMBAR (FP)
23149membar #StoreLoad
23150
23151P1783: !_REPLACEMENT [0] (Int)
23152sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
23153add %i0, %i2, %i2
23154sethi %hi(0x20000), %l3
23155ld [%i2+0], %l7
23156st %l7, [%i2+0]
23157add %i2, %l3, %l6
23158ld [%l6+0], %l7
23159st %l7, [%l6+0]
23160add %l6, %l3, %l6
23161ld [%l6+0], %l7
23162st %l7, [%l6+0]
23163add %l6, %l3, %l6
23164ld [%l6+0], %l7
23165st %l7, [%l6+0]
23166add %l6, %l3, %l6
23167ld [%l6+0], %l7
23168st %l7, [%l6+0]
23169add %l6, %l3, %l6
23170ld [%l6+0], %l7
23171st %l7, [%l6+0]
23172add %l6, %l3, %l6
23173ld [%l6+0], %l7
23174st %l7, [%l6+0]
23175add %l6, %l3, %l6
23176ld [%l6+0], %l7
23177st %l7, [%l6+0]
23178
23179P1784: !_MEMBAR (FP)
23180
23181P1785: !_BST [11] (maybe <- 0x40000108) (FP)
23182wr %g0, 0xf0, %asi
23183sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
23184add %i0, %i3, %i3
23185! preparing store val #0, next val will be in f32
23186fmovs %f16, %f20
23187fadds %f16, %f17, %f16
23188! preparing store val #1, next val will be in f33
23189fmovs %f16, %f21
23190fadds %f16, %f17, %f16
23191! preparing store val #2, next val will be in f35
23192fmovd %f20, %f32
23193fmovs %f16, %f21
23194fadds %f16, %f17, %f16
23195fmovd %f20, %f34
23196membar #Sync
23197stda %f32, [%i3 + 0 ] %asi
23198
23199P1786: !_MEMBAR (FP)
23200
23201P1787: !_BSTC [6] (maybe <- 0x4000010b) (FP)
23202wr %g0, 0xe0, %asi
23203sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
23204sub %i0, %i2, %i2
23205! preparing store val #0, next val will be in f32
23206fmovs %f16, %f20
23207fadds %f16, %f17, %f16
23208! preparing store val #1, next val will be in f33
23209fmovs %f16, %f21
23210fadds %f16, %f17, %f16
23211! preparing store val #2, next val will be in f35
23212fmovd %f20, %f32
23213fmovs %f16, %f21
23214fadds %f16, %f17, %f16
23215fmovd %f20, %f34
23216membar #Sync
23217stda %f32, [%i2 + 0 ] %asi
23218
23219P1788: !_MEMBAR (FP)
23220membar #StoreLoad
23221
23222P1789: !_ST_BINIT [5] (maybe <- 0x80012f) (Int)
23223wr %g0, 0xe2, %asi
23224stwa %l4, [%i1 + 12] %asi
23225add %l4, 1, %l4
23226
23227P1790: !_MEMBAR (Int)
23228membar #StoreLoad
23229
23230P1791: !_SWAP [6] (maybe <- 0x800130) (Int)
23231mov %l4, %o4
23232swap [%i2 + 0], %o4
23233! move %o4(lower) -> %o4(upper)
23234sllx %o4, 32, %o4
23235add %l4, 1, %l4
23236
23237P1792: !_MEMBAR (FP)
23238
23239P1793: !_BSTC [1] (maybe <- 0x4000010e) (FP)
23240wr %g0, 0xe0, %asi
23241! preparing store val #0, next val will be in f32
23242fmovs %f16, %f20
23243fadds %f16, %f17, %f16
23244! preparing store val #1, next val will be in f33
23245fmovs %f16, %f21
23246fadds %f16, %f17, %f16
23247! preparing store val #2, next val will be in f35
23248fmovd %f20, %f32
23249fmovs %f16, %f21
23250fadds %f16, %f17, %f16
23251fmovd %f20, %f34
23252membar #Sync
23253stda %f32, [%i0 + 0 ] %asi
23254
23255P1794: !_MEMBAR (FP)
23256membar #StoreLoad
23257
23258P1795: !_DWST [11] (maybe <- 0x800131) (Int)
23259mov %l4, %l7
23260stx %l7, [%i3 + 8]
23261add %l4, 1, %l4
23262
23263P1796: !_CAS [7] (maybe <- 0x800132) (Int)
23264add %i2, 4, %l7
23265lduw [%l7], %l3
23266mov %l3, %l6
23267! move %l6(lower) -> %o4(lower)
23268or %l6, %o4, %o4
23269!---- flushing int results buffer----
23270mov %o0, %l5
23271mov %o1, %l5
23272mov %o2, %l5
23273mov %o3, %l5
23274mov %o4, %l5
23275mov %l4, %o0
23276cas [%l7], %l6, %o0
23277! move %o0(lower) -> %o0(upper)
23278sllx %o0, 32, %o0
23279add %l4, 1, %l4
23280
23281P1797: !_CAS [23] (maybe <- 0x800133) (Int) (Branch target of P1210)
23282sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
23283add %i0, %i3, %i3
23284add %i3, 12, %l7
23285lduw [%l7], %l3
23286mov %l3, %l6
23287! move %l6(lower) -> %o0(lower)
23288or %l6, %o0, %o0
23289mov %l4, %o1
23290cas [%l7], %l6, %o1
23291! move %o1(lower) -> %o1(upper)
23292sllx %o1, 32, %o1
23293add %l4, 1, %l4
23294ba P1798
23295nop
23296
23297TARGET1210:
23298ba RET1210
23299nop
23300
23301
23302P1798: !_MEMBAR (FP)
23303
23304P1799: !_BST [6] (maybe <- 0x40000111) (FP)
23305wr %g0, 0xf0, %asi
23306! preparing store val #0, next val will be in f32
23307fmovs %f16, %f20
23308fadds %f16, %f17, %f16
23309! preparing store val #1, next val will be in f33
23310fmovs %f16, %f21
23311fadds %f16, %f17, %f16
23312! preparing store val #2, next val will be in f35
23313fmovd %f20, %f32
23314fmovs %f16, %f21
23315fadds %f16, %f17, %f16
23316fmovd %f20, %f34
23317membar #Sync
23318stda %f32, [%i2 + 0 ] %asi
23319
23320P1800: !_MEMBAR (FP) (CBR)
23321membar #StoreLoad
23322
23323! cbranch
23324andcc %l0, 1, %g0
23325be,pn %xcc, TARGET1800
23326nop
23327RET1800:
23328
23329! lfsr step begin
23330srlx %l0, 1, %l3
23331xnor %l3, %l0, %l3
23332sllx %l3, 63, %l3
23333or %l3, %l0, %l0
23334srlx %l0, 1, %l0
23335
23336
23337P1801: !_REPLACEMENT [18] (Int) (Branch target of P1259)
23338sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
23339add %i0, %i2, %i2
23340sethi %hi(0x20000), %l6
23341ld [%i2+0], %o5
23342st %o5, [%i2+0]
23343add %i2, %l6, %l7
23344ld [%l7+0], %o5
23345st %o5, [%l7+0]
23346add %l7, %l6, %l7
23347ld [%l7+0], %o5
23348st %o5, [%l7+0]
23349add %l7, %l6, %l7
23350ld [%l7+0], %o5
23351st %o5, [%l7+0]
23352add %l7, %l6, %l7
23353ld [%l7+0], %o5
23354st %o5, [%l7+0]
23355add %l7, %l6, %l7
23356ld [%l7+0], %o5
23357st %o5, [%l7+0]
23358add %l7, %l6, %l7
23359ld [%l7+0], %o5
23360st %o5, [%l7+0]
23361add %l7, %l6, %l7
23362ld [%l7+0], %o5
23363st %o5, [%l7+0]
23364ba P1802
23365nop
23366
23367TARGET1259:
23368ba RET1259
23369nop
23370
23371
23372P1802: !_MEMBAR (FP)
23373
23374P1803: !_BST [6] (maybe <- 0x40000114) (FP)
23375wr %g0, 0xf0, %asi
23376sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
23377sub %i0, %i3, %i3
23378! preparing store val #0, next val will be in f32
23379fmovs %f16, %f20
23380fadds %f16, %f17, %f16
23381! preparing store val #1, next val will be in f33
23382fmovs %f16, %f21
23383fadds %f16, %f17, %f16
23384! preparing store val #2, next val will be in f35
23385fmovd %f20, %f32
23386fmovs %f16, %f21
23387fadds %f16, %f17, %f16
23388fmovd %f20, %f34
23389membar #Sync
23390stda %f32, [%i3 + 0 ] %asi
23391
23392P1804: !_MEMBAR (FP)
23393membar #StoreLoad
23394
23395P1805: !_ST_BINIT [11] (maybe <- 0x800134) (Int)
23396wr %g0, 0xe2, %asi
23397sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
23398add %i0, %i2, %i2
23399stwa %l4, [%i2 + 12] %asi
23400add %l4, 1, %l4
23401
23402P1806: !_MEMBAR (Int)
23403membar #StoreLoad
23404
23405P1807: !_ST_BINIT [12] (maybe <- 0x800135) (Int)
23406wr %g0, 0xe2, %asi
23407sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
23408add %i0, %i3, %i3
23409stwa %l4, [%i3 + 0] %asi
23410add %l4, 1, %l4
23411
23412P1808: !_MEMBAR (Int)
23413membar #StoreLoad
23414
23415P1809: !_PREFETCH [2] (Int)
23416prefetch [%i0 + 12], 23
23417
23418P1810: !_MEMBAR (FP)
23419
23420P1811: !_BST [19] (maybe <- 0x40000117) (FP)
23421wr %g0, 0xf0, %asi
23422sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
23423sub %i0, %i2, %i2
23424! preparing store val #0, next val will be in f32
23425fmovs %f16, %f20
23426fadds %f16, %f17, %f16
23427! preparing store val #1, next val will be in f33
23428fmovs %f16, %f21
23429fadds %f16, %f17, %f16
23430! preparing store val #2, next val will be in f35
23431fmovd %f20, %f32
23432fmovs %f16, %f21
23433fadds %f16, %f17, %f16
23434fmovd %f20, %f34
23435membar #Sync
23436stda %f32, [%i2 + 0 ] %asi
23437
23438P1812: !_MEMBAR (FP)
23439membar #StoreLoad
23440
23441P1813: !_ST_BINIT [22] (maybe <- 0x800136) (Int) (CBR)
23442wr %g0, 0xe2, %asi
23443sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
23444add %i0, %i3, %i3
23445stwa %l4, [%i3 + 4] %asi
23446add %l4, 1, %l4
23447
23448! cbranch
23449andcc %l0, 1, %g0
23450be,pn %xcc, TARGET1813
23451nop
23452RET1813:
23453
23454! lfsr step begin
23455srlx %l0, 1, %o5
23456xnor %o5, %l0, %o5
23457sllx %o5, 63, %o5
23458or %o5, %l0, %l0
23459srlx %l0, 1, %l0
23460
23461
23462P1814: !_MEMBAR (Int)
23463
23464P1815: !_BSTC [0] (maybe <- 0x4000011a) (FP)
23465wr %g0, 0xe0, %asi
23466! preparing store val #0, next val will be in f32
23467fmovs %f16, %f20
23468fadds %f16, %f17, %f16
23469! preparing store val #1, next val will be in f33
23470fmovs %f16, %f21
23471fadds %f16, %f17, %f16
23472! preparing store val #2, next val will be in f35
23473fmovd %f20, %f32
23474fmovs %f16, %f21
23475fadds %f16, %f17, %f16
23476fmovd %f20, %f34
23477membar #Sync
23478stda %f32, [%i0 + 0 ] %asi
23479
23480P1816: !_MEMBAR (FP)
23481membar #StoreLoad
23482
23483P1817: !_CASX [15] (maybe <- 0x800137) (Int)
23484sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
23485sub %i0, %i2, %i2
23486ldx [%i2], %l7
23487! move %l7(upper) -> %o1(lower)
23488srlx %l7, 32, %o5
23489or %o5, %o1, %o1
23490! move %l7(lower) -> %o2(upper)
23491sllx %l7, 32, %o2
23492mov %l7, %o5
23493sllx %l4, 32, %l7
23494add %l4, 1, %l4
23495or %l4, %l7, %l7
23496casx [%i2], %o5, %l7
23497! move %l7(upper) -> %o2(lower)
23498srlx %l7, 32, %o5
23499or %o5, %o2, %o2
23500! move %l7(lower) -> %o3(upper)
23501sllx %l7, 32, %o3
23502add %l4, 1, %l4
23503
23504P1818: !_ST [23] (maybe <- 0x800139) (Int)
23505stw %l4, [%i3 + 12 ]
23506add %l4, 1, %l4
23507
23508P1819: !_LDD [0] (Int)
23509ldd [%i0 + 0], %l6
23510! move %l6(lower) -> %o3(lower)
23511or %l6, %o3, %o3
23512! move %l7(lower) -> %o4(upper)
23513sllx %l7, 32, %o4
23514
23515P1820: !_CASX [4] (maybe <- 0x80013a) (Int)
23516ldx [%i1], %o5
23517! move %o5(upper) -> %o4(lower)
23518srlx %o5, 32, %l3
23519or %l3, %o4, %o4
23520!---- flushing int results buffer----
23521mov %o0, %l5
23522mov %o1, %l5
23523mov %o2, %l5
23524mov %o3, %l5
23525mov %o4, %l5
23526! move %o5(lower) -> %o0(upper)
23527sllx %o5, 32, %o0
23528mov %o5, %l3
23529sllx %l4, 32, %o5
23530add %l4, 1, %l4
23531or %l4, %o5, %o5
23532casx [%i1], %l3, %o5
23533! move %o5(upper) -> %o0(lower)
23534srlx %o5, 32, %l3
23535or %l3, %o0, %o0
23536! move %o5(lower) -> %o1(upper)
23537sllx %o5, 32, %o1
23538add %l4, 1, %l4
23539
23540P1821: !_MEMBAR (FP)
23541
23542P1822: !_BST [8] (maybe <- 0x4000011d) (FP)
23543wr %g0, 0xf0, %asi
23544sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
23545sub %i0, %i3, %i3
23546! preparing store val #0, next val will be in f32
23547fmovs %f16, %f20
23548fadds %f16, %f17, %f16
23549! preparing store val #1, next val will be in f33
23550fmovs %f16, %f21
23551fadds %f16, %f17, %f16
23552! preparing store val #2, next val will be in f35
23553fmovd %f20, %f32
23554fmovs %f16, %f21
23555fadds %f16, %f17, %f16
23556fmovd %f20, %f34
23557membar #Sync
23558stda %f32, [%i3 + 0 ] %asi
23559
23560P1823: !_MEMBAR (FP)
23561membar #StoreLoad
23562
23563P1824: !_PREFETCH [12] (Int)
23564sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
23565add %i0, %i2, %i2
23566prefetch [%i2 + 0], 4
23567
23568P1825: !_CAS [8] (maybe <- 0x80013c) (Int)
23569add %i3, 12, %l3
23570lduw [%l3], %l7
23571mov %l7, %o5
23572! move %o5(lower) -> %o1(lower)
23573or %o5, %o1, %o1
23574mov %l4, %o2
23575cas [%l3], %o5, %o2
23576! move %o2(lower) -> %o2(upper)
23577sllx %o2, 32, %o2
23578add %l4, 1, %l4
23579
23580P1826: !_MEMBAR (FP)
23581
23582P1827: !_BST [22] (maybe <- 0x40000120) (FP)
23583wr %g0, 0xf0, %asi
23584sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
23585add %i0, %i3, %i3
23586! preparing store val #0, next val will be in f32
23587fmovs %f16, %f20
23588fadds %f16, %f17, %f16
23589! preparing store val #1, next val will be in f33
23590fmovs %f16, %f21
23591fadds %f16, %f17, %f16
23592! preparing store val #2, next val will be in f35
23593fmovd %f20, %f32
23594fmovs %f16, %f21
23595fadds %f16, %f17, %f16
23596fmovd %f20, %f34
23597membar #Sync
23598stda %f32, [%i3 + 0 ] %asi
23599
23600P1828: !_MEMBAR (FP)
23601
23602P1829: !_BSTC [12] (maybe <- 0x40000123) (FP)
23603wr %g0, 0xe0, %asi
23604! preparing store val #0, next val will be in f32
23605fmovs %f16, %f20
23606fadds %f16, %f17, %f16
23607! preparing store val #1, next val will be in f33
23608fmovs %f16, %f21
23609fadds %f16, %f17, %f16
23610! preparing store val #2, next val will be in f35
23611fmovd %f20, %f32
23612fmovs %f16, %f21
23613fadds %f16, %f17, %f16
23614fmovd %f20, %f34
23615membar #Sync
23616stda %f32, [%i2 + 0 ] %asi
23617
23618P1830: !_MEMBAR (FP)
23619membar #StoreLoad
23620
23621P1831: !_LDD [19] (Int)
23622sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
23623sub %i0, %i2, %i2
23624ldd [%i2 + 0], %l6
23625! move %l6(lower) -> %o2(lower)
23626or %l6, %o2, %o2
23627! move %l7(lower) -> %o3(upper)
23628sllx %l7, 32, %o3
23629
23630P1832: !_ST [0] (maybe <- 0x40000126) (FP)
23631! preparing store val #0, next val will be in f20
23632fmovs %f16, %f20
23633fadds %f16, %f17, %f16
23634st %f20, [%i0 + 0 ]
23635
23636P1833: !_MEMBAR (FP)
23637
23638P1834: !_BST [13] (maybe <- 0x40000127) (FP)
23639wr %g0, 0xf0, %asi
23640sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
23641add %i0, %i3, %i3
23642! preparing store val #0, next val will be in f32
23643fmovs %f16, %f20
23644fadds %f16, %f17, %f16
23645! preparing store val #1, next val will be in f33
23646fmovs %f16, %f21
23647fadds %f16, %f17, %f16
23648! preparing store val #2, next val will be in f35
23649fmovd %f20, %f32
23650fmovs %f16, %f21
23651fadds %f16, %f17, %f16
23652fmovd %f20, %f34
23653membar #Sync
23654stda %f32, [%i3 + 0 ] %asi
23655
23656P1835: !_MEMBAR (FP)
23657membar #StoreLoad
23658
23659P1836: !_PREFETCH [23] (Int)
23660sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
23661add %i0, %i2, %i2
23662prefetch [%i2 + 12], 1
23663
23664P1837: !_CASX [16] (maybe <- 0x80013d) (Int) (Branch target of P1590)
23665sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
23666sub %i0, %i3, %i3
23667ldx [%i3], %l7
23668! move %l7(upper) -> %o3(lower)
23669srlx %l7, 32, %o5
23670or %o5, %o3, %o3
23671! move %l7(lower) -> %o4(upper)
23672sllx %l7, 32, %o4
23673mov %l7, %o5
23674sllx %l4, 32, %l7
23675add %l4, 1, %l4
23676or %l4, %l7, %l7
23677casx [%i3], %o5, %l7
23678! move %l7(upper) -> %o4(lower)
23679srlx %l7, 32, %o5
23680or %o5, %o4, %o4
23681!---- flushing int results buffer----
23682mov %o0, %l5
23683mov %o1, %l5
23684mov %o2, %l5
23685mov %o3, %l5
23686mov %o4, %l5
23687! move %l7(lower) -> %o0(upper)
23688sllx %l7, 32, %o0
23689add %l4, 1, %l4
23690ba P1838
23691nop
23692
23693TARGET1590:
23694ba RET1590
23695nop
23696
23697
23698P1838: !_SWAP [10] (maybe <- 0x80013f) (Int)
23699sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
23700add %i0, %i2, %i2
23701mov %l4, %l6
23702swap [%i2 + 4], %l6
23703! move %l6(lower) -> %o0(lower)
23704srl %l6, 0, %o5
23705or %o5, %o0, %o0
23706add %l4, 1, %l4
23707
23708P1839: !_SWAP [12] (maybe <- 0x800140) (Int)
23709sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
23710add %i0, %i3, %i3
23711mov %l4, %o1
23712swap [%i3 + 0], %o1
23713! move %o1(lower) -> %o1(upper)
23714sllx %o1, 32, %o1
23715add %l4, 1, %l4
23716
23717P1840: !_CAS [12] (maybe <- 0x800141) (Int) (CBR)
23718lduw [%i3], %l3
23719mov %l3, %l6
23720! move %l6(lower) -> %o1(lower)
23721or %l6, %o1, %o1
23722mov %l4, %o2
23723cas [%i3], %l6, %o2
23724! move %o2(lower) -> %o2(upper)
23725sllx %o2, 32, %o2
23726add %l4, 1, %l4
23727
23728! cbranch
23729andcc %l0, 1, %g0
23730be,pt %xcc, TARGET1840
23731nop
23732RET1840:
23733
23734! lfsr step begin
23735srlx %l0, 1, %l6
23736xnor %l6, %l0, %l6
23737sllx %l6, 63, %l6
23738or %l6, %l0, %l0
23739srlx %l0, 1, %l0
23740
23741
23742P1841: !_PREFETCH [19] (Int) (CBR)
23743sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
23744sub %i0, %i2, %i2
23745prefetch [%i2 + 4], 18
23746
23747! cbranch
23748andcc %l0, 1, %g0
23749be,pn %xcc, TARGET1841
23750nop
23751RET1841:
23752
23753! lfsr step begin
23754srlx %l0, 1, %l7
23755xnor %l7, %l0, %l7
23756sllx %l7, 63, %l7
23757or %l7, %l0, %l0
23758srlx %l0, 1, %l0
23759
23760
23761P1842: !_CAS [9] (maybe <- 0x800142) (Int)
23762sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
23763add %i0, %i3, %i3
23764lduw [%i3], %l7
23765mov %l7, %o5
23766! move %o5(lower) -> %o2(lower)
23767or %o5, %o2, %o2
23768mov %l4, %o3
23769cas [%i3], %o5, %o3
23770! move %o3(lower) -> %o3(upper)
23771sllx %o3, 32, %o3
23772add %l4, 1, %l4
23773
23774P1843: !_LDD [1] (Int) (LE)
23775wr %g0, 0x88, %asi
23776ldda [%i0 + 0] %asi, %l6
23777! move %l6(lower) -> %o3(lower)
23778or %l6, %o3, %o3
23779! move %l7(lower) -> %o4(upper)
23780sllx %l7, 32, %o4
23781
23782P1844: !_DWST_BINIT [19] (maybe <- 0x800143) (Int)
23783wr %g0, 0xe2, %asi
23784sllx %l4, 32, %l3
23785add %l4, 1, %l4
23786or %l3, %l4, %l3
23787stxa %l3, [%i2 + 0] %asi
23788add %l4, 1, %l4
23789
23790P1845: !_MEMBAR (Int)
23791membar #StoreLoad
23792
23793P1846: !_DWLD [4] (Int)
23794ldx [%i1 + 0], %l3
23795! move %l3(upper) -> %o4(lower)
23796srlx %l3, 32, %o5
23797or %o5, %o4, %o4
23798!---- flushing int results buffer----
23799mov %o0, %l5
23800mov %o1, %l5
23801mov %o2, %l5
23802mov %o3, %l5
23803mov %o4, %l5
23804! move %l3(lower) -> %o0(upper)
23805sllx %l3, 32, %o0
23806
23807P1847: !_SWAP [17] (maybe <- 0x800145) (Int)
23808sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
23809sub %i0, %i2, %i2
23810mov %l4, %o5
23811swap [%i2 + 12], %o5
23812! move %o5(lower) -> %o0(lower)
23813srl %o5, 0, %l6
23814or %l6, %o0, %o0
23815add %l4, 1, %l4
23816
23817P1848: !_MEMBAR (FP)
23818
23819P1849: !_BST [17] (maybe <- 0x4000012a) (FP)
23820wr %g0, 0xf0, %asi
23821! preparing store val #0, next val will be in f32
23822fmovs %f16, %f20
23823fadds %f16, %f17, %f16
23824! preparing store val #1, next val will be in f33
23825fmovs %f16, %f21
23826fadds %f16, %f17, %f16
23827! preparing store val #2, next val will be in f35
23828fmovd %f20, %f32
23829fmovs %f16, %f21
23830fadds %f16, %f17, %f16
23831fmovd %f20, %f34
23832membar #Sync
23833stda %f32, [%i2 + 0 ] %asi
23834
23835P1850: !_MEMBAR (FP)
23836
23837P1851: !_BSTC [2] (maybe <- 0x4000012d) (FP)
23838wr %g0, 0xe0, %asi
23839! preparing store val #0, next val will be in f32
23840fmovs %f16, %f20
23841fadds %f16, %f17, %f16
23842! preparing store val #1, next val will be in f33
23843fmovs %f16, %f21
23844fadds %f16, %f17, %f16
23845! preparing store val #2, next val will be in f35
23846fmovd %f20, %f32
23847fmovs %f16, %f21
23848fadds %f16, %f17, %f16
23849fmovd %f20, %f34
23850membar #Sync
23851stda %f32, [%i0 + 0 ] %asi
23852
23853P1852: !_MEMBAR (FP)
23854membar #StoreLoad
23855
23856P1853: !_BLD [13] (FP)
23857wr %g0, 0xf0, %asi
23858sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
23859add %i0, %i3, %i3
23860ldda [%i3 + 0] %asi, %f32
23861membar #Sync
23862! 3 addresses covered
23863fmovd %f32, %f12
23864fmovd %f34, %f18
23865fmovs %f19, %f14
23866
23867P1854: !_MEMBAR (FP)
23868
23869P1855: !_DWST_BINIT [0] (maybe <- 0x800146) (Int)
23870wr %g0, 0xe2, %asi
23871sllx %l4, 32, %l7
23872add %l4, 1, %l4
23873or %l7, %l4, %l7
23874stxa %l7, [%i0 + 0] %asi
23875add %l4, 1, %l4
23876
23877P1856: !_MEMBAR (Int)
23878membar #StoreLoad
23879
23880P1857: !_ST_BINIT [4] (maybe <- 0x800148) (Int) (Branch target of P1290)
23881wr %g0, 0xe2, %asi
23882stwa %l4, [%i1 + 4] %asi
23883add %l4, 1, %l4
23884ba P1858
23885nop
23886
23887TARGET1290:
23888ba RET1290
23889nop
23890
23891
23892P1858: !_MEMBAR (Int)
23893membar #StoreLoad
23894
23895P1859: !_CAS [16] (maybe <- 0x800149) (Int)
23896add %i2, 4, %l6
23897lduw [%l6], %o1
23898mov %o1, %l3
23899! move %l3(lower) -> %o1(upper)
23900sllx %l3, 32, %o1
23901mov %l4, %o5
23902cas [%l6], %l3, %o5
23903! move %o5(lower) -> %o1(lower)
23904srl %o5, 0, %l3
23905or %l3, %o1, %o1
23906add %l4, 1, %l4
23907
23908P1860: !_DWST_BINIT [22] (maybe <- 0x80014a) (Int)
23909wr %g0, 0xe2, %asi
23910sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
23911add %i0, %i2, %i2
23912sllx %l4, 32, %l3
23913add %l4, 1, %l4
23914or %l3, %l4, %l3
23915stxa %l3, [%i2 + 0] %asi
23916add %l4, 1, %l4
23917
23918P1861: !_MEMBAR (Int)
23919membar #StoreLoad
23920
23921P1862: !_LDD [17] (Int)
23922sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
23923sub %i0, %i3, %i3
23924ldd [%i3 + 8], %l6
23925! move %l7(lower) -> %o2(upper)
23926sllx %l7, 32, %o2
23927
23928P1863: !_ST [0] (maybe <- 0x80014c) (Int)
23929stw %l4, [%i0 + 0 ]
23930add %l4, 1, %l4
23931
23932P1864: !_DWST [15] (maybe <- 0x80014d) (Int)
23933sllx %l4, 32, %o5
23934add %l4, 1, %l4
23935or %o5, %l4, %o5
23936stx %o5, [%i3 + 0]
23937add %l4, 1, %l4
23938
23939P1865: !_MEMBAR (FP)
23940membar #StoreLoad
23941
23942P1866: !_BLD [11] (FP)
23943wr %g0, 0xf0, %asi
23944sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
23945add %i0, %i2, %i2
23946ldda [%i2 + 0] %asi, %f32
23947membar #Sync
23948! 3 addresses covered
23949fmovd %f32, %f18
23950fmovs %f18, %f15
23951!---- flushing fp results buffer to %f30 ----
23952fmovd %f0, %f30
23953fmovd %f2, %f30
23954fmovd %f4, %f30
23955fmovd %f6, %f30
23956fmovd %f8, %f30
23957fmovd %f10, %f30
23958fmovd %f12, %f30
23959fmovd %f14, %f30
23960!--
23961fmovs %f19, %f0
23962fmovd %f34, %f18
23963fmovs %f19, %f1
23964
23965P1867: !_MEMBAR (FP)
23966
23967P1868: !_BSTC [21] (maybe <- 0x40000130) (FP)
23968wr %g0, 0xe0, %asi
23969sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
23970add %i0, %i3, %i3
23971! preparing store val #0, next val will be in f32
23972fmovs %f16, %f20
23973fadds %f16, %f17, %f16
23974! preparing store val #1, next val will be in f33
23975fmovs %f16, %f21
23976fadds %f16, %f17, %f16
23977! preparing store val #2, next val will be in f35
23978fmovd %f20, %f32
23979fmovs %f16, %f21
23980fadds %f16, %f17, %f16
23981fmovd %f20, %f34
23982membar #Sync
23983stda %f32, [%i3 + 0 ] %asi
23984
23985P1869: !_MEMBAR (FP)
23986membar #StoreLoad
23987
23988P1870: !_ST [20] (maybe <- 0x80014f) (Int)
23989sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
23990sub %i0, %i2, %i2
23991stw %l4, [%i2 + 12 ]
23992add %l4, 1, %l4
23993
23994P1871: !_PREFETCH [22] (Int)
23995prefetch [%i3 + 4], 20
23996
23997P1872: !_MEMBAR (FP)
23998membar #StoreLoad
23999
24000P1873: !_BLD [16] (FP)
24001wr %g0, 0xf0, %asi
24002sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
24003sub %i0, %i3, %i3
24004ldda [%i3 + 0] %asi, %f32
24005membar #Sync
24006! 3 addresses covered
24007fmovd %f32, %f2
24008fmovd %f34, %f18
24009fmovs %f19, %f4
24010
24011P1874: !_MEMBAR (FP)
24012
24013P1875: !_LDD [19] (Int)
24014ldd [%i2 + 0], %l6
24015! move %l6(lower) -> %o2(lower)
24016or %l6, %o2, %o2
24017! move %l7(lower) -> %o3(upper)
24018sllx %l7, 32, %o3
24019
24020P1876: !_CAS [10] (maybe <- 0x800150) (Int)
24021sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
24022add %i0, %i2, %i2
24023add %i2, 4, %l6
24024lduw [%l6], %o5
24025mov %o5, %l3
24026! move %l3(lower) -> %o3(lower)
24027or %l3, %o3, %o3
24028mov %l4, %o4
24029cas [%l6], %l3, %o4
24030! move %o4(lower) -> %o4(upper)
24031sllx %o4, 32, %o4
24032add %l4, 1, %l4
24033
24034P1877: !_MEMBAR (FP)
24035
24036P1878: !_BSTC [12] (maybe <- 0x40000133) (FP)
24037wr %g0, 0xe0, %asi
24038sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
24039add %i0, %i3, %i3
24040! preparing store val #0, next val will be in f32
24041fmovs %f16, %f20
24042fadds %f16, %f17, %f16
24043! preparing store val #1, next val will be in f33
24044fmovs %f16, %f21
24045fadds %f16, %f17, %f16
24046! preparing store val #2, next val will be in f35
24047fmovd %f20, %f32
24048fmovs %f16, %f21
24049fadds %f16, %f17, %f16
24050fmovd %f20, %f34
24051membar #Sync
24052stda %f32, [%i3 + 0 ] %asi
24053
24054P1879: !_MEMBAR (FP)
24055membar #StoreLoad
24056
24057P1880: !_BLD [4] (FP)
24058wr %g0, 0xf0, %asi
24059ldda [%i1 + 0] %asi, %f32
24060membar #Sync
24061! 3 addresses covered
24062fmovd %f32, %f18
24063fmovs %f18, %f5
24064fmovs %f19, %f6
24065fmovd %f34, %f18
24066fmovs %f19, %f7
24067
24068P1881: !_MEMBAR (FP)
24069
24070P1882: !_LD [6] (Int)
24071sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
24072sub %i0, %i2, %i2
24073lduw [%i2 + 0], %l3
24074! move %l3(lower) -> %o4(lower)
24075or %l3, %o4, %o4
24076!---- flushing int results buffer----
24077mov %o0, %l5
24078mov %o1, %l5
24079mov %o2, %l5
24080mov %o3, %l5
24081mov %o4, %l5
24082
24083P1883: !_LDD [1] (Int)
24084ldd [%i0 + 0], %l6
24085! move %l6(lower) -> %o0(upper)
24086sllx %l6, 32, %o0
24087! move %l7(lower) -> %o0(lower)
24088or %l7, %o0, %o0
24089
24090P1884: !_MEMBAR (FP)
24091
24092P1885: !_BSTC [17] (maybe <- 0x40000136) (FP)
24093wr %g0, 0xe0, %asi
24094sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
24095sub %i0, %i3, %i3
24096! preparing store val #0, next val will be in f32
24097fmovs %f16, %f20
24098fadds %f16, %f17, %f16
24099! preparing store val #1, next val will be in f33
24100fmovs %f16, %f21
24101fadds %f16, %f17, %f16
24102! preparing store val #2, next val will be in f35
24103fmovd %f20, %f32
24104fmovs %f16, %f21
24105fadds %f16, %f17, %f16
24106fmovd %f20, %f34
24107membar #Sync
24108stda %f32, [%i3 + 0 ] %asi
24109
24110P1886: !_MEMBAR (FP)
24111membar #StoreLoad
24112
24113P1887: !_DWLD [21] (Int)
24114sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
24115add %i0, %i2, %i2
24116ldx [%i2 + 0], %o1
24117! move %o1(upper) -> %o1(upper)
24118! move %o1(lower) -> %o1(lower)
24119
24120P1888: !_CAS [17] (maybe <- 0x800151) (Int) (LE)
24121! Change single-word-level endianess (big endian <-> little endian)
24122sethi %hi(0xff00ff00), %l7
24123or %l7, %lo(0xff00ff00), %l7
24124and %l4, %l7, %l6
24125srl %l6, 8, %l6
24126sll %l4, 8, %o5
24127and %o5, %l7, %o5
24128or %o5, %l6, %o5
24129srl %o5, 16, %l6
24130sll %o5, 16, %o5
24131srl %o5, 0, %o5
24132or %o5, %l6, %o5
24133wr %g0, 0x88, %asi
24134add %i3, 12, %l7
24135lduwa [%l7] %asi, %o2
24136mov %o2, %l6
24137! move %l6(lower) -> %o2(upper)
24138sllx %l6, 32, %o2
24139mov %o5, %l3
24140casa [%l7] %asi, %l6, %l3
24141! move %l3(lower) -> %o2(lower)
24142srl %l3, 0, %l6
24143or %l6, %o2, %o2
24144add %l4, 1, %l4
24145
24146P1889: !_CASX [18] (maybe <- 0x800152) (Int)
24147sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
24148sub %i0, %i3, %i3
24149ldx [%i3], %o3
24150! move %o3(upper) -> %o3(upper)
24151! move %o3(lower) -> %o3(lower)
24152mov %o3, %l6
24153sllx %l4, 32, %o4
24154add %l4, 1, %l4
24155or %l4, %o4, %o4
24156casx [%i3], %l6, %o4
24157! move %o4(upper) -> %o4(upper)
24158! move %o4(lower) -> %o4(lower)
24159!---- flushing int results buffer----
24160mov %o0, %l5
24161mov %o1, %l5
24162mov %o2, %l5
24163mov %o3, %l5
24164mov %o4, %l5
24165add %l4, 1, %l4
24166
24167P1890: !_LDD [16] (Int)
24168sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
24169sub %i0, %i2, %i2
24170ldd [%i2 + 0], %l6
24171! move %l6(lower) -> %o0(upper)
24172sllx %l6, 32, %o0
24173! move %l7(lower) -> %o0(lower)
24174or %l7, %o0, %o0
24175
24176P1891: !_MEMBAR (FP)
24177membar #StoreLoad
24178
24179P1892: !_BLD [3] (FP)
24180wr %g0, 0xf0, %asi
24181ldda [%i1 + 0] %asi, %f32
24182membar #Sync
24183! 3 addresses covered
24184fmovd %f32, %f8
24185fmovd %f34, %f18
24186fmovs %f19, %f10
24187
24188P1893: !_MEMBAR (FP)
24189
24190P1894: !_ST [17] (maybe <- 0x800154) (Int)
24191stw %l4, [%i2 + 12 ]
24192add %l4, 1, %l4
24193
24194P1895: !_CAS [1] (maybe <- 0x800155) (Int)
24195add %i0, 4, %l3
24196lduw [%l3], %o1
24197mov %o1, %o5
24198! move %o5(lower) -> %o1(upper)
24199sllx %o5, 32, %o1
24200mov %l4, %l7
24201cas [%l3], %o5, %l7
24202! move %l7(lower) -> %o1(lower)
24203srl %l7, 0, %o5
24204or %o5, %o1, %o1
24205add %l4, 1, %l4
24206
24207P1896: !_SWAP [20] (maybe <- 0x800156) (Int)
24208mov %l4, %o2
24209swap [%i3 + 12], %o2
24210! move %o2(lower) -> %o2(upper)
24211sllx %o2, 32, %o2
24212add %l4, 1, %l4
24213
24214P1897: !_CAS [22] (maybe <- 0x800157) (Int)
24215sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
24216sub %i0, %i3, %i3
24217add %i3, 4, %l3
24218lduw [%l3], %l7
24219mov %l7, %o5
24220! move %o5(lower) -> %o2(lower)
24221or %o5, %o2, %o2
24222mov %l4, %o3
24223cas [%l3], %o5, %o3
24224! move %o3(lower) -> %o3(upper)
24225sllx %o3, 32, %o3
24226add %l4, 1, %l4
24227
24228P1898: !_LDD [5] (Int)
24229ldd [%i1 + 8], %l6
24230! move %l7(lower) -> %o3(lower)
24231or %l7, %o3, %o3
24232
24233P1899: !_CASX [22] (maybe <- 0x800158) (Int)
24234ldx [%i3], %o4
24235! move %o4(upper) -> %o4(upper)
24236! move %o4(lower) -> %o4(lower)
24237!---- flushing int results buffer----
24238mov %o0, %l5
24239mov %o1, %l5
24240mov %o2, %l5
24241mov %o3, %l5
24242mov %o4, %l5
24243mov %o4, %l3
24244sllx %l4, 32, %o0
24245add %l4, 1, %l4
24246or %l4, %o0, %o0
24247casx [%i3], %l3, %o0
24248! move %o0(upper) -> %o0(upper)
24249! move %o0(lower) -> %o0(lower)
24250add %l4, 1, %l4
24251
24252P1900: !_LDD [16] (Int)
24253ldd [%i2 + 0], %l6
24254! move %l6(lower) -> %o1(upper)
24255sllx %l6, 32, %o1
24256! move %l7(lower) -> %o1(lower)
24257or %l7, %o1, %o1
24258
24259P1901: !_MEMBAR (FP)
24260
24261P1902: !_BST [6] (maybe <- 0x40000139) (FP)
24262wr %g0, 0xf0, %asi
24263sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
24264sub %i0, %i2, %i2
24265! preparing store val #0, next val will be in f32
24266fmovs %f16, %f20
24267fadds %f16, %f17, %f16
24268! preparing store val #1, next val will be in f33
24269fmovs %f16, %f21
24270fadds %f16, %f17, %f16
24271! preparing store val #2, next val will be in f35
24272fmovd %f20, %f32
24273fmovs %f16, %f21
24274fadds %f16, %f17, %f16
24275fmovd %f20, %f34
24276membar #Sync
24277stda %f32, [%i2 + 0 ] %asi
24278
24279P1903: !_MEMBAR (FP)
24280
24281P1904: !_BST [0] (maybe <- 0x4000013c) (FP)
24282wr %g0, 0xf0, %asi
24283! preparing store val #0, next val will be in f32
24284fmovs %f16, %f20
24285fadds %f16, %f17, %f16
24286! preparing store val #1, next val will be in f33
24287fmovs %f16, %f21
24288fadds %f16, %f17, %f16
24289! preparing store val #2, next val will be in f35
24290fmovd %f20, %f32
24291fmovs %f16, %f21
24292fadds %f16, %f17, %f16
24293fmovd %f20, %f34
24294membar #Sync
24295stda %f32, [%i0 + 0 ] %asi
24296
24297P1905: !_MEMBAR (FP)
24298membar #StoreLoad
24299
24300P1906: !_BLD [23] (FP)
24301wr %g0, 0xf0, %asi
24302ldda [%i3 + 0] %asi, %f32
24303membar #Sync
24304! 3 addresses covered
24305fmovd %f32, %f18
24306fmovs %f18, %f11
24307fmovs %f19, %f12
24308fmovd %f34, %f18
24309fmovs %f19, %f13
24310
24311P1907: !_MEMBAR (FP)
24312
24313P1908: !_LD [13] (Int) (CBR)
24314sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
24315add %i0, %i3, %i3
24316lduw [%i3 + 4], %o2
24317! move %o2(lower) -> %o2(upper)
24318sllx %o2, 32, %o2
24319
24320! cbranch
24321andcc %l0, 1, %g0
24322be,pt %xcc, TARGET1908
24323nop
24324RET1908:
24325
24326! lfsr step begin
24327srlx %l0, 1, %l3
24328xnor %l3, %l0, %l3
24329sllx %l3, 63, %l3
24330or %l3, %l0, %l0
24331srlx %l0, 1, %l0
24332
24333
24334P1909: !_PREFETCH [21] (Int)
24335sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
24336sub %i0, %i2, %i2
24337prefetch [%i2 + 0], 4
24338
24339P1910: !_MEMBAR (FP)
24340
24341P1911: !_BST [2] (maybe <- 0x4000013f) (FP)
24342wr %g0, 0xf0, %asi
24343! preparing store val #0, next val will be in f32
24344fmovs %f16, %f20
24345fadds %f16, %f17, %f16
24346! preparing store val #1, next val will be in f33
24347fmovs %f16, %f21
24348fadds %f16, %f17, %f16
24349! preparing store val #2, next val will be in f35
24350fmovd %f20, %f32
24351fmovs %f16, %f21
24352fadds %f16, %f17, %f16
24353fmovd %f20, %f34
24354membar #Sync
24355stda %f32, [%i0 + 0 ] %asi
24356
24357P1912: !_MEMBAR (FP)
24358membar #StoreLoad
24359
24360P1913: !_DWST [0] (maybe <- 0x80015a) (Int)
24361sllx %l4, 32, %l3
24362add %l4, 1, %l4
24363or %l3, %l4, %l3
24364stx %l3, [%i0 + 0]
24365add %l4, 1, %l4
24366
24367P1914: !_MEMBAR (FP)
24368
24369P1915: !_BSTC [16] (maybe <- 0x40000142) (FP)
24370wr %g0, 0xe0, %asi
24371sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
24372sub %i0, %i3, %i3
24373! preparing store val #0, next val will be in f32
24374fmovs %f16, %f20
24375fadds %f16, %f17, %f16
24376! preparing store val #1, next val will be in f33
24377fmovs %f16, %f21
24378fadds %f16, %f17, %f16
24379! preparing store val #2, next val will be in f35
24380fmovd %f20, %f32
24381fmovs %f16, %f21
24382fadds %f16, %f17, %f16
24383fmovd %f20, %f34
24384membar #Sync
24385stda %f32, [%i3 + 0 ] %asi
24386
24387P1916: !_MEMBAR (FP)
24388
24389P1917: !_BSTC [18] (maybe <- 0x40000145) (FP)
24390wr %g0, 0xe0, %asi
24391sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
24392sub %i0, %i2, %i2
24393! preparing store val #0, next val will be in f32
24394fmovs %f16, %f20
24395fadds %f16, %f17, %f16
24396! preparing store val #1, next val will be in f33
24397fmovs %f16, %f21
24398fadds %f16, %f17, %f16
24399! preparing store val #2, next val will be in f35
24400fmovd %f20, %f32
24401fmovs %f16, %f21
24402fadds %f16, %f17, %f16
24403fmovd %f20, %f34
24404membar #Sync
24405stda %f32, [%i2 + 0 ] %asi
24406
24407P1918: !_MEMBAR (FP)
24408membar #StoreLoad
24409
24410P1919: !_CASX [11] (maybe <- 0x80015c) (Int)
24411sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
24412add %i0, %i3, %i3
24413add %i3, 8, %l7
24414ldx [%l7], %l3
24415! move %l3(upper) -> %o2(lower)
24416srlx %l3, 32, %l6
24417or %l6, %o2, %o2
24418! move %l3(lower) -> %o3(upper)
24419sllx %l3, 32, %o3
24420mov %l3, %l6
24421mov %l4, %l3
24422casx [%l7], %l6, %l3
24423! move %l3(upper) -> %o3(lower)
24424srlx %l3, 32, %l6
24425or %l6, %o3, %o3
24426! move %l3(lower) -> %o4(upper)
24427sllx %l3, 32, %o4
24428add %l4, 1, %l4
24429
24430P1920: !_SWAP [2] (maybe <- 0x80015d) (Int)
24431mov %l4, %o5
24432swap [%i0 + 12], %o5
24433! move %o5(lower) -> %o4(lower)
24434srl %o5, 0, %l6
24435or %l6, %o4, %o4
24436!---- flushing int results buffer----
24437mov %o0, %l5
24438mov %o1, %l5
24439mov %o2, %l5
24440mov %o3, %l5
24441mov %o4, %l5
24442add %l4, 1, %l4
24443
24444P1921: !_LD [22] (Int)
24445sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
24446sub %i0, %i2, %i2
24447lduw [%i2 + 4], %o0
24448! move %o0(lower) -> %o0(upper)
24449sllx %o0, 32, %o0
24450
24451P1922: !_MEMBAR (FP)
24452membar #StoreLoad
24453
24454P1923: !_BLD [18] (FP)
24455wr %g0, 0xf0, %asi
24456sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
24457sub %i0, %i3, %i3
24458ldda [%i3 + 0] %asi, %f32
24459membar #Sync
24460! 3 addresses covered
24461fmovd %f32, %f14
24462!---- flushing fp results buffer to %f30 ----
24463fmovd %f0, %f30
24464fmovd %f2, %f30
24465fmovd %f4, %f30
24466fmovd %f6, %f30
24467fmovd %f8, %f30
24468fmovd %f10, %f30
24469fmovd %f12, %f30
24470fmovd %f14, %f30
24471!--
24472fmovd %f34, %f18
24473fmovs %f19, %f0
24474
24475P1924: !_MEMBAR (FP)
24476
24477P1925: !_CASX [15] (maybe <- 0x80015e) (Int)
24478sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
24479sub %i0, %i2, %i2
24480ldx [%i2], %l6
24481! move %l6(upper) -> %o0(lower)
24482srlx %l6, 32, %l7
24483or %l7, %o0, %o0
24484! move %l6(lower) -> %o1(upper)
24485sllx %l6, 32, %o1
24486mov %l6, %l7
24487sllx %l4, 32, %l6
24488add %l4, 1, %l4
24489or %l4, %l6, %l6
24490casx [%i2], %l7, %l6
24491! move %l6(upper) -> %o1(lower)
24492srlx %l6, 32, %l7
24493or %l7, %o1, %o1
24494! move %l6(lower) -> %o2(upper)
24495sllx %l6, 32, %o2
24496add %l4, 1, %l4
24497
24498P1926: !_SWAP [18] (maybe <- 0x800160) (Int)
24499mov %l4, %l3
24500swap [%i3 + 0], %l3
24501! move %l3(lower) -> %o2(lower)
24502srl %l3, 0, %l7
24503or %l7, %o2, %o2
24504add %l4, 1, %l4
24505
24506P1927: !_LDD [22] (Int)
24507sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
24508sub %i0, %i3, %i3
24509ldd [%i3 + 0], %l6
24510! move %l6(lower) -> %o3(upper)
24511sllx %l6, 32, %o3
24512! move %l7(lower) -> %o3(lower)
24513or %l7, %o3, %o3
24514
24515P1928: !_LD [1] (Int)
24516lduw [%i0 + 4], %o4
24517! move %o4(lower) -> %o4(upper)
24518sllx %o4, 32, %o4
24519
24520P1929: !_ST [10] (maybe <- 0x800161) (Int) (CBR)
24521sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
24522add %i0, %i2, %i2
24523stw %l4, [%i2 + 4 ]
24524add %l4, 1, %l4
24525
24526! cbranch
24527andcc %l0, 1, %g0
24528be,pn %xcc, TARGET1929
24529nop
24530RET1929:
24531
24532! lfsr step begin
24533srlx %l0, 1, %l6
24534xnor %l6, %l0, %l6
24535sllx %l6, 63, %l6
24536or %l6, %l0, %l0
24537srlx %l0, 1, %l0
24538
24539
24540P1930: !_MEMBAR (FP)
24541
24542P1931: !_BST [12] (maybe <- 0x40000148) (FP)
24543wr %g0, 0xf0, %asi
24544sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
24545add %i0, %i3, %i3
24546! preparing store val #0, next val will be in f32
24547fmovs %f16, %f20
24548fadds %f16, %f17, %f16
24549! preparing store val #1, next val will be in f33
24550fmovs %f16, %f21
24551fadds %f16, %f17, %f16
24552! preparing store val #2, next val will be in f35
24553fmovd %f20, %f32
24554fmovs %f16, %f21
24555fadds %f16, %f17, %f16
24556fmovd %f20, %f34
24557membar #Sync
24558stda %f32, [%i3 + 0 ] %asi
24559
24560P1932: !_MEMBAR (FP)
24561membar #StoreLoad
24562
24563P1933: !_CAS [8] (maybe <- 0x800162) (Int)
24564sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
24565sub %i0, %i2, %i2
24566add %i2, 12, %l7
24567lduw [%l7], %l3
24568mov %l3, %l6
24569! move %l6(lower) -> %o4(lower)
24570or %l6, %o4, %o4
24571!---- flushing int results buffer----
24572mov %o0, %l5
24573mov %o1, %l5
24574mov %o2, %l5
24575mov %o3, %l5
24576mov %o4, %l5
24577mov %l4, %o0
24578cas [%l7], %l6, %o0
24579! move %o0(lower) -> %o0(upper)
24580sllx %o0, 32, %o0
24581add %l4, 1, %l4
24582
24583P1934: !_ST_BINIT [5] (maybe <- 0x800163) (Int)
24584wr %g0, 0xe2, %asi
24585stwa %l4, [%i1 + 12] %asi
24586add %l4, 1, %l4
24587
24588P1935: !_MEMBAR (Int)
24589membar #StoreLoad
24590
24591P1936: !_SWAP [8] (maybe <- 0x800164) (Int)
24592mov %l4, %l7
24593swap [%i2 + 12], %l7
24594! move %l7(lower) -> %o0(lower)
24595srl %l7, 0, %l3
24596or %l3, %o0, %o0
24597add %l4, 1, %l4
24598
24599P1937: !_MEMBAR (FP)
24600membar #StoreLoad
24601
24602P1938: !_BLD [13] (FP)
24603wr %g0, 0xf0, %asi
24604ldda [%i3 + 0] %asi, %f32
24605membar #Sync
24606! 3 addresses covered
24607fmovd %f32, %f18
24608fmovs %f18, %f1
24609fmovs %f19, %f2
24610fmovd %f34, %f18
24611fmovs %f19, %f3
24612
24613P1939: !_MEMBAR (FP)
24614
24615P1940: !_DWST_BINIT [21] (maybe <- 0x800165) (Int)
24616wr %g0, 0xe2, %asi
24617sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
24618sub %i0, %i3, %i3
24619sllx %l4, 32, %o5
24620add %l4, 1, %l4
24621or %o5, %l4, %o5
24622stxa %o5, [%i3 + 0] %asi
24623add %l4, 1, %l4
24624
24625P1941: !_MEMBAR (Int)
24626membar #StoreLoad
24627
24628P1942: !_ST_BINIT [9] (maybe <- 0x800167) (Int) (CBR)
24629wr %g0, 0xe2, %asi
24630sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
24631add %i0, %i2, %i2
24632stwa %l4, [%i2 + 0] %asi
24633add %l4, 1, %l4
24634
24635! cbranch
24636andcc %l0, 1, %g0
24637be,pn %xcc, TARGET1942
24638nop
24639RET1942:
24640
24641! lfsr step begin
24642srlx %l0, 1, %l6
24643xnor %l6, %l0, %l6
24644sllx %l6, 63, %l6
24645or %l6, %l0, %l0
24646srlx %l0, 1, %l0
24647
24648
24649P1943: !_MEMBAR (Int)
24650membar #StoreLoad
24651
24652P1944: !_CASX [17] (maybe <- 0x800168) (Int)
24653sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
24654sub %i0, %i3, %i3
24655add %i3, 8, %o5
24656ldx [%o5], %o1
24657! move %o1(upper) -> %o1(upper)
24658! move %o1(lower) -> %o1(lower)
24659mov %o1, %l7
24660mov %l4, %o2
24661casx [%o5], %l7, %o2
24662! move %o2(upper) -> %o2(upper)
24663! move %o2(lower) -> %o2(lower)
24664add %l4, 1, %l4
24665
24666P1945: !_MEMBAR (FP)
24667membar #StoreLoad
24668
24669P1946: !_BLD [4] (FP)
24670wr %g0, 0xf0, %asi
24671ldda [%i1 + 0] %asi, %f32
24672membar #Sync
24673! 3 addresses covered
24674fmovd %f32, %f4
24675fmovd %f34, %f18
24676fmovs %f19, %f6
24677
24678P1947: !_MEMBAR (FP)
24679
24680P1948: !_LDD [12] (Int)
24681sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
24682add %i0, %i2, %i2
24683ldd [%i2 + 0], %l6
24684! move %l6(lower) -> %o3(upper)
24685sllx %l6, 32, %o3
24686! move %l7(lower) -> %o3(lower)
24687or %l7, %o3, %o3
24688
24689P1949: !_ST_BINIT [20] (maybe <- 0x800169) (Int)
24690wr %g0, 0xe2, %asi
24691sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
24692sub %i0, %i3, %i3
24693stwa %l4, [%i3 + 12] %asi
24694add %l4, 1, %l4
24695
24696P1950: !_MEMBAR (Int)
24697membar #StoreLoad
24698
24699P1951: !_DWLD [12] (Int)
24700ldx [%i2 + 0], %o4
24701! move %o4(upper) -> %o4(upper)
24702! move %o4(lower) -> %o4(lower)
24703!---- flushing int results buffer----
24704mov %o0, %l5
24705mov %o1, %l5
24706mov %o2, %l5
24707mov %o3, %l5
24708mov %o4, %l5
24709
24710P1952: !_ST_BINIT [0] (maybe <- 0x80016a) (Int)
24711wr %g0, 0xe2, %asi
24712stwa %l4, [%i0 + 0] %asi
24713add %l4, 1, %l4
24714
24715P1953: !_MEMBAR (Int)
24716membar #StoreLoad
24717
24718P1954: !_BLD [4] (FP)
24719wr %g0, 0xf0, %asi
24720ldda [%i1 + 0] %asi, %f32
24721membar #Sync
24722! 3 addresses covered
24723fmovd %f32, %f18
24724fmovs %f18, %f7
24725fmovs %f19, %f8
24726fmovd %f34, %f18
24727fmovs %f19, %f9
24728
24729P1955: !_MEMBAR (FP)
24730
24731P1956: !_DWLD [3] (Int)
24732ldx [%i1 + 0], %o0
24733! move %o0(upper) -> %o0(upper)
24734! move %o0(lower) -> %o0(lower)
24735
24736P1957: !_SWAP [4] (maybe <- 0x80016b) (Int)
24737mov %l4, %o1
24738swap [%i1 + 4], %o1
24739! move %o1(lower) -> %o1(upper)
24740sllx %o1, 32, %o1
24741add %l4, 1, %l4
24742
24743P1958: !_CAS [14] (maybe <- 0x80016c) (Int)
24744add %i2, 12, %l7
24745lduw [%l7], %l3
24746mov %l3, %l6
24747! move %l6(lower) -> %o1(lower)
24748or %l6, %o1, %o1
24749mov %l4, %o2
24750cas [%l7], %l6, %o2
24751! move %o2(lower) -> %o2(upper)
24752sllx %o2, 32, %o2
24753add %l4, 1, %l4
24754
24755P1959: !_ST [4] (maybe <- 0x80016d) (Int)
24756stw %l4, [%i1 + 4 ]
24757add %l4, 1, %l4
24758
24759P1960: !_MEMBAR (FP)
24760
24761P1961: !_BST [16] (maybe <- 0x4000014b) (FP)
24762wr %g0, 0xf0, %asi
24763sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
24764sub %i0, %i2, %i2
24765! preparing store val #0, next val will be in f32
24766fmovs %f16, %f20
24767fadds %f16, %f17, %f16
24768! preparing store val #1, next val will be in f33
24769fmovs %f16, %f21
24770fadds %f16, %f17, %f16
24771! preparing store val #2, next val will be in f35
24772fmovd %f20, %f32
24773fmovs %f16, %f21
24774fadds %f16, %f17, %f16
24775fmovd %f20, %f34
24776membar #Sync
24777stda %f32, [%i2 + 0 ] %asi
24778
24779P1962: !_MEMBAR (FP)
24780
24781P1963: !_BST [22] (maybe <- 0x4000014e) (FP)
24782wr %g0, 0xf0, %asi
24783sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
24784sub %i0, %i3, %i3
24785! preparing store val #0, next val will be in f32
24786fmovs %f16, %f20
24787fadds %f16, %f17, %f16
24788! preparing store val #1, next val will be in f33
24789fmovs %f16, %f21
24790fadds %f16, %f17, %f16
24791! preparing store val #2, next val will be in f35
24792fmovd %f20, %f32
24793fmovs %f16, %f21
24794fadds %f16, %f17, %f16
24795fmovd %f20, %f34
24796membar #Sync
24797stda %f32, [%i3 + 0 ] %asi
24798
24799P1964: !_MEMBAR (FP)
24800
24801P1965: !_BSTC [18] (maybe <- 0x40000151) (FP)
24802wr %g0, 0xe0, %asi
24803sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
24804sub %i0, %i2, %i2
24805! preparing store val #0, next val will be in f32
24806fmovs %f16, %f20
24807fadds %f16, %f17, %f16
24808! preparing store val #1, next val will be in f33
24809fmovs %f16, %f21
24810fadds %f16, %f17, %f16
24811! preparing store val #2, next val will be in f35
24812fmovd %f20, %f32
24813fmovs %f16, %f21
24814fadds %f16, %f17, %f16
24815fmovd %f20, %f34
24816membar #Sync
24817stda %f32, [%i2 + 0 ] %asi
24818
24819P1966: !_MEMBAR (FP)
24820
24821P1967: !_BSTC [11] (maybe <- 0x40000154) (FP)
24822wr %g0, 0xe0, %asi
24823sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
24824add %i0, %i3, %i3
24825! preparing store val #0, next val will be in f32
24826fmovs %f16, %f20
24827fadds %f16, %f17, %f16
24828! preparing store val #1, next val will be in f33
24829fmovs %f16, %f21
24830fadds %f16, %f17, %f16
24831! preparing store val #2, next val will be in f35
24832fmovd %f20, %f32
24833fmovs %f16, %f21
24834fadds %f16, %f17, %f16
24835fmovd %f20, %f34
24836membar #Sync
24837stda %f32, [%i3 + 0 ] %asi
24838
24839P1968: !_MEMBAR (FP) (CBR)
24840
24841! cbranch
24842andcc %l0, 1, %g0
24843be,pn %xcc, TARGET1968
24844nop
24845RET1968:
24846
24847! lfsr step begin
24848srlx %l0, 1, %l6
24849xnor %l6, %l0, %l6
24850sllx %l6, 63, %l6
24851or %l6, %l0, %l0
24852srlx %l0, 1, %l0
24853
24854
24855P1969: !_BSTC [1] (maybe <- 0x40000157) (FP)
24856wr %g0, 0xe0, %asi
24857! preparing store val #0, next val will be in f32
24858fmovs %f16, %f20
24859fadds %f16, %f17, %f16
24860! preparing store val #1, next val will be in f33
24861fmovs %f16, %f21
24862fadds %f16, %f17, %f16
24863! preparing store val #2, next val will be in f35
24864fmovd %f20, %f32
24865fmovs %f16, %f21
24866fadds %f16, %f17, %f16
24867fmovd %f20, %f34
24868membar #Sync
24869stda %f32, [%i0 + 0 ] %asi
24870
24871P1970: !_MEMBAR (FP)
24872membar #StoreLoad
24873
24874P1971: !_CASX [3] (maybe <- 0x80016e) (Int)
24875ldx [%i1], %l3
24876! move %l3(upper) -> %o2(lower)
24877srlx %l3, 32, %l6
24878or %l6, %o2, %o2
24879! move %l3(lower) -> %o3(upper)
24880sllx %l3, 32, %o3
24881mov %l3, %l6
24882sllx %l4, 32, %l3
24883add %l4, 1, %l4
24884or %l4, %l3, %l3
24885casx [%i1], %l6, %l3
24886! move %l3(upper) -> %o3(lower)
24887srlx %l3, 32, %l6
24888or %l6, %o3, %o3
24889! move %l3(lower) -> %o4(upper)
24890sllx %l3, 32, %o4
24891add %l4, 1, %l4
24892
24893P1972: !_DWST [15] (maybe <- 0x800170) (Int)
24894sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
24895sub %i0, %i2, %i2
24896sllx %l4, 32, %l6
24897add %l4, 1, %l4
24898or %l6, %l4, %l6
24899stx %l6, [%i2 + 0]
24900add %l4, 1, %l4
24901
24902P1973: !_SWAP [2] (maybe <- 0x800172) (Int)
24903mov %l4, %l7
24904swap [%i0 + 12], %l7
24905! move %l7(lower) -> %o4(lower)
24906srl %l7, 0, %l3
24907or %l3, %o4, %o4
24908!---- flushing int results buffer----
24909mov %o0, %l5
24910mov %o1, %l5
24911mov %o2, %l5
24912mov %o3, %l5
24913mov %o4, %l5
24914add %l4, 1, %l4
24915
24916P1974: !_DWST [7] (maybe <- 0x800173) (Int) (LE)
24917wr %g0, 0x88, %asi
24918sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
24919sub %i0, %i3, %i3
24920sllx %l4, 32, %o5
24921add %l4, 1, %l4
24922or %o5, %l4, %l3
24923! Change double-word-level endianess (big endian <-> little endian)
24924sethi %hi(0xff00ff00), %l6
24925or %l6, %lo(0xff00ff00), %l6
24926sllx %l6, 32, %o5
24927or %l6, %o5, %l6
24928and %l3, %l6, %o5
24929srlx %o5, 8, %o5
24930sllx %l3, 8, %l3
24931and %l3, %l6, %l3
24932or %l3, %o5, %l3
24933sethi %hi(0xffff0000), %l6
24934srlx %l3, 16, %o5
24935andn %o5, %l6, %o5
24936andn %l3, %l6, %l3
24937sllx %l3, 16, %l3
24938or %l3, %o5, %l3
24939srlx %l3, 32, %o5
24940sllx %l3, 32, %l3
24941or %l3, %o5, %o5
24942stxa %o5, [%i3 + 0 ] %asi
24943add %l4, 1, %l4
24944
24945P1975: !_CASX [22] (maybe <- 0x800175) (Int)
24946sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
24947sub %i0, %i2, %i2
24948ldx [%i2], %o0
24949! move %o0(upper) -> %o0(upper)
24950! move %o0(lower) -> %o0(lower)
24951mov %o0, %l7
24952sllx %l4, 32, %o1
24953add %l4, 1, %l4
24954or %l4, %o1, %o1
24955casx [%i2], %l7, %o1
24956! move %o1(upper) -> %o1(upper)
24957! move %o1(lower) -> %o1(lower)
24958add %l4, 1, %l4
24959
24960P1976: !_MEMBAR (FP)
24961membar #StoreLoad
24962
24963P1977: !_BLD [21] (FP)
24964wr %g0, 0xf0, %asi
24965ldda [%i2 + 0] %asi, %f32
24966membar #Sync
24967! 3 addresses covered
24968fmovd %f32, %f10
24969fmovd %f34, %f18
24970fmovs %f19, %f12
24971
24972P1978: !_MEMBAR (FP)
24973
24974P1979: !_SWAP [16] (maybe <- 0x800177) (Int)
24975sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
24976sub %i0, %i3, %i3
24977mov %l4, %o2
24978swap [%i3 + 4], %o2
24979! move %o2(lower) -> %o2(upper)
24980sllx %o2, 32, %o2
24981add %l4, 1, %l4
24982
24983P1980: !_REPLACEMENT [12] (Int)
24984sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
24985sub %i0, %i2, %i2
24986sethi %hi(0x20000), %l6
24987ld [%i2+0], %o5
24988st %o5, [%i2+0]
24989add %i2, %l6, %l7
24990ld [%l7+0], %o5
24991st %o5, [%l7+0]
24992add %l7, %l6, %l7
24993ld [%l7+0], %o5
24994st %o5, [%l7+0]
24995add %l7, %l6, %l7
24996ld [%l7+0], %o5
24997st %o5, [%l7+0]
24998add %l7, %l6, %l7
24999ld [%l7+0], %o5
25000st %o5, [%l7+0]
25001add %l7, %l6, %l7
25002ld [%l7+0], %o5
25003st %o5, [%l7+0]
25004add %l7, %l6, %l7
25005ld [%l7+0], %o5
25006st %o5, [%l7+0]
25007add %l7, %l6, %l7
25008ld [%l7+0], %o5
25009st %o5, [%l7+0]
25010
25011P1981: !_SWAP [21] (maybe <- 0x800178) (Int)
25012sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
25013sub %i0, %i3, %i3
25014mov %l4, %l7
25015swap [%i3 + 0], %l7
25016! move %l7(lower) -> %o2(lower)
25017srl %l7, 0, %l3
25018or %l3, %o2, %o2
25019add %l4, 1, %l4
25020
25021P1982: !_DWLD [0] (Int) (CBR)
25022ldx [%i0 + 0], %o3
25023! move %o3(upper) -> %o3(upper)
25024! move %o3(lower) -> %o3(lower)
25025
25026! cbranch
25027andcc %l0, 1, %g0
25028be,pn %xcc, TARGET1982
25029nop
25030RET1982:
25031
25032! lfsr step begin
25033srlx %l0, 1, %l6
25034xnor %l6, %l0, %l6
25035sllx %l6, 63, %l6
25036or %l6, %l0, %l0
25037srlx %l0, 1, %l0
25038
25039
25040P1983: !_MEMBAR (FP)
25041
25042P1984: !_BSTC [2] (maybe <- 0x4000015a) (FP)
25043wr %g0, 0xe0, %asi
25044! preparing store val #0, next val will be in f32
25045fmovs %f16, %f20
25046fadds %f16, %f17, %f16
25047! preparing store val #1, next val will be in f33
25048fmovs %f16, %f21
25049fadds %f16, %f17, %f16
25050! preparing store val #2, next val will be in f35
25051fmovd %f20, %f32
25052fmovs %f16, %f21
25053fadds %f16, %f17, %f16
25054fmovd %f20, %f34
25055membar #Sync
25056stda %f32, [%i0 + 0 ] %asi
25057
25058P1985: !_MEMBAR (FP)
25059
25060P1986: !_BST [19] (maybe <- 0x4000015d) (FP)
25061wr %g0, 0xf0, %asi
25062sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
25063sub %i0, %i2, %i2
25064! preparing store val #0, next val will be in f32
25065fmovs %f16, %f20
25066fadds %f16, %f17, %f16
25067! preparing store val #1, next val will be in f33
25068fmovs %f16, %f21
25069fadds %f16, %f17, %f16
25070! preparing store val #2, next val will be in f35
25071fmovd %f20, %f32
25072fmovs %f16, %f21
25073fadds %f16, %f17, %f16
25074fmovd %f20, %f34
25075membar #Sync
25076stda %f32, [%i2 + 0 ] %asi
25077
25078P1987: !_MEMBAR (FP) (Branch target of P1968)
25079membar #StoreLoad
25080ba P1988
25081nop
25082
25083TARGET1968:
25084ba RET1968
25085nop
25086
25087
25088P1988: !_BLD [12] (FP)
25089wr %g0, 0xf0, %asi
25090sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
25091add %i0, %i3, %i3
25092ldda [%i3 + 0] %asi, %f32
25093membar #Sync
25094! 3 addresses covered
25095fmovd %f32, %f18
25096fmovs %f18, %f13
25097fmovs %f19, %f14
25098fmovd %f34, %f18
25099fmovs %f19, %f15
25100!---- flushing fp results buffer to %f30 ----
25101fmovd %f0, %f30
25102fmovd %f2, %f30
25103fmovd %f4, %f30
25104fmovd %f6, %f30
25105fmovd %f8, %f30
25106fmovd %f10, %f30
25107fmovd %f12, %f30
25108fmovd %f14, %f30
25109!--
25110
25111P1989: !_MEMBAR (FP)
25112
25113P1990: !_SWAP [18] (maybe <- 0x800179) (Int)
25114mov %l4, %o4
25115swap [%i2 + 0], %o4
25116! move %o4(lower) -> %o4(upper)
25117sllx %o4, 32, %o4
25118add %l4, 1, %l4
25119
25120P1991: !_ST_BINIT [11] (maybe <- 0x80017a) (Int)
25121wr %g0, 0xe2, %asi
25122sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
25123add %i0, %i2, %i2
25124stwa %l4, [%i2 + 12] %asi
25125add %l4, 1, %l4
25126
25127P1992: !_MEMBAR (Int)
25128membar #StoreLoad
25129
25130P1993: !_CASX [20] (maybe <- 0x80017b) (Int)
25131sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
25132sub %i0, %i3, %i3
25133add %i3, 8, %o5
25134ldx [%o5], %l6
25135! move %l6(upper) -> %o4(lower)
25136srlx %l6, 32, %l7
25137or %l7, %o4, %o4
25138!---- flushing int results buffer----
25139mov %o0, %l5
25140mov %o1, %l5
25141mov %o2, %l5
25142mov %o3, %l5
25143mov %o4, %l5
25144! move %l6(lower) -> %o0(upper)
25145sllx %l6, 32, %o0
25146mov %l6, %l7
25147mov %l4, %l6
25148casx [%o5], %l7, %l6
25149! move %l6(upper) -> %o0(lower)
25150srlx %l6, 32, %l7
25151or %l7, %o0, %o0
25152! move %l6(lower) -> %o1(upper)
25153sllx %l6, 32, %o1
25154add %l4, 1, %l4
25155
25156P1994: !_DWST [17] (maybe <- 0x80017c) (Int)
25157sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
25158sub %i0, %i2, %i2
25159mov %l4, %l7
25160stx %l7, [%i2 + 8]
25161add %l4, 1, %l4
25162
25163P1995: !_LDD [17] (Int)
25164ldd [%i2 + 8], %l6
25165! move %l7(lower) -> %o1(lower)
25166or %l7, %o1, %o1
25167
25168P1996: !_DWLD [19] (Int)
25169ldx [%i3 + 0], %o2
25170! move %o2(upper) -> %o2(upper)
25171! move %o2(lower) -> %o2(lower)
25172
25173P1997: !_MEMBAR (FP)
25174membar #StoreLoad
25175
25176P1998: !_BLD [13] (FP)
25177wr %g0, 0xf0, %asi
25178sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
25179add %i0, %i3, %i3
25180ldda [%i3 + 0] %asi, %f0
25181membar #Sync
25182! 3 addresses covered
25183fmovs %f3, %f2
25184
25185P1999: !_MEMBAR (FP)
25186
25187P2000: !_LDD [12] (Int)
25188ldd [%i3 + 0], %l6
25189! move %l6(lower) -> %o3(upper)
25190sllx %l6, 32, %o3
25191! move %l7(lower) -> %o3(lower)
25192or %l7, %o3, %o3
25193
25194P2001: !_LD [18] (Int)
25195sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
25196sub %i0, %i2, %i2
25197lduw [%i2 + 0], %o4
25198! move %o4(lower) -> %o4(upper)
25199sllx %o4, 32, %o4
25200
25201P2002: !_LD [18] (Int) (Loop exit) (CBR)
25202lduw [%i2 + 0], %o5
25203! move %o5(lower) -> %o4(lower)
25204or %o5, %o4, %o4
25205!---- flushing int results buffer----
25206mov %o0, %l5
25207mov %o1, %l5
25208mov %o2, %l5
25209mov %o3, %l5
25210mov %o4, %l5
25211
25212! cbranch
25213andcc %l0, 1, %g0
25214be,pn %xcc, TARGET2002
25215nop
25216RET2002:
25217
25218! lfsr step begin
25219srlx %l0, 1, %l3
25220xnor %l3, %l0, %l3
25221sllx %l3, 63, %l3
25222or %l3, %l0, %l0
25223srlx %l0, 1, %l0
25224
25225!---- flushing fp results buffer to %f30 ----
25226fmovd %f0, %f30
25227fmovs %f2, %f30
25228!--
25229
25230sethi %hi(0x400000), %l6
25231add %i1, %l6, %i1
25232!-- End Aliased access: base register for region 1 (%i1) restored
25233loop_exit_1_0:
25234sub %l2, 1, %l2
25235cmp %l2, 0
25236bg loop_entry_1_0
25237nop
25238
25239P2003: !_MEMBAR (Int) (CBR)
25240membar #StoreLoad
25241
25242! cbranch
25243andcc %l0, 1, %g0
25244be,pn %xcc, TARGET2003
25245nop
25246RET2003:
25247
25248! lfsr step begin
25249srlx %l0, 1, %l7
25250xnor %l7, %l0, %l7
25251sllx %l7, 63, %l7
25252or %l7, %l0, %l0
25253srlx %l0, 1, %l0
25254
25255
25256END_NODES1: ! Test instruction sequence for CPU 1 ends
25257sethi %hi(0xdead0e0f), %o5
25258or %o5, %lo(0xdead0e0f), %o5
25259! move %o5(lower) -> %o0(upper)
25260sllx %o5, 32, %o0
25261sethi %hi(0xdead0e0f), %o5
25262or %o5, %lo(0xdead0e0f), %o5
25263stw %o5, [%i5]
25264ld [%i5], %f0
25265!---- flushing int results buffer----
25266mov %o0, %l5
25267!---- flushing fp results buffer to %f30 ----
25268fmovs %f0, %f30
25269!--
25270
25271restore
25272retl
25273nop
25274!-----------------
25275
25276! register usage:
25277! %i0 %i1 : base registers for first 2 regions
25278! %i2 %i3 : cache registers for 8 regions
25279! %i4 fixed pointer to per-cpu results area
25280! %l1 moving pointer to per-cpu FP results area
25281! %o7 moving pointer to per-cpu integer results area
25282! %i5 pointer to per-cpu private area
25283! %l0 holds lfsr, used as source of random bits
25284! %l2 loop count register
25285! %f16 running counter for unique fp store values
25286! %f17 holds increment value for fp counter
25287! %l4 running counter for unique integer store values (increment value is always 1)
25288! %l5 move-to register for load values (simulation only)
25289! %f30 move-to register for FP values (simulation only)
25290! %i4 holds the instructions count which is used for interrupt ordering
25291! %i4 holds the thread_id (OBP only)
25292! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage
25293! %l3 %l6 %l7 %o5 : 4 temporary registers
25294! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
25295! %f0-f15 FP results buffer registers
25296! %f32-f47 FP block load/store registers
25297
25298func2:
25299! instruction sequence begins
25300save %sp, -192, %sp
25301
25302! Force %i0-%i3 to be 64-byte aligned
25303add %i0, 63, %i0
25304andn %i0, 63, %i0
25305
25306add %i1, 63, %i1
25307andn %i1, 63, %i1
25308
25309add %i2, 63, %i2
25310andn %i2, 63, %i2
25311
25312add %i3, 63, %i3
25313andn %i3, 63, %i3
25314
25315add %i4, 63, %i4
25316andn %i4, 63, %i4
25317
25318add %i5, 63, %i5
25319andn %i5, 63, %i5
25320
25321
25322! Initialize pointer to FP load results area
25323mov %i4, %l1
25324
25325! Initialize pointer to integer load results area
25326sethi %hi(0x80000), %o7
25327or %o7, %lo(0x80000), %o7
25328add %o7, %l1, %o7
25329
25330! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info
25331mov 0x0, %i4
25332
25333! Initialize %f0-%f62 to 0xdeadbee0deadbee1
25334sethi %hi(0xdeadbee0), %l7
25335or %l7, %lo(0xdeadbee0), %l7
25336stw %l7, [%i5]
25337sethi %hi(0xdeadbee1), %l7
25338or %l7, %lo(0xdeadbee1), %l7
25339stw %l7, [%i5+4]
25340ldd [%i5], %f0
25341fmovd %f0, %f2
25342fmovd %f0, %f4
25343fmovd %f0, %f6
25344fmovd %f0, %f8
25345fmovd %f0, %f10
25346fmovd %f0, %f12
25347fmovd %f0, %f14
25348fmovd %f0, %f16
25349fmovd %f0, %f18
25350fmovd %f0, %f20
25351fmovd %f0, %f22
25352fmovd %f0, %f24
25353fmovd %f0, %f26
25354fmovd %f0, %f28
25355fmovd %f0, %f30
25356fmovd %f0, %f32
25357fmovd %f0, %f34
25358fmovd %f0, %f36
25359fmovd %f0, %f38
25360fmovd %f0, %f40
25361fmovd %f0, %f42
25362fmovd %f0, %f44
25363fmovd %f0, %f46
25364fmovd %f0, %f48
25365fmovd %f0, %f50
25366fmovd %f0, %f52
25367fmovd %f0, %f54
25368fmovd %f0, %f56
25369fmovd %f0, %f58
25370fmovd %f0, %f60
25371fmovd %f0, %f62
25372
25373! Signature for extract_loads script to start extracting load values for this stream
25374sethi %hi(0x02deade1), %l7
25375or %l7, %lo(0x02deade1), %l7
25376stw %l7, [%i5]
25377ld [%i5], %f16
25378
25379! Initialize running integer counter in register %l4
25380sethi %hi(0x1000001), %l4
25381or %l4, %lo(0x1000001), %l4
25382
25383! Initialize running FP counter in register %f16
25384sethi %hi(0x40800001), %l7
25385or %l7, %lo(0x40800001), %l7
25386stw %l7, [%i5]
25387ld [%i5], %f16
25388
25389! Initialize FP counter increment value in register %f17 (constant)
25390sethi %hi(0x35000000), %l7
25391or %l7, %lo(0x35000000), %l7
25392stw %l7, [%i5]
25393ld [%i5], %f17
25394
25395! Initialize LFSR to 0x39d8^4
25396sethi %hi(0x39d8), %l0
25397or %l0, %lo(0x39d8), %l0
25398mulx %l0, %l0, %l0
25399mulx %l0, %l0, %l0
25400
25401BEGIN_NODES2: ! Test instruction sequence for ISTREAM 2 begins
25402
25403P2004: !_DWLD [1] (Int) (Loop entry)
25404sethi %hi(0x1), %l2
25405or %l2, %lo(0x1), %l2
25406loop_entry_2_0:
25407ldx [%i0 + 0], %o0
25408! move %o0(upper) -> %o0(upper)
25409! move %o0(lower) -> %o0(lower)
25410
25411P2005: !_ST_BINIT [10] (maybe <- 0x1000001) (Int)
25412wr %g0, 0xe2, %asi
25413sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
25414add %i0, %i3, %i3
25415stwa %l4, [%i3 + 4] %asi
25416add %l4, 1, %l4
25417
25418P2006: !_MEMBAR (Int)
25419membar #StoreLoad
25420
25421P2007: !_SWAP [5] (maybe <- 0x1000002) (Int)
25422mov %l4, %o1
25423swap [%i1 + 12], %o1
25424! move %o1(lower) -> %o1(upper)
25425sllx %o1, 32, %o1
25426add %l4, 1, %l4
25427
25428P2008: !_ST_BINIT [6] (maybe <- 0x1000003) (Int)
25429wr %g0, 0xe2, %asi
25430sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
25431sub %i0, %i2, %i2
25432stwa %l4, [%i2 + 0] %asi
25433add %l4, 1, %l4
25434
25435P2009: !_MEMBAR (Int)
25436membar #StoreLoad
25437
25438P2010: !_ST_BINIT [18] (maybe <- 0x1000004) (Int)
25439wr %g0, 0xe2, %asi
25440sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
25441sub %i0, %i3, %i3
25442stwa %l4, [%i3 + 0] %asi
25443add %l4, 1, %l4
25444
25445P2011: !_MEMBAR (Int)
25446membar #StoreLoad
25447
25448P2012: !_ST [7] (maybe <- 0x1000005) (Int)
25449stw %l4, [%i2 + 4 ]
25450add %l4, 1, %l4
25451
25452P2013: !_ST_BINIT [4] (maybe <- 0x1000006) (Int)
25453wr %g0, 0xe2, %asi
25454stwa %l4, [%i1 + 4] %asi
25455add %l4, 1, %l4
25456
25457P2014: !_MEMBAR (Int)
25458membar #StoreLoad
25459
25460P2015: !_CASX [8] (maybe <- 0x1000007) (Int)
25461add %i2, 8, %l3
25462ldx [%l3], %l7
25463! move %l7(upper) -> %o1(lower)
25464srlx %l7, 32, %o5
25465or %o5, %o1, %o1
25466! move %l7(lower) -> %o2(upper)
25467sllx %l7, 32, %o2
25468mov %l7, %o5
25469mov %l4, %l7
25470casx [%l3], %o5, %l7
25471! move %l7(upper) -> %o2(lower)
25472srlx %l7, 32, %o5
25473or %o5, %o2, %o2
25474! move %l7(lower) -> %o3(upper)
25475sllx %l7, 32, %o3
25476add %l4, 1, %l4
25477
25478P2016: !_PREFETCH [10] (Int)
25479sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
25480add %i0, %i2, %i2
25481prefetch [%i2 + 4], 1
25482
25483P2017: !_MEMBAR (FP)
25484membar #StoreLoad
25485
25486P2018: !_BLD [19] (FP)
25487wr %g0, 0xf0, %asi
25488ldda [%i3 + 0] %asi, %f0
25489membar #Sync
25490! 3 addresses covered
25491fmovs %f3, %f2
25492
25493P2019: !_MEMBAR (FP)
25494
25495P2020: !_BSTC [20] (maybe <- 0x40800001) (FP)
25496wr %g0, 0xe0, %asi
25497! preparing store val #0, next val will be in f32
25498fmovs %f16, %f20
25499fadds %f16, %f17, %f16
25500! preparing store val #1, next val will be in f33
25501fmovs %f16, %f21
25502fadds %f16, %f17, %f16
25503! preparing store val #2, next val will be in f35
25504fmovd %f20, %f32
25505fmovs %f16, %f21
25506fadds %f16, %f17, %f16
25507fmovd %f20, %f34
25508membar #Sync
25509stda %f32, [%i3 + 0 ] %asi
25510
25511P2021: !_MEMBAR (FP) (CBR)
25512membar #StoreLoad
25513
25514! cbranch
25515andcc %l0, 1, %g0
25516be,pn %xcc, TARGET2021
25517nop
25518RET2021:
25519
25520! lfsr step begin
25521srlx %l0, 1, %l7
25522xnor %l7, %l0, %l7
25523sllx %l7, 63, %l7
25524or %l7, %l0, %l0
25525srlx %l0, 1, %l0
25526
25527
25528P2022: !_ST [7] (maybe <- 0x1000008) (Int)
25529sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
25530sub %i0, %i3, %i3
25531stw %l4, [%i3 + 4 ]
25532add %l4, 1, %l4
25533
25534P2023: !_LDD [12] (Int)
25535sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
25536add %i0, %i2, %i2
25537ldd [%i2 + 0], %l6
25538! move %l6(lower) -> %o3(lower)
25539or %l6, %o3, %o3
25540! move %l7(lower) -> %o4(upper)
25541sllx %l7, 32, %o4
25542
25543P2024: !_LD [3] (Int)
25544lduw [%i1 + 0], %l6
25545! move %l6(lower) -> %o4(lower)
25546or %l6, %o4, %o4
25547!---- flushing int results buffer----
25548mov %o0, %l5
25549mov %o1, %l5
25550mov %o2, %l5
25551mov %o3, %l5
25552mov %o4, %l5
25553
25554P2025: !_DWST [1] (maybe <- 0x1000009) (Int)
25555sllx %l4, 32, %l7
25556add %l4, 1, %l4
25557or %l7, %l4, %l7
25558stx %l7, [%i0 + 0]
25559add %l4, 1, %l4
25560
25561P2026: !_ST [21] (maybe <- 0x100000b) (Int) (Branch target of P2728)
25562sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
25563sub %i0, %i3, %i3
25564stw %l4, [%i3 + 0 ]
25565add %l4, 1, %l4
25566ba P2027
25567nop
25568
25569TARGET2728:
25570ba RET2728
25571nop
25572
25573
25574P2027: !_REPLACEMENT [15] (Int)
25575sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
25576sub %i0, %i2, %i2
25577sethi %hi(0x20000), %l3
25578ld [%i2+0], %l7
25579st %l7, [%i2+0]
25580add %i2, %l3, %l6
25581ld [%l6+0], %l7
25582st %l7, [%l6+0]
25583add %l6, %l3, %l6
25584ld [%l6+0], %l7
25585st %l7, [%l6+0]
25586add %l6, %l3, %l6
25587ld [%l6+0], %l7
25588st %l7, [%l6+0]
25589add %l6, %l3, %l6
25590ld [%l6+0], %l7
25591st %l7, [%l6+0]
25592add %l6, %l3, %l6
25593ld [%l6+0], %l7
25594st %l7, [%l6+0]
25595add %l6, %l3, %l6
25596ld [%l6+0], %l7
25597st %l7, [%l6+0]
25598add %l6, %l3, %l6
25599ld [%l6+0], %l7
25600st %l7, [%l6+0]
25601
25602P2028: !_MEMBAR (FP)
25603
25604P2029: !_BST [22] (maybe <- 0x40800004) (FP)
25605wr %g0, 0xf0, %asi
25606! preparing store val #0, next val will be in f32
25607fmovs %f16, %f20
25608fadds %f16, %f17, %f16
25609! preparing store val #1, next val will be in f33
25610fmovs %f16, %f21
25611fadds %f16, %f17, %f16
25612! preparing store val #2, next val will be in f35
25613fmovd %f20, %f32
25614fmovs %f16, %f21
25615fadds %f16, %f17, %f16
25616fmovd %f20, %f34
25617membar #Sync
25618stda %f32, [%i3 + 0 ] %asi
25619
25620P2030: !_MEMBAR (FP)
25621membar #StoreLoad
25622
25623P2031: !_LDD [4] (Int)
25624ldd [%i1 + 0], %l6
25625! move %l6(lower) -> %o0(upper)
25626sllx %l6, 32, %o0
25627! move %l7(lower) -> %o0(lower)
25628or %l7, %o0, %o0
25629
25630P2032: !_PREFETCH [7] (Int)
25631sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
25632sub %i0, %i3, %i3
25633prefetch [%i3 + 4], 1
25634
25635P2033: !_LDD [15] (Int)
25636sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
25637sub %i0, %i2, %i2
25638ldd [%i2 + 0], %l6
25639! move %l6(lower) -> %o1(upper)
25640sllx %l6, 32, %o1
25641! move %l7(lower) -> %o1(lower)
25642or %l7, %o1, %o1
25643
25644P2034: !_MEMBAR (FP)
25645
25646P2035: !_BSTC [13] (maybe <- 0x40800007) (FP)
25647wr %g0, 0xe0, %asi
25648sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
25649add %i0, %i3, %i3
25650! preparing store val #0, next val will be in f32
25651fmovs %f16, %f20
25652fadds %f16, %f17, %f16
25653! preparing store val #1, next val will be in f33
25654fmovs %f16, %f21
25655fadds %f16, %f17, %f16
25656! preparing store val #2, next val will be in f35
25657fmovd %f20, %f32
25658fmovs %f16, %f21
25659fadds %f16, %f17, %f16
25660fmovd %f20, %f34
25661membar #Sync
25662stda %f32, [%i3 + 0 ] %asi
25663
25664P2036: !_MEMBAR (FP)
25665membar #StoreLoad
25666
25667P2037: !_CAS [5] (maybe <- 0x100000c) (Int)
25668add %i1, 12, %l3
25669lduw [%l3], %o2
25670mov %o2, %o5
25671! move %o5(lower) -> %o2(upper)
25672sllx %o5, 32, %o2
25673mov %l4, %l7
25674cas [%l3], %o5, %l7
25675! move %l7(lower) -> %o2(lower)
25676srl %l7, 0, %o5
25677or %o5, %o2, %o2
25678add %l4, 1, %l4
25679
25680P2038: !_MEMBAR (FP)
25681
25682P2039: !_BST [15] (maybe <- 0x4080000a) (FP)
25683wr %g0, 0xf0, %asi
25684! preparing store val #0, next val will be in f32
25685fmovs %f16, %f20
25686fadds %f16, %f17, %f16
25687! preparing store val #1, next val will be in f33
25688fmovs %f16, %f21
25689fadds %f16, %f17, %f16
25690! preparing store val #2, next val will be in f35
25691fmovd %f20, %f32
25692fmovs %f16, %f21
25693fadds %f16, %f17, %f16
25694fmovd %f20, %f34
25695membar #Sync
25696stda %f32, [%i2 + 0 ] %asi
25697
25698P2040: !_MEMBAR (FP)
25699membar #StoreLoad
25700
25701P2041: !_REPLACEMENT [7] (Int) (CBR)
25702sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
25703sub %i0, %i2, %i2
25704sethi %hi(0x20000), %l7
25705ld [%i2+4], %l3
25706st %l3, [%i2+4]
25707add %i2, %l7, %o5
25708ld [%o5+4], %l3
25709st %l3, [%o5+4]
25710add %o5, %l7, %o5
25711ld [%o5+4], %l3
25712st %l3, [%o5+4]
25713add %o5, %l7, %o5
25714ld [%o5+4], %l3
25715st %l3, [%o5+4]
25716add %o5, %l7, %o5
25717ld [%o5+4], %l3
25718st %l3, [%o5+4]
25719add %o5, %l7, %o5
25720ld [%o5+4], %l3
25721st %l3, [%o5+4]
25722add %o5, %l7, %o5
25723ld [%o5+4], %l3
25724st %l3, [%o5+4]
25725add %o5, %l7, %o5
25726ld [%o5+4], %l3
25727st %l3, [%o5+4]
25728
25729! cbranch
25730andcc %l0, 1, %g0
25731be,pn %xcc, TARGET2041
25732nop
25733RET2041:
25734
25735! lfsr step begin
25736srlx %l0, 1, %l6
25737xnor %l6, %l0, %l6
25738sllx %l6, 63, %l6
25739or %l6, %l0, %l0
25740srlx %l0, 1, %l0
25741
25742
25743P2042: !_ST_BINIT [13] (maybe <- 0x100000d) (Int) (LE)
25744wr %g0, 0xea, %asi
25745! Change single-word-level endianess (big endian <-> little endian)
25746sethi %hi(0xff00ff00), %o5
25747or %o5, %lo(0xff00ff00), %o5
25748and %l4, %o5, %l3
25749srl %l3, 8, %l3
25750sll %l4, 8, %l7
25751and %l7, %o5, %l7
25752or %l7, %l3, %l7
25753srl %l7, 16, %l3
25754sll %l7, 16, %l7
25755srl %l7, 0, %l7
25756or %l7, %l3, %l7
25757stwa %l7, [%i3 + 4] %asi
25758add %l4, 1, %l4
25759
25760P2043: !_MEMBAR (Int) (LE)
25761membar #StoreLoad
25762
25763P2044: !_ST [5] (maybe <- 0x4080000d) (FP)
25764! preparing store val #0, next val will be in f20
25765fmovs %f16, %f20
25766fadds %f16, %f17, %f16
25767st %f20, [%i1 + 12 ]
25768
25769P2045: !_MEMBAR (FP)
25770
25771P2046: !_BST [0] (maybe <- 0x4080000e) (FP)
25772wr %g0, 0xf0, %asi
25773! preparing store val #0, next val will be in f32
25774fmovs %f16, %f20
25775fadds %f16, %f17, %f16
25776! preparing store val #1, next val will be in f33
25777fmovs %f16, %f21
25778fadds %f16, %f17, %f16
25779! preparing store val #2, next val will be in f35
25780fmovd %f20, %f32
25781fmovs %f16, %f21
25782fadds %f16, %f17, %f16
25783fmovd %f20, %f34
25784membar #Sync
25785stda %f32, [%i0 + 0 ] %asi
25786
25787P2047: !_MEMBAR (FP)
25788membar #StoreLoad
25789
25790P2048: !_REPLACEMENT [15] (Int)
25791sethi %hi(0x20000), %o5
25792ld [%i2+0], %l6
25793st %l6, [%i2+0]
25794add %i2, %o5, %l3
25795ld [%l3+0], %l6
25796st %l6, [%l3+0]
25797add %l3, %o5, %l3
25798ld [%l3+0], %l6
25799st %l6, [%l3+0]
25800add %l3, %o5, %l3
25801ld [%l3+0], %l6
25802st %l6, [%l3+0]
25803add %l3, %o5, %l3
25804ld [%l3+0], %l6
25805st %l6, [%l3+0]
25806add %l3, %o5, %l3
25807ld [%l3+0], %l6
25808st %l6, [%l3+0]
25809add %l3, %o5, %l3
25810ld [%l3+0], %l6
25811st %l6, [%l3+0]
25812add %l3, %o5, %l3
25813ld [%l3+0], %l6
25814st %l6, [%l3+0]
25815
25816P2049: !_CAS [14] (maybe <- 0x100000e) (Int)
25817add %i3, 12, %o5
25818lduw [%o5], %o3
25819mov %o3, %l7
25820! move %l7(lower) -> %o3(upper)
25821sllx %l7, 32, %o3
25822mov %l4, %l6
25823cas [%o5], %l7, %l6
25824! move %l6(lower) -> %o3(lower)
25825srl %l6, 0, %l7
25826or %l7, %o3, %o3
25827add %l4, 1, %l4
25828
25829P2050: !_MEMBAR (FP)
25830
25831P2051: !_BSTC [4] (maybe <- 0x40800011) (FP)
25832wr %g0, 0xe0, %asi
25833! preparing store val #0, next val will be in f32
25834fmovs %f16, %f20
25835fadds %f16, %f17, %f16
25836! preparing store val #1, next val will be in f33
25837fmovs %f16, %f21
25838fadds %f16, %f17, %f16
25839! preparing store val #2, next val will be in f35
25840fmovd %f20, %f32
25841fmovs %f16, %f21
25842fadds %f16, %f17, %f16
25843fmovd %f20, %f34
25844membar #Sync
25845stda %f32, [%i1 + 0 ] %asi
25846
25847P2052: !_MEMBAR (FP)
25848membar #StoreLoad
25849
25850P2053: !_CASX [17] (maybe <- 0x100000f) (Int)
25851sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
25852sub %i0, %i3, %i3
25853add %i3, 8, %l7
25854ldx [%l7], %o4
25855! move %o4(upper) -> %o4(upper)
25856! move %o4(lower) -> %o4(lower)
25857!---- flushing int results buffer----
25858mov %o0, %l5
25859mov %o1, %l5
25860mov %o2, %l5
25861mov %o3, %l5
25862mov %o4, %l5
25863mov %o4, %l6
25864mov %l4, %o0
25865casx [%l7], %l6, %o0
25866! move %o0(upper) -> %o0(upper)
25867! move %o0(lower) -> %o0(lower)
25868add %l4, 1, %l4
25869
25870P2054: !_ST_BINIT [7] (maybe <- 0x1000010) (Int)
25871wr %g0, 0xe2, %asi
25872sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
25873sub %i0, %i2, %i2
25874stwa %l4, [%i2 + 4] %asi
25875add %l4, 1, %l4
25876
25877P2055: !_MEMBAR (Int) (Branch target of P2423)
25878membar #StoreLoad
25879ba P2056
25880nop
25881
25882TARGET2423:
25883ba RET2423
25884nop
25885
25886
25887P2056: !_SWAP [10] (maybe <- 0x1000011) (Int)
25888sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
25889add %i0, %i3, %i3
25890mov %l4, %o1
25891swap [%i3 + 4], %o1
25892! move %o1(lower) -> %o1(upper)
25893sllx %o1, 32, %o1
25894add %l4, 1, %l4
25895
25896P2057: !_SWAP [12] (maybe <- 0x1000012) (Int)
25897sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
25898add %i0, %i2, %i2
25899mov %l4, %l6
25900swap [%i2 + 0], %l6
25901! move %l6(lower) -> %o1(lower)
25902srl %l6, 0, %o5
25903or %o5, %o1, %o1
25904add %l4, 1, %l4
25905
25906P2058: !_DWST_BINIT [9] (maybe <- 0x1000013) (Int)
25907wr %g0, 0xe2, %asi
25908sllx %l4, 32, %l7
25909add %l4, 1, %l4
25910or %l7, %l4, %l7
25911stxa %l7, [%i3 + 0] %asi
25912add %l4, 1, %l4
25913
25914P2059: !_MEMBAR (Int)
25915membar #StoreLoad
25916
25917P2060: !_SWAP [1] (maybe <- 0x1000015) (Int)
25918mov %l4, %o2
25919swap [%i0 + 4], %o2
25920! move %o2(lower) -> %o2(upper)
25921sllx %o2, 32, %o2
25922add %l4, 1, %l4
25923
25924P2061: !_PREFETCH [1] (Int)
25925prefetch [%i0 + 4], 2
25926
25927P2062: !_ST [23] (maybe <- 0x40800014) (FP)
25928sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
25929sub %i0, %i3, %i3
25930! preparing store val #0, next val will be in f20
25931fmovs %f16, %f20
25932fadds %f16, %f17, %f16
25933st %f20, [%i3 + 12 ]
25934
25935P2063: !_DWST [0] (maybe <- 0x1000016) (Int)
25936sllx %l4, 32, %o5
25937add %l4, 1, %l4
25938or %o5, %l4, %o5
25939stx %o5, [%i0 + 0]
25940add %l4, 1, %l4
25941
25942P2064: !_DWST [1] (maybe <- 0x1000018) (Int)
25943sllx %l4, 32, %l7
25944add %l4, 1, %l4
25945or %l7, %l4, %l7
25946stx %l7, [%i0 + 0]
25947add %l4, 1, %l4
25948
25949P2065: !_DWST_BINIT [4] (maybe <- 0x100001a) (Int)
25950wr %g0, 0xe2, %asi
25951sllx %l4, 32, %l6
25952add %l4, 1, %l4
25953or %l6, %l4, %l6
25954stxa %l6, [%i1 + 0] %asi
25955add %l4, 1, %l4
25956
25957P2066: !_MEMBAR (Int)
25958membar #StoreLoad
25959
25960P2067: !_CASX [21] (maybe <- 0x100001c) (Int)
25961sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
25962sub %i0, %i2, %i2
25963ldx [%i2], %l3
25964! move %l3(upper) -> %o2(lower)
25965srlx %l3, 32, %l6
25966or %l6, %o2, %o2
25967! move %l3(lower) -> %o3(upper)
25968sllx %l3, 32, %o3
25969mov %l3, %l6
25970sllx %l4, 32, %l3
25971add %l4, 1, %l4
25972or %l4, %l3, %l3
25973casx [%i2], %l6, %l3
25974! move %l3(upper) -> %o3(lower)
25975srlx %l3, 32, %l6
25976or %l6, %o3, %o3
25977! move %l3(lower) -> %o4(upper)
25978sllx %l3, 32, %o4
25979add %l4, 1, %l4
25980
25981P2068: !_SWAP [16] (maybe <- 0x100001e) (Int)
25982sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
25983sub %i0, %i3, %i3
25984mov %l4, %o5
25985swap [%i3 + 4], %o5
25986! move %o5(lower) -> %o4(lower)
25987srl %o5, 0, %l6
25988or %l6, %o4, %o4
25989!---- flushing int results buffer----
25990mov %o0, %l5
25991mov %o1, %l5
25992mov %o2, %l5
25993mov %o3, %l5
25994mov %o4, %l5
25995add %l4, 1, %l4
25996
25997P2069: !_DWLD [1] (Int)
25998ldx [%i0 + 0], %o0
25999! move %o0(upper) -> %o0(upper)
26000! move %o0(lower) -> %o0(lower)
26001
26002P2070: !_DWLD [13] (Int)
26003sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
26004add %i0, %i2, %i2
26005ldx [%i2 + 0], %o1
26006! move %o1(upper) -> %o1(upper)
26007! move %o1(lower) -> %o1(lower)
26008
26009P2071: !_CAS [18] (maybe <- 0x100001f) (Int)
26010sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
26011sub %i0, %i3, %i3
26012lduw [%i3], %o2
26013mov %o2, %l3
26014! move %l3(lower) -> %o2(upper)
26015sllx %l3, 32, %o2
26016mov %l4, %o5
26017cas [%i3], %l3, %o5
26018! move %o5(lower) -> %o2(lower)
26019srl %o5, 0, %l3
26020or %l3, %o2, %o2
26021add %l4, 1, %l4
26022
26023P2072: !_SWAP [1] (maybe <- 0x1000020) (Int)
26024mov %l4, %o3
26025swap [%i0 + 4], %o3
26026! move %o3(lower) -> %o3(upper)
26027sllx %o3, 32, %o3
26028add %l4, 1, %l4
26029
26030P2073: !_DWST [14] (maybe <- 0x1000021) (Int)
26031mov %l4, %o5
26032stx %o5, [%i2 + 8]
26033add %l4, 1, %l4
26034
26035P2074: !_ST [23] (maybe <- 0x1000022) (Int)
26036sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
26037sub %i0, %i2, %i2
26038stw %l4, [%i2 + 12 ]
26039add %l4, 1, %l4
26040
26041P2075: !_MEMBAR (FP) (CBR)
26042
26043! cbranch
26044andcc %l0, 1, %g0
26045be,pt %xcc, TARGET2075
26046nop
26047RET2075:
26048
26049! lfsr step begin
26050srlx %l0, 1, %l6
26051xnor %l6, %l0, %l6
26052sllx %l6, 63, %l6
26053or %l6, %l0, %l0
26054srlx %l0, 1, %l0
26055
26056
26057P2076: !_BST [13] (maybe <- 0x40800015) (FP)
26058wr %g0, 0xf0, %asi
26059sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
26060add %i0, %i3, %i3
26061! preparing store val #0, next val will be in f32
26062fmovs %f16, %f20
26063fadds %f16, %f17, %f16
26064! preparing store val #1, next val will be in f33
26065fmovs %f16, %f21
26066fadds %f16, %f17, %f16
26067! preparing store val #2, next val will be in f35
26068fmovd %f20, %f32
26069fmovs %f16, %f21
26070fadds %f16, %f17, %f16
26071fmovd %f20, %f34
26072membar #Sync
26073stda %f32, [%i3 + 0 ] %asi
26074
26075P2077: !_MEMBAR (FP) (Branch target of P2445)
26076membar #StoreLoad
26077ba P2078
26078nop
26079
26080TARGET2445:
26081ba RET2445
26082nop
26083
26084
26085P2078: !_SWAP [18] (maybe <- 0x1000023) (Int)
26086sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
26087sub %i0, %i2, %i2
26088mov %l4, %o5
26089swap [%i2 + 0], %o5
26090! move %o5(lower) -> %o3(lower)
26091srl %o5, 0, %l6
26092or %l6, %o3, %o3
26093add %l4, 1, %l4
26094
26095P2079: !_ST [4] (maybe <- 0x40800018) (FP)
26096! preparing store val #0, next val will be in f20
26097fmovs %f16, %f20
26098fadds %f16, %f17, %f16
26099st %f20, [%i1 + 4 ]
26100
26101P2080: !_DWST_BINIT [14] (maybe <- 0x1000024) (Int)
26102wr %g0, 0xe2, %asi
26103mov %l4, %o5
26104stxa %o5, [%i3 + 8] %asi
26105add %l4, 1, %l4
26106
26107P2081: !_MEMBAR (Int)
26108membar #StoreLoad
26109
26110P2082: !_CASX [2] (maybe <- 0x1000025) (Int)
26111add %i0, 8, %o5
26112ldx [%o5], %o4
26113! move %o4(upper) -> %o4(upper)
26114! move %o4(lower) -> %o4(lower)
26115!---- flushing int results buffer----
26116mov %o0, %l5
26117mov %o1, %l5
26118mov %o2, %l5
26119mov %o3, %l5
26120mov %o4, %l5
26121mov %o4, %l7
26122mov %l4, %o0
26123casx [%o5], %l7, %o0
26124! move %o0(upper) -> %o0(upper)
26125! move %o0(lower) -> %o0(lower)
26126add %l4, 1, %l4
26127
26128P2083: !_MEMBAR (FP)
26129
26130P2084: !_BSTC [17] (maybe <- 0x40800019) (FP)
26131wr %g0, 0xe0, %asi
26132sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
26133sub %i0, %i3, %i3
26134! preparing store val #0, next val will be in f32
26135fmovs %f16, %f20
26136fadds %f16, %f17, %f16
26137! preparing store val #1, next val will be in f33
26138fmovs %f16, %f21
26139fadds %f16, %f17, %f16
26140! preparing store val #2, next val will be in f35
26141fmovd %f20, %f32
26142fmovs %f16, %f21
26143fadds %f16, %f17, %f16
26144fmovd %f20, %f34
26145membar #Sync
26146stda %f32, [%i3 + 0 ] %asi
26147
26148P2085: !_MEMBAR (FP)
26149membar #StoreLoad
26150
26151P2086: !_DWLD [11] (Int) (Branch target of P2524)
26152sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
26153add %i0, %i2, %i2
26154ldx [%i2 + 8], %o1
26155! move %o1(lower) -> %o1(upper)
26156sllx %o1, 32, %o1
26157ba P2087
26158nop
26159
26160TARGET2524:
26161ba RET2524
26162nop
26163
26164
26165P2087: !_ST [23] (maybe <- 0x1000026) (Int)
26166sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
26167sub %i0, %i3, %i3
26168stw %l4, [%i3 + 12 ]
26169add %l4, 1, %l4
26170
26171P2088: !_MEMBAR (FP)
26172
26173P2089: !_BSTC [13] (maybe <- 0x4080001c) (FP)
26174wr %g0, 0xe0, %asi
26175sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
26176add %i0, %i2, %i2
26177! preparing store val #0, next val will be in f32
26178fmovs %f16, %f20
26179fadds %f16, %f17, %f16
26180! preparing store val #1, next val will be in f33
26181fmovs %f16, %f21
26182fadds %f16, %f17, %f16
26183! preparing store val #2, next val will be in f35
26184fmovd %f20, %f32
26185fmovs %f16, %f21
26186fadds %f16, %f17, %f16
26187fmovd %f20, %f34
26188membar #Sync
26189stda %f32, [%i2 + 0 ] %asi
26190
26191P2090: !_MEMBAR (FP)
26192membar #StoreLoad
26193
26194P2091: !_ST [4] (maybe <- 0x1000027) (Int)
26195stw %l4, [%i1 + 4 ]
26196add %l4, 1, %l4
26197
26198P2092: !_ST_BINIT [6] (maybe <- 0x1000028) (Int)
26199wr %g0, 0xe2, %asi
26200sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
26201sub %i0, %i3, %i3
26202stwa %l4, [%i3 + 0] %asi
26203add %l4, 1, %l4
26204
26205P2093: !_MEMBAR (Int)
26206membar #StoreLoad
26207
26208P2094: !_SWAP [7] (maybe <- 0x1000029) (Int)
26209mov %l4, %l6
26210swap [%i3 + 4], %l6
26211! move %l6(lower) -> %o1(lower)
26212srl %l6, 0, %o5
26213or %o5, %o1, %o1
26214add %l4, 1, %l4
26215
26216P2095: !_DWLD [1] (Int)
26217ldx [%i0 + 0], %o2
26218! move %o2(upper) -> %o2(upper)
26219! move %o2(lower) -> %o2(lower)
26220
26221P2096: !_MEMBAR (FP)
26222
26223P2097: !_BSTC [22] (maybe <- 0x4080001f) (FP)
26224wr %g0, 0xe0, %asi
26225sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
26226sub %i0, %i2, %i2
26227! preparing store val #0, next val will be in f32
26228fmovs %f16, %f20
26229fadds %f16, %f17, %f16
26230! preparing store val #1, next val will be in f33
26231fmovs %f16, %f21
26232fadds %f16, %f17, %f16
26233! preparing store val #2, next val will be in f35
26234fmovd %f20, %f32
26235fmovs %f16, %f21
26236fadds %f16, %f17, %f16
26237fmovd %f20, %f34
26238membar #Sync
26239stda %f32, [%i2 + 0 ] %asi
26240
26241P2098: !_MEMBAR (FP)
26242membar #StoreLoad
26243
26244P2099: !_PREFETCH [22] (Int)
26245prefetch [%i2 + 4], 23
26246
26247P2100: !_SWAP [7] (maybe <- 0x100002a) (Int)
26248mov %l4, %o3
26249swap [%i3 + 4], %o3
26250! move %o3(lower) -> %o3(upper)
26251sllx %o3, 32, %o3
26252add %l4, 1, %l4
26253
26254P2101: !_CAS [12] (maybe <- 0x100002b) (Int)
26255sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
26256add %i0, %i3, %i3
26257lduw [%i3], %l6
26258mov %l6, %l7
26259! move %l7(lower) -> %o3(lower)
26260or %l7, %o3, %o3
26261mov %l4, %o4
26262cas [%i3], %l7, %o4
26263! move %o4(lower) -> %o4(upper)
26264sllx %o4, 32, %o4
26265add %l4, 1, %l4
26266
26267P2102: !_MEMBAR (FP)
26268membar #StoreLoad
26269
26270P2103: !_BLD [11] (FP)
26271wr %g0, 0xf0, %asi
26272sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
26273add %i0, %i2, %i2
26274ldda [%i2 + 0] %asi, %f32
26275membar #Sync
26276! 3 addresses covered
26277fmovd %f32, %f18
26278fmovs %f18, %f3
26279fmovs %f19, %f4
26280fmovd %f34, %f18
26281fmovs %f19, %f5
26282
26283P2104: !_MEMBAR (FP)
26284
26285P2105: !_PREFETCH [10] (Int)
26286prefetch [%i2 + 4], 2
26287
26288P2106: !_MEMBAR (FP)
26289
26290P2107: !_BSTC [20] (maybe <- 0x40800022) (FP)
26291wr %g0, 0xe0, %asi
26292sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
26293sub %i0, %i3, %i3
26294! preparing store val #0, next val will be in f32
26295fmovs %f16, %f20
26296fadds %f16, %f17, %f16
26297! preparing store val #1, next val will be in f33
26298fmovs %f16, %f21
26299fadds %f16, %f17, %f16
26300! preparing store val #2, next val will be in f35
26301fmovd %f20, %f32
26302fmovs %f16, %f21
26303fadds %f16, %f17, %f16
26304fmovd %f20, %f34
26305membar #Sync
26306stda %f32, [%i3 + 0 ] %asi
26307
26308P2108: !_MEMBAR (FP)
26309membar #StoreLoad
26310
26311P2109: !_REPLACEMENT [16] (Int)
26312sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
26313add %i0, %i2, %i2
26314sethi %hi(0x20000), %l6
26315ld [%i2+4], %o5
26316st %o5, [%i2+4]
26317add %i2, %l6, %l7
26318ld [%l7+4], %o5
26319st %o5, [%l7+4]
26320add %l7, %l6, %l7
26321ld [%l7+4], %o5
26322st %o5, [%l7+4]
26323add %l7, %l6, %l7
26324ld [%l7+4], %o5
26325st %o5, [%l7+4]
26326add %l7, %l6, %l7
26327ld [%l7+4], %o5
26328st %o5, [%l7+4]
26329add %l7, %l6, %l7
26330ld [%l7+4], %o5
26331st %o5, [%l7+4]
26332add %l7, %l6, %l7
26333ld [%l7+4], %o5
26334st %o5, [%l7+4]
26335add %l7, %l6, %l7
26336ld [%l7+4], %o5
26337st %o5, [%l7+4]
26338
26339P2110: !_ST_BINIT [12] (maybe <- 0x100002c) (Int)
26340wr %g0, 0xe2, %asi
26341sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
26342add %i0, %i3, %i3
26343stwa %l4, [%i3 + 0] %asi
26344add %l4, 1, %l4
26345
26346P2111: !_MEMBAR (Int)
26347
26348P2112: !_BST [12] (maybe <- 0x40800025) (FP)
26349wr %g0, 0xf0, %asi
26350! preparing store val #0, next val will be in f32
26351fmovs %f16, %f20
26352fadds %f16, %f17, %f16
26353! preparing store val #1, next val will be in f33
26354fmovs %f16, %f21
26355fadds %f16, %f17, %f16
26356! preparing store val #2, next val will be in f35
26357fmovd %f20, %f32
26358fmovs %f16, %f21
26359fadds %f16, %f17, %f16
26360fmovd %f20, %f34
26361membar #Sync
26362stda %f32, [%i3 + 0 ] %asi
26363
26364P2113: !_MEMBAR (FP)
26365membar #StoreLoad
26366
26367P2114: !_BLD [21] (FP)
26368wr %g0, 0xf0, %asi
26369sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
26370sub %i0, %i2, %i2
26371ldda [%i2 + 0] %asi, %f32
26372membar #Sync
26373! 3 addresses covered
26374fmovd %f32, %f6
26375fmovd %f34, %f18
26376fmovs %f19, %f8
26377
26378P2115: !_MEMBAR (FP)
26379
26380P2116: !_CAS [21] (maybe <- 0x100002d) (Int)
26381lduw [%i2], %l6
26382mov %l6, %l7
26383! move %l7(lower) -> %o4(lower)
26384or %l7, %o4, %o4
26385!---- flushing int results buffer----
26386mov %o0, %l5
26387mov %o1, %l5
26388mov %o2, %l5
26389mov %o3, %l5
26390mov %o4, %l5
26391mov %l4, %o0
26392cas [%i2], %l7, %o0
26393! move %o0(lower) -> %o0(upper)
26394sllx %o0, 32, %o0
26395add %l4, 1, %l4
26396
26397P2117: !_DWST_BINIT [4] (maybe <- 0x100002e) (Int)
26398wr %g0, 0xe2, %asi
26399sllx %l4, 32, %l7
26400add %l4, 1, %l4
26401or %l7, %l4, %l7
26402stxa %l7, [%i1 + 0] %asi
26403add %l4, 1, %l4
26404
26405P2118: !_MEMBAR (Int)
26406
26407P2119: !_BSTC [14] (maybe <- 0x40800028) (FP)
26408wr %g0, 0xe0, %asi
26409! preparing store val #0, next val will be in f32
26410fmovs %f16, %f20
26411fadds %f16, %f17, %f16
26412! preparing store val #1, next val will be in f33
26413fmovs %f16, %f21
26414fadds %f16, %f17, %f16
26415! preparing store val #2, next val will be in f35
26416fmovd %f20, %f32
26417fmovs %f16, %f21
26418fadds %f16, %f17, %f16
26419fmovd %f20, %f34
26420membar #Sync
26421stda %f32, [%i3 + 0 ] %asi
26422
26423P2120: !_MEMBAR (FP)
26424
26425P2121: !_BSTC [10] (maybe <- 0x4080002b) (FP)
26426wr %g0, 0xe0, %asi
26427sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
26428add %i0, %i3, %i3
26429! preparing store val #0, next val will be in f32
26430fmovs %f16, %f20
26431fadds %f16, %f17, %f16
26432! preparing store val #1, next val will be in f33
26433fmovs %f16, %f21
26434fadds %f16, %f17, %f16
26435! preparing store val #2, next val will be in f35
26436fmovd %f20, %f32
26437fmovs %f16, %f21
26438fadds %f16, %f17, %f16
26439fmovd %f20, %f34
26440membar #Sync
26441stda %f32, [%i3 + 0 ] %asi
26442
26443P2122: !_MEMBAR (FP)
26444membar #StoreLoad
26445
26446P2123: !_LD [4] (Int)
26447lduw [%i1 + 4], %l3
26448! move %l3(lower) -> %o0(lower)
26449or %l3, %o0, %o0
26450
26451P2124: !_LD [6] (Int)
26452sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
26453sub %i0, %i2, %i2
26454lduw [%i2 + 0], %o1
26455! move %o1(lower) -> %o1(upper)
26456sllx %o1, 32, %o1
26457
26458P2125: !_LD [20] (Int)
26459sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
26460sub %i0, %i3, %i3
26461lduw [%i3 + 12], %l3
26462! move %l3(lower) -> %o1(lower)
26463or %l3, %o1, %o1
26464
26465P2126: !_CASX [12] (maybe <- 0x1000030) (Int)
26466sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
26467add %i0, %i2, %i2
26468ldx [%i2], %o2
26469! move %o2(upper) -> %o2(upper)
26470! move %o2(lower) -> %o2(lower)
26471mov %o2, %l6
26472sllx %l4, 32, %o3
26473add %l4, 1, %l4
26474or %l4, %o3, %o3
26475casx [%i2], %l6, %o3
26476! move %o3(upper) -> %o3(upper)
26477! move %o3(lower) -> %o3(lower)
26478add %l4, 1, %l4
26479
26480P2127: !_ST_BINIT [1] (maybe <- 0x1000032) (Int)
26481wr %g0, 0xe2, %asi
26482stwa %l4, [%i0 + 4] %asi
26483add %l4, 1, %l4
26484
26485P2128: !_MEMBAR (Int) (CBR)
26486membar #StoreLoad
26487
26488! cbranch
26489andcc %l0, 1, %g0
26490be,pt %xcc, TARGET2128
26491nop
26492RET2128:
26493
26494! lfsr step begin
26495srlx %l0, 1, %l3
26496xnor %l3, %l0, %l3
26497sllx %l3, 63, %l3
26498or %l3, %l0, %l0
26499srlx %l0, 1, %l0
26500
26501
26502P2129: !_BLD [0] (FP)
26503wr %g0, 0xf0, %asi
26504ldda [%i0 + 0] %asi, %f32
26505membar #Sync
26506! 3 addresses covered
26507fmovd %f32, %f18
26508fmovs %f18, %f9
26509fmovs %f19, %f10
26510fmovd %f34, %f18
26511fmovs %f19, %f11
26512
26513P2130: !_MEMBAR (FP)
26514
26515P2131: !_DWST [0] (maybe <- 0x1000033) (Int)
26516sllx %l4, 32, %l7
26517add %l4, 1, %l4
26518or %l7, %l4, %l7
26519stx %l7, [%i0 + 0]
26520add %l4, 1, %l4
26521
26522P2132: !_DWLD [19] (Int)
26523ldx [%i3 + 0], %o4
26524! move %o4(upper) -> %o4(upper)
26525! move %o4(lower) -> %o4(lower)
26526!---- flushing int results buffer----
26527mov %o0, %l5
26528mov %o1, %l5
26529mov %o2, %l5
26530mov %o3, %l5
26531mov %o4, %l5
26532
26533P2133: !_CASX [4] (maybe <- 0x1000035) (Int)
26534ldx [%i1], %o0
26535! move %o0(upper) -> %o0(upper)
26536! move %o0(lower) -> %o0(lower)
26537mov %o0, %o5
26538sllx %l4, 32, %o1
26539add %l4, 1, %l4
26540or %l4, %o1, %o1
26541casx [%i1], %o5, %o1
26542! move %o1(upper) -> %o1(upper)
26543! move %o1(lower) -> %o1(lower)
26544add %l4, 1, %l4
26545
26546P2134: !_CAS [21] (maybe <- 0x1000037) (Int)
26547sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
26548sub %i0, %i3, %i3
26549lduw [%i3], %o2
26550mov %o2, %o5
26551! move %o5(lower) -> %o2(upper)
26552sllx %o5, 32, %o2
26553mov %l4, %l7
26554cas [%i3], %o5, %l7
26555! move %l7(lower) -> %o2(lower)
26556srl %l7, 0, %o5
26557or %o5, %o2, %o2
26558add %l4, 1, %l4
26559
26560P2135: !_MEMBAR (FP)
26561
26562P2136: !_BST [7] (maybe <- 0x4080002e) (FP)
26563wr %g0, 0xf0, %asi
26564sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
26565sub %i0, %i2, %i2
26566! preparing store val #0, next val will be in f32
26567fmovs %f16, %f20
26568fadds %f16, %f17, %f16
26569! preparing store val #1, next val will be in f33
26570fmovs %f16, %f21
26571fadds %f16, %f17, %f16
26572! preparing store val #2, next val will be in f35
26573fmovd %f20, %f32
26574fmovs %f16, %f21
26575fadds %f16, %f17, %f16
26576fmovd %f20, %f34
26577membar #Sync
26578stda %f32, [%i2 + 0 ] %asi
26579
26580P2137: !_MEMBAR (FP)
26581membar #StoreLoad
26582
26583P2138: !_SWAP [0] (maybe <- 0x1000038) (Int) (LE)
26584wr %g0, 0x88, %asi
26585mov %l4, %o3
26586! Change single-word-level endianess (big endian <-> little endian)
26587sethi %hi(0xff00ff00), %l7
26588or %l7, %lo(0xff00ff00), %l7
26589and %o3, %l7, %o5
26590srl %o5, 8, %o5
26591sll %o3, 8, %o3
26592and %o3, %l7, %o3
26593or %o3, %o5, %o3
26594srl %o3, 16, %o5
26595sll %o3, 16, %o3
26596srl %o3, 0, %o3
26597or %o3, %o5, %o3
26598swapa [%i0 + 0] %asi, %o3
26599! move %o3(lower) -> %o3(upper)
26600sllx %o3, 32, %o3
26601add %l4, 1, %l4
26602
26603P2139: !_CASX [23] (maybe <- 0x1000039) (Int)
26604add %i3, 8, %l7
26605ldx [%l7], %l3
26606! move %l3(upper) -> %o3(lower)
26607srlx %l3, 32, %l6
26608or %l6, %o3, %o3
26609! move %l3(lower) -> %o4(upper)
26610sllx %l3, 32, %o4
26611mov %l3, %l6
26612mov %l4, %l3
26613casx [%l7], %l6, %l3
26614! move %l3(upper) -> %o4(lower)
26615srlx %l3, 32, %l6
26616or %l6, %o4, %o4
26617!---- flushing int results buffer----
26618mov %o0, %l5
26619mov %o1, %l5
26620mov %o2, %l5
26621mov %o3, %l5
26622mov %o4, %l5
26623! move %l3(lower) -> %o0(upper)
26624sllx %l3, 32, %o0
26625add %l4, 1, %l4
26626
26627P2140: !_CAS [6] (maybe <- 0x100003a) (Int)
26628lduw [%i2], %l3
26629mov %l3, %l6
26630! move %l6(lower) -> %o0(lower)
26631or %l6, %o0, %o0
26632mov %l4, %o1
26633cas [%i2], %l6, %o1
26634! move %o1(lower) -> %o1(upper)
26635sllx %o1, 32, %o1
26636add %l4, 1, %l4
26637
26638P2141: !_ST [11] (maybe <- 0x100003b) (Int)
26639sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
26640add %i0, %i3, %i3
26641stw %l4, [%i3 + 12 ]
26642add %l4, 1, %l4
26643
26644P2142: !_LDD [8] (Int)
26645ldd [%i2 + 8], %l6
26646! move %l7(lower) -> %o1(lower)
26647or %l7, %o1, %o1
26648
26649P2143: !_MEMBAR (FP)
26650membar #StoreLoad
26651
26652P2144: !_BLD [4] (FP)
26653wr %g0, 0xf0, %asi
26654ldda [%i1 + 0] %asi, %f32
26655membar #Sync
26656! 3 addresses covered
26657fmovd %f32, %f12
26658fmovd %f34, %f18
26659fmovs %f19, %f14
26660
26661P2145: !_MEMBAR (FP)
26662
26663P2146: !_CASX [2] (maybe <- 0x100003c) (Int)
26664add %i0, 8, %l6
26665ldx [%l6], %o2
26666! move %o2(upper) -> %o2(upper)
26667! move %o2(lower) -> %o2(lower)
26668mov %o2, %l3
26669mov %l4, %o3
26670casx [%l6], %l3, %o3
26671! move %o3(upper) -> %o3(upper)
26672! move %o3(lower) -> %o3(lower)
26673add %l4, 1, %l4
26674
26675P2147: !_MEMBAR (FP)
26676
26677P2148: !_BSTC [10] (maybe <- 0x40800031) (FP)
26678wr %g0, 0xe0, %asi
26679! preparing store val #0, next val will be in f32
26680fmovs %f16, %f20
26681fadds %f16, %f17, %f16
26682! preparing store val #1, next val will be in f33
26683fmovs %f16, %f21
26684fadds %f16, %f17, %f16
26685! preparing store val #2, next val will be in f35
26686fmovd %f20, %f32
26687fmovs %f16, %f21
26688fadds %f16, %f17, %f16
26689fmovd %f20, %f34
26690membar #Sync
26691stda %f32, [%i3 + 0 ] %asi
26692
26693P2149: !_MEMBAR (FP)
26694membar #StoreLoad
26695
26696P2150: !_LDD [16] (Int)
26697sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
26698sub %i0, %i2, %i2
26699ldd [%i2 + 0], %l6
26700! move %l6(lower) -> %o4(upper)
26701sllx %l6, 32, %o4
26702! move %l7(lower) -> %o4(lower)
26703or %l7, %o4, %o4
26704!---- flushing int results buffer----
26705mov %o0, %l5
26706mov %o1, %l5
26707mov %o2, %l5
26708mov %o3, %l5
26709mov %o4, %l5
26710
26711P2151: !_DWST_BINIT [13] (maybe <- 0x100003d) (Int)
26712wr %g0, 0xe2, %asi
26713sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
26714add %i0, %i3, %i3
26715sllx %l4, 32, %l3
26716add %l4, 1, %l4
26717or %l3, %l4, %l3
26718stxa %l3, [%i3 + 0] %asi
26719add %l4, 1, %l4
26720
26721P2152: !_MEMBAR (Int)
26722
26723P2153: !_BST [15] (maybe <- 0x40800034) (FP) (CBR) (Branch target of P2940)
26724wr %g0, 0xf0, %asi
26725! preparing store val #0, next val will be in f32
26726fmovs %f16, %f20
26727fadds %f16, %f17, %f16
26728! preparing store val #1, next val will be in f33
26729fmovs %f16, %f21
26730fadds %f16, %f17, %f16
26731! preparing store val #2, next val will be in f35
26732fmovd %f20, %f32
26733fmovs %f16, %f21
26734fadds %f16, %f17, %f16
26735fmovd %f20, %f34
26736membar #Sync
26737stda %f32, [%i2 + 0 ] %asi
26738
26739! cbranch
26740andcc %l0, 1, %g0
26741be,pn %xcc, TARGET2153
26742nop
26743RET2153:
26744
26745! lfsr step begin
26746srlx %l0, 1, %l7
26747xnor %l7, %l0, %l7
26748sllx %l7, 63, %l7
26749or %l7, %l0, %l0
26750srlx %l0, 1, %l0
26751
26752ba P2154
26753nop
26754
26755TARGET2940:
26756ba RET2940
26757nop
26758
26759
26760P2154: !_MEMBAR (FP)
26761
26762P2155: !_BST [22] (maybe <- 0x40800037) (FP)
26763wr %g0, 0xf0, %asi
26764sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
26765sub %i0, %i2, %i2
26766! preparing store val #0, next val will be in f32
26767fmovs %f16, %f20
26768fadds %f16, %f17, %f16
26769! preparing store val #1, next val will be in f33
26770fmovs %f16, %f21
26771fadds %f16, %f17, %f16
26772! preparing store val #2, next val will be in f35
26773fmovd %f20, %f32
26774fmovs %f16, %f21
26775fadds %f16, %f17, %f16
26776fmovd %f20, %f34
26777membar #Sync
26778stda %f32, [%i2 + 0 ] %asi
26779
26780P2156: !_MEMBAR (FP)
26781membar #StoreLoad
26782
26783P2157: !_DWST_BINIT [13] (maybe <- 0x100003f) (Int)
26784wr %g0, 0xe2, %asi
26785sllx %l4, 32, %l7
26786add %l4, 1, %l4
26787or %l7, %l4, %l7
26788stxa %l7, [%i3 + 0] %asi
26789add %l4, 1, %l4
26790
26791P2158: !_MEMBAR (Int)
26792membar #StoreLoad
26793
26794P2159: !_LDD [16] (Int)
26795sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
26796sub %i0, %i3, %i3
26797ldd [%i3 + 0], %l6
26798! move %l6(lower) -> %o0(upper)
26799sllx %l6, 32, %o0
26800! move %l7(lower) -> %o0(lower)
26801or %l7, %o0, %o0
26802
26803P2160: !_DWST_BINIT [23] (maybe <- 0x1000041) (Int)
26804wr %g0, 0xe2, %asi
26805mov %l4, %l3
26806stxa %l3, [%i2 + 8] %asi
26807add %l4, 1, %l4
26808
26809P2161: !_MEMBAR (Int)
26810
26811P2162: !_BSTC [13] (maybe <- 0x4080003a) (FP)
26812wr %g0, 0xe0, %asi
26813sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
26814add %i0, %i2, %i2
26815! preparing store val #0, next val will be in f32
26816fmovs %f16, %f20
26817fadds %f16, %f17, %f16
26818! preparing store val #1, next val will be in f33
26819fmovs %f16, %f21
26820fadds %f16, %f17, %f16
26821! preparing store val #2, next val will be in f35
26822fmovd %f20, %f32
26823fmovs %f16, %f21
26824fadds %f16, %f17, %f16
26825fmovd %f20, %f34
26826membar #Sync
26827stda %f32, [%i2 + 0 ] %asi
26828
26829P2163: !_MEMBAR (FP)
26830membar #StoreLoad
26831
26832P2164: !_SWAP [10] (maybe <- 0x1000042) (Int)
26833sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
26834add %i0, %i3, %i3
26835mov %l4, %o1
26836swap [%i3 + 4], %o1
26837! move %o1(lower) -> %o1(upper)
26838sllx %o1, 32, %o1
26839add %l4, 1, %l4
26840
26841P2165: !_PREFETCH [18] (Int)
26842sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
26843sub %i0, %i2, %i2
26844prefetch [%i2 + 0], 22
26845
26846P2166: !_MEMBAR (FP)
26847membar #StoreLoad
26848
26849P2167: !_BLD [16] (FP)
26850wr %g0, 0xf0, %asi
26851sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
26852sub %i0, %i3, %i3
26853ldda [%i3 + 0] %asi, %f32
26854membar #Sync
26855! 3 addresses covered
26856fmovd %f32, %f18
26857fmovs %f18, %f15
26858!---- flushing fp results buffer to %f30 ----
26859fmovd %f0, %f30
26860fmovd %f2, %f30
26861fmovd %f4, %f30
26862fmovd %f6, %f30
26863fmovd %f8, %f30
26864fmovd %f10, %f30
26865fmovd %f12, %f30
26866fmovd %f14, %f30
26867!--
26868fmovs %f19, %f0
26869fmovd %f34, %f18
26870fmovs %f19, %f1
26871
26872P2168: !_MEMBAR (FP)
26873
26874P2169: !_ST [13] (maybe <- 0x4080003d) (FP)
26875sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
26876add %i0, %i2, %i2
26877! preparing store val #0, next val will be in f20
26878fmovs %f16, %f20
26879fadds %f16, %f17, %f16
26880st %f20, [%i2 + 4 ]
26881
26882P2170: !_DWST_BINIT [12] (maybe <- 0x1000043) (Int)
26883wr %g0, 0xe2, %asi
26884sllx %l4, 32, %l3
26885add %l4, 1, %l4
26886or %l3, %l4, %l3
26887stxa %l3, [%i2 + 0] %asi
26888add %l4, 1, %l4
26889
26890P2171: !_MEMBAR (Int)
26891membar #StoreLoad
26892
26893P2172: !_DWST [13] (maybe <- 0x1000045) (Int)
26894sllx %l4, 32, %o5
26895add %l4, 1, %l4
26896or %o5, %l4, %o5
26897stx %o5, [%i2 + 0]
26898add %l4, 1, %l4
26899
26900P2173: !_CASX [2] (maybe <- 0x1000047) (Int)
26901add %i0, 8, %o5
26902ldx [%o5], %l6
26903! move %l6(upper) -> %o1(lower)
26904srlx %l6, 32, %l7
26905or %l7, %o1, %o1
26906! move %l6(lower) -> %o2(upper)
26907sllx %l6, 32, %o2
26908mov %l6, %l7
26909mov %l4, %l6
26910casx [%o5], %l7, %l6
26911! move %l6(upper) -> %o2(lower)
26912srlx %l6, 32, %l7
26913or %l7, %o2, %o2
26914! move %l6(lower) -> %o3(upper)
26915sllx %l6, 32, %o3
26916add %l4, 1, %l4
26917
26918P2174: !_ST_BINIT [13] (maybe <- 0x1000048) (Int)
26919wr %g0, 0xe2, %asi
26920stwa %l4, [%i2 + 4] %asi
26921add %l4, 1, %l4
26922
26923P2175: !_MEMBAR (Int)
26924membar #StoreLoad
26925
26926P2176: !_BLD [9] (FP)
26927wr %g0, 0xf0, %asi
26928sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
26929add %i0, %i3, %i3
26930ldda [%i3 + 0] %asi, %f32
26931membar #Sync
26932! 3 addresses covered
26933fmovd %f32, %f2
26934fmovd %f34, %f18
26935fmovs %f19, %f4
26936
26937P2177: !_MEMBAR (FP)
26938
26939P2178: !_DWST [16] (maybe <- 0x1000049) (Int)
26940sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
26941sub %i0, %i2, %i2
26942sllx %l4, 32, %l6
26943add %l4, 1, %l4
26944or %l6, %l4, %l6
26945stx %l6, [%i2 + 0]
26946add %l4, 1, %l4
26947
26948P2179: !_CAS [5] (maybe <- 0x100004b) (Int)
26949add %i1, 12, %l6
26950lduw [%l6], %o5
26951mov %o5, %l3
26952! move %l3(lower) -> %o3(lower)
26953or %l3, %o3, %o3
26954mov %l4, %o4
26955cas [%l6], %l3, %o4
26956! move %o4(lower) -> %o4(upper)
26957sllx %o4, 32, %o4
26958add %l4, 1, %l4
26959
26960P2180: !_LD [4] (Int)
26961lduw [%i1 + 4], %l6
26962! move %l6(lower) -> %o4(lower)
26963or %l6, %o4, %o4
26964!---- flushing int results buffer----
26965mov %o0, %l5
26966mov %o1, %l5
26967mov %o2, %l5
26968mov %o3, %l5
26969mov %o4, %l5
26970
26971P2181: !_CAS [22] (maybe <- 0x100004c) (Int)
26972sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
26973sub %i0, %i3, %i3
26974add %i3, 4, %o5
26975lduw [%o5], %o0
26976mov %o0, %l7
26977! move %l7(lower) -> %o0(upper)
26978sllx %l7, 32, %o0
26979mov %l4, %l6
26980cas [%o5], %l7, %l6
26981! move %l6(lower) -> %o0(lower)
26982srl %l6, 0, %l7
26983or %l7, %o0, %o0
26984add %l4, 1, %l4
26985
26986P2182: !_DWLD [19] (Int)
26987sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
26988sub %i0, %i2, %i2
26989ldx [%i2 + 0], %o1
26990! move %o1(upper) -> %o1(upper)
26991! move %o1(lower) -> %o1(lower)
26992
26993P2183: !_CASX [16] (maybe <- 0x100004d) (Int)
26994sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
26995sub %i0, %i3, %i3
26996ldx [%i3], %o2
26997! move %o2(upper) -> %o2(upper)
26998! move %o2(lower) -> %o2(lower)
26999mov %o2, %l3
27000sllx %l4, 32, %o3
27001add %l4, 1, %l4
27002or %l4, %o3, %o3
27003casx [%i3], %l3, %o3
27004! move %o3(upper) -> %o3(upper)
27005! move %o3(lower) -> %o3(lower)
27006add %l4, 1, %l4
27007
27008P2184: !_DWLD [10] (Int)
27009sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
27010add %i0, %i2, %i2
27011ldx [%i2 + 0], %o4
27012! move %o4(upper) -> %o4(upper)
27013! move %o4(lower) -> %o4(lower)
27014!---- flushing int results buffer----
27015mov %o0, %l5
27016mov %o1, %l5
27017mov %o2, %l5
27018mov %o3, %l5
27019mov %o4, %l5
27020
27021P2185: !_ST_BINIT [19] (maybe <- 0x100004f) (Int) (Branch target of P2766)
27022wr %g0, 0xe2, %asi
27023sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
27024sub %i0, %i3, %i3
27025stwa %l4, [%i3 + 4] %asi
27026add %l4, 1, %l4
27027ba P2186
27028nop
27029
27030TARGET2766:
27031ba RET2766
27032nop
27033
27034
27035P2186: !_MEMBAR (Int)
27036membar #StoreLoad
27037
27038P2187: !_SWAP [21] (maybe <- 0x1000050) (Int)
27039sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
27040sub %i0, %i2, %i2
27041mov %l4, %o0
27042swap [%i2 + 0], %o0
27043! move %o0(lower) -> %o0(upper)
27044sllx %o0, 32, %o0
27045add %l4, 1, %l4
27046
27047P2188: !_DWLD [19] (FP) (Branch target of P2075)
27048ldd [%i3 + 0], %f18
27049! 2 addresses covered
27050fmovs %f18, %f5
27051fmovs %f19, %f6
27052ba P2189
27053nop
27054
27055TARGET2075:
27056ba RET2075
27057nop
27058
27059
27060P2189: !_MEMBAR (FP)
27061
27062P2190: !_BST [2] (maybe <- 0x4080003e) (FP)
27063wr %g0, 0xf0, %asi
27064! preparing store val #0, next val will be in f32
27065fmovs %f16, %f20
27066fadds %f16, %f17, %f16
27067! preparing store val #1, next val will be in f33
27068fmovs %f16, %f21
27069fadds %f16, %f17, %f16
27070! preparing store val #2, next val will be in f35
27071fmovd %f20, %f32
27072fmovs %f16, %f21
27073fadds %f16, %f17, %f16
27074fmovd %f20, %f34
27075membar #Sync
27076stda %f32, [%i0 + 0 ] %asi
27077
27078P2191: !_MEMBAR (FP)
27079membar #StoreLoad
27080
27081P2192: !_LDD [19] (Int)
27082ldd [%i3 + 0], %l6
27083! move %l6(lower) -> %o0(lower)
27084or %l6, %o0, %o0
27085! move %l7(lower) -> %o1(upper)
27086sllx %l7, 32, %o1
27087
27088P2193: !_CASX [22] (maybe <- 0x1000051) (Int)
27089ldx [%i2], %o5
27090! move %o5(upper) -> %o1(lower)
27091srlx %o5, 32, %l3
27092or %l3, %o1, %o1
27093! move %o5(lower) -> %o2(upper)
27094sllx %o5, 32, %o2
27095mov %o5, %l3
27096sllx %l4, 32, %o5
27097add %l4, 1, %l4
27098or %l4, %o5, %o5
27099casx [%i2], %l3, %o5
27100! move %o5(upper) -> %o2(lower)
27101srlx %o5, 32, %l3
27102or %l3, %o2, %o2
27103! move %o5(lower) -> %o3(upper)
27104sllx %o5, 32, %o3
27105add %l4, 1, %l4
27106
27107P2194: !_MEMBAR (FP)
27108
27109P2195: !_BSTC [12] (maybe <- 0x40800041) (FP)
27110wr %g0, 0xe0, %asi
27111sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
27112sub %i0, %i3, %i3
27113! preparing store val #0, next val will be in f32
27114fmovs %f16, %f20
27115fadds %f16, %f17, %f16
27116! preparing store val #1, next val will be in f33
27117fmovs %f16, %f21
27118fadds %f16, %f17, %f16
27119! preparing store val #2, next val will be in f35
27120fmovd %f20, %f32
27121fmovs %f16, %f21
27122fadds %f16, %f17, %f16
27123fmovd %f20, %f34
27124membar #Sync
27125stda %f32, [%i3 + 0 ] %asi
27126
27127P2196: !_MEMBAR (FP)
27128membar #StoreLoad
27129
27130P2197: !_ST [16] (maybe <- 0x1000053) (Int) (LE)
27131wr %g0, 0x88, %asi
27132sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
27133sub %i0, %i2, %i2
27134! Change single-word-level endianess (big endian <-> little endian)
27135sethi %hi(0xff00ff00), %l6
27136or %l6, %lo(0xff00ff00), %l6
27137and %l4, %l6, %l7
27138srl %l7, 8, %l7
27139sll %l4, 8, %l3
27140and %l3, %l6, %l3
27141or %l3, %l7, %l3
27142srl %l3, 16, %l7
27143sll %l3, 16, %l3
27144srl %l3, 0, %l3
27145or %l3, %l7, %l3
27146stwa %l3, [%i2 + 4] %asi
27147add %l4, 1, %l4
27148
27149P2198: !_LDD [15] (Int)
27150ldd [%i2 + 0], %l6
27151! move %l6(lower) -> %o3(lower)
27152or %l6, %o3, %o3
27153! move %l7(lower) -> %o4(upper)
27154sllx %l7, 32, %o4
27155
27156P2199: !_CAS [18] (maybe <- 0x1000054) (Int)
27157sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
27158sub %i0, %i3, %i3
27159lduw [%i3], %o5
27160mov %o5, %l3
27161! move %l3(lower) -> %o4(lower)
27162or %l3, %o4, %o4
27163!---- flushing int results buffer----
27164mov %o0, %l5
27165mov %o1, %l5
27166mov %o2, %l5
27167mov %o3, %l5
27168mov %o4, %l5
27169mov %l4, %o0
27170cas [%i3], %l3, %o0
27171! move %o0(lower) -> %o0(upper)
27172sllx %o0, 32, %o0
27173add %l4, 1, %l4
27174
27175P2200: !_LD [1] (FP)
27176ld [%i0 + 4], %f7
27177! 1 addresses covered
27178
27179P2201: !_DWST_BINIT [6] (maybe <- 0x1000055) (Int)
27180wr %g0, 0xe2, %asi
27181sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
27182sub %i0, %i2, %i2
27183sllx %l4, 32, %l3
27184add %l4, 1, %l4
27185or %l3, %l4, %l3
27186stxa %l3, [%i2 + 0] %asi
27187add %l4, 1, %l4
27188
27189P2202: !_MEMBAR (Int)
27190membar #StoreLoad
27191
27192P2203: !_DWST_BINIT [14] (maybe <- 0x1000057) (Int)
27193wr %g0, 0xe2, %asi
27194sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
27195sub %i0, %i3, %i3
27196mov %l4, %o5
27197stxa %o5, [%i3 + 8] %asi
27198add %l4, 1, %l4
27199
27200P2204: !_MEMBAR (Int)
27201membar #StoreLoad
27202
27203P2205: !_DWST_BINIT [23] (maybe <- 0x1000058) (Int)
27204wr %g0, 0xe2, %asi
27205sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
27206sub %i0, %i2, %i2
27207mov %l4, %l7
27208stxa %l7, [%i2 + 8] %asi
27209add %l4, 1, %l4
27210
27211P2206: !_MEMBAR (Int)
27212membar #StoreLoad
27213
27214P2207: !_REPLACEMENT [12] (Int)
27215sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
27216sub %i0, %i3, %i3
27217sethi %hi(0x20000), %l6
27218ld [%i3+0], %o5
27219st %o5, [%i3+0]
27220add %i3, %l6, %l7
27221ld [%l7+0], %o5
27222st %o5, [%l7+0]
27223add %l7, %l6, %l7
27224ld [%l7+0], %o5
27225st %o5, [%l7+0]
27226add %l7, %l6, %l7
27227ld [%l7+0], %o5
27228st %o5, [%l7+0]
27229add %l7, %l6, %l7
27230ld [%l7+0], %o5
27231st %o5, [%l7+0]
27232add %l7, %l6, %l7
27233ld [%l7+0], %o5
27234st %o5, [%l7+0]
27235add %l7, %l6, %l7
27236ld [%l7+0], %o5
27237st %o5, [%l7+0]
27238add %l7, %l6, %l7
27239ld [%l7+0], %o5
27240st %o5, [%l7+0]
27241
27242P2208: !_DWST [13] (maybe <- 0x1000059) (Int)
27243sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
27244sub %i0, %i2, %i2
27245sllx %l4, 32, %l3
27246add %l4, 1, %l4
27247or %l3, %l4, %l3
27248stx %l3, [%i2 + 0]
27249add %l4, 1, %l4
27250
27251P2209: !_LDD [11] (Int)
27252sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
27253add %i0, %i3, %i3
27254ldd [%i3 + 8], %l6
27255! move %l7(lower) -> %o0(lower)
27256or %l7, %o0, %o0
27257
27258P2210: !_MEMBAR (FP)
27259membar #StoreLoad
27260
27261P2211: !_BLD [2] (FP)
27262wr %g0, 0xf0, %asi
27263ldda [%i0 + 0] %asi, %f32
27264membar #Sync
27265! 3 addresses covered
27266fmovd %f32, %f8
27267fmovd %f34, %f18
27268fmovs %f19, %f10
27269
27270P2212: !_MEMBAR (FP)
27271
27272P2213: !_BST [22] (maybe <- 0x40800044) (FP)
27273wr %g0, 0xf0, %asi
27274sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
27275sub %i0, %i2, %i2
27276! preparing store val #0, next val will be in f32
27277fmovs %f16, %f20
27278fadds %f16, %f17, %f16
27279! preparing store val #1, next val will be in f33
27280fmovs %f16, %f21
27281fadds %f16, %f17, %f16
27282! preparing store val #2, next val will be in f35
27283fmovd %f20, %f32
27284fmovs %f16, %f21
27285fadds %f16, %f17, %f16
27286fmovd %f20, %f34
27287membar #Sync
27288stda %f32, [%i2 + 0 ] %asi
27289
27290P2214: !_MEMBAR (FP)
27291membar #StoreLoad
27292
27293P2215: !_CAS [3] (maybe <- 0x100005b) (Int)
27294lduw [%i1], %o1
27295mov %o1, %o5
27296! move %o5(lower) -> %o1(upper)
27297sllx %o5, 32, %o1
27298mov %l4, %l7
27299cas [%i1], %o5, %l7
27300! move %l7(lower) -> %o1(lower)
27301srl %l7, 0, %o5
27302or %o5, %o1, %o1
27303add %l4, 1, %l4
27304
27305P2216: !_DWST_BINIT [6] (maybe <- 0x100005c) (Int)
27306wr %g0, 0xe2, %asi
27307sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
27308sub %i0, %i3, %i3
27309sllx %l4, 32, %o5
27310add %l4, 1, %l4
27311or %o5, %l4, %o5
27312stxa %o5, [%i3 + 0] %asi
27313add %l4, 1, %l4
27314
27315P2217: !_MEMBAR (Int)
27316membar #StoreLoad
27317
27318P2218: !_ST_BINIT [23] (maybe <- 0x100005e) (Int)
27319wr %g0, 0xe2, %asi
27320stwa %l4, [%i2 + 12] %asi
27321add %l4, 1, %l4
27322
27323P2219: !_MEMBAR (Int)
27324membar #StoreLoad
27325
27326P2220: !_BLD [9] (FP)
27327wr %g0, 0xf0, %asi
27328sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
27329add %i0, %i2, %i2
27330ldda [%i2 + 0] %asi, %f32
27331membar #Sync
27332! 3 addresses covered
27333fmovd %f32, %f18
27334fmovs %f18, %f11
27335fmovs %f19, %f12
27336fmovd %f34, %f18
27337fmovs %f19, %f13
27338
27339P2221: !_MEMBAR (FP)
27340
27341P2222: !_CAS [8] (maybe <- 0x100005f) (Int)
27342add %i3, 12, %l7
27343lduw [%l7], %o2
27344mov %o2, %l6
27345! move %l6(lower) -> %o2(upper)
27346sllx %l6, 32, %o2
27347mov %l4, %l3
27348cas [%l7], %l6, %l3
27349! move %l3(lower) -> %o2(lower)
27350srl %l3, 0, %l6
27351or %l6, %o2, %o2
27352add %l4, 1, %l4
27353
27354P2223: !_MEMBAR (FP)
27355
27356P2224: !_BST [16] (maybe <- 0x40800047) (FP)
27357wr %g0, 0xf0, %asi
27358sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
27359sub %i0, %i3, %i3
27360! preparing store val #0, next val will be in f32
27361fmovs %f16, %f20
27362fadds %f16, %f17, %f16
27363! preparing store val #1, next val will be in f33
27364fmovs %f16, %f21
27365fadds %f16, %f17, %f16
27366! preparing store val #2, next val will be in f35
27367fmovd %f20, %f32
27368fmovs %f16, %f21
27369fadds %f16, %f17, %f16
27370fmovd %f20, %f34
27371membar #Sync
27372stda %f32, [%i3 + 0 ] %asi
27373
27374P2225: !_MEMBAR (FP)
27375
27376P2226: !_BST [16] (maybe <- 0x4080004a) (FP)
27377wr %g0, 0xf0, %asi
27378! preparing store val #0, next val will be in f32
27379fmovs %f16, %f20
27380fadds %f16, %f17, %f16
27381! preparing store val #1, next val will be in f33
27382fmovs %f16, %f21
27383fadds %f16, %f17, %f16
27384! preparing store val #2, next val will be in f35
27385fmovd %f20, %f32
27386fmovs %f16, %f21
27387fadds %f16, %f17, %f16
27388fmovd %f20, %f34
27389membar #Sync
27390stda %f32, [%i3 + 0 ] %asi
27391
27392P2227: !_MEMBAR (FP)
27393
27394P2228: !_BST [0] (maybe <- 0x4080004d) (FP)
27395wr %g0, 0xf0, %asi
27396! preparing store val #0, next val will be in f32
27397fmovs %f16, %f20
27398fadds %f16, %f17, %f16
27399! preparing store val #1, next val will be in f33
27400fmovs %f16, %f21
27401fadds %f16, %f17, %f16
27402! preparing store val #2, next val will be in f35
27403fmovd %f20, %f32
27404fmovs %f16, %f21
27405fadds %f16, %f17, %f16
27406fmovd %f20, %f34
27407membar #Sync
27408stda %f32, [%i0 + 0 ] %asi
27409
27410P2229: !_MEMBAR (FP)
27411membar #StoreLoad
27412
27413P2230: !_ST_BINIT [1] (maybe <- 0x1000060) (Int)
27414wr %g0, 0xe2, %asi
27415stwa %l4, [%i0 + 4] %asi
27416add %l4, 1, %l4
27417
27418P2231: !_MEMBAR (Int)
27419membar #StoreLoad
27420
27421P2232: !_DWLD [6] (Int) (LE)
27422wr %g0, 0x88, %asi
27423sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
27424sub %i0, %i2, %i2
27425ldxa [%i2 + 0] %asi, %l7
27426! move %l7(lower) -> %o3(upper)
27427sllx %l7, 32, %o3
27428! move %l7(upper) -> %o3(lower)
27429srlx %l7, 32, %l6
27430or %l6, %o3, %o3
27431
27432P2233: !_ST_BINIT [5] (maybe <- 0x1000061) (Int)
27433wr %g0, 0xe2, %asi
27434stwa %l4, [%i1 + 12] %asi
27435add %l4, 1, %l4
27436
27437P2234: !_MEMBAR (Int)
27438membar #StoreLoad
27439
27440P2235: !_ST [16] (maybe <- 0x1000062) (Int)
27441stw %l4, [%i3 + 4 ]
27442add %l4, 1, %l4
27443
27444P2236: !_DWLD [2] (FP)
27445ldd [%i0 + 8], %f14
27446! 1 addresses covered
27447fmovs %f15, %f14
27448
27449P2237: !_ST_BINIT [15] (maybe <- 0x1000063) (Int) (Branch target of P2919)
27450wr %g0, 0xe2, %asi
27451stwa %l4, [%i3 + 0] %asi
27452add %l4, 1, %l4
27453ba P2238
27454nop
27455
27456TARGET2919:
27457ba RET2919
27458nop
27459
27460
27461P2238: !_MEMBAR (Int)
27462membar #StoreLoad
27463
27464P2239: !_DWST [15] (maybe <- 0x1000064) (Int)
27465sllx %l4, 32, %l3
27466add %l4, 1, %l4
27467or %l3, %l4, %l3
27468stx %l3, [%i3 + 0]
27469add %l4, 1, %l4
27470
27471P2240: !_ST_BINIT [21] (maybe <- 0x1000066) (Int)
27472wr %g0, 0xe2, %asi
27473sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
27474sub %i0, %i3, %i3
27475stwa %l4, [%i3 + 0] %asi
27476add %l4, 1, %l4
27477
27478P2241: !_MEMBAR (Int)
27479membar #StoreLoad
27480
27481P2242: !_CASX [13] (maybe <- 0x1000067) (Int)
27482sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
27483sub %i0, %i2, %i2
27484ldx [%i2], %o4
27485! move %o4(upper) -> %o4(upper)
27486! move %o4(lower) -> %o4(lower)
27487!---- flushing int results buffer----
27488mov %o0, %l5
27489mov %o1, %l5
27490mov %o2, %l5
27491mov %o3, %l5
27492mov %o4, %l5
27493mov %o4, %l7
27494sllx %l4, 32, %o0
27495add %l4, 1, %l4
27496or %l4, %o0, %o0
27497casx [%i2], %l7, %o0
27498! move %o0(upper) -> %o0(upper)
27499! move %o0(lower) -> %o0(lower)
27500add %l4, 1, %l4
27501
27502P2243: !_MEMBAR (FP)
27503membar #StoreLoad
27504
27505P2244: !_BLD [6] (FP)
27506wr %g0, 0xf0, %asi
27507sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
27508sub %i0, %i3, %i3
27509ldda [%i3 + 0] %asi, %f32
27510membar #Sync
27511! 3 addresses covered
27512fmovd %f32, %f18
27513fmovs %f18, %f15
27514!---- flushing fp results buffer to %f30 ----
27515fmovd %f0, %f30
27516fmovd %f2, %f30
27517fmovd %f4, %f30
27518fmovd %f6, %f30
27519fmovd %f8, %f30
27520fmovd %f10, %f30
27521fmovd %f12, %f30
27522fmovd %f14, %f30
27523!--
27524fmovs %f19, %f0
27525fmovd %f34, %f18
27526fmovs %f19, %f1
27527
27528P2245: !_MEMBAR (FP)
27529
27530P2246: !_BST [9] (maybe <- 0x40800050) (FP)
27531wr %g0, 0xf0, %asi
27532sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
27533add %i0, %i2, %i2
27534! preparing store val #0, next val will be in f32
27535fmovs %f16, %f20
27536fadds %f16, %f17, %f16
27537! preparing store val #1, next val will be in f33
27538fmovs %f16, %f21
27539fadds %f16, %f17, %f16
27540! preparing store val #2, next val will be in f35
27541fmovd %f20, %f32
27542fmovs %f16, %f21
27543fadds %f16, %f17, %f16
27544fmovd %f20, %f34
27545membar #Sync
27546stda %f32, [%i2 + 0 ] %asi
27547
27548P2247: !_MEMBAR (FP)
27549membar #StoreLoad
27550
27551P2248: !_SWAP [23] (maybe <- 0x1000069) (Int)
27552sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
27553sub %i0, %i3, %i3
27554mov %l4, %o1
27555swap [%i3 + 12], %o1
27556! move %o1(lower) -> %o1(upper)
27557sllx %o1, 32, %o1
27558add %l4, 1, %l4
27559
27560P2249: !_PREFETCH [18] (Int) (LE)
27561wr %g0, 0x88, %asi
27562sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
27563sub %i0, %i2, %i2
27564prefetcha [%i2 + 0] %asi, 2
27565
27566P2250: !_DWST_BINIT [15] (maybe <- 0x100006a) (Int) (LE)
27567wr %g0, 0xea, %asi
27568sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
27569sub %i0, %i3, %i3
27570sllx %l4, 32, %l3
27571add %l4, 1, %l4
27572or %l3, %l4, %l6
27573! Change double-word-level endianess (big endian <-> little endian)
27574sethi %hi(0xff00ff00), %l7
27575or %l7, %lo(0xff00ff00), %l7
27576sllx %l7, 32, %l3
27577or %l7, %l3, %l7
27578and %l6, %l7, %l3
27579srlx %l3, 8, %l3
27580sllx %l6, 8, %l6
27581and %l6, %l7, %l6
27582or %l6, %l3, %l6
27583sethi %hi(0xffff0000), %l7
27584srlx %l6, 16, %l3
27585andn %l3, %l7, %l3
27586andn %l6, %l7, %l6
27587sllx %l6, 16, %l6
27588or %l6, %l3, %l6
27589srlx %l6, 32, %l3
27590sllx %l6, 32, %l6
27591or %l6, %l3, %l3
27592stxa %l3, [%i3 + 0 ] %asi
27593add %l4, 1, %l4
27594
27595P2251: !_MEMBAR (Int) (LE)
27596membar #StoreLoad
27597
27598P2252: !_SWAP [4] (maybe <- 0x100006c) (Int)
27599mov %l4, %l6
27600swap [%i1 + 4], %l6
27601! move %l6(lower) -> %o1(lower)
27602srl %l6, 0, %o5
27603or %o5, %o1, %o1
27604add %l4, 1, %l4
27605
27606P2253: !_DWST [8] (maybe <- 0x100006d) (Int)
27607sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
27608sub %i0, %i2, %i2
27609mov %l4, %l7
27610stx %l7, [%i2 + 8]
27611add %l4, 1, %l4
27612
27613P2254: !_PREFETCH [1] (Int)
27614prefetch [%i0 + 4], 3
27615
27616P2255: !_LD [20] (Int)
27617sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
27618sub %i0, %i3, %i3
27619lduw [%i3 + 12], %o2
27620! move %o2(lower) -> %o2(upper)
27621sllx %o2, 32, %o2
27622
27623P2256: !_LD [15] (Int)
27624sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
27625sub %i0, %i2, %i2
27626lduw [%i2 + 0], %l3
27627! move %l3(lower) -> %o2(lower)
27628or %l3, %o2, %o2
27629
27630P2257: !_MEMBAR (FP)
27631membar #StoreLoad
27632
27633P2258: !_BLD [11] (FP)
27634wr %g0, 0xf0, %asi
27635sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
27636add %i0, %i3, %i3
27637ldda [%i3 + 0] %asi, %f32
27638membar #Sync
27639! 3 addresses covered
27640fmovd %f32, %f2
27641fmovd %f34, %f18
27642fmovs %f19, %f4
27643
27644P2259: !_MEMBAR (FP)
27645
27646P2260: !_SWAP [19] (maybe <- 0x100006e) (Int)
27647sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
27648sub %i0, %i2, %i2
27649mov %l4, %o3
27650swap [%i2 + 4], %o3
27651! move %o3(lower) -> %o3(upper)
27652sllx %o3, 32, %o3
27653add %l4, 1, %l4
27654
27655P2261: !_CASX [21] (maybe <- 0x100006f) (Int)
27656sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
27657sub %i0, %i3, %i3
27658ldx [%i3], %l3
27659! move %l3(upper) -> %o3(lower)
27660srlx %l3, 32, %l6
27661or %l6, %o3, %o3
27662! move %l3(lower) -> %o4(upper)
27663sllx %l3, 32, %o4
27664mov %l3, %l6
27665sllx %l4, 32, %l3
27666add %l4, 1, %l4
27667or %l4, %l3, %l3
27668casx [%i3], %l6, %l3
27669! move %l3(upper) -> %o4(lower)
27670srlx %l3, 32, %l6
27671or %l6, %o4, %o4
27672!---- flushing int results buffer----
27673mov %o0, %l5
27674mov %o1, %l5
27675mov %o2, %l5
27676mov %o3, %l5
27677mov %o4, %l5
27678! move %l3(lower) -> %o0(upper)
27679sllx %l3, 32, %o0
27680add %l4, 1, %l4
27681
27682P2262: !_LDD [12] (Int)
27683sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
27684sub %i0, %i2, %i2
27685ldd [%i2 + 0], %l6
27686! move %l6(lower) -> %o0(lower)
27687or %l6, %o0, %o0
27688! move %l7(lower) -> %o1(upper)
27689sllx %l7, 32, %o1
27690
27691P2263: !_ST [21] (maybe <- 0x1000071) (Int)
27692stw %l4, [%i3 + 0 ]
27693add %l4, 1, %l4
27694
27695P2264: !_PREFETCH [12] (Int)
27696prefetch [%i2 + 0], 21
27697
27698P2265: !_MEMBAR (FP)
27699
27700P2266: !_BSTC [19] (maybe <- 0x40800053) (FP)
27701wr %g0, 0xe0, %asi
27702sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
27703sub %i0, %i3, %i3
27704! preparing store val #0, next val will be in f32
27705fmovs %f16, %f20
27706fadds %f16, %f17, %f16
27707! preparing store val #1, next val will be in f33
27708fmovs %f16, %f21
27709fadds %f16, %f17, %f16
27710! preparing store val #2, next val will be in f35
27711fmovd %f20, %f32
27712fmovs %f16, %f21
27713fadds %f16, %f17, %f16
27714fmovd %f20, %f34
27715membar #Sync
27716stda %f32, [%i3 + 0 ] %asi
27717
27718P2267: !_MEMBAR (FP)
27719membar #StoreLoad
27720
27721P2268: !_LDD [4] (Int) (CBR)
27722ldd [%i1 + 0], %l6
27723! move %l6(lower) -> %o1(lower)
27724or %l6, %o1, %o1
27725! move %l7(lower) -> %o2(upper)
27726sllx %l7, 32, %o2
27727
27728! cbranch
27729andcc %l0, 1, %g0
27730be,pt %xcc, TARGET2268
27731nop
27732RET2268:
27733
27734! lfsr step begin
27735srlx %l0, 1, %l3
27736xnor %l3, %l0, %l3
27737sllx %l3, 63, %l3
27738or %l3, %l0, %l0
27739srlx %l0, 1, %l0
27740
27741
27742P2269: !_MEMBAR (FP)
27743
27744P2270: !_BSTC [8] (maybe <- 0x40800056) (FP)
27745wr %g0, 0xe0, %asi
27746sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
27747sub %i0, %i2, %i2
27748! preparing store val #0, next val will be in f32
27749fmovs %f16, %f20
27750fadds %f16, %f17, %f16
27751! preparing store val #1, next val will be in f33
27752fmovs %f16, %f21
27753fadds %f16, %f17, %f16
27754! preparing store val #2, next val will be in f35
27755fmovd %f20, %f32
27756fmovs %f16, %f21
27757fadds %f16, %f17, %f16
27758fmovd %f20, %f34
27759membar #Sync
27760stda %f32, [%i2 + 0 ] %asi
27761
27762P2271: !_MEMBAR (FP)
27763membar #StoreLoad
27764
27765P2272: !_PREFETCH [17] (Int)
27766sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
27767sub %i0, %i3, %i3
27768prefetch [%i3 + 12], 0
27769
27770P2273: !_MEMBAR (FP)
27771membar #StoreLoad
27772
27773P2274: !_BLD [3] (FP)
27774wr %g0, 0xf0, %asi
27775ldda [%i1 + 0] %asi, %f32
27776membar #Sync
27777! 3 addresses covered
27778fmovd %f32, %f18
27779fmovs %f18, %f5
27780fmovs %f19, %f6
27781fmovd %f34, %f18
27782fmovs %f19, %f7
27783
27784P2275: !_MEMBAR (FP) (Branch target of P2565)
27785ba P2276
27786nop
27787
27788TARGET2565:
27789ba RET2565
27790nop
27791
27792
27793P2276: !_DWLD [19] (Int)
27794sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
27795sub %i0, %i2, %i2
27796ldx [%i2 + 0], %l6
27797! move %l6(upper) -> %o2(lower)
27798srlx %l6, 32, %l3
27799or %l3, %o2, %o2
27800! move %l6(lower) -> %o3(upper)
27801sllx %l6, 32, %o3
27802
27803P2277: !_CASX [20] (maybe <- 0x1000072) (Int)
27804add %i2, 8, %o5
27805ldx [%o5], %l6
27806! move %l6(upper) -> %o3(lower)
27807srlx %l6, 32, %l7
27808or %l7, %o3, %o3
27809! move %l6(lower) -> %o4(upper)
27810sllx %l6, 32, %o4
27811mov %l6, %l7
27812mov %l4, %l6
27813casx [%o5], %l7, %l6
27814! move %l6(upper) -> %o4(lower)
27815srlx %l6, 32, %l7
27816or %l7, %o4, %o4
27817!---- flushing int results buffer----
27818mov %o0, %l5
27819mov %o1, %l5
27820mov %o2, %l5
27821mov %o3, %l5
27822mov %o4, %l5
27823! move %l6(lower) -> %o0(upper)
27824sllx %l6, 32, %o0
27825add %l4, 1, %l4
27826
27827P2278: !_MEMBAR (FP)
27828
27829P2279: !_BSTC [16] (maybe <- 0x40800059) (FP)
27830wr %g0, 0xe0, %asi
27831! preparing store val #0, next val will be in f32
27832fmovs %f16, %f20
27833fadds %f16, %f17, %f16
27834! preparing store val #1, next val will be in f33
27835fmovs %f16, %f21
27836fadds %f16, %f17, %f16
27837! preparing store val #2, next val will be in f35
27838fmovd %f20, %f32
27839fmovs %f16, %f21
27840fadds %f16, %f17, %f16
27841fmovd %f20, %f34
27842membar #Sync
27843stda %f32, [%i3 + 0 ] %asi
27844
27845P2280: !_MEMBAR (FP)
27846membar #StoreLoad
27847
27848P2281: !_PREFETCH [3] (Int)
27849prefetch [%i1 + 0], 23
27850
27851P2282: !_CASX [11] (maybe <- 0x1000073) (Int)
27852sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
27853add %i0, %i3, %i3
27854add %i3, 8, %l7
27855ldx [%l7], %l3
27856! move %l3(upper) -> %o0(lower)
27857srlx %l3, 32, %l6
27858or %l6, %o0, %o0
27859! move %l3(lower) -> %o1(upper)
27860sllx %l3, 32, %o1
27861mov %l3, %l6
27862mov %l4, %l3
27863casx [%l7], %l6, %l3
27864! move %l3(upper) -> %o1(lower)
27865srlx %l3, 32, %l6
27866or %l6, %o1, %o1
27867! move %l3(lower) -> %o2(upper)
27868sllx %l3, 32, %o2
27869add %l4, 1, %l4
27870
27871P2283: !_ST [3] (maybe <- 0x1000074) (Int)
27872stw %l4, [%i1 + 0 ]
27873add %l4, 1, %l4
27874
27875P2284: !_DWLD [20] (Int)
27876ldx [%i2 + 8], %l6
27877! move %l6(lower) -> %o2(lower)
27878srl %l6, 0, %l3
27879or %l3, %o2, %o2
27880
27881P2285: !_DWLD [15] (Int)
27882sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
27883sub %i0, %i2, %i2
27884ldx [%i2 + 0], %o3
27885! move %o3(upper) -> %o3(upper)
27886! move %o3(lower) -> %o3(lower)
27887
27888P2286: !_MEMBAR (FP)
27889
27890P2287: !_BSTC [5] (maybe <- 0x4080005c) (FP)
27891wr %g0, 0xe0, %asi
27892! preparing store val #0, next val will be in f32
27893fmovs %f16, %f20
27894fadds %f16, %f17, %f16
27895! preparing store val #1, next val will be in f33
27896fmovs %f16, %f21
27897fadds %f16, %f17, %f16
27898! preparing store val #2, next val will be in f35
27899fmovd %f20, %f32
27900fmovs %f16, %f21
27901fadds %f16, %f17, %f16
27902fmovd %f20, %f34
27903membar #Sync
27904stda %f32, [%i1 + 0 ] %asi
27905
27906P2288: !_MEMBAR (FP)
27907membar #StoreLoad
27908
27909P2289: !_LD [1] (FP)
27910ld [%i0 + 4], %f8
27911! 1 addresses covered
27912
27913P2290: !_CAS [1] (maybe <- 0x1000075) (Int)
27914add %i0, 4, %l3
27915lduw [%l3], %o4
27916mov %o4, %o5
27917! move %o5(lower) -> %o4(upper)
27918sllx %o5, 32, %o4
27919mov %l4, %l7
27920cas [%l3], %o5, %l7
27921! move %l7(lower) -> %o4(lower)
27922srl %l7, 0, %o5
27923or %o5, %o4, %o4
27924!---- flushing int results buffer----
27925mov %o0, %l5
27926mov %o1, %l5
27927mov %o2, %l5
27928mov %o3, %l5
27929mov %o4, %l5
27930add %l4, 1, %l4
27931
27932P2291: !_MEMBAR (FP)
27933
27934P2292: !_BST [4] (maybe <- 0x4080005f) (FP)
27935wr %g0, 0xf0, %asi
27936! preparing store val #0, next val will be in f32
27937fmovs %f16, %f20
27938fadds %f16, %f17, %f16
27939! preparing store val #1, next val will be in f33
27940fmovs %f16, %f21
27941fadds %f16, %f17, %f16
27942! preparing store val #2, next val will be in f35
27943fmovd %f20, %f32
27944fmovs %f16, %f21
27945fadds %f16, %f17, %f16
27946fmovd %f20, %f34
27947membar #Sync
27948stda %f32, [%i1 + 0 ] %asi
27949
27950P2293: !_MEMBAR (FP)
27951
27952P2294: !_BSTC [20] (maybe <- 0x40800062) (FP)
27953wr %g0, 0xe0, %asi
27954sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
27955sub %i0, %i3, %i3
27956! preparing store val #0, next val will be in f32
27957fmovs %f16, %f20
27958fadds %f16, %f17, %f16
27959! preparing store val #1, next val will be in f33
27960fmovs %f16, %f21
27961fadds %f16, %f17, %f16
27962! preparing store val #2, next val will be in f35
27963fmovd %f20, %f32
27964fmovs %f16, %f21
27965fadds %f16, %f17, %f16
27966fmovd %f20, %f34
27967membar #Sync
27968stda %f32, [%i3 + 0 ] %asi
27969
27970P2295: !_MEMBAR (FP)
27971membar #StoreLoad
27972
27973P2296: !_BLD [18] (FP)
27974wr %g0, 0xf0, %asi
27975ldda [%i3 + 0] %asi, %f32
27976membar #Sync
27977! 3 addresses covered
27978fmovd %f32, %f18
27979fmovs %f18, %f9
27980fmovs %f19, %f10
27981fmovd %f34, %f18
27982fmovs %f19, %f11
27983
27984P2297: !_MEMBAR (FP)
27985
27986P2298: !_PREFETCH [3] (Int)
27987prefetch [%i1 + 0], 28
27988
27989P2299: !_CAS [8] (maybe <- 0x1000076) (Int)
27990sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
27991sub %i0, %i2, %i2
27992add %i2, 12, %l7
27993lduw [%l7], %o0
27994mov %o0, %l6
27995! move %l6(lower) -> %o0(upper)
27996sllx %l6, 32, %o0
27997mov %l4, %l3
27998cas [%l7], %l6, %l3
27999! move %l3(lower) -> %o0(lower)
28000srl %l3, 0, %l6
28001or %l6, %o0, %o0
28002add %l4, 1, %l4
28003
28004P2300: !_MEMBAR (FP)
28005
28006P2301: !_BST [13] (maybe <- 0x40800065) (FP)
28007wr %g0, 0xf0, %asi
28008sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
28009sub %i0, %i3, %i3
28010! preparing store val #0, next val will be in f32
28011fmovs %f16, %f20
28012fadds %f16, %f17, %f16
28013! preparing store val #1, next val will be in f33
28014fmovs %f16, %f21
28015fadds %f16, %f17, %f16
28016! preparing store val #2, next val will be in f35
28017fmovd %f20, %f32
28018fmovs %f16, %f21
28019fadds %f16, %f17, %f16
28020fmovd %f20, %f34
28021membar #Sync
28022stda %f32, [%i3 + 0 ] %asi
28023
28024P2302: !_MEMBAR (FP)
28025membar #StoreLoad
28026
28027P2303: !_PREFETCH [16] (Int)
28028sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
28029sub %i0, %i2, %i2
28030prefetch [%i2 + 4], 23
28031
28032P2304: !_MEMBAR (FP) (Branch target of P2350)
28033membar #StoreLoad
28034ba P2305
28035nop
28036
28037TARGET2350:
28038ba RET2350
28039nop
28040
28041
28042P2305: !_BLD [10] (FP)
28043wr %g0, 0xf0, %asi
28044sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
28045add %i0, %i3, %i3
28046ldda [%i3 + 0] %asi, %f32
28047membar #Sync
28048! 3 addresses covered
28049fmovd %f32, %f12
28050fmovd %f34, %f18
28051fmovs %f19, %f14
28052
28053P2306: !_MEMBAR (FP)
28054
28055P2307: !_BST [17] (maybe <- 0x40800068) (FP)
28056wr %g0, 0xf0, %asi
28057! preparing store val #0, next val will be in f32
28058fmovs %f16, %f20
28059fadds %f16, %f17, %f16
28060! preparing store val #1, next val will be in f33
28061fmovs %f16, %f21
28062fadds %f16, %f17, %f16
28063! preparing store val #2, next val will be in f35
28064fmovd %f20, %f32
28065fmovs %f16, %f21
28066fadds %f16, %f17, %f16
28067fmovd %f20, %f34
28068membar #Sync
28069stda %f32, [%i2 + 0 ] %asi
28070
28071P2308: !_MEMBAR (FP)
28072membar #StoreLoad
28073
28074P2309: !_BLD [8] (FP)
28075wr %g0, 0xf0, %asi
28076sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
28077sub %i0, %i2, %i2
28078ldda [%i2 + 0] %asi, %f32
28079membar #Sync
28080! 3 addresses covered
28081fmovd %f32, %f18
28082fmovs %f18, %f15
28083!---- flushing fp results buffer to %f30 ----
28084fmovd %f0, %f30
28085fmovd %f2, %f30
28086fmovd %f4, %f30
28087fmovd %f6, %f30
28088fmovd %f8, %f30
28089fmovd %f10, %f30
28090fmovd %f12, %f30
28091fmovd %f14, %f30
28092!--
28093fmovs %f19, %f0
28094fmovd %f34, %f18
28095fmovs %f19, %f1
28096
28097P2310: !_MEMBAR (FP)
28098
28099P2311: !_LD [15] (Int)
28100sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
28101sub %i0, %i3, %i3
28102lduw [%i3 + 0], %o1
28103! move %o1(lower) -> %o1(upper)
28104sllx %o1, 32, %o1
28105
28106P2312: !_DWST [14] (maybe <- 0x1000077) (Int)
28107sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
28108sub %i0, %i2, %i2
28109mov %l4, %l6
28110stx %l6, [%i2 + 8]
28111add %l4, 1, %l4
28112
28113P2313: !_CASX [22] (maybe <- 0x1000078) (Int)
28114sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
28115sub %i0, %i3, %i3
28116ldx [%i3], %o5
28117! move %o5(upper) -> %o1(lower)
28118srlx %o5, 32, %l3
28119or %l3, %o1, %o1
28120! move %o5(lower) -> %o2(upper)
28121sllx %o5, 32, %o2
28122mov %o5, %l3
28123sllx %l4, 32, %o5
28124add %l4, 1, %l4
28125or %l4, %o5, %o5
28126casx [%i3], %l3, %o5
28127! move %o5(upper) -> %o2(lower)
28128srlx %o5, 32, %l3
28129or %l3, %o2, %o2
28130! move %o5(lower) -> %o3(upper)
28131sllx %o5, 32, %o3
28132add %l4, 1, %l4
28133
28134P2314: !_DWST_BINIT [15] (maybe <- 0x100007a) (Int) (CBR)
28135wr %g0, 0xe2, %asi
28136sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
28137sub %i0, %i2, %i2
28138sllx %l4, 32, %l3
28139add %l4, 1, %l4
28140or %l3, %l4, %l3
28141stxa %l3, [%i2 + 0] %asi
28142add %l4, 1, %l4
28143
28144! cbranch
28145andcc %l0, 1, %g0
28146be,pn %xcc, TARGET2314
28147nop
28148RET2314:
28149
28150! lfsr step begin
28151srlx %l0, 1, %o5
28152xnor %o5, %l0, %o5
28153sllx %o5, 63, %o5
28154or %o5, %l0, %l0
28155srlx %l0, 1, %l0
28156
28157
28158P2315: !_MEMBAR (Int)
28159membar #StoreLoad
28160
28161P2316: !_DWST_BINIT [17] (maybe <- 0x100007c) (Int)
28162wr %g0, 0xe2, %asi
28163mov %l4, %l3
28164stxa %l3, [%i2 + 8] %asi
28165add %l4, 1, %l4
28166
28167P2317: !_MEMBAR (Int) (Branch target of P2458)
28168membar #StoreLoad
28169ba P2318
28170nop
28171
28172TARGET2458:
28173ba RET2458
28174nop
28175
28176
28177P2318: !_ST [19] (maybe <- 0x4080006b) (FP)
28178sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
28179sub %i0, %i3, %i3
28180! preparing store val #0, next val will be in f20
28181fmovs %f16, %f20
28182fadds %f16, %f17, %f16
28183st %f20, [%i3 + 4 ]
28184
28185P2319: !_DWST [20] (maybe <- 0x100007d) (Int)
28186mov %l4, %l7
28187stx %l7, [%i3 + 8]
28188add %l4, 1, %l4
28189
28190P2320: !_DWST_BINIT [4] (maybe <- 0x100007e) (Int)
28191wr %g0, 0xe2, %asi
28192sllx %l4, 32, %l6
28193add %l4, 1, %l4
28194or %l6, %l4, %l6
28195stxa %l6, [%i1 + 0] %asi
28196add %l4, 1, %l4
28197
28198P2321: !_MEMBAR (Int)
28199membar #StoreLoad
28200
28201P2322: !_SWAP [11] (maybe <- 0x1000080) (Int)
28202sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
28203add %i0, %i2, %i2
28204mov %l4, %l7
28205swap [%i2 + 12], %l7
28206! move %l7(lower) -> %o3(lower)
28207srl %l7, 0, %l3
28208or %l3, %o3, %o3
28209add %l4, 1, %l4
28210
28211P2323: !_PREFETCH [23] (Int)
28212sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
28213sub %i0, %i3, %i3
28214prefetch [%i3 + 12], 2
28215
28216P2324: !_MEMBAR (FP) (CBR)
28217
28218! cbranch
28219andcc %l0, 1, %g0
28220be,pn %xcc, TARGET2324
28221nop
28222RET2324:
28223
28224! lfsr step begin
28225srlx %l0, 1, %l3
28226xnor %l3, %l0, %l3
28227sllx %l3, 63, %l3
28228or %l3, %l0, %l0
28229srlx %l0, 1, %l0
28230
28231
28232P2325: !_BSTC [10] (maybe <- 0x4080006c) (FP)
28233wr %g0, 0xe0, %asi
28234! preparing store val #0, next val will be in f32
28235fmovs %f16, %f20
28236fadds %f16, %f17, %f16
28237! preparing store val #1, next val will be in f33
28238fmovs %f16, %f21
28239fadds %f16, %f17, %f16
28240! preparing store val #2, next val will be in f35
28241fmovd %f20, %f32
28242fmovs %f16, %f21
28243fadds %f16, %f17, %f16
28244fmovd %f20, %f34
28245membar #Sync
28246stda %f32, [%i2 + 0 ] %asi
28247
28248P2326: !_MEMBAR (FP)
28249
28250P2327: !_BST [7] (maybe <- 0x4080006f) (FP)
28251wr %g0, 0xf0, %asi
28252sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
28253sub %i0, %i2, %i2
28254! preparing store val #0, next val will be in f32
28255fmovs %f16, %f20
28256fadds %f16, %f17, %f16
28257! preparing store val #1, next val will be in f33
28258fmovs %f16, %f21
28259fadds %f16, %f17, %f16
28260! preparing store val #2, next val will be in f35
28261fmovd %f20, %f32
28262fmovs %f16, %f21
28263fadds %f16, %f17, %f16
28264fmovd %f20, %f34
28265membar #Sync
28266stda %f32, [%i2 + 0 ] %asi
28267
28268P2328: !_MEMBAR (FP)
28269membar #StoreLoad
28270
28271P2329: !_LDD [13] (Int)
28272sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
28273sub %i0, %i3, %i3
28274ldd [%i3 + 0], %l6
28275! move %l6(lower) -> %o4(upper)
28276sllx %l6, 32, %o4
28277! move %l7(lower) -> %o4(lower)
28278or %l7, %o4, %o4
28279!---- flushing int results buffer----
28280mov %o0, %l5
28281mov %o1, %l5
28282mov %o2, %l5
28283mov %o3, %l5
28284mov %o4, %l5
28285
28286P2330: !_PREFETCH [22] (Int)
28287sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
28288sub %i0, %i2, %i2
28289prefetch [%i2 + 4], 31
28290
28291P2331: !_LDD [8] (Int)
28292sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
28293sub %i0, %i3, %i3
28294ldd [%i3 + 8], %l6
28295! move %l7(lower) -> %o0(upper)
28296sllx %l7, 32, %o0
28297
28298P2332: !_DWST [2] (maybe <- 0x1000081) (Int)
28299mov %l4, %l3
28300stx %l3, [%i0 + 8]
28301add %l4, 1, %l4
28302
28303P2333: !_MEMBAR (FP)
28304membar #StoreLoad
28305
28306P2334: !_BLD [17] (FP)
28307wr %g0, 0xf0, %asi
28308sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
28309sub %i0, %i2, %i2
28310ldda [%i2 + 0] %asi, %f32
28311membar #Sync
28312! 3 addresses covered
28313fmovd %f32, %f2
28314fmovd %f34, %f18
28315fmovs %f19, %f4
28316
28317P2335: !_MEMBAR (FP)
28318
28319P2336: !_DWLD [19] (Int)
28320sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
28321sub %i0, %i3, %i3
28322ldx [%i3 + 0], %l3
28323! move %l3(upper) -> %o0(lower)
28324srlx %l3, 32, %o5
28325or %o5, %o0, %o0
28326! move %l3(lower) -> %o1(upper)
28327sllx %l3, 32, %o1
28328
28329P2337: !_MEMBAR (FP)
28330membar #StoreLoad
28331
28332P2338: !_BLD [21] (FP) (Branch target of P2755)
28333wr %g0, 0xf0, %asi
28334sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
28335sub %i0, %i2, %i2
28336ldda [%i2 + 0] %asi, %f32
28337membar #Sync
28338! 3 addresses covered
28339fmovd %f32, %f18
28340fmovs %f18, %f5
28341fmovs %f19, %f6
28342fmovd %f34, %f18
28343fmovs %f19, %f7
28344ba P2339
28345nop
28346
28347TARGET2755:
28348ba RET2755
28349nop
28350
28351
28352P2339: !_MEMBAR (FP)
28353
28354P2340: !_PREFETCH [15] (Int)
28355sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
28356sub %i0, %i3, %i3
28357prefetch [%i3 + 0], 4
28358
28359P2341: !_DWLD [3] (Int)
28360ldx [%i1 + 0], %l7
28361! move %l7(upper) -> %o1(lower)
28362srlx %l7, 32, %l6
28363or %l6, %o1, %o1
28364! move %l7(lower) -> %o2(upper)
28365sllx %l7, 32, %o2
28366
28367P2342: !_DWST_BINIT [4] (maybe <- 0x1000082) (Int)
28368wr %g0, 0xe2, %asi
28369sllx %l4, 32, %o5
28370add %l4, 1, %l4
28371or %o5, %l4, %o5
28372stxa %o5, [%i1 + 0] %asi
28373add %l4, 1, %l4
28374
28375P2343: !_MEMBAR (Int)
28376membar #StoreLoad
28377
28378P2344: !_CAS [7] (maybe <- 0x1000084) (Int)
28379sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
28380sub %i0, %i2, %i2
28381add %i2, 4, %o5
28382lduw [%o5], %l6
28383mov %l6, %l7
28384! move %l7(lower) -> %o2(lower)
28385or %l7, %o2, %o2
28386mov %l4, %o3
28387cas [%o5], %l7, %o3
28388! move %o3(lower) -> %o3(upper)
28389sllx %o3, 32, %o3
28390add %l4, 1, %l4
28391
28392P2345: !_MEMBAR (FP) (Branch target of P2538)
28393ba P2346
28394nop
28395
28396TARGET2538:
28397ba RET2538
28398nop
28399
28400
28401P2346: !_BSTC [6] (maybe <- 0x40800072) (FP)
28402wr %g0, 0xe0, %asi
28403! preparing store val #0, next val will be in f32
28404fmovs %f16, %f20
28405fadds %f16, %f17, %f16
28406! preparing store val #1, next val will be in f33
28407fmovs %f16, %f21
28408fadds %f16, %f17, %f16
28409! preparing store val #2, next val will be in f35
28410fmovd %f20, %f32
28411fmovs %f16, %f21
28412fadds %f16, %f17, %f16
28413fmovd %f20, %f34
28414membar #Sync
28415stda %f32, [%i2 + 0 ] %asi
28416
28417P2347: !_MEMBAR (FP)
28418
28419P2348: !_BST [16] (maybe <- 0x40800075) (FP)
28420wr %g0, 0xf0, %asi
28421! preparing store val #0, next val will be in f32
28422fmovs %f16, %f20
28423fadds %f16, %f17, %f16
28424! preparing store val #1, next val will be in f33
28425fmovs %f16, %f21
28426fadds %f16, %f17, %f16
28427! preparing store val #2, next val will be in f35
28428fmovd %f20, %f32
28429fmovs %f16, %f21
28430fadds %f16, %f17, %f16
28431fmovd %f20, %f34
28432membar #Sync
28433stda %f32, [%i3 + 0 ] %asi
28434
28435P2349: !_MEMBAR (FP)
28436membar #StoreLoad
28437
28438P2350: !_ST [1] (maybe <- 0x40800078) (FP) (CBR)
28439! preparing store val #0, next val will be in f20
28440fmovs %f16, %f20
28441fadds %f16, %f17, %f16
28442st %f20, [%i0 + 4 ]
28443
28444! cbranch
28445andcc %l0, 1, %g0
28446be,pt %xcc, TARGET2350
28447nop
28448RET2350:
28449
28450! lfsr step begin
28451srlx %l0, 1, %o5
28452xnor %o5, %l0, %o5
28453sllx %o5, 63, %o5
28454or %o5, %l0, %l0
28455srlx %l0, 1, %l0
28456
28457
28458P2351: !_SWAP [5] (maybe <- 0x1000085) (Int)
28459mov %l4, %l7
28460swap [%i1 + 12], %l7
28461! move %l7(lower) -> %o3(lower)
28462srl %l7, 0, %l3
28463or %l3, %o3, %o3
28464add %l4, 1, %l4
28465
28466P2352: !_LDD [9] (Int)
28467sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
28468add %i0, %i3, %i3
28469ldd [%i3 + 0], %l6
28470! move %l6(lower) -> %o4(upper)
28471sllx %l6, 32, %o4
28472! move %l7(lower) -> %o4(lower)
28473or %l7, %o4, %o4
28474!---- flushing int results buffer----
28475mov %o0, %l5
28476mov %o1, %l5
28477mov %o2, %l5
28478mov %o3, %l5
28479mov %o4, %l5
28480
28481P2353: !_ST [1] (maybe <- 0x1000086) (Int)
28482stw %l4, [%i0 + 4 ]
28483add %l4, 1, %l4
28484
28485P2354: !_ST_BINIT [2] (maybe <- 0x1000087) (Int)
28486wr %g0, 0xe2, %asi
28487stwa %l4, [%i0 + 12] %asi
28488add %l4, 1, %l4
28489
28490P2355: !_MEMBAR (Int)
28491membar #StoreLoad
28492
28493P2356: !_DWLD [19] (Int) (Branch target of P2041)
28494sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
28495sub %i0, %i2, %i2
28496ldx [%i2 + 0], %o0
28497! move %o0(upper) -> %o0(upper)
28498! move %o0(lower) -> %o0(lower)
28499ba P2357
28500nop
28501
28502TARGET2041:
28503ba RET2041
28504nop
28505
28506
28507P2357: !_LDD [1] (Int) (CBR)
28508ldd [%i0 + 0], %l6
28509! move %l6(lower) -> %o1(upper)
28510sllx %l6, 32, %o1
28511! move %l7(lower) -> %o1(lower)
28512or %l7, %o1, %o1
28513
28514! cbranch
28515andcc %l0, 1, %g0
28516be,pt %xcc, TARGET2357
28517nop
28518RET2357:
28519
28520! lfsr step begin
28521srlx %l0, 1, %l3
28522xnor %l3, %l0, %l3
28523sllx %l3, 63, %l3
28524or %l3, %l0, %l0
28525srlx %l0, 1, %l0
28526
28527
28528P2358: !_LDD [21] (Int)
28529sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
28530sub %i0, %i3, %i3
28531ldd [%i3 + 0], %l6
28532! move %l6(lower) -> %o2(upper)
28533sllx %l6, 32, %o2
28534! move %l7(lower) -> %o2(lower)
28535or %l7, %o2, %o2
28536
28537P2359: !_ST_BINIT [16] (maybe <- 0x1000088) (Int)
28538wr %g0, 0xe2, %asi
28539sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
28540sub %i0, %i2, %i2
28541stwa %l4, [%i2 + 4] %asi
28542add %l4, 1, %l4
28543
28544P2360: !_MEMBAR (Int)
28545membar #StoreLoad
28546
28547P2361: !_LDD [1] (Int)
28548ldd [%i0 + 0], %l6
28549! move %l6(lower) -> %o3(upper)
28550sllx %l6, 32, %o3
28551! move %l7(lower) -> %o3(lower)
28552or %l7, %o3, %o3
28553
28554P2362: !_DWLD [18] (Int)
28555sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
28556sub %i0, %i3, %i3
28557ldx [%i3 + 0], %o4
28558! move %o4(upper) -> %o4(upper)
28559! move %o4(lower) -> %o4(lower)
28560!---- flushing int results buffer----
28561mov %o0, %l5
28562mov %o1, %l5
28563mov %o2, %l5
28564mov %o3, %l5
28565mov %o4, %l5
28566
28567P2363: !_MEMBAR (FP) (CBR)
28568
28569! cbranch
28570andcc %l0, 1, %g0
28571be,pn %xcc, TARGET2363
28572nop
28573RET2363:
28574
28575! lfsr step begin
28576srlx %l0, 1, %l7
28577xnor %l7, %l0, %l7
28578sllx %l7, 63, %l7
28579or %l7, %l0, %l0
28580srlx %l0, 1, %l0
28581
28582
28583P2364: !_BST [3] (maybe <- 0x40800079) (FP)
28584wr %g0, 0xf0, %asi
28585! preparing store val #0, next val will be in f32
28586fmovs %f16, %f20
28587fadds %f16, %f17, %f16
28588! preparing store val #1, next val will be in f33
28589fmovs %f16, %f21
28590fadds %f16, %f17, %f16
28591! preparing store val #2, next val will be in f35
28592fmovd %f20, %f32
28593fmovs %f16, %f21
28594fadds %f16, %f17, %f16
28595fmovd %f20, %f34
28596membar #Sync
28597stda %f32, [%i1 + 0 ] %asi
28598
28599P2365: !_MEMBAR (FP)
28600membar #StoreLoad
28601
28602P2366: !_DWLD [10] (Int)
28603sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
28604add %i0, %i2, %i2
28605ldx [%i2 + 0], %o0
28606! move %o0(upper) -> %o0(upper)
28607! move %o0(lower) -> %o0(lower)
28608
28609P2367: !_ST [1] (maybe <- 0x4080007c) (FP)
28610! preparing store val #0, next val will be in f20
28611fmovs %f16, %f20
28612fadds %f16, %f17, %f16
28613st %f20, [%i0 + 4 ]
28614
28615P2368: !_MEMBAR (FP)
28616
28617P2369: !_BST [19] (maybe <- 0x4080007d) (FP)
28618wr %g0, 0xf0, %asi
28619! preparing store val #0, next val will be in f32
28620fmovs %f16, %f20
28621fadds %f16, %f17, %f16
28622! preparing store val #1, next val will be in f33
28623fmovs %f16, %f21
28624fadds %f16, %f17, %f16
28625! preparing store val #2, next val will be in f35
28626fmovd %f20, %f32
28627fmovs %f16, %f21
28628fadds %f16, %f17, %f16
28629fmovd %f20, %f34
28630membar #Sync
28631stda %f32, [%i3 + 0 ] %asi
28632
28633P2370: !_MEMBAR (FP)
28634membar #StoreLoad
28635
28636P2371: !_SWAP [20] (maybe <- 0x1000089) (Int)
28637mov %l4, %o1
28638swap [%i3 + 12], %o1
28639! move %o1(lower) -> %o1(upper)
28640sllx %o1, 32, %o1
28641add %l4, 1, %l4
28642
28643P2372: !_LDD [9] (Int)
28644ldd [%i2 + 0], %l6
28645! move %l6(lower) -> %o1(lower)
28646or %l6, %o1, %o1
28647! move %l7(lower) -> %o2(upper)
28648sllx %l7, 32, %o2
28649
28650P2373: !_PREFETCH [9] (Int)
28651prefetch [%i2 + 0], 1
28652
28653P2374: !_LD [12] (Int)
28654sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
28655sub %i0, %i3, %i3
28656lduw [%i3 + 0], %l6
28657! move %l6(lower) -> %o2(lower)
28658or %l6, %o2, %o2
28659
28660P2375: !_LD [10] (FP)
28661ld [%i2 + 4], %f8
28662! 1 addresses covered
28663
28664P2376: !_CAS [13] (maybe <- 0x100008a) (Int)
28665add %i3, 4, %o5
28666lduw [%o5], %o3
28667mov %o3, %l7
28668! move %l7(lower) -> %o3(upper)
28669sllx %l7, 32, %o3
28670mov %l4, %l6
28671cas [%o5], %l7, %l6
28672! move %l6(lower) -> %o3(lower)
28673srl %l6, 0, %l7
28674or %l7, %o3, %o3
28675add %l4, 1, %l4
28676
28677P2377: !_MEMBAR (FP)
28678
28679P2378: !_BST [4] (maybe <- 0x40800080) (FP)
28680wr %g0, 0xf0, %asi
28681! preparing store val #0, next val will be in f32
28682fmovs %f16, %f20
28683fadds %f16, %f17, %f16
28684! preparing store val #1, next val will be in f33
28685fmovs %f16, %f21
28686fadds %f16, %f17, %f16
28687! preparing store val #2, next val will be in f35
28688fmovd %f20, %f32
28689fmovs %f16, %f21
28690fadds %f16, %f17, %f16
28691fmovd %f20, %f34
28692membar #Sync
28693stda %f32, [%i1 + 0 ] %asi
28694
28695P2379: !_MEMBAR (FP)
28696membar #StoreLoad
28697
28698P2380: !_PREFETCH [13] (Int)
28699prefetch [%i3 + 4], 1
28700
28701P2381: !_PREFETCH [18] (Int)
28702sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
28703sub %i0, %i2, %i2
28704prefetch [%i2 + 0], 21
28705
28706P2382: !_LD [23] (Int)
28707sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
28708sub %i0, %i3, %i3
28709lduw [%i3 + 12], %o4
28710! move %o4(lower) -> %o4(upper)
28711sllx %o4, 32, %o4
28712
28713P2383: !_CASX [13] (maybe <- 0x100008b) (Int)
28714sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
28715sub %i0, %i2, %i2
28716ldx [%i2], %l7
28717! move %l7(upper) -> %o4(lower)
28718srlx %l7, 32, %o5
28719or %o5, %o4, %o4
28720!---- flushing int results buffer----
28721mov %o0, %l5
28722mov %o1, %l5
28723mov %o2, %l5
28724mov %o3, %l5
28725mov %o4, %l5
28726! move %l7(lower) -> %o0(upper)
28727sllx %l7, 32, %o0
28728mov %l7, %o5
28729sllx %l4, 32, %l7
28730add %l4, 1, %l4
28731or %l4, %l7, %l7
28732casx [%i2], %o5, %l7
28733! move %l7(upper) -> %o0(lower)
28734srlx %l7, 32, %o5
28735or %o5, %o0, %o0
28736! move %l7(lower) -> %o1(upper)
28737sllx %l7, 32, %o1
28738add %l4, 1, %l4
28739
28740P2384: !_MEMBAR (FP)
28741membar #StoreLoad
28742
28743P2385: !_BLD [2] (FP)
28744wr %g0, 0xf0, %asi
28745ldda [%i0 + 0] %asi, %f32
28746membar #Sync
28747! 3 addresses covered
28748fmovd %f32, %f18
28749fmovs %f18, %f9
28750fmovs %f19, %f10
28751fmovd %f34, %f18
28752fmovs %f19, %f11
28753
28754P2386: !_MEMBAR (FP)
28755
28756P2387: !_BSTC [13] (maybe <- 0x40800083) (FP)
28757wr %g0, 0xe0, %asi
28758sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
28759sub %i0, %i3, %i3
28760! preparing store val #0, next val will be in f32
28761fmovs %f16, %f20
28762fadds %f16, %f17, %f16
28763! preparing store val #1, next val will be in f33
28764fmovs %f16, %f21
28765fadds %f16, %f17, %f16
28766! preparing store val #2, next val will be in f35
28767fmovd %f20, %f32
28768fmovs %f16, %f21
28769fadds %f16, %f17, %f16
28770fmovd %f20, %f34
28771membar #Sync
28772stda %f32, [%i3 + 0 ] %asi
28773
28774P2388: !_MEMBAR (FP)
28775
28776P2389: !_BSTC [12] (maybe <- 0x40800086) (FP)
28777wr %g0, 0xe0, %asi
28778! preparing store val #0, next val will be in f32
28779fmovs %f16, %f20
28780fadds %f16, %f17, %f16
28781! preparing store val #1, next val will be in f33
28782fmovs %f16, %f21
28783fadds %f16, %f17, %f16
28784! preparing store val #2, next val will be in f35
28785fmovd %f20, %f32
28786fmovs %f16, %f21
28787fadds %f16, %f17, %f16
28788fmovd %f20, %f34
28789membar #Sync
28790stda %f32, [%i3 + 0 ] %asi
28791
28792P2390: !_MEMBAR (FP)
28793
28794P2391: !_BSTC [0] (maybe <- 0x40800089) (FP)
28795wr %g0, 0xe0, %asi
28796! preparing store val #0, next val will be in f32
28797fmovs %f16, %f20
28798fadds %f16, %f17, %f16
28799! preparing store val #1, next val will be in f33
28800fmovs %f16, %f21
28801fadds %f16, %f17, %f16
28802! preparing store val #2, next val will be in f35
28803fmovd %f20, %f32
28804fmovs %f16, %f21
28805fadds %f16, %f17, %f16
28806fmovd %f20, %f34
28807membar #Sync
28808stda %f32, [%i0 + 0 ] %asi
28809
28810P2392: !_MEMBAR (FP)
28811membar #StoreLoad
28812
28813P2393: !_ST [23] (maybe <- 0x100008d) (Int)
28814sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
28815sub %i0, %i2, %i2
28816stw %l4, [%i2 + 12 ]
28817add %l4, 1, %l4
28818
28819P2394: !_DWST_BINIT [5] (maybe <- 0x100008e) (Int)
28820wr %g0, 0xe2, %asi
28821mov %l4, %l3
28822stxa %l3, [%i1 + 8] %asi
28823add %l4, 1, %l4
28824
28825P2395: !_MEMBAR (Int) (Branch target of P2021)
28826membar #StoreLoad
28827ba P2396
28828nop
28829
28830TARGET2021:
28831ba RET2021
28832nop
28833
28834
28835P2396: !_BLD [18] (FP)
28836wr %g0, 0xf0, %asi
28837sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
28838sub %i0, %i3, %i3
28839ldda [%i3 + 0] %asi, %f32
28840membar #Sync
28841! 3 addresses covered
28842fmovd %f32, %f12
28843fmovd %f34, %f18
28844fmovs %f19, %f14
28845
28846P2397: !_MEMBAR (FP)
28847
28848P2398: !_CASX [7] (maybe <- 0x100008f) (Int)
28849sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
28850sub %i0, %i2, %i2
28851ldx [%i2], %l7
28852! move %l7(upper) -> %o1(lower)
28853srlx %l7, 32, %o5
28854or %o5, %o1, %o1
28855! move %l7(lower) -> %o2(upper)
28856sllx %l7, 32, %o2
28857mov %l7, %o5
28858sllx %l4, 32, %l7
28859add %l4, 1, %l4
28860or %l4, %l7, %l7
28861casx [%i2], %o5, %l7
28862! move %l7(upper) -> %o2(lower)
28863srlx %l7, 32, %o5
28864or %o5, %o2, %o2
28865! move %l7(lower) -> %o3(upper)
28866sllx %l7, 32, %o3
28867add %l4, 1, %l4
28868
28869P2399: !_MEMBAR (FP)
28870
28871P2400: !_BST [21] (maybe <- 0x4080008c) (FP)
28872wr %g0, 0xf0, %asi
28873sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
28874sub %i0, %i3, %i3
28875! preparing store val #0, next val will be in f32
28876fmovs %f16, %f20
28877fadds %f16, %f17, %f16
28878! preparing store val #1, next val will be in f33
28879fmovs %f16, %f21
28880fadds %f16, %f17, %f16
28881! preparing store val #2, next val will be in f35
28882fmovd %f20, %f32
28883fmovs %f16, %f21
28884fadds %f16, %f17, %f16
28885fmovd %f20, %f34
28886membar #Sync
28887stda %f32, [%i3 + 0 ] %asi
28888
28889P2401: !_MEMBAR (FP)
28890
28891P2402: !_BSTC [16] (maybe <- 0x4080008f) (FP)
28892wr %g0, 0xe0, %asi
28893sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
28894sub %i0, %i2, %i2
28895! preparing store val #0, next val will be in f32
28896fmovs %f16, %f20
28897fadds %f16, %f17, %f16
28898! preparing store val #1, next val will be in f33
28899fmovs %f16, %f21
28900fadds %f16, %f17, %f16
28901! preparing store val #2, next val will be in f35
28902fmovd %f20, %f32
28903fmovs %f16, %f21
28904fadds %f16, %f17, %f16
28905fmovd %f20, %f34
28906membar #Sync
28907stda %f32, [%i2 + 0 ] %asi
28908
28909P2403: !_MEMBAR (FP)
28910membar #StoreLoad
28911
28912P2404: !_BLD [8] (FP) (CBR) (Branch target of P2577)
28913wr %g0, 0xf0, %asi
28914sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
28915sub %i0, %i3, %i3
28916ldda [%i3 + 0] %asi, %f32
28917membar #Sync
28918! 3 addresses covered
28919fmovd %f32, %f18
28920fmovs %f18, %f15
28921!---- flushing fp results buffer to %f30 ----
28922fmovd %f0, %f30
28923fmovd %f2, %f30
28924fmovd %f4, %f30
28925fmovd %f6, %f30
28926fmovd %f8, %f30
28927fmovd %f10, %f30
28928fmovd %f12, %f30
28929fmovd %f14, %f30
28930!--
28931fmovs %f19, %f0
28932fmovd %f34, %f18
28933fmovs %f19, %f1
28934
28935! cbranch
28936andcc %l0, 1, %g0
28937be,pn %xcc, TARGET2404
28938nop
28939RET2404:
28940
28941! lfsr step begin
28942srlx %l0, 1, %l6
28943xnor %l6, %l0, %l6
28944sllx %l6, 63, %l6
28945or %l6, %l0, %l0
28946srlx %l0, 1, %l0
28947
28948ba P2405
28949nop
28950
28951TARGET2577:
28952ba RET2577
28953nop
28954
28955
28956P2405: !_MEMBAR (FP)
28957
28958P2406: !_BLD [15] (FP)
28959wr %g0, 0xf0, %asi
28960ldda [%i2 + 0] %asi, %f32
28961membar #Sync
28962! 3 addresses covered
28963fmovd %f32, %f2
28964fmovd %f34, %f18
28965fmovs %f19, %f4
28966
28967P2407: !_MEMBAR (FP)
28968
28969P2408: !_ST [19] (maybe <- 0x1000091) (Int)
28970sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
28971sub %i0, %i2, %i2
28972stw %l4, [%i2 + 4 ]
28973add %l4, 1, %l4
28974
28975P2409: !_MEMBAR (FP)
28976membar #StoreLoad
28977
28978P2410: !_BLD [13] (FP) (Branch target of P2731)
28979wr %g0, 0xf0, %asi
28980sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
28981sub %i0, %i3, %i3
28982ldda [%i3 + 0] %asi, %f32
28983membar #Sync
28984! 3 addresses covered
28985fmovd %f32, %f18
28986fmovs %f18, %f5
28987fmovs %f19, %f6
28988fmovd %f34, %f18
28989fmovs %f19, %f7
28990ba P2411
28991nop
28992
28993TARGET2731:
28994ba RET2731
28995nop
28996
28997
28998P2411: !_MEMBAR (FP)
28999
29000P2412: !_ST_BINIT [6] (maybe <- 0x1000092) (Int)
29001wr %g0, 0xe2, %asi
29002sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
29003sub %i0, %i2, %i2
29004stwa %l4, [%i2 + 0] %asi
29005add %l4, 1, %l4
29006
29007P2413: !_MEMBAR (Int)
29008membar #StoreLoad
29009
29010P2414: !_PREFETCH [2] (Int)
29011prefetch [%i0 + 12], 28
29012
29013P2415: !_DWLD [20] (Int)
29014sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
29015sub %i0, %i3, %i3
29016ldx [%i3 + 8], %l6
29017! move %l6(lower) -> %o3(lower)
29018srl %l6, 0, %l3
29019or %l3, %o3, %o3
29020
29021P2416: !_SWAP [22] (maybe <- 0x1000093) (Int)
29022sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
29023sub %i0, %i2, %i2
29024mov %l4, %o4
29025swap [%i2 + 4], %o4
29026! move %o4(lower) -> %o4(upper)
29027sllx %o4, 32, %o4
29028add %l4, 1, %l4
29029
29030P2417: !_MEMBAR (FP)
29031
29032P2418: !_BST [7] (maybe <- 0x40800092) (FP) (Branch target of P2783)
29033wr %g0, 0xf0, %asi
29034sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
29035sub %i0, %i3, %i3
29036! preparing store val #0, next val will be in f32
29037fmovs %f16, %f20
29038fadds %f16, %f17, %f16
29039! preparing store val #1, next val will be in f33
29040fmovs %f16, %f21
29041fadds %f16, %f17, %f16
29042! preparing store val #2, next val will be in f35
29043fmovd %f20, %f32
29044fmovs %f16, %f21
29045fadds %f16, %f17, %f16
29046fmovd %f20, %f34
29047membar #Sync
29048stda %f32, [%i3 + 0 ] %asi
29049ba P2419
29050nop
29051
29052TARGET2783:
29053ba RET2783
29054nop
29055
29056
29057P2419: !_MEMBAR (FP)
29058membar #StoreLoad
29059
29060P2420: !_CASX [5] (maybe <- 0x1000094) (Int)
29061add %i1, 8, %l6
29062ldx [%l6], %o5
29063! move %o5(upper) -> %o4(lower)
29064srlx %o5, 32, %l3
29065or %l3, %o4, %o4
29066!---- flushing int results buffer----
29067mov %o0, %l5
29068mov %o1, %l5
29069mov %o2, %l5
29070mov %o3, %l5
29071mov %o4, %l5
29072! move %o5(lower) -> %o0(upper)
29073sllx %o5, 32, %o0
29074mov %o5, %l3
29075mov %l4, %o5
29076casx [%l6], %l3, %o5
29077! move %o5(upper) -> %o0(lower)
29078srlx %o5, 32, %l3
29079or %l3, %o0, %o0
29080! move %o5(lower) -> %o1(upper)
29081sllx %o5, 32, %o1
29082add %l4, 1, %l4
29083
29084P2421: !_MEMBAR (FP)
29085
29086P2422: !_BST [6] (maybe <- 0x40800095) (FP)
29087wr %g0, 0xf0, %asi
29088! preparing store val #0, next val will be in f32
29089fmovs %f16, %f20
29090fadds %f16, %f17, %f16
29091! preparing store val #1, next val will be in f33
29092fmovs %f16, %f21
29093fadds %f16, %f17, %f16
29094! preparing store val #2, next val will be in f35
29095fmovd %f20, %f32
29096fmovs %f16, %f21
29097fadds %f16, %f17, %f16
29098fmovd %f20, %f34
29099membar #Sync
29100stda %f32, [%i3 + 0 ] %asi
29101
29102P2423: !_MEMBAR (FP) (CBR)
29103membar #StoreLoad
29104
29105! cbranch
29106andcc %l0, 1, %g0
29107be,pt %xcc, TARGET2423
29108nop
29109RET2423:
29110
29111! lfsr step begin
29112srlx %l0, 1, %o5
29113xnor %o5, %l0, %o5
29114sllx %o5, 63, %o5
29115or %o5, %l0, %l0
29116srlx %l0, 1, %l0
29117
29118
29119P2424: !_SWAP [6] (maybe <- 0x1000095) (Int)
29120mov %l4, %l7
29121swap [%i3 + 0], %l7
29122! move %l7(lower) -> %o1(lower)
29123srl %l7, 0, %l3
29124or %l3, %o1, %o1
29125add %l4, 1, %l4
29126
29127P2425: !_DWST [16] (maybe <- 0x1000096) (Int)
29128sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
29129sub %i0, %i2, %i2
29130sllx %l4, 32, %o5
29131add %l4, 1, %l4
29132or %o5, %l4, %o5
29133stx %o5, [%i2 + 0]
29134add %l4, 1, %l4
29135
29136P2426: !_LD [17] (Int)
29137lduw [%i2 + 12], %o2
29138! move %o2(lower) -> %o2(upper)
29139sllx %o2, 32, %o2
29140
29141P2427: !_DWST [11] (maybe <- 0x1000098) (Int)
29142sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
29143add %i0, %i3, %i3
29144mov %l4, %l3
29145stx %l3, [%i3 + 8]
29146add %l4, 1, %l4
29147
29148P2428: !_CAS [16] (maybe <- 0x1000099) (Int)
29149add %i2, 4, %l3
29150lduw [%l3], %l7
29151mov %l7, %o5
29152! move %o5(lower) -> %o2(lower)
29153or %o5, %o2, %o2
29154mov %l4, %o3
29155cas [%l3], %o5, %o3
29156! move %o3(lower) -> %o3(upper)
29157sllx %o3, 32, %o3
29158add %l4, 1, %l4
29159
29160P2429: !_CAS [18] (maybe <- 0x100009a) (Int)
29161sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
29162sub %i0, %i2, %i2
29163lduw [%i2], %l7
29164mov %l7, %o5
29165! move %o5(lower) -> %o3(lower)
29166or %o5, %o3, %o3
29167mov %l4, %o4
29168cas [%i2], %o5, %o4
29169! move %o4(lower) -> %o4(upper)
29170sllx %o4, 32, %o4
29171add %l4, 1, %l4
29172
29173P2430: !_ST [8] (maybe <- 0x100009b) (Int)
29174sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
29175sub %i0, %i3, %i3
29176stw %l4, [%i3 + 12 ]
29177add %l4, 1, %l4
29178
29179P2431: !_MEMBAR (FP)
29180
29181P2432: !_BST [19] (maybe <- 0x40800098) (FP)
29182wr %g0, 0xf0, %asi
29183! preparing store val #0, next val will be in f32
29184fmovs %f16, %f20
29185fadds %f16, %f17, %f16
29186! preparing store val #1, next val will be in f33
29187fmovs %f16, %f21
29188fadds %f16, %f17, %f16
29189! preparing store val #2, next val will be in f35
29190fmovd %f20, %f32
29191fmovs %f16, %f21
29192fadds %f16, %f17, %f16
29193fmovd %f20, %f34
29194membar #Sync
29195stda %f32, [%i2 + 0 ] %asi
29196
29197P2433: !_MEMBAR (FP)
29198membar #StoreLoad
29199
29200P2434: !_CAS [21] (maybe <- 0x100009c) (Int)
29201sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
29202sub %i0, %i2, %i2
29203lduw [%i2], %l3
29204mov %l3, %l6
29205! move %l6(lower) -> %o4(lower)
29206or %l6, %o4, %o4
29207!---- flushing int results buffer----
29208mov %o0, %l5
29209mov %o1, %l5
29210mov %o2, %l5
29211mov %o3, %l5
29212mov %o4, %l5
29213mov %l4, %o0
29214cas [%i2], %l6, %o0
29215! move %o0(lower) -> %o0(upper)
29216sllx %o0, 32, %o0
29217add %l4, 1, %l4
29218
29219P2435: !_REPLACEMENT [21] (Int)
29220sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
29221sub %i0, %i3, %i3
29222sethi %hi(0x20000), %l6
29223ld [%i3+0], %o5
29224st %o5, [%i3+0]
29225add %i3, %l6, %l7
29226ld [%l7+0], %o5
29227st %o5, [%l7+0]
29228add %l7, %l6, %l7
29229ld [%l7+0], %o5
29230st %o5, [%l7+0]
29231add %l7, %l6, %l7
29232ld [%l7+0], %o5
29233st %o5, [%l7+0]
29234add %l7, %l6, %l7
29235ld [%l7+0], %o5
29236st %o5, [%l7+0]
29237add %l7, %l6, %l7
29238ld [%l7+0], %o5
29239st %o5, [%l7+0]
29240add %l7, %l6, %l7
29241ld [%l7+0], %o5
29242st %o5, [%l7+0]
29243add %l7, %l6, %l7
29244ld [%l7+0], %o5
29245st %o5, [%l7+0]
29246
29247P2436: !_ST [4] (maybe <- 0x100009d) (Int)
29248stw %l4, [%i1 + 4 ]
29249add %l4, 1, %l4
29250
29251P2437: !_CAS [6] (maybe <- 0x100009e) (Int)
29252sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
29253sub %i0, %i2, %i2
29254lduw [%i2], %l7
29255mov %l7, %o5
29256! move %o5(lower) -> %o0(lower)
29257or %o5, %o0, %o0
29258mov %l4, %o1
29259cas [%i2], %o5, %o1
29260! move %o1(lower) -> %o1(upper)
29261sllx %o1, 32, %o1
29262add %l4, 1, %l4
29263
29264P2438: !_DWST_BINIT [14] (maybe <- 0x100009f) (Int)
29265wr %g0, 0xe2, %asi
29266sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS2_O), %i3
29267sub %i0, %i3, %i3
29268mov %l4, %o5
29269stxa %o5, [%i3 + 8] %asi
29270add %l4, 1, %l4
29271
29272P2439: !_MEMBAR (Int)
29273membar #StoreLoad
29274
29275P2440: !_DWST_BINIT [16] (maybe <- 0x10000a0) (Int)
29276wr %g0, 0xe2, %asi
29277sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
29278sub %i0, %i2, %i2
29279sllx %l4, 32, %l7
29280add %l4, 1, %l4
29281or %l7, %l4, %l7
29282stxa %l7, [%i2 + 0] %asi
29283add %l4, 1, %l4
29284
29285P2441: !_MEMBAR (Int) (Branch target of P2128)
29286ba P2442
29287nop
29288
29289TARGET2128:
29290ba RET2128
29291nop
29292
29293
29294P2442: !_BSTC [0] (maybe <- 0x4080009b) (FP)
29295wr %g0, 0xe0, %asi
29296! preparing store val #0, next val will be in f32
29297fmovs %f16, %f20
29298fadds %f16, %f17, %f16
29299! preparing store val #1, next val will be in f33
29300fmovs %f16, %f21
29301fadds %f16, %f17, %f16
29302! preparing store val #2, next val will be in f35
29303fmovd %f20, %f32
29304fmovs %f16, %f21
29305fadds %f16, %f17, %f16
29306fmovd %f20, %f34
29307membar #Sync
29308stda %f32, [%i0 + 0 ] %asi
29309
29310P2443: !_MEMBAR (FP) (CBR)
29311membar #StoreLoad
29312
29313! cbranch
29314andcc %l0, 1, %g0
29315be,pn %xcc, TARGET2443
29316nop
29317RET2443:
29318
29319! lfsr step begin
29320srlx %l0, 1, %l3
29321xnor %l3, %l0, %l3
29322sllx %l3, 63, %l3
29323or %l3, %l0, %l0
29324srlx %l0, 1, %l0
29325
29326
29327P2444: !_BLD [7] (FP)
29328wr %g0, 0xf0, %asi
29329sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
29330sub %i0, %i3, %i3
29331ldda [%i3 + 0] %asi, %f32
29332membar #Sync
29333! 3 addresses covered
29334fmovd %f32, %f8
29335fmovd %f34, %f18
29336fmovs %f19, %f10
29337
29338P2445: !_MEMBAR (FP) (CBR)
29339
29340! cbranch
29341andcc %l0, 1, %g0
29342be,pt %xcc, TARGET2445
29343nop
29344RET2445:
29345
29346! lfsr step begin
29347srlx %l0, 1, %l6
29348xnor %l6, %l0, %l6
29349sllx %l6, 63, %l6
29350or %l6, %l0, %l0
29351srlx %l0, 1, %l0
29352
29353
29354P2446: !_LDD [10] (Int)
29355sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
29356add %i0, %i2, %i2
29357ldd [%i2 + 0], %l6
29358! move %l6(lower) -> %o1(lower)
29359or %l6, %o1, %o1
29360! move %l7(lower) -> %o2(upper)
29361sllx %l7, 32, %o2
29362
29363P2447: !_DWLD [1] (Int)
29364ldx [%i0 + 0], %l6
29365! move %l6(upper) -> %o2(lower)
29366srlx %l6, 32, %l3
29367or %l3, %o2, %o2
29368! move %l6(lower) -> %o3(upper)
29369sllx %l6, 32, %o3
29370
29371P2448: !_MEMBAR (FP)
29372
29373P2449: !_BSTC [19] (maybe <- 0x4080009e) (FP)
29374wr %g0, 0xe0, %asi
29375sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
29376sub %i0, %i3, %i3
29377! preparing store val #0, next val will be in f32
29378fmovs %f16, %f20
29379fadds %f16, %f17, %f16
29380! preparing store val #1, next val will be in f33
29381fmovs %f16, %f21
29382fadds %f16, %f17, %f16
29383! preparing store val #2, next val will be in f35
29384fmovd %f20, %f32
29385fmovs %f16, %f21
29386fadds %f16, %f17, %f16
29387fmovd %f20, %f34
29388membar #Sync
29389stda %f32, [%i3 + 0 ] %asi
29390
29391P2450: !_MEMBAR (FP)
29392
29393P2451: !_BST [12] (maybe <- 0x408000a1) (FP)
29394wr %g0, 0xf0, %asi
29395sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
29396sub %i0, %i2, %i2
29397! preparing store val #0, next val will be in f32
29398fmovs %f16, %f20
29399fadds %f16, %f17, %f16
29400! preparing store val #1, next val will be in f33
29401fmovs %f16, %f21
29402fadds %f16, %f17, %f16
29403! preparing store val #2, next val will be in f35
29404fmovd %f20, %f32
29405fmovs %f16, %f21
29406fadds %f16, %f17, %f16
29407fmovd %f20, %f34
29408membar #Sync
29409stda %f32, [%i2 + 0 ] %asi
29410
29411P2452: !_MEMBAR (FP)
29412membar #StoreLoad
29413
29414P2453: !_ST [12] (maybe <- 0x10000a2) (Int)
29415stw %l4, [%i2 + 0 ]
29416add %l4, 1, %l4
29417
29418P2454: !_LDD [19] (Int)
29419ldd [%i3 + 0], %l6
29420! move %l6(lower) -> %o3(lower)
29421or %l6, %o3, %o3
29422! move %l7(lower) -> %o4(upper)
29423sllx %l7, 32, %o4
29424
29425P2455: !_CASX [16] (maybe <- 0x10000a3) (Int)
29426sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
29427sub %i0, %i3, %i3
29428ldx [%i3], %o5
29429! move %o5(upper) -> %o4(lower)
29430srlx %o5, 32, %l3
29431or %l3, %o4, %o4
29432!---- flushing int results buffer----
29433mov %o0, %l5
29434mov %o1, %l5
29435mov %o2, %l5
29436mov %o3, %l5
29437mov %o4, %l5
29438! move %o5(lower) -> %o0(upper)
29439sllx %o5, 32, %o0
29440mov %o5, %l3
29441sllx %l4, 32, %o5
29442add %l4, 1, %l4
29443or %l4, %o5, %o5
29444casx [%i3], %l3, %o5
29445! move %o5(upper) -> %o0(lower)
29446srlx %o5, 32, %l3
29447or %l3, %o0, %o0
29448! move %o5(lower) -> %o1(upper)
29449sllx %o5, 32, %o1
29450add %l4, 1, %l4
29451
29452P2456: !_CASX [1] (maybe <- 0x10000a5) (Int)
29453ldx [%i0], %o5
29454! move %o5(upper) -> %o1(lower)
29455srlx %o5, 32, %l3
29456or %l3, %o1, %o1
29457! move %o5(lower) -> %o2(upper)
29458sllx %o5, 32, %o2
29459mov %o5, %l3
29460sllx %l4, 32, %o5
29461add %l4, 1, %l4
29462or %l4, %o5, %o5
29463casx [%i0], %l3, %o5
29464! move %o5(upper) -> %o2(lower)
29465srlx %o5, 32, %l3
29466or %l3, %o2, %o2
29467! move %o5(lower) -> %o3(upper)
29468sllx %o5, 32, %o3
29469add %l4, 1, %l4
29470
29471P2457: !_REPLACEMENT [1] (Int)
29472sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
29473sub %i0, %i2, %i2
29474sethi %hi(0x20000), %l3
29475ld [%i2+4], %l7
29476st %l7, [%i2+4]
29477add %i2, %l3, %l6
29478ld [%l6+4], %l7
29479st %l7, [%l6+4]
29480add %l6, %l3, %l6
29481ld [%l6+4], %l7
29482st %l7, [%l6+4]
29483add %l6, %l3, %l6
29484ld [%l6+4], %l7
29485st %l7, [%l6+4]
29486add %l6, %l3, %l6
29487ld [%l6+4], %l7
29488st %l7, [%l6+4]
29489add %l6, %l3, %l6
29490ld [%l6+4], %l7
29491st %l7, [%l6+4]
29492add %l6, %l3, %l6
29493ld [%l6+4], %l7
29494st %l7, [%l6+4]
29495add %l6, %l3, %l6
29496ld [%l6+4], %l7
29497st %l7, [%l6+4]
29498
29499P2458: !_MEMBAR (FP) (CBR)
29500membar #StoreLoad
29501
29502! cbranch
29503andcc %l0, 1, %g0
29504be,pn %xcc, TARGET2458
29505nop
29506RET2458:
29507
29508! lfsr step begin
29509srlx %l0, 1, %o5
29510xnor %o5, %l0, %o5
29511sllx %o5, 63, %o5
29512or %o5, %l0, %l0
29513srlx %l0, 1, %l0
29514
29515
29516P2459: !_BLD [16] (FP)
29517wr %g0, 0xf0, %asi
29518ldda [%i3 + 0] %asi, %f32
29519membar #Sync
29520! 3 addresses covered
29521fmovd %f32, %f18
29522fmovs %f18, %f11
29523fmovs %f19, %f12
29524fmovd %f34, %f18
29525fmovs %f19, %f13
29526
29527P2460: !_MEMBAR (FP)
29528
29529P2461: !_DWLD [0] (Int)
29530ldx [%i0 + 0], %l6
29531! move %l6(upper) -> %o3(lower)
29532srlx %l6, 32, %l3
29533or %l3, %o3, %o3
29534! move %l6(lower) -> %o4(upper)
29535sllx %l6, 32, %o4
29536
29537P2462: !_ST_BINIT [6] (maybe <- 0x10000a7) (Int)
29538wr %g0, 0xe2, %asi
29539sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
29540sub %i0, %i3, %i3
29541stwa %l4, [%i3 + 0] %asi
29542add %l4, 1, %l4
29543
29544P2463: !_MEMBAR (Int)
29545membar #StoreLoad
29546
29547P2464: !_DWLD [13] (Int)
29548sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
29549sub %i0, %i2, %i2
29550ldx [%i2 + 0], %l7
29551! move %l7(upper) -> %o4(lower)
29552srlx %l7, 32, %l6
29553or %l6, %o4, %o4
29554!---- flushing int results buffer----
29555mov %o0, %l5
29556mov %o1, %l5
29557mov %o2, %l5
29558mov %o3, %l5
29559mov %o4, %l5
29560! move %l7(lower) -> %o0(upper)
29561sllx %l7, 32, %o0
29562
29563P2465: !_CAS [16] (maybe <- 0x10000a8) (Int)
29564sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
29565sub %i0, %i3, %i3
29566add %i3, 4, %l3
29567lduw [%l3], %l7
29568mov %l7, %o5
29569! move %o5(lower) -> %o0(lower)
29570or %o5, %o0, %o0
29571mov %l4, %o1
29572cas [%l3], %o5, %o1
29573! move %o1(lower) -> %o1(upper)
29574sllx %o1, 32, %o1
29575add %l4, 1, %l4
29576
29577P2466: !_ST [0] (maybe <- 0x408000a4) (FP)
29578! preparing store val #0, next val will be in f20
29579fmovs %f16, %f20
29580fadds %f16, %f17, %f16
29581st %f20, [%i0 + 0 ]
29582
29583P2467: !_CASX [15] (maybe <- 0x10000a9) (Int)
29584ldx [%i3], %l6
29585! move %l6(upper) -> %o1(lower)
29586srlx %l6, 32, %l7
29587or %l7, %o1, %o1
29588! move %l6(lower) -> %o2(upper)
29589sllx %l6, 32, %o2
29590mov %l6, %l7
29591sllx %l4, 32, %l6
29592add %l4, 1, %l4
29593or %l4, %l6, %l6
29594casx [%i3], %l7, %l6
29595! move %l6(upper) -> %o2(lower)
29596srlx %l6, 32, %l7
29597or %l7, %o2, %o2
29598! move %l6(lower) -> %o3(upper)
29599sllx %l6, 32, %o3
29600add %l4, 1, %l4
29601
29602P2468: !_MEMBAR (FP)
29603membar #StoreLoad
29604
29605P2469: !_BLD [8] (FP)
29606wr %g0, 0xf0, %asi
29607sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
29608sub %i0, %i2, %i2
29609ldda [%i2 + 0] %asi, %f32
29610membar #Sync
29611! 3 addresses covered
29612fmovd %f32, %f14
29613!---- flushing fp results buffer to %f30 ----
29614fmovd %f0, %f30
29615fmovd %f2, %f30
29616fmovd %f4, %f30
29617fmovd %f6, %f30
29618fmovd %f8, %f30
29619fmovd %f10, %f30
29620fmovd %f12, %f30
29621fmovd %f14, %f30
29622!--
29623fmovd %f34, %f18
29624fmovs %f19, %f0
29625
29626P2470: !_MEMBAR (FP)
29627
29628P2471: !_DWST_BINIT [22] (maybe <- 0x10000ab) (Int)
29629wr %g0, 0xe2, %asi
29630sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
29631sub %i0, %i3, %i3
29632sllx %l4, 32, %l7
29633add %l4, 1, %l4
29634or %l7, %l4, %l7
29635stxa %l7, [%i3 + 0] %asi
29636add %l4, 1, %l4
29637
29638P2472: !_MEMBAR (Int)
29639membar #StoreLoad
29640
29641P2473: !_ST_BINIT [3] (maybe <- 0x10000ad) (Int)
29642wr %g0, 0xe2, %asi
29643stwa %l4, [%i1 + 0] %asi
29644add %l4, 1, %l4
29645
29646P2474: !_MEMBAR (Int)
29647
29648P2475: !_BSTC [17] (maybe <- 0x408000a5) (FP)
29649wr %g0, 0xe0, %asi
29650sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
29651sub %i0, %i2, %i2
29652! preparing store val #0, next val will be in f32
29653fmovs %f16, %f20
29654fadds %f16, %f17, %f16
29655! preparing store val #1, next val will be in f33
29656fmovs %f16, %f21
29657fadds %f16, %f17, %f16
29658! preparing store val #2, next val will be in f35
29659fmovd %f20, %f32
29660fmovs %f16, %f21
29661fadds %f16, %f17, %f16
29662fmovd %f20, %f34
29663membar #Sync
29664stda %f32, [%i2 + 0 ] %asi
29665
29666P2476: !_MEMBAR (FP) (Branch target of P2575)
29667membar #StoreLoad
29668ba P2477
29669nop
29670
29671TARGET2575:
29672ba RET2575
29673nop
29674
29675
29676P2477: !_ST [13] (maybe <- 0x10000ae) (Int) (LE)
29677wr %g0, 0x88, %asi
29678sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
29679sub %i0, %i3, %i3
29680! Change single-word-level endianess (big endian <-> little endian)
29681sethi %hi(0xff00ff00), %l3
29682or %l3, %lo(0xff00ff00), %l3
29683and %l4, %l3, %l6
29684srl %l6, 8, %l6
29685sll %l4, 8, %o5
29686and %o5, %l3, %o5
29687or %o5, %l6, %o5
29688srl %o5, 16, %l6
29689sll %o5, 16, %o5
29690srl %o5, 0, %o5
29691or %o5, %l6, %o5
29692stwa %o5, [%i3 + 4] %asi
29693add %l4, 1, %l4
29694
29695P2478: !_MEMBAR (FP)
29696membar #StoreLoad
29697
29698P2479: !_BLD [19] (FP)
29699wr %g0, 0xf0, %asi
29700sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
29701sub %i0, %i2, %i2
29702ldda [%i2 + 0] %asi, %f32
29703membar #Sync
29704! 3 addresses covered
29705fmovd %f32, %f18
29706fmovs %f18, %f1
29707fmovs %f19, %f2
29708fmovd %f34, %f18
29709fmovs %f19, %f3
29710
29711P2480: !_MEMBAR (FP) (CBR)
29712
29713! cbranch
29714andcc %l0, 1, %g0
29715be,pn %xcc, TARGET2480
29716nop
29717RET2480:
29718
29719! lfsr step begin
29720srlx %l0, 1, %l7
29721xnor %l7, %l0, %l7
29722sllx %l7, 63, %l7
29723or %l7, %l0, %l0
29724srlx %l0, 1, %l0
29725
29726
29727P2481: !_ST_BINIT [19] (maybe <- 0x10000af) (Int)
29728wr %g0, 0xe2, %asi
29729stwa %l4, [%i2 + 4] %asi
29730add %l4, 1, %l4
29731
29732P2482: !_MEMBAR (Int)
29733membar #StoreLoad
29734
29735P2483: !_ST [8] (maybe <- 0x10000b0) (Int)
29736sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
29737sub %i0, %i3, %i3
29738stw %l4, [%i3 + 12 ]
29739add %l4, 1, %l4
29740
29741P2484: !_DWLD [15] (Int)
29742sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
29743sub %i0, %i2, %i2
29744ldx [%i2 + 0], %l7
29745! move %l7(upper) -> %o3(lower)
29746srlx %l7, 32, %l6
29747or %l6, %o3, %o3
29748! move %l7(lower) -> %o4(upper)
29749sllx %l7, 32, %o4
29750
29751P2485: !_DWLD [7] (Int)
29752ldx [%i3 + 0], %l3
29753! move %l3(upper) -> %o4(lower)
29754srlx %l3, 32, %o5
29755or %o5, %o4, %o4
29756!---- flushing int results buffer----
29757mov %o0, %l5
29758mov %o1, %l5
29759mov %o2, %l5
29760mov %o3, %l5
29761mov %o4, %l5
29762! move %l3(lower) -> %o0(upper)
29763sllx %l3, 32, %o0
29764
29765P2486: !_MEMBAR (FP)
29766
29767P2487: !_BSTC [18] (maybe <- 0x408000a8) (FP)
29768wr %g0, 0xe0, %asi
29769sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
29770sub %i0, %i3, %i3
29771! preparing store val #0, next val will be in f32
29772fmovs %f16, %f20
29773fadds %f16, %f17, %f16
29774! preparing store val #1, next val will be in f33
29775fmovs %f16, %f21
29776fadds %f16, %f17, %f16
29777! preparing store val #2, next val will be in f35
29778fmovd %f20, %f32
29779fmovs %f16, %f21
29780fadds %f16, %f17, %f16
29781fmovd %f20, %f34
29782membar #Sync
29783stda %f32, [%i3 + 0 ] %asi
29784
29785P2488: !_MEMBAR (FP)
29786membar #StoreLoad
29787
29788P2489: !_PREFETCH [21] (Int)
29789sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
29790sub %i0, %i2, %i2
29791prefetch [%i2 + 0], 0
29792
29793P2490: !_ST_BINIT [22] (maybe <- 0x10000b1) (Int)
29794wr %g0, 0xe2, %asi
29795stwa %l4, [%i2 + 4] %asi
29796add %l4, 1, %l4
29797
29798P2491: !_MEMBAR (Int)
29799membar #StoreLoad
29800
29801P2492: !_PREFETCH [0] (Int)
29802prefetch [%i0 + 0], 3
29803
29804P2493: !_ST_BINIT [2] (maybe <- 0x10000b2) (Int)
29805wr %g0, 0xe2, %asi
29806stwa %l4, [%i0 + 12] %asi
29807add %l4, 1, %l4
29808
29809P2494: !_MEMBAR (Int)
29810membar #StoreLoad
29811
29812P2495: !_PREFETCH [8] (Int)
29813sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
29814sub %i0, %i3, %i3
29815prefetch [%i3 + 12], 16
29816
29817P2496: !_ST [21] (maybe <- 0x10000b3) (Int)
29818stw %l4, [%i2 + 0 ]
29819add %l4, 1, %l4
29820
29821P2497: !_DWST_BINIT [8] (maybe <- 0x10000b4) (Int)
29822wr %g0, 0xe2, %asi
29823mov %l4, %l6
29824stxa %l6, [%i3 + 8] %asi
29825add %l4, 1, %l4
29826
29827P2498: !_MEMBAR (Int)
29828membar #StoreLoad
29829
29830P2499: !_DWLD [4] (Int)
29831ldx [%i1 + 0], %l6
29832! move %l6(upper) -> %o0(lower)
29833srlx %l6, 32, %l3
29834or %l3, %o0, %o0
29835! move %l6(lower) -> %o1(upper)
29836sllx %l6, 32, %o1
29837
29838P2500: !_DWLD [9] (FP)
29839sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
29840add %i0, %i2, %i2
29841ldd [%i2 + 0], %f4
29842! 2 addresses covered
29843
29844P2501: !_DWST_BINIT [5] (maybe <- 0x10000b5) (Int)
29845wr %g0, 0xe2, %asi
29846mov %l4, %l7
29847stxa %l7, [%i1 + 8] %asi
29848add %l4, 1, %l4
29849
29850P2502: !_MEMBAR (Int)
29851membar #StoreLoad
29852
29853P2503: !_ST [4] (maybe <- 0x10000b6) (Int)
29854stw %l4, [%i1 + 4 ]
29855add %l4, 1, %l4
29856
29857P2504: !_DWST [0] (maybe <- 0x10000b7) (Int)
29858sllx %l4, 32, %l3
29859add %l4, 1, %l4
29860or %l3, %l4, %l3
29861stx %l3, [%i0 + 0]
29862add %l4, 1, %l4
29863
29864P2505: !_DWST_BINIT [13] (maybe <- 0x10000b9) (Int)
29865wr %g0, 0xe2, %asi
29866sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
29867sub %i0, %i3, %i3
29868sllx %l4, 32, %o5
29869add %l4, 1, %l4
29870or %o5, %l4, %o5
29871stxa %o5, [%i3 + 0] %asi
29872add %l4, 1, %l4
29873
29874P2506: !_MEMBAR (Int)
29875membar #StoreLoad
29876
29877P2507: !_LDD [13] (Int)
29878ldd [%i3 + 0], %l6
29879! move %l6(lower) -> %o1(lower)
29880or %l6, %o1, %o1
29881! move %l7(lower) -> %o2(upper)
29882sllx %l7, 32, %o2
29883
29884P2508: !_MEMBAR (FP)
29885
29886P2509: !_BST [10] (maybe <- 0x408000ab) (FP) (CBR)
29887wr %g0, 0xf0, %asi
29888! preparing store val #0, next val will be in f32
29889fmovs %f16, %f20
29890fadds %f16, %f17, %f16
29891! preparing store val #1, next val will be in f33
29892fmovs %f16, %f21
29893fadds %f16, %f17, %f16
29894! preparing store val #2, next val will be in f35
29895fmovd %f20, %f32
29896fmovs %f16, %f21
29897fadds %f16, %f17, %f16
29898fmovd %f20, %f34
29899membar #Sync
29900stda %f32, [%i2 + 0 ] %asi
29901
29902! cbranch
29903andcc %l0, 1, %g0
29904be,pn %xcc, TARGET2509
29905nop
29906RET2509:
29907
29908! lfsr step begin
29909srlx %l0, 1, %o5
29910xnor %o5, %l0, %o5
29911sllx %o5, 63, %o5
29912or %o5, %l0, %l0
29913srlx %l0, 1, %l0
29914
29915
29916P2510: !_MEMBAR (FP)
29917membar #StoreLoad
29918
29919P2511: !_ST_BINIT [0] (maybe <- 0x10000bb) (Int)
29920wr %g0, 0xe2, %asi
29921stwa %l4, [%i0 + 0] %asi
29922add %l4, 1, %l4
29923
29924P2512: !_MEMBAR (Int)
29925membar #StoreLoad
29926
29927P2513: !_CAS [1] (maybe <- 0x10000bc) (Int)
29928add %i0, 4, %l3
29929lduw [%l3], %l7
29930mov %l7, %o5
29931! move %o5(lower) -> %o2(lower)
29932or %o5, %o2, %o2
29933mov %l4, %o3
29934cas [%l3], %o5, %o3
29935! move %o3(lower) -> %o3(upper)
29936sllx %o3, 32, %o3
29937add %l4, 1, %l4
29938
29939P2514: !_MEMBAR (FP)
29940membar #StoreLoad
29941
29942P2515: !_BLD [16] (FP)
29943wr %g0, 0xf0, %asi
29944sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
29945add %i0, %i2, %i2
29946ldda [%i2 + 0] %asi, %f32
29947membar #Sync
29948! 3 addresses covered
29949fmovd %f32, %f6
29950fmovd %f34, %f18
29951fmovs %f19, %f8
29952
29953P2516: !_MEMBAR (FP)
29954
29955P2517: !_PREFETCH [9] (Int)
29956sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
29957add %i0, %i3, %i3
29958prefetch [%i3 + 0], 1
29959
29960P2518: !_LDD [1] (Int)
29961ldd [%i0 + 0], %l6
29962! move %l6(lower) -> %o3(lower)
29963or %l6, %o3, %o3
29964! move %l7(lower) -> %o4(upper)
29965sllx %l7, 32, %o4
29966
29967P2519: !_SWAP [14] (maybe <- 0x10000bd) (Int)
29968sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
29969sub %i0, %i2, %i2
29970mov %l4, %l7
29971swap [%i2 + 12], %l7
29972! move %l7(lower) -> %o4(lower)
29973srl %l7, 0, %l3
29974or %l3, %o4, %o4
29975!---- flushing int results buffer----
29976mov %o0, %l5
29977mov %o1, %l5
29978mov %o2, %l5
29979mov %o3, %l5
29980mov %o4, %l5
29981add %l4, 1, %l4
29982
29983P2520: !_DWST_BINIT [5] (maybe <- 0x10000be) (Int) (CBR)
29984wr %g0, 0xe2, %asi
29985mov %l4, %o5
29986stxa %o5, [%i1 + 8] %asi
29987add %l4, 1, %l4
29988
29989! cbranch
29990andcc %l0, 1, %g0
29991be,pn %xcc, TARGET2520
29992nop
29993RET2520:
29994
29995! lfsr step begin
29996srlx %l0, 1, %l7
29997xnor %l7, %l0, %l7
29998sllx %l7, 63, %l7
29999or %l7, %l0, %l0
30000srlx %l0, 1, %l0
30001
30002
30003P2521: !_MEMBAR (Int)
30004membar #StoreLoad
30005
30006P2522: !_CAS [5] (maybe <- 0x10000bf) (Int)
30007add %i1, 12, %l3
30008lduw [%l3], %o0
30009mov %o0, %o5
30010! move %o5(lower) -> %o0(upper)
30011sllx %o5, 32, %o0
30012mov %l4, %l7
30013cas [%l3], %o5, %l7
30014! move %l7(lower) -> %o0(lower)
30015srl %l7, 0, %o5
30016or %o5, %o0, %o0
30017add %l4, 1, %l4
30018
30019P2523: !_MEMBAR (FP)
30020
30021P2524: !_BSTC [18] (maybe <- 0x408000ae) (FP) (CBR)
30022wr %g0, 0xe0, %asi
30023sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
30024sub %i0, %i3, %i3
30025! preparing store val #0, next val will be in f32
30026fmovs %f16, %f20
30027fadds %f16, %f17, %f16
30028! preparing store val #1, next val will be in f33
30029fmovs %f16, %f21
30030fadds %f16, %f17, %f16
30031! preparing store val #2, next val will be in f35
30032fmovd %f20, %f32
30033fmovs %f16, %f21
30034fadds %f16, %f17, %f16
30035fmovd %f20, %f34
30036membar #Sync
30037stda %f32, [%i3 + 0 ] %asi
30038
30039! cbranch
30040andcc %l0, 1, %g0
30041be,pt %xcc, TARGET2524
30042nop
30043RET2524:
30044
30045! lfsr step begin
30046srlx %l0, 1, %l7
30047xnor %l7, %l0, %l7
30048sllx %l7, 63, %l7
30049or %l7, %l0, %l0
30050srlx %l0, 1, %l0
30051
30052
30053P2525: !_MEMBAR (FP) (CBR)
30054membar #StoreLoad
30055
30056! cbranch
30057andcc %l0, 1, %g0
30058be,pt %xcc, TARGET2525
30059nop
30060RET2525:
30061
30062! lfsr step begin
30063srlx %l0, 1, %o5
30064xnor %o5, %l0, %o5
30065sllx %o5, 63, %o5
30066or %o5, %l0, %l0
30067srlx %l0, 1, %l0
30068
30069
30070P2526: !_ST_BINIT [14] (maybe <- 0x10000c0) (Int)
30071wr %g0, 0xe2, %asi
30072stwa %l4, [%i2 + 12] %asi
30073add %l4, 1, %l4
30074
30075P2527: !_MEMBAR (Int)
30076membar #StoreLoad
30077
30078P2528: !_CASX [2] (maybe <- 0x10000c1) (Int)
30079add %i0, 8, %l3
30080ldx [%l3], %o1
30081! move %o1(upper) -> %o1(upper)
30082! move %o1(lower) -> %o1(lower)
30083mov %o1, %o5
30084mov %l4, %o2
30085casx [%l3], %o5, %o2
30086! move %o2(upper) -> %o2(upper)
30087! move %o2(lower) -> %o2(lower)
30088add %l4, 1, %l4
30089
30090P2529: !_DWST_BINIT [10] (maybe <- 0x10000c2) (Int)
30091wr %g0, 0xe2, %asi
30092sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
30093add %i0, %i2, %i2
30094sllx %l4, 32, %o5
30095add %l4, 1, %l4
30096or %o5, %l4, %o5
30097stxa %o5, [%i2 + 0] %asi
30098add %l4, 1, %l4
30099
30100P2530: !_MEMBAR (Int) (Branch target of P2525)
30101membar #StoreLoad
30102ba P2531
30103nop
30104
30105TARGET2525:
30106ba RET2525
30107nop
30108
30109
30110P2531: !_DWLD [17] (Int)
30111sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
30112add %i0, %i3, %i3
30113ldx [%i3 + 8], %o3
30114! move %o3(lower) -> %o3(upper)
30115sllx %o3, 32, %o3
30116
30117P2532: !_MEMBAR (FP) (Branch target of P2726)
30118ba P2533
30119nop
30120
30121TARGET2726:
30122ba RET2726
30123nop
30124
30125
30126P2533: !_BST [0] (maybe <- 0x408000b1) (FP) (Branch target of P2959)
30127wr %g0, 0xf0, %asi
30128! preparing store val #0, next val will be in f32
30129fmovs %f16, %f20
30130fadds %f16, %f17, %f16
30131! preparing store val #1, next val will be in f33
30132fmovs %f16, %f21
30133fadds %f16, %f17, %f16
30134! preparing store val #2, next val will be in f35
30135fmovd %f20, %f32
30136fmovs %f16, %f21
30137fadds %f16, %f17, %f16
30138fmovd %f20, %f34
30139membar #Sync
30140stda %f32, [%i0 + 0 ] %asi
30141ba P2534
30142nop
30143
30144TARGET2959:
30145ba RET2959
30146nop
30147
30148
30149P2534: !_MEMBAR (FP)
30150membar #StoreLoad
30151
30152P2535: !_ST_BINIT [17] (maybe <- 0x10000c4) (Int)
30153wr %g0, 0xe2, %asi
30154stwa %l4, [%i3 + 12] %asi
30155add %l4, 1, %l4
30156
30157P2536: !_MEMBAR (Int)
30158
30159P2537: !_BST [1] (maybe <- 0x408000b4) (FP)
30160wr %g0, 0xf0, %asi
30161! preparing store val #0, next val will be in f32
30162fmovs %f16, %f20
30163fadds %f16, %f17, %f16
30164! preparing store val #1, next val will be in f33
30165fmovs %f16, %f21
30166fadds %f16, %f17, %f16
30167! preparing store val #2, next val will be in f35
30168fmovd %f20, %f32
30169fmovs %f16, %f21
30170fadds %f16, %f17, %f16
30171fmovd %f20, %f34
30172membar #Sync
30173stda %f32, [%i0 + 0 ] %asi
30174
30175P2538: !_MEMBAR (FP) (CBR)
30176membar #StoreLoad
30177
30178! cbranch
30179andcc %l0, 1, %g0
30180be,pt %xcc, TARGET2538
30181nop
30182RET2538:
30183
30184! lfsr step begin
30185srlx %l0, 1, %l6
30186xnor %l6, %l0, %l6
30187sllx %l6, 63, %l6
30188or %l6, %l0, %l0
30189srlx %l0, 1, %l0
30190
30191
30192P2539: !_BLD [14] (FP)
30193wr %g0, 0xf0, %asi
30194sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
30195sub %i0, %i2, %i2
30196ldda [%i2 + 0] %asi, %f32
30197membar #Sync
30198! 3 addresses covered
30199fmovd %f32, %f18
30200fmovs %f18, %f9
30201fmovs %f19, %f10
30202fmovd %f34, %f18
30203fmovs %f19, %f11
30204
30205P2540: !_MEMBAR (FP)
30206
30207P2541: !_CAS [0] (maybe <- 0x10000c5) (Int)
30208lduw [%i0], %l6
30209mov %l6, %l7
30210! move %l7(lower) -> %o3(lower)
30211or %l7, %o3, %o3
30212mov %l4, %o4
30213cas [%i0], %l7, %o4
30214! move %o4(lower) -> %o4(upper)
30215sllx %o4, 32, %o4
30216add %l4, 1, %l4
30217
30218P2542: !_PREFETCH [5] (Int)
30219prefetch [%i1 + 12], 2
30220
30221P2543: !_PREFETCH [13] (Int)
30222prefetch [%i2 + 4], 4
30223
30224P2544: !_DWST [16] (maybe <- 0x10000c6) (Int)
30225sllx %l4, 32, %l7
30226add %l4, 1, %l4
30227or %l7, %l4, %l7
30228stx %l7, [%i3 + 0]
30229add %l4, 1, %l4
30230
30231P2545: !_DWST_BINIT [2] (maybe <- 0x10000c8) (Int)
30232wr %g0, 0xe2, %asi
30233mov %l4, %l6
30234stxa %l6, [%i0 + 8] %asi
30235add %l4, 1, %l4
30236
30237P2546: !_MEMBAR (Int)
30238membar #StoreLoad
30239
30240P2547: !_BLD [19] (FP)
30241wr %g0, 0xf0, %asi
30242sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
30243sub %i0, %i3, %i3
30244ldda [%i3 + 0] %asi, %f32
30245membar #Sync
30246! 3 addresses covered
30247fmovd %f32, %f12
30248fmovd %f34, %f18
30249fmovs %f19, %f14
30250
30251P2548: !_MEMBAR (FP)
30252
30253P2549: !_ST [21] (maybe <- 0x10000c9) (Int)
30254sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
30255sub %i0, %i2, %i2
30256stw %l4, [%i2 + 0 ]
30257add %l4, 1, %l4
30258
30259P2550: !_MEMBAR (FP)
30260membar #StoreLoad
30261
30262P2551: !_BLD [21] (FP)
30263wr %g0, 0xf0, %asi
30264ldda [%i2 + 0] %asi, %f32
30265membar #Sync
30266! 3 addresses covered
30267fmovd %f32, %f18
30268fmovs %f18, %f15
30269!---- flushing fp results buffer to %f30 ----
30270fmovd %f0, %f30
30271fmovd %f2, %f30
30272fmovd %f4, %f30
30273fmovd %f6, %f30
30274fmovd %f8, %f30
30275fmovd %f10, %f30
30276fmovd %f12, %f30
30277fmovd %f14, %f30
30278!--
30279fmovs %f19, %f0
30280fmovd %f34, %f18
30281fmovs %f19, %f1
30282
30283P2552: !_MEMBAR (FP)
30284
30285P2553: !_CASX [18] (maybe <- 0x10000ca) (Int)
30286ldx [%i3], %l7
30287! move %l7(upper) -> %o4(lower)
30288srlx %l7, 32, %o5
30289or %o5, %o4, %o4
30290!---- flushing int results buffer----
30291mov %o0, %l5
30292mov %o1, %l5
30293mov %o2, %l5
30294mov %o3, %l5
30295mov %o4, %l5
30296! move %l7(lower) -> %o0(upper)
30297sllx %l7, 32, %o0
30298mov %l7, %o5
30299sllx %l4, 32, %l7
30300add %l4, 1, %l4
30301or %l4, %l7, %l7
30302casx [%i3], %o5, %l7
30303! move %l7(upper) -> %o0(lower)
30304srlx %l7, 32, %o5
30305or %o5, %o0, %o0
30306! move %l7(lower) -> %o1(upper)
30307sllx %l7, 32, %o1
30308add %l4, 1, %l4
30309
30310P2554: !_DWST_BINIT [1] (maybe <- 0x10000cc) (Int)
30311wr %g0, 0xe2, %asi
30312sllx %l4, 32, %o5
30313add %l4, 1, %l4
30314or %o5, %l4, %o5
30315stxa %o5, [%i0 + 0] %asi
30316add %l4, 1, %l4
30317
30318P2555: !_MEMBAR (Int)
30319membar #StoreLoad
30320
30321P2556: !_PREFETCH [20] (Int)
30322prefetch [%i3 + 12], 1
30323
30324P2557: !_MEMBAR (FP)
30325membar #StoreLoad
30326
30327P2558: !_BLD [11] (FP)
30328wr %g0, 0xf0, %asi
30329sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
30330add %i0, %i3, %i3
30331ldda [%i3 + 0] %asi, %f32
30332membar #Sync
30333! 3 addresses covered
30334fmovd %f32, %f2
30335fmovd %f34, %f18
30336fmovs %f19, %f4
30337
30338P2559: !_MEMBAR (FP)
30339
30340P2560: !_DWLD [20] (Int)
30341sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
30342sub %i0, %i2, %i2
30343ldx [%i2 + 8], %o5
30344! move %o5(lower) -> %o1(lower)
30345srl %o5, 0, %l7
30346or %l7, %o1, %o1
30347
30348P2561: !_DWLD [14] (Int)
30349sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
30350sub %i0, %i3, %i3
30351ldx [%i3 + 8], %o2
30352! move %o2(lower) -> %o2(upper)
30353sllx %o2, 32, %o2
30354
30355P2562: !_LD [18] (Int)
30356lduw [%i2 + 0], %o5
30357! move %o5(lower) -> %o2(lower)
30358or %o5, %o2, %o2
30359
30360P2563: !_SWAP [7] (maybe <- 0x10000ce) (Int)
30361sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
30362sub %i0, %i2, %i2
30363mov %l4, %o3
30364swap [%i2 + 4], %o3
30365! move %o3(lower) -> %o3(upper)
30366sllx %o3, 32, %o3
30367add %l4, 1, %l4
30368
30369P2564: !_MEMBAR (FP)
30370
30371P2565: !_BST [7] (maybe <- 0x408000b7) (FP) (CBR)
30372wr %g0, 0xf0, %asi
30373! preparing store val #0, next val will be in f32
30374fmovs %f16, %f20
30375fadds %f16, %f17, %f16
30376! preparing store val #1, next val will be in f33
30377fmovs %f16, %f21
30378fadds %f16, %f17, %f16
30379! preparing store val #2, next val will be in f35
30380fmovd %f20, %f32
30381fmovs %f16, %f21
30382fadds %f16, %f17, %f16
30383fmovd %f20, %f34
30384membar #Sync
30385stda %f32, [%i2 + 0 ] %asi
30386
30387! cbranch
30388andcc %l0, 1, %g0
30389be,pt %xcc, TARGET2565
30390nop
30391RET2565:
30392
30393! lfsr step begin
30394srlx %l0, 1, %l7
30395xnor %l7, %l0, %l7
30396sllx %l7, 63, %l7
30397or %l7, %l0, %l0
30398srlx %l0, 1, %l0
30399
30400
30401P2566: !_MEMBAR (FP)
30402membar #StoreLoad
30403
30404P2567: !_LD [15] (Int) (CBR) (Branch target of P2690)
30405sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
30406add %i0, %i3, %i3
30407lduw [%i3 + 0], %l3
30408! move %l3(lower) -> %o3(lower)
30409or %l3, %o3, %o3
30410
30411! cbranch
30412andcc %l0, 1, %g0
30413be,pn %xcc, TARGET2567
30414nop
30415RET2567:
30416
30417! lfsr step begin
30418srlx %l0, 1, %l6
30419xnor %l6, %l0, %l6
30420sllx %l6, 63, %l6
30421or %l6, %l0, %l0
30422srlx %l0, 1, %l0
30423
30424ba P2568
30425nop
30426
30427TARGET2690:
30428ba RET2690
30429nop
30430
30431
30432P2568: !_PREFETCH [7] (Int)
30433prefetch [%i2 + 4], 17
30434
30435P2569: !_PREFETCH [11] (Int)
30436sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
30437add %i0, %i2, %i2
30438prefetch [%i2 + 12], 4
30439
30440P2570: !_LDD [5] (Int)
30441ldd [%i1 + 8], %l6
30442! move %l7(lower) -> %o4(upper)
30443sllx %l7, 32, %o4
30444
30445P2571: !_CAS [14] (maybe <- 0x10000cf) (Int)
30446sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
30447sub %i0, %i3, %i3
30448add %i3, 12, %l6
30449lduw [%l6], %o5
30450mov %o5, %l3
30451! move %l3(lower) -> %o4(lower)
30452or %l3, %o4, %o4
30453!---- flushing int results buffer----
30454mov %o0, %l5
30455mov %o1, %l5
30456mov %o2, %l5
30457mov %o3, %l5
30458mov %o4, %l5
30459mov %l4, %o0
30460cas [%l6], %l3, %o0
30461! move %o0(lower) -> %o0(upper)
30462sllx %o0, 32, %o0
30463add %l4, 1, %l4
30464
30465P2572: !_PREFETCH [21] (Int) (LE)
30466wr %g0, 0x88, %asi
30467sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
30468sub %i0, %i2, %i2
30469prefetcha [%i2 + 0] %asi, 20
30470
30471P2573: !_CASX [13] (maybe <- 0x10000d0) (Int)
30472ldx [%i3], %o5
30473! move %o5(upper) -> %o0(lower)
30474srlx %o5, 32, %l3
30475or %l3, %o0, %o0
30476! move %o5(lower) -> %o1(upper)
30477sllx %o5, 32, %o1
30478mov %o5, %l3
30479sllx %l4, 32, %o5
30480add %l4, 1, %l4
30481or %l4, %o5, %o5
30482casx [%i3], %l3, %o5
30483! move %o5(upper) -> %o1(lower)
30484srlx %o5, 32, %l3
30485or %l3, %o1, %o1
30486! move %o5(lower) -> %o2(upper)
30487sllx %o5, 32, %o2
30488add %l4, 1, %l4
30489
30490P2574: !_SWAP [14] (maybe <- 0x10000d2) (Int)
30491mov %l4, %l7
30492swap [%i3 + 12], %l7
30493! move %l7(lower) -> %o2(lower)
30494srl %l7, 0, %l3
30495or %l3, %o2, %o2
30496add %l4, 1, %l4
30497
30498P2575: !_DWST_BINIT [6] (maybe <- 0x10000d3) (Int) (CBR)
30499wr %g0, 0xe2, %asi
30500sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
30501sub %i0, %i3, %i3
30502sllx %l4, 32, %o5
30503add %l4, 1, %l4
30504or %o5, %l4, %o5
30505stxa %o5, [%i3 + 0] %asi
30506add %l4, 1, %l4
30507
30508! cbranch
30509andcc %l0, 1, %g0
30510be,pt %xcc, TARGET2575
30511nop
30512RET2575:
30513
30514! lfsr step begin
30515srlx %l0, 1, %l7
30516xnor %l7, %l0, %l7
30517sllx %l7, 63, %l7
30518or %l7, %l0, %l0
30519srlx %l0, 1, %l0
30520
30521
30522P2576: !_MEMBAR (Int)
30523membar #StoreLoad
30524
30525P2577: !_DWLD [13] (FP) (CBR)
30526sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
30527sub %i0, %i2, %i2
30528ldd [%i2 + 0], %f18
30529! 2 addresses covered
30530fmovs %f18, %f5
30531fmovs %f19, %f6
30532
30533! cbranch
30534andcc %l0, 1, %g0
30535be,pt %xcc, TARGET2577
30536nop
30537RET2577:
30538
30539! lfsr step begin
30540srlx %l0, 1, %o5
30541xnor %o5, %l0, %o5
30542sllx %o5, 63, %o5
30543or %o5, %l0, %l0
30544srlx %l0, 1, %l0
30545
30546
30547P2578: !_DWST_BINIT [1] (maybe <- 0x10000d5) (Int)
30548wr %g0, 0xe2, %asi
30549sllx %l4, 32, %l3
30550add %l4, 1, %l4
30551or %l3, %l4, %l3
30552stxa %l3, [%i0 + 0] %asi
30553add %l4, 1, %l4
30554
30555P2579: !_MEMBAR (Int)
30556
30557P2580: !_BSTC [4] (maybe <- 0x408000ba) (FP)
30558wr %g0, 0xe0, %asi
30559! preparing store val #0, next val will be in f32
30560fmovs %f16, %f20
30561fadds %f16, %f17, %f16
30562! preparing store val #1, next val will be in f33
30563fmovs %f16, %f21
30564fadds %f16, %f17, %f16
30565! preparing store val #2, next val will be in f35
30566fmovd %f20, %f32
30567fmovs %f16, %f21
30568fadds %f16, %f17, %f16
30569fmovd %f20, %f34
30570membar #Sync
30571stda %f32, [%i1 + 0 ] %asi
30572
30573P2581: !_MEMBAR (FP)
30574membar #StoreLoad
30575
30576P2582: !_CAS [22] (maybe <- 0x10000d7) (Int)
30577sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
30578sub %i0, %i3, %i3
30579add %i3, 4, %l3
30580lduw [%l3], %o3
30581mov %o3, %o5
30582! move %o5(lower) -> %o3(upper)
30583sllx %o5, 32, %o3
30584mov %l4, %l7
30585cas [%l3], %o5, %l7
30586! move %l7(lower) -> %o3(lower)
30587srl %l7, 0, %o5
30588or %o5, %o3, %o3
30589add %l4, 1, %l4
30590
30591P2583: !_LDD [4] (Int)
30592ldd [%i1 + 0], %l6
30593! move %l6(lower) -> %o4(upper)
30594sllx %l6, 32, %o4
30595! move %l7(lower) -> %o4(lower)
30596or %l7, %o4, %o4
30597!---- flushing int results buffer----
30598mov %o0, %l5
30599mov %o1, %l5
30600mov %o2, %l5
30601mov %o3, %l5
30602mov %o4, %l5
30603
30604P2584: !_CAS [18] (maybe <- 0x10000d8) (Int) (CBR)
30605sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
30606sub %i0, %i2, %i2
30607lduw [%i2], %o0
30608mov %o0, %l3
30609! move %l3(lower) -> %o0(upper)
30610sllx %l3, 32, %o0
30611mov %l4, %o5
30612cas [%i2], %l3, %o5
30613! move %o5(lower) -> %o0(lower)
30614srl %o5, 0, %l3
30615or %l3, %o0, %o0
30616add %l4, 1, %l4
30617
30618! cbranch
30619andcc %l0, 1, %g0
30620be,pn %xcc, TARGET2584
30621nop
30622RET2584:
30623
30624! lfsr step begin
30625srlx %l0, 1, %l3
30626xnor %l3, %l0, %l3
30627sllx %l3, 63, %l3
30628or %l3, %l0, %l0
30629srlx %l0, 1, %l0
30630
30631
30632P2585: !_MEMBAR (FP) (Branch target of P2625)
30633ba P2586
30634nop
30635
30636TARGET2625:
30637ba RET2625
30638nop
30639
30640
30641P2586: !_BST [16] (maybe <- 0x408000bd) (FP)
30642wr %g0, 0xf0, %asi
30643sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
30644add %i0, %i3, %i3
30645! preparing store val #0, next val will be in f32
30646fmovs %f16, %f20
30647fadds %f16, %f17, %f16
30648! preparing store val #1, next val will be in f33
30649fmovs %f16, %f21
30650fadds %f16, %f17, %f16
30651! preparing store val #2, next val will be in f35
30652fmovd %f20, %f32
30653fmovs %f16, %f21
30654fadds %f16, %f17, %f16
30655fmovd %f20, %f34
30656membar #Sync
30657stda %f32, [%i3 + 0 ] %asi
30658
30659P2587: !_MEMBAR (FP)
30660membar #StoreLoad
30661
30662P2588: !_DWST_BINIT [11] (maybe <- 0x10000d9) (Int)
30663wr %g0, 0xe2, %asi
30664sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
30665add %i0, %i2, %i2
30666mov %l4, %l3
30667stxa %l3, [%i2 + 8] %asi
30668add %l4, 1, %l4
30669
30670P2589: !_MEMBAR (Int)
30671membar #StoreLoad
30672
30673P2590: !_ST [13] (maybe <- 0x10000da) (Int)
30674sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
30675sub %i0, %i3, %i3
30676stw %l4, [%i3 + 4 ]
30677add %l4, 1, %l4
30678
30679P2591: !_CAS [18] (maybe <- 0x10000db) (Int)
30680sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
30681sub %i0, %i2, %i2
30682lduw [%i2], %o1
30683mov %o1, %l7
30684! move %l7(lower) -> %o1(upper)
30685sllx %l7, 32, %o1
30686mov %l4, %l6
30687cas [%i2], %l7, %l6
30688! move %l6(lower) -> %o1(lower)
30689srl %l6, 0, %l7
30690or %l7, %o1, %o1
30691add %l4, 1, %l4
30692
30693P2592: !_CASX [1] (maybe <- 0x10000dc) (Int)
30694ldx [%i0], %o2
30695! move %o2(upper) -> %o2(upper)
30696! move %o2(lower) -> %o2(lower)
30697mov %o2, %l7
30698sllx %l4, 32, %o3
30699add %l4, 1, %l4
30700or %l4, %o3, %o3
30701casx [%i0], %l7, %o3
30702! move %o3(upper) -> %o3(upper)
30703! move %o3(lower) -> %o3(lower)
30704add %l4, 1, %l4
30705
30706P2593: !_DWST_BINIT [17] (maybe <- 0x10000de) (Int) (Branch target of P2567)
30707wr %g0, 0xe2, %asi
30708sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
30709add %i0, %i3, %i3
30710mov %l4, %l7
30711stxa %l7, [%i3 + 8] %asi
30712add %l4, 1, %l4
30713ba P2594
30714nop
30715
30716TARGET2567:
30717ba RET2567
30718nop
30719
30720
30721P2594: !_MEMBAR (Int)
30722
30723P2595: !_BST [20] (maybe <- 0x408000c0) (FP)
30724wr %g0, 0xf0, %asi
30725! preparing store val #0, next val will be in f32
30726fmovs %f16, %f20
30727fadds %f16, %f17, %f16
30728! preparing store val #1, next val will be in f33
30729fmovs %f16, %f21
30730fadds %f16, %f17, %f16
30731! preparing store val #2, next val will be in f35
30732fmovd %f20, %f32
30733fmovs %f16, %f21
30734fadds %f16, %f17, %f16
30735fmovd %f20, %f34
30736membar #Sync
30737stda %f32, [%i2 + 0 ] %asi
30738
30739P2596: !_MEMBAR (FP)
30740
30741P2597: !_BST [21] (maybe <- 0x408000c3) (FP)
30742wr %g0, 0xf0, %asi
30743sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
30744sub %i0, %i2, %i2
30745! preparing store val #0, next val will be in f32
30746fmovs %f16, %f20
30747fadds %f16, %f17, %f16
30748! preparing store val #1, next val will be in f33
30749fmovs %f16, %f21
30750fadds %f16, %f17, %f16
30751! preparing store val #2, next val will be in f35
30752fmovd %f20, %f32
30753fmovs %f16, %f21
30754fadds %f16, %f17, %f16
30755fmovd %f20, %f34
30756membar #Sync
30757stda %f32, [%i2 + 0 ] %asi
30758
30759P2598: !_MEMBAR (FP)
30760membar #StoreLoad
30761
30762P2599: !_ST_BINIT [6] (maybe <- 0x10000df) (Int)
30763wr %g0, 0xe2, %asi
30764sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
30765sub %i0, %i3, %i3
30766stwa %l4, [%i3 + 0] %asi
30767add %l4, 1, %l4
30768
30769P2600: !_MEMBAR (Int)
30770membar #StoreLoad
30771
30772P2601: !_LD [20] (Int)
30773sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
30774sub %i0, %i2, %i2
30775lduw [%i2 + 12], %o4
30776! move %o4(lower) -> %o4(upper)
30777sllx %o4, 32, %o4
30778
30779P2602: !_DWLD [19] (Int) (LE)
30780wr %g0, 0x88, %asi
30781ldxa [%i2 + 0] %asi, %l6
30782! move %l6(lower) -> %o4(lower)
30783srl %l6, 0, %l3
30784or %l3, %o4, %o4
30785!---- flushing int results buffer----
30786mov %o0, %l5
30787mov %o1, %l5
30788mov %o2, %l5
30789mov %o3, %l5
30790mov %o4, %l5
30791! move %l6(upper) -> %o0(upper)
30792or %l6, %g0, %o0
30793
30794P2603: !_ST [20] (maybe <- 0x408000c6) (FP)
30795! preparing store val #0, next val will be in f20
30796fmovs %f16, %f20
30797fadds %f16, %f17, %f16
30798st %f20, [%i2 + 12 ]
30799
30800P2604: !_CAS [21] (maybe <- 0x10000e0) (Int)
30801sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
30802sub %i0, %i3, %i3
30803lduw [%i3], %l3
30804mov %l3, %l6
30805! move %l6(lower) -> %o0(lower)
30806srlx %o0, 32, %o0
30807sllx %o0, 32, %o0
30808or %l6, %o0, %o0
30809mov %l4, %o1
30810cas [%i3], %l6, %o1
30811! move %o1(lower) -> %o1(upper)
30812sllx %o1, 32, %o1
30813add %l4, 1, %l4
30814
30815P2605: !_LD [23] (Int) (LE)
30816wr %g0, 0x88, %asi
30817lduwa [%i3 + 12] %asi, %l7
30818! move %l7(lower) -> %o1(lower)
30819or %l7, %o1, %o1
30820
30821P2606: !_DWST_BINIT [22] (maybe <- 0x10000e1) (Int)
30822wr %g0, 0xe2, %asi
30823sllx %l4, 32, %o5
30824add %l4, 1, %l4
30825or %o5, %l4, %o5
30826stxa %o5, [%i3 + 0] %asi
30827add %l4, 1, %l4
30828
30829P2607: !_MEMBAR (Int) (CBR)
30830membar #StoreLoad
30831
30832! cbranch
30833andcc %l0, 1, %g0
30834be,pn %xcc, TARGET2607
30835nop
30836RET2607:
30837
30838! lfsr step begin
30839srlx %l0, 1, %l7
30840xnor %l7, %l0, %l7
30841sllx %l7, 63, %l7
30842or %l7, %l0, %l0
30843srlx %l0, 1, %l0
30844
30845
30846P2608: !_SWAP [7] (maybe <- 0x10000e3) (Int)
30847sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
30848sub %i0, %i2, %i2
30849mov %l4, %o2
30850swap [%i2 + 4], %o2
30851! move %o2(lower) -> %o2(upper)
30852sllx %o2, 32, %o2
30853add %l4, 1, %l4
30854
30855P2609: !_LD [9] (Int)
30856sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
30857add %i0, %i3, %i3
30858lduw [%i3 + 0], %o5
30859! move %o5(lower) -> %o2(lower)
30860or %o5, %o2, %o2
30861
30862P2610: !_CASX [10] (maybe <- 0x10000e4) (Int)
30863ldx [%i3], %o3
30864! move %o3(upper) -> %o3(upper)
30865! move %o3(lower) -> %o3(lower)
30866mov %o3, %l3
30867sllx %l4, 32, %o4
30868add %l4, 1, %l4
30869or %l4, %o4, %o4
30870casx [%i3], %l3, %o4
30871! move %o4(upper) -> %o4(upper)
30872! move %o4(lower) -> %o4(lower)
30873!---- flushing int results buffer----
30874mov %o0, %l5
30875mov %o1, %l5
30876mov %o2, %l5
30877mov %o3, %l5
30878mov %o4, %l5
30879add %l4, 1, %l4
30880
30881P2611: !_ST [14] (maybe <- 0x10000e6) (Int)
30882sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
30883sub %i0, %i2, %i2
30884stw %l4, [%i2 + 12 ]
30885add %l4, 1, %l4
30886
30887P2612: !_LDD [20] (Int)
30888sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
30889sub %i0, %i3, %i3
30890ldd [%i3 + 8], %l6
30891! move %l7(lower) -> %o0(upper)
30892sllx %l7, 32, %o0
30893
30894P2613: !_LDD [13] (Int)
30895ldd [%i2 + 0], %l6
30896! move %l6(lower) -> %o0(lower)
30897or %l6, %o0, %o0
30898! move %l7(lower) -> %o1(upper)
30899sllx %l7, 32, %o1
30900
30901P2614: !_CASX [5] (maybe <- 0x10000e7) (Int)
30902add %i1, 8, %l6
30903ldx [%l6], %o5
30904! move %o5(upper) -> %o1(lower)
30905srlx %o5, 32, %l3
30906or %l3, %o1, %o1
30907! move %o5(lower) -> %o2(upper)
30908sllx %o5, 32, %o2
30909mov %o5, %l3
30910mov %l4, %o5
30911casx [%l6], %l3, %o5
30912! move %o5(upper) -> %o2(lower)
30913srlx %o5, 32, %l3
30914or %l3, %o2, %o2
30915! move %o5(lower) -> %o3(upper)
30916sllx %o5, 32, %o3
30917add %l4, 1, %l4
30918
30919P2615: !_CASX [14] (maybe <- 0x10000e8) (Int)
30920add %i2, 8, %l6
30921ldx [%l6], %o5
30922! move %o5(upper) -> %o3(lower)
30923srlx %o5, 32, %l3
30924or %l3, %o3, %o3
30925! move %o5(lower) -> %o4(upper)
30926sllx %o5, 32, %o4
30927mov %o5, %l3
30928mov %l4, %o5
30929casx [%l6], %l3, %o5
30930! move %o5(upper) -> %o4(lower)
30931srlx %o5, 32, %l3
30932or %l3, %o4, %o4
30933!---- flushing int results buffer----
30934mov %o0, %l5
30935mov %o1, %l5
30936mov %o2, %l5
30937mov %o3, %l5
30938mov %o4, %l5
30939! move %o5(lower) -> %o0(upper)
30940sllx %o5, 32, %o0
30941add %l4, 1, %l4
30942
30943P2616: !_CASX [0] (maybe <- 0x10000e9) (Int)
30944ldx [%i0], %o5
30945! move %o5(upper) -> %o0(lower)
30946srlx %o5, 32, %l3
30947or %l3, %o0, %o0
30948! move %o5(lower) -> %o1(upper)
30949sllx %o5, 32, %o1
30950mov %o5, %l3
30951sllx %l4, 32, %o5
30952add %l4, 1, %l4
30953or %l4, %o5, %o5
30954casx [%i0], %l3, %o5
30955! move %o5(upper) -> %o1(lower)
30956srlx %o5, 32, %l3
30957or %l3, %o1, %o1
30958! move %o5(lower) -> %o2(upper)
30959sllx %o5, 32, %o2
30960add %l4, 1, %l4
30961
30962P2617: !_MEMBAR (FP)
30963membar #StoreLoad
30964
30965P2618: !_BLD [19] (FP)
30966wr %g0, 0xf0, %asi
30967ldda [%i3 + 0] %asi, %f32
30968membar #Sync
30969! 3 addresses covered
30970fmovd %f32, %f18
30971fmovs %f18, %f7
30972fmovs %f19, %f8
30973fmovd %f34, %f18
30974fmovs %f19, %f9
30975
30976P2619: !_MEMBAR (FP)
30977
30978P2620: !_PREFETCH [18] (Int)
30979prefetch [%i3 + 0], 1
30980
30981P2621: !_ST [12] (maybe <- 0x10000eb) (Int) (CBR)
30982stw %l4, [%i2 + 0 ]
30983add %l4, 1, %l4
30984
30985! cbranch
30986andcc %l0, 1, %g0
30987be,pn %xcc, TARGET2621
30988nop
30989RET2621:
30990
30991! lfsr step begin
30992srlx %l0, 1, %o5
30993xnor %o5, %l0, %o5
30994sllx %o5, 63, %o5
30995or %o5, %l0, %l0
30996srlx %l0, 1, %l0
30997
30998
30999P2622: !_ST_BINIT [5] (maybe <- 0x10000ec) (Int) (CBR)
31000wr %g0, 0xe2, %asi
31001stwa %l4, [%i1 + 12] %asi
31002add %l4, 1, %l4
31003
31004! cbranch
31005andcc %l0, 1, %g0
31006be,pt %xcc, TARGET2622
31007nop
31008RET2622:
31009
31010! lfsr step begin
31011srlx %l0, 1, %o5
31012xnor %o5, %l0, %o5
31013sllx %o5, 63, %o5
31014or %o5, %l0, %l0
31015srlx %l0, 1, %l0
31016
31017
31018P2623: !_MEMBAR (Int)
31019
31020P2624: !_BST [4] (maybe <- 0x408000c7) (FP)
31021wr %g0, 0xf0, %asi
31022! preparing store val #0, next val will be in f32
31023fmovs %f16, %f20
31024fadds %f16, %f17, %f16
31025! preparing store val #1, next val will be in f33
31026fmovs %f16, %f21
31027fadds %f16, %f17, %f16
31028! preparing store val #2, next val will be in f35
31029fmovd %f20, %f32
31030fmovs %f16, %f21
31031fadds %f16, %f17, %f16
31032fmovd %f20, %f34
31033membar #Sync
31034stda %f32, [%i1 + 0 ] %asi
31035
31036P2625: !_MEMBAR (FP) (CBR)
31037membar #StoreLoad
31038
31039! cbranch
31040andcc %l0, 1, %g0
31041be,pn %xcc, TARGET2625
31042nop
31043RET2625:
31044
31045! lfsr step begin
31046srlx %l0, 1, %o5
31047xnor %o5, %l0, %o5
31048sllx %o5, 63, %o5
31049or %o5, %l0, %l0
31050srlx %l0, 1, %l0
31051
31052
31053P2626: !_DWST [7] (maybe <- 0x10000ed) (Int)
31054sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
31055sub %i0, %i2, %i2
31056sllx %l4, 32, %l3
31057add %l4, 1, %l4
31058or %l3, %l4, %l3
31059stx %l3, [%i2 + 0]
31060add %l4, 1, %l4
31061
31062P2627: !_SWAP [23] (maybe <- 0x10000ef) (Int)
31063sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
31064sub %i0, %i3, %i3
31065mov %l4, %l6
31066swap [%i3 + 12], %l6
31067! move %l6(lower) -> %o2(lower)
31068srl %l6, 0, %o5
31069or %o5, %o2, %o2
31070add %l4, 1, %l4
31071
31072P2628: !_ST [12] (maybe <- 0x10000f0) (Int)
31073sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
31074sub %i0, %i2, %i2
31075stw %l4, [%i2 + 0 ]
31076add %l4, 1, %l4
31077
31078P2629: !_LD [9] (Int)
31079sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
31080add %i0, %i3, %i3
31081lduw [%i3 + 0], %o3
31082! move %o3(lower) -> %o3(upper)
31083sllx %o3, 32, %o3
31084
31085P2630: !_MEMBAR (FP)
31086membar #StoreLoad
31087
31088P2631: !_BLD [17] (FP)
31089wr %g0, 0xf0, %asi
31090sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
31091add %i0, %i2, %i2
31092ldda [%i2 + 0] %asi, %f32
31093membar #Sync
31094! 3 addresses covered
31095fmovd %f32, %f10
31096fmovd %f34, %f18
31097fmovs %f19, %f12
31098
31099P2632: !_MEMBAR (FP)
31100
31101P2633: !_BLD [12] (FP)
31102wr %g0, 0xf0, %asi
31103sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
31104sub %i0, %i3, %i3
31105ldda [%i3 + 0] %asi, %f32
31106membar #Sync
31107! 3 addresses covered
31108fmovd %f32, %f18
31109fmovs %f18, %f13
31110fmovs %f19, %f14
31111fmovd %f34, %f18
31112fmovs %f19, %f15
31113!---- flushing fp results buffer to %f30 ----
31114fmovd %f0, %f30
31115fmovd %f2, %f30
31116fmovd %f4, %f30
31117fmovd %f6, %f30
31118fmovd %f8, %f30
31119fmovd %f10, %f30
31120fmovd %f12, %f30
31121fmovd %f14, %f30
31122!--
31123
31124P2634: !_MEMBAR (FP)
31125
31126P2635: !_CAS [21] (maybe <- 0x10000f1) (Int)
31127sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
31128sub %i0, %i2, %i2
31129lduw [%i2], %l7
31130mov %l7, %o5
31131! move %o5(lower) -> %o3(lower)
31132or %o5, %o3, %o3
31133mov %l4, %o4
31134cas [%i2], %o5, %o4
31135! move %o4(lower) -> %o4(upper)
31136sllx %o4, 32, %o4
31137add %l4, 1, %l4
31138
31139P2636: !_CASX [14] (maybe <- 0x10000f2) (Int)
31140add %i3, 8, %l3
31141ldx [%l3], %l7
31142! move %l7(upper) -> %o4(lower)
31143srlx %l7, 32, %o5
31144or %o5, %o4, %o4
31145!---- flushing int results buffer----
31146mov %o0, %l5
31147mov %o1, %l5
31148mov %o2, %l5
31149mov %o3, %l5
31150mov %o4, %l5
31151! move %l7(lower) -> %o0(upper)
31152sllx %l7, 32, %o0
31153mov %l7, %o5
31154mov %l4, %l7
31155casx [%l3], %o5, %l7
31156! move %l7(upper) -> %o0(lower)
31157srlx %l7, 32, %o5
31158or %o5, %o0, %o0
31159! move %l7(lower) -> %o1(upper)
31160sllx %l7, 32, %o1
31161add %l4, 1, %l4
31162
31163P2637: !_LDD [6] (Int) (Branch target of P2621)
31164sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
31165sub %i0, %i3, %i3
31166ldd [%i3 + 0], %l6
31167! move %l6(lower) -> %o1(lower)
31168or %l6, %o1, %o1
31169! move %l7(lower) -> %o2(upper)
31170sllx %l7, 32, %o2
31171ba P2638
31172nop
31173
31174TARGET2621:
31175ba RET2621
31176nop
31177
31178
31179P2638: !_LD [17] (Int)
31180sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
31181add %i0, %i2, %i2
31182lduw [%i2 + 12], %l6
31183! move %l6(lower) -> %o2(lower)
31184or %l6, %o2, %o2
31185
31186P2639: !_ST [17] (maybe <- 0x10000f3) (Int) (Branch target of P2607)
31187stw %l4, [%i2 + 12 ]
31188add %l4, 1, %l4
31189ba P2640
31190nop
31191
31192TARGET2607:
31193ba RET2607
31194nop
31195
31196
31197P2640: !_MEMBAR (FP)
31198membar #StoreLoad
31199
31200P2641: !_BLD [7] (FP)
31201wr %g0, 0xf0, %asi
31202ldda [%i3 + 0] %asi, %f0
31203membar #Sync
31204! 3 addresses covered
31205fmovs %f3, %f2
31206
31207P2642: !_MEMBAR (FP)
31208
31209P2643: !_DWST [15] (maybe <- 0x10000f4) (Int)
31210sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
31211sub %i0, %i3, %i3
31212sllx %l4, 32, %l7
31213add %l4, 1, %l4
31214or %l7, %l4, %l7
31215stx %l7, [%i3 + 0]
31216add %l4, 1, %l4
31217
31218P2644: !_LD [16] (Int)
31219lduw [%i3 + 4], %o3
31220! move %o3(lower) -> %o3(upper)
31221sllx %o3, 32, %o3
31222
31223P2645: !_MEMBAR (FP)
31224
31225P2646: !_BST [22] (maybe <- 0x408000ca) (FP)
31226wr %g0, 0xf0, %asi
31227sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
31228sub %i0, %i2, %i2
31229! preparing store val #0, next val will be in f32
31230fmovs %f16, %f20
31231fadds %f16, %f17, %f16
31232! preparing store val #1, next val will be in f33
31233fmovs %f16, %f21
31234fadds %f16, %f17, %f16
31235! preparing store val #2, next val will be in f35
31236fmovd %f20, %f32
31237fmovs %f16, %f21
31238fadds %f16, %f17, %f16
31239fmovd %f20, %f34
31240membar #Sync
31241stda %f32, [%i2 + 0 ] %asi
31242
31243P2647: !_MEMBAR (FP)
31244membar #StoreLoad
31245
31246P2648: !_PREFETCH [22] (Int)
31247prefetch [%i2 + 4], 26
31248
31249P2649: !_MEMBAR (FP)
31250
31251P2650: !_BSTC [9] (maybe <- 0x408000cd) (FP)
31252wr %g0, 0xe0, %asi
31253sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
31254add %i0, %i3, %i3
31255! preparing store val #0, next val will be in f32
31256fmovs %f16, %f20
31257fadds %f16, %f17, %f16
31258! preparing store val #1, next val will be in f33
31259fmovs %f16, %f21
31260fadds %f16, %f17, %f16
31261! preparing store val #2, next val will be in f35
31262fmovd %f20, %f32
31263fmovs %f16, %f21
31264fadds %f16, %f17, %f16
31265fmovd %f20, %f34
31266membar #Sync
31267stda %f32, [%i3 + 0 ] %asi
31268
31269P2651: !_MEMBAR (FP)
31270membar #StoreLoad
31271
31272P2652: !_CASX [4] (maybe <- 0x10000f6) (Int)
31273ldx [%i1], %l3
31274! move %l3(upper) -> %o3(lower)
31275srlx %l3, 32, %l6
31276or %l6, %o3, %o3
31277! move %l3(lower) -> %o4(upper)
31278sllx %l3, 32, %o4
31279mov %l3, %l6
31280sllx %l4, 32, %l3
31281add %l4, 1, %l4
31282or %l4, %l3, %l3
31283casx [%i1], %l6, %l3
31284! move %l3(upper) -> %o4(lower)
31285srlx %l3, 32, %l6
31286or %l6, %o4, %o4
31287!---- flushing int results buffer----
31288mov %o0, %l5
31289mov %o1, %l5
31290mov %o2, %l5
31291mov %o3, %l5
31292mov %o4, %l5
31293! move %l3(lower) -> %o0(upper)
31294sllx %l3, 32, %o0
31295add %l4, 1, %l4
31296
31297P2653: !_PREFETCH [2] (Int)
31298prefetch [%i0 + 12], 1
31299
31300P2654: !_CASX [8] (maybe <- 0x10000f8) (Int)
31301sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
31302sub %i0, %i2, %i2
31303add %i2, 8, %l7
31304ldx [%l7], %l3
31305! move %l3(upper) -> %o0(lower)
31306srlx %l3, 32, %l6
31307or %l6, %o0, %o0
31308! move %l3(lower) -> %o1(upper)
31309sllx %l3, 32, %o1
31310mov %l3, %l6
31311mov %l4, %l3
31312casx [%l7], %l6, %l3
31313! move %l3(upper) -> %o1(lower)
31314srlx %l3, 32, %l6
31315or %l6, %o1, %o1
31316! move %l3(lower) -> %o2(upper)
31317sllx %l3, 32, %o2
31318add %l4, 1, %l4
31319
31320P2655: !_SWAP [20] (maybe <- 0x10000f9) (Int) (LE)
31321wr %g0, 0x88, %asi
31322sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
31323sub %i0, %i3, %i3
31324mov %l4, %o5
31325! Change single-word-level endianess (big endian <-> little endian)
31326sethi %hi(0xff00ff00), %l6
31327or %l6, %lo(0xff00ff00), %l6
31328and %o5, %l6, %l7
31329srl %l7, 8, %l7
31330sll %o5, 8, %o5
31331and %o5, %l6, %o5
31332or %o5, %l7, %o5
31333srl %o5, 16, %l7
31334sll %o5, 16, %o5
31335srl %o5, 0, %o5
31336or %o5, %l7, %o5
31337swapa [%i3 + 12] %asi, %o5
31338! move %o5(lower) -> %o2(lower)
31339srl %o5, 0, %l6
31340or %l6, %o2, %o2
31341add %l4, 1, %l4
31342
31343P2656: !_DWLD [8] (Int)
31344ldx [%i2 + 8], %o3
31345! move %o3(lower) -> %o3(upper)
31346sllx %o3, 32, %o3
31347
31348P2657: !_CASX [7] (maybe <- 0x10000fa) (Int)
31349ldx [%i2], %l6
31350! move %l6(upper) -> %o3(lower)
31351srlx %l6, 32, %l7
31352or %l7, %o3, %o3
31353! move %l6(lower) -> %o4(upper)
31354sllx %l6, 32, %o4
31355mov %l6, %l7
31356sllx %l4, 32, %l6
31357add %l4, 1, %l4
31358or %l4, %l6, %l6
31359casx [%i2], %l7, %l6
31360! move %l6(upper) -> %o4(lower)
31361srlx %l6, 32, %l7
31362or %l7, %o4, %o4
31363!---- flushing int results buffer----
31364mov %o0, %l5
31365mov %o1, %l5
31366mov %o2, %l5
31367mov %o3, %l5
31368mov %o4, %l5
31369! move %l6(lower) -> %o0(upper)
31370sllx %l6, 32, %o0
31371add %l4, 1, %l4
31372
31373P2658: !_ST [15] (maybe <- 0x10000fc) (Int)
31374sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
31375sub %i0, %i2, %i2
31376stw %l4, [%i2 + 0 ]
31377add %l4, 1, %l4
31378
31379P2659: !_MEMBAR (FP)
31380membar #StoreLoad
31381
31382P2660: !_BLD [14] (FP)
31383wr %g0, 0xf0, %asi
31384sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
31385sub %i0, %i3, %i3
31386ldda [%i3 + 0] %asi, %f32
31387membar #Sync
31388! 3 addresses covered
31389fmovd %f32, %f18
31390fmovs %f18, %f3
31391fmovs %f19, %f4
31392fmovd %f34, %f18
31393fmovs %f19, %f5
31394
31395P2661: !_MEMBAR (FP)
31396
31397P2662: !_BLD [10] (FP)
31398wr %g0, 0xf0, %asi
31399sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
31400add %i0, %i2, %i2
31401ldda [%i2 + 0] %asi, %f32
31402membar #Sync
31403! 3 addresses covered
31404fmovd %f32, %f6
31405fmovd %f34, %f18
31406fmovs %f19, %f8
31407
31408P2663: !_MEMBAR (FP)
31409
31410P2664: !_CAS [15] (maybe <- 0x10000fd) (Int)
31411sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
31412sub %i0, %i3, %i3
31413lduw [%i3], %l3
31414mov %l3, %l6
31415! move %l6(lower) -> %o0(lower)
31416or %l6, %o0, %o0
31417mov %l4, %o1
31418cas [%i3], %l6, %o1
31419! move %o1(lower) -> %o1(upper)
31420sllx %o1, 32, %o1
31421add %l4, 1, %l4
31422
31423P2665: !_DWST_BINIT [21] (maybe <- 0x10000fe) (Int)
31424wr %g0, 0xe2, %asi
31425sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
31426sub %i0, %i2, %i2
31427sllx %l4, 32, %l6
31428add %l4, 1, %l4
31429or %l6, %l4, %l6
31430stxa %l6, [%i2 + 0] %asi
31431add %l4, 1, %l4
31432
31433P2666: !_MEMBAR (Int)
31434membar #StoreLoad
31435
31436P2667: !_DWST [17] (maybe <- 0x1000100) (Int)
31437mov %l4, %l3
31438stx %l3, [%i3 + 8]
31439add %l4, 1, %l4
31440
31441P2668: !_PREFETCH [7] (Int)
31442sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
31443sub %i0, %i3, %i3
31444prefetch [%i3 + 4], 20
31445
31446P2669: !_MEMBAR (FP)
31447
31448P2670: !_BSTC [20] (maybe <- 0x408000d0) (FP)
31449wr %g0, 0xe0, %asi
31450sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
31451sub %i0, %i2, %i2
31452! preparing store val #0, next val will be in f32
31453fmovs %f16, %f20
31454fadds %f16, %f17, %f16
31455! preparing store val #1, next val will be in f33
31456fmovs %f16, %f21
31457fadds %f16, %f17, %f16
31458! preparing store val #2, next val will be in f35
31459fmovd %f20, %f32
31460fmovs %f16, %f21
31461fadds %f16, %f17, %f16
31462fmovd %f20, %f34
31463membar #Sync
31464stda %f32, [%i2 + 0 ] %asi
31465
31466P2671: !_MEMBAR (FP)
31467membar #StoreLoad
31468
31469P2672: !_SWAP [14] (maybe <- 0x1000101) (Int)
31470sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
31471sub %i0, %i3, %i3
31472mov %l4, %l3
31473swap [%i3 + 12], %l3
31474! move %l3(lower) -> %o1(lower)
31475srl %l3, 0, %l7
31476or %l7, %o1, %o1
31477add %l4, 1, %l4
31478
31479P2673: !_CAS [19] (maybe <- 0x1000102) (Int)
31480add %i2, 4, %l7
31481lduw [%l7], %o2
31482mov %o2, %l6
31483! move %l6(lower) -> %o2(upper)
31484sllx %l6, 32, %o2
31485mov %l4, %l3
31486cas [%l7], %l6, %l3
31487! move %l3(lower) -> %o2(lower)
31488srl %l3, 0, %l6
31489or %l6, %o2, %o2
31490add %l4, 1, %l4
31491
31492P2674: !_LDD [18] (Int)
31493ldd [%i2 + 0], %l6
31494! move %l6(lower) -> %o3(upper)
31495sllx %l6, 32, %o3
31496! move %l7(lower) -> %o3(lower)
31497or %l7, %o3, %o3
31498
31499P2675: !_DWST_BINIT [23] (maybe <- 0x1000103) (Int)
31500wr %g0, 0xe2, %asi
31501sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
31502sub %i0, %i2, %i2
31503mov %l4, %l3
31504stxa %l3, [%i2 + 8] %asi
31505add %l4, 1, %l4
31506
31507P2676: !_MEMBAR (Int)
31508membar #StoreLoad
31509
31510P2677: !_BLD [10] (FP)
31511wr %g0, 0xf0, %asi
31512sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
31513add %i0, %i3, %i3
31514ldda [%i3 + 0] %asi, %f32
31515membar #Sync
31516! 3 addresses covered
31517fmovd %f32, %f18
31518fmovs %f18, %f9
31519fmovs %f19, %f10
31520fmovd %f34, %f18
31521fmovs %f19, %f11
31522
31523P2678: !_MEMBAR (FP)
31524
31525P2679: !_REPLACEMENT [6] (Int)
31526sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
31527sub %i0, %i2, %i2
31528sethi %hi(0x20000), %o5
31529ld [%i2+0], %l6
31530st %l6, [%i2+0]
31531add %i2, %o5, %l3
31532ld [%l3+0], %l6
31533st %l6, [%l3+0]
31534add %l3, %o5, %l3
31535ld [%l3+0], %l6
31536st %l6, [%l3+0]
31537add %l3, %o5, %l3
31538ld [%l3+0], %l6
31539st %l6, [%l3+0]
31540add %l3, %o5, %l3
31541ld [%l3+0], %l6
31542st %l6, [%l3+0]
31543add %l3, %o5, %l3
31544ld [%l3+0], %l6
31545st %l6, [%l3+0]
31546add %l3, %o5, %l3
31547ld [%l3+0], %l6
31548st %l6, [%l3+0]
31549add %l3, %o5, %l3
31550ld [%l3+0], %l6
31551st %l6, [%l3+0]
31552
31553P2680: !_REPLACEMENT [13] (Int)
31554sethi %hi(0x20000), %l7
31555ld [%i2+4], %l3
31556st %l3, [%i2+4]
31557add %i2, %l7, %o5
31558ld [%o5+4], %l3
31559st %l3, [%o5+4]
31560add %o5, %l7, %o5
31561ld [%o5+4], %l3
31562st %l3, [%o5+4]
31563add %o5, %l7, %o5
31564ld [%o5+4], %l3
31565st %l3, [%o5+4]
31566add %o5, %l7, %o5
31567ld [%o5+4], %l3
31568st %l3, [%o5+4]
31569add %o5, %l7, %o5
31570ld [%o5+4], %l3
31571st %l3, [%o5+4]
31572add %o5, %l7, %o5
31573ld [%o5+4], %l3
31574st %l3, [%o5+4]
31575add %o5, %l7, %o5
31576ld [%o5+4], %l3
31577st %l3, [%o5+4]
31578
31579P2681: !_REPLACEMENT [20] (Int)
31580sethi %hi(0x20000), %l6
31581ld [%i2+12], %o5
31582st %o5, [%i2+12]
31583add %i2, %l6, %l7
31584ld [%l7+12], %o5
31585st %o5, [%l7+12]
31586add %l7, %l6, %l7
31587ld [%l7+12], %o5
31588st %o5, [%l7+12]
31589add %l7, %l6, %l7
31590ld [%l7+12], %o5
31591st %o5, [%l7+12]
31592add %l7, %l6, %l7
31593ld [%l7+12], %o5
31594st %o5, [%l7+12]
31595add %l7, %l6, %l7
31596ld [%l7+12], %o5
31597st %o5, [%l7+12]
31598add %l7, %l6, %l7
31599ld [%l7+12], %o5
31600st %o5, [%l7+12]
31601add %l7, %l6, %l7
31602ld [%l7+12], %o5
31603st %o5, [%l7+12]
31604
31605P2682: !_PREFETCH [19] (Int)
31606sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
31607sub %i0, %i3, %i3
31608prefetch [%i3 + 4], 1
31609
31610P2683: !_MEMBAR (FP)
31611membar #StoreLoad
31612
31613P2684: !_BLD [15] (FP)
31614wr %g0, 0xf0, %asi
31615sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
31616sub %i0, %i2, %i2
31617ldda [%i2 + 0] %asi, %f32
31618membar #Sync
31619! 3 addresses covered
31620fmovd %f32, %f12
31621fmovd %f34, %f18
31622fmovs %f19, %f14
31623
31624P2685: !_MEMBAR (FP)
31625
31626P2686: !_SWAP [22] (maybe <- 0x1000104) (Int)
31627sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
31628sub %i0, %i3, %i3
31629mov %l4, %o4
31630swap [%i3 + 4], %o4
31631! move %o4(lower) -> %o4(upper)
31632sllx %o4, 32, %o4
31633add %l4, 1, %l4
31634
31635P2687: !_PREFETCH [21] (Int)
31636prefetch [%i3 + 0], 4
31637
31638P2688: !_CASX [12] (maybe <- 0x1000105) (Int)
31639sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
31640sub %i0, %i2, %i2
31641ldx [%i2], %l7
31642! move %l7(upper) -> %o4(lower)
31643srlx %l7, 32, %o5
31644or %o5, %o4, %o4
31645!---- flushing int results buffer----
31646mov %o0, %l5
31647mov %o1, %l5
31648mov %o2, %l5
31649mov %o3, %l5
31650mov %o4, %l5
31651! move %l7(lower) -> %o0(upper)
31652sllx %l7, 32, %o0
31653mov %l7, %o5
31654sllx %l4, 32, %l7
31655add %l4, 1, %l4
31656or %l4, %l7, %l7
31657casx [%i2], %o5, %l7
31658! move %l7(upper) -> %o0(lower)
31659srlx %l7, 32, %o5
31660or %o5, %o0, %o0
31661! move %l7(lower) -> %o1(upper)
31662sllx %l7, 32, %o1
31663add %l4, 1, %l4
31664
31665P2689: !_ST [23] (maybe <- 0x1000107) (Int)
31666stw %l4, [%i3 + 12 ]
31667add %l4, 1, %l4
31668
31669P2690: !_CASX [13] (maybe <- 0x1000108) (Int) (CBR) (Branch target of P2520)
31670ldx [%i2], %l6
31671! move %l6(upper) -> %o1(lower)
31672srlx %l6, 32, %l7
31673or %l7, %o1, %o1
31674! move %l6(lower) -> %o2(upper)
31675sllx %l6, 32, %o2
31676mov %l6, %l7
31677sllx %l4, 32, %l6
31678add %l4, 1, %l4
31679or %l4, %l6, %l6
31680casx [%i2], %l7, %l6
31681! move %l6(upper) -> %o2(lower)
31682srlx %l6, 32, %l7
31683or %l7, %o2, %o2
31684! move %l6(lower) -> %o3(upper)
31685sllx %l6, 32, %o3
31686add %l4, 1, %l4
31687
31688! cbranch
31689andcc %l0, 1, %g0
31690be,pt %xcc, TARGET2690
31691nop
31692RET2690:
31693
31694! lfsr step begin
31695srlx %l0, 1, %l7
31696xnor %l7, %l0, %l7
31697sllx %l7, 63, %l7
31698or %l7, %l0, %l0
31699srlx %l0, 1, %l0
31700
31701ba P2691
31702nop
31703
31704TARGET2520:
31705ba RET2520
31706nop
31707
31708
31709P2691: !_MEMBAR (FP)
31710
31711P2692: !_BSTC [9] (maybe <- 0x408000d3) (FP)
31712wr %g0, 0xe0, %asi
31713sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
31714add %i0, %i3, %i3
31715! preparing store val #0, next val will be in f32
31716fmovs %f16, %f20
31717fadds %f16, %f17, %f16
31718! preparing store val #1, next val will be in f33
31719fmovs %f16, %f21
31720fadds %f16, %f17, %f16
31721! preparing store val #2, next val will be in f35
31722fmovd %f20, %f32
31723fmovs %f16, %f21
31724fadds %f16, %f17, %f16
31725fmovd %f20, %f34
31726membar #Sync
31727stda %f32, [%i3 + 0 ] %asi
31728
31729P2693: !_MEMBAR (FP)
31730
31731P2694: !_BSTC [11] (maybe <- 0x408000d6) (FP)
31732wr %g0, 0xe0, %asi
31733! preparing store val #0, next val will be in f32
31734fmovs %f16, %f20
31735fadds %f16, %f17, %f16
31736! preparing store val #1, next val will be in f33
31737fmovs %f16, %f21
31738fadds %f16, %f17, %f16
31739! preparing store val #2, next val will be in f35
31740fmovd %f20, %f32
31741fmovs %f16, %f21
31742fadds %f16, %f17, %f16
31743fmovd %f20, %f34
31744membar #Sync
31745stda %f32, [%i3 + 0 ] %asi
31746
31747P2695: !_MEMBAR (FP) (Branch target of P2584)
31748membar #StoreLoad
31749ba P2696
31750nop
31751
31752TARGET2584:
31753ba RET2584
31754nop
31755
31756
31757P2696: !_ST_BINIT [0] (maybe <- 0x100010a) (Int)
31758wr %g0, 0xe2, %asi
31759stwa %l4, [%i0 + 0] %asi
31760add %l4, 1, %l4
31761
31762P2697: !_MEMBAR (Int)
31763membar #StoreLoad
31764
31765P2698: !_REPLACEMENT [1] (Int)
31766sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
31767sub %i0, %i2, %i2
31768sethi %hi(0x20000), %l3
31769ld [%i2+4], %l7
31770st %l7, [%i2+4]
31771add %i2, %l3, %l6
31772ld [%l6+4], %l7
31773st %l7, [%l6+4]
31774add %l6, %l3, %l6
31775ld [%l6+4], %l7
31776st %l7, [%l6+4]
31777add %l6, %l3, %l6
31778ld [%l6+4], %l7
31779st %l7, [%l6+4]
31780add %l6, %l3, %l6
31781ld [%l6+4], %l7
31782st %l7, [%l6+4]
31783add %l6, %l3, %l6
31784ld [%l6+4], %l7
31785st %l7, [%l6+4]
31786add %l6, %l3, %l6
31787ld [%l6+4], %l7
31788st %l7, [%l6+4]
31789add %l6, %l3, %l6
31790ld [%l6+4], %l7
31791st %l7, [%l6+4]
31792
31793P2699: !_CASX [21] (maybe <- 0x100010b) (Int)
31794sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
31795sub %i0, %i3, %i3
31796ldx [%i3], %l7
31797! move %l7(upper) -> %o3(lower)
31798srlx %l7, 32, %o5
31799or %o5, %o3, %o3
31800! move %l7(lower) -> %o4(upper)
31801sllx %l7, 32, %o4
31802mov %l7, %o5
31803sllx %l4, 32, %l7
31804add %l4, 1, %l4
31805or %l4, %l7, %l7
31806casx [%i3], %o5, %l7
31807! move %l7(upper) -> %o4(lower)
31808srlx %l7, 32, %o5
31809or %o5, %o4, %o4
31810!---- flushing int results buffer----
31811mov %o0, %l5
31812mov %o1, %l5
31813mov %o2, %l5
31814mov %o3, %l5
31815mov %o4, %l5
31816! move %l7(lower) -> %o0(upper)
31817sllx %l7, 32, %o0
31818add %l4, 1, %l4
31819
31820P2700: !_LD [1] (Int)
31821lduw [%i0 + 4], %l3
31822! move %l3(lower) -> %o0(lower)
31823or %l3, %o0, %o0
31824
31825P2701: !_LD [19] (Int)
31826sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
31827sub %i0, %i2, %i2
31828lduw [%i2 + 4], %o1
31829! move %o1(lower) -> %o1(upper)
31830sllx %o1, 32, %o1
31831
31832P2702: !_DWST_BINIT [4] (maybe <- 0x100010d) (Int)
31833wr %g0, 0xe2, %asi
31834sllx %l4, 32, %o5
31835add %l4, 1, %l4
31836or %o5, %l4, %o5
31837stxa %o5, [%i1 + 0] %asi
31838add %l4, 1, %l4
31839
31840P2703: !_MEMBAR (Int)
31841membar #StoreLoad
31842
31843P2704: !_PREFETCH [6] (Int)
31844sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
31845sub %i0, %i3, %i3
31846prefetch [%i3 + 0], 2
31847
31848P2705: !_REPLACEMENT [3] (Int)
31849sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
31850sub %i0, %i2, %i2
31851sethi %hi(0x20000), %l7
31852ld [%i2+0], %l3
31853st %l3, [%i2+0]
31854add %i2, %l7, %o5
31855ld [%o5+0], %l3
31856st %l3, [%o5+0]
31857add %o5, %l7, %o5
31858ld [%o5+0], %l3
31859st %l3, [%o5+0]
31860add %o5, %l7, %o5
31861ld [%o5+0], %l3
31862st %l3, [%o5+0]
31863add %o5, %l7, %o5
31864ld [%o5+0], %l3
31865st %l3, [%o5+0]
31866add %o5, %l7, %o5
31867ld [%o5+0], %l3
31868st %l3, [%o5+0]
31869add %o5, %l7, %o5
31870ld [%o5+0], %l3
31871st %l3, [%o5+0]
31872add %o5, %l7, %o5
31873ld [%o5+0], %l3
31874st %l3, [%o5+0]
31875
31876P2706: !_ST_BINIT [13] (maybe <- 0x100010f) (Int)
31877wr %g0, 0xe2, %asi
31878sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
31879sub %i0, %i3, %i3
31880stwa %l4, [%i3 + 4] %asi
31881add %l4, 1, %l4
31882
31883P2707: !_MEMBAR (Int)
31884membar #StoreLoad
31885
31886P2708: !_CASX [8] (maybe <- 0x1000110) (Int)
31887sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
31888sub %i0, %i2, %i2
31889add %i2, 8, %l7
31890ldx [%l7], %l3
31891! move %l3(upper) -> %o1(lower)
31892srlx %l3, 32, %l6
31893or %l6, %o1, %o1
31894! move %l3(lower) -> %o2(upper)
31895sllx %l3, 32, %o2
31896mov %l3, %l6
31897mov %l4, %l3
31898casx [%l7], %l6, %l3
31899! move %l3(upper) -> %o2(lower)
31900srlx %l3, 32, %l6
31901or %l6, %o2, %o2
31902! move %l3(lower) -> %o3(upper)
31903sllx %l3, 32, %o3
31904add %l4, 1, %l4
31905
31906P2709: !_CASX [4] (maybe <- 0x1000111) (Int)
31907ldx [%i1], %l3
31908! move %l3(upper) -> %o3(lower)
31909srlx %l3, 32, %l6
31910or %l6, %o3, %o3
31911! move %l3(lower) -> %o4(upper)
31912sllx %l3, 32, %o4
31913mov %l3, %l6
31914sllx %l4, 32, %l3
31915add %l4, 1, %l4
31916or %l4, %l3, %l3
31917casx [%i1], %l6, %l3
31918! move %l3(upper) -> %o4(lower)
31919srlx %l3, 32, %l6
31920or %l6, %o4, %o4
31921!---- flushing int results buffer----
31922mov %o0, %l5
31923mov %o1, %l5
31924mov %o2, %l5
31925mov %o3, %l5
31926mov %o4, %l5
31927! move %l3(lower) -> %o0(upper)
31928sllx %l3, 32, %o0
31929add %l4, 1, %l4
31930
31931P2710: !_DWST [22] (maybe <- 0x1000113) (Int)
31932sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
31933sub %i0, %i3, %i3
31934sllx %l4, 32, %l6
31935add %l4, 1, %l4
31936or %l6, %l4, %l6
31937stx %l6, [%i3 + 0]
31938add %l4, 1, %l4
31939
31940P2711: !_LDD [7] (Int)
31941ldd [%i2 + 0], %l6
31942! move %l6(lower) -> %o0(lower)
31943or %l6, %o0, %o0
31944! move %l7(lower) -> %o1(upper)
31945sllx %l7, 32, %o1
31946
31947P2712: !_LD [21] (Int)
31948lduw [%i3 + 0], %l6
31949! move %l6(lower) -> %o1(lower)
31950or %l6, %o1, %o1
31951
31952P2713: !_PREFETCH [12] (Int)
31953sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
31954sub %i0, %i2, %i2
31955prefetch [%i2 + 0], 16
31956
31957P2714: !_SWAP [23] (maybe <- 0x1000115) (Int)
31958mov %l4, %o2
31959swap [%i3 + 12], %o2
31960! move %o2(lower) -> %o2(upper)
31961sllx %o2, 32, %o2
31962add %l4, 1, %l4
31963
31964P2715: !_SWAP [5] (maybe <- 0x1000116) (Int)
31965mov %l4, %o5
31966swap [%i1 + 12], %o5
31967! move %o5(lower) -> %o2(lower)
31968srl %o5, 0, %l6
31969or %l6, %o2, %o2
31970add %l4, 1, %l4
31971
31972P2716: !_ST_BINIT [2] (maybe <- 0x1000117) (Int)
31973wr %g0, 0xe2, %asi
31974stwa %l4, [%i0 + 12] %asi
31975add %l4, 1, %l4
31976
31977P2717: !_MEMBAR (Int)
31978membar #StoreLoad
31979
31980P2718: !_SWAP [12] (maybe <- 0x1000118) (Int)
31981mov %l4, %o3
31982swap [%i2 + 0], %o3
31983! move %o3(lower) -> %o3(upper)
31984sllx %o3, 32, %o3
31985add %l4, 1, %l4
31986
31987P2719: !_ST_BINIT [20] (maybe <- 0x1000119) (Int)
31988wr %g0, 0xe2, %asi
31989sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
31990sub %i0, %i3, %i3
31991stwa %l4, [%i3 + 12] %asi
31992add %l4, 1, %l4
31993
31994P2720: !_MEMBAR (Int)
31995membar #StoreLoad
31996
31997P2721: !_DWST_BINIT [19] (maybe <- 0x100011a) (Int)
31998wr %g0, 0xe2, %asi
31999sllx %l4, 32, %l6
32000add %l4, 1, %l4
32001or %l6, %l4, %l6
32002stxa %l6, [%i3 + 0] %asi
32003add %l4, 1, %l4
32004
32005P2722: !_MEMBAR (Int)
32006membar #StoreLoad
32007
32008P2723: !_PREFETCH [23] (Int)
32009sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
32010sub %i0, %i2, %i2
32011prefetch [%i2 + 12], 2
32012
32013P2724: !_PREFETCH [13] (Int)
32014sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
32015sub %i0, %i3, %i3
32016prefetch [%i3 + 4], 3
32017
32018P2725: !_PREFETCH [16] (Int)
32019sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
32020sub %i0, %i2, %i2
32021prefetch [%i2 + 4], 0
32022
32023P2726: !_REPLACEMENT [1] (Int) (CBR)
32024sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
32025add %i0, %i3, %i3
32026sethi %hi(0x20000), %l3
32027ld [%i3+4], %l7
32028st %l7, [%i3+4]
32029add %i3, %l3, %l6
32030ld [%l6+4], %l7
32031st %l7, [%l6+4]
32032add %l6, %l3, %l6
32033ld [%l6+4], %l7
32034st %l7, [%l6+4]
32035add %l6, %l3, %l6
32036ld [%l6+4], %l7
32037st %l7, [%l6+4]
32038add %l6, %l3, %l6
32039ld [%l6+4], %l7
32040st %l7, [%l6+4]
32041add %l6, %l3, %l6
32042ld [%l6+4], %l7
32043st %l7, [%l6+4]
32044add %l6, %l3, %l6
32045ld [%l6+4], %l7
32046st %l7, [%l6+4]
32047add %l6, %l3, %l6
32048ld [%l6+4], %l7
32049st %l7, [%l6+4]
32050
32051! cbranch
32052andcc %l0, 1, %g0
32053be,pt %xcc, TARGET2726
32054nop
32055RET2726:
32056
32057! lfsr step begin
32058srlx %l0, 1, %o5
32059xnor %o5, %l0, %o5
32060sllx %o5, 63, %o5
32061or %o5, %l0, %l0
32062srlx %l0, 1, %l0
32063
32064
32065P2727: !_MEMBAR (FP)
32066membar #StoreLoad
32067
32068P2728: !_BLD [21] (FP) (CBR)
32069wr %g0, 0xf0, %asi
32070sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
32071sub %i0, %i2, %i2
32072ldda [%i2 + 0] %asi, %f32
32073membar #Sync
32074! 3 addresses covered
32075fmovd %f32, %f18
32076fmovs %f18, %f15
32077!---- flushing fp results buffer to %f30 ----
32078fmovd %f0, %f30
32079fmovd %f2, %f30
32080fmovd %f4, %f30
32081fmovd %f6, %f30
32082fmovd %f8, %f30
32083fmovd %f10, %f30
32084fmovd %f12, %f30
32085fmovd %f14, %f30
32086!--
32087fmovs %f19, %f0
32088fmovd %f34, %f18
32089fmovs %f19, %f1
32090
32091! cbranch
32092andcc %l0, 1, %g0
32093be,pt %xcc, TARGET2728
32094nop
32095RET2728:
32096
32097! lfsr step begin
32098srlx %l0, 1, %l3
32099xnor %l3, %l0, %l3
32100sllx %l3, 63, %l3
32101or %l3, %l0, %l0
32102srlx %l0, 1, %l0
32103
32104
32105P2729: !_MEMBAR (FP)
32106
32107P2730: !_ST_BINIT [19] (maybe <- 0x100011c) (Int)
32108wr %g0, 0xe2, %asi
32109sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
32110sub %i0, %i3, %i3
32111stwa %l4, [%i3 + 4] %asi
32112add %l4, 1, %l4
32113
32114P2731: !_MEMBAR (Int) (CBR)
32115membar #StoreLoad
32116
32117! cbranch
32118andcc %l0, 1, %g0
32119be,pt %xcc, TARGET2731
32120nop
32121RET2731:
32122
32123! lfsr step begin
32124srlx %l0, 1, %l3
32125xnor %l3, %l0, %l3
32126sllx %l3, 63, %l3
32127or %l3, %l0, %l0
32128srlx %l0, 1, %l0
32129
32130
32131P2732: !_ST_BINIT [1] (maybe <- 0x100011d) (Int)
32132wr %g0, 0xe2, %asi
32133stwa %l4, [%i0 + 4] %asi
32134add %l4, 1, %l4
32135
32136P2733: !_MEMBAR (Int)
32137
32138P2734: !_BST [8] (maybe <- 0x408000d9) (FP)
32139wr %g0, 0xf0, %asi
32140sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
32141sub %i0, %i2, %i2
32142! preparing store val #0, next val will be in f32
32143fmovs %f16, %f20
32144fadds %f16, %f17, %f16
32145! preparing store val #1, next val will be in f33
32146fmovs %f16, %f21
32147fadds %f16, %f17, %f16
32148! preparing store val #2, next val will be in f35
32149fmovd %f20, %f32
32150fmovs %f16, %f21
32151fadds %f16, %f17, %f16
32152fmovd %f20, %f34
32153membar #Sync
32154stda %f32, [%i2 + 0 ] %asi
32155
32156P2735: !_MEMBAR (FP)
32157membar #StoreLoad
32158
32159P2736: !_DWST [1] (maybe <- 0x100011e) (Int)
32160sllx %l4, 32, %o5
32161add %l4, 1, %l4
32162or %o5, %l4, %o5
32163stx %o5, [%i0 + 0]
32164add %l4, 1, %l4
32165
32166P2737: !_ST_BINIT [16] (maybe <- 0x1000120) (Int)
32167wr %g0, 0xe2, %asi
32168sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
32169sub %i0, %i3, %i3
32170stwa %l4, [%i3 + 4] %asi
32171add %l4, 1, %l4
32172
32173P2738: !_MEMBAR (Int)
32174membar #StoreLoad
32175
32176P2739: !_PREFETCH [9] (Int)
32177sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
32178add %i0, %i2, %i2
32179prefetch [%i2 + 0], 4
32180
32181P2740: !_PREFETCH [19] (Int)
32182sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
32183sub %i0, %i3, %i3
32184prefetch [%i3 + 4], 16
32185
32186P2741: !_DWST_BINIT [6] (maybe <- 0x1000121) (Int)
32187wr %g0, 0xe2, %asi
32188sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
32189sub %i0, %i2, %i2
32190sllx %l4, 32, %l6
32191add %l4, 1, %l4
32192or %l6, %l4, %l6
32193stxa %l6, [%i2 + 0] %asi
32194add %l4, 1, %l4
32195
32196P2742: !_MEMBAR (Int) (Branch target of P2268)
32197ba P2743
32198nop
32199
32200TARGET2268:
32201ba RET2268
32202nop
32203
32204
32205P2743: !_BST [4] (maybe <- 0x408000dc) (FP)
32206wr %g0, 0xf0, %asi
32207! preparing store val #0, next val will be in f32
32208fmovs %f16, %f20
32209fadds %f16, %f17, %f16
32210! preparing store val #1, next val will be in f33
32211fmovs %f16, %f21
32212fadds %f16, %f17, %f16
32213! preparing store val #2, next val will be in f35
32214fmovd %f20, %f32
32215fmovs %f16, %f21
32216fadds %f16, %f17, %f16
32217fmovd %f20, %f34
32218membar #Sync
32219stda %f32, [%i1 + 0 ] %asi
32220
32221P2744: !_MEMBAR (FP)
32222membar #StoreLoad
32223
32224P2745: !_PREFETCH [3] (Int)
32225prefetch [%i1 + 0], 3
32226
32227P2746: !_DWLD [10] (Int)
32228sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
32229add %i0, %i3, %i3
32230ldx [%i3 + 0], %l3
32231! move %l3(upper) -> %o3(lower)
32232srlx %l3, 32, %o5
32233or %o5, %o3, %o3
32234! move %l3(lower) -> %o4(upper)
32235sllx %l3, 32, %o4
32236
32237P2747: !_MEMBAR (FP)
32238
32239P2748: !_BSTC [23] (maybe <- 0x408000df) (FP)
32240wr %g0, 0xe0, %asi
32241sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
32242sub %i0, %i2, %i2
32243! preparing store val #0, next val will be in f32
32244fmovs %f16, %f20
32245fadds %f16, %f17, %f16
32246! preparing store val #1, next val will be in f33
32247fmovs %f16, %f21
32248fadds %f16, %f17, %f16
32249! preparing store val #2, next val will be in f35
32250fmovd %f20, %f32
32251fmovs %f16, %f21
32252fadds %f16, %f17, %f16
32253fmovd %f20, %f34
32254membar #Sync
32255stda %f32, [%i2 + 0 ] %asi
32256
32257P2749: !_MEMBAR (FP)
32258membar #StoreLoad
32259
32260P2750: !_DWLD [3] (Int) (Branch target of P2968)
32261ldx [%i1 + 0], %l6
32262! move %l6(upper) -> %o4(lower)
32263srlx %l6, 32, %l3
32264or %l3, %o4, %o4
32265!---- flushing int results buffer----
32266mov %o0, %l5
32267mov %o1, %l5
32268mov %o2, %l5
32269mov %o3, %l5
32270mov %o4, %l5
32271! move %l6(lower) -> %o0(upper)
32272sllx %l6, 32, %o0
32273ba P2751
32274nop
32275
32276TARGET2968:
32277ba RET2968
32278nop
32279
32280
32281P2751: !_SWAP [15] (maybe <- 0x1000123) (Int) (Branch target of P2324)
32282sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
32283sub %i0, %i3, %i3
32284mov %l4, %l3
32285swap [%i3 + 0], %l3
32286! move %l3(lower) -> %o0(lower)
32287srl %l3, 0, %l7
32288or %l7, %o0, %o0
32289add %l4, 1, %l4
32290ba P2752
32291nop
32292
32293TARGET2324:
32294ba RET2324
32295nop
32296
32297
32298P2752: !_PREFETCH [4] (Int)
32299prefetch [%i1 + 4], 0
32300
32301P2753: !_LD [11] (Int)
32302sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
32303add %i0, %i2, %i2
32304lduw [%i2 + 12], %o1
32305! move %o1(lower) -> %o1(upper)
32306sllx %o1, 32, %o1
32307
32308P2754: !_MEMBAR (FP)
32309membar #StoreLoad
32310
32311P2755: !_BLD [4] (FP) (CBR)
32312wr %g0, 0xf0, %asi
32313ldda [%i1 + 0] %asi, %f32
32314membar #Sync
32315! 3 addresses covered
32316fmovd %f32, %f2
32317fmovd %f34, %f18
32318fmovs %f19, %f4
32319
32320! cbranch
32321andcc %l0, 1, %g0
32322be,pt %xcc, TARGET2755
32323nop
32324RET2755:
32325
32326! lfsr step begin
32327srlx %l0, 1, %o5
32328xnor %o5, %l0, %o5
32329sllx %o5, 63, %o5
32330or %o5, %l0, %l0
32331srlx %l0, 1, %l0
32332
32333
32334P2756: !_MEMBAR (FP) (Branch target of P2153)
32335ba P2757
32336nop
32337
32338TARGET2153:
32339ba RET2153
32340nop
32341
32342
32343P2757: !_PREFETCH [5] (Int)
32344prefetch [%i1 + 12], 19
32345
32346P2758: !_MEMBAR (FP)
32347
32348P2759: !_BST [17] (maybe <- 0x408000e2) (FP)
32349wr %g0, 0xf0, %asi
32350! preparing store val #0, next val will be in f32
32351fmovs %f16, %f20
32352fadds %f16, %f17, %f16
32353! preparing store val #1, next val will be in f33
32354fmovs %f16, %f21
32355fadds %f16, %f17, %f16
32356! preparing store val #2, next val will be in f35
32357fmovd %f20, %f32
32358fmovs %f16, %f21
32359fadds %f16, %f17, %f16
32360fmovd %f20, %f34
32361membar #Sync
32362stda %f32, [%i3 + 0 ] %asi
32363
32364P2760: !_MEMBAR (FP)
32365membar #StoreLoad
32366
32367P2761: !_ST_BINIT [5] (maybe <- 0x1000124) (Int) (LE)
32368wr %g0, 0xea, %asi
32369! Change single-word-level endianess (big endian <-> little endian)
32370sethi %hi(0xff00ff00), %l3
32371or %l3, %lo(0xff00ff00), %l3
32372and %l4, %l3, %l6
32373srl %l6, 8, %l6
32374sll %l4, 8, %o5
32375and %o5, %l3, %o5
32376or %o5, %l6, %o5
32377srl %o5, 16, %l6
32378sll %o5, 16, %o5
32379srl %o5, 0, %o5
32380or %o5, %l6, %o5
32381stwa %o5, [%i1 + 12] %asi
32382add %l4, 1, %l4
32383
32384P2762: !_MEMBAR (Int) (LE)
32385membar #StoreLoad
32386
32387P2763: !_ST [12] (maybe <- 0x1000125) (Int)
32388sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
32389sub %i0, %i3, %i3
32390stw %l4, [%i3 + 0 ]
32391add %l4, 1, %l4
32392
32393P2764: !_MEMBAR (FP)
32394
32395P2765: !_BST [10] (maybe <- 0x408000e5) (FP)
32396wr %g0, 0xf0, %asi
32397! preparing store val #0, next val will be in f32
32398fmovs %f16, %f20
32399fadds %f16, %f17, %f16
32400! preparing store val #1, next val will be in f33
32401fmovs %f16, %f21
32402fadds %f16, %f17, %f16
32403! preparing store val #2, next val will be in f35
32404fmovd %f20, %f32
32405fmovs %f16, %f21
32406fadds %f16, %f17, %f16
32407fmovd %f20, %f34
32408membar #Sync
32409stda %f32, [%i2 + 0 ] %asi
32410
32411P2766: !_MEMBAR (FP) (CBR)
32412membar #StoreLoad
32413
32414! cbranch
32415andcc %l0, 1, %g0
32416be,pn %xcc, TARGET2766
32417nop
32418RET2766:
32419
32420! lfsr step begin
32421srlx %l0, 1, %l3
32422xnor %l3, %l0, %l3
32423sllx %l3, 63, %l3
32424or %l3, %l0, %l0
32425srlx %l0, 1, %l0
32426
32427
32428P2767: !_LDD [9] (Int)
32429ldd [%i2 + 0], %l6
32430! move %l6(lower) -> %o1(lower)
32431or %l6, %o1, %o1
32432! move %l7(lower) -> %o2(upper)
32433sllx %l7, 32, %o2
32434
32435P2768: !_ST_BINIT [8] (maybe <- 0x1000126) (Int)
32436wr %g0, 0xe2, %asi
32437sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
32438sub %i0, %i2, %i2
32439stwa %l4, [%i2 + 12] %asi
32440add %l4, 1, %l4
32441
32442P2769: !_MEMBAR (Int)
32443
32444P2770: !_BSTC [4] (maybe <- 0x408000e8) (FP)
32445wr %g0, 0xe0, %asi
32446! preparing store val #0, next val will be in f32
32447fmovs %f16, %f20
32448fadds %f16, %f17, %f16
32449! preparing store val #1, next val will be in f33
32450fmovs %f16, %f21
32451fadds %f16, %f17, %f16
32452! preparing store val #2, next val will be in f35
32453fmovd %f20, %f32
32454fmovs %f16, %f21
32455fadds %f16, %f17, %f16
32456fmovd %f20, %f34
32457membar #Sync
32458stda %f32, [%i1 + 0 ] %asi
32459
32460P2771: !_MEMBAR (FP)
32461membar #StoreLoad
32462
32463P2772: !_LD [4] (Int)
32464lduw [%i1 + 4], %l3
32465! move %l3(lower) -> %o2(lower)
32466or %l3, %o2, %o2
32467
32468P2773: !_ST_BINIT [20] (maybe <- 0x1000127) (Int)
32469wr %g0, 0xe2, %asi
32470sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
32471sub %i0, %i3, %i3
32472stwa %l4, [%i3 + 12] %asi
32473add %l4, 1, %l4
32474
32475P2774: !_MEMBAR (Int)
32476membar #StoreLoad
32477
32478P2775: !_ST [0] (maybe <- 0x1000128) (Int)
32479stw %l4, [%i0 + 0 ]
32480add %l4, 1, %l4
32481
32482P2776: !_PREFETCH [2] (Int)
32483prefetch [%i0 + 12], 22
32484
32485P2777: !_DWST [1] (maybe <- 0x1000129) (Int)
32486sllx %l4, 32, %o5
32487add %l4, 1, %l4
32488or %o5, %l4, %o5
32489stx %o5, [%i0 + 0]
32490add %l4, 1, %l4
32491
32492P2778: !_MEMBAR (FP)
32493
32494P2779: !_BST [20] (maybe <- 0x408000eb) (FP)
32495wr %g0, 0xf0, %asi
32496! preparing store val #0, next val will be in f32
32497fmovs %f16, %f20
32498fadds %f16, %f17, %f16
32499! preparing store val #1, next val will be in f33
32500fmovs %f16, %f21
32501fadds %f16, %f17, %f16
32502! preparing store val #2, next val will be in f35
32503fmovd %f20, %f32
32504fmovs %f16, %f21
32505fadds %f16, %f17, %f16
32506fmovd %f20, %f34
32507membar #Sync
32508stda %f32, [%i3 + 0 ] %asi
32509
32510P2780: !_MEMBAR (FP)
32511membar #StoreLoad
32512
32513P2781: !_DWST [7] (maybe <- 0x408000ee) (FP) (Branch target of P2814)
32514! preparing store val #0, next val will be in f20
32515fmovs %f16, %f20
32516fadds %f16, %f17, %f16
32517! preparing store val #1, next val will be in f21
32518fmovs %f16, %f21
32519fadds %f16, %f17, %f16
32520std %f20, [%i2 + 0]
32521ba P2782
32522nop
32523
32524TARGET2814:
32525ba RET2814
32526nop
32527
32528
32529P2782: !_LDD [1] (Int)
32530ldd [%i0 + 0], %l6
32531! move %l6(lower) -> %o3(upper)
32532sllx %l6, 32, %o3
32533! move %l7(lower) -> %o3(lower)
32534or %l7, %o3, %o3
32535
32536P2783: !_SWAP [8] (maybe <- 0x100012b) (Int) (CBR)
32537mov %l4, %o4
32538swap [%i2 + 12], %o4
32539! move %o4(lower) -> %o4(upper)
32540sllx %o4, 32, %o4
32541add %l4, 1, %l4
32542
32543! cbranch
32544andcc %l0, 1, %g0
32545be,pn %xcc, TARGET2783
32546nop
32547RET2783:
32548
32549! lfsr step begin
32550srlx %l0, 1, %o5
32551xnor %o5, %l0, %o5
32552sllx %o5, 63, %o5
32553or %o5, %l0, %l0
32554srlx %l0, 1, %l0
32555
32556
32557P2784: !_MEMBAR (FP)
32558
32559P2785: !_BSTC [18] (maybe <- 0x408000f0) (FP) (Branch target of P2622)
32560wr %g0, 0xe0, %asi
32561! preparing store val #0, next val will be in f32
32562fmovs %f16, %f20
32563fadds %f16, %f17, %f16
32564! preparing store val #1, next val will be in f33
32565fmovs %f16, %f21
32566fadds %f16, %f17, %f16
32567! preparing store val #2, next val will be in f35
32568fmovd %f20, %f32
32569fmovs %f16, %f21
32570fadds %f16, %f17, %f16
32571fmovd %f20, %f34
32572membar #Sync
32573stda %f32, [%i3 + 0 ] %asi
32574ba P2786
32575nop
32576
32577TARGET2622:
32578ba RET2622
32579nop
32580
32581
32582P2786: !_MEMBAR (FP)
32583membar #StoreLoad
32584
32585P2787: !_PREFETCH [17] (Int)
32586sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
32587sub %i0, %i2, %i2
32588prefetch [%i2 + 12], 24
32589
32590P2788: !_LD [2] (Int)
32591lduw [%i0 + 12], %l3
32592! move %l3(lower) -> %o4(lower)
32593or %l3, %o4, %o4
32594!---- flushing int results buffer----
32595mov %o0, %l5
32596mov %o1, %l5
32597mov %o2, %l5
32598mov %o3, %l5
32599mov %o4, %l5
32600
32601P2789: !_ST_BINIT [3] (maybe <- 0x100012c) (Int)
32602wr %g0, 0xe2, %asi
32603stwa %l4, [%i1 + 0] %asi
32604add %l4, 1, %l4
32605
32606P2790: !_MEMBAR (Int)
32607membar #StoreLoad
32608
32609P2791: !_PREFETCH [15] (Int)
32610prefetch [%i2 + 0], 22
32611
32612P2792: !_REPLACEMENT [1] (Int)
32613sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
32614add %i0, %i3, %i3
32615sethi %hi(0x20000), %l3
32616ld [%i3+4], %l7
32617st %l7, [%i3+4]
32618add %i3, %l3, %l6
32619ld [%l6+4], %l7
32620st %l7, [%l6+4]
32621add %l6, %l3, %l6
32622ld [%l6+4], %l7
32623st %l7, [%l6+4]
32624add %l6, %l3, %l6
32625ld [%l6+4], %l7
32626st %l7, [%l6+4]
32627add %l6, %l3, %l6
32628ld [%l6+4], %l7
32629st %l7, [%l6+4]
32630add %l6, %l3, %l6
32631ld [%l6+4], %l7
32632st %l7, [%l6+4]
32633add %l6, %l3, %l6
32634ld [%l6+4], %l7
32635st %l7, [%l6+4]
32636add %l6, %l3, %l6
32637ld [%l6+4], %l7
32638st %l7, [%l6+4]
32639
32640P2793: !_CASX [8] (maybe <- 0x100012d) (Int) (Branch target of P2363)
32641sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
32642sub %i0, %i2, %i2
32643add %i2, 8, %l3
32644ldx [%l3], %o0
32645! move %o0(upper) -> %o0(upper)
32646! move %o0(lower) -> %o0(lower)
32647mov %o0, %o5
32648mov %l4, %o1
32649casx [%l3], %o5, %o1
32650! move %o1(upper) -> %o1(upper)
32651! move %o1(lower) -> %o1(lower)
32652add %l4, 1, %l4
32653ba P2794
32654nop
32655
32656TARGET2363:
32657ba RET2363
32658nop
32659
32660
32661P2794: !_ST_BINIT [15] (maybe <- 0x100012e) (Int)
32662wr %g0, 0xe2, %asi
32663sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
32664sub %i0, %i3, %i3
32665stwa %l4, [%i3 + 0] %asi
32666add %l4, 1, %l4
32667
32668P2795: !_MEMBAR (Int)
32669
32670P2796: !_BST [2] (maybe <- 0x408000f3) (FP)
32671wr %g0, 0xf0, %asi
32672! preparing store val #0, next val will be in f32
32673fmovs %f16, %f20
32674fadds %f16, %f17, %f16
32675! preparing store val #1, next val will be in f33
32676fmovs %f16, %f21
32677fadds %f16, %f17, %f16
32678! preparing store val #2, next val will be in f35
32679fmovd %f20, %f32
32680fmovs %f16, %f21
32681fadds %f16, %f17, %f16
32682fmovd %f20, %f34
32683membar #Sync
32684stda %f32, [%i0 + 0 ] %asi
32685
32686P2797: !_MEMBAR (FP)
32687membar #StoreLoad
32688
32689P2798: !_DWST [1] (maybe <- 0x100012f) (Int)
32690sllx %l4, 32, %l6
32691add %l4, 1, %l4
32692or %l6, %l4, %l6
32693stx %l6, [%i0 + 0]
32694add %l4, 1, %l4
32695
32696P2799: !_DWST [17] (maybe <- 0x1000131) (Int)
32697mov %l4, %l3
32698stx %l3, [%i3 + 8]
32699add %l4, 1, %l4
32700
32701P2800: !_CAS [20] (maybe <- 0x1000132) (Int)
32702sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
32703sub %i0, %i2, %i2
32704add %i2, 12, %l3
32705lduw [%l3], %o2
32706mov %o2, %o5
32707! move %o5(lower) -> %o2(upper)
32708sllx %o5, 32, %o2
32709mov %l4, %l7
32710cas [%l3], %o5, %l7
32711! move %l7(lower) -> %o2(lower)
32712srl %l7, 0, %o5
32713or %o5, %o2, %o2
32714add %l4, 1, %l4
32715
32716P2801: !_CAS [18] (maybe <- 0x1000133) (Int) (LE) (CBR)
32717! Change single-word-level endianess (big endian <-> little endian)
32718sethi %hi(0xff00ff00), %l3
32719or %l3, %lo(0xff00ff00), %l3
32720and %l4, %l3, %o5
32721srl %o5, 8, %o5
32722sll %l4, 8, %l6
32723and %l6, %l3, %l6
32724or %l6, %o5, %l6
32725srl %l6, 16, %o5
32726sll %l6, 16, %l6
32727srl %l6, 0, %l6
32728or %l6, %o5, %l6
32729wr %g0, 0x88, %asi
32730lduwa [%i2] %asi, %o3
32731mov %o3, %o5
32732! move %o5(lower) -> %o3(upper)
32733sllx %o5, 32, %o3
32734mov %l6, %l7
32735casa [%i2] %asi, %o5, %l7
32736! move %l7(lower) -> %o3(lower)
32737srl %l7, 0, %o5
32738or %o5, %o3, %o3
32739add %l4, 1, %l4
32740
32741! cbranch
32742andcc %l0, 1, %g0
32743be,pn %xcc, TARGET2801
32744nop
32745RET2801:
32746
32747! lfsr step begin
32748srlx %l0, 1, %o5
32749xnor %o5, %l0, %o5
32750sllx %o5, 63, %o5
32751or %o5, %l0, %l0
32752srlx %l0, 1, %l0
32753
32754
32755P2802: !_DWLD [9] (Int)
32756sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
32757add %i0, %i3, %i3
32758ldx [%i3 + 0], %o4
32759! move %o4(upper) -> %o4(upper)
32760! move %o4(lower) -> %o4(lower)
32761!---- flushing int results buffer----
32762mov %o0, %l5
32763mov %o1, %l5
32764mov %o2, %l5
32765mov %o3, %l5
32766mov %o4, %l5
32767
32768P2803: !_DWST_BINIT [18] (maybe <- 0x1000134) (Int)
32769wr %g0, 0xe2, %asi
32770sllx %l4, 32, %l7
32771add %l4, 1, %l4
32772or %l7, %l4, %l7
32773stxa %l7, [%i2 + 0] %asi
32774add %l4, 1, %l4
32775
32776P2804: !_MEMBAR (Int)
32777membar #StoreLoad
32778
32779P2805: !_PREFETCH [6] (Int)
32780sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
32781sub %i0, %i2, %i2
32782prefetch [%i2 + 0], 1
32783
32784P2806: !_CASX [6] (maybe <- 0x1000136) (Int)
32785ldx [%i2], %o0
32786! move %o0(upper) -> %o0(upper)
32787! move %o0(lower) -> %o0(lower)
32788mov %o0, %l6
32789sllx %l4, 32, %o1
32790add %l4, 1, %l4
32791or %l4, %o1, %o1
32792casx [%i2], %l6, %o1
32793! move %o1(upper) -> %o1(upper)
32794! move %o1(lower) -> %o1(lower)
32795add %l4, 1, %l4
32796
32797P2807: !_SWAP [17] (maybe <- 0x1000138) (Int)
32798sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
32799sub %i0, %i3, %i3
32800mov %l4, %o2
32801swap [%i3 + 12], %o2
32802! move %o2(lower) -> %o2(upper)
32803sllx %o2, 32, %o2
32804add %l4, 1, %l4
32805
32806P2808: !_LDD [6] (Int)
32807ldd [%i2 + 0], %l6
32808! move %l6(lower) -> %o2(lower)
32809or %l6, %o2, %o2
32810! move %l7(lower) -> %o3(upper)
32811sllx %l7, 32, %o3
32812
32813P2809: !_MEMBAR (FP)
32814membar #StoreLoad
32815
32816P2810: !_BLD [6] (FP)
32817wr %g0, 0xf0, %asi
32818ldda [%i2 + 0] %asi, %f32
32819membar #Sync
32820! 3 addresses covered
32821fmovd %f32, %f18
32822fmovs %f18, %f5
32823fmovs %f19, %f6
32824fmovd %f34, %f18
32825fmovs %f19, %f7
32826
32827P2811: !_MEMBAR (FP)
32828
32829P2812: !_BLD [5] (FP)
32830wr %g0, 0xf0, %asi
32831ldda [%i1 + 0] %asi, %f32
32832membar #Sync
32833! 3 addresses covered
32834fmovd %f32, %f8
32835fmovd %f34, %f18
32836fmovs %f19, %f10
32837
32838P2813: !_MEMBAR (FP)
32839
32840P2814: !_DWLD [14] (Int) (LE) (CBR)
32841wr %g0, 0x88, %asi
32842sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
32843sub %i0, %i2, %i2
32844ldxa [%i2 + 8] %asi, %l6
32845! move %l6(upper) -> %o3(lower)
32846srlx %l6, 32, %l3
32847or %l3, %o3, %o3
32848
32849! cbranch
32850andcc %l0, 1, %g0
32851be,pn %xcc, TARGET2814
32852nop
32853RET2814:
32854
32855! lfsr step begin
32856srlx %l0, 1, %l7
32857xnor %l7, %l0, %l7
32858sllx %l7, 63, %l7
32859or %l7, %l0, %l0
32860srlx %l0, 1, %l0
32861
32862
32863P2815: !_REPLACEMENT [15] (Int)
32864sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
32865sub %i0, %i3, %i3
32866sethi %hi(0x20000), %o5
32867ld [%i3+0], %l6
32868st %l6, [%i3+0]
32869add %i3, %o5, %l3
32870ld [%l3+0], %l6
32871st %l6, [%l3+0]
32872add %l3, %o5, %l3
32873ld [%l3+0], %l6
32874st %l6, [%l3+0]
32875add %l3, %o5, %l3
32876ld [%l3+0], %l6
32877st %l6, [%l3+0]
32878add %l3, %o5, %l3
32879ld [%l3+0], %l6
32880st %l6, [%l3+0]
32881add %l3, %o5, %l3
32882ld [%l3+0], %l6
32883st %l6, [%l3+0]
32884add %l3, %o5, %l3
32885ld [%l3+0], %l6
32886st %l6, [%l3+0]
32887add %l3, %o5, %l3
32888ld [%l3+0], %l6
32889st %l6, [%l3+0]
32890
32891P2816: !_MEMBAR (FP)
32892
32893P2817: !_BSTC [20] (maybe <- 0x408000f6) (FP)
32894wr %g0, 0xe0, %asi
32895sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
32896sub %i0, %i2, %i2
32897! preparing store val #0, next val will be in f32
32898fmovs %f16, %f20
32899fadds %f16, %f17, %f16
32900! preparing store val #1, next val will be in f33
32901fmovs %f16, %f21
32902fadds %f16, %f17, %f16
32903! preparing store val #2, next val will be in f35
32904fmovd %f20, %f32
32905fmovs %f16, %f21
32906fadds %f16, %f17, %f16
32907fmovd %f20, %f34
32908membar #Sync
32909stda %f32, [%i2 + 0 ] %asi
32910
32911P2818: !_MEMBAR (FP)
32912membar #StoreLoad
32913
32914P2819: !_ST_BINIT [15] (maybe <- 0x1000139) (Int)
32915wr %g0, 0xe2, %asi
32916sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
32917sub %i0, %i3, %i3
32918stwa %l4, [%i3 + 0] %asi
32919add %l4, 1, %l4
32920
32921P2820: !_MEMBAR (Int)
32922membar #StoreLoad
32923
32924P2821: !_DWLD [12] (Int)
32925sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
32926sub %i0, %i2, %i2
32927ldx [%i2 + 0], %o4
32928! move %o4(upper) -> %o4(upper)
32929! move %o4(lower) -> %o4(lower)
32930!---- flushing int results buffer----
32931mov %o0, %l5
32932mov %o1, %l5
32933mov %o2, %l5
32934mov %o3, %l5
32935mov %o4, %l5
32936
32937P2822: !_MEMBAR (FP)
32938
32939P2823: !_BSTC [10] (maybe <- 0x408000f9) (FP) (Branch target of P2509)
32940wr %g0, 0xe0, %asi
32941sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
32942add %i0, %i3, %i3
32943! preparing store val #0, next val will be in f32
32944fmovs %f16, %f20
32945fadds %f16, %f17, %f16
32946! preparing store val #1, next val will be in f33
32947fmovs %f16, %f21
32948fadds %f16, %f17, %f16
32949! preparing store val #2, next val will be in f35
32950fmovd %f20, %f32
32951fmovs %f16, %f21
32952fadds %f16, %f17, %f16
32953fmovd %f20, %f34
32954membar #Sync
32955stda %f32, [%i3 + 0 ] %asi
32956ba P2824
32957nop
32958
32959TARGET2509:
32960ba RET2509
32961nop
32962
32963
32964P2824: !_MEMBAR (FP)
32965membar #StoreLoad
32966
32967P2825: !_DWST_BINIT [18] (maybe <- 0x100013a) (Int)
32968wr %g0, 0xe2, %asi
32969sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
32970sub %i0, %i2, %i2
32971sllx %l4, 32, %l6
32972add %l4, 1, %l4
32973or %l6, %l4, %l6
32974stxa %l6, [%i2 + 0] %asi
32975add %l4, 1, %l4
32976
32977P2826: !_MEMBAR (Int)
32978membar #StoreLoad
32979
32980P2827: !_ST_BINIT [1] (maybe <- 0x100013c) (Int)
32981wr %g0, 0xe2, %asi
32982stwa %l4, [%i0 + 4] %asi
32983add %l4, 1, %l4
32984
32985P2828: !_MEMBAR (Int)
32986membar #StoreLoad
32987
32988P2829: !_LD [1] (Int)
32989lduw [%i0 + 4], %o0
32990! move %o0(lower) -> %o0(upper)
32991sllx %o0, 32, %o0
32992
32993P2830: !_ST [21] (maybe <- 0x100013d) (Int)
32994sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
32995sub %i0, %i3, %i3
32996stw %l4, [%i3 + 0 ]
32997add %l4, 1, %l4
32998
32999P2831: !_PREFETCH [18] (Int)
33000prefetch [%i2 + 0], 1
33001
33002P2832: !_MEMBAR (FP)
33003membar #StoreLoad
33004
33005P2833: !_BLD [20] (FP)
33006wr %g0, 0xf0, %asi
33007ldda [%i2 + 0] %asi, %f32
33008membar #Sync
33009! 3 addresses covered
33010fmovd %f32, %f18
33011fmovs %f18, %f11
33012fmovs %f19, %f12
33013fmovd %f34, %f18
33014fmovs %f19, %f13
33015
33016P2834: !_MEMBAR (FP)
33017
33018P2835: !_CASX [4] (maybe <- 0x100013e) (Int)
33019!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
33020!Logical addr: 4
33021
33022sethi %hi(0x200000), %l3
33023sub %i1, %l3, %i1
33024ldx [%i1], %l3
33025! move %l3(upper) -> %o0(lower)
33026srlx %l3, 32, %l6
33027or %l6, %o0, %o0
33028! move %l3(lower) -> %o1(upper)
33029sllx %l3, 32, %o1
33030mov %l3, %l6
33031sllx %l4, 32, %l3
33032add %l4, 1, %l4
33033or %l4, %l3, %l3
33034casx [%i1], %l6, %l3
33035! move %l3(upper) -> %o1(lower)
33036srlx %l3, 32, %l6
33037or %l6, %o1, %o1
33038! move %l3(lower) -> %o2(upper)
33039sllx %l3, 32, %o2
33040add %l4, 1, %l4
33041
33042P2836: !_CAS [10] (maybe <- 0x1000140) (Int)
33043sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
33044add %i0, %i2, %i2
33045add %i2, 4, %l7
33046lduw [%l7], %l3
33047mov %l3, %l6
33048! move %l6(lower) -> %o2(lower)
33049or %l6, %o2, %o2
33050mov %l4, %o3
33051cas [%l7], %l6, %o3
33052! move %o3(lower) -> %o3(upper)
33053sllx %o3, 32, %o3
33054add %l4, 1, %l4
33055
33056P2837: !_MEMBAR (FP)
33057
33058P2838: !_BSTC [21] (maybe <- 0x408000fc) (FP)
33059wr %g0, 0xe0, %asi
33060! preparing store val #0, next val will be in f32
33061fmovs %f16, %f20
33062fadds %f16, %f17, %f16
33063! preparing store val #1, next val will be in f33
33064fmovs %f16, %f21
33065fadds %f16, %f17, %f16
33066! preparing store val #2, next val will be in f35
33067fmovd %f20, %f32
33068fmovs %f16, %f21
33069fadds %f16, %f17, %f16
33070fmovd %f20, %f34
33071membar #Sync
33072stda %f32, [%i3 + 0 ] %asi
33073
33074P2839: !_MEMBAR (FP)
33075membar #StoreLoad
33076
33077P2840: !_REPLACEMENT [4] (Int)
33078sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
33079add %i0, %i3, %i3
33080sethi %hi(0x20000), %l3
33081ld [%i3+4], %l7
33082st %l7, [%i3+4]
33083add %i3, %l3, %l6
33084ld [%l6+4], %l7
33085st %l7, [%l6+4]
33086add %l6, %l3, %l6
33087ld [%l6+4], %l7
33088st %l7, [%l6+4]
33089add %l6, %l3, %l6
33090ld [%l6+4], %l7
33091st %l7, [%l6+4]
33092add %l6, %l3, %l6
33093ld [%l6+4], %l7
33094st %l7, [%l6+4]
33095add %l6, %l3, %l6
33096ld [%l6+4], %l7
33097st %l7, [%l6+4]
33098add %l6, %l3, %l6
33099ld [%l6+4], %l7
33100st %l7, [%l6+4]
33101add %l6, %l3, %l6
33102ld [%l6+4], %l7
33103st %l7, [%l6+4]
33104
33105P2841: !_ST_BINIT [19] (maybe <- 0x1000141) (Int)
33106wr %g0, 0xe2, %asi
33107sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
33108sub %i0, %i2, %i2
33109stwa %l4, [%i2 + 4] %asi
33110add %l4, 1, %l4
33111
33112P2842: !_MEMBAR (Int)
33113membar #StoreLoad
33114
33115P2843: !_CASX [10] (maybe <- 0x1000142) (Int)
33116sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
33117add %i0, %i3, %i3
33118ldx [%i3], %l6
33119! move %l6(upper) -> %o3(lower)
33120srlx %l6, 32, %l7
33121or %l7, %o3, %o3
33122! move %l6(lower) -> %o4(upper)
33123sllx %l6, 32, %o4
33124mov %l6, %l7
33125sllx %l4, 32, %l6
33126add %l4, 1, %l4
33127or %l4, %l6, %l6
33128casx [%i3], %l7, %l6
33129! move %l6(upper) -> %o4(lower)
33130srlx %l6, 32, %l7
33131or %l7, %o4, %o4
33132!---- flushing int results buffer----
33133mov %o0, %l5
33134mov %o1, %l5
33135mov %o2, %l5
33136mov %o3, %l5
33137mov %o4, %l5
33138! move %l6(lower) -> %o0(upper)
33139sllx %l6, 32, %o0
33140add %l4, 1, %l4
33141
33142P2844: !_PREFETCH [12] (Int)
33143sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
33144sub %i0, %i2, %i2
33145prefetch [%i2 + 0], 22
33146
33147P2845: !_DWST_BINIT [6] (maybe <- 0x1000144) (Int)
33148wr %g0, 0xe2, %asi
33149sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
33150sub %i0, %i3, %i3
33151sllx %l4, 32, %l7
33152add %l4, 1, %l4
33153or %l7, %l4, %l7
33154stxa %l7, [%i3 + 0] %asi
33155add %l4, 1, %l4
33156
33157P2846: !_MEMBAR (Int)
33158membar #StoreLoad
33159
33160P2847: !_BLD [11] (FP)
33161wr %g0, 0xf0, %asi
33162sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
33163add %i0, %i2, %i2
33164ldda [%i2 + 0] %asi, %f32
33165membar #Sync
33166! 3 addresses covered
33167fmovd %f32, %f14
33168!---- flushing fp results buffer to %f30 ----
33169fmovd %f0, %f30
33170fmovd %f2, %f30
33171fmovd %f4, %f30
33172fmovd %f6, %f30
33173fmovd %f8, %f30
33174fmovd %f10, %f30
33175fmovd %f12, %f30
33176fmovd %f14, %f30
33177!--
33178fmovd %f34, %f18
33179fmovs %f19, %f0
33180
33181P2848: !_MEMBAR (FP)
33182
33183P2849: !_DWST [3] (maybe <- 0x1000146) (Int)
33184sllx %l4, 32, %l6
33185add %l4, 1, %l4
33186or %l6, %l4, %l6
33187stx %l6, [%i1 + 0]
33188add %l4, 1, %l4
33189
33190P2850: !_DWST_BINIT [15] (maybe <- 0x1000148) (Int)
33191wr %g0, 0xe2, %asi
33192sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
33193sub %i0, %i3, %i3
33194sllx %l4, 32, %l3
33195add %l4, 1, %l4
33196or %l3, %l4, %l3
33197stxa %l3, [%i3 + 0] %asi
33198add %l4, 1, %l4
33199
33200P2851: !_MEMBAR (Int)
33201membar #StoreLoad
33202
33203P2852: !_DWLD [22] (Int)
33204sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
33205sub %i0, %i2, %i2
33206ldx [%i2 + 0], %l3
33207! move %l3(upper) -> %o0(lower)
33208srlx %l3, 32, %o5
33209or %o5, %o0, %o0
33210! move %l3(lower) -> %o1(upper)
33211sllx %l3, 32, %o1
33212
33213P2853: !_MEMBAR (FP)
33214
33215P2854: !_BSTC [20] (maybe <- 0x408000ff) (FP)
33216wr %g0, 0xe0, %asi
33217sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
33218sub %i0, %i3, %i3
33219! preparing store val #0, next val will be in f32
33220fmovs %f16, %f20
33221fadds %f16, %f17, %f16
33222! preparing store val #1, next val will be in f33
33223fmovs %f16, %f21
33224fadds %f16, %f17, %f16
33225! preparing store val #2, next val will be in f35
33226fmovd %f20, %f32
33227fmovs %f16, %f21
33228fadds %f16, %f17, %f16
33229fmovd %f20, %f34
33230membar #Sync
33231stda %f32, [%i3 + 0 ] %asi
33232
33233P2855: !_MEMBAR (FP) (Branch target of P2357)
33234ba P2856
33235nop
33236
33237TARGET2357:
33238ba RET2357
33239nop
33240
33241
33242P2856: !_BST [15] (maybe <- 0x40800102) (FP)
33243wr %g0, 0xf0, %asi
33244sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
33245sub %i0, %i2, %i2
33246! preparing store val #0, next val will be in f32
33247fmovs %f16, %f20
33248fadds %f16, %f17, %f16
33249! preparing store val #1, next val will be in f33
33250fmovs %f16, %f21
33251fadds %f16, %f17, %f16
33252! preparing store val #2, next val will be in f35
33253fmovd %f20, %f32
33254fmovs %f16, %f21
33255fadds %f16, %f17, %f16
33256fmovd %f20, %f34
33257membar #Sync
33258stda %f32, [%i2 + 0 ] %asi
33259
33260P2857: !_MEMBAR (FP)
33261membar #StoreLoad
33262
33263P2858: !_BLD [1] (FP)
33264wr %g0, 0xf0, %asi
33265ldda [%i0 + 0] %asi, %f32
33266membar #Sync
33267! 3 addresses covered
33268fmovd %f32, %f18
33269fmovs %f18, %f1
33270fmovs %f19, %f2
33271fmovd %f34, %f18
33272fmovs %f19, %f3
33273
33274P2859: !_MEMBAR (FP)
33275
33276P2860: !_ST [14] (maybe <- 0x100014a) (Int)
33277sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
33278sub %i0, %i3, %i3
33279stw %l4, [%i3 + 12 ]
33280add %l4, 1, %l4
33281
33282P2861: !_DWST_BINIT [11] (maybe <- 0x100014b) (Int)
33283wr %g0, 0xe2, %asi
33284sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
33285add %i0, %i2, %i2
33286mov %l4, %l7
33287stxa %l7, [%i2 + 8] %asi
33288add %l4, 1, %l4
33289
33290P2862: !_MEMBAR (Int)
33291membar #StoreLoad
33292
33293P2863: !_SWAP [16] (maybe <- 0x100014c) (Int)
33294sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
33295sub %i0, %i3, %i3
33296mov %l4, %o5
33297swap [%i3 + 4], %o5
33298! move %o5(lower) -> %o1(lower)
33299srl %o5, 0, %l6
33300or %l6, %o1, %o1
33301add %l4, 1, %l4
33302
33303P2864: !_MEMBAR (FP)
33304membar #StoreLoad
33305
33306P2865: !_BLD [15] (FP)
33307wr %g0, 0xf0, %asi
33308ldda [%i3 + 0] %asi, %f32
33309membar #Sync
33310! 3 addresses covered
33311fmovd %f32, %f4
33312fmovd %f34, %f18
33313fmovs %f19, %f6
33314
33315P2866: !_MEMBAR (FP)
33316
33317P2867: !_BSTC [6] (maybe <- 0x40800105) (FP)
33318wr %g0, 0xe0, %asi
33319sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
33320sub %i0, %i2, %i2
33321! preparing store val #0, next val will be in f32
33322fmovs %f16, %f20
33323fadds %f16, %f17, %f16
33324! preparing store val #1, next val will be in f33
33325fmovs %f16, %f21
33326fadds %f16, %f17, %f16
33327! preparing store val #2, next val will be in f35
33328fmovd %f20, %f32
33329fmovs %f16, %f21
33330fadds %f16, %f17, %f16
33331fmovd %f20, %f34
33332membar #Sync
33333stda %f32, [%i2 + 0 ] %asi
33334
33335P2868: !_MEMBAR (FP)
33336membar #StoreLoad
33337
33338P2869: !_REPLACEMENT [6] (Int)
33339sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
33340sub %i0, %i3, %i3
33341sethi %hi(0x20000), %o5
33342ld [%i3+0], %l6
33343st %l6, [%i3+0]
33344add %i3, %o5, %l3
33345ld [%l3+0], %l6
33346st %l6, [%l3+0]
33347add %l3, %o5, %l3
33348ld [%l3+0], %l6
33349st %l6, [%l3+0]
33350add %l3, %o5, %l3
33351ld [%l3+0], %l6
33352st %l6, [%l3+0]
33353add %l3, %o5, %l3
33354ld [%l3+0], %l6
33355st %l6, [%l3+0]
33356add %l3, %o5, %l3
33357ld [%l3+0], %l6
33358st %l6, [%l3+0]
33359add %l3, %o5, %l3
33360ld [%l3+0], %l6
33361st %l6, [%l3+0]
33362add %l3, %o5, %l3
33363ld [%l3+0], %l6
33364st %l6, [%l3+0]
33365
33366P2870: !_CAS [3] (maybe <- 0x100014d) (Int) (LE)
33367! Change single-word-level endianess (big endian <-> little endian)
33368sethi %hi(0xff00ff00), %o5
33369or %o5, %lo(0xff00ff00), %o5
33370and %l4, %o5, %l7
33371srl %l7, 8, %l7
33372sll %l4, 8, %l3
33373and %l3, %o5, %l3
33374or %l3, %l7, %l3
33375srl %l3, 16, %l7
33376sll %l3, 16, %l3
33377srl %l3, 0, %l3
33378or %l3, %l7, %l3
33379wr %g0, 0x88, %asi
33380lduwa [%i1] %asi, %o2
33381mov %o2, %l7
33382! move %l7(lower) -> %o2(upper)
33383sllx %l7, 32, %o2
33384mov %l3, %l6
33385casa [%i1] %asi, %l7, %l6
33386! move %l6(lower) -> %o2(lower)
33387srl %l6, 0, %l7
33388or %l7, %o2, %o2
33389add %l4, 1, %l4
33390
33391P2871: !_MEMBAR (FP)
33392membar #StoreLoad
33393
33394P2872: !_BLD [9] (FP)
33395wr %g0, 0xf0, %asi
33396sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
33397add %i0, %i2, %i2
33398ldda [%i2 + 0] %asi, %f32
33399membar #Sync
33400! 3 addresses covered
33401fmovd %f32, %f18
33402fmovs %f18, %f7
33403fmovs %f19, %f8
33404fmovd %f34, %f18
33405fmovs %f19, %f9
33406
33407P2873: !_MEMBAR (FP)
33408
33409P2874: !_BSTC [13] (maybe <- 0x40800108) (FP)
33410wr %g0, 0xe0, %asi
33411sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
33412sub %i0, %i3, %i3
33413! preparing store val #0, next val will be in f32
33414fmovs %f16, %f20
33415fadds %f16, %f17, %f16
33416! preparing store val #1, next val will be in f33
33417fmovs %f16, %f21
33418fadds %f16, %f17, %f16
33419! preparing store val #2, next val will be in f35
33420fmovd %f20, %f32
33421fmovs %f16, %f21
33422fadds %f16, %f17, %f16
33423fmovd %f20, %f34
33424membar #Sync
33425stda %f32, [%i3 + 0 ] %asi
33426
33427P2875: !_MEMBAR (FP)
33428membar #StoreLoad
33429
33430P2876: !_REPLACEMENT [6] (Int)
33431sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
33432add %i0, %i2, %i2
33433sethi %hi(0x20000), %l6
33434ld [%i2+0], %o5
33435st %o5, [%i2+0]
33436add %i2, %l6, %l7
33437ld [%l7+0], %o5
33438st %o5, [%l7+0]
33439add %l7, %l6, %l7
33440ld [%l7+0], %o5
33441st %o5, [%l7+0]
33442add %l7, %l6, %l7
33443ld [%l7+0], %o5
33444st %o5, [%l7+0]
33445add %l7, %l6, %l7
33446ld [%l7+0], %o5
33447st %o5, [%l7+0]
33448add %l7, %l6, %l7
33449ld [%l7+0], %o5
33450st %o5, [%l7+0]
33451add %l7, %l6, %l7
33452ld [%l7+0], %o5
33453st %o5, [%l7+0]
33454add %l7, %l6, %l7
33455ld [%l7+0], %o5
33456st %o5, [%l7+0]
33457
33458P2877: !_PREFETCH [4] (Int)
33459prefetch [%i1 + 4], 20
33460
33461P2878: !_MEMBAR (FP)
33462membar #StoreLoad
33463
33464P2879: !_BLD [4] (FP)
33465wr %g0, 0xf0, %asi
33466ldda [%i1 + 0] %asi, %f32
33467membar #Sync
33468! 3 addresses covered
33469fmovd %f32, %f10
33470fmovd %f34, %f18
33471fmovs %f19, %f12
33472
33473P2880: !_MEMBAR (FP)
33474
33475P2881: !_BST [3] (maybe <- 0x4080010b) (FP)
33476wr %g0, 0xf0, %asi
33477! preparing store val #0, next val will be in f32
33478fmovs %f16, %f20
33479fadds %f16, %f17, %f16
33480! preparing store val #1, next val will be in f33
33481fmovs %f16, %f21
33482fadds %f16, %f17, %f16
33483! preparing store val #2, next val will be in f35
33484fmovd %f20, %f32
33485fmovs %f16, %f21
33486fadds %f16, %f17, %f16
33487fmovd %f20, %f34
33488membar #Sync
33489stda %f32, [%i1 + 0 ] %asi
33490
33491P2882: !_MEMBAR (FP)
33492membar #StoreLoad
33493
33494P2883: !_DWLD [10] (Int)
33495sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
33496add %i0, %i3, %i3
33497ldx [%i3 + 0], %o3
33498! move %o3(upper) -> %o3(upper)
33499! move %o3(lower) -> %o3(lower)
33500
33501P2884: !_CAS [5] (maybe <- 0x100014e) (Int)
33502add %i1, 12, %l7
33503lduw [%l7], %o4
33504mov %o4, %l6
33505! move %l6(lower) -> %o4(upper)
33506sllx %l6, 32, %o4
33507mov %l4, %l3
33508cas [%l7], %l6, %l3
33509! move %l3(lower) -> %o4(lower)
33510srl %l3, 0, %l6
33511or %l6, %o4, %o4
33512!---- flushing int results buffer----
33513mov %o0, %l5
33514mov %o1, %l5
33515mov %o2, %l5
33516mov %o3, %l5
33517mov %o4, %l5
33518add %l4, 1, %l4
33519
33520P2885: !_MEMBAR (FP)
33521membar #StoreLoad
33522
33523P2886: !_BLD [21] (FP)
33524wr %g0, 0xf0, %asi
33525sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
33526sub %i0, %i2, %i2
33527ldda [%i2 + 0] %asi, %f32
33528membar #Sync
33529! 3 addresses covered
33530fmovd %f32, %f18
33531fmovs %f18, %f13
33532fmovs %f19, %f14
33533fmovd %f34, %f18
33534fmovs %f19, %f15
33535!---- flushing fp results buffer to %f30 ----
33536fmovd %f0, %f30
33537fmovd %f2, %f30
33538fmovd %f4, %f30
33539fmovd %f6, %f30
33540fmovd %f8, %f30
33541fmovd %f10, %f30
33542fmovd %f12, %f30
33543fmovd %f14, %f30
33544!--
33545
33546P2887: !_MEMBAR (FP)
33547
33548P2888: !_BSTC [21] (maybe <- 0x4080010e) (FP)
33549wr %g0, 0xe0, %asi
33550! preparing store val #0, next val will be in f32
33551fmovs %f16, %f20
33552fadds %f16, %f17, %f16
33553! preparing store val #1, next val will be in f33
33554fmovs %f16, %f21
33555fadds %f16, %f17, %f16
33556! preparing store val #2, next val will be in f35
33557fmovd %f20, %f32
33558fmovs %f16, %f21
33559fadds %f16, %f17, %f16
33560fmovd %f20, %f34
33561membar #Sync
33562stda %f32, [%i2 + 0 ] %asi
33563
33564P2889: !_MEMBAR (FP)
33565membar #StoreLoad
33566
33567P2890: !_ST_BINIT [10] (maybe <- 0x100014f) (Int)
33568wr %g0, 0xe2, %asi
33569stwa %l4, [%i3 + 4] %asi
33570add %l4, 1, %l4
33571
33572P2891: !_MEMBAR (Int)
33573
33574P2892: !_BSTC [0] (maybe <- 0x40800111) (FP)
33575wr %g0, 0xe0, %asi
33576! preparing store val #0, next val will be in f32
33577fmovs %f16, %f20
33578fadds %f16, %f17, %f16
33579! preparing store val #1, next val will be in f33
33580fmovs %f16, %f21
33581fadds %f16, %f17, %f16
33582! preparing store val #2, next val will be in f35
33583fmovd %f20, %f32
33584fmovs %f16, %f21
33585fadds %f16, %f17, %f16
33586fmovd %f20, %f34
33587membar #Sync
33588stda %f32, [%i0 + 0 ] %asi
33589
33590P2893: !_MEMBAR (FP)
33591membar #StoreLoad
33592
33593P2894: !_CASX [14] (maybe <- 0x1000150) (Int) (Branch target of P2908)
33594sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
33595sub %i0, %i3, %i3
33596add %i3, 8, %o5
33597ldx [%o5], %o0
33598! move %o0(upper) -> %o0(upper)
33599! move %o0(lower) -> %o0(lower)
33600mov %o0, %l7
33601mov %l4, %o1
33602casx [%o5], %l7, %o1
33603! move %o1(upper) -> %o1(upper)
33604! move %o1(lower) -> %o1(lower)
33605add %l4, 1, %l4
33606ba P2895
33607nop
33608
33609TARGET2908:
33610ba RET2908
33611nop
33612
33613
33614P2895: !_MEMBAR (FP)
33615
33616P2896: !_BST [15] (maybe <- 0x40800114) (FP)
33617wr %g0, 0xf0, %asi
33618sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
33619sub %i0, %i2, %i2
33620! preparing store val #0, next val will be in f32
33621fmovs %f16, %f20
33622fadds %f16, %f17, %f16
33623! preparing store val #1, next val will be in f33
33624fmovs %f16, %f21
33625fadds %f16, %f17, %f16
33626! preparing store val #2, next val will be in f35
33627fmovd %f20, %f32
33628fmovs %f16, %f21
33629fadds %f16, %f17, %f16
33630fmovd %f20, %f34
33631membar #Sync
33632stda %f32, [%i2 + 0 ] %asi
33633
33634P2897: !_MEMBAR (FP)
33635
33636P2898: !_BSTC [20] (maybe <- 0x40800117) (FP)
33637wr %g0, 0xe0, %asi
33638sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
33639sub %i0, %i3, %i3
33640! preparing store val #0, next val will be in f32
33641fmovs %f16, %f20
33642fadds %f16, %f17, %f16
33643! preparing store val #1, next val will be in f33
33644fmovs %f16, %f21
33645fadds %f16, %f17, %f16
33646! preparing store val #2, next val will be in f35
33647fmovd %f20, %f32
33648fmovs %f16, %f21
33649fadds %f16, %f17, %f16
33650fmovd %f20, %f34
33651membar #Sync
33652stda %f32, [%i3 + 0 ] %asi
33653
33654P2899: !_MEMBAR (FP)
33655
33656P2900: !_BST [6] (maybe <- 0x4080011a) (FP) (Branch target of P3003)
33657wr %g0, 0xf0, %asi
33658sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
33659sub %i0, %i2, %i2
33660! preparing store val #0, next val will be in f32
33661fmovs %f16, %f20
33662fadds %f16, %f17, %f16
33663! preparing store val #1, next val will be in f33
33664fmovs %f16, %f21
33665fadds %f16, %f17, %f16
33666! preparing store val #2, next val will be in f35
33667fmovd %f20, %f32
33668fmovs %f16, %f21
33669fadds %f16, %f17, %f16
33670fmovd %f20, %f34
33671membar #Sync
33672stda %f32, [%i2 + 0 ] %asi
33673ba P2901
33674nop
33675
33676TARGET3003:
33677ba RET3003
33678nop
33679
33680
33681P2901: !_MEMBAR (FP)
33682
33683P2902: !_BSTC [0] (maybe <- 0x4080011d) (FP)
33684wr %g0, 0xe0, %asi
33685! preparing store val #0, next val will be in f32
33686fmovs %f16, %f20
33687fadds %f16, %f17, %f16
33688! preparing store val #1, next val will be in f33
33689fmovs %f16, %f21
33690fadds %f16, %f17, %f16
33691! preparing store val #2, next val will be in f35
33692fmovd %f20, %f32
33693fmovs %f16, %f21
33694fadds %f16, %f17, %f16
33695fmovd %f20, %f34
33696membar #Sync
33697stda %f32, [%i0 + 0 ] %asi
33698
33699P2903: !_MEMBAR (FP) (Branch target of P2404)
33700membar #StoreLoad
33701ba P2904
33702nop
33703
33704TARGET2404:
33705ba RET2404
33706nop
33707
33708
33709P2904: !_DWLD [17] (Int)
33710sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
33711sub %i0, %i3, %i3
33712ldx [%i3 + 8], %o2
33713! move %o2(lower) -> %o2(upper)
33714sllx %o2, 32, %o2
33715
33716P2905: !_CAS [10] (maybe <- 0x1000151) (Int)
33717sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
33718add %i0, %i2, %i2
33719add %i2, 4, %l7
33720lduw [%l7], %l3
33721mov %l3, %l6
33722! move %l6(lower) -> %o2(lower)
33723or %l6, %o2, %o2
33724mov %l4, %o3
33725cas [%l7], %l6, %o3
33726! move %o3(lower) -> %o3(upper)
33727sllx %o3, 32, %o3
33728add %l4, 1, %l4
33729
33730P2906: !_CAS [8] (maybe <- 0x1000152) (Int)
33731sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
33732sub %i0, %i3, %i3
33733add %i3, 12, %l7
33734lduw [%l7], %l3
33735mov %l3, %l6
33736! move %l6(lower) -> %o3(lower)
33737or %l6, %o3, %o3
33738mov %l4, %o4
33739cas [%l7], %l6, %o4
33740! move %o4(lower) -> %o4(upper)
33741sllx %o4, 32, %o4
33742add %l4, 1, %l4
33743
33744P2907: !_LD [19] (FP)
33745sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
33746sub %i0, %i2, %i2
33747ld [%i2 + 4], %f0
33748! 1 addresses covered
33749
33750P2908: !_PREFETCH [4] (Int) (CBR)
33751prefetch [%i1 + 4], 3
33752
33753! cbranch
33754andcc %l0, 1, %g0
33755be,pt %xcc, TARGET2908
33756nop
33757RET2908:
33758
33759! lfsr step begin
33760srlx %l0, 1, %l6
33761xnor %l6, %l0, %l6
33762sllx %l6, 63, %l6
33763or %l6, %l0, %l0
33764srlx %l0, 1, %l0
33765
33766
33767P2909: !_DWST [10] (maybe <- 0x40800120) (FP)
33768sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
33769add %i0, %i3, %i3
33770! preparing store val #0, next val will be in f20
33771fmovs %f16, %f20
33772fadds %f16, %f17, %f16
33773! preparing store val #1, next val will be in f21
33774fmovs %f16, %f21
33775fadds %f16, %f17, %f16
33776std %f20, [%i3 + 0]
33777
33778P2910: !_ST_BINIT [20] (maybe <- 0x1000153) (Int)
33779wr %g0, 0xe2, %asi
33780stwa %l4, [%i2 + 12] %asi
33781add %l4, 1, %l4
33782
33783P2911: !_MEMBAR (Int)
33784membar #StoreLoad
33785
33786P2912: !_LD [17] (Int)
33787sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
33788sub %i0, %i2, %i2
33789lduw [%i2 + 12], %l6
33790! move %l6(lower) -> %o4(lower)
33791or %l6, %o4, %o4
33792!---- flushing int results buffer----
33793mov %o0, %l5
33794mov %o1, %l5
33795mov %o2, %l5
33796mov %o3, %l5
33797mov %o4, %l5
33798
33799P2913: !_DWST [15] (maybe <- 0x1000154) (Int) (LE)
33800wr %g0, 0x88, %asi
33801sllx %l4, 32, %l7
33802add %l4, 1, %l4
33803or %l7, %l4, %o5
33804! Change double-word-level endianess (big endian <-> little endian)
33805sethi %hi(0xff00ff00), %l3
33806or %l3, %lo(0xff00ff00), %l3
33807sllx %l3, 32, %l7
33808or %l3, %l7, %l3
33809and %o5, %l3, %l7
33810srlx %l7, 8, %l7
33811sllx %o5, 8, %o5
33812and %o5, %l3, %o5
33813or %o5, %l7, %o5
33814sethi %hi(0xffff0000), %l3
33815srlx %o5, 16, %l7
33816andn %l7, %l3, %l7
33817andn %o5, %l3, %o5
33818sllx %o5, 16, %o5
33819or %o5, %l7, %o5
33820srlx %o5, 32, %l7
33821sllx %o5, 32, %o5
33822or %o5, %l7, %l7
33823stxa %l7, [%i2 + 0 ] %asi
33824add %l4, 1, %l4
33825
33826P2914: !_ST_BINIT [12] (maybe <- 0x1000156) (Int)
33827wr %g0, 0xe2, %asi
33828sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
33829sub %i0, %i3, %i3
33830stwa %l4, [%i3 + 0] %asi
33831add %l4, 1, %l4
33832
33833P2915: !_MEMBAR (Int)
33834membar #StoreLoad
33835
33836P2916: !_CAS [17] (maybe <- 0x1000157) (Int)
33837add %i2, 12, %l6
33838lduw [%l6], %o0
33839mov %o0, %l3
33840! move %l3(lower) -> %o0(upper)
33841sllx %l3, 32, %o0
33842mov %l4, %o5
33843cas [%l6], %l3, %o5
33844! move %o5(lower) -> %o0(lower)
33845srl %o5, 0, %l3
33846or %l3, %o0, %o0
33847add %l4, 1, %l4
33848
33849P2917: !_LDD [23] (Int)
33850sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
33851sub %i0, %i2, %i2
33852ldd [%i2 + 8], %l6
33853! move %l7(lower) -> %o1(upper)
33854sllx %l7, 32, %o1
33855
33856P2918: !_MEMBAR (FP)
33857
33858P2919: !_BSTC [15] (maybe <- 0x40800122) (FP) (CBR)
33859wr %g0, 0xe0, %asi
33860sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
33861sub %i0, %i3, %i3
33862! preparing store val #0, next val will be in f32
33863fmovs %f16, %f20
33864fadds %f16, %f17, %f16
33865! preparing store val #1, next val will be in f33
33866fmovs %f16, %f21
33867fadds %f16, %f17, %f16
33868! preparing store val #2, next val will be in f35
33869fmovd %f20, %f32
33870fmovs %f16, %f21
33871fadds %f16, %f17, %f16
33872fmovd %f20, %f34
33873membar #Sync
33874stda %f32, [%i3 + 0 ] %asi
33875
33876! cbranch
33877andcc %l0, 1, %g0
33878be,pn %xcc, TARGET2919
33879nop
33880RET2919:
33881
33882! lfsr step begin
33883srlx %l0, 1, %o5
33884xnor %o5, %l0, %o5
33885sllx %o5, 63, %o5
33886or %o5, %l0, %l0
33887srlx %l0, 1, %l0
33888
33889
33890P2920: !_MEMBAR (FP)
33891
33892P2921: !_BST [17] (maybe <- 0x40800125) (FP)
33893wr %g0, 0xf0, %asi
33894! preparing store val #0, next val will be in f32
33895fmovs %f16, %f20
33896fadds %f16, %f17, %f16
33897! preparing store val #1, next val will be in f33
33898fmovs %f16, %f21
33899fadds %f16, %f17, %f16
33900! preparing store val #2, next val will be in f35
33901fmovd %f20, %f32
33902fmovs %f16, %f21
33903fadds %f16, %f17, %f16
33904fmovd %f20, %f34
33905membar #Sync
33906stda %f32, [%i3 + 0 ] %asi
33907
33908P2922: !_MEMBAR (FP)
33909membar #StoreLoad
33910
33911P2923: !_CASX [15] (maybe <- 0x1000158) (Int)
33912ldx [%i3], %l7
33913! move %l7(upper) -> %o1(lower)
33914srlx %l7, 32, %o5
33915or %o5, %o1, %o1
33916! move %l7(lower) -> %o2(upper)
33917sllx %l7, 32, %o2
33918mov %l7, %o5
33919sllx %l4, 32, %l7
33920add %l4, 1, %l4
33921or %l4, %l7, %l7
33922casx [%i3], %o5, %l7
33923! move %l7(upper) -> %o2(lower)
33924srlx %l7, 32, %o5
33925or %o5, %o2, %o2
33926! move %l7(lower) -> %o3(upper)
33927sllx %l7, 32, %o3
33928add %l4, 1, %l4
33929
33930P2924: !_MEMBAR (FP)
33931
33932P2925: !_BSTC [15] (maybe <- 0x40800128) (FP) (Branch target of P2480)
33933wr %g0, 0xe0, %asi
33934! preparing store val #0, next val will be in f32
33935fmovs %f16, %f20
33936fadds %f16, %f17, %f16
33937! preparing store val #1, next val will be in f33
33938fmovs %f16, %f21
33939fadds %f16, %f17, %f16
33940! preparing store val #2, next val will be in f35
33941fmovd %f20, %f32
33942fmovs %f16, %f21
33943fadds %f16, %f17, %f16
33944fmovd %f20, %f34
33945membar #Sync
33946stda %f32, [%i3 + 0 ] %asi
33947ba P2926
33948nop
33949
33950TARGET2480:
33951ba RET2480
33952nop
33953
33954
33955P2926: !_MEMBAR (FP)
33956membar #StoreLoad
33957
33958P2927: !_LD [2] (Int)
33959lduw [%i0 + 12], %o5
33960! move %o5(lower) -> %o3(lower)
33961or %o5, %o3, %o3
33962
33963P2928: !_LD [6] (Int)
33964sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
33965sub %i0, %i2, %i2
33966lduw [%i2 + 0], %o4
33967! move %o4(lower) -> %o4(upper)
33968sllx %o4, 32, %o4
33969
33970P2929: !_ST_BINIT [13] (maybe <- 0x100015a) (Int)
33971wr %g0, 0xe2, %asi
33972sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
33973sub %i0, %i3, %i3
33974stwa %l4, [%i3 + 4] %asi
33975add %l4, 1, %l4
33976
33977P2930: !_MEMBAR (Int) (Branch target of P2314)
33978membar #StoreLoad
33979ba P2931
33980nop
33981
33982TARGET2314:
33983ba RET2314
33984nop
33985
33986
33987P2931: !_DWST_BINIT [11] (maybe <- 0x100015b) (Int)
33988wr %g0, 0xe2, %asi
33989sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
33990add %i0, %i2, %i2
33991mov %l4, %l6
33992stxa %l6, [%i2 + 8] %asi
33993add %l4, 1, %l4
33994
33995P2932: !_MEMBAR (Int)
33996membar #StoreLoad
33997
33998P2933: !_DWST [2] (maybe <- 0x100015c) (Int)
33999mov %l4, %l3
34000stx %l3, [%i0 + 8]
34001add %l4, 1, %l4
34002
34003P2934: !_MEMBAR (FP)
34004membar #StoreLoad
34005
34006P2935: !_BLD [19] (FP)
34007wr %g0, 0xf0, %asi
34008sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
34009sub %i0, %i3, %i3
34010ldda [%i3 + 0] %asi, %f32
34011membar #Sync
34012! 3 addresses covered
34013fmovd %f32, %f18
34014fmovs %f18, %f1
34015fmovs %f19, %f2
34016fmovd %f34, %f18
34017fmovs %f19, %f3
34018
34019P2936: !_MEMBAR (FP)
34020
34021P2937: !_SWAP [23] (maybe <- 0x100015d) (Int)
34022sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
34023sub %i0, %i2, %i2
34024mov %l4, %l6
34025swap [%i2 + 12], %l6
34026! move %l6(lower) -> %o4(lower)
34027srl %l6, 0, %o5
34028or %o5, %o4, %o4
34029!---- flushing int results buffer----
34030mov %o0, %l5
34031mov %o1, %l5
34032mov %o2, %l5
34033mov %o3, %l5
34034mov %o4, %l5
34035add %l4, 1, %l4
34036
34037P2938: !_MEMBAR (FP)
34038
34039P2939: !_BSTC [23] (maybe <- 0x4080012b) (FP)
34040wr %g0, 0xe0, %asi
34041! preparing store val #0, next val will be in f32
34042fmovs %f16, %f20
34043fadds %f16, %f17, %f16
34044! preparing store val #1, next val will be in f33
34045fmovs %f16, %f21
34046fadds %f16, %f17, %f16
34047! preparing store val #2, next val will be in f35
34048fmovd %f20, %f32
34049fmovs %f16, %f21
34050fadds %f16, %f17, %f16
34051fmovd %f20, %f34
34052membar #Sync
34053stda %f32, [%i2 + 0 ] %asi
34054
34055P2940: !_MEMBAR (FP) (CBR)
34056membar #StoreLoad
34057
34058! cbranch
34059andcc %l0, 1, %g0
34060be,pt %xcc, TARGET2940
34061nop
34062RET2940:
34063
34064! lfsr step begin
34065srlx %l0, 1, %l6
34066xnor %l6, %l0, %l6
34067sllx %l6, 63, %l6
34068or %l6, %l0, %l0
34069srlx %l0, 1, %l0
34070
34071
34072P2941: !_CAS [21] (maybe <- 0x100015e) (Int)
34073lduw [%i2], %o0
34074mov %o0, %l7
34075! move %l7(lower) -> %o0(upper)
34076sllx %l7, 32, %o0
34077mov %l4, %l6
34078cas [%i2], %l7, %l6
34079! move %l6(lower) -> %o0(lower)
34080srl %l6, 0, %l7
34081or %l7, %o0, %o0
34082add %l4, 1, %l4
34083
34084P2942: !_ST [20] (maybe <- 0x100015f) (Int)
34085stw %l4, [%i3 + 12 ]
34086add %l4, 1, %l4
34087
34088P2943: !_MEMBAR (FP)
34089
34090P2944: !_BST [1] (maybe <- 0x4080012e) (FP)
34091wr %g0, 0xf0, %asi
34092! preparing store val #0, next val will be in f32
34093fmovs %f16, %f20
34094fadds %f16, %f17, %f16
34095! preparing store val #1, next val will be in f33
34096fmovs %f16, %f21
34097fadds %f16, %f17, %f16
34098! preparing store val #2, next val will be in f35
34099fmovd %f20, %f32
34100fmovs %f16, %f21
34101fadds %f16, %f17, %f16
34102fmovd %f20, %f34
34103membar #Sync
34104stda %f32, [%i0 + 0 ] %asi
34105
34106P2945: !_MEMBAR (FP)
34107membar #StoreLoad
34108
34109P2946: !_REPLACEMENT [15] (Int)
34110sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
34111sub %i0, %i3, %i3
34112sethi %hi(0x20000), %l3
34113ld [%i3+0], %l7
34114st %l7, [%i3+0]
34115add %i3, %l3, %l6
34116ld [%l6+0], %l7
34117st %l7, [%l6+0]
34118add %l6, %l3, %l6
34119ld [%l6+0], %l7
34120st %l7, [%l6+0]
34121add %l6, %l3, %l6
34122ld [%l6+0], %l7
34123st %l7, [%l6+0]
34124add %l6, %l3, %l6
34125ld [%l6+0], %l7
34126st %l7, [%l6+0]
34127add %l6, %l3, %l6
34128ld [%l6+0], %l7
34129st %l7, [%l6+0]
34130add %l6, %l3, %l6
34131ld [%l6+0], %l7
34132st %l7, [%l6+0]
34133add %l6, %l3, %l6
34134ld [%l6+0], %l7
34135st %l7, [%l6+0]
34136
34137P2947: !_LDD [10] (Int) (Branch target of P2801)
34138sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
34139add %i0, %i2, %i2
34140ldd [%i2 + 0], %l6
34141! move %l6(lower) -> %o1(upper)
34142sllx %l6, 32, %o1
34143! move %l7(lower) -> %o1(lower)
34144or %l7, %o1, %o1
34145ba P2948
34146nop
34147
34148TARGET2801:
34149ba RET2801
34150nop
34151
34152
34153P2948: !_MEMBAR (FP)
34154
34155P2949: !_BST [13] (maybe <- 0x40800131) (FP)
34156wr %g0, 0xf0, %asi
34157sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
34158sub %i0, %i3, %i3
34159! preparing store val #0, next val will be in f32
34160fmovs %f16, %f20
34161fadds %f16, %f17, %f16
34162! preparing store val #1, next val will be in f33
34163fmovs %f16, %f21
34164fadds %f16, %f17, %f16
34165! preparing store val #2, next val will be in f35
34166fmovd %f20, %f32
34167fmovs %f16, %f21
34168fadds %f16, %f17, %f16
34169fmovd %f20, %f34
34170membar #Sync
34171stda %f32, [%i3 + 0 ] %asi
34172
34173P2950: !_MEMBAR (FP)
34174membar #StoreLoad
34175
34176P2951: !_DWLD [8] (Int)
34177sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
34178sub %i0, %i2, %i2
34179ldx [%i2 + 8], %o2
34180! move %o2(lower) -> %o2(upper)
34181sllx %o2, 32, %o2
34182
34183P2952: !_ST_BINIT [16] (maybe <- 0x1000160) (Int)
34184wr %g0, 0xe2, %asi
34185sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
34186sub %i0, %i3, %i3
34187stwa %l4, [%i3 + 4] %asi
34188add %l4, 1, %l4
34189
34190P2953: !_MEMBAR (Int)
34191membar #StoreLoad
34192
34193P2954: !_ST_BINIT [16] (maybe <- 0x1000161) (Int)
34194wr %g0, 0xe2, %asi
34195stwa %l4, [%i3 + 4] %asi
34196add %l4, 1, %l4
34197
34198P2955: !_MEMBAR (Int)
34199membar #StoreLoad
34200
34201P2956: !_ST_BINIT [12] (maybe <- 0x1000162) (Int)
34202wr %g0, 0xe2, %asi
34203sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
34204sub %i0, %i2, %i2
34205stwa %l4, [%i2 + 0] %asi
34206add %l4, 1, %l4
34207
34208P2957: !_MEMBAR (Int)
34209membar #StoreLoad
34210
34211P2958: !_BLD [8] (FP)
34212wr %g0, 0xf0, %asi
34213sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
34214sub %i0, %i3, %i3
34215ldda [%i3 + 0] %asi, %f32
34216membar #Sync
34217! 3 addresses covered
34218fmovd %f32, %f4
34219fmovd %f34, %f18
34220fmovs %f19, %f6
34221
34222P2959: !_MEMBAR (FP) (CBR)
34223
34224! cbranch
34225andcc %l0, 1, %g0
34226be,pt %xcc, TARGET2959
34227nop
34228RET2959:
34229
34230! lfsr step begin
34231srlx %l0, 1, %l7
34232xnor %l7, %l0, %l7
34233sllx %l7, 63, %l7
34234or %l7, %l0, %l0
34235srlx %l0, 1, %l0
34236
34237
34238P2960: !_LDD [21] (Int)
34239sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
34240sub %i0, %i2, %i2
34241ldd [%i2 + 0], %l6
34242! move %l6(lower) -> %o2(lower)
34243or %l6, %o2, %o2
34244! move %l7(lower) -> %o3(upper)
34245sllx %l7, 32, %o3
34246
34247P2961: !_LD [0] (Int)
34248lduw [%i0 + 0], %l6
34249! move %l6(lower) -> %o3(lower)
34250or %l6, %o3, %o3
34251
34252P2962: !_CAS [23] (maybe <- 0x1000163) (Int)
34253add %i2, 12, %o5
34254lduw [%o5], %o4
34255mov %o4, %l7
34256! move %l7(lower) -> %o4(upper)
34257sllx %l7, 32, %o4
34258mov %l4, %l6
34259cas [%o5], %l7, %l6
34260! move %l6(lower) -> %o4(lower)
34261srl %l6, 0, %l7
34262or %l7, %o4, %o4
34263!---- flushing int results buffer----
34264mov %o0, %l5
34265mov %o1, %l5
34266mov %o2, %l5
34267mov %o3, %l5
34268mov %o4, %l5
34269add %l4, 1, %l4
34270
34271P2963: !_LDD [2] (Int)
34272ldd [%i0 + 8], %l6
34273! move %l7(lower) -> %o0(upper)
34274sllx %l7, 32, %o0
34275
34276P2964: !_MEMBAR (FP)
34277
34278P2965: !_BST [5] (maybe <- 0x40800134) (FP)
34279wr %g0, 0xf0, %asi
34280! preparing store val #0, next val will be in f32
34281fmovs %f16, %f20
34282fadds %f16, %f17, %f16
34283! preparing store val #1, next val will be in f33
34284fmovs %f16, %f21
34285fadds %f16, %f17, %f16
34286! preparing store val #2, next val will be in f35
34287fmovd %f20, %f32
34288fmovs %f16, %f21
34289fadds %f16, %f17, %f16
34290fmovd %f20, %f34
34291membar #Sync
34292stda %f32, [%i1 + 0 ] %asi
34293
34294P2966: !_MEMBAR (FP)
34295membar #StoreLoad
34296
34297P2967: !_DWST_BINIT [11] (maybe <- 0x1000164) (Int)
34298wr %g0, 0xe2, %asi
34299sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
34300add %i0, %i3, %i3
34301mov %l4, %o5
34302stxa %o5, [%i3 + 8] %asi
34303add %l4, 1, %l4
34304
34305P2968: !_MEMBAR (Int) (CBR)
34306membar #StoreLoad
34307
34308! cbranch
34309andcc %l0, 1, %g0
34310be,pt %xcc, TARGET2968
34311nop
34312RET2968:
34313
34314! lfsr step begin
34315srlx %l0, 1, %l7
34316xnor %l7, %l0, %l7
34317sllx %l7, 63, %l7
34318or %l7, %l0, %l0
34319srlx %l0, 1, %l0
34320
34321
34322P2969: !_DWST [0] (maybe <- 0x1000165) (Int)
34323sllx %l4, 32, %o5
34324add %l4, 1, %l4
34325or %o5, %l4, %o5
34326stx %o5, [%i0 + 0]
34327add %l4, 1, %l4
34328
34329P2970: !_DWST [22] (maybe <- 0x1000167) (Int)
34330sllx %l4, 32, %l7
34331add %l4, 1, %l4
34332or %l7, %l4, %l7
34333stx %l7, [%i2 + 0]
34334add %l4, 1, %l4
34335
34336P2971: !_REPLACEMENT [15] (Int)
34337sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
34338add %i0, %i2, %i2
34339sethi %hi(0x20000), %l6
34340ld [%i2+0], %o5
34341st %o5, [%i2+0]
34342add %i2, %l6, %l7
34343ld [%l7+0], %o5
34344st %o5, [%l7+0]
34345add %l7, %l6, %l7
34346ld [%l7+0], %o5
34347st %o5, [%l7+0]
34348add %l7, %l6, %l7
34349ld [%l7+0], %o5
34350st %o5, [%l7+0]
34351add %l7, %l6, %l7
34352ld [%l7+0], %o5
34353st %o5, [%l7+0]
34354add %l7, %l6, %l7
34355ld [%l7+0], %o5
34356st %o5, [%l7+0]
34357add %l7, %l6, %l7
34358ld [%l7+0], %o5
34359st %o5, [%l7+0]
34360add %l7, %l6, %l7
34361ld [%l7+0], %o5
34362st %o5, [%l7+0]
34363
34364P2972: !_DWLD [2] (Int)
34365ldx [%i0 + 8], %l6
34366! move %l6(lower) -> %o0(lower)
34367srl %l6, 0, %l3
34368or %l3, %o0, %o0
34369
34370P2973: !_SWAP [3] (maybe <- 0x1000169) (Int)
34371mov %l4, %o1
34372swap [%i1 + 0], %o1
34373! move %o1(lower) -> %o1(upper)
34374sllx %o1, 32, %o1
34375add %l4, 1, %l4
34376
34377P2974: !_ST_BINIT [12] (maybe <- 0x100016a) (Int)
34378wr %g0, 0xe2, %asi
34379sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
34380sub %i0, %i3, %i3
34381stwa %l4, [%i3 + 0] %asi
34382add %l4, 1, %l4
34383
34384P2975: !_MEMBAR (Int)
34385membar #StoreLoad
34386
34387P2976: !_BLD [20] (FP) (Branch target of P2443)
34388wr %g0, 0xf0, %asi
34389sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
34390sub %i0, %i2, %i2
34391ldda [%i2 + 0] %asi, %f32
34392membar #Sync
34393! 3 addresses covered
34394fmovd %f32, %f18
34395fmovs %f18, %f7
34396fmovs %f19, %f8
34397fmovd %f34, %f18
34398fmovs %f19, %f9
34399ba P2977
34400nop
34401
34402TARGET2443:
34403ba RET2443
34404nop
34405
34406
34407P2977: !_MEMBAR (FP)
34408
34409P2978: !_REPLACEMENT [18] (Int)
34410sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
34411sub %i0, %i3, %i3
34412sethi %hi(0x20000), %l3
34413ld [%i3+0], %l7
34414st %l7, [%i3+0]
34415add %i3, %l3, %l6
34416ld [%l6+0], %l7
34417st %l7, [%l6+0]
34418add %l6, %l3, %l6
34419ld [%l6+0], %l7
34420st %l7, [%l6+0]
34421add %l6, %l3, %l6
34422ld [%l6+0], %l7
34423st %l7, [%l6+0]
34424add %l6, %l3, %l6
34425ld [%l6+0], %l7
34426st %l7, [%l6+0]
34427add %l6, %l3, %l6
34428ld [%l6+0], %l7
34429st %l7, [%l6+0]
34430add %l6, %l3, %l6
34431ld [%l6+0], %l7
34432st %l7, [%l6+0]
34433add %l6, %l3, %l6
34434ld [%l6+0], %l7
34435st %l7, [%l6+0]
34436
34437P2979: !_ST [0] (maybe <- 0x100016b) (Int)
34438stw %l4, [%i0 + 0 ]
34439add %l4, 1, %l4
34440
34441P2980: !_DWST_BINIT [13] (maybe <- 0x100016c) (Int)
34442wr %g0, 0xe2, %asi
34443sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
34444sub %i0, %i2, %i2
34445sllx %l4, 32, %l7
34446add %l4, 1, %l4
34447or %l7, %l4, %l7
34448stxa %l7, [%i2 + 0] %asi
34449add %l4, 1, %l4
34450
34451P2981: !_MEMBAR (Int)
34452membar #StoreLoad
34453
34454P2982: !_BLD [12] (FP)
34455wr %g0, 0xf0, %asi
34456ldda [%i2 + 0] %asi, %f32
34457membar #Sync
34458! 3 addresses covered
34459fmovd %f32, %f10
34460fmovd %f34, %f18
34461fmovs %f19, %f12
34462
34463P2983: !_MEMBAR (FP)
34464
34465P2984: !_BST [14] (maybe <- 0x40800137) (FP)
34466wr %g0, 0xf0, %asi
34467! preparing store val #0, next val will be in f32
34468fmovs %f16, %f20
34469fadds %f16, %f17, %f16
34470! preparing store val #1, next val will be in f33
34471fmovs %f16, %f21
34472fadds %f16, %f17, %f16
34473! preparing store val #2, next val will be in f35
34474fmovd %f20, %f32
34475fmovs %f16, %f21
34476fadds %f16, %f17, %f16
34477fmovd %f20, %f34
34478membar #Sync
34479stda %f32, [%i2 + 0 ] %asi
34480
34481P2985: !_MEMBAR (FP)
34482membar #StoreLoad
34483
34484P2986: !_CAS [7] (maybe <- 0x100016e) (Int)
34485sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
34486sub %i0, %i3, %i3
34487add %i3, 4, %l6
34488lduw [%l6], %o5
34489mov %o5, %l3
34490! move %l3(lower) -> %o1(lower)
34491or %l3, %o1, %o1
34492mov %l4, %o2
34493cas [%l6], %l3, %o2
34494! move %o2(lower) -> %o2(upper)
34495sllx %o2, 32, %o2
34496add %l4, 1, %l4
34497
34498P2987: !_DWST [0] (maybe <- 0x100016f) (Int)
34499sllx %l4, 32, %l3
34500add %l4, 1, %l4
34501or %l3, %l4, %l3
34502stx %l3, [%i0 + 0]
34503add %l4, 1, %l4
34504
34505P2988: !_SWAP [12] (maybe <- 0x1000171) (Int)
34506mov %l4, %l6
34507swap [%i2 + 0], %l6
34508! move %l6(lower) -> %o2(lower)
34509srl %l6, 0, %o5
34510or %o5, %o2, %o2
34511add %l4, 1, %l4
34512
34513P2989: !_MEMBAR (FP)
34514membar #StoreLoad
34515
34516P2990: !_BLD [15] (FP)
34517wr %g0, 0xf0, %asi
34518sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
34519sub %i0, %i2, %i2
34520ldda [%i2 + 0] %asi, %f32
34521membar #Sync
34522! 3 addresses covered
34523fmovd %f32, %f18
34524fmovs %f18, %f13
34525fmovs %f19, %f14
34526fmovd %f34, %f18
34527fmovs %f19, %f15
34528!---- flushing fp results buffer to %f30 ----
34529fmovd %f0, %f30
34530fmovd %f2, %f30
34531fmovd %f4, %f30
34532fmovd %f6, %f30
34533fmovd %f8, %f30
34534fmovd %f10, %f30
34535fmovd %f12, %f30
34536fmovd %f14, %f30
34537!--
34538
34539P2991: !_MEMBAR (FP)
34540
34541P2992: !_CASX [23] (maybe <- 0x1000172) (Int)
34542sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
34543sub %i0, %i3, %i3
34544add %i3, 8, %o5
34545ldx [%o5], %o3
34546! move %o3(upper) -> %o3(upper)
34547! move %o3(lower) -> %o3(lower)
34548mov %o3, %l7
34549mov %l4, %o4
34550casx [%o5], %l7, %o4
34551! move %o4(upper) -> %o4(upper)
34552! move %o4(lower) -> %o4(lower)
34553!---- flushing int results buffer----
34554mov %o0, %l5
34555mov %o1, %l5
34556mov %o2, %l5
34557mov %o3, %l5
34558mov %o4, %l5
34559add %l4, 1, %l4
34560
34561P2993: !_LDD [16] (Int)
34562ldd [%i2 + 0], %l6
34563! move %l6(lower) -> %o0(upper)
34564sllx %l6, 32, %o0
34565! move %l7(lower) -> %o0(lower)
34566or %l7, %o0, %o0
34567
34568P2994: !_ST_BINIT [20] (maybe <- 0x1000173) (Int)
34569wr %g0, 0xe2, %asi
34570sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
34571sub %i0, %i2, %i2
34572stwa %l4, [%i2 + 12] %asi
34573add %l4, 1, %l4
34574
34575P2995: !_MEMBAR (Int)
34576membar #StoreLoad
34577
34578P2996: !_LDD [0] (Int)
34579ldd [%i0 + 0], %l6
34580! move %l6(lower) -> %o1(upper)
34581sllx %l6, 32, %o1
34582! move %l7(lower) -> %o1(lower)
34583or %l7, %o1, %o1
34584
34585P2997: !_PREFETCH [13] (Int)
34586sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
34587sub %i0, %i3, %i3
34588prefetch [%i3 + 4], 23
34589
34590P2998: !_ST_BINIT [3] (maybe <- 0x1000174) (Int)
34591wr %g0, 0xe2, %asi
34592stwa %l4, [%i1 + 0] %asi
34593add %l4, 1, %l4
34594
34595P2999: !_MEMBAR (Int)
34596membar #StoreLoad
34597
34598P3000: !_DWST [2] (maybe <- 0x1000175) (Int)
34599mov %l4, %o5
34600stx %o5, [%i0 + 8]
34601add %l4, 1, %l4
34602
34603P3001: !_DWST_BINIT [23] (maybe <- 0x1000176) (Int)
34604wr %g0, 0xe2, %asi
34605sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
34606sub %i0, %i2, %i2
34607mov %l4, %l7
34608stxa %l7, [%i2 + 8] %asi
34609add %l4, 1, %l4
34610
34611P3002: !_MEMBAR (Int)
34612membar #StoreLoad
34613
34614P3003: !_ST_BINIT [14] (maybe <- 0x1000177) (Int) (CBR)
34615wr %g0, 0xe2, %asi
34616stwa %l4, [%i3 + 12] %asi
34617add %l4, 1, %l4
34618
34619! cbranch
34620andcc %l0, 1, %g0
34621be,pn %xcc, TARGET3003
34622nop
34623RET3003:
34624
34625! lfsr step begin
34626srlx %l0, 1, %l3
34627xnor %l3, %l0, %l3
34628sllx %l3, 63, %l3
34629or %l3, %l0, %l0
34630srlx %l0, 1, %l0
34631
34632
34633P3004: !_MEMBAR (Int) (Loop exit)
34634membar #StoreLoad
34635!---- flushing int results buffer----
34636mov %o0, %l5
34637mov %o1, %l5
34638
34639sethi %hi(0x200000), %l6
34640add %i1, %l6, %i1
34641!-- End Aliased access: base register for region 1 (%i1) restored
34642loop_exit_2_0:
34643sub %l2, 1, %l2
34644cmp %l2, 0
34645bg loop_entry_2_0
34646nop
34647
34648P3005: !_MEMBAR (Int)
34649membar #StoreLoad
34650
34651END_NODES2: ! Test instruction sequence for CPU 2 ends
34652sethi %hi(0xdead0e0f), %l7
34653or %l7, %lo(0xdead0e0f), %l7
34654! move %l7(lower) -> %o0(upper)
34655sllx %l7, 32, %o0
34656sethi %hi(0xdead0e0f), %l7
34657or %l7, %lo(0xdead0e0f), %l7
34658stw %l7, [%i5]
34659ld [%i5], %f0
34660!---- flushing int results buffer----
34661mov %o0, %l5
34662!---- flushing fp results buffer to %f30 ----
34663fmovs %f0, %f30
34664!--
34665
34666restore
34667retl
34668nop
34669!-----------------
34670
34671! register usage:
34672! %i0 %i1 : base registers for first 2 regions
34673! %i2 %i3 : cache registers for 8 regions
34674! %i4 fixed pointer to per-cpu results area
34675! %l1 moving pointer to per-cpu FP results area
34676! %o7 moving pointer to per-cpu integer results area
34677! %i5 pointer to per-cpu private area
34678! %l0 holds lfsr, used as source of random bits
34679! %l2 loop count register
34680! %f16 running counter for unique fp store values
34681! %f17 holds increment value for fp counter
34682! %l4 running counter for unique integer store values (increment value is always 1)
34683! %l5 move-to register for load values (simulation only)
34684! %f30 move-to register for FP values (simulation only)
34685! %i4 holds the instructions count which is used for interrupt ordering
34686! %i4 holds the thread_id (OBP only)
34687! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage
34688! %l3 %l6 %l7 %o5 : 4 temporary registers
34689! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
34690! %f0-f15 FP results buffer registers
34691! %f32-f47 FP block load/store registers
34692
34693func3:
34694! instruction sequence begins
34695save %sp, -192, %sp
34696
34697! Force %i0-%i3 to be 64-byte aligned
34698add %i0, 63, %i0
34699andn %i0, 63, %i0
34700
34701add %i1, 63, %i1
34702andn %i1, 63, %i1
34703
34704add %i2, 63, %i2
34705andn %i2, 63, %i2
34706
34707add %i3, 63, %i3
34708andn %i3, 63, %i3
34709
34710add %i4, 63, %i4
34711andn %i4, 63, %i4
34712
34713add %i5, 63, %i5
34714andn %i5, 63, %i5
34715
34716
34717! Initialize pointer to FP load results area
34718mov %i4, %l1
34719
34720! Initialize pointer to integer load results area
34721sethi %hi(0x80000), %o7
34722or %o7, %lo(0x80000), %o7
34723add %o7, %l1, %o7
34724
34725! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info
34726mov 0x0, %i4
34727
34728! Initialize %f0-%f62 to 0xdeadbee0deadbee1
34729sethi %hi(0xdeadbee0), %l6
34730or %l6, %lo(0xdeadbee0), %l6
34731stw %l6, [%i5]
34732sethi %hi(0xdeadbee1), %l6
34733or %l6, %lo(0xdeadbee1), %l6
34734stw %l6, [%i5+4]
34735ldd [%i5], %f0
34736fmovd %f0, %f2
34737fmovd %f0, %f4
34738fmovd %f0, %f6
34739fmovd %f0, %f8
34740fmovd %f0, %f10
34741fmovd %f0, %f12
34742fmovd %f0, %f14
34743fmovd %f0, %f16
34744fmovd %f0, %f18
34745fmovd %f0, %f20
34746fmovd %f0, %f22
34747fmovd %f0, %f24
34748fmovd %f0, %f26
34749fmovd %f0, %f28
34750fmovd %f0, %f30
34751fmovd %f0, %f32
34752fmovd %f0, %f34
34753fmovd %f0, %f36
34754fmovd %f0, %f38
34755fmovd %f0, %f40
34756fmovd %f0, %f42
34757fmovd %f0, %f44
34758fmovd %f0, %f46
34759fmovd %f0, %f48
34760fmovd %f0, %f50
34761fmovd %f0, %f52
34762fmovd %f0, %f54
34763fmovd %f0, %f56
34764fmovd %f0, %f58
34765fmovd %f0, %f60
34766fmovd %f0, %f62
34767
34768! Signature for extract_loads script to start extracting load values for this stream
34769sethi %hi(0x03deade1), %l6
34770or %l6, %lo(0x03deade1), %l6
34771stw %l6, [%i5]
34772ld [%i5], %f16
34773
34774! Initialize running integer counter in register %l4
34775sethi %hi(0x1800001), %l4
34776or %l4, %lo(0x1800001), %l4
34777
34778! Initialize running FP counter in register %f16
34779sethi %hi(0x41000001), %l6
34780or %l6, %lo(0x41000001), %l6
34781stw %l6, [%i5]
34782ld [%i5], %f16
34783
34784! Initialize FP counter increment value in register %f17 (constant)
34785sethi %hi(0x35800000), %l6
34786or %l6, %lo(0x35800000), %l6
34787stw %l6, [%i5]
34788ld [%i5], %f17
34789
34790! Initialize LFSR to 0xe08^4
34791sethi %hi(0xe08), %l0
34792or %l0, %lo(0xe08), %l0
34793mulx %l0, %l0, %l0
34794mulx %l0, %l0, %l0
34795
34796BEGIN_NODES3: ! Test instruction sequence for ISTREAM 3 begins
34797
34798P3006: !_ST_BINIT [0] (maybe <- 0x1800001) (Int) (Loop entry)
34799sethi %hi(0x1), %l2
34800or %l2, %lo(0x1), %l2
34801loop_entry_3_0:
34802wr %g0, 0xe2, %asi
34803stwa %l4, [%i0 + 0] %asi
34804add %l4, 1, %l4
34805
34806P3007: !_MEMBAR (Int)
34807membar #StoreLoad
34808
34809P3008: !_LDD [12] (Int)
34810sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
34811sub %i0, %i3, %i3
34812ldd [%i3 + 0], %l6
34813! move %l6(lower) -> %o0(upper)
34814sllx %l6, 32, %o0
34815! move %l7(lower) -> %o0(lower)
34816or %l7, %o0, %o0
34817
34818P3009: !_CAS [0] (maybe <- 0x1800002) (Int)
34819lduw [%i0], %o1
34820mov %o1, %l3
34821! move %l3(lower) -> %o1(upper)
34822sllx %l3, 32, %o1
34823mov %l4, %o5
34824cas [%i0], %l3, %o5
34825! move %o5(lower) -> %o1(lower)
34826srl %o5, 0, %l3
34827or %l3, %o1, %o1
34828add %l4, 1, %l4
34829
34830P3010: !_CASX [6] (maybe <- 0x1800003) (Int) (LE)
34831sllx %l4, 32, %l6
34832add %l4, 1, %l4
34833or %l4, %l6, %l6
34834! Change double-word-level endianess (big endian <-> little endian)
34835sethi %hi(0xff00ff00), %l3
34836or %l3, %lo(0xff00ff00), %l3
34837sllx %l3, 32, %l7
34838or %l3, %l7, %l3
34839and %l6, %l3, %l7
34840srlx %l7, 8, %l7
34841sllx %l6, 8, %l6
34842and %l6, %l3, %l6
34843or %l6, %l7, %l6
34844sethi %hi(0xffff0000), %l3
34845srlx %l6, 16, %l7
34846andn %l7, %l3, %l7
34847andn %l6, %l3, %l6
34848sllx %l6, 16, %l6
34849or %l6, %l7, %l6
34850srlx %l6, 32, %l7
34851sllx %l6, 32, %l6
34852or %l6, %l7, %l7
34853wr %g0, 0x88, %asi
34854sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
34855sub %i0, %i2, %i2
34856ldxa [%i2] %asi, %o5
34857! move %o5(lower) -> %o2(upper)
34858sllx %o5, 32, %o2
34859! move %o5(upper) -> %o2(lower)
34860srlx %o5, 32, %l3
34861or %l3, %o2, %o2
34862mov %o5, %l3
34863mov %l7, %o5
34864casxa [%i2] %asi, %l3, %o5
34865! move %o5(lower) -> %o3(upper)
34866sllx %o5, 32, %o3
34867! move %o5(upper) -> %o3(lower)
34868srlx %o5, 32, %l3
34869or %l3, %o3, %o3
34870add %l4, 1, %l4
34871
34872P3011: !_DWST_BINIT [4] (maybe <- 0x1800005) (Int)
34873wr %g0, 0xe2, %asi
34874sllx %l4, 32, %l3
34875add %l4, 1, %l4
34876or %l3, %l4, %l3
34877stxa %l3, [%i1 + 0] %asi
34878add %l4, 1, %l4
34879
34880P3012: !_MEMBAR (Int)
34881membar #StoreLoad
34882
34883P3013: !_LDD [12] (Int)
34884ldd [%i3 + 0], %l6
34885! move %l6(lower) -> %o4(upper)
34886sllx %l6, 32, %o4
34887! move %l7(lower) -> %o4(lower)
34888or %l7, %o4, %o4
34889!---- flushing int results buffer----
34890mov %o0, %l5
34891mov %o1, %l5
34892mov %o2, %l5
34893mov %o3, %l5
34894mov %o4, %l5
34895
34896P3014: !_ST_BINIT [11] (maybe <- 0x1800007) (Int)
34897wr %g0, 0xe2, %asi
34898sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
34899add %i0, %i3, %i3
34900stwa %l4, [%i3 + 12] %asi
34901add %l4, 1, %l4
34902
34903P3015: !_MEMBAR (Int)
34904membar #StoreLoad
34905
34906P3016: !_REPLACEMENT [0] (Int)
34907sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
34908sub %i0, %i2, %i2
34909sethi %hi(0x20000), %o5
34910ld [%i2+0], %l6
34911st %l6, [%i2+0]
34912add %i2, %o5, %l3
34913ld [%l3+0], %l6
34914st %l6, [%l3+0]
34915add %l3, %o5, %l3
34916ld [%l3+0], %l6
34917st %l6, [%l3+0]
34918add %l3, %o5, %l3
34919ld [%l3+0], %l6
34920st %l6, [%l3+0]
34921add %l3, %o5, %l3
34922ld [%l3+0], %l6
34923st %l6, [%l3+0]
34924add %l3, %o5, %l3
34925ld [%l3+0], %l6
34926st %l6, [%l3+0]
34927add %l3, %o5, %l3
34928ld [%l3+0], %l6
34929st %l6, [%l3+0]
34930add %l3, %o5, %l3
34931ld [%l3+0], %l6
34932st %l6, [%l3+0]
34933
34934P3017: !_LD [22] (Int)
34935sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
34936sub %i0, %i3, %i3
34937lduw [%i3 + 4], %o0
34938! move %o0(lower) -> %o0(upper)
34939sllx %o0, 32, %o0
34940
34941P3018: !_PREFETCH [21] (Int)
34942prefetch [%i3 + 0], 22
34943
34944P3019: !_MEMBAR (FP)
34945
34946P3020: !_BSTC [19] (maybe <- 0x41000001) (FP)
34947wr %g0, 0xe0, %asi
34948sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
34949sub %i0, %i2, %i2
34950! preparing store val #0, next val will be in f32
34951fmovs %f16, %f20
34952fadds %f16, %f17, %f16
34953! preparing store val #1, next val will be in f33
34954fmovs %f16, %f21
34955fadds %f16, %f17, %f16
34956! preparing store val #2, next val will be in f35
34957fmovd %f20, %f32
34958fmovs %f16, %f21
34959fadds %f16, %f17, %f16
34960fmovd %f20, %f34
34961membar #Sync
34962stda %f32, [%i2 + 0 ] %asi
34963
34964P3021: !_MEMBAR (FP)
34965membar #StoreLoad
34966
34967P3022: !_SWAP [3] (maybe <- 0x1800008) (Int)
34968mov %l4, %l6
34969swap [%i1 + 0], %l6
34970! move %l6(lower) -> %o0(lower)
34971srl %l6, 0, %o5
34972or %o5, %o0, %o0
34973add %l4, 1, %l4
34974
34975P3023: !_DWLD [11] (FP)
34976sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
34977add %i0, %i3, %i3
34978ldd [%i3 + 8], %f0
34979! 1 addresses covered
34980fmovs %f1, %f0
34981
34982P3024: !_SWAP [10] (maybe <- 0x1800009) (Int)
34983mov %l4, %o1
34984swap [%i3 + 4], %o1
34985! move %o1(lower) -> %o1(upper)
34986sllx %o1, 32, %o1
34987add %l4, 1, %l4
34988
34989P3025: !_DWLD [14] (FP) (CBR)
34990sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
34991sub %i0, %i2, %i2
34992ldd [%i2 + 8], %f18
34993! 1 addresses covered
34994fmovs %f19, %f1
34995
34996! cbranch
34997andcc %l0, 1, %g0
34998be,pn %xcc, TARGET3025
34999nop
35000RET3025:
35001
35002! lfsr step begin
35003srlx %l0, 1, %l6
35004xnor %l6, %l0, %l6
35005sllx %l6, 63, %l6
35006or %l6, %l0, %l0
35007srlx %l0, 1, %l0
35008
35009
35010P3026: !_ST [16] (maybe <- 0x180000a) (Int)
35011sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
35012sub %i0, %i3, %i3
35013stw %l4, [%i3 + 4 ]
35014add %l4, 1, %l4
35015
35016P3027: !_ST [22] (maybe <- 0x180000b) (Int)
35017sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
35018sub %i0, %i2, %i2
35019stw %l4, [%i2 + 4 ]
35020add %l4, 1, %l4
35021
35022P3028: !_DWST_BINIT [23] (maybe <- 0x180000c) (Int)
35023wr %g0, 0xe2, %asi
35024mov %l4, %l3
35025stxa %l3, [%i2 + 8] %asi
35026add %l4, 1, %l4
35027
35028P3029: !_MEMBAR (Int)
35029membar #StoreLoad
35030
35031P3030: !_DWST_BINIT [3] (maybe <- 0x180000d) (Int)
35032wr %g0, 0xe2, %asi
35033sllx %l4, 32, %o5
35034add %l4, 1, %l4
35035or %o5, %l4, %o5
35036stxa %o5, [%i1 + 0] %asi
35037add %l4, 1, %l4
35038
35039P3031: !_MEMBAR (Int)
35040membar #StoreLoad
35041
35042P3032: !_CASX [5] (maybe <- 0x180000f) (Int)
35043add %i1, 8, %o5
35044ldx [%o5], %l6
35045! move %l6(upper) -> %o1(lower)
35046srlx %l6, 32, %l7
35047or %l7, %o1, %o1
35048! move %l6(lower) -> %o2(upper)
35049sllx %l6, 32, %o2
35050mov %l6, %l7
35051mov %l4, %l6
35052casx [%o5], %l7, %l6
35053! move %l6(upper) -> %o2(lower)
35054srlx %l6, 32, %l7
35055or %l7, %o2, %o2
35056! move %l6(lower) -> %o3(upper)
35057sllx %l6, 32, %o3
35058add %l4, 1, %l4
35059
35060P3033: !_DWST [19] (maybe <- 0x1800010) (Int)
35061sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
35062sub %i0, %i3, %i3
35063sllx %l4, 32, %l7
35064add %l4, 1, %l4
35065or %l7, %l4, %l7
35066stx %l7, [%i3 + 0]
35067add %l4, 1, %l4
35068
35069P3034: !_DWST [2] (maybe <- 0x1800012) (Int) (Branch target of P3256)
35070mov %l4, %l6
35071stx %l6, [%i0 + 8]
35072add %l4, 1, %l4
35073ba P3035
35074nop
35075
35076TARGET3256:
35077ba RET3256
35078nop
35079
35080
35081P3035: !_MEMBAR (FP) (CBR)
35082
35083! cbranch
35084andcc %l0, 1, %g0
35085be,pn %xcc, TARGET3035
35086nop
35087RET3035:
35088
35089! lfsr step begin
35090srlx %l0, 1, %l3
35091xnor %l3, %l0, %l3
35092sllx %l3, 63, %l3
35093or %l3, %l0, %l0
35094srlx %l0, 1, %l0
35095
35096
35097P3036: !_BST [20] (maybe <- 0x41000004) (FP)
35098wr %g0, 0xf0, %asi
35099! preparing store val #0, next val will be in f32
35100fmovs %f16, %f20
35101fadds %f16, %f17, %f16
35102! preparing store val #1, next val will be in f33
35103fmovs %f16, %f21
35104fadds %f16, %f17, %f16
35105! preparing store val #2, next val will be in f35
35106fmovd %f20, %f32
35107fmovs %f16, %f21
35108fadds %f16, %f17, %f16
35109fmovd %f20, %f34
35110membar #Sync
35111stda %f32, [%i3 + 0 ] %asi
35112
35113P3037: !_MEMBAR (FP)
35114membar #StoreLoad
35115
35116P3038: !_DWST_BINIT [22] (maybe <- 0x1800013) (Int)
35117wr %g0, 0xe2, %asi
35118sllx %l4, 32, %l3
35119add %l4, 1, %l4
35120or %l3, %l4, %l3
35121stxa %l3, [%i2 + 0] %asi
35122add %l4, 1, %l4
35123
35124P3039: !_MEMBAR (Int)
35125membar #StoreLoad
35126
35127P3040: !_LDD [20] (Int)
35128ldd [%i3 + 8], %l6
35129! move %l7(lower) -> %o3(lower)
35130or %l7, %o3, %o3
35131
35132P3041: !_PREFETCH [9] (Int)
35133sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
35134add %i0, %i2, %i2
35135prefetch [%i2 + 0], 0
35136
35137P3042: !_MEMBAR (FP)
35138membar #StoreLoad
35139
35140P3043: !_BLD [4] (FP)
35141wr %g0, 0xf0, %asi
35142ldda [%i1 + 0] %asi, %f32
35143membar #Sync
35144! 3 addresses covered
35145fmovd %f32, %f2
35146fmovd %f34, %f18
35147fmovs %f19, %f4
35148
35149P3044: !_MEMBAR (FP)
35150
35151P3045: !_ST_BINIT [0] (maybe <- 0x1800015) (Int)
35152wr %g0, 0xe2, %asi
35153stwa %l4, [%i0 + 0] %asi
35154add %l4, 1, %l4
35155
35156P3046: !_MEMBAR (Int)
35157membar #StoreLoad
35158
35159P3047: !_DWST_BINIT [12] (maybe <- 0x1800016) (Int)
35160wr %g0, 0xe2, %asi
35161sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
35162sub %i0, %i3, %i3
35163sllx %l4, 32, %o5
35164add %l4, 1, %l4
35165or %o5, %l4, %o5
35166stxa %o5, [%i3 + 0] %asi
35167add %l4, 1, %l4
35168
35169P3048: !_MEMBAR (Int)
35170membar #StoreLoad
35171
35172P3049: !_CAS [1] (maybe <- 0x1800018) (Int)
35173add %i0, 4, %o5
35174lduw [%o5], %o4
35175mov %o4, %l7
35176! move %l7(lower) -> %o4(upper)
35177sllx %l7, 32, %o4
35178mov %l4, %l6
35179cas [%o5], %l7, %l6
35180! move %l6(lower) -> %o4(lower)
35181srl %l6, 0, %l7
35182or %l7, %o4, %o4
35183!---- flushing int results buffer----
35184mov %o0, %l5
35185mov %o1, %l5
35186mov %o2, %l5
35187mov %o3, %l5
35188mov %o4, %l5
35189add %l4, 1, %l4
35190
35191P3050: !_SWAP [12] (maybe <- 0x1800019) (Int)
35192mov %l4, %o0
35193swap [%i3 + 0], %o0
35194! move %o0(lower) -> %o0(upper)
35195sllx %o0, 32, %o0
35196add %l4, 1, %l4
35197
35198P3051: !_ST [4] (maybe <- 0x180001a) (Int)
35199stw %l4, [%i1 + 4 ]
35200add %l4, 1, %l4
35201
35202P3052: !_DWST [7] (maybe <- 0x180001b) (Int)
35203sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
35204sub %i0, %i2, %i2
35205sllx %l4, 32, %l3
35206add %l4, 1, %l4
35207or %l3, %l4, %l3
35208stx %l3, [%i2 + 0]
35209add %l4, 1, %l4
35210
35211P3053: !_DWST_BINIT [7] (maybe <- 0x180001d) (Int)
35212wr %g0, 0xe2, %asi
35213sllx %l4, 32, %o5
35214add %l4, 1, %l4
35215or %o5, %l4, %o5
35216stxa %o5, [%i2 + 0] %asi
35217add %l4, 1, %l4
35218
35219P3054: !_MEMBAR (Int)
35220membar #StoreLoad
35221
35222P3055: !_LD [5] (Int)
35223lduw [%i1 + 12], %o5
35224! move %o5(lower) -> %o0(lower)
35225or %o5, %o0, %o0
35226
35227P3056: !_ST_BINIT [2] (maybe <- 0x180001f) (Int)
35228wr %g0, 0xe2, %asi
35229stwa %l4, [%i0 + 12] %asi
35230add %l4, 1, %l4
35231
35232P3057: !_MEMBAR (Int)
35233membar #StoreLoad
35234
35235P3058: !_LD [5] (Int)
35236lduw [%i1 + 12], %o1
35237! move %o1(lower) -> %o1(upper)
35238sllx %o1, 32, %o1
35239
35240P3059: !_PREFETCH [10] (Int)
35241sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
35242add %i0, %i3, %i3
35243prefetch [%i3 + 4], 3
35244
35245P3060: !_DWST_BINIT [15] (maybe <- 0x1800020) (Int)
35246wr %g0, 0xe2, %asi
35247sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
35248sub %i0, %i2, %i2
35249sllx %l4, 32, %l6
35250add %l4, 1, %l4
35251or %l6, %l4, %l6
35252stxa %l6, [%i2 + 0] %asi
35253add %l4, 1, %l4
35254
35255P3061: !_MEMBAR (Int)
35256membar #StoreLoad
35257
35258P3062: !_BLD [21] (FP)
35259wr %g0, 0xf0, %asi
35260sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
35261sub %i0, %i3, %i3
35262ldda [%i3 + 0] %asi, %f32
35263membar #Sync
35264! 3 addresses covered
35265fmovd %f32, %f18
35266fmovs %f18, %f5
35267fmovs %f19, %f6
35268fmovd %f34, %f18
35269fmovs %f19, %f7
35270
35271P3063: !_MEMBAR (FP) (CBR)
35272
35273! cbranch
35274andcc %l0, 1, %g0
35275be,pn %xcc, TARGET3063
35276nop
35277RET3063:
35278
35279! lfsr step begin
35280srlx %l0, 1, %l3
35281xnor %l3, %l0, %l3
35282sllx %l3, 63, %l3
35283or %l3, %l0, %l0
35284srlx %l0, 1, %l0
35285
35286
35287P3064: !_LD [20] (Int) (LE)
35288wr %g0, 0x88, %asi
35289sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
35290sub %i0, %i2, %i2
35291lduwa [%i2 + 12] %asi, %l7
35292! move %l7(lower) -> %o1(lower)
35293or %l7, %o1, %o1
35294
35295P3065: !_DWST_BINIT [15] (maybe <- 0x1800022) (Int)
35296wr %g0, 0xe2, %asi
35297sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
35298sub %i0, %i3, %i3
35299sllx %l4, 32, %o5
35300add %l4, 1, %l4
35301or %o5, %l4, %o5
35302stxa %o5, [%i3 + 0] %asi
35303add %l4, 1, %l4
35304
35305P3066: !_MEMBAR (Int)
35306membar #StoreLoad
35307
35308P3067: !_BLD [6] (FP) (CBR)
35309wr %g0, 0xf0, %asi
35310sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
35311sub %i0, %i2, %i2
35312ldda [%i2 + 0] %asi, %f32
35313membar #Sync
35314! 3 addresses covered
35315fmovd %f32, %f8
35316fmovd %f34, %f18
35317fmovs %f19, %f10
35318
35319! cbranch
35320andcc %l0, 1, %g0
35321be,pt %xcc, TARGET3067
35322nop
35323RET3067:
35324
35325! lfsr step begin
35326srlx %l0, 1, %l7
35327xnor %l7, %l0, %l7
35328sllx %l7, 63, %l7
35329or %l7, %l0, %l0
35330srlx %l0, 1, %l0
35331
35332
35333P3068: !_MEMBAR (FP)
35334
35335P3069: !_DWLD [21] (Int)
35336sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
35337add %i0, %i3, %i3
35338ldx [%i3 + 0], %o2
35339! move %o2(upper) -> %o2(upper)
35340! move %o2(lower) -> %o2(lower)
35341
35342P3070: !_DWST [21] (maybe <- 0x1800024) (Int)
35343sllx %l4, 32, %l7
35344add %l4, 1, %l4
35345or %l7, %l4, %l7
35346stx %l7, [%i3 + 0]
35347add %l4, 1, %l4
35348
35349P3071: !_LDD [18] (Int)
35350sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
35351sub %i0, %i2, %i2
35352ldd [%i2 + 0], %l6
35353! move %l6(lower) -> %o3(upper)
35354sllx %l6, 32, %o3
35355! move %l7(lower) -> %o3(lower)
35356or %l7, %o3, %o3
35357
35358P3072: !_CASX [18] (maybe <- 0x1800026) (Int)
35359ldx [%i2], %o4
35360! move %o4(upper) -> %o4(upper)
35361! move %o4(lower) -> %o4(lower)
35362!---- flushing int results buffer----
35363mov %o0, %l5
35364mov %o1, %l5
35365mov %o2, %l5
35366mov %o3, %l5
35367mov %o4, %l5
35368mov %o4, %l3
35369sllx %l4, 32, %o0
35370add %l4, 1, %l4
35371or %l4, %o0, %o0
35372casx [%i2], %l3, %o0
35373! move %o0(upper) -> %o0(upper)
35374! move %o0(lower) -> %o0(lower)
35375add %l4, 1, %l4
35376
35377P3073: !_REPLACEMENT [15] (Int)
35378sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
35379sub %i0, %i3, %i3
35380sethi %hi(0x20000), %l3
35381ld [%i3+0], %l7
35382st %l7, [%i3+0]
35383add %i3, %l3, %l6
35384ld [%l6+0], %l7
35385st %l7, [%l6+0]
35386add %l6, %l3, %l6
35387ld [%l6+0], %l7
35388st %l7, [%l6+0]
35389add %l6, %l3, %l6
35390ld [%l6+0], %l7
35391st %l7, [%l6+0]
35392add %l6, %l3, %l6
35393ld [%l6+0], %l7
35394st %l7, [%l6+0]
35395add %l6, %l3, %l6
35396ld [%l6+0], %l7
35397st %l7, [%l6+0]
35398add %l6, %l3, %l6
35399ld [%l6+0], %l7
35400st %l7, [%l6+0]
35401add %l6, %l3, %l6
35402ld [%l6+0], %l7
35403st %l7, [%l6+0]
35404
35405P3074: !_MEMBAR (FP) (Branch target of P3932)
35406membar #StoreLoad
35407ba P3075
35408nop
35409
35410TARGET3932:
35411ba RET3932
35412nop
35413
35414
35415P3075: !_BLD [22] (FP)
35416wr %g0, 0xf0, %asi
35417sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
35418add %i0, %i2, %i2
35419ldda [%i2 + 0] %asi, %f32
35420membar #Sync
35421! 3 addresses covered
35422fmovd %f32, %f18
35423fmovs %f18, %f11
35424fmovs %f19, %f12
35425fmovd %f34, %f18
35426fmovs %f19, %f13
35427
35428P3076: !_MEMBAR (FP)
35429
35430P3077: !_PREFETCH [12] (Int)
35431sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
35432sub %i0, %i3, %i3
35433prefetch [%i3 + 0], 23
35434
35435P3078: !_SWAP [9] (maybe <- 0x1800028) (Int)
35436sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
35437add %i0, %i2, %i2
35438mov %l4, %o1
35439swap [%i2 + 0], %o1
35440! move %o1(lower) -> %o1(upper)
35441sllx %o1, 32, %o1
35442add %l4, 1, %l4
35443
35444P3079: !_ST [15] (maybe <- 0x1800029) (Int)
35445sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
35446sub %i0, %i3, %i3
35447stw %l4, [%i3 + 0 ]
35448add %l4, 1, %l4
35449
35450P3080: !_LDD [20] (Int)
35451sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
35452sub %i0, %i2, %i2
35453ldd [%i2 + 8], %l6
35454! move %l7(lower) -> %o1(lower)
35455or %l7, %o1, %o1
35456
35457P3081: !_CASX [10] (maybe <- 0x180002a) (Int)
35458sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
35459add %i0, %i3, %i3
35460ldx [%i3], %o2
35461! move %o2(upper) -> %o2(upper)
35462! move %o2(lower) -> %o2(lower)
35463mov %o2, %l3
35464sllx %l4, 32, %o3
35465add %l4, 1, %l4
35466or %l4, %o3, %o3
35467casx [%i3], %l3, %o3
35468! move %o3(upper) -> %o3(upper)
35469! move %o3(lower) -> %o3(lower)
35470add %l4, 1, %l4
35471
35472P3082: !_MEMBAR (FP)
35473
35474P3083: !_BSTC [19] (maybe <- 0x41000007) (FP)
35475wr %g0, 0xe0, %asi
35476! preparing store val #0, next val will be in f32
35477fmovs %f16, %f20
35478fadds %f16, %f17, %f16
35479! preparing store val #1, next val will be in f33
35480fmovs %f16, %f21
35481fadds %f16, %f17, %f16
35482! preparing store val #2, next val will be in f35
35483fmovd %f20, %f32
35484fmovs %f16, %f21
35485fadds %f16, %f17, %f16
35486fmovd %f20, %f34
35487membar #Sync
35488stda %f32, [%i2 + 0 ] %asi
35489
35490P3084: !_MEMBAR (FP)
35491membar #StoreLoad
35492
35493P3085: !_REPLACEMENT [14] (Int)
35494sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
35495sub %i0, %i2, %i2
35496sethi %hi(0x20000), %o5
35497ld [%i2+12], %l6
35498st %l6, [%i2+12]
35499add %i2, %o5, %l3
35500ld [%l3+12], %l6
35501st %l6, [%l3+12]
35502add %l3, %o5, %l3
35503ld [%l3+12], %l6
35504st %l6, [%l3+12]
35505add %l3, %o5, %l3
35506ld [%l3+12], %l6
35507st %l6, [%l3+12]
35508add %l3, %o5, %l3
35509ld [%l3+12], %l6
35510st %l6, [%l3+12]
35511add %l3, %o5, %l3
35512ld [%l3+12], %l6
35513st %l6, [%l3+12]
35514add %l3, %o5, %l3
35515ld [%l3+12], %l6
35516st %l6, [%l3+12]
35517add %l3, %o5, %l3
35518ld [%l3+12], %l6
35519st %l6, [%l3+12]
35520
35521P3086: !_PREFETCH [21] (Int) (LE)
35522wr %g0, 0x88, %asi
35523sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
35524add %i0, %i3, %i3
35525prefetcha [%i3 + 0] %asi, 2
35526
35527P3087: !_CAS [10] (maybe <- 0x180002c) (Int)
35528sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
35529add %i0, %i2, %i2
35530add %i2, 4, %o5
35531lduw [%o5], %o4
35532mov %o4, %l7
35533! move %l7(lower) -> %o4(upper)
35534sllx %l7, 32, %o4
35535mov %l4, %l6
35536cas [%o5], %l7, %l6
35537! move %l6(lower) -> %o4(lower)
35538srl %l6, 0, %l7
35539or %l7, %o4, %o4
35540!---- flushing int results buffer----
35541mov %o0, %l5
35542mov %o1, %l5
35543mov %o2, %l5
35544mov %o3, %l5
35545mov %o4, %l5
35546add %l4, 1, %l4
35547
35548P3088: !_ST_BINIT [15] (maybe <- 0x180002d) (Int)
35549wr %g0, 0xe2, %asi
35550sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
35551sub %i0, %i3, %i3
35552stwa %l4, [%i3 + 0] %asi
35553add %l4, 1, %l4
35554
35555P3089: !_MEMBAR (Int)
35556membar #StoreLoad
35557
35558P3090: !_BLD [15] (FP)
35559wr %g0, 0xf0, %asi
35560ldda [%i3 + 0] %asi, %f32
35561membar #Sync
35562! 3 addresses covered
35563fmovd %f32, %f14
35564!---- flushing fp results buffer to %f30 ----
35565fmovd %f0, %f30
35566fmovd %f2, %f30
35567fmovd %f4, %f30
35568fmovd %f6, %f30
35569fmovd %f8, %f30
35570fmovd %f10, %f30
35571fmovd %f12, %f30
35572fmovd %f14, %f30
35573!--
35574fmovd %f34, %f18
35575fmovs %f19, %f0
35576
35577P3091: !_MEMBAR (FP)
35578
35579P3092: !_ST_BINIT [7] (maybe <- 0x180002e) (Int)
35580wr %g0, 0xe2, %asi
35581sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
35582sub %i0, %i2, %i2
35583stwa %l4, [%i2 + 4] %asi
35584add %l4, 1, %l4
35585
35586P3093: !_MEMBAR (Int)
35587membar #StoreLoad
35588
35589P3094: !_DWST [18] (maybe <- 0x180002f) (Int) (Branch target of P3994)
35590sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
35591sub %i0, %i3, %i3
35592sllx %l4, 32, %l3
35593add %l4, 1, %l4
35594or %l3, %l4, %l3
35595stx %l3, [%i3 + 0]
35596add %l4, 1, %l4
35597ba P3095
35598nop
35599
35600TARGET3994:
35601ba RET3994
35602nop
35603
35604
35605P3095: !_MEMBAR (FP)
35606
35607P3096: !_BST [3] (maybe <- 0x4100000a) (FP)
35608wr %g0, 0xf0, %asi
35609! preparing store val #0, next val will be in f32
35610fmovs %f16, %f20
35611fadds %f16, %f17, %f16
35612! preparing store val #1, next val will be in f33
35613fmovs %f16, %f21
35614fadds %f16, %f17, %f16
35615! preparing store val #2, next val will be in f35
35616fmovd %f20, %f32
35617fmovs %f16, %f21
35618fadds %f16, %f17, %f16
35619fmovd %f20, %f34
35620membar #Sync
35621stda %f32, [%i1 + 0 ] %asi
35622
35623P3097: !_MEMBAR (FP)
35624membar #StoreLoad
35625
35626P3098: !_DWST [8] (maybe <- 0x1800031) (Int)
35627mov %l4, %l7
35628stx %l7, [%i2 + 8]
35629add %l4, 1, %l4
35630
35631P3099: !_LD [15] (Int)
35632sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
35633sub %i0, %i2, %i2
35634lduw [%i2 + 0], %o0
35635! move %o0(lower) -> %o0(upper)
35636sllx %o0, 32, %o0
35637
35638P3100: !_CASX [17] (maybe <- 0x1800032) (Int)
35639add %i2, 8, %l3
35640ldx [%l3], %l7
35641! move %l7(upper) -> %o0(lower)
35642srlx %l7, 32, %o5
35643or %o5, %o0, %o0
35644! move %l7(lower) -> %o1(upper)
35645sllx %l7, 32, %o1
35646mov %l7, %o5
35647mov %l4, %l7
35648casx [%l3], %o5, %l7
35649! move %l7(upper) -> %o1(lower)
35650srlx %l7, 32, %o5
35651or %o5, %o1, %o1
35652! move %l7(lower) -> %o2(upper)
35653sllx %l7, 32, %o2
35654add %l4, 1, %l4
35655
35656P3101: !_CASX [1] (maybe <- 0x1800033) (Int)
35657ldx [%i0], %l7
35658! move %l7(upper) -> %o2(lower)
35659srlx %l7, 32, %o5
35660or %o5, %o2, %o2
35661! move %l7(lower) -> %o3(upper)
35662sllx %l7, 32, %o3
35663mov %l7, %o5
35664sllx %l4, 32, %l7
35665add %l4, 1, %l4
35666or %l4, %l7, %l7
35667casx [%i0], %o5, %l7
35668! move %l7(upper) -> %o3(lower)
35669srlx %l7, 32, %o5
35670or %o5, %o3, %o3
35671! move %l7(lower) -> %o4(upper)
35672sllx %l7, 32, %o4
35673add %l4, 1, %l4
35674
35675P3102: !_LDD [22] (Int)
35676sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
35677add %i0, %i3, %i3
35678ldd [%i3 + 0], %l6
35679! move %l6(lower) -> %o4(lower)
35680or %l6, %o4, %o4
35681!---- flushing int results buffer----
35682mov %o0, %l5
35683mov %o1, %l5
35684mov %o2, %l5
35685mov %o3, %l5
35686mov %o4, %l5
35687! move %l7(lower) -> %o0(upper)
35688sllx %l7, 32, %o0
35689
35690P3103: !_MEMBAR (FP)
35691membar #StoreLoad
35692
35693P3104: !_BLD [5] (FP)
35694wr %g0, 0xf0, %asi
35695ldda [%i1 + 0] %asi, %f32
35696membar #Sync
35697! 3 addresses covered
35698fmovd %f32, %f18
35699fmovs %f18, %f1
35700fmovs %f19, %f2
35701fmovd %f34, %f18
35702fmovs %f19, %f3
35703
35704P3105: !_MEMBAR (FP)
35705
35706P3106: !_BLD [13] (FP)
35707wr %g0, 0xf0, %asi
35708sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
35709sub %i0, %i2, %i2
35710ldda [%i2 + 0] %asi, %f32
35711membar #Sync
35712! 3 addresses covered
35713fmovd %f32, %f4
35714fmovd %f34, %f18
35715fmovs %f19, %f6
35716
35717P3107: !_MEMBAR (FP)
35718
35719P3108: !_BLD [12] (FP)
35720wr %g0, 0xf0, %asi
35721ldda [%i2 + 0] %asi, %f32
35722membar #Sync
35723! 3 addresses covered
35724fmovd %f32, %f18
35725fmovs %f18, %f7
35726fmovs %f19, %f8
35727fmovd %f34, %f18
35728fmovs %f19, %f9
35729
35730P3109: !_MEMBAR (FP)
35731
35732P3110: !_CASX [8] (maybe <- 0x1800035) (Int)
35733sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
35734sub %i0, %i3, %i3
35735add %i3, 8, %l6
35736ldx [%l6], %o5
35737! move %o5(upper) -> %o0(lower)
35738srlx %o5, 32, %l3
35739or %l3, %o0, %o0
35740! move %o5(lower) -> %o1(upper)
35741sllx %o5, 32, %o1
35742mov %o5, %l3
35743mov %l4, %o5
35744casx [%l6], %l3, %o5
35745! move %o5(upper) -> %o1(lower)
35746srlx %o5, 32, %l3
35747or %l3, %o1, %o1
35748! move %o5(lower) -> %o2(upper)
35749sllx %o5, 32, %o2
35750add %l4, 1, %l4
35751
35752P3111: !_LDD [9] (Int)
35753sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
35754add %i0, %i2, %i2
35755ldd [%i2 + 0], %l6
35756! move %l6(lower) -> %o2(lower)
35757or %l6, %o2, %o2
35758! move %l7(lower) -> %o3(upper)
35759sllx %l7, 32, %o3
35760
35761P3112: !_DWST_BINIT [14] (maybe <- 0x1800036) (Int)
35762wr %g0, 0xe2, %asi
35763sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
35764sub %i0, %i3, %i3
35765mov %l4, %l3
35766stxa %l3, [%i3 + 8] %asi
35767add %l4, 1, %l4
35768
35769P3113: !_MEMBAR (Int)
35770membar #StoreLoad
35771
35772P3114: !_LD [17] (Int)
35773sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
35774sub %i0, %i2, %i2
35775lduw [%i2 + 12], %l3
35776! move %l3(lower) -> %o3(lower)
35777or %l3, %o3, %o3
35778
35779P3115: !_CAS [5] (maybe <- 0x1800037) (Int)
35780add %i1, 12, %l7
35781lduw [%l7], %o4
35782mov %o4, %l6
35783! move %l6(lower) -> %o4(upper)
35784sllx %l6, 32, %o4
35785mov %l4, %l3
35786cas [%l7], %l6, %l3
35787! move %l3(lower) -> %o4(lower)
35788srl %l3, 0, %l6
35789or %l6, %o4, %o4
35790!---- flushing int results buffer----
35791mov %o0, %l5
35792mov %o1, %l5
35793mov %o2, %l5
35794mov %o3, %l5
35795mov %o4, %l5
35796add %l4, 1, %l4
35797
35798P3116: !_CAS [1] (maybe <- 0x1800038) (Int)
35799add %i0, 4, %l7
35800lduw [%l7], %o0
35801mov %o0, %l6
35802! move %l6(lower) -> %o0(upper)
35803sllx %l6, 32, %o0
35804mov %l4, %l3
35805cas [%l7], %l6, %l3
35806! move %l3(lower) -> %o0(lower)
35807srl %l3, 0, %l6
35808or %l6, %o0, %o0
35809add %l4, 1, %l4
35810
35811P3117: !_PREFETCH [9] (Int)
35812sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
35813add %i0, %i3, %i3
35814prefetch [%i3 + 0], 4
35815
35816P3118: !_DWLD [14] (Int)
35817sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
35818sub %i0, %i2, %i2
35819ldx [%i2 + 8], %o1
35820! move %o1(lower) -> %o1(upper)
35821sllx %o1, 32, %o1
35822
35823P3119: !_MEMBAR (FP)
35824
35825P3120: !_BSTC [15] (maybe <- 0x4100000d) (FP)
35826wr %g0, 0xe0, %asi
35827sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
35828sub %i0, %i3, %i3
35829! preparing store val #0, next val will be in f32
35830fmovs %f16, %f20
35831fadds %f16, %f17, %f16
35832! preparing store val #1, next val will be in f33
35833fmovs %f16, %f21
35834fadds %f16, %f17, %f16
35835! preparing store val #2, next val will be in f35
35836fmovd %f20, %f32
35837fmovs %f16, %f21
35838fadds %f16, %f17, %f16
35839fmovd %f20, %f34
35840membar #Sync
35841stda %f32, [%i3 + 0 ] %asi
35842
35843P3121: !_MEMBAR (FP)
35844membar #StoreLoad
35845
35846P3122: !_LDD [1] (Int)
35847ldd [%i0 + 0], %l6
35848! move %l6(lower) -> %o1(lower)
35849or %l6, %o1, %o1
35850! move %l7(lower) -> %o2(upper)
35851sllx %l7, 32, %o2
35852
35853P3123: !_MEMBAR (FP)
35854
35855P3124: !_BST [23] (maybe <- 0x41000010) (FP) (CBR)
35856wr %g0, 0xf0, %asi
35857sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
35858add %i0, %i2, %i2
35859! preparing store val #0, next val will be in f32
35860fmovs %f16, %f20
35861fadds %f16, %f17, %f16
35862! preparing store val #1, next val will be in f33
35863fmovs %f16, %f21
35864fadds %f16, %f17, %f16
35865! preparing store val #2, next val will be in f35
35866fmovd %f20, %f32
35867fmovs %f16, %f21
35868fadds %f16, %f17, %f16
35869fmovd %f20, %f34
35870membar #Sync
35871stda %f32, [%i2 + 0 ] %asi
35872
35873! cbranch
35874andcc %l0, 1, %g0
35875be,pn %xcc, TARGET3124
35876nop
35877RET3124:
35878
35879! lfsr step begin
35880srlx %l0, 1, %o5
35881xnor %o5, %l0, %o5
35882sllx %o5, 63, %o5
35883or %o5, %l0, %l0
35884srlx %l0, 1, %l0
35885
35886
35887P3125: !_MEMBAR (FP) (Branch target of P3742)
35888membar #StoreLoad
35889ba P3126
35890nop
35891
35892TARGET3742:
35893ba RET3742
35894nop
35895
35896
35897P3126: !_CASX [23] (maybe <- 0x1800039) (Int)
35898add %i2, 8, %l6
35899ldx [%l6], %o5
35900! move %o5(upper) -> %o2(lower)
35901srlx %o5, 32, %l3
35902or %l3, %o2, %o2
35903! move %o5(lower) -> %o3(upper)
35904sllx %o5, 32, %o3
35905mov %o5, %l3
35906mov %l4, %o5
35907casx [%l6], %l3, %o5
35908! move %o5(upper) -> %o3(lower)
35909srlx %o5, 32, %l3
35910or %l3, %o3, %o3
35911! move %o5(lower) -> %o4(upper)
35912sllx %o5, 32, %o4
35913add %l4, 1, %l4
35914
35915P3127: !_MEMBAR (FP)
35916
35917P3128: !_BST [22] (maybe <- 0x41000013) (FP)
35918wr %g0, 0xf0, %asi
35919! preparing store val #0, next val will be in f32
35920fmovs %f16, %f20
35921fadds %f16, %f17, %f16
35922! preparing store val #1, next val will be in f33
35923fmovs %f16, %f21
35924fadds %f16, %f17, %f16
35925! preparing store val #2, next val will be in f35
35926fmovd %f20, %f32
35927fmovs %f16, %f21
35928fadds %f16, %f17, %f16
35929fmovd %f20, %f34
35930membar #Sync
35931stda %f32, [%i2 + 0 ] %asi
35932
35933P3129: !_MEMBAR (FP)
35934membar #StoreLoad
35935
35936P3130: !_BLD [3] (FP)
35937wr %g0, 0xf0, %asi
35938ldda [%i1 + 0] %asi, %f32
35939membar #Sync
35940! 3 addresses covered
35941fmovd %f32, %f10
35942fmovd %f34, %f18
35943fmovs %f19, %f12
35944
35945P3131: !_MEMBAR (FP)
35946
35947P3132: !_DWST_BINIT [4] (maybe <- 0x180003a) (Int)
35948wr %g0, 0xe2, %asi
35949sllx %l4, 32, %o5
35950add %l4, 1, %l4
35951or %o5, %l4, %o5
35952stxa %o5, [%i1 + 0] %asi
35953add %l4, 1, %l4
35954
35955P3133: !_MEMBAR (Int) (CBR)
35956membar #StoreLoad
35957
35958! cbranch
35959andcc %l0, 1, %g0
35960be,pt %xcc, TARGET3133
35961nop
35962RET3133:
35963
35964! lfsr step begin
35965srlx %l0, 1, %o5
35966xnor %o5, %l0, %o5
35967sllx %o5, 63, %o5
35968or %o5, %l0, %l0
35969srlx %l0, 1, %l0
35970
35971
35972P3134: !_ST_BINIT [7] (maybe <- 0x180003c) (Int)
35973wr %g0, 0xe2, %asi
35974sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
35975sub %i0, %i3, %i3
35976stwa %l4, [%i3 + 4] %asi
35977add %l4, 1, %l4
35978
35979P3135: !_MEMBAR (Int)
35980
35981P3136: !_BSTC [18] (maybe <- 0x41000016) (FP)
35982wr %g0, 0xe0, %asi
35983sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
35984sub %i0, %i2, %i2
35985! preparing store val #0, next val will be in f32
35986fmovs %f16, %f20
35987fadds %f16, %f17, %f16
35988! preparing store val #1, next val will be in f33
35989fmovs %f16, %f21
35990fadds %f16, %f17, %f16
35991! preparing store val #2, next val will be in f35
35992fmovd %f20, %f32
35993fmovs %f16, %f21
35994fadds %f16, %f17, %f16
35995fmovd %f20, %f34
35996membar #Sync
35997stda %f32, [%i2 + 0 ] %asi
35998
35999P3137: !_MEMBAR (FP) (Branch target of P3160)
36000membar #StoreLoad
36001ba P3138
36002nop
36003
36004TARGET3160:
36005ba RET3160
36006nop
36007
36008
36009P3138: !_REPLACEMENT [5] (Int) (Branch target of P3918)
36010sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
36011add %i0, %i3, %i3
36012sethi %hi(0x20000), %l7
36013ld [%i3+12], %l3
36014st %l3, [%i3+12]
36015add %i3, %l7, %o5
36016ld [%o5+12], %l3
36017st %l3, [%o5+12]
36018add %o5, %l7, %o5
36019ld [%o5+12], %l3
36020st %l3, [%o5+12]
36021add %o5, %l7, %o5
36022ld [%o5+12], %l3
36023st %l3, [%o5+12]
36024add %o5, %l7, %o5
36025ld [%o5+12], %l3
36026st %l3, [%o5+12]
36027add %o5, %l7, %o5
36028ld [%o5+12], %l3
36029st %l3, [%o5+12]
36030add %o5, %l7, %o5
36031ld [%o5+12], %l3
36032st %l3, [%o5+12]
36033add %o5, %l7, %o5
36034ld [%o5+12], %l3
36035st %l3, [%o5+12]
36036ba P3139
36037nop
36038
36039TARGET3918:
36040ba RET3918
36041nop
36042
36043
36044P3139: !_REPLACEMENT [10] (Int)
36045sethi %hi(0x20000), %l6
36046ld [%i3+4], %o5
36047st %o5, [%i3+4]
36048add %i3, %l6, %l7
36049ld [%l7+4], %o5
36050st %o5, [%l7+4]
36051add %l7, %l6, %l7
36052ld [%l7+4], %o5
36053st %o5, [%l7+4]
36054add %l7, %l6, %l7
36055ld [%l7+4], %o5
36056st %o5, [%l7+4]
36057add %l7, %l6, %l7
36058ld [%l7+4], %o5
36059st %o5, [%l7+4]
36060add %l7, %l6, %l7
36061ld [%l7+4], %o5
36062st %o5, [%l7+4]
36063add %l7, %l6, %l7
36064ld [%l7+4], %o5
36065st %o5, [%l7+4]
36066add %l7, %l6, %l7
36067ld [%l7+4], %o5
36068st %o5, [%l7+4]
36069
36070P3140: !_LD [18] (Int)
36071lduw [%i2 + 0], %l6
36072! move %l6(lower) -> %o4(lower)
36073or %l6, %o4, %o4
36074!---- flushing int results buffer----
36075mov %o0, %l5
36076mov %o1, %l5
36077mov %o2, %l5
36078mov %o3, %l5
36079mov %o4, %l5
36080
36081P3141: !_DWLD [3] (Int)
36082ldx [%i1 + 0], %o0
36083! move %o0(upper) -> %o0(upper)
36084! move %o0(lower) -> %o0(lower)
36085
36086P3142: !_CASX [16] (maybe <- 0x180003d) (Int)
36087sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
36088sub %i0, %i2, %i2
36089ldx [%i2], %o1
36090! move %o1(upper) -> %o1(upper)
36091! move %o1(lower) -> %o1(lower)
36092mov %o1, %l3
36093sllx %l4, 32, %o2
36094add %l4, 1, %l4
36095or %l4, %o2, %o2
36096casx [%i2], %l3, %o2
36097! move %o2(upper) -> %o2(upper)
36098! move %o2(lower) -> %o2(lower)
36099add %l4, 1, %l4
36100
36101P3143: !_SWAP [19] (maybe <- 0x180003f) (Int) (Branch target of P3501)
36102sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
36103sub %i0, %i3, %i3
36104mov %l4, %o3
36105swap [%i3 + 4], %o3
36106! move %o3(lower) -> %o3(upper)
36107sllx %o3, 32, %o3
36108add %l4, 1, %l4
36109ba P3144
36110nop
36111
36112TARGET3501:
36113ba RET3501
36114nop
36115
36116
36117P3144: !_CAS [17] (maybe <- 0x1800040) (Int)
36118add %i2, 12, %l3
36119lduw [%l3], %l7
36120mov %l7, %o5
36121! move %o5(lower) -> %o3(lower)
36122or %o5, %o3, %o3
36123mov %l4, %o4
36124cas [%l3], %o5, %o4
36125! move %o4(lower) -> %o4(upper)
36126sllx %o4, 32, %o4
36127add %l4, 1, %l4
36128
36129P3145: !_PREFETCH [15] (Int)
36130prefetch [%i2 + 0], 18
36131
36132P3146: !_CASX [18] (maybe <- 0x1800041) (Int)
36133ldx [%i3], %l7
36134! move %l7(upper) -> %o4(lower)
36135srlx %l7, 32, %o5
36136or %o5, %o4, %o4
36137!---- flushing int results buffer----
36138mov %o0, %l5
36139mov %o1, %l5
36140mov %o2, %l5
36141mov %o3, %l5
36142mov %o4, %l5
36143! move %l7(lower) -> %o0(upper)
36144sllx %l7, 32, %o0
36145mov %l7, %o5
36146sllx %l4, 32, %l7
36147add %l4, 1, %l4
36148or %l4, %l7, %l7
36149casx [%i3], %o5, %l7
36150! move %l7(upper) -> %o0(lower)
36151srlx %l7, 32, %o5
36152or %o5, %o0, %o0
36153! move %l7(lower) -> %o1(upper)
36154sllx %l7, 32, %o1
36155add %l4, 1, %l4
36156
36157P3147: !_ST_BINIT [1] (maybe <- 0x1800043) (Int)
36158wr %g0, 0xe2, %asi
36159stwa %l4, [%i0 + 4] %asi
36160add %l4, 1, %l4
36161
36162P3148: !_MEMBAR (Int)
36163membar #StoreLoad
36164
36165P3149: !_DWST [19] (maybe <- 0x1800044) (Int)
36166sllx %l4, 32, %l7
36167add %l4, 1, %l4
36168or %l7, %l4, %l7
36169stx %l7, [%i3 + 0]
36170add %l4, 1, %l4
36171
36172P3150: !_LDD [5] (Int)
36173ldd [%i1 + 8], %l6
36174! move %l7(lower) -> %o1(lower)
36175or %l7, %o1, %o1
36176
36177P3151: !_LD [1] (Int)
36178lduw [%i0 + 4], %o2
36179! move %o2(lower) -> %o2(upper)
36180sllx %o2, 32, %o2
36181
36182P3152: !_MEMBAR (FP)
36183membar #StoreLoad
36184
36185P3153: !_BLD [9] (FP)
36186wr %g0, 0xf0, %asi
36187sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
36188add %i0, %i2, %i2
36189ldda [%i2 + 0] %asi, %f32
36190membar #Sync
36191! 3 addresses covered
36192fmovd %f32, %f18
36193fmovs %f18, %f13
36194fmovs %f19, %f14
36195fmovd %f34, %f18
36196fmovs %f19, %f15
36197!---- flushing fp results buffer to %f30 ----
36198fmovd %f0, %f30
36199fmovd %f2, %f30
36200fmovd %f4, %f30
36201fmovd %f6, %f30
36202fmovd %f8, %f30
36203fmovd %f10, %f30
36204fmovd %f12, %f30
36205fmovd %f14, %f30
36206!--
36207
36208P3154: !_MEMBAR (FP)
36209
36210P3155: !_BLD [0] (FP)
36211wr %g0, 0xf0, %asi
36212ldda [%i0 + 0] %asi, %f0
36213membar #Sync
36214! 3 addresses covered
36215fmovs %f3, %f2
36216
36217P3156: !_MEMBAR (FP)
36218
36219P3157: !_LDD [20] (Int)
36220ldd [%i3 + 8], %l6
36221! move %l7(lower) -> %o2(lower)
36222or %l7, %o2, %o2
36223
36224P3158: !_LDD [18] (Int)
36225ldd [%i3 + 0], %l6
36226! move %l6(lower) -> %o3(upper)
36227sllx %l6, 32, %o3
36228! move %l7(lower) -> %o3(lower)
36229or %l7, %o3, %o3
36230
36231P3159: !_MEMBAR (FP)
36232
36233P3160: !_BSTC [13] (maybe <- 0x41000019) (FP) (CBR)
36234wr %g0, 0xe0, %asi
36235sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
36236sub %i0, %i3, %i3
36237! preparing store val #0, next val will be in f32
36238fmovs %f16, %f20
36239fadds %f16, %f17, %f16
36240! preparing store val #1, next val will be in f33
36241fmovs %f16, %f21
36242fadds %f16, %f17, %f16
36243! preparing store val #2, next val will be in f35
36244fmovd %f20, %f32
36245fmovs %f16, %f21
36246fadds %f16, %f17, %f16
36247fmovd %f20, %f34
36248membar #Sync
36249stda %f32, [%i3 + 0 ] %asi
36250
36251! cbranch
36252andcc %l0, 1, %g0
36253be,pt %xcc, TARGET3160
36254nop
36255RET3160:
36256
36257! lfsr step begin
36258srlx %l0, 1, %o5
36259xnor %o5, %l0, %o5
36260sllx %o5, 63, %o5
36261or %o5, %l0, %l0
36262srlx %l0, 1, %l0
36263
36264
36265P3161: !_MEMBAR (FP)
36266membar #StoreLoad
36267
36268P3162: !_DWST [12] (maybe <- 0x1800046) (Int)
36269sllx %l4, 32, %l3
36270add %l4, 1, %l4
36271or %l3, %l4, %l3
36272stx %l3, [%i3 + 0]
36273add %l4, 1, %l4
36274
36275P3163: !_ST_BINIT [7] (maybe <- 0x1800048) (Int)
36276wr %g0, 0xe2, %asi
36277sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
36278sub %i0, %i2, %i2
36279stwa %l4, [%i2 + 4] %asi
36280add %l4, 1, %l4
36281
36282P3164: !_MEMBAR (Int)
36283membar #StoreLoad
36284
36285P3165: !_PREFETCH [15] (Int)
36286sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
36287sub %i0, %i3, %i3
36288prefetch [%i3 + 0], 1
36289
36290P3166: !_CASX [23] (maybe <- 0x1800049) (Int)
36291sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
36292add %i0, %i2, %i2
36293add %i2, 8, %o5
36294ldx [%o5], %o4
36295! move %o4(upper) -> %o4(upper)
36296! move %o4(lower) -> %o4(lower)
36297!---- flushing int results buffer----
36298mov %o0, %l5
36299mov %o1, %l5
36300mov %o2, %l5
36301mov %o3, %l5
36302mov %o4, %l5
36303mov %o4, %l7
36304mov %l4, %o0
36305casx [%o5], %l7, %o0
36306! move %o0(upper) -> %o0(upper)
36307! move %o0(lower) -> %o0(lower)
36308add %l4, 1, %l4
36309
36310P3167: !_CAS [4] (maybe <- 0x180004a) (Int)
36311add %i1, 4, %o5
36312lduw [%o5], %o1
36313mov %o1, %l7
36314! move %l7(lower) -> %o1(upper)
36315sllx %l7, 32, %o1
36316mov %l4, %l6
36317cas [%o5], %l7, %l6
36318! move %l6(lower) -> %o1(lower)
36319srl %l6, 0, %l7
36320or %l7, %o1, %o1
36321add %l4, 1, %l4
36322
36323P3168: !_DWLD [9] (Int)
36324sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
36325add %i0, %i3, %i3
36326ldx [%i3 + 0], %o2
36327! move %o2(upper) -> %o2(upper)
36328! move %o2(lower) -> %o2(lower)
36329
36330P3169: !_MEMBAR (FP)
36331membar #StoreLoad
36332
36333P3170: !_BLD [14] (FP)
36334wr %g0, 0xf0, %asi
36335sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
36336sub %i0, %i2, %i2
36337ldda [%i2 + 0] %asi, %f32
36338membar #Sync
36339! 3 addresses covered
36340fmovd %f32, %f18
36341fmovs %f18, %f3
36342fmovs %f19, %f4
36343fmovd %f34, %f18
36344fmovs %f19, %f5
36345
36346P3171: !_MEMBAR (FP)
36347
36348P3172: !_BST [5] (maybe <- 0x4100001c) (FP)
36349wr %g0, 0xf0, %asi
36350! preparing store val #0, next val will be in f32
36351fmovs %f16, %f20
36352fadds %f16, %f17, %f16
36353! preparing store val #1, next val will be in f33
36354fmovs %f16, %f21
36355fadds %f16, %f17, %f16
36356! preparing store val #2, next val will be in f35
36357fmovd %f20, %f32
36358fmovs %f16, %f21
36359fadds %f16, %f17, %f16
36360fmovd %f20, %f34
36361membar #Sync
36362stda %f32, [%i1 + 0 ] %asi
36363
36364P3173: !_MEMBAR (FP)
36365
36366P3174: !_BST [1] (maybe <- 0x4100001f) (FP) (Branch target of P3508)
36367wr %g0, 0xf0, %asi
36368! preparing store val #0, next val will be in f32
36369fmovs %f16, %f20
36370fadds %f16, %f17, %f16
36371! preparing store val #1, next val will be in f33
36372fmovs %f16, %f21
36373fadds %f16, %f17, %f16
36374! preparing store val #2, next val will be in f35
36375fmovd %f20, %f32
36376fmovs %f16, %f21
36377fadds %f16, %f17, %f16
36378fmovd %f20, %f34
36379membar #Sync
36380stda %f32, [%i0 + 0 ] %asi
36381ba P3175
36382nop
36383
36384TARGET3508:
36385ba RET3508
36386nop
36387
36388
36389P3175: !_MEMBAR (FP)
36390membar #StoreLoad
36391
36392P3176: !_REPLACEMENT [6] (Int)
36393sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
36394sub %i0, %i3, %i3
36395sethi %hi(0x20000), %l7
36396ld [%i3+0], %l3
36397st %l3, [%i3+0]
36398add %i3, %l7, %o5
36399ld [%o5+0], %l3
36400st %l3, [%o5+0]
36401add %o5, %l7, %o5
36402ld [%o5+0], %l3
36403st %l3, [%o5+0]
36404add %o5, %l7, %o5
36405ld [%o5+0], %l3
36406st %l3, [%o5+0]
36407add %o5, %l7, %o5
36408ld [%o5+0], %l3
36409st %l3, [%o5+0]
36410add %o5, %l7, %o5
36411ld [%o5+0], %l3
36412st %l3, [%o5+0]
36413add %o5, %l7, %o5
36414ld [%o5+0], %l3
36415st %l3, [%o5+0]
36416add %o5, %l7, %o5
36417ld [%o5+0], %l3
36418st %l3, [%o5+0]
36419
36420P3177: !_LD [4] (Int)
36421lduw [%i1 + 4], %o3
36422! move %o3(lower) -> %o3(upper)
36423sllx %o3, 32, %o3
36424
36425P3178: !_MEMBAR (FP)
36426
36427P3179: !_BSTC [14] (maybe <- 0x41000022) (FP)
36428wr %g0, 0xe0, %asi
36429! preparing store val #0, next val will be in f32
36430fmovs %f16, %f20
36431fadds %f16, %f17, %f16
36432! preparing store val #1, next val will be in f33
36433fmovs %f16, %f21
36434fadds %f16, %f17, %f16
36435! preparing store val #2, next val will be in f35
36436fmovd %f20, %f32
36437fmovs %f16, %f21
36438fadds %f16, %f17, %f16
36439fmovd %f20, %f34
36440membar #Sync
36441stda %f32, [%i2 + 0 ] %asi
36442
36443P3180: !_MEMBAR (FP)
36444membar #StoreLoad
36445
36446P3181: !_SWAP [2] (maybe <- 0x180004b) (Int) (Branch target of P3909)
36447mov %l4, %l3
36448swap [%i0 + 12], %l3
36449! move %l3(lower) -> %o3(lower)
36450srl %l3, 0, %l7
36451or %l7, %o3, %o3
36452add %l4, 1, %l4
36453ba P3182
36454nop
36455
36456TARGET3909:
36457ba RET3909
36458nop
36459
36460
36461P3182: !_CAS [5] (maybe <- 0x180004c) (Int) (LE) (Branch target of P3620)
36462! Change single-word-level endianess (big endian <-> little endian)
36463sethi %hi(0xff00ff00), %l7
36464or %l7, %lo(0xff00ff00), %l7
36465and %l4, %l7, %l6
36466srl %l6, 8, %l6
36467sll %l4, 8, %o5
36468and %o5, %l7, %o5
36469or %o5, %l6, %o5
36470srl %o5, 16, %l6
36471sll %o5, 16, %o5
36472srl %o5, 0, %o5
36473or %o5, %l6, %o5
36474wr %g0, 0x88, %asi
36475add %i1, 12, %l7
36476lduwa [%l7] %asi, %o4
36477mov %o4, %l6
36478! move %l6(lower) -> %o4(upper)
36479sllx %l6, 32, %o4
36480mov %o5, %l3
36481casa [%l7] %asi, %l6, %l3
36482! move %l3(lower) -> %o4(lower)
36483srl %l3, 0, %l6
36484or %l6, %o4, %o4
36485!---- flushing int results buffer----
36486mov %o0, %l5
36487mov %o1, %l5
36488mov %o2, %l5
36489mov %o3, %l5
36490mov %o4, %l5
36491add %l4, 1, %l4
36492ba P3183
36493nop
36494
36495TARGET3620:
36496ba RET3620
36497nop
36498
36499
36500P3183: !_MEMBAR (FP)
36501membar #StoreLoad
36502
36503P3184: !_BLD [20] (FP)
36504wr %g0, 0xf0, %asi
36505sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
36506sub %i0, %i2, %i2
36507ldda [%i2 + 0] %asi, %f32
36508membar #Sync
36509! 3 addresses covered
36510fmovd %f32, %f6
36511fmovd %f34, %f18
36512fmovs %f19, %f8
36513
36514P3185: !_MEMBAR (FP)
36515
36516P3186: !_LDD [9] (Int)
36517sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
36518add %i0, %i3, %i3
36519ldd [%i3 + 0], %l6
36520! move %l6(lower) -> %o0(upper)
36521sllx %l6, 32, %o0
36522! move %l7(lower) -> %o0(lower)
36523or %l7, %o0, %o0
36524
36525P3187: !_DWST_BINIT [12] (maybe <- 0x180004d) (Int)
36526wr %g0, 0xe2, %asi
36527sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
36528sub %i0, %i2, %i2
36529sllx %l4, 32, %l3
36530add %l4, 1, %l4
36531or %l3, %l4, %l3
36532stxa %l3, [%i2 + 0] %asi
36533add %l4, 1, %l4
36534
36535P3188: !_MEMBAR (Int)
36536membar #StoreLoad
36537
36538P3189: !_CAS [22] (maybe <- 0x180004f) (Int)
36539sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
36540add %i0, %i3, %i3
36541add %i3, 4, %l3
36542lduw [%l3], %o1
36543mov %o1, %o5
36544! move %o5(lower) -> %o1(upper)
36545sllx %o5, 32, %o1
36546mov %l4, %l7
36547cas [%l3], %o5, %l7
36548! move %l7(lower) -> %o1(lower)
36549srl %l7, 0, %o5
36550or %o5, %o1, %o1
36551add %l4, 1, %l4
36552
36553P3190: !_LD [2] (Int)
36554lduw [%i0 + 12], %o2
36555! move %o2(lower) -> %o2(upper)
36556sllx %o2, 32, %o2
36557
36558P3191: !_MEMBAR (FP)
36559membar #StoreLoad
36560
36561P3192: !_BLD [7] (FP)
36562wr %g0, 0xf0, %asi
36563sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
36564sub %i0, %i2, %i2
36565ldda [%i2 + 0] %asi, %f32
36566membar #Sync
36567! 3 addresses covered
36568fmovd %f32, %f18
36569fmovs %f18, %f9
36570fmovs %f19, %f10
36571fmovd %f34, %f18
36572fmovs %f19, %f11
36573
36574P3193: !_MEMBAR (FP)
36575
36576P3194: !_BSTC [10] (maybe <- 0x41000025) (FP)
36577wr %g0, 0xe0, %asi
36578sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
36579add %i0, %i3, %i3
36580! preparing store val #0, next val will be in f32
36581fmovs %f16, %f20
36582fadds %f16, %f17, %f16
36583! preparing store val #1, next val will be in f33
36584fmovs %f16, %f21
36585fadds %f16, %f17, %f16
36586! preparing store val #2, next val will be in f35
36587fmovd %f20, %f32
36588fmovs %f16, %f21
36589fadds %f16, %f17, %f16
36590fmovd %f20, %f34
36591membar #Sync
36592stda %f32, [%i3 + 0 ] %asi
36593
36594P3195: !_MEMBAR (FP)
36595membar #StoreLoad
36596
36597P3196: !_LD [1] (Int)
36598lduw [%i0 + 4], %l6
36599! move %l6(lower) -> %o2(lower)
36600or %l6, %o2, %o2
36601
36602P3197: !_REPLACEMENT [9] (Int)
36603sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
36604add %i0, %i2, %i2
36605sethi %hi(0x20000), %o5
36606ld [%i2+0], %l6
36607st %l6, [%i2+0]
36608add %i2, %o5, %l3
36609ld [%l3+0], %l6
36610st %l6, [%l3+0]
36611add %l3, %o5, %l3
36612ld [%l3+0], %l6
36613st %l6, [%l3+0]
36614add %l3, %o5, %l3
36615ld [%l3+0], %l6
36616st %l6, [%l3+0]
36617add %l3, %o5, %l3
36618ld [%l3+0], %l6
36619st %l6, [%l3+0]
36620add %l3, %o5, %l3
36621ld [%l3+0], %l6
36622st %l6, [%l3+0]
36623add %l3, %o5, %l3
36624ld [%l3+0], %l6
36625st %l6, [%l3+0]
36626add %l3, %o5, %l3
36627ld [%l3+0], %l6
36628st %l6, [%l3+0]
36629
36630P3198: !_DWST [0] (maybe <- 0x1800050) (Int)
36631sllx %l4, 32, %l7
36632add %l4, 1, %l4
36633or %l7, %l4, %l7
36634stx %l7, [%i0 + 0]
36635add %l4, 1, %l4
36636
36637P3199: !_CAS [19] (maybe <- 0x1800052) (Int)
36638sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
36639sub %i0, %i3, %i3
36640add %i3, 4, %l7
36641lduw [%l7], %o3
36642mov %o3, %l6
36643! move %l6(lower) -> %o3(upper)
36644sllx %l6, 32, %o3
36645mov %l4, %l3
36646cas [%l7], %l6, %l3
36647! move %l3(lower) -> %o3(lower)
36648srl %l3, 0, %l6
36649or %l6, %o3, %o3
36650add %l4, 1, %l4
36651
36652P3200: !_DWST_BINIT [2] (maybe <- 0x1800053) (Int)
36653wr %g0, 0xe2, %asi
36654mov %l4, %l6
36655stxa %l6, [%i0 + 8] %asi
36656add %l4, 1, %l4
36657
36658P3201: !_MEMBAR (Int)
36659membar #StoreLoad
36660
36661P3202: !_DWST [6] (maybe <- 0x1800054) (Int)
36662sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
36663sub %i0, %i2, %i2
36664sllx %l4, 32, %l3
36665add %l4, 1, %l4
36666or %l3, %l4, %l3
36667stx %l3, [%i2 + 0]
36668add %l4, 1, %l4
36669
36670P3203: !_MEMBAR (FP)
36671
36672P3204: !_BST [15] (maybe <- 0x41000028) (FP)
36673wr %g0, 0xf0, %asi
36674sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
36675sub %i0, %i3, %i3
36676! preparing store val #0, next val will be in f32
36677fmovs %f16, %f20
36678fadds %f16, %f17, %f16
36679! preparing store val #1, next val will be in f33
36680fmovs %f16, %f21
36681fadds %f16, %f17, %f16
36682! preparing store val #2, next val will be in f35
36683fmovd %f20, %f32
36684fmovs %f16, %f21
36685fadds %f16, %f17, %f16
36686fmovd %f20, %f34
36687membar #Sync
36688stda %f32, [%i3 + 0 ] %asi
36689
36690P3205: !_MEMBAR (FP)
36691membar #StoreLoad
36692
36693P3206: !_ST [16] (maybe <- 0x1800056) (Int)
36694stw %l4, [%i3 + 4 ]
36695add %l4, 1, %l4
36696
36697P3207: !_CAS [15] (maybe <- 0x1800057) (Int)
36698lduw [%i3], %o4
36699mov %o4, %l6
36700! move %l6(lower) -> %o4(upper)
36701sllx %l6, 32, %o4
36702mov %l4, %l3
36703cas [%i3], %l6, %l3
36704! move %l3(lower) -> %o4(lower)
36705srl %l3, 0, %l6
36706or %l6, %o4, %o4
36707!---- flushing int results buffer----
36708mov %o0, %l5
36709mov %o1, %l5
36710mov %o2, %l5
36711mov %o3, %l5
36712mov %o4, %l5
36713add %l4, 1, %l4
36714
36715P3208: !_LD [13] (Int)
36716sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
36717sub %i0, %i2, %i2
36718lduw [%i2 + 4], %o0
36719! move %o0(lower) -> %o0(upper)
36720sllx %o0, 32, %o0
36721
36722P3209: !_CASX [15] (maybe <- 0x1800058) (Int)
36723ldx [%i3], %l7
36724! move %l7(upper) -> %o0(lower)
36725srlx %l7, 32, %o5
36726or %o5, %o0, %o0
36727! move %l7(lower) -> %o1(upper)
36728sllx %l7, 32, %o1
36729mov %l7, %o5
36730sllx %l4, 32, %l7
36731add %l4, 1, %l4
36732or %l4, %l7, %l7
36733casx [%i3], %o5, %l7
36734! move %l7(upper) -> %o1(lower)
36735srlx %l7, 32, %o5
36736or %o5, %o1, %o1
36737! move %l7(lower) -> %o2(upper)
36738sllx %l7, 32, %o2
36739add %l4, 1, %l4
36740
36741P3210: !_DWST_BINIT [1] (maybe <- 0x180005a) (Int)
36742wr %g0, 0xe2, %asi
36743sllx %l4, 32, %o5
36744add %l4, 1, %l4
36745or %o5, %l4, %o5
36746stxa %o5, [%i0 + 0] %asi
36747add %l4, 1, %l4
36748
36749P3211: !_MEMBAR (Int)
36750membar #StoreLoad
36751
36752P3212: !_DWST [21] (maybe <- 0x180005c) (Int)
36753sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
36754add %i0, %i3, %i3
36755sllx %l4, 32, %l7
36756add %l4, 1, %l4
36757or %l7, %l4, %l7
36758stx %l7, [%i3 + 0]
36759add %l4, 1, %l4
36760
36761P3213: !_DWLD [13] (Int)
36762ldx [%i2 + 0], %l7
36763! move %l7(upper) -> %o2(lower)
36764srlx %l7, 32, %l6
36765or %l6, %o2, %o2
36766! move %l7(lower) -> %o3(upper)
36767sllx %l7, 32, %o3
36768
36769P3214: !_SWAP [11] (maybe <- 0x180005e) (Int)
36770sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
36771add %i0, %i2, %i2
36772mov %l4, %l6
36773swap [%i2 + 12], %l6
36774! move %l6(lower) -> %o3(lower)
36775srl %l6, 0, %o5
36776or %o5, %o3, %o3
36777add %l4, 1, %l4
36778
36779P3215: !_MEMBAR (FP)
36780membar #StoreLoad
36781
36782P3216: !_BLD [2] (FP)
36783wr %g0, 0xf0, %asi
36784ldda [%i0 + 0] %asi, %f32
36785membar #Sync
36786! 3 addresses covered
36787fmovd %f32, %f12
36788fmovd %f34, %f18
36789fmovs %f19, %f14
36790
36791P3217: !_MEMBAR (FP)
36792
36793P3218: !_BLD [22] (FP)
36794wr %g0, 0xf0, %asi
36795ldda [%i3 + 0] %asi, %f32
36796membar #Sync
36797! 3 addresses covered
36798fmovd %f32, %f18
36799fmovs %f18, %f15
36800!---- flushing fp results buffer to %f30 ----
36801fmovd %f0, %f30
36802fmovd %f2, %f30
36803fmovd %f4, %f30
36804fmovd %f6, %f30
36805fmovd %f8, %f30
36806fmovd %f10, %f30
36807fmovd %f12, %f30
36808fmovd %f14, %f30
36809!--
36810fmovs %f19, %f0
36811fmovd %f34, %f18
36812fmovs %f19, %f1
36813
36814P3219: !_MEMBAR (FP)
36815
36816P3220: !_BST [20] (maybe <- 0x4100002b) (FP)
36817wr %g0, 0xf0, %asi
36818sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
36819sub %i0, %i3, %i3
36820! preparing store val #0, next val will be in f32
36821fmovs %f16, %f20
36822fadds %f16, %f17, %f16
36823! preparing store val #1, next val will be in f33
36824fmovs %f16, %f21
36825fadds %f16, %f17, %f16
36826! preparing store val #2, next val will be in f35
36827fmovd %f20, %f32
36828fmovs %f16, %f21
36829fadds %f16, %f17, %f16
36830fmovd %f20, %f34
36831membar #Sync
36832stda %f32, [%i3 + 0 ] %asi
36833
36834P3221: !_MEMBAR (FP) (CBR)
36835membar #StoreLoad
36836
36837! cbranch
36838andcc %l0, 1, %g0
36839be,pt %xcc, TARGET3221
36840nop
36841RET3221:
36842
36843! lfsr step begin
36844srlx %l0, 1, %l6
36845xnor %l6, %l0, %l6
36846sllx %l6, 63, %l6
36847or %l6, %l0, %l0
36848srlx %l0, 1, %l0
36849
36850
36851P3222: !_PREFETCH [2] (Int)
36852prefetch [%i0 + 12], 21
36853
36854P3223: !_MEMBAR (FP)
36855
36856P3224: !_BSTC [7] (maybe <- 0x4100002e) (FP)
36857wr %g0, 0xe0, %asi
36858sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
36859sub %i0, %i2, %i2
36860! preparing store val #0, next val will be in f32
36861fmovs %f16, %f20
36862fadds %f16, %f17, %f16
36863! preparing store val #1, next val will be in f33
36864fmovs %f16, %f21
36865fadds %f16, %f17, %f16
36866! preparing store val #2, next val will be in f35
36867fmovd %f20, %f32
36868fmovs %f16, %f21
36869fadds %f16, %f17, %f16
36870fmovd %f20, %f34
36871membar #Sync
36872stda %f32, [%i2 + 0 ] %asi
36873
36874P3225: !_MEMBAR (FP)
36875membar #StoreLoad
36876
36877P3226: !_DWST [0] (maybe <- 0x180005f) (Int)
36878sllx %l4, 32, %l6
36879add %l4, 1, %l4
36880or %l6, %l4, %l6
36881stx %l6, [%i0 + 0]
36882add %l4, 1, %l4
36883
36884P3227: !_ST [13] (maybe <- 0x1800061) (Int)
36885sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
36886sub %i0, %i3, %i3
36887stw %l4, [%i3 + 4 ]
36888add %l4, 1, %l4
36889
36890P3228: !_CAS [19] (maybe <- 0x1800062) (Int)
36891sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
36892sub %i0, %i2, %i2
36893add %i2, 4, %l3
36894lduw [%l3], %o4
36895mov %o4, %o5
36896! move %o5(lower) -> %o4(upper)
36897sllx %o5, 32, %o4
36898mov %l4, %l7
36899cas [%l3], %o5, %l7
36900! move %l7(lower) -> %o4(lower)
36901srl %l7, 0, %o5
36902or %o5, %o4, %o4
36903!---- flushing int results buffer----
36904mov %o0, %l5
36905mov %o1, %l5
36906mov %o2, %l5
36907mov %o3, %l5
36908mov %o4, %l5
36909add %l4, 1, %l4
36910
36911P3229: !_DWLD [0] (Int)
36912ldx [%i0 + 0], %o0
36913! move %o0(upper) -> %o0(upper)
36914! move %o0(lower) -> %o0(lower)
36915
36916P3230: !_CASX [16] (maybe <- 0x1800063) (Int)
36917sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
36918sub %i0, %i3, %i3
36919ldx [%i3], %o1
36920! move %o1(upper) -> %o1(upper)
36921! move %o1(lower) -> %o1(lower)
36922mov %o1, %l6
36923sllx %l4, 32, %o2
36924add %l4, 1, %l4
36925or %l4, %o2, %o2
36926casx [%i3], %l6, %o2
36927! move %o2(upper) -> %o2(upper)
36928! move %o2(lower) -> %o2(lower)
36929add %l4, 1, %l4
36930
36931P3231: !_CASX [1] (maybe <- 0x1800065) (Int)
36932ldx [%i0], %o3
36933! move %o3(upper) -> %o3(upper)
36934! move %o3(lower) -> %o3(lower)
36935mov %o3, %l6
36936sllx %l4, 32, %o4
36937add %l4, 1, %l4
36938or %l4, %o4, %o4
36939casx [%i0], %l6, %o4
36940! move %o4(upper) -> %o4(upper)
36941! move %o4(lower) -> %o4(lower)
36942!---- flushing int results buffer----
36943mov %o0, %l5
36944mov %o1, %l5
36945mov %o2, %l5
36946mov %o3, %l5
36947mov %o4, %l5
36948add %l4, 1, %l4
36949
36950P3232: !_LD [22] (Int)
36951sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
36952add %i0, %i2, %i2
36953lduw [%i2 + 4], %o0
36954! move %o0(lower) -> %o0(upper)
36955sllx %o0, 32, %o0
36956
36957P3233: !_DWST [21] (maybe <- 0x1800067) (Int)
36958sllx %l4, 32, %o5
36959add %l4, 1, %l4
36960or %o5, %l4, %o5
36961stx %o5, [%i2 + 0]
36962add %l4, 1, %l4
36963
36964P3234: !_LDD [21] (Int)
36965ldd [%i2 + 0], %l6
36966! move %l6(lower) -> %o0(lower)
36967or %l6, %o0, %o0
36968! move %l7(lower) -> %o1(upper)
36969sllx %l7, 32, %o1
36970
36971P3235: !_MEMBAR (FP)
36972membar #StoreLoad
36973
36974P3236: !_BLD [14] (FP)
36975wr %g0, 0xf0, %asi
36976sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
36977sub %i0, %i3, %i3
36978ldda [%i3 + 0] %asi, %f32
36979membar #Sync
36980! 3 addresses covered
36981fmovd %f32, %f2
36982fmovd %f34, %f18
36983fmovs %f19, %f4
36984
36985P3237: !_MEMBAR (FP)
36986
36987P3238: !_DWLD [1] (Int)
36988ldx [%i0 + 0], %l6
36989! move %l6(upper) -> %o1(lower)
36990srlx %l6, 32, %l3
36991or %l3, %o1, %o1
36992! move %l6(lower) -> %o2(upper)
36993sllx %l6, 32, %o2
36994
36995P3239: !_LDD [0] (Int) (Branch target of P3025)
36996ldd [%i0 + 0], %l6
36997! move %l6(lower) -> %o2(lower)
36998or %l6, %o2, %o2
36999! move %l7(lower) -> %o3(upper)
37000sllx %l7, 32, %o3
37001ba P3240
37002nop
37003
37004TARGET3025:
37005ba RET3025
37006nop
37007
37008
37009P3240: !_LD [14] (Int) (Branch target of P3063)
37010lduw [%i3 + 12], %l6
37011! move %l6(lower) -> %o3(lower)
37012or %l6, %o3, %o3
37013ba P3241
37014nop
37015
37016TARGET3063:
37017ba RET3063
37018nop
37019
37020
37021P3241: !_CAS [22] (maybe <- 0x1800069) (Int)
37022add %i2, 4, %o5
37023lduw [%o5], %o4
37024mov %o4, %l7
37025! move %l7(lower) -> %o4(upper)
37026sllx %l7, 32, %o4
37027mov %l4, %l6
37028cas [%o5], %l7, %l6
37029! move %l6(lower) -> %o4(lower)
37030srl %l6, 0, %l7
37031or %l7, %o4, %o4
37032!---- flushing int results buffer----
37033mov %o0, %l5
37034mov %o1, %l5
37035mov %o2, %l5
37036mov %o3, %l5
37037mov %o4, %l5
37038add %l4, 1, %l4
37039
37040P3242: !_SWAP [1] (maybe <- 0x180006a) (Int)
37041mov %l4, %o0
37042swap [%i0 + 4], %o0
37043! move %o0(lower) -> %o0(upper)
37044sllx %o0, 32, %o0
37045add %l4, 1, %l4
37046
37047P3243: !_LD [8] (Int)
37048sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
37049sub %i0, %i2, %i2
37050lduw [%i2 + 12], %l7
37051! move %l7(lower) -> %o0(lower)
37052or %l7, %o0, %o0
37053
37054P3244: !_ST_BINIT [6] (maybe <- 0x180006b) (Int)
37055wr %g0, 0xe2, %asi
37056stwa %l4, [%i2 + 0] %asi
37057add %l4, 1, %l4
37058
37059P3245: !_MEMBAR (Int)
37060membar #StoreLoad
37061
37062P3246: !_CAS [4] (maybe <- 0x180006c) (Int)
37063add %i1, 4, %o5
37064lduw [%o5], %o1
37065mov %o1, %l7
37066! move %l7(lower) -> %o1(upper)
37067sllx %l7, 32, %o1
37068mov %l4, %l6
37069cas [%o5], %l7, %l6
37070! move %l6(lower) -> %o1(lower)
37071srl %l6, 0, %l7
37072or %l7, %o1, %o1
37073add %l4, 1, %l4
37074
37075P3247: !_DWST_BINIT [23] (maybe <- 0x180006d) (Int)
37076wr %g0, 0xe2, %asi
37077sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
37078add %i0, %i3, %i3
37079mov %l4, %l7
37080stxa %l7, [%i3 + 8] %asi
37081add %l4, 1, %l4
37082
37083P3248: !_MEMBAR (Int) (CBR)
37084membar #StoreLoad
37085
37086! cbranch
37087andcc %l0, 1, %g0
37088be,pn %xcc, TARGET3248
37089nop
37090RET3248:
37091
37092! lfsr step begin
37093srlx %l0, 1, %l6
37094xnor %l6, %l0, %l6
37095sllx %l6, 63, %l6
37096or %l6, %l0, %l0
37097srlx %l0, 1, %l0
37098
37099
37100P3249: !_LDD [22] (Int)
37101ldd [%i3 + 0], %l6
37102! move %l6(lower) -> %o2(upper)
37103sllx %l6, 32, %o2
37104! move %l7(lower) -> %o2(lower)
37105or %l7, %o2, %o2
37106
37107P3250: !_ST [22] (maybe <- 0x180006e) (Int)
37108stw %l4, [%i3 + 4 ]
37109add %l4, 1, %l4
37110
37111P3251: !_LDD [7] (Int)
37112ldd [%i2 + 0], %l6
37113! move %l6(lower) -> %o3(upper)
37114sllx %l6, 32, %o3
37115! move %l7(lower) -> %o3(lower)
37116or %l7, %o3, %o3
37117
37118P3252: !_ST [3] (maybe <- 0x180006f) (Int)
37119stw %l4, [%i1 + 0 ]
37120add %l4, 1, %l4
37121
37122P3253: !_MEMBAR (FP)
37123
37124P3254: !_BST [2] (maybe <- 0x41000031) (FP)
37125wr %g0, 0xf0, %asi
37126! preparing store val #0, next val will be in f32
37127fmovs %f16, %f20
37128fadds %f16, %f17, %f16
37129! preparing store val #1, next val will be in f33
37130fmovs %f16, %f21
37131fadds %f16, %f17, %f16
37132! preparing store val #2, next val will be in f35
37133fmovd %f20, %f32
37134fmovs %f16, %f21
37135fadds %f16, %f17, %f16
37136fmovd %f20, %f34
37137membar #Sync
37138stda %f32, [%i0 + 0 ] %asi
37139
37140P3255: !_MEMBAR (FP)
37141membar #StoreLoad
37142
37143P3256: !_ST_BINIT [2] (maybe <- 0x1800070) (Int) (CBR)
37144wr %g0, 0xe2, %asi
37145stwa %l4, [%i0 + 12] %asi
37146add %l4, 1, %l4
37147
37148! cbranch
37149andcc %l0, 1, %g0
37150be,pt %xcc, TARGET3256
37151nop
37152RET3256:
37153
37154! lfsr step begin
37155srlx %l0, 1, %l6
37156xnor %l6, %l0, %l6
37157sllx %l6, 63, %l6
37158or %l6, %l0, %l0
37159srlx %l0, 1, %l0
37160
37161
37162P3257: !_MEMBAR (Int)
37163membar #StoreLoad
37164
37165P3258: !_LD [17] (Int)
37166sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
37167sub %i0, %i2, %i2
37168lduw [%i2 + 12], %o4
37169! move %o4(lower) -> %o4(upper)
37170sllx %o4, 32, %o4
37171
37172P3259: !_MEMBAR (FP)
37173
37174P3260: !_BST [20] (maybe <- 0x41000034) (FP)
37175wr %g0, 0xf0, %asi
37176sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
37177sub %i0, %i3, %i3
37178! preparing store val #0, next val will be in f32
37179fmovs %f16, %f20
37180fadds %f16, %f17, %f16
37181! preparing store val #1, next val will be in f33
37182fmovs %f16, %f21
37183fadds %f16, %f17, %f16
37184! preparing store val #2, next val will be in f35
37185fmovd %f20, %f32
37186fmovs %f16, %f21
37187fadds %f16, %f17, %f16
37188fmovd %f20, %f34
37189membar #Sync
37190stda %f32, [%i3 + 0 ] %asi
37191
37192P3261: !_MEMBAR (FP)
37193membar #StoreLoad
37194
37195P3262: !_LDD [1] (Int) (CBR)
37196ldd [%i0 + 0], %l6
37197! move %l6(lower) -> %o4(lower)
37198or %l6, %o4, %o4
37199!---- flushing int results buffer----
37200mov %o0, %l5
37201mov %o1, %l5
37202mov %o2, %l5
37203mov %o3, %l5
37204mov %o4, %l5
37205! move %l7(lower) -> %o0(upper)
37206sllx %l7, 32, %o0
37207
37208! cbranch
37209andcc %l0, 1, %g0
37210be,pn %xcc, TARGET3262
37211nop
37212RET3262:
37213
37214! lfsr step begin
37215srlx %l0, 1, %l3
37216xnor %l3, %l0, %l3
37217sllx %l3, 63, %l3
37218or %l3, %l0, %l0
37219srlx %l0, 1, %l0
37220
37221
37222P3263: !_MEMBAR (FP)
37223
37224P3264: !_BSTC [6] (maybe <- 0x41000037) (FP)
37225wr %g0, 0xe0, %asi
37226sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
37227sub %i0, %i2, %i2
37228! preparing store val #0, next val will be in f32
37229fmovs %f16, %f20
37230fadds %f16, %f17, %f16
37231! preparing store val #1, next val will be in f33
37232fmovs %f16, %f21
37233fadds %f16, %f17, %f16
37234! preparing store val #2, next val will be in f35
37235fmovd %f20, %f32
37236fmovs %f16, %f21
37237fadds %f16, %f17, %f16
37238fmovd %f20, %f34
37239membar #Sync
37240stda %f32, [%i2 + 0 ] %asi
37241
37242P3265: !_MEMBAR (FP)
37243
37244P3266: !_BST [0] (maybe <- 0x4100003a) (FP)
37245wr %g0, 0xf0, %asi
37246! preparing store val #0, next val will be in f32
37247fmovs %f16, %f20
37248fadds %f16, %f17, %f16
37249! preparing store val #1, next val will be in f33
37250fmovs %f16, %f21
37251fadds %f16, %f17, %f16
37252! preparing store val #2, next val will be in f35
37253fmovd %f20, %f32
37254fmovs %f16, %f21
37255fadds %f16, %f17, %f16
37256fmovd %f20, %f34
37257membar #Sync
37258stda %f32, [%i0 + 0 ] %asi
37259
37260P3267: !_MEMBAR (FP)
37261membar #StoreLoad
37262
37263P3268: !_DWST_BINIT [5] (maybe <- 0x1800071) (Int) (LE)
37264wr %g0, 0xea, %asi
37265! Change single-word-level endianess (big endian <-> little endian)
37266sethi %hi(0xff00ff00), %o5
37267or %o5, %lo(0xff00ff00), %o5
37268and %l4, %o5, %l6
37269srl %l6, 8, %l6
37270sll %l4, 8, %l3
37271and %l3, %o5, %l3
37272or %l3, %l6, %l3
37273srl %l3, 16, %l6
37274sll %l3, 16, %l3
37275srl %l3, 0, %l3
37276or %l3, %l6, %l3
37277sllx %l3, 32, %l3
37278stxa %l3, [%i1 + 8 ] %asi
37279add %l4, 1, %l4
37280
37281P3269: !_MEMBAR (Int) (LE)
37282membar #StoreLoad
37283
37284P3270: !_DWST [15] (maybe <- 0x1800072) (Int)
37285sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
37286sub %i0, %i3, %i3
37287sllx %l4, 32, %l7
37288add %l4, 1, %l4
37289or %l7, %l4, %l7
37290stx %l7, [%i3 + 0]
37291add %l4, 1, %l4
37292
37293P3271: !_ST [13] (maybe <- 0x1800074) (Int)
37294sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
37295sub %i0, %i2, %i2
37296stw %l4, [%i2 + 4 ]
37297add %l4, 1, %l4
37298
37299P3272: !_REPLACEMENT [23] (Int)
37300sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
37301sub %i0, %i3, %i3
37302sethi %hi(0x20000), %l3
37303ld [%i3+12], %l7
37304st %l7, [%i3+12]
37305add %i3, %l3, %l6
37306ld [%l6+12], %l7
37307st %l7, [%l6+12]
37308add %l6, %l3, %l6
37309ld [%l6+12], %l7
37310st %l7, [%l6+12]
37311add %l6, %l3, %l6
37312ld [%l6+12], %l7
37313st %l7, [%l6+12]
37314add %l6, %l3, %l6
37315ld [%l6+12], %l7
37316st %l7, [%l6+12]
37317add %l6, %l3, %l6
37318ld [%l6+12], %l7
37319st %l7, [%l6+12]
37320add %l6, %l3, %l6
37321ld [%l6+12], %l7
37322st %l7, [%l6+12]
37323add %l6, %l3, %l6
37324ld [%l6+12], %l7
37325st %l7, [%l6+12]
37326
37327P3273: !_DWST [16] (maybe <- 0x1800075) (Int)
37328sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
37329sub %i0, %i2, %i2
37330sllx %l4, 32, %o5
37331add %l4, 1, %l4
37332or %o5, %l4, %o5
37333stx %o5, [%i2 + 0]
37334add %l4, 1, %l4
37335
37336P3274: !_REPLACEMENT [1] (Int)
37337sethi %hi(0x20000), %l7
37338ld [%i3+4], %l3
37339st %l3, [%i3+4]
37340add %i3, %l7, %o5
37341ld [%o5+4], %l3
37342st %l3, [%o5+4]
37343add %o5, %l7, %o5
37344ld [%o5+4], %l3
37345st %l3, [%o5+4]
37346add %o5, %l7, %o5
37347ld [%o5+4], %l3
37348st %l3, [%o5+4]
37349add %o5, %l7, %o5
37350ld [%o5+4], %l3
37351st %l3, [%o5+4]
37352add %o5, %l7, %o5
37353ld [%o5+4], %l3
37354st %l3, [%o5+4]
37355add %o5, %l7, %o5
37356ld [%o5+4], %l3
37357st %l3, [%o5+4]
37358add %o5, %l7, %o5
37359ld [%o5+4], %l3
37360st %l3, [%o5+4]
37361
37362P3275: !_CASX [6] (maybe <- 0x1800077) (Int)
37363sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
37364sub %i0, %i3, %i3
37365ldx [%i3], %l3
37366! move %l3(upper) -> %o0(lower)
37367srlx %l3, 32, %l6
37368or %l6, %o0, %o0
37369! move %l3(lower) -> %o1(upper)
37370sllx %l3, 32, %o1
37371mov %l3, %l6
37372sllx %l4, 32, %l3
37373add %l4, 1, %l4
37374or %l4, %l3, %l3
37375casx [%i3], %l6, %l3
37376! move %l3(upper) -> %o1(lower)
37377srlx %l3, 32, %l6
37378or %l6, %o1, %o1
37379! move %l3(lower) -> %o2(upper)
37380sllx %l3, 32, %o2
37381add %l4, 1, %l4
37382
37383P3276: !_DWLD [9] (Int)
37384sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
37385add %i0, %i2, %i2
37386ldx [%i2 + 0], %l7
37387! move %l7(upper) -> %o2(lower)
37388srlx %l7, 32, %l6
37389or %l6, %o2, %o2
37390! move %l7(lower) -> %o3(upper)
37391sllx %l7, 32, %o3
37392
37393P3277: !_SWAP [6] (maybe <- 0x1800079) (Int)
37394mov %l4, %l6
37395swap [%i3 + 0], %l6
37396! move %l6(lower) -> %o3(lower)
37397srl %l6, 0, %o5
37398or %o5, %o3, %o3
37399add %l4, 1, %l4
37400
37401P3278: !_MEMBAR (FP)
37402membar #StoreLoad
37403
37404P3279: !_BLD [12] (FP) (CBR) (Branch target of P3279)
37405wr %g0, 0xf0, %asi
37406sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
37407sub %i0, %i3, %i3
37408ldda [%i3 + 0] %asi, %f32
37409membar #Sync
37410! 3 addresses covered
37411fmovd %f32, %f18
37412fmovs %f18, %f5
37413fmovs %f19, %f6
37414fmovd %f34, %f18
37415fmovs %f19, %f7
37416
37417! cbranch
37418andcc %l0, 1, %g0
37419be,pt %xcc, TARGET3279
37420nop
37421RET3279:
37422
37423! lfsr step begin
37424srlx %l0, 1, %l7
37425xnor %l7, %l0, %l7
37426sllx %l7, 63, %l7
37427or %l7, %l0, %l0
37428srlx %l0, 1, %l0
37429
37430ba P3280
37431nop
37432
37433TARGET3279:
37434ba RET3279
37435nop
37436
37437
37438P3280: !_MEMBAR (FP)
37439
37440P3281: !_ST_BINIT [9] (maybe <- 0x180007a) (Int) (CBR)
37441wr %g0, 0xe2, %asi
37442stwa %l4, [%i2 + 0] %asi
37443add %l4, 1, %l4
37444
37445! cbranch
37446andcc %l0, 1, %g0
37447be,pn %xcc, TARGET3281
37448nop
37449RET3281:
37450
37451! lfsr step begin
37452srlx %l0, 1, %l7
37453xnor %l7, %l0, %l7
37454sllx %l7, 63, %l7
37455or %l7, %l0, %l0
37456srlx %l0, 1, %l0
37457
37458
37459P3282: !_MEMBAR (Int)
37460membar #StoreLoad
37461
37462P3283: !_LDD [2] (Int)
37463ldd [%i0 + 8], %l6
37464! move %l7(lower) -> %o4(upper)
37465sllx %l7, 32, %o4
37466
37467P3284: !_MEMBAR (FP)
37468
37469P3285: !_BST [19] (maybe <- 0x4100003d) (FP)
37470wr %g0, 0xf0, %asi
37471sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
37472sub %i0, %i2, %i2
37473! preparing store val #0, next val will be in f32
37474fmovs %f16, %f20
37475fadds %f16, %f17, %f16
37476! preparing store val #1, next val will be in f33
37477fmovs %f16, %f21
37478fadds %f16, %f17, %f16
37479! preparing store val #2, next val will be in f35
37480fmovd %f20, %f32
37481fmovs %f16, %f21
37482fadds %f16, %f17, %f16
37483fmovd %f20, %f34
37484membar #Sync
37485stda %f32, [%i2 + 0 ] %asi
37486
37487P3286: !_MEMBAR (FP)
37488membar #StoreLoad
37489
37490P3287: !_CASX [16] (maybe <- 0x180007b) (Int)
37491sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
37492sub %i0, %i3, %i3
37493ldx [%i3], %l7
37494! move %l7(upper) -> %o4(lower)
37495srlx %l7, 32, %o5
37496or %o5, %o4, %o4
37497!---- flushing int results buffer----
37498mov %o0, %l5
37499mov %o1, %l5
37500mov %o2, %l5
37501mov %o3, %l5
37502mov %o4, %l5
37503! move %l7(lower) -> %o0(upper)
37504sllx %l7, 32, %o0
37505mov %l7, %o5
37506sllx %l4, 32, %l7
37507add %l4, 1, %l4
37508or %l4, %l7, %l7
37509casx [%i3], %o5, %l7
37510! move %l7(upper) -> %o0(lower)
37511srlx %l7, 32, %o5
37512or %o5, %o0, %o0
37513! move %l7(lower) -> %o1(upper)
37514sllx %l7, 32, %o1
37515add %l4, 1, %l4
37516
37517P3288: !_DWST_BINIT [1] (maybe <- 0x180007d) (Int) (Branch target of P3714)
37518wr %g0, 0xe2, %asi
37519sllx %l4, 32, %o5
37520add %l4, 1, %l4
37521or %o5, %l4, %o5
37522stxa %o5, [%i0 + 0] %asi
37523add %l4, 1, %l4
37524ba P3289
37525nop
37526
37527TARGET3714:
37528ba RET3714
37529nop
37530
37531
37532P3289: !_MEMBAR (Int)
37533
37534P3290: !_BST [10] (maybe <- 0x41000040) (FP)
37535wr %g0, 0xf0, %asi
37536sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
37537add %i0, %i2, %i2
37538! preparing store val #0, next val will be in f32
37539fmovs %f16, %f20
37540fadds %f16, %f17, %f16
37541! preparing store val #1, next val will be in f33
37542fmovs %f16, %f21
37543fadds %f16, %f17, %f16
37544! preparing store val #2, next val will be in f35
37545fmovd %f20, %f32
37546fmovs %f16, %f21
37547fadds %f16, %f17, %f16
37548fmovd %f20, %f34
37549membar #Sync
37550stda %f32, [%i2 + 0 ] %asi
37551
37552P3291: !_MEMBAR (FP)
37553membar #StoreLoad
37554
37555P3292: !_ST [18] (maybe <- 0x41000043) (FP)
37556sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
37557sub %i0, %i3, %i3
37558! preparing store val #0, next val will be in f20
37559fmovs %f16, %f20
37560fadds %f16, %f17, %f16
37561st %f20, [%i3 + 0 ]
37562
37563P3293: !_DWST_BINIT [3] (maybe <- 0x180007f) (Int)
37564wr %g0, 0xe2, %asi
37565sllx %l4, 32, %l3
37566add %l4, 1, %l4
37567or %l3, %l4, %l3
37568stxa %l3, [%i1 + 0] %asi
37569add %l4, 1, %l4
37570
37571P3294: !_MEMBAR (Int)
37572membar #StoreLoad
37573
37574P3295: !_LDD [14] (Int)
37575sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
37576sub %i0, %i2, %i2
37577ldd [%i2 + 8], %l6
37578! move %l7(lower) -> %o1(lower)
37579or %l7, %o1, %o1
37580
37581P3296: !_LD [16] (Int)
37582sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
37583sub %i0, %i3, %i3
37584lduw [%i3 + 4], %o2
37585! move %o2(lower) -> %o2(upper)
37586sllx %o2, 32, %o2
37587
37588P3297: !_DWST_BINIT [13] (maybe <- 0x1800081) (Int)
37589wr %g0, 0xe2, %asi
37590sllx %l4, 32, %l7
37591add %l4, 1, %l4
37592or %l7, %l4, %l7
37593stxa %l7, [%i2 + 0] %asi
37594add %l4, 1, %l4
37595
37596P3298: !_MEMBAR (Int)
37597membar #StoreLoad
37598
37599P3299: !_CAS [20] (maybe <- 0x1800083) (Int) (LE)
37600! Change single-word-level endianess (big endian <-> little endian)
37601sethi %hi(0xff00ff00), %l7
37602or %l7, %lo(0xff00ff00), %l7
37603and %l4, %l7, %l6
37604srl %l6, 8, %l6
37605sll %l4, 8, %o5
37606and %o5, %l7, %o5
37607or %o5, %l6, %o5
37608srl %o5, 16, %l6
37609sll %o5, 16, %o5
37610srl %o5, 0, %o5
37611or %o5, %l6, %o5
37612wr %g0, 0x88, %asi
37613sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
37614sub %i0, %i2, %i2
37615add %i2, 12, %l7
37616lduwa [%l7] %asi, %l3
37617mov %l3, %l6
37618! move %l6(lower) -> %o2(lower)
37619or %l6, %o2, %o2
37620mov %o5, %o3
37621casa [%l7] %asi, %l6, %o3
37622! move %o3(lower) -> %o3(upper)
37623sllx %o3, 32, %o3
37624add %l4, 1, %l4
37625
37626P3300: !_ST [22] (maybe <- 0x1800084) (Int)
37627sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
37628add %i0, %i3, %i3
37629stw %l4, [%i3 + 4 ]
37630add %l4, 1, %l4
37631
37632P3301: !_MEMBAR (FP) (CBR)
37633
37634! cbranch
37635andcc %l0, 1, %g0
37636be,pt %xcc, TARGET3301
37637nop
37638RET3301:
37639
37640! lfsr step begin
37641srlx %l0, 1, %l3
37642xnor %l3, %l0, %l3
37643sllx %l3, 63, %l3
37644or %l3, %l0, %l0
37645srlx %l0, 1, %l0
37646
37647
37648P3302: !_BST [4] (maybe <- 0x41000044) (FP)
37649wr %g0, 0xf0, %asi
37650! preparing store val #0, next val will be in f32
37651fmovs %f16, %f20
37652fadds %f16, %f17, %f16
37653! preparing store val #1, next val will be in f33
37654fmovs %f16, %f21
37655fadds %f16, %f17, %f16
37656! preparing store val #2, next val will be in f35
37657fmovd %f20, %f32
37658fmovs %f16, %f21
37659fadds %f16, %f17, %f16
37660fmovd %f20, %f34
37661membar #Sync
37662stda %f32, [%i1 + 0 ] %asi
37663
37664P3303: !_MEMBAR (FP)
37665
37666P3304: !_BSTC [2] (maybe <- 0x41000047) (FP)
37667wr %g0, 0xe0, %asi
37668! preparing store val #0, next val will be in f32
37669fmovs %f16, %f20
37670fadds %f16, %f17, %f16
37671! preparing store val #1, next val will be in f33
37672fmovs %f16, %f21
37673fadds %f16, %f17, %f16
37674! preparing store val #2, next val will be in f35
37675fmovd %f20, %f32
37676fmovs %f16, %f21
37677fadds %f16, %f17, %f16
37678fmovd %f20, %f34
37679membar #Sync
37680stda %f32, [%i0 + 0 ] %asi
37681
37682P3305: !_MEMBAR (FP) (CBR)
37683membar #StoreLoad
37684
37685! cbranch
37686andcc %l0, 1, %g0
37687be,pn %xcc, TARGET3305
37688nop
37689RET3305:
37690
37691! lfsr step begin
37692srlx %l0, 1, %o5
37693xnor %o5, %l0, %o5
37694sllx %o5, 63, %o5
37695or %o5, %l0, %l0
37696srlx %l0, 1, %l0
37697
37698
37699P3306: !_REPLACEMENT [9] (Int)
37700sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
37701sub %i0, %i2, %i2
37702sethi %hi(0x20000), %l3
37703ld [%i2+0], %l7
37704st %l7, [%i2+0]
37705add %i2, %l3, %l6
37706ld [%l6+0], %l7
37707st %l7, [%l6+0]
37708add %l6, %l3, %l6
37709ld [%l6+0], %l7
37710st %l7, [%l6+0]
37711add %l6, %l3, %l6
37712ld [%l6+0], %l7
37713st %l7, [%l6+0]
37714add %l6, %l3, %l6
37715ld [%l6+0], %l7
37716st %l7, [%l6+0]
37717add %l6, %l3, %l6
37718ld [%l6+0], %l7
37719st %l7, [%l6+0]
37720add %l6, %l3, %l6
37721ld [%l6+0], %l7
37722st %l7, [%l6+0]
37723add %l6, %l3, %l6
37724ld [%l6+0], %l7
37725st %l7, [%l6+0]
37726
37727P3307: !_MEMBAR (FP)
37728
37729P3308: !_BST [6] (maybe <- 0x4100004a) (FP)
37730wr %g0, 0xf0, %asi
37731sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
37732sub %i0, %i3, %i3
37733! preparing store val #0, next val will be in f32
37734fmovs %f16, %f20
37735fadds %f16, %f17, %f16
37736! preparing store val #1, next val will be in f33
37737fmovs %f16, %f21
37738fadds %f16, %f17, %f16
37739! preparing store val #2, next val will be in f35
37740fmovd %f20, %f32
37741fmovs %f16, %f21
37742fadds %f16, %f17, %f16
37743fmovd %f20, %f34
37744membar #Sync
37745stda %f32, [%i3 + 0 ] %asi
37746
37747P3309: !_MEMBAR (FP)
37748membar #StoreLoad
37749
37750P3310: !_CASX [19] (maybe <- 0x1800085) (Int)
37751sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
37752sub %i0, %i2, %i2
37753ldx [%i2], %l6
37754! move %l6(upper) -> %o3(lower)
37755srlx %l6, 32, %l7
37756or %l7, %o3, %o3
37757! move %l6(lower) -> %o4(upper)
37758sllx %l6, 32, %o4
37759mov %l6, %l7
37760sllx %l4, 32, %l6
37761add %l4, 1, %l4
37762or %l4, %l6, %l6
37763casx [%i2], %l7, %l6
37764! move %l6(upper) -> %o4(lower)
37765srlx %l6, 32, %l7
37766or %l7, %o4, %o4
37767!---- flushing int results buffer----
37768mov %o0, %l5
37769mov %o1, %l5
37770mov %o2, %l5
37771mov %o3, %l5
37772mov %o4, %l5
37773! move %l6(lower) -> %o0(upper)
37774sllx %l6, 32, %o0
37775add %l4, 1, %l4
37776
37777P3311: !_CASX [10] (maybe <- 0x1800087) (Int)
37778sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
37779add %i0, %i3, %i3
37780ldx [%i3], %l6
37781! move %l6(upper) -> %o0(lower)
37782srlx %l6, 32, %l7
37783or %l7, %o0, %o0
37784! move %l6(lower) -> %o1(upper)
37785sllx %l6, 32, %o1
37786mov %l6, %l7
37787sllx %l4, 32, %l6
37788add %l4, 1, %l4
37789or %l4, %l6, %l6
37790casx [%i3], %l7, %l6
37791! move %l6(upper) -> %o1(lower)
37792srlx %l6, 32, %l7
37793or %l7, %o1, %o1
37794! move %l6(lower) -> %o2(upper)
37795sllx %l6, 32, %o2
37796add %l4, 1, %l4
37797
37798P3312: !_LDD [4] (Int)
37799ldd [%i1 + 0], %l6
37800! move %l6(lower) -> %o2(lower)
37801or %l6, %o2, %o2
37802! move %l7(lower) -> %o3(upper)
37803sllx %l7, 32, %o3
37804
37805P3313: !_PREFETCH [15] (Int)
37806sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
37807sub %i0, %i2, %i2
37808prefetch [%i2 + 0], 3
37809
37810P3314: !_ST_BINIT [10] (maybe <- 0x1800089) (Int)
37811wr %g0, 0xe2, %asi
37812stwa %l4, [%i3 + 4] %asi
37813add %l4, 1, %l4
37814
37815P3315: !_MEMBAR (Int)
37816membar #StoreLoad
37817
37818P3316: !_DWST [16] (maybe <- 0x180008a) (Int)
37819sllx %l4, 32, %o5
37820add %l4, 1, %l4
37821or %o5, %l4, %o5
37822stx %o5, [%i2 + 0]
37823add %l4, 1, %l4
37824
37825P3317: !_MEMBAR (FP)
37826membar #StoreLoad
37827
37828P3318: !_BLD [1] (FP)
37829wr %g0, 0xf0, %asi
37830ldda [%i0 + 0] %asi, %f32
37831membar #Sync
37832! 3 addresses covered
37833fmovd %f32, %f8
37834fmovd %f34, %f18
37835fmovs %f19, %f10
37836
37837P3319: !_MEMBAR (FP)
37838
37839P3320: !_PREFETCH [1] (Int)
37840prefetch [%i0 + 4], 0
37841
37842P3321: !_REPLACEMENT [8] (Int)
37843sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
37844add %i0, %i3, %i3
37845sethi %hi(0x20000), %l7
37846ld [%i3+12], %l3
37847st %l3, [%i3+12]
37848add %i3, %l7, %o5
37849ld [%o5+12], %l3
37850st %l3, [%o5+12]
37851add %o5, %l7, %o5
37852ld [%o5+12], %l3
37853st %l3, [%o5+12]
37854add %o5, %l7, %o5
37855ld [%o5+12], %l3
37856st %l3, [%o5+12]
37857add %o5, %l7, %o5
37858ld [%o5+12], %l3
37859st %l3, [%o5+12]
37860add %o5, %l7, %o5
37861ld [%o5+12], %l3
37862st %l3, [%o5+12]
37863add %o5, %l7, %o5
37864ld [%o5+12], %l3
37865st %l3, [%o5+12]
37866add %o5, %l7, %o5
37867ld [%o5+12], %l3
37868st %l3, [%o5+12]
37869
37870P3322: !_ST [9] (maybe <- 0x180008c) (Int) (LE)
37871wr %g0, 0x88, %asi
37872sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
37873add %i0, %i2, %i2
37874! Change single-word-level endianess (big endian <-> little endian)
37875sethi %hi(0xff00ff00), %l7
37876or %l7, %lo(0xff00ff00), %l7
37877and %l4, %l7, %o5
37878srl %o5, 8, %o5
37879sll %l4, 8, %l6
37880and %l6, %l7, %l6
37881or %l6, %o5, %l6
37882srl %l6, 16, %o5
37883sll %l6, 16, %l6
37884srl %l6, 0, %l6
37885or %l6, %o5, %l6
37886stwa %l6, [%i2 + 0] %asi
37887add %l4, 1, %l4
37888
37889P3323: !_PREFETCH [16] (Int)
37890sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
37891sub %i0, %i3, %i3
37892prefetch [%i3 + 4], 1
37893
37894P3324: !_ST_BINIT [19] (maybe <- 0x180008d) (Int)
37895wr %g0, 0xe2, %asi
37896sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
37897sub %i0, %i2, %i2
37898stwa %l4, [%i2 + 4] %asi
37899add %l4, 1, %l4
37900
37901P3325: !_MEMBAR (Int)
37902membar #StoreLoad
37903
37904P3326: !_ST_BINIT [6] (maybe <- 0x180008e) (Int)
37905wr %g0, 0xe2, %asi
37906sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
37907sub %i0, %i3, %i3
37908stwa %l4, [%i3 + 0] %asi
37909add %l4, 1, %l4
37910
37911P3327: !_MEMBAR (Int)
37912membar #StoreLoad
37913
37914P3328: !_CAS [7] (maybe <- 0x180008f) (Int)
37915add %i3, 4, %l3
37916lduw [%l3], %l7
37917mov %l7, %o5
37918! move %o5(lower) -> %o3(lower)
37919or %o5, %o3, %o3
37920mov %l4, %o4
37921cas [%l3], %o5, %o4
37922! move %o4(lower) -> %o4(upper)
37923sllx %o4, 32, %o4
37924add %l4, 1, %l4
37925
37926P3329: !_PREFETCH [4] (Int)
37927prefetch [%i1 + 4], 0
37928
37929P3330: !_DWST_BINIT [17] (maybe <- 0x1800090) (Int)
37930wr %g0, 0xe2, %asi
37931sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
37932sub %i0, %i2, %i2
37933mov %l4, %o5
37934stxa %o5, [%i2 + 8] %asi
37935add %l4, 1, %l4
37936
37937P3331: !_MEMBAR (Int)
37938membar #StoreLoad
37939
37940P3332: !_LDD [13] (Int) (LE)
37941wr %g0, 0x88, %asi
37942sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
37943sub %i0, %i3, %i3
37944ldda [%i3 + 0] %asi, %l6
37945! move %l6(lower) -> %o4(lower)
37946or %l6, %o4, %o4
37947!---- flushing int results buffer----
37948mov %o0, %l5
37949mov %o1, %l5
37950mov %o2, %l5
37951mov %o3, %l5
37952mov %o4, %l5
37953! move %l7(lower) -> %o0(upper)
37954sllx %l7, 32, %o0
37955
37956P3333: !_MEMBAR (FP)
37957
37958P3334: !_BST [8] (maybe <- 0x4100004d) (FP)
37959wr %g0, 0xf0, %asi
37960sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
37961sub %i0, %i2, %i2
37962! preparing store val #0, next val will be in f32
37963fmovs %f16, %f20
37964fadds %f16, %f17, %f16
37965! preparing store val #1, next val will be in f33
37966fmovs %f16, %f21
37967fadds %f16, %f17, %f16
37968! preparing store val #2, next val will be in f35
37969fmovd %f20, %f32
37970fmovs %f16, %f21
37971fadds %f16, %f17, %f16
37972fmovd %f20, %f34
37973membar #Sync
37974stda %f32, [%i2 + 0 ] %asi
37975
37976P3335: !_MEMBAR (FP)
37977membar #StoreLoad
37978
37979P3336: !_LD [22] (Int)
37980sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
37981add %i0, %i3, %i3
37982lduw [%i3 + 4], %l3
37983! move %l3(lower) -> %o0(lower)
37984or %l3, %o0, %o0
37985
37986P3337: !_MEMBAR (FP)
37987membar #StoreLoad
37988
37989P3338: !_BLD [8] (FP) (Branch target of P3399)
37990wr %g0, 0xf0, %asi
37991ldda [%i2 + 0] %asi, %f32
37992membar #Sync
37993! 3 addresses covered
37994fmovd %f32, %f18
37995fmovs %f18, %f11
37996fmovs %f19, %f12
37997fmovd %f34, %f18
37998fmovs %f19, %f13
37999ba P3339
38000nop
38001
38002TARGET3399:
38003ba RET3399
38004nop
38005
38006
38007P3339: !_MEMBAR (FP)
38008
38009P3340: !_SWAP [17] (maybe <- 0x1800091) (Int)
38010sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
38011sub %i0, %i2, %i2
38012mov %l4, %o1
38013swap [%i2 + 12], %o1
38014! move %o1(lower) -> %o1(upper)
38015sllx %o1, 32, %o1
38016add %l4, 1, %l4
38017
38018P3341: !_SWAP [8] (maybe <- 0x1800092) (Int)
38019sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
38020sub %i0, %i3, %i3
38021mov %l4, %l7
38022swap [%i3 + 12], %l7
38023! move %l7(lower) -> %o1(lower)
38024srl %l7, 0, %l3
38025or %l3, %o1, %o1
38026add %l4, 1, %l4
38027
38028P3342: !_SWAP [6] (maybe <- 0x1800093) (Int)
38029mov %l4, %o2
38030swap [%i3 + 0], %o2
38031! move %o2(lower) -> %o2(upper)
38032sllx %o2, 32, %o2
38033add %l4, 1, %l4
38034
38035P3343: !_ST_BINIT [21] (maybe <- 0x1800094) (Int) (Branch target of P3753)
38036wr %g0, 0xe2, %asi
38037sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
38038add %i0, %i2, %i2
38039stwa %l4, [%i2 + 0] %asi
38040add %l4, 1, %l4
38041ba P3344
38042nop
38043
38044TARGET3753:
38045ba RET3753
38046nop
38047
38048
38049P3344: !_MEMBAR (Int)
38050membar #StoreLoad
38051
38052P3345: !_DWLD [8] (FP)
38053ldd [%i3 + 8], %f14
38054! 1 addresses covered
38055fmovs %f15, %f14
38056
38057P3346: !_DWST [22] (maybe <- 0x1800095) (Int)
38058sllx %l4, 32, %l6
38059add %l4, 1, %l4
38060or %l6, %l4, %l6
38061stx %l6, [%i2 + 0]
38062add %l4, 1, %l4
38063
38064P3347: !_LD [5] (Int)
38065lduw [%i1 + 12], %l6
38066! move %l6(lower) -> %o2(lower)
38067or %l6, %o2, %o2
38068
38069P3348: !_SWAP [1] (maybe <- 0x1800097) (Int)
38070mov %l4, %o3
38071swap [%i0 + 4], %o3
38072! move %o3(lower) -> %o3(upper)
38073sllx %o3, 32, %o3
38074add %l4, 1, %l4
38075
38076P3349: !_CAS [7] (maybe <- 0x1800098) (Int)
38077add %i3, 4, %l7
38078lduw [%l7], %l3
38079mov %l3, %l6
38080! move %l6(lower) -> %o3(lower)
38081or %l6, %o3, %o3
38082mov %l4, %o4
38083cas [%l7], %l6, %o4
38084! move %o4(lower) -> %o4(upper)
38085sllx %o4, 32, %o4
38086add %l4, 1, %l4
38087
38088P3350: !_MEMBAR (FP)
38089membar #StoreLoad
38090
38091P3351: !_BLD [5] (FP)
38092wr %g0, 0xf0, %asi
38093ldda [%i1 + 0] %asi, %f32
38094membar #Sync
38095! 3 addresses covered
38096fmovd %f32, %f18
38097fmovs %f18, %f15
38098!---- flushing fp results buffer to %f30 ----
38099fmovd %f0, %f30
38100fmovd %f2, %f30
38101fmovd %f4, %f30
38102fmovd %f6, %f30
38103fmovd %f8, %f30
38104fmovd %f10, %f30
38105fmovd %f12, %f30
38106fmovd %f14, %f30
38107!--
38108fmovs %f19, %f0
38109fmovd %f34, %f18
38110fmovs %f19, %f1
38111
38112P3352: !_MEMBAR (FP)
38113
38114P3353: !_BST [13] (maybe <- 0x41000050) (FP)
38115wr %g0, 0xf0, %asi
38116sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
38117sub %i0, %i3, %i3
38118! preparing store val #0, next val will be in f32
38119fmovs %f16, %f20
38120fadds %f16, %f17, %f16
38121! preparing store val #1, next val will be in f33
38122fmovs %f16, %f21
38123fadds %f16, %f17, %f16
38124! preparing store val #2, next val will be in f35
38125fmovd %f20, %f32
38126fmovs %f16, %f21
38127fadds %f16, %f17, %f16
38128fmovd %f20, %f34
38129membar #Sync
38130stda %f32, [%i3 + 0 ] %asi
38131
38132P3354: !_MEMBAR (FP)
38133membar #StoreLoad
38134
38135P3355: !_PREFETCH [12] (Int)
38136prefetch [%i3 + 0], 19
38137
38138P3356: !_CASX [21] (maybe <- 0x1800099) (Int)
38139ldx [%i2], %o5
38140! move %o5(upper) -> %o4(lower)
38141srlx %o5, 32, %l3
38142or %l3, %o4, %o4
38143!---- flushing int results buffer----
38144mov %o0, %l5
38145mov %o1, %l5
38146mov %o2, %l5
38147mov %o3, %l5
38148mov %o4, %l5
38149! move %o5(lower) -> %o0(upper)
38150sllx %o5, 32, %o0
38151mov %o5, %l3
38152sllx %l4, 32, %o5
38153add %l4, 1, %l4
38154or %l4, %o5, %o5
38155casx [%i2], %l3, %o5
38156! move %o5(upper) -> %o0(lower)
38157srlx %o5, 32, %l3
38158or %l3, %o0, %o0
38159! move %o5(lower) -> %o1(upper)
38160sllx %o5, 32, %o1
38161add %l4, 1, %l4
38162
38163P3357: !_SWAP [6] (maybe <- 0x180009b) (Int)
38164sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
38165sub %i0, %i2, %i2
38166mov %l4, %l7
38167swap [%i2 + 0], %l7
38168! move %l7(lower) -> %o1(lower)
38169srl %l7, 0, %l3
38170or %l3, %o1, %o1
38171add %l4, 1, %l4
38172
38173P3358: !_PREFETCH [8] (Int) (LE)
38174wr %g0, 0x88, %asi
38175prefetcha [%i2 + 12] %asi, 2
38176
38177P3359: !_DWST [20] (maybe <- 0x180009c) (Int)
38178sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
38179sub %i0, %i3, %i3
38180mov %l4, %o5
38181stx %o5, [%i3 + 8]
38182add %l4, 1, %l4
38183
38184P3360: !_CASX [4] (maybe <- 0x180009d) (Int) (CBR) (Branch target of P3305)
38185ldx [%i1], %o2
38186! move %o2(upper) -> %o2(upper)
38187! move %o2(lower) -> %o2(lower)
38188mov %o2, %l7
38189sllx %l4, 32, %o3
38190add %l4, 1, %l4
38191or %l4, %o3, %o3
38192casx [%i1], %l7, %o3
38193! move %o3(upper) -> %o3(upper)
38194! move %o3(lower) -> %o3(lower)
38195add %l4, 1, %l4
38196
38197! cbranch
38198andcc %l0, 1, %g0
38199be,pt %xcc, TARGET3360
38200nop
38201RET3360:
38202
38203! lfsr step begin
38204srlx %l0, 1, %l7
38205xnor %l7, %l0, %l7
38206sllx %l7, 63, %l7
38207or %l7, %l0, %l0
38208srlx %l0, 1, %l0
38209
38210ba P3361
38211nop
38212
38213TARGET3305:
38214ba RET3305
38215nop
38216
38217
38218P3361: !_LD [9] (Int)
38219sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
38220add %i0, %i2, %i2
38221lduw [%i2 + 0], %o4
38222! move %o4(lower) -> %o4(upper)
38223sllx %o4, 32, %o4
38224
38225P3362: !_ST [7] (maybe <- 0x180009f) (Int)
38226sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
38227sub %i0, %i3, %i3
38228stw %l4, [%i3 + 4 ]
38229add %l4, 1, %l4
38230
38231P3363: !_LDD [10] (Int)
38232ldd [%i2 + 0], %l6
38233! move %l6(lower) -> %o4(lower)
38234or %l6, %o4, %o4
38235!---- flushing int results buffer----
38236mov %o0, %l5
38237mov %o1, %l5
38238mov %o2, %l5
38239mov %o3, %l5
38240mov %o4, %l5
38241! move %l7(lower) -> %o0(upper)
38242sllx %l7, 32, %o0
38243
38244P3364: !_ST_BINIT [15] (maybe <- 0x18000a0) (Int)
38245wr %g0, 0xe2, %asi
38246sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
38247sub %i0, %i2, %i2
38248stwa %l4, [%i2 + 0] %asi
38249add %l4, 1, %l4
38250
38251P3365: !_MEMBAR (Int)
38252membar #StoreLoad
38253
38254P3366: !_CAS [4] (maybe <- 0x18000a1) (Int)
38255add %i1, 4, %l3
38256lduw [%l3], %l7
38257mov %l7, %o5
38258! move %o5(lower) -> %o0(lower)
38259or %o5, %o0, %o0
38260mov %l4, %o1
38261cas [%l3], %o5, %o1
38262! move %o1(lower) -> %o1(upper)
38263sllx %o1, 32, %o1
38264add %l4, 1, %l4
38265
38266P3367: !_MEMBAR (FP)
38267membar #StoreLoad
38268
38269P3368: !_BLD [23] (FP)
38270wr %g0, 0xf0, %asi
38271sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
38272add %i0, %i3, %i3
38273ldda [%i3 + 0] %asi, %f32
38274membar #Sync
38275! 3 addresses covered
38276fmovd %f32, %f2
38277fmovd %f34, %f18
38278fmovs %f19, %f4
38279
38280P3369: !_MEMBAR (FP)
38281
38282P3370: !_BLD [8] (FP)
38283wr %g0, 0xf0, %asi
38284sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
38285sub %i0, %i2, %i2
38286ldda [%i2 + 0] %asi, %f32
38287membar #Sync
38288! 3 addresses covered
38289fmovd %f32, %f18
38290fmovs %f18, %f5
38291fmovs %f19, %f6
38292fmovd %f34, %f18
38293fmovs %f19, %f7
38294
38295P3371: !_MEMBAR (FP)
38296
38297P3372: !_ST_BINIT [14] (maybe <- 0x18000a2) (Int)
38298wr %g0, 0xe2, %asi
38299sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
38300sub %i0, %i3, %i3
38301stwa %l4, [%i3 + 12] %asi
38302add %l4, 1, %l4
38303
38304P3373: !_MEMBAR (Int)
38305
38306P3374: !_BSTC [16] (maybe <- 0x41000053) (FP)
38307wr %g0, 0xe0, %asi
38308sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
38309sub %i0, %i2, %i2
38310! preparing store val #0, next val will be in f32
38311fmovs %f16, %f20
38312fadds %f16, %f17, %f16
38313! preparing store val #1, next val will be in f33
38314fmovs %f16, %f21
38315fadds %f16, %f17, %f16
38316! preparing store val #2, next val will be in f35
38317fmovd %f20, %f32
38318fmovs %f16, %f21
38319fadds %f16, %f17, %f16
38320fmovd %f20, %f34
38321membar #Sync
38322stda %f32, [%i2 + 0 ] %asi
38323
38324P3375: !_MEMBAR (FP)
38325
38326P3376: !_BSTC [21] (maybe <- 0x41000056) (FP)
38327wr %g0, 0xe0, %asi
38328sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
38329add %i0, %i3, %i3
38330! preparing store val #0, next val will be in f32
38331fmovs %f16, %f20
38332fadds %f16, %f17, %f16
38333! preparing store val #1, next val will be in f33
38334fmovs %f16, %f21
38335fadds %f16, %f17, %f16
38336! preparing store val #2, next val will be in f35
38337fmovd %f20, %f32
38338fmovs %f16, %f21
38339fadds %f16, %f17, %f16
38340fmovd %f20, %f34
38341membar #Sync
38342stda %f32, [%i3 + 0 ] %asi
38343
38344P3377: !_MEMBAR (FP)
38345membar #StoreLoad
38346
38347P3378: !_CASX [4] (maybe <- 0x18000a3) (Int)
38348ldx [%i1], %o5
38349! move %o5(upper) -> %o1(lower)
38350srlx %o5, 32, %l3
38351or %l3, %o1, %o1
38352! move %o5(lower) -> %o2(upper)
38353sllx %o5, 32, %o2
38354mov %o5, %l3
38355sllx %l4, 32, %o5
38356add %l4, 1, %l4
38357or %l4, %o5, %o5
38358casx [%i1], %l3, %o5
38359! move %o5(upper) -> %o2(lower)
38360srlx %o5, 32, %l3
38361or %l3, %o2, %o2
38362! move %o5(lower) -> %o3(upper)
38363sllx %o5, 32, %o3
38364add %l4, 1, %l4
38365
38366P3379: !_DWST [21] (maybe <- 0x18000a5) (Int) (Branch target of P3475)
38367sllx %l4, 32, %l3
38368add %l4, 1, %l4
38369or %l3, %l4, %l3
38370stx %l3, [%i3 + 0]
38371add %l4, 1, %l4
38372ba P3380
38373nop
38374
38375TARGET3475:
38376ba RET3475
38377nop
38378
38379
38380P3380: !_CAS [2] (maybe <- 0x18000a7) (Int)
38381add %i0, 12, %l3
38382lduw [%l3], %l7
38383mov %l7, %o5
38384! move %o5(lower) -> %o3(lower)
38385or %o5, %o3, %o3
38386mov %l4, %o4
38387cas [%l3], %o5, %o4
38388! move %o4(lower) -> %o4(upper)
38389sllx %o4, 32, %o4
38390add %l4, 1, %l4
38391
38392P3381: !_SWAP [3] (maybe <- 0x18000a8) (Int)
38393mov %l4, %l6
38394swap [%i1 + 0], %l6
38395! move %l6(lower) -> %o4(lower)
38396srl %l6, 0, %o5
38397or %o5, %o4, %o4
38398!---- flushing int results buffer----
38399mov %o0, %l5
38400mov %o1, %l5
38401mov %o2, %l5
38402mov %o3, %l5
38403mov %o4, %l5
38404add %l4, 1, %l4
38405
38406P3382: !_DWLD [22] (Int)
38407ldx [%i3 + 0], %o0
38408! move %o0(upper) -> %o0(upper)
38409! move %o0(lower) -> %o0(lower)
38410
38411P3383: !_MEMBAR (FP)
38412
38413P3384: !_BST [20] (maybe <- 0x41000059) (FP)
38414wr %g0, 0xf0, %asi
38415sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
38416sub %i0, %i2, %i2
38417! preparing store val #0, next val will be in f32
38418fmovs %f16, %f20
38419fadds %f16, %f17, %f16
38420! preparing store val #1, next val will be in f33
38421fmovs %f16, %f21
38422fadds %f16, %f17, %f16
38423! preparing store val #2, next val will be in f35
38424fmovd %f20, %f32
38425fmovs %f16, %f21
38426fadds %f16, %f17, %f16
38427fmovd %f20, %f34
38428membar #Sync
38429stda %f32, [%i2 + 0 ] %asi
38430
38431P3385: !_MEMBAR (FP) (CBR)
38432membar #StoreLoad
38433
38434! cbranch
38435andcc %l0, 1, %g0
38436be,pn %xcc, TARGET3385
38437nop
38438RET3385:
38439
38440! lfsr step begin
38441srlx %l0, 1, %o5
38442xnor %o5, %l0, %o5
38443sllx %o5, 63, %o5
38444or %o5, %l0, %l0
38445srlx %l0, 1, %l0
38446
38447
38448P3386: !_CAS [3] (maybe <- 0x18000a9) (Int)
38449lduw [%i1], %o1
38450mov %o1, %l3
38451! move %l3(lower) -> %o1(upper)
38452sllx %l3, 32, %o1
38453mov %l4, %o5
38454cas [%i1], %l3, %o5
38455! move %o5(lower) -> %o1(lower)
38456srl %o5, 0, %l3
38457or %l3, %o1, %o1
38458add %l4, 1, %l4
38459
38460P3387: !_CAS [8] (maybe <- 0x18000aa) (Int)
38461sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
38462sub %i0, %i3, %i3
38463add %i3, 12, %l6
38464lduw [%l6], %o2
38465mov %o2, %l3
38466! move %l3(lower) -> %o2(upper)
38467sllx %l3, 32, %o2
38468mov %l4, %o5
38469cas [%l6], %l3, %o5
38470! move %o5(lower) -> %o2(lower)
38471srl %o5, 0, %l3
38472or %l3, %o2, %o2
38473add %l4, 1, %l4
38474
38475P3388: !_ST [8] (maybe <- 0x4100005c) (FP)
38476! preparing store val #0, next val will be in f20
38477fmovs %f16, %f20
38478fadds %f16, %f17, %f16
38479st %f20, [%i3 + 12 ]
38480
38481P3389: !_LD [5] (Int)
38482!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
38483!Logical addr: 5
38484
38485sethi %hi(0x200000), %o5
38486sub %i1, %o5, %i1
38487lduw [%i1 + 12], %o3
38488! move %o3(lower) -> %o3(upper)
38489sllx %o3, 32, %o3
38490
38491P3390: !_ST_BINIT [12] (maybe <- 0x18000ab) (Int)
38492wr %g0, 0xe2, %asi
38493sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
38494sub %i0, %i2, %i2
38495stwa %l4, [%i2 + 0] %asi
38496add %l4, 1, %l4
38497
38498P3391: !_MEMBAR (Int)
38499membar #StoreLoad
38500
38501P3392: !_ST_BINIT [17] (maybe <- 0x18000ac) (Int)
38502wr %g0, 0xe2, %asi
38503sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
38504sub %i0, %i3, %i3
38505stwa %l4, [%i3 + 12] %asi
38506add %l4, 1, %l4
38507
38508P3393: !_MEMBAR (Int)
38509membar #StoreLoad
38510
38511P3394: !_PREFETCH [9] (Int)
38512sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
38513add %i0, %i2, %i2
38514prefetch [%i2 + 0], 19
38515
38516P3395: !_PREFETCH [8] (Int)
38517sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
38518sub %i0, %i3, %i3
38519prefetch [%i3 + 12], 20
38520
38521P3396: !_MEMBAR (FP)
38522
38523P3397: !_BST [23] (maybe <- 0x4100005d) (FP)
38524wr %g0, 0xf0, %asi
38525sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
38526add %i0, %i2, %i2
38527! preparing store val #0, next val will be in f32
38528fmovs %f16, %f20
38529fadds %f16, %f17, %f16
38530! preparing store val #1, next val will be in f33
38531fmovs %f16, %f21
38532fadds %f16, %f17, %f16
38533! preparing store val #2, next val will be in f35
38534fmovd %f20, %f32
38535fmovs %f16, %f21
38536fadds %f16, %f17, %f16
38537fmovd %f20, %f34
38538membar #Sync
38539stda %f32, [%i2 + 0 ] %asi
38540
38541P3398: !_MEMBAR (FP)
38542membar #StoreLoad
38543
38544P3399: !_PREFETCH [19] (Int) (CBR)
38545sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
38546sub %i0, %i3, %i3
38547prefetch [%i3 + 4], 1
38548
38549! cbranch
38550andcc %l0, 1, %g0
38551be,pt %xcc, TARGET3399
38552nop
38553RET3399:
38554
38555! lfsr step begin
38556srlx %l0, 1, %o5
38557xnor %o5, %l0, %o5
38558sllx %o5, 63, %o5
38559or %o5, %l0, %l0
38560srlx %l0, 1, %l0
38561
38562
38563P3400: !_DWST_BINIT [2] (maybe <- 0x18000ad) (Int)
38564wr %g0, 0xe2, %asi
38565mov %l4, %l3
38566stxa %l3, [%i0 + 8] %asi
38567add %l4, 1, %l4
38568
38569P3401: !_MEMBAR (Int)
38570membar #StoreLoad
38571
38572P3402: !_CASX [7] (maybe <- 0x18000ae) (Int)
38573sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
38574sub %i0, %i2, %i2
38575ldx [%i2], %l7
38576! move %l7(upper) -> %o3(lower)
38577srlx %l7, 32, %o5
38578or %o5, %o3, %o3
38579! move %l7(lower) -> %o4(upper)
38580sllx %l7, 32, %o4
38581mov %l7, %o5
38582sllx %l4, 32, %l7
38583add %l4, 1, %l4
38584or %l4, %l7, %l7
38585casx [%i2], %o5, %l7
38586! move %l7(upper) -> %o4(lower)
38587srlx %l7, 32, %o5
38588or %o5, %o4, %o4
38589!---- flushing int results buffer----
38590mov %o0, %l5
38591mov %o1, %l5
38592mov %o2, %l5
38593mov %o3, %l5
38594mov %o4, %l5
38595! move %l7(lower) -> %o0(upper)
38596sllx %l7, 32, %o0
38597add %l4, 1, %l4
38598
38599P3403: !_LDD [3] (Int)
38600ldd [%i1 + 0], %l6
38601! move %l6(lower) -> %o0(lower)
38602or %l6, %o0, %o0
38603! move %l7(lower) -> %o1(upper)
38604sllx %l7, 32, %o1
38605
38606P3404: !_CASX [13] (maybe <- 0x18000b0) (Int)
38607sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
38608sub %i0, %i3, %i3
38609ldx [%i3], %o5
38610! move %o5(upper) -> %o1(lower)
38611srlx %o5, 32, %l3
38612or %l3, %o1, %o1
38613! move %o5(lower) -> %o2(upper)
38614sllx %o5, 32, %o2
38615mov %o5, %l3
38616sllx %l4, 32, %o5
38617add %l4, 1, %l4
38618or %l4, %o5, %o5
38619casx [%i3], %l3, %o5
38620! move %o5(upper) -> %o2(lower)
38621srlx %o5, 32, %l3
38622or %l3, %o2, %o2
38623! move %o5(lower) -> %o3(upper)
38624sllx %o5, 32, %o3
38625add %l4, 1, %l4
38626
38627P3405: !_DWST [7] (maybe <- 0x18000b2) (Int)
38628sllx %l4, 32, %l3
38629add %l4, 1, %l4
38630or %l3, %l4, %l3
38631stx %l3, [%i2 + 0]
38632add %l4, 1, %l4
38633
38634P3406: !_LD [13] (FP)
38635ld [%i3 + 4], %f8
38636! 1 addresses covered
38637
38638P3407: !_DWLD [13] (Int)
38639ldx [%i3 + 0], %l3
38640! move %l3(upper) -> %o3(lower)
38641srlx %l3, 32, %o5
38642or %o5, %o3, %o3
38643! move %l3(lower) -> %o4(upper)
38644sllx %l3, 32, %o4
38645
38646P3408: !_MEMBAR (FP)
38647
38648P3409: !_BSTC [0] (maybe <- 0x41000060) (FP)
38649wr %g0, 0xe0, %asi
38650! preparing store val #0, next val will be in f32
38651fmovs %f16, %f20
38652fadds %f16, %f17, %f16
38653! preparing store val #1, next val will be in f33
38654fmovs %f16, %f21
38655fadds %f16, %f17, %f16
38656! preparing store val #2, next val will be in f35
38657fmovd %f20, %f32
38658fmovs %f16, %f21
38659fadds %f16, %f17, %f16
38660fmovd %f20, %f34
38661membar #Sync
38662stda %f32, [%i0 + 0 ] %asi
38663
38664P3410: !_MEMBAR (FP)
38665membar #StoreLoad
38666
38667P3411: !_DWST [14] (maybe <- 0x18000b4) (Int)
38668mov %l4, %l3
38669stx %l3, [%i3 + 8]
38670add %l4, 1, %l4
38671
38672P3412: !_ST_BINIT [13] (maybe <- 0x18000b5) (Int)
38673wr %g0, 0xe2, %asi
38674stwa %l4, [%i3 + 4] %asi
38675add %l4, 1, %l4
38676
38677P3413: !_MEMBAR (Int)
38678membar #StoreLoad
38679
38680P3414: !_LDD [17] (Int)
38681sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
38682sub %i0, %i2, %i2
38683ldd [%i2 + 8], %l6
38684! move %l7(lower) -> %o4(lower)
38685or %l7, %o4, %o4
38686!---- flushing int results buffer----
38687mov %o0, %l5
38688mov %o1, %l5
38689mov %o2, %l5
38690mov %o3, %l5
38691mov %o4, %l5
38692
38693P3415: !_MEMBAR (FP)
38694membar #StoreLoad
38695
38696P3416: !_BLD [15] (FP)
38697wr %g0, 0xf0, %asi
38698ldda [%i2 + 0] %asi, %f32
38699membar #Sync
38700! 3 addresses covered
38701fmovd %f32, %f18
38702fmovs %f18, %f9
38703fmovs %f19, %f10
38704fmovd %f34, %f18
38705fmovs %f19, %f11
38706
38707P3417: !_MEMBAR (FP)
38708
38709P3418: !_LDD [15] (Int)
38710ldd [%i2 + 0], %l6
38711! move %l6(lower) -> %o0(upper)
38712sllx %l6, 32, %o0
38713! move %l7(lower) -> %o0(lower)
38714or %l7, %o0, %o0
38715
38716P3419: !_LDD [4] (Int)
38717ldd [%i1 + 0], %l6
38718! move %l6(lower) -> %o1(upper)
38719sllx %l6, 32, %o1
38720! move %l7(lower) -> %o1(lower)
38721or %l7, %o1, %o1
38722
38723P3420: !_CAS [9] (maybe <- 0x18000b6) (Int)
38724sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
38725add %i0, %i3, %i3
38726lduw [%i3], %o2
38727mov %o2, %l3
38728! move %l3(lower) -> %o2(upper)
38729sllx %l3, 32, %o2
38730mov %l4, %o5
38731cas [%i3], %l3, %o5
38732! move %o5(lower) -> %o2(lower)
38733srl %o5, 0, %l3
38734or %l3, %o2, %o2
38735add %l4, 1, %l4
38736
38737P3421: !_DWST_BINIT [19] (maybe <- 0x18000b7) (Int)
38738wr %g0, 0xe2, %asi
38739sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
38740sub %i0, %i2, %i2
38741sllx %l4, 32, %l3
38742add %l4, 1, %l4
38743or %l3, %l4, %l3
38744stxa %l3, [%i2 + 0] %asi
38745add %l4, 1, %l4
38746
38747P3422: !_MEMBAR (Int)
38748membar #StoreLoad
38749
38750P3423: !_CAS [16] (maybe <- 0x18000b9) (Int)
38751sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
38752sub %i0, %i3, %i3
38753add %i3, 4, %l3
38754lduw [%l3], %o3
38755mov %o3, %o5
38756! move %o5(lower) -> %o3(upper)
38757sllx %o5, 32, %o3
38758mov %l4, %l7
38759cas [%l3], %o5, %l7
38760! move %l7(lower) -> %o3(lower)
38761srl %l7, 0, %o5
38762or %o5, %o3, %o3
38763add %l4, 1, %l4
38764
38765P3424: !_SWAP [9] (maybe <- 0x18000ba) (Int)
38766sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
38767add %i0, %i2, %i2
38768mov %l4, %o4
38769swap [%i2 + 0], %o4
38770! move %o4(lower) -> %o4(upper)
38771sllx %o4, 32, %o4
38772add %l4, 1, %l4
38773
38774P3425: !_CAS [21] (maybe <- 0x18000bb) (Int)
38775sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
38776add %i0, %i3, %i3
38777lduw [%i3], %l6
38778mov %l6, %l7
38779! move %l7(lower) -> %o4(lower)
38780or %l7, %o4, %o4
38781!---- flushing int results buffer----
38782mov %o0, %l5
38783mov %o1, %l5
38784mov %o2, %l5
38785mov %o3, %l5
38786mov %o4, %l5
38787mov %l4, %o0
38788cas [%i3], %l7, %o0
38789! move %o0(lower) -> %o0(upper)
38790sllx %o0, 32, %o0
38791add %l4, 1, %l4
38792
38793P3426: !_DWST_BINIT [18] (maybe <- 0x18000bc) (Int)
38794wr %g0, 0xe2, %asi
38795sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
38796sub %i0, %i2, %i2
38797sllx %l4, 32, %l7
38798add %l4, 1, %l4
38799or %l7, %l4, %l7
38800stxa %l7, [%i2 + 0] %asi
38801add %l4, 1, %l4
38802
38803P3427: !_MEMBAR (Int)
38804membar #StoreLoad
38805
38806P3428: !_BLD [17] (FP)
38807wr %g0, 0xf0, %asi
38808sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
38809sub %i0, %i3, %i3
38810ldda [%i3 + 0] %asi, %f32
38811membar #Sync
38812! 3 addresses covered
38813fmovd %f32, %f12
38814fmovd %f34, %f18
38815fmovs %f19, %f14
38816
38817P3429: !_MEMBAR (FP)
38818
38819P3430: !_REPLACEMENT [19] (Int)
38820sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
38821sub %i0, %i2, %i2
38822sethi %hi(0x20000), %l6
38823ld [%i2+4], %o5
38824st %o5, [%i2+4]
38825add %i2, %l6, %l7
38826ld [%l7+4], %o5
38827st %o5, [%l7+4]
38828add %l7, %l6, %l7
38829ld [%l7+4], %o5
38830st %o5, [%l7+4]
38831add %l7, %l6, %l7
38832ld [%l7+4], %o5
38833st %o5, [%l7+4]
38834add %l7, %l6, %l7
38835ld [%l7+4], %o5
38836st %o5, [%l7+4]
38837add %l7, %l6, %l7
38838ld [%l7+4], %o5
38839st %o5, [%l7+4]
38840add %l7, %l6, %l7
38841ld [%l7+4], %o5
38842st %o5, [%l7+4]
38843add %l7, %l6, %l7
38844ld [%l7+4], %o5
38845st %o5, [%l7+4]
38846
38847P3431: !_ST [5] (maybe <- 0x18000be) (Int)
38848stw %l4, [%i1 + 12 ]
38849add %l4, 1, %l4
38850
38851P3432: !_ST_BINIT [10] (maybe <- 0x18000bf) (Int)
38852wr %g0, 0xe2, %asi
38853sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
38854add %i0, %i3, %i3
38855stwa %l4, [%i3 + 4] %asi
38856add %l4, 1, %l4
38857
38858P3433: !_MEMBAR (Int) (Branch target of P3626)
38859membar #StoreLoad
38860ba P3434
38861nop
38862
38863TARGET3626:
38864ba RET3626
38865nop
38866
38867
38868P3434: !_CAS [12] (maybe <- 0x18000c0) (Int)
38869sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
38870sub %i0, %i2, %i2
38871lduw [%i2], %l6
38872mov %l6, %l7
38873! move %l7(lower) -> %o0(lower)
38874or %l7, %o0, %o0
38875mov %l4, %o1
38876cas [%i2], %l7, %o1
38877! move %o1(lower) -> %o1(upper)
38878sllx %o1, 32, %o1
38879add %l4, 1, %l4
38880
38881P3435: !_MEMBAR (FP)
38882membar #StoreLoad
38883
38884P3436: !_BLD [11] (FP)
38885wr %g0, 0xf0, %asi
38886ldda [%i3 + 0] %asi, %f32
38887membar #Sync
38888! 3 addresses covered
38889fmovd %f32, %f18
38890fmovs %f18, %f15
38891!---- flushing fp results buffer to %f30 ----
38892fmovd %f0, %f30
38893fmovd %f2, %f30
38894fmovd %f4, %f30
38895fmovd %f6, %f30
38896fmovd %f8, %f30
38897fmovd %f10, %f30
38898fmovd %f12, %f30
38899fmovd %f14, %f30
38900!--
38901fmovs %f19, %f0
38902fmovd %f34, %f18
38903fmovs %f19, %f1
38904
38905P3437: !_MEMBAR (FP)
38906
38907P3438: !_BLD [13] (FP)
38908wr %g0, 0xf0, %asi
38909ldda [%i2 + 0] %asi, %f32
38910membar #Sync
38911! 3 addresses covered
38912fmovd %f32, %f2
38913fmovd %f34, %f18
38914fmovs %f19, %f4
38915
38916P3439: !_MEMBAR (FP)
38917
38918P3440: !_PREFETCH [20] (Int)
38919sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
38920sub %i0, %i3, %i3
38921prefetch [%i3 + 12], 18
38922
38923P3441: !_REPLACEMENT [23] (Int)
38924sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
38925sub %i0, %i2, %i2
38926sethi %hi(0x20000), %l7
38927ld [%i2+12], %l3
38928st %l3, [%i2+12]
38929add %i2, %l7, %o5
38930ld [%o5+12], %l3
38931st %l3, [%o5+12]
38932add %o5, %l7, %o5
38933ld [%o5+12], %l3
38934st %l3, [%o5+12]
38935add %o5, %l7, %o5
38936ld [%o5+12], %l3
38937st %l3, [%o5+12]
38938add %o5, %l7, %o5
38939ld [%o5+12], %l3
38940st %l3, [%o5+12]
38941add %o5, %l7, %o5
38942ld [%o5+12], %l3
38943st %l3, [%o5+12]
38944add %o5, %l7, %o5
38945ld [%o5+12], %l3
38946st %l3, [%o5+12]
38947add %o5, %l7, %o5
38948ld [%o5+12], %l3
38949st %l3, [%o5+12]
38950
38951P3442: !_DWST [15] (maybe <- 0x18000c1) (Int)
38952sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
38953sub %i0, %i3, %i3
38954sllx %l4, 32, %l6
38955add %l4, 1, %l4
38956or %l6, %l4, %l6
38957stx %l6, [%i3 + 0]
38958add %l4, 1, %l4
38959
38960P3443: !_LD [19] (Int)
38961sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
38962sub %i0, %i2, %i2
38963lduw [%i2 + 4], %l6
38964! move %l6(lower) -> %o1(lower)
38965or %l6, %o1, %o1
38966
38967P3444: !_LDD [14] (Int)
38968sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
38969sub %i0, %i3, %i3
38970ldd [%i3 + 8], %l6
38971! move %l7(lower) -> %o2(upper)
38972sllx %l7, 32, %o2
38973
38974P3445: !_MEMBAR (FP)
38975
38976P3446: !_BSTC [9] (maybe <- 0x41000063) (FP)
38977wr %g0, 0xe0, %asi
38978sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
38979add %i0, %i2, %i2
38980! preparing store val #0, next val will be in f32
38981fmovs %f16, %f20
38982fadds %f16, %f17, %f16
38983! preparing store val #1, next val will be in f33
38984fmovs %f16, %f21
38985fadds %f16, %f17, %f16
38986! preparing store val #2, next val will be in f35
38987fmovd %f20, %f32
38988fmovs %f16, %f21
38989fadds %f16, %f17, %f16
38990fmovd %f20, %f34
38991membar #Sync
38992stda %f32, [%i2 + 0 ] %asi
38993
38994P3447: !_MEMBAR (FP)
38995membar #StoreLoad
38996
38997P3448: !_BLD [21] (FP)
38998wr %g0, 0xf0, %asi
38999sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
39000add %i0, %i3, %i3
39001ldda [%i3 + 0] %asi, %f32
39002membar #Sync
39003! 3 addresses covered
39004fmovd %f32, %f18
39005fmovs %f18, %f5
39006fmovs %f19, %f6
39007fmovd %f34, %f18
39008fmovs %f19, %f7
39009
39010P3449: !_MEMBAR (FP)
39011
39012P3450: !_BST [16] (maybe <- 0x41000066) (FP)
39013wr %g0, 0xf0, %asi
39014sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
39015sub %i0, %i2, %i2
39016! preparing store val #0, next val will be in f32
39017fmovs %f16, %f20
39018fadds %f16, %f17, %f16
39019! preparing store val #1, next val will be in f33
39020fmovs %f16, %f21
39021fadds %f16, %f17, %f16
39022! preparing store val #2, next val will be in f35
39023fmovd %f20, %f32
39024fmovs %f16, %f21
39025fadds %f16, %f17, %f16
39026fmovd %f20, %f34
39027membar #Sync
39028stda %f32, [%i2 + 0 ] %asi
39029
39030P3451: !_MEMBAR (FP)
39031membar #StoreLoad
39032
39033P3452: !_ST [7] (maybe <- 0x18000c3) (Int) (Branch target of P3281)
39034sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
39035sub %i0, %i3, %i3
39036stw %l4, [%i3 + 4 ]
39037add %l4, 1, %l4
39038ba P3453
39039nop
39040
39041TARGET3281:
39042ba RET3281
39043nop
39044
39045
39046P3453: !_CASX [8] (maybe <- 0x18000c4) (Int)
39047sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
39048sub %i0, %i2, %i2
39049add %i2, 8, %o5
39050ldx [%o5], %l6
39051! move %l6(upper) -> %o2(lower)
39052srlx %l6, 32, %l7
39053or %l7, %o2, %o2
39054! move %l6(lower) -> %o3(upper)
39055sllx %l6, 32, %o3
39056mov %l6, %l7
39057mov %l4, %l6
39058casx [%o5], %l7, %l6
39059! move %l6(upper) -> %o3(lower)
39060srlx %l6, 32, %l7
39061or %l7, %o3, %o3
39062! move %l6(lower) -> %o4(upper)
39063sllx %l6, 32, %o4
39064add %l4, 1, %l4
39065
39066P3454: !_ST_BINIT [15] (maybe <- 0x18000c5) (Int)
39067wr %g0, 0xe2, %asi
39068sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
39069sub %i0, %i3, %i3
39070stwa %l4, [%i3 + 0] %asi
39071add %l4, 1, %l4
39072
39073P3455: !_MEMBAR (Int)
39074
39075P3456: !_BSTC [2] (maybe <- 0x41000069) (FP) (CBR)
39076wr %g0, 0xe0, %asi
39077! preparing store val #0, next val will be in f32
39078fmovs %f16, %f20
39079fadds %f16, %f17, %f16
39080! preparing store val #1, next val will be in f33
39081fmovs %f16, %f21
39082fadds %f16, %f17, %f16
39083! preparing store val #2, next val will be in f35
39084fmovd %f20, %f32
39085fmovs %f16, %f21
39086fadds %f16, %f17, %f16
39087fmovd %f20, %f34
39088membar #Sync
39089stda %f32, [%i0 + 0 ] %asi
39090
39091! cbranch
39092andcc %l0, 1, %g0
39093be,pt %xcc, TARGET3456
39094nop
39095RET3456:
39096
39097! lfsr step begin
39098srlx %l0, 1, %l3
39099xnor %l3, %l0, %l3
39100sllx %l3, 63, %l3
39101or %l3, %l0, %l0
39102srlx %l0, 1, %l0
39103
39104
39105P3457: !_MEMBAR (FP)
39106membar #StoreLoad
39107
39108P3458: !_BLD [1] (FP)
39109wr %g0, 0xf0, %asi
39110ldda [%i0 + 0] %asi, %f32
39111membar #Sync
39112! 3 addresses covered
39113fmovd %f32, %f8
39114fmovd %f34, %f18
39115fmovs %f19, %f10
39116
39117P3459: !_MEMBAR (FP)
39118
39119P3460: !_LD [17] (Int)
39120lduw [%i3 + 12], %l7
39121! move %l7(lower) -> %o4(lower)
39122or %l7, %o4, %o4
39123!---- flushing int results buffer----
39124mov %o0, %l5
39125mov %o1, %l5
39126mov %o2, %l5
39127mov %o3, %l5
39128mov %o4, %l5
39129
39130P3461: !_DWLD [19] (Int)
39131sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
39132sub %i0, %i2, %i2
39133ldx [%i2 + 0], %o0
39134! move %o0(upper) -> %o0(upper)
39135! move %o0(lower) -> %o0(lower)
39136
39137P3462: !_DWST_BINIT [17] (maybe <- 0x18000c6) (Int)
39138wr %g0, 0xe2, %asi
39139mov %l4, %l6
39140stxa %l6, [%i3 + 8] %asi
39141add %l4, 1, %l4
39142
39143P3463: !_MEMBAR (Int)
39144membar #StoreLoad
39145
39146P3464: !_DWST [15] (maybe <- 0x18000c7) (Int)
39147sllx %l4, 32, %l3
39148add %l4, 1, %l4
39149or %l3, %l4, %l3
39150stx %l3, [%i3 + 0]
39151add %l4, 1, %l4
39152
39153P3465: !_REPLACEMENT [18] (Int)
39154sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
39155sub %i0, %i3, %i3
39156sethi %hi(0x20000), %o5
39157ld [%i3+0], %l6
39158st %l6, [%i3+0]
39159add %i3, %o5, %l3
39160ld [%l3+0], %l6
39161st %l6, [%l3+0]
39162add %l3, %o5, %l3
39163ld [%l3+0], %l6
39164st %l6, [%l3+0]
39165add %l3, %o5, %l3
39166ld [%l3+0], %l6
39167st %l6, [%l3+0]
39168add %l3, %o5, %l3
39169ld [%l3+0], %l6
39170st %l6, [%l3+0]
39171add %l3, %o5, %l3
39172ld [%l3+0], %l6
39173st %l6, [%l3+0]
39174add %l3, %o5, %l3
39175ld [%l3+0], %l6
39176st %l6, [%l3+0]
39177add %l3, %o5, %l3
39178ld [%l3+0], %l6
39179st %l6, [%l3+0]
39180
39181P3466: !_ST [2] (maybe <- 0x18000c9) (Int) (LE)
39182wr %g0, 0x88, %asi
39183! Change single-word-level endianess (big endian <-> little endian)
39184sethi %hi(0xff00ff00), %o5
39185or %o5, %lo(0xff00ff00), %o5
39186and %l4, %o5, %l3
39187srl %l3, 8, %l3
39188sll %l4, 8, %l7
39189and %l7, %o5, %l7
39190or %l7, %l3, %l7
39191srl %l7, 16, %l3
39192sll %l7, 16, %l7
39193srl %l7, 0, %l7
39194or %l7, %l3, %l7
39195stwa %l7, [%i0 + 12] %asi
39196add %l4, 1, %l4
39197
39198P3467: !_DWLD [0] (Int) (CBR)
39199ldx [%i0 + 0], %o1
39200! move %o1(upper) -> %o1(upper)
39201! move %o1(lower) -> %o1(lower)
39202
39203! cbranch
39204andcc %l0, 1, %g0
39205be,pn %xcc, TARGET3467
39206nop
39207RET3467:
39208
39209! lfsr step begin
39210srlx %l0, 1, %o5
39211xnor %o5, %l0, %o5
39212sllx %o5, 63, %o5
39213or %o5, %l0, %l0
39214srlx %l0, 1, %l0
39215
39216
39217P3468: !_CAS [2] (maybe <- 0x18000ca) (Int)
39218add %i0, 12, %l6
39219lduw [%l6], %o2
39220mov %o2, %l3
39221! move %l3(lower) -> %o2(upper)
39222sllx %l3, 32, %o2
39223mov %l4, %o5
39224cas [%l6], %l3, %o5
39225! move %o5(lower) -> %o2(lower)
39226srl %o5, 0, %l3
39227or %l3, %o2, %o2
39228add %l4, 1, %l4
39229
39230P3469: !_ST [15] (maybe <- 0x18000cb) (Int)
39231sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
39232sub %i0, %i2, %i2
39233stw %l4, [%i2 + 0 ]
39234add %l4, 1, %l4
39235
39236P3470: !_ST [14] (maybe <- 0x18000cc) (Int)
39237sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
39238sub %i0, %i3, %i3
39239stw %l4, [%i3 + 12 ]
39240add %l4, 1, %l4
39241
39242P3471: !_MEMBAR (FP)
39243membar #StoreLoad
39244
39245P3472: !_BLD [12] (FP)
39246wr %g0, 0xf0, %asi
39247ldda [%i3 + 0] %asi, %f32
39248membar #Sync
39249! 3 addresses covered
39250fmovd %f32, %f18
39251fmovs %f18, %f11
39252fmovs %f19, %f12
39253fmovd %f34, %f18
39254fmovs %f19, %f13
39255
39256P3473: !_MEMBAR (FP)
39257
39258P3474: !_PREFETCH [8] (Int)
39259sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
39260sub %i0, %i2, %i2
39261prefetch [%i2 + 12], 2
39262
39263P3475: !_LD [11] (Int) (CBR)
39264sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
39265add %i0, %i3, %i3
39266lduw [%i3 + 12], %o3
39267! move %o3(lower) -> %o3(upper)
39268sllx %o3, 32, %o3
39269
39270! cbranch
39271andcc %l0, 1, %g0
39272be,pt %xcc, TARGET3475
39273nop
39274RET3475:
39275
39276! lfsr step begin
39277srlx %l0, 1, %l3
39278xnor %l3, %l0, %l3
39279sllx %l3, 63, %l3
39280or %l3, %l0, %l0
39281srlx %l0, 1, %l0
39282
39283
39284P3476: !_SWAP [13] (maybe <- 0x18000cd) (Int)
39285sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
39286sub %i0, %i2, %i2
39287mov %l4, %o5
39288swap [%i2 + 4], %o5
39289! move %o5(lower) -> %o3(lower)
39290srl %o5, 0, %l6
39291or %l6, %o3, %o3
39292add %l4, 1, %l4
39293
39294P3477: !_LD [7] (Int)
39295sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
39296sub %i0, %i3, %i3
39297lduw [%i3 + 4], %o4
39298! move %o4(lower) -> %o4(upper)
39299sllx %o4, 32, %o4
39300
39301P3478: !_DWST [14] (maybe <- 0x18000ce) (Int)
39302mov %l4, %l7
39303stx %l7, [%i2 + 8]
39304add %l4, 1, %l4
39305
39306P3479: !_MEMBAR (FP)
39307
39308P3480: !_BST [11] (maybe <- 0x4100006c) (FP)
39309wr %g0, 0xf0, %asi
39310sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
39311add %i0, %i2, %i2
39312! preparing store val #0, next val will be in f32
39313fmovs %f16, %f20
39314fadds %f16, %f17, %f16
39315! preparing store val #1, next val will be in f33
39316fmovs %f16, %f21
39317fadds %f16, %f17, %f16
39318! preparing store val #2, next val will be in f35
39319fmovd %f20, %f32
39320fmovs %f16, %f21
39321fadds %f16, %f17, %f16
39322fmovd %f20, %f34
39323membar #Sync
39324stda %f32, [%i2 + 0 ] %asi
39325
39326P3481: !_MEMBAR (FP)
39327membar #StoreLoad
39328
39329P3482: !_ST [23] (maybe <- 0x18000cf) (Int)
39330sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
39331add %i0, %i3, %i3
39332stw %l4, [%i3 + 12 ]
39333add %l4, 1, %l4
39334
39335P3483: !_DWST_BINIT [10] (maybe <- 0x18000d0) (Int)
39336wr %g0, 0xe2, %asi
39337sllx %l4, 32, %o5
39338add %l4, 1, %l4
39339or %o5, %l4, %o5
39340stxa %o5, [%i2 + 0] %asi
39341add %l4, 1, %l4
39342
39343P3484: !_MEMBAR (Int)
39344membar #StoreLoad
39345
39346P3485: !_BLD [14] (FP)
39347wr %g0, 0xf0, %asi
39348sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
39349sub %i0, %i2, %i2
39350ldda [%i2 + 0] %asi, %f32
39351membar #Sync
39352! 3 addresses covered
39353fmovd %f32, %f14
39354!---- flushing fp results buffer to %f30 ----
39355fmovd %f0, %f30
39356fmovd %f2, %f30
39357fmovd %f4, %f30
39358fmovd %f6, %f30
39359fmovd %f8, %f30
39360fmovd %f10, %f30
39361fmovd %f12, %f30
39362fmovd %f14, %f30
39363!--
39364fmovd %f34, %f18
39365fmovs %f19, %f0
39366
39367P3486: !_MEMBAR (FP)
39368
39369P3487: !_CASX [12] (maybe <- 0x18000d2) (Int)
39370ldx [%i2], %l6
39371! move %l6(upper) -> %o4(lower)
39372srlx %l6, 32, %l7
39373or %l7, %o4, %o4
39374!---- flushing int results buffer----
39375mov %o0, %l5
39376mov %o1, %l5
39377mov %o2, %l5
39378mov %o3, %l5
39379mov %o4, %l5
39380! move %l6(lower) -> %o0(upper)
39381sllx %l6, 32, %o0
39382mov %l6, %l7
39383sllx %l4, 32, %l6
39384add %l4, 1, %l4
39385or %l4, %l6, %l6
39386casx [%i2], %l7, %l6
39387! move %l6(upper) -> %o0(lower)
39388srlx %l6, 32, %l7
39389or %l7, %o0, %o0
39390! move %l6(lower) -> %o1(upper)
39391sllx %l6, 32, %o1
39392add %l4, 1, %l4
39393
39394P3488: !_LDD [11] (Int)
39395sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
39396add %i0, %i3, %i3
39397ldd [%i3 + 8], %l6
39398! move %l7(lower) -> %o1(lower)
39399or %l7, %o1, %o1
39400
39401P3489: !_LD [19] (Int)
39402sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
39403sub %i0, %i2, %i2
39404lduw [%i2 + 4], %o2
39405! move %o2(lower) -> %o2(upper)
39406sllx %o2, 32, %o2
39407
39408P3490: !_MEMBAR (FP)
39409membar #StoreLoad
39410
39411P3491: !_BLD [11] (FP)
39412wr %g0, 0xf0, %asi
39413ldda [%i3 + 0] %asi, %f32
39414membar #Sync
39415! 3 addresses covered
39416fmovd %f32, %f18
39417fmovs %f18, %f1
39418fmovs %f19, %f2
39419fmovd %f34, %f18
39420fmovs %f19, %f3
39421
39422P3492: !_MEMBAR (FP)
39423
39424P3493: !_BSTC [12] (maybe <- 0x4100006f) (FP)
39425wr %g0, 0xe0, %asi
39426sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
39427sub %i0, %i3, %i3
39428! preparing store val #0, next val will be in f32
39429fmovs %f16, %f20
39430fadds %f16, %f17, %f16
39431! preparing store val #1, next val will be in f33
39432fmovs %f16, %f21
39433fadds %f16, %f17, %f16
39434! preparing store val #2, next val will be in f35
39435fmovd %f20, %f32
39436fmovs %f16, %f21
39437fadds %f16, %f17, %f16
39438fmovd %f20, %f34
39439membar #Sync
39440stda %f32, [%i3 + 0 ] %asi
39441
39442P3494: !_MEMBAR (FP)
39443membar #StoreLoad
39444
39445P3495: !_DWLD [1] (Int)
39446ldx [%i0 + 0], %l7
39447! move %l7(upper) -> %o2(lower)
39448srlx %l7, 32, %l6
39449or %l6, %o2, %o2
39450! move %l7(lower) -> %o3(upper)
39451sllx %l7, 32, %o3
39452
39453P3496: !_MEMBAR (FP)
39454
39455P3497: !_BST [15] (maybe <- 0x41000072) (FP)
39456wr %g0, 0xf0, %asi
39457sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
39458sub %i0, %i2, %i2
39459! preparing store val #0, next val will be in f32
39460fmovs %f16, %f20
39461fadds %f16, %f17, %f16
39462! preparing store val #1, next val will be in f33
39463fmovs %f16, %f21
39464fadds %f16, %f17, %f16
39465! preparing store val #2, next val will be in f35
39466fmovd %f20, %f32
39467fmovs %f16, %f21
39468fadds %f16, %f17, %f16
39469fmovd %f20, %f34
39470membar #Sync
39471stda %f32, [%i2 + 0 ] %asi
39472
39473P3498: !_MEMBAR (FP)
39474membar #StoreLoad
39475
39476P3499: !_DWLD [15] (FP)
39477ldd [%i2 + 0], %f4
39478! 2 addresses covered
39479
39480P3500: !_DWLD [6] (Int)
39481sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
39482sub %i0, %i3, %i3
39483ldx [%i3 + 0], %o5
39484! move %o5(upper) -> %o3(lower)
39485srlx %o5, 32, %l7
39486or %l7, %o3, %o3
39487! move %o5(lower) -> %o4(upper)
39488sllx %o5, 32, %o4
39489
39490P3501: !_ST [17] (maybe <- 0x18000d4) (Int) (CBR)
39491stw %l4, [%i2 + 12 ]
39492add %l4, 1, %l4
39493
39494! cbranch
39495andcc %l0, 1, %g0
39496be,pn %xcc, TARGET3501
39497nop
39498RET3501:
39499
39500! lfsr step begin
39501srlx %l0, 1, %o5
39502xnor %o5, %l0, %o5
39503sllx %o5, 63, %o5
39504or %o5, %l0, %l0
39505srlx %l0, 1, %l0
39506
39507
39508P3502: !_CAS [13] (maybe <- 0x18000d5) (Int)
39509sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
39510sub %i0, %i2, %i2
39511add %i2, 4, %l6
39512lduw [%l6], %o5
39513mov %o5, %l3
39514! move %l3(lower) -> %o4(lower)
39515or %l3, %o4, %o4
39516!---- flushing int results buffer----
39517mov %o0, %l5
39518mov %o1, %l5
39519mov %o2, %l5
39520mov %o3, %l5
39521mov %o4, %l5
39522mov %l4, %o0
39523cas [%l6], %l3, %o0
39524! move %o0(lower) -> %o0(upper)
39525sllx %o0, 32, %o0
39526add %l4, 1, %l4
39527
39528P3503: !_ST_BINIT [13] (maybe <- 0x18000d6) (Int)
39529wr %g0, 0xe2, %asi
39530stwa %l4, [%i2 + 4] %asi
39531add %l4, 1, %l4
39532
39533P3504: !_MEMBAR (Int)
39534membar #StoreLoad
39535
39536P3505: !_ST_BINIT [18] (maybe <- 0x18000d7) (Int)
39537wr %g0, 0xe2, %asi
39538sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
39539sub %i0, %i3, %i3
39540stwa %l4, [%i3 + 0] %asi
39541add %l4, 1, %l4
39542
39543P3506: !_MEMBAR (Int)
39544membar #StoreLoad
39545
39546P3507: !_BLD [18] (FP)
39547wr %g0, 0xf0, %asi
39548ldda [%i3 + 0] %asi, %f32
39549membar #Sync
39550! 3 addresses covered
39551fmovd %f32, %f6
39552fmovd %f34, %f18
39553fmovs %f19, %f8
39554
39555P3508: !_MEMBAR (FP) (CBR)
39556
39557! cbranch
39558andcc %l0, 1, %g0
39559be,pt %xcc, TARGET3508
39560nop
39561RET3508:
39562
39563! lfsr step begin
39564srlx %l0, 1, %l7
39565xnor %l7, %l0, %l7
39566sllx %l7, 63, %l7
39567or %l7, %l0, %l0
39568srlx %l0, 1, %l0
39569
39570
39571P3509: !_DWLD [4] (Int)
39572ldx [%i1 + 0], %l3
39573! move %l3(upper) -> %o0(lower)
39574srlx %l3, 32, %o5
39575or %o5, %o0, %o0
39576! move %l3(lower) -> %o1(upper)
39577sllx %l3, 32, %o1
39578
39579P3510: !_CASX [9] (maybe <- 0x18000d8) (Int)
39580sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
39581add %i0, %i2, %i2
39582ldx [%i2], %l3
39583! move %l3(upper) -> %o1(lower)
39584srlx %l3, 32, %l6
39585or %l6, %o1, %o1
39586! move %l3(lower) -> %o2(upper)
39587sllx %l3, 32, %o2
39588mov %l3, %l6
39589sllx %l4, 32, %l3
39590add %l4, 1, %l4
39591or %l4, %l3, %l3
39592casx [%i2], %l6, %l3
39593! move %l3(upper) -> %o2(lower)
39594srlx %l3, 32, %l6
39595or %l6, %o2, %o2
39596! move %l3(lower) -> %o3(upper)
39597sllx %l3, 32, %o3
39598add %l4, 1, %l4
39599
39600P3511: !_MEMBAR (FP)
39601membar #StoreLoad
39602
39603P3512: !_BLD [5] (FP)
39604wr %g0, 0xf0, %asi
39605ldda [%i1 + 0] %asi, %f32
39606membar #Sync
39607! 3 addresses covered
39608fmovd %f32, %f18
39609fmovs %f18, %f9
39610fmovs %f19, %f10
39611fmovd %f34, %f18
39612fmovs %f19, %f11
39613
39614P3513: !_MEMBAR (FP)
39615
39616P3514: !_ST [17] (maybe <- 0x18000da) (Int) (LE)
39617wr %g0, 0x88, %asi
39618sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
39619sub %i0, %i3, %i3
39620! Change single-word-level endianess (big endian <-> little endian)
39621sethi %hi(0xff00ff00), %l7
39622or %l7, %lo(0xff00ff00), %l7
39623and %l4, %l7, %o5
39624srl %o5, 8, %o5
39625sll %l4, 8, %l6
39626and %l6, %l7, %l6
39627or %l6, %o5, %l6
39628srl %l6, 16, %o5
39629sll %l6, 16, %l6
39630srl %l6, 0, %l6
39631or %l6, %o5, %l6
39632stwa %l6, [%i3 + 12] %asi
39633add %l4, 1, %l4
39634
39635P3515: !_ST_BINIT [13] (maybe <- 0x18000db) (Int)
39636wr %g0, 0xe2, %asi
39637sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
39638sub %i0, %i2, %i2
39639stwa %l4, [%i2 + 4] %asi
39640add %l4, 1, %l4
39641
39642P3516: !_MEMBAR (Int)
39643membar #StoreLoad
39644
39645P3517: !_ST [10] (maybe <- 0x18000dc) (Int)
39646sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
39647sub %i0, %i3, %i3
39648stw %l4, [%i3 + 4 ]
39649add %l4, 1, %l4
39650
39651P3518: !_ST [12] (maybe <- 0x18000dd) (Int)
39652stw %l4, [%i2 + 0 ]
39653add %l4, 1, %l4
39654
39655P3519: !_ST_BINIT [6] (maybe <- 0x18000de) (Int)
39656wr %g0, 0xe2, %asi
39657sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
39658sub %i0, %i2, %i2
39659stwa %l4, [%i2 + 0] %asi
39660add %l4, 1, %l4
39661
39662P3520: !_MEMBAR (Int)
39663membar #StoreLoad
39664
39665P3521: !_SWAP [16] (maybe <- 0x18000df) (Int)
39666sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
39667sub %i0, %i3, %i3
39668mov %l4, %o5
39669swap [%i3 + 4], %o5
39670! move %o5(lower) -> %o3(lower)
39671srl %o5, 0, %l6
39672or %l6, %o3, %o3
39673add %l4, 1, %l4
39674
39675P3522: !_MEMBAR (FP)
39676
39677P3523: !_BSTC [19] (maybe <- 0x41000075) (FP)
39678wr %g0, 0xe0, %asi
39679sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
39680sub %i0, %i2, %i2
39681! preparing store val #0, next val will be in f32
39682fmovs %f16, %f20
39683fadds %f16, %f17, %f16
39684! preparing store val #1, next val will be in f33
39685fmovs %f16, %f21
39686fadds %f16, %f17, %f16
39687! preparing store val #2, next val will be in f35
39688fmovd %f20, %f32
39689fmovs %f16, %f21
39690fadds %f16, %f17, %f16
39691fmovd %f20, %f34
39692membar #Sync
39693stda %f32, [%i2 + 0 ] %asi
39694
39695P3524: !_MEMBAR (FP)
39696membar #StoreLoad
39697
39698P3525: !_SWAP [6] (maybe <- 0x18000e0) (Int)
39699sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
39700sub %i0, %i3, %i3
39701mov %l4, %o4
39702swap [%i3 + 0], %o4
39703! move %o4(lower) -> %o4(upper)
39704sllx %o4, 32, %o4
39705add %l4, 1, %l4
39706
39707P3526: !_SWAP [1] (maybe <- 0x18000e1) (Int)
39708mov %l4, %l3
39709swap [%i0 + 4], %l3
39710! move %l3(lower) -> %o4(lower)
39711srl %l3, 0, %l7
39712or %l7, %o4, %o4
39713!---- flushing int results buffer----
39714mov %o0, %l5
39715mov %o1, %l5
39716mov %o2, %l5
39717mov %o3, %l5
39718mov %o4, %l5
39719add %l4, 1, %l4
39720
39721P3527: !_PREFETCH [10] (Int)
39722sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
39723sub %i0, %i2, %i2
39724prefetch [%i2 + 4], 3
39725
39726P3528: !_ST [21] (maybe <- 0x18000e2) (Int)
39727sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
39728add %i0, %i3, %i3
39729stw %l4, [%i3 + 0 ]
39730add %l4, 1, %l4
39731
39732P3529: !_CASX [17] (maybe <- 0x18000e3) (Int)
39733sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
39734sub %i0, %i2, %i2
39735add %i2, 8, %l6
39736ldx [%l6], %o0
39737! move %o0(upper) -> %o0(upper)
39738! move %o0(lower) -> %o0(lower)
39739mov %o0, %l3
39740mov %l4, %o1
39741casx [%l6], %l3, %o1
39742! move %o1(upper) -> %o1(upper)
39743! move %o1(lower) -> %o1(lower)
39744add %l4, 1, %l4
39745
39746P3530: !_SWAP [22] (maybe <- 0x18000e4) (Int) (Branch target of P3221)
39747mov %l4, %o2
39748swap [%i3 + 4], %o2
39749! move %o2(lower) -> %o2(upper)
39750sllx %o2, 32, %o2
39751add %l4, 1, %l4
39752ba P3531
39753nop
39754
39755TARGET3221:
39756ba RET3221
39757nop
39758
39759
39760P3531: !_MEMBAR (FP)
39761
39762P3532: !_BST [22] (maybe <- 0x41000078) (FP)
39763wr %g0, 0xf0, %asi
39764! preparing store val #0, next val will be in f32
39765fmovs %f16, %f20
39766fadds %f16, %f17, %f16
39767! preparing store val #1, next val will be in f33
39768fmovs %f16, %f21
39769fadds %f16, %f17, %f16
39770! preparing store val #2, next val will be in f35
39771fmovd %f20, %f32
39772fmovs %f16, %f21
39773fadds %f16, %f17, %f16
39774fmovd %f20, %f34
39775membar #Sync
39776stda %f32, [%i3 + 0 ] %asi
39777
39778P3533: !_MEMBAR (FP)
39779membar #StoreLoad
39780
39781P3534: !_LD [20] (Int)
39782sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
39783sub %i0, %i3, %i3
39784lduw [%i3 + 12], %o5
39785! move %o5(lower) -> %o2(lower)
39786or %o5, %o2, %o2
39787
39788P3535: !_CAS [19] (maybe <- 0x18000e5) (Int)
39789add %i3, 4, %l6
39790lduw [%l6], %o3
39791mov %o3, %l3
39792! move %l3(lower) -> %o3(upper)
39793sllx %l3, 32, %o3
39794mov %l4, %o5
39795cas [%l6], %l3, %o5
39796! move %o5(lower) -> %o3(lower)
39797srl %o5, 0, %l3
39798or %l3, %o3, %o3
39799add %l4, 1, %l4
39800
39801P3536: !_REPLACEMENT [4] (Int) (Branch target of P3987)
39802sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
39803sub %i0, %i2, %i2
39804sethi %hi(0x20000), %l3
39805ld [%i2+4], %l7
39806st %l7, [%i2+4]
39807add %i2, %l3, %l6
39808ld [%l6+4], %l7
39809st %l7, [%l6+4]
39810add %l6, %l3, %l6
39811ld [%l6+4], %l7
39812st %l7, [%l6+4]
39813add %l6, %l3, %l6
39814ld [%l6+4], %l7
39815st %l7, [%l6+4]
39816add %l6, %l3, %l6
39817ld [%l6+4], %l7
39818st %l7, [%l6+4]
39819add %l6, %l3, %l6
39820ld [%l6+4], %l7
39821st %l7, [%l6+4]
39822add %l6, %l3, %l6
39823ld [%l6+4], %l7
39824st %l7, [%l6+4]
39825add %l6, %l3, %l6
39826ld [%l6+4], %l7
39827st %l7, [%l6+4]
39828ba P3537
39829nop
39830
39831TARGET3987:
39832ba RET3987
39833nop
39834
39835
39836P3537: !_ST [5] (maybe <- 0x18000e6) (Int)
39837stw %l4, [%i1 + 12 ]
39838add %l4, 1, %l4
39839
39840P3538: !_DWLD [17] (Int) (Branch target of P3792)
39841sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
39842sub %i0, %i3, %i3
39843ldx [%i3 + 8], %o4
39844! move %o4(lower) -> %o4(upper)
39845sllx %o4, 32, %o4
39846ba P3539
39847nop
39848
39849TARGET3792:
39850ba RET3792
39851nop
39852
39853
39854P3539: !_LDD [6] (Int)
39855sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
39856sub %i0, %i2, %i2
39857ldd [%i2 + 0], %l6
39858! move %l6(lower) -> %o4(lower)
39859or %l6, %o4, %o4
39860!---- flushing int results buffer----
39861mov %o0, %l5
39862mov %o1, %l5
39863mov %o2, %l5
39864mov %o3, %l5
39865mov %o4, %l5
39866! move %l7(lower) -> %o0(upper)
39867sllx %l7, 32, %o0
39868
39869P3540: !_MEMBAR (FP)
39870
39871P3541: !_BSTC [14] (maybe <- 0x4100007b) (FP)
39872wr %g0, 0xe0, %asi
39873sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
39874sub %i0, %i3, %i3
39875! preparing store val #0, next val will be in f32
39876fmovs %f16, %f20
39877fadds %f16, %f17, %f16
39878! preparing store val #1, next val will be in f33
39879fmovs %f16, %f21
39880fadds %f16, %f17, %f16
39881! preparing store val #2, next val will be in f35
39882fmovd %f20, %f32
39883fmovs %f16, %f21
39884fadds %f16, %f17, %f16
39885fmovd %f20, %f34
39886membar #Sync
39887stda %f32, [%i3 + 0 ] %asi
39888
39889P3542: !_MEMBAR (FP)
39890
39891P3543: !_BST [4] (maybe <- 0x4100007e) (FP)
39892wr %g0, 0xf0, %asi
39893! preparing store val #0, next val will be in f32
39894fmovs %f16, %f20
39895fadds %f16, %f17, %f16
39896! preparing store val #1, next val will be in f33
39897fmovs %f16, %f21
39898fadds %f16, %f17, %f16
39899! preparing store val #2, next val will be in f35
39900fmovd %f20, %f32
39901fmovs %f16, %f21
39902fadds %f16, %f17, %f16
39903fmovd %f20, %f34
39904membar #Sync
39905stda %f32, [%i1 + 0 ] %asi
39906
39907P3544: !_MEMBAR (FP)
39908membar #StoreLoad
39909
39910P3545: !_PREFETCH [11] (Int)
39911sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
39912sub %i0, %i2, %i2
39913prefetch [%i2 + 12], 4
39914
39915P3546: !_MEMBAR (FP)
39916membar #StoreLoad
39917
39918P3547: !_BLD [9] (FP)
39919wr %g0, 0xf0, %asi
39920ldda [%i2 + 0] %asi, %f32
39921membar #Sync
39922! 3 addresses covered
39923fmovd %f32, %f12
39924fmovd %f34, %f18
39925fmovs %f19, %f14
39926
39927P3548: !_MEMBAR (FP)
39928
39929P3549: !_ST_BINIT [8] (maybe <- 0x18000e7) (Int)
39930wr %g0, 0xe2, %asi
39931sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
39932sub %i0, %i3, %i3
39933stwa %l4, [%i3 + 12] %asi
39934add %l4, 1, %l4
39935
39936P3550: !_MEMBAR (Int)
39937membar #StoreLoad
39938
39939P3551: !_ST_BINIT [6] (maybe <- 0x18000e8) (Int)
39940wr %g0, 0xe2, %asi
39941stwa %l4, [%i3 + 0] %asi
39942add %l4, 1, %l4
39943
39944P3552: !_MEMBAR (Int) (Branch target of P3262)
39945membar #StoreLoad
39946ba P3553
39947nop
39948
39949TARGET3262:
39950ba RET3262
39951nop
39952
39953
39954P3553: !_ST_BINIT [5] (maybe <- 0x18000e9) (Int)
39955wr %g0, 0xe2, %asi
39956stwa %l4, [%i1 + 12] %asi
39957add %l4, 1, %l4
39958
39959P3554: !_MEMBAR (Int)
39960membar #StoreLoad
39961
39962P3555: !_ST_BINIT [0] (maybe <- 0x18000ea) (Int)
39963wr %g0, 0xe2, %asi
39964stwa %l4, [%i0 + 0] %asi
39965add %l4, 1, %l4
39966
39967P3556: !_MEMBAR (Int)
39968membar #StoreLoad
39969
39970P3557: !_CAS [1] (maybe <- 0x18000eb) (Int)
39971add %i0, 4, %o5
39972lduw [%o5], %l6
39973mov %l6, %l7
39974! move %l7(lower) -> %o0(lower)
39975or %l7, %o0, %o0
39976mov %l4, %o1
39977cas [%o5], %l7, %o1
39978! move %o1(lower) -> %o1(upper)
39979sllx %o1, 32, %o1
39980add %l4, 1, %l4
39981
39982P3558: !_SWAP [13] (maybe <- 0x18000ec) (Int)
39983sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
39984sub %i0, %i2, %i2
39985mov %l4, %l3
39986swap [%i2 + 4], %l3
39987! move %l3(lower) -> %o1(lower)
39988srl %l3, 0, %l7
39989or %l7, %o1, %o1
39990add %l4, 1, %l4
39991
39992P3559: !_ST_BINIT [0] (maybe <- 0x18000ed) (Int)
39993wr %g0, 0xe2, %asi
39994stwa %l4, [%i0 + 0] %asi
39995add %l4, 1, %l4
39996
39997P3560: !_MEMBAR (Int)
39998
39999P3561: !_BST [11] (maybe <- 0x41000081) (FP)
40000wr %g0, 0xf0, %asi
40001sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
40002sub %i0, %i3, %i3
40003! preparing store val #0, next val will be in f32
40004fmovs %f16, %f20
40005fadds %f16, %f17, %f16
40006! preparing store val #1, next val will be in f33
40007fmovs %f16, %f21
40008fadds %f16, %f17, %f16
40009! preparing store val #2, next val will be in f35
40010fmovd %f20, %f32
40011fmovs %f16, %f21
40012fadds %f16, %f17, %f16
40013fmovd %f20, %f34
40014membar #Sync
40015stda %f32, [%i3 + 0 ] %asi
40016
40017P3562: !_MEMBAR (FP)
40018membar #StoreLoad
40019
40020P3563: !_ST [16] (maybe <- 0x18000ee) (Int)
40021sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
40022sub %i0, %i2, %i2
40023stw %l4, [%i2 + 4 ]
40024add %l4, 1, %l4
40025
40026P3564: !_PREFETCH [11] (Int)
40027prefetch [%i3 + 12], 23
40028
40029P3565: !_REPLACEMENT [12] (Int)
40030sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
40031sub %i0, %i3, %i3
40032sethi %hi(0x20000), %l7
40033ld [%i3+0], %l3
40034st %l3, [%i3+0]
40035add %i3, %l7, %o5
40036ld [%o5+0], %l3
40037st %l3, [%o5+0]
40038add %o5, %l7, %o5
40039ld [%o5+0], %l3
40040st %l3, [%o5+0]
40041add %o5, %l7, %o5
40042ld [%o5+0], %l3
40043st %l3, [%o5+0]
40044add %o5, %l7, %o5
40045ld [%o5+0], %l3
40046st %l3, [%o5+0]
40047add %o5, %l7, %o5
40048ld [%o5+0], %l3
40049st %l3, [%o5+0]
40050add %o5, %l7, %o5
40051ld [%o5+0], %l3
40052st %l3, [%o5+0]
40053add %o5, %l7, %o5
40054ld [%o5+0], %l3
40055st %l3, [%o5+0]
40056
40057P3566: !_ST_BINIT [22] (maybe <- 0x18000ef) (Int)
40058wr %g0, 0xe2, %asi
40059sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
40060add %i0, %i2, %i2
40061stwa %l4, [%i2 + 4] %asi
40062add %l4, 1, %l4
40063
40064P3567: !_MEMBAR (Int)
40065membar #StoreLoad
40066
40067P3568: !_CAS [15] (maybe <- 0x18000f0) (Int)
40068sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
40069sub %i0, %i3, %i3
40070lduw [%i3], %o2
40071mov %o2, %l3
40072! move %l3(lower) -> %o2(upper)
40073sllx %l3, 32, %o2
40074mov %l4, %o5
40075cas [%i3], %l3, %o5
40076! move %o5(lower) -> %o2(lower)
40077srl %o5, 0, %l3
40078or %l3, %o2, %o2
40079add %l4, 1, %l4
40080
40081P3569: !_ST [15] (maybe <- 0x18000f1) (Int)
40082stw %l4, [%i3 + 0 ]
40083add %l4, 1, %l4
40084
40085P3570: !_CAS [4] (maybe <- 0x18000f2) (Int)
40086add %i1, 4, %l3
40087lduw [%l3], %o3
40088mov %o3, %o5
40089! move %o5(lower) -> %o3(upper)
40090sllx %o5, 32, %o3
40091mov %l4, %l7
40092cas [%l3], %o5, %l7
40093! move %l7(lower) -> %o3(lower)
40094srl %l7, 0, %o5
40095or %o5, %o3, %o3
40096add %l4, 1, %l4
40097
40098P3571: !_DWST_BINIT [14] (maybe <- 0x18000f3) (Int)
40099wr %g0, 0xe2, %asi
40100sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
40101sub %i0, %i2, %i2
40102mov %l4, %o5
40103stxa %o5, [%i2 + 8] %asi
40104add %l4, 1, %l4
40105
40106P3572: !_MEMBAR (Int)
40107
40108P3573: !_BST [16] (maybe <- 0x41000084) (FP)
40109wr %g0, 0xf0, %asi
40110! preparing store val #0, next val will be in f32
40111fmovs %f16, %f20
40112fadds %f16, %f17, %f16
40113! preparing store val #1, next val will be in f33
40114fmovs %f16, %f21
40115fadds %f16, %f17, %f16
40116! preparing store val #2, next val will be in f35
40117fmovd %f20, %f32
40118fmovs %f16, %f21
40119fadds %f16, %f17, %f16
40120fmovd %f20, %f34
40121membar #Sync
40122stda %f32, [%i3 + 0 ] %asi
40123
40124P3574: !_MEMBAR (FP)
40125membar #StoreLoad
40126
40127P3575: !_CAS [2] (maybe <- 0x18000f4) (Int)
40128add %i0, 12, %l7
40129lduw [%l7], %o4
40130mov %o4, %l6
40131! move %l6(lower) -> %o4(upper)
40132sllx %l6, 32, %o4
40133mov %l4, %l3
40134cas [%l7], %l6, %l3
40135! move %l3(lower) -> %o4(lower)
40136srl %l3, 0, %l6
40137or %l6, %o4, %o4
40138!---- flushing int results buffer----
40139mov %o0, %l5
40140mov %o1, %l5
40141mov %o2, %l5
40142mov %o3, %l5
40143mov %o4, %l5
40144add %l4, 1, %l4
40145
40146P3576: !_ST [1] (maybe <- 0x18000f5) (Int) (Branch target of P3874)
40147stw %l4, [%i0 + 4 ]
40148add %l4, 1, %l4
40149ba P3577
40150nop
40151
40152TARGET3874:
40153ba RET3874
40154nop
40155
40156
40157P3577: !_MEMBAR (FP)
40158
40159P3578: !_BST [10] (maybe <- 0x41000087) (FP)
40160wr %g0, 0xf0, %asi
40161sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
40162sub %i0, %i3, %i3
40163! preparing store val #0, next val will be in f32
40164fmovs %f16, %f20
40165fadds %f16, %f17, %f16
40166! preparing store val #1, next val will be in f33
40167fmovs %f16, %f21
40168fadds %f16, %f17, %f16
40169! preparing store val #2, next val will be in f35
40170fmovd %f20, %f32
40171fmovs %f16, %f21
40172fadds %f16, %f17, %f16
40173fmovd %f20, %f34
40174membar #Sync
40175stda %f32, [%i3 + 0 ] %asi
40176
40177P3579: !_MEMBAR (FP)
40178membar #StoreLoad
40179
40180P3580: !_SWAP [13] (maybe <- 0x18000f6) (Int) (Branch target of P3810)
40181mov %l4, %o0
40182swap [%i2 + 4], %o0
40183! move %o0(lower) -> %o0(upper)
40184sllx %o0, 32, %o0
40185add %l4, 1, %l4
40186ba P3581
40187nop
40188
40189TARGET3810:
40190ba RET3810
40191nop
40192
40193
40194P3581: !_SWAP [8] (maybe <- 0x18000f7) (Int)
40195sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
40196add %i0, %i2, %i2
40197mov %l4, %l6
40198swap [%i2 + 12], %l6
40199! move %l6(lower) -> %o0(lower)
40200srl %l6, 0, %o5
40201or %o5, %o0, %o0
40202add %l4, 1, %l4
40203
40204P3582: !_DWST [9] (maybe <- 0x18000f8) (Int)
40205sllx %l4, 32, %l7
40206add %l4, 1, %l4
40207or %l7, %l4, %l7
40208stx %l7, [%i3 + 0]
40209add %l4, 1, %l4
40210
40211P3583: !_ST_BINIT [7] (maybe <- 0x18000fa) (Int)
40212wr %g0, 0xe2, %asi
40213stwa %l4, [%i2 + 4] %asi
40214add %l4, 1, %l4
40215
40216P3584: !_MEMBAR (Int)
40217
40218P3585: !_BST [14] (maybe <- 0x4100008a) (FP)
40219wr %g0, 0xf0, %asi
40220sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
40221sub %i0, %i3, %i3
40222! preparing store val #0, next val will be in f32
40223fmovs %f16, %f20
40224fadds %f16, %f17, %f16
40225! preparing store val #1, next val will be in f33
40226fmovs %f16, %f21
40227fadds %f16, %f17, %f16
40228! preparing store val #2, next val will be in f35
40229fmovd %f20, %f32
40230fmovs %f16, %f21
40231fadds %f16, %f17, %f16
40232fmovd %f20, %f34
40233membar #Sync
40234stda %f32, [%i3 + 0 ] %asi
40235
40236P3586: !_MEMBAR (FP)
40237membar #StoreLoad
40238
40239P3587: !_BLD [8] (FP)
40240wr %g0, 0xf0, %asi
40241ldda [%i2 + 0] %asi, %f32
40242membar #Sync
40243! 3 addresses covered
40244fmovd %f32, %f18
40245fmovs %f18, %f15
40246!---- flushing fp results buffer to %f30 ----
40247fmovd %f0, %f30
40248fmovd %f2, %f30
40249fmovd %f4, %f30
40250fmovd %f6, %f30
40251fmovd %f8, %f30
40252fmovd %f10, %f30
40253fmovd %f12, %f30
40254fmovd %f14, %f30
40255!--
40256fmovs %f19, %f0
40257fmovd %f34, %f18
40258fmovs %f19, %f1
40259
40260P3588: !_MEMBAR (FP)
40261
40262P3589: !_DWST [7] (maybe <- 0x18000fb) (Int)
40263sllx %l4, 32, %o5
40264add %l4, 1, %l4
40265or %o5, %l4, %o5
40266stx %o5, [%i2 + 0]
40267add %l4, 1, %l4
40268
40269P3590: !_DWST [18] (maybe <- 0x18000fd) (Int)
40270sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
40271sub %i0, %i2, %i2
40272sllx %l4, 32, %l7
40273add %l4, 1, %l4
40274or %l7, %l4, %l7
40275stx %l7, [%i2 + 0]
40276add %l4, 1, %l4
40277
40278P3591: !_PREFETCH [4] (Int)
40279prefetch [%i1 + 4], 0
40280
40281P3592: !_DWST_BINIT [7] (maybe <- 0x18000ff) (Int) (LE)
40282wr %g0, 0xea, %asi
40283sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
40284add %i0, %i3, %i3
40285sllx %l4, 32, %l6
40286add %l4, 1, %l4
40287or %l6, %l4, %l7
40288! Change double-word-level endianess (big endian <-> little endian)
40289sethi %hi(0xff00ff00), %o5
40290or %o5, %lo(0xff00ff00), %o5
40291sllx %o5, 32, %l6
40292or %o5, %l6, %o5
40293and %l7, %o5, %l6
40294srlx %l6, 8, %l6
40295sllx %l7, 8, %l7
40296and %l7, %o5, %l7
40297or %l7, %l6, %l7
40298sethi %hi(0xffff0000), %o5
40299srlx %l7, 16, %l6
40300andn %l6, %o5, %l6
40301andn %l7, %o5, %l7
40302sllx %l7, 16, %l7
40303or %l7, %l6, %l7
40304srlx %l7, 32, %l6
40305sllx %l7, 32, %l7
40306or %l7, %l6, %l6
40307stxa %l6, [%i3 + 0 ] %asi
40308add %l4, 1, %l4
40309
40310P3593: !_MEMBAR (Int) (LE)
40311membar #StoreLoad
40312
40313P3594: !_LD [13] (Int)
40314sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
40315sub %i0, %i2, %i2
40316lduw [%i2 + 4], %o1
40317! move %o1(lower) -> %o1(upper)
40318sllx %o1, 32, %o1
40319
40320P3595: !_MEMBAR (FP)
40321
40322P3596: !_BSTC [21] (maybe <- 0x4100008d) (FP)
40323wr %g0, 0xe0, %asi
40324sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
40325add %i0, %i3, %i3
40326! preparing store val #0, next val will be in f32
40327fmovs %f16, %f20
40328fadds %f16, %f17, %f16
40329! preparing store val #1, next val will be in f33
40330fmovs %f16, %f21
40331fadds %f16, %f17, %f16
40332! preparing store val #2, next val will be in f35
40333fmovd %f20, %f32
40334fmovs %f16, %f21
40335fadds %f16, %f17, %f16
40336fmovd %f20, %f34
40337membar #Sync
40338stda %f32, [%i3 + 0 ] %asi
40339
40340P3597: !_MEMBAR (FP)
40341membar #StoreLoad
40342
40343P3598: !_ST [23] (maybe <- 0x41000090) (FP)
40344! preparing store val #0, next val will be in f20
40345fmovs %f16, %f20
40346fadds %f16, %f17, %f16
40347st %f20, [%i3 + 12 ]
40348
40349P3599: !_MEMBAR (FP)
40350
40351P3600: !_BSTC [6] (maybe <- 0x41000091) (FP)
40352wr %g0, 0xe0, %asi
40353sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
40354add %i0, %i2, %i2
40355! preparing store val #0, next val will be in f32
40356fmovs %f16, %f20
40357fadds %f16, %f17, %f16
40358! preparing store val #1, next val will be in f33
40359fmovs %f16, %f21
40360fadds %f16, %f17, %f16
40361! preparing store val #2, next val will be in f35
40362fmovd %f20, %f32
40363fmovs %f16, %f21
40364fadds %f16, %f17, %f16
40365fmovd %f20, %f34
40366membar #Sync
40367stda %f32, [%i2 + 0 ] %asi
40368
40369P3601: !_MEMBAR (FP)
40370membar #StoreLoad
40371
40372P3602: !_BLD [6] (FP)
40373wr %g0, 0xf0, %asi
40374ldda [%i2 + 0] %asi, %f32
40375membar #Sync
40376! 3 addresses covered
40377fmovd %f32, %f2
40378fmovd %f34, %f18
40379fmovs %f19, %f4
40380
40381P3603: !_MEMBAR (FP)
40382
40383P3604: !_BLD [14] (FP)
40384wr %g0, 0xf0, %asi
40385sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
40386sub %i0, %i3, %i3
40387ldda [%i3 + 0] %asi, %f32
40388membar #Sync
40389! 3 addresses covered
40390fmovd %f32, %f18
40391fmovs %f18, %f5
40392fmovs %f19, %f6
40393fmovd %f34, %f18
40394fmovs %f19, %f7
40395
40396P3605: !_MEMBAR (FP)
40397
40398P3606: !_LD [18] (Int)
40399sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
40400sub %i0, %i2, %i2
40401lduw [%i2 + 0], %l3
40402! move %l3(lower) -> %o1(lower)
40403or %l3, %o1, %o1
40404
40405P3607: !_DWST_BINIT [17] (maybe <- 0x1800101) (Int)
40406wr %g0, 0xe2, %asi
40407sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
40408sub %i0, %i3, %i3
40409mov %l4, %l6
40410stxa %l6, [%i3 + 8] %asi
40411add %l4, 1, %l4
40412
40413P3608: !_MEMBAR (Int)
40414membar #StoreLoad
40415
40416P3609: !_REPLACEMENT [17] (Int)
40417sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
40418sub %i0, %i2, %i2
40419sethi %hi(0x20000), %l3
40420ld [%i2+12], %l7
40421st %l7, [%i2+12]
40422add %i2, %l3, %l6
40423ld [%l6+12], %l7
40424st %l7, [%l6+12]
40425add %l6, %l3, %l6
40426ld [%l6+12], %l7
40427st %l7, [%l6+12]
40428add %l6, %l3, %l6
40429ld [%l6+12], %l7
40430st %l7, [%l6+12]
40431add %l6, %l3, %l6
40432ld [%l6+12], %l7
40433st %l7, [%l6+12]
40434add %l6, %l3, %l6
40435ld [%l6+12], %l7
40436st %l7, [%l6+12]
40437add %l6, %l3, %l6
40438ld [%l6+12], %l7
40439st %l7, [%l6+12]
40440add %l6, %l3, %l6
40441ld [%l6+12], %l7
40442st %l7, [%l6+12]
40443
40444P3610: !_CASX [21] (maybe <- 0x1800102) (Int)
40445sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
40446add %i0, %i3, %i3
40447ldx [%i3], %o2
40448! move %o2(upper) -> %o2(upper)
40449! move %o2(lower) -> %o2(lower)
40450mov %o2, %o5
40451sllx %l4, 32, %o3
40452add %l4, 1, %l4
40453or %l4, %o3, %o3
40454casx [%i3], %o5, %o3
40455! move %o3(upper) -> %o3(upper)
40456! move %o3(lower) -> %o3(lower)
40457add %l4, 1, %l4
40458
40459P3611: !_PREFETCH [20] (Int)
40460sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
40461sub %i0, %i2, %i2
40462prefetch [%i2 + 12], 2
40463
40464P3612: !_CAS [8] (maybe <- 0x1800104) (Int)
40465sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
40466add %i0, %i3, %i3
40467add %i3, 12, %l3
40468lduw [%l3], %o4
40469mov %o4, %o5
40470! move %o5(lower) -> %o4(upper)
40471sllx %o5, 32, %o4
40472mov %l4, %l7
40473cas [%l3], %o5, %l7
40474! move %l7(lower) -> %o4(lower)
40475srl %l7, 0, %o5
40476or %o5, %o4, %o4
40477!---- flushing int results buffer----
40478mov %o0, %l5
40479mov %o1, %l5
40480mov %o2, %l5
40481mov %o3, %l5
40482mov %o4, %l5
40483add %l4, 1, %l4
40484
40485P3613: !_MEMBAR (FP)
40486
40487P3614: !_BST [19] (maybe <- 0x41000094) (FP)
40488wr %g0, 0xf0, %asi
40489! preparing store val #0, next val will be in f32
40490fmovs %f16, %f20
40491fadds %f16, %f17, %f16
40492! preparing store val #1, next val will be in f33
40493fmovs %f16, %f21
40494fadds %f16, %f17, %f16
40495! preparing store val #2, next val will be in f35
40496fmovd %f20, %f32
40497fmovs %f16, %f21
40498fadds %f16, %f17, %f16
40499fmovd %f20, %f34
40500membar #Sync
40501stda %f32, [%i2 + 0 ] %asi
40502
40503P3615: !_MEMBAR (FP)
40504membar #StoreLoad
40505
40506P3616: !_PREFETCH [10] (Int)
40507sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
40508sub %i0, %i2, %i2
40509prefetch [%i2 + 4], 0
40510
40511P3617: !_MEMBAR (FP)
40512
40513P3618: !_BSTC [13] (maybe <- 0x41000097) (FP)
40514wr %g0, 0xe0, %asi
40515sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
40516sub %i0, %i3, %i3
40517! preparing store val #0, next val will be in f32
40518fmovs %f16, %f20
40519fadds %f16, %f17, %f16
40520! preparing store val #1, next val will be in f33
40521fmovs %f16, %f21
40522fadds %f16, %f17, %f16
40523! preparing store val #2, next val will be in f35
40524fmovd %f20, %f32
40525fmovs %f16, %f21
40526fadds %f16, %f17, %f16
40527fmovd %f20, %f34
40528membar #Sync
40529stda %f32, [%i3 + 0 ] %asi
40530
40531P3619: !_MEMBAR (FP) (Branch target of P3133)
40532membar #StoreLoad
40533ba P3620
40534nop
40535
40536TARGET3133:
40537ba RET3133
40538nop
40539
40540
40541P3620: !_DWLD [1] (Int) (CBR)
40542ldx [%i0 + 0], %o0
40543! move %o0(upper) -> %o0(upper)
40544! move %o0(lower) -> %o0(lower)
40545
40546! cbranch
40547andcc %l0, 1, %g0
40548be,pn %xcc, TARGET3620
40549nop
40550RET3620:
40551
40552! lfsr step begin
40553srlx %l0, 1, %o5
40554xnor %o5, %l0, %o5
40555sllx %o5, 63, %o5
40556or %o5, %l0, %l0
40557srlx %l0, 1, %l0
40558
40559
40560P3621: !_DWST [17] (maybe <- 0x1800105) (Int)
40561sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
40562sub %i0, %i2, %i2
40563mov %l4, %l3
40564stx %l3, [%i2 + 8]
40565add %l4, 1, %l4
40566
40567P3622: !_DWLD [13] (FP)
40568ldd [%i3 + 0], %f8
40569! 2 addresses covered
40570
40571P3623: !_LD [0] (Int)
40572lduw [%i0 + 0], %o1
40573! move %o1(lower) -> %o1(upper)
40574sllx %o1, 32, %o1
40575
40576P3624: !_CAS [3] (maybe <- 0x1800106) (Int)
40577lduw [%i1], %l3
40578mov %l3, %l6
40579! move %l6(lower) -> %o1(lower)
40580or %l6, %o1, %o1
40581mov %l4, %o2
40582cas [%i1], %l6, %o2
40583! move %o2(lower) -> %o2(upper)
40584sllx %o2, 32, %o2
40585add %l4, 1, %l4
40586
40587P3625: !_MEMBAR (FP)
40588
40589P3626: !_BSTC [3] (maybe <- 0x4100009a) (FP) (CBR)
40590wr %g0, 0xe0, %asi
40591! preparing store val #0, next val will be in f32
40592fmovs %f16, %f20
40593fadds %f16, %f17, %f16
40594! preparing store val #1, next val will be in f33
40595fmovs %f16, %f21
40596fadds %f16, %f17, %f16
40597! preparing store val #2, next val will be in f35
40598fmovd %f20, %f32
40599fmovs %f16, %f21
40600fadds %f16, %f17, %f16
40601fmovd %f20, %f34
40602membar #Sync
40603stda %f32, [%i1 + 0 ] %asi
40604
40605! cbranch
40606andcc %l0, 1, %g0
40607be,pn %xcc, TARGET3626
40608nop
40609RET3626:
40610
40611! lfsr step begin
40612srlx %l0, 1, %l3
40613xnor %l3, %l0, %l3
40614sllx %l3, 63, %l3
40615or %l3, %l0, %l0
40616srlx %l0, 1, %l0
40617
40618
40619P3627: !_MEMBAR (FP)
40620membar #StoreLoad
40621
40622P3628: !_LDD [2] (Int)
40623ldd [%i0 + 8], %l6
40624! move %l7(lower) -> %o2(lower)
40625or %l7, %o2, %o2
40626
40627P3629: !_MEMBAR (FP)
40628membar #StoreLoad
40629
40630P3630: !_BLD [3] (FP)
40631wr %g0, 0xf0, %asi
40632ldda [%i1 + 0] %asi, %f32
40633membar #Sync
40634! 3 addresses covered
40635fmovd %f32, %f10
40636fmovd %f34, %f18
40637fmovs %f19, %f12
40638
40639P3631: !_MEMBAR (FP)
40640
40641P3632: !_PREFETCH [20] (Int)
40642sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
40643sub %i0, %i3, %i3
40644prefetch [%i3 + 12], 18
40645
40646P3633: !_DWLD [22] (Int)
40647sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
40648add %i0, %i2, %i2
40649ldx [%i2 + 0], %o3
40650! move %o3(upper) -> %o3(upper)
40651! move %o3(lower) -> %o3(lower)
40652
40653P3634: !_DWLD [0] (Int)
40654ldx [%i0 + 0], %o4
40655! move %o4(upper) -> %o4(upper)
40656! move %o4(lower) -> %o4(lower)
40657!---- flushing int results buffer----
40658mov %o0, %l5
40659mov %o1, %l5
40660mov %o2, %l5
40661mov %o3, %l5
40662mov %o4, %l5
40663
40664P3635: !_CASX [6] (maybe <- 0x1800107) (Int)
40665sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
40666add %i0, %i3, %i3
40667ldx [%i3], %o0
40668! move %o0(upper) -> %o0(upper)
40669! move %o0(lower) -> %o0(lower)
40670mov %o0, %l3
40671sllx %l4, 32, %o1
40672add %l4, 1, %l4
40673or %l4, %o1, %o1
40674casx [%i3], %l3, %o1
40675! move %o1(upper) -> %o1(upper)
40676! move %o1(lower) -> %o1(lower)
40677add %l4, 1, %l4
40678
40679P3636: !_PREFETCH [8] (Int) (Branch target of P3124)
40680prefetch [%i3 + 12], 1
40681ba P3637
40682nop
40683
40684TARGET3124:
40685ba RET3124
40686nop
40687
40688
40689P3637: !_CASX [7] (maybe <- 0x1800109) (Int) (LE)
40690sllx %l4, 32, %l6
40691add %l4, 1, %l4
40692or %l4, %l6, %l6
40693! Change double-word-level endianess (big endian <-> little endian)
40694sethi %hi(0xff00ff00), %l3
40695or %l3, %lo(0xff00ff00), %l3
40696sllx %l3, 32, %l7
40697or %l3, %l7, %l3
40698and %l6, %l3, %l7
40699srlx %l7, 8, %l7
40700sllx %l6, 8, %l6
40701and %l6, %l3, %l6
40702or %l6, %l7, %l6
40703sethi %hi(0xffff0000), %l3
40704srlx %l6, 16, %l7
40705andn %l7, %l3, %l7
40706andn %l6, %l3, %l6
40707sllx %l6, 16, %l6
40708or %l6, %l7, %l6
40709srlx %l6, 32, %l7
40710sllx %l6, 32, %l6
40711or %l6, %l7, %l7
40712wr %g0, 0x88, %asi
40713ldxa [%i3] %asi, %o5
40714! move %o5(lower) -> %o2(upper)
40715sllx %o5, 32, %o2
40716! move %o5(upper) -> %o2(lower)
40717srlx %o5, 32, %l3
40718or %l3, %o2, %o2
40719mov %o5, %l3
40720mov %l7, %o5
40721casxa [%i3] %asi, %l3, %o5
40722! move %o5(lower) -> %o3(upper)
40723sllx %o5, 32, %o3
40724! move %o5(upper) -> %o3(lower)
40725srlx %o5, 32, %l3
40726or %l3, %o3, %o3
40727add %l4, 1, %l4
40728
40729P3638: !_MEMBAR (FP)
40730membar #StoreLoad
40731
40732P3639: !_BLD [16] (FP)
40733wr %g0, 0xf0, %asi
40734sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
40735sub %i0, %i2, %i2
40736ldda [%i2 + 0] %asi, %f32
40737membar #Sync
40738! 3 addresses covered
40739fmovd %f32, %f18
40740fmovs %f18, %f13
40741fmovs %f19, %f14
40742fmovd %f34, %f18
40743fmovs %f19, %f15
40744!---- flushing fp results buffer to %f30 ----
40745fmovd %f0, %f30
40746fmovd %f2, %f30
40747fmovd %f4, %f30
40748fmovd %f6, %f30
40749fmovd %f8, %f30
40750fmovd %f10, %f30
40751fmovd %f12, %f30
40752fmovd %f14, %f30
40753!--
40754
40755P3640: !_MEMBAR (FP)
40756
40757P3641: !_SWAP [13] (maybe <- 0x180010b) (Int)
40758sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
40759sub %i0, %i3, %i3
40760mov %l4, %o4
40761swap [%i3 + 4], %o4
40762! move %o4(lower) -> %o4(upper)
40763sllx %o4, 32, %o4
40764add %l4, 1, %l4
40765
40766P3642: !_CASX [5] (maybe <- 0x180010c) (Int)
40767add %i1, 8, %l3
40768ldx [%l3], %l7
40769! move %l7(upper) -> %o4(lower)
40770srlx %l7, 32, %o5
40771or %o5, %o4, %o4
40772!---- flushing int results buffer----
40773mov %o0, %l5
40774mov %o1, %l5
40775mov %o2, %l5
40776mov %o3, %l5
40777mov %o4, %l5
40778! move %l7(lower) -> %o0(upper)
40779sllx %l7, 32, %o0
40780mov %l7, %o5
40781mov %l4, %l7
40782casx [%l3], %o5, %l7
40783! move %l7(upper) -> %o0(lower)
40784srlx %l7, 32, %o5
40785or %o5, %o0, %o0
40786! move %l7(lower) -> %o1(upper)
40787sllx %l7, 32, %o1
40788add %l4, 1, %l4
40789
40790P3643: !_CAS [22] (maybe <- 0x180010d) (Int)
40791sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
40792add %i0, %i2, %i2
40793add %i2, 4, %l3
40794lduw [%l3], %l7
40795mov %l7, %o5
40796! move %o5(lower) -> %o1(lower)
40797or %o5, %o1, %o1
40798mov %l4, %o2
40799cas [%l3], %o5, %o2
40800! move %o2(lower) -> %o2(upper)
40801sllx %o2, 32, %o2
40802add %l4, 1, %l4
40803
40804P3644: !_PREFETCH [1] (Int)
40805prefetch [%i0 + 4], 25
40806
40807P3645: !_CASX [5] (maybe <- 0x180010e) (Int)
40808!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
40809!Logical addr: 5
40810
40811sethi %hi(0x200000), %o5
40812sub %i1, %o5, %i1
40813add %i1, 8, %l6
40814ldx [%l6], %o5
40815! move %o5(upper) -> %o2(lower)
40816srlx %o5, 32, %l3
40817or %l3, %o2, %o2
40818! move %o5(lower) -> %o3(upper)
40819sllx %o5, 32, %o3
40820mov %o5, %l3
40821mov %l4, %o5
40822casx [%l6], %l3, %o5
40823! move %o5(upper) -> %o3(lower)
40824srlx %o5, 32, %l3
40825or %l3, %o3, %o3
40826! move %o5(lower) -> %o4(upper)
40827sllx %o5, 32, %o4
40828add %l4, 1, %l4
40829
40830P3646: !_ST [9] (maybe <- 0x180010f) (Int)
40831sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
40832sub %i0, %i3, %i3
40833stw %l4, [%i3 + 0 ]
40834add %l4, 1, %l4
40835
40836P3647: !_MEMBAR (FP)
40837membar #StoreLoad
40838
40839P3648: !_BLD [3] (FP)
40840wr %g0, 0xf0, %asi
40841ldda [%i1 + 0] %asi, %f0
40842membar #Sync
40843! 3 addresses covered
40844fmovs %f3, %f2
40845
40846P3649: !_MEMBAR (FP)
40847
40848P3650: !_LDD [23] (Int)
40849ldd [%i2 + 8], %l6
40850! move %l7(lower) -> %o4(lower)
40851or %l7, %o4, %o4
40852!---- flushing int results buffer----
40853mov %o0, %l5
40854mov %o1, %l5
40855mov %o2, %l5
40856mov %o3, %l5
40857mov %o4, %l5
40858
40859P3651: !_ST [19] (maybe <- 0x1800110) (Int)
40860sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
40861sub %i0, %i2, %i2
40862stw %l4, [%i2 + 4 ]
40863add %l4, 1, %l4
40864
40865P3652: !_LD [12] (Int)
40866sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
40867sub %i0, %i3, %i3
40868lduw [%i3 + 0], %o0
40869! move %o0(lower) -> %o0(upper)
40870sllx %o0, 32, %o0
40871
40872P3653: !_CAS [7] (maybe <- 0x1800111) (Int)
40873sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
40874add %i0, %i2, %i2
40875add %i2, 4, %l7
40876lduw [%l7], %l3
40877mov %l3, %l6
40878! move %l6(lower) -> %o0(lower)
40879or %l6, %o0, %o0
40880mov %l4, %o1
40881cas [%l7], %l6, %o1
40882! move %o1(lower) -> %o1(upper)
40883sllx %o1, 32, %o1
40884add %l4, 1, %l4
40885
40886P3654: !_CASX [6] (maybe <- 0x1800112) (Int)
40887ldx [%i2], %l3
40888! move %l3(upper) -> %o1(lower)
40889srlx %l3, 32, %l6
40890or %l6, %o1, %o1
40891! move %l3(lower) -> %o2(upper)
40892sllx %l3, 32, %o2
40893mov %l3, %l6
40894sllx %l4, 32, %l3
40895add %l4, 1, %l4
40896or %l4, %l3, %l3
40897casx [%i2], %l6, %l3
40898! move %l3(upper) -> %o2(lower)
40899srlx %l3, 32, %l6
40900or %l6, %o2, %o2
40901! move %l3(lower) -> %o3(upper)
40902sllx %l3, 32, %o3
40903add %l4, 1, %l4
40904
40905P3655: !_SWAP [12] (maybe <- 0x1800114) (Int)
40906mov %l4, %o5
40907swap [%i3 + 0], %o5
40908! move %o5(lower) -> %o3(lower)
40909srl %o5, 0, %l6
40910or %l6, %o3, %o3
40911add %l4, 1, %l4
40912
40913P3656: !_MEMBAR (FP)
40914
40915P3657: !_BST [4] (maybe <- 0x4100009d) (FP)
40916wr %g0, 0xf0, %asi
40917! preparing store val #0, next val will be in f32
40918fmovs %f16, %f20
40919fadds %f16, %f17, %f16
40920! preparing store val #1, next val will be in f33
40921fmovs %f16, %f21
40922fadds %f16, %f17, %f16
40923! preparing store val #2, next val will be in f35
40924fmovd %f20, %f32
40925fmovs %f16, %f21
40926fadds %f16, %f17, %f16
40927fmovd %f20, %f34
40928membar #Sync
40929stda %f32, [%i1 + 0 ] %asi
40930
40931P3658: !_MEMBAR (FP) (CBR)
40932membar #StoreLoad
40933
40934! cbranch
40935andcc %l0, 1, %g0
40936be,pn %xcc, TARGET3658
40937nop
40938RET3658:
40939
40940! lfsr step begin
40941srlx %l0, 1, %o5
40942xnor %o5, %l0, %o5
40943sllx %o5, 63, %o5
40944or %o5, %l0, %l0
40945srlx %l0, 1, %l0
40946
40947
40948P3659: !_DWLD [19] (Int) (LE)
40949wr %g0, 0x88, %asi
40950sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
40951sub %i0, %i3, %i3
40952ldxa [%i3 + 0] %asi, %l6
40953! move %l6(lower) -> %o4(upper)
40954sllx %l6, 32, %o4
40955! move %l6(upper) -> %o4(lower)
40956srlx %l6, 32, %l3
40957or %l3, %o4, %o4
40958!---- flushing int results buffer----
40959mov %o0, %l5
40960mov %o1, %l5
40961mov %o2, %l5
40962mov %o3, %l5
40963mov %o4, %l5
40964
40965P3660: !_ST [1] (maybe <- 0x1800115) (Int)
40966stw %l4, [%i0 + 4 ]
40967add %l4, 1, %l4
40968
40969P3661: !_ST_BINIT [16] (maybe <- 0x1800116) (Int)
40970wr %g0, 0xe2, %asi
40971sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
40972sub %i0, %i2, %i2
40973stwa %l4, [%i2 + 4] %asi
40974add %l4, 1, %l4
40975
40976P3662: !_MEMBAR (Int)
40977membar #StoreLoad
40978
40979P3663: !_SWAP [16] (maybe <- 0x1800117) (Int)
40980mov %l4, %o0
40981swap [%i2 + 4], %o0
40982! move %o0(lower) -> %o0(upper)
40983sllx %o0, 32, %o0
40984add %l4, 1, %l4
40985
40986P3664: !_MEMBAR (FP)
40987membar #StoreLoad
40988
40989P3665: !_BLD [5] (FP)
40990wr %g0, 0xf0, %asi
40991ldda [%i1 + 0] %asi, %f32
40992membar #Sync
40993! 3 addresses covered
40994fmovd %f32, %f18
40995fmovs %f18, %f3
40996fmovs %f19, %f4
40997fmovd %f34, %f18
40998fmovs %f19, %f5
40999
41000P3666: !_MEMBAR (FP)
41001
41002P3667: !_BLD [17] (FP)
41003wr %g0, 0xf0, %asi
41004ldda [%i2 + 0] %asi, %f32
41005membar #Sync
41006! 3 addresses covered
41007fmovd %f32, %f6
41008fmovd %f34, %f18
41009fmovs %f19, %f8
41010
41011P3668: !_MEMBAR (FP)
41012
41013P3669: !_ST [15] (maybe <- 0x1800118) (Int)
41014stw %l4, [%i2 + 0 ]
41015add %l4, 1, %l4
41016
41017P3670: !_MEMBAR (FP)
41018membar #StoreLoad
41019
41020P3671: !_BLD [4] (FP)
41021wr %g0, 0xf0, %asi
41022ldda [%i1 + 0] %asi, %f32
41023membar #Sync
41024! 3 addresses covered
41025fmovd %f32, %f18
41026fmovs %f18, %f9
41027fmovs %f19, %f10
41028fmovd %f34, %f18
41029fmovs %f19, %f11
41030
41031P3672: !_MEMBAR (FP)
41032
41033P3673: !_ST [20] (maybe <- 0x1800119) (Int)
41034stw %l4, [%i3 + 12 ]
41035add %l4, 1, %l4
41036
41037P3674: !_MEMBAR (FP)
41038membar #StoreLoad
41039
41040P3675: !_BLD [10] (FP)
41041wr %g0, 0xf0, %asi
41042sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
41043sub %i0, %i3, %i3
41044ldda [%i3 + 0] %asi, %f32
41045membar #Sync
41046! 3 addresses covered
41047fmovd %f32, %f12
41048fmovd %f34, %f18
41049fmovs %f19, %f14
41050
41051P3676: !_MEMBAR (FP)
41052
41053P3677: !_ST [8] (maybe <- 0x180011a) (Int)
41054sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
41055add %i0, %i2, %i2
41056stw %l4, [%i2 + 12 ]
41057add %l4, 1, %l4
41058
41059P3678: !_LD [11] (Int)
41060lduw [%i3 + 12], %l6
41061! move %l6(lower) -> %o0(lower)
41062or %l6, %o0, %o0
41063
41064P3679: !_ST [11] (maybe <- 0x180011b) (Int)
41065stw %l4, [%i3 + 12 ]
41066add %l4, 1, %l4
41067
41068P3680: !_ST [17] (maybe <- 0x180011c) (Int)
41069sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
41070sub %i0, %i3, %i3
41071stw %l4, [%i3 + 12 ]
41072add %l4, 1, %l4
41073
41074P3681: !_CASX [16] (maybe <- 0x180011d) (Int)
41075ldx [%i3], %o1
41076! move %o1(upper) -> %o1(upper)
41077! move %o1(lower) -> %o1(lower)
41078mov %o1, %l3
41079sllx %l4, 32, %o2
41080add %l4, 1, %l4
41081or %l4, %o2, %o2
41082casx [%i3], %l3, %o2
41083! move %o2(upper) -> %o2(upper)
41084! move %o2(lower) -> %o2(lower)
41085add %l4, 1, %l4
41086
41087P3682: !_DWST_BINIT [23] (maybe <- 0x180011f) (Int)
41088wr %g0, 0xe2, %asi
41089sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
41090add %i0, %i2, %i2
41091mov %l4, %l3
41092stxa %l3, [%i2 + 8] %asi
41093add %l4, 1, %l4
41094
41095P3683: !_MEMBAR (Int)
41096
41097P3684: !_BSTC [19] (maybe <- 0x410000a0) (FP)
41098wr %g0, 0xe0, %asi
41099sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
41100sub %i0, %i3, %i3
41101! preparing store val #0, next val will be in f32
41102fmovs %f16, %f20
41103fadds %f16, %f17, %f16
41104! preparing store val #1, next val will be in f33
41105fmovs %f16, %f21
41106fadds %f16, %f17, %f16
41107! preparing store val #2, next val will be in f35
41108fmovd %f20, %f32
41109fmovs %f16, %f21
41110fadds %f16, %f17, %f16
41111fmovd %f20, %f34
41112membar #Sync
41113stda %f32, [%i3 + 0 ] %asi
41114
41115P3685: !_MEMBAR (FP)
41116membar #StoreLoad
41117
41118P3686: !_CASX [1] (maybe <- 0x1800120) (Int)
41119ldx [%i0], %o3
41120! move %o3(upper) -> %o3(upper)
41121! move %o3(lower) -> %o3(lower)
41122mov %o3, %l7
41123sllx %l4, 32, %o4
41124add %l4, 1, %l4
41125or %l4, %o4, %o4
41126casx [%i0], %l7, %o4
41127! move %o4(upper) -> %o4(upper)
41128! move %o4(lower) -> %o4(lower)
41129!---- flushing int results buffer----
41130mov %o0, %l5
41131mov %o1, %l5
41132mov %o2, %l5
41133mov %o3, %l5
41134mov %o4, %l5
41135add %l4, 1, %l4
41136
41137P3687: !_PREFETCH [23] (Int)
41138prefetch [%i2 + 12], 21
41139
41140P3688: !_LD [11] (Int)
41141sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
41142sub %i0, %i2, %i2
41143lduw [%i2 + 12], %o0
41144! move %o0(lower) -> %o0(upper)
41145sllx %o0, 32, %o0
41146
41147P3689: !_MEMBAR (FP)
41148
41149P3690: !_BST [7] (maybe <- 0x410000a3) (FP)
41150wr %g0, 0xf0, %asi
41151sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
41152add %i0, %i3, %i3
41153! preparing store val #0, next val will be in f32
41154fmovs %f16, %f20
41155fadds %f16, %f17, %f16
41156! preparing store val #1, next val will be in f33
41157fmovs %f16, %f21
41158fadds %f16, %f17, %f16
41159! preparing store val #2, next val will be in f35
41160fmovd %f20, %f32
41161fmovs %f16, %f21
41162fadds %f16, %f17, %f16
41163fmovd %f20, %f34
41164membar #Sync
41165stda %f32, [%i3 + 0 ] %asi
41166
41167P3691: !_MEMBAR (FP)
41168membar #StoreLoad
41169
41170P3692: !_SWAP [14] (maybe <- 0x1800122) (Int)
41171sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
41172sub %i0, %i2, %i2
41173mov %l4, %l6
41174swap [%i2 + 12], %l6
41175! move %l6(lower) -> %o0(lower)
41176srl %l6, 0, %o5
41177or %o5, %o0, %o0
41178add %l4, 1, %l4
41179
41180P3693: !_CASX [10] (maybe <- 0x1800123) (Int)
41181sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
41182sub %i0, %i3, %i3
41183ldx [%i3], %o1
41184! move %o1(upper) -> %o1(upper)
41185! move %o1(lower) -> %o1(lower)
41186mov %o1, %l7
41187sllx %l4, 32, %o2
41188add %l4, 1, %l4
41189or %l4, %o2, %o2
41190casx [%i3], %l7, %o2
41191! move %o2(upper) -> %o2(upper)
41192! move %o2(lower) -> %o2(lower)
41193add %l4, 1, %l4
41194
41195P3694: !_MEMBAR (FP)
41196
41197P3695: !_BSTC [0] (maybe <- 0x410000a6) (FP)
41198wr %g0, 0xe0, %asi
41199! preparing store val #0, next val will be in f32
41200fmovs %f16, %f20
41201fadds %f16, %f17, %f16
41202! preparing store val #1, next val will be in f33
41203fmovs %f16, %f21
41204fadds %f16, %f17, %f16
41205! preparing store val #2, next val will be in f35
41206fmovd %f20, %f32
41207fmovs %f16, %f21
41208fadds %f16, %f17, %f16
41209fmovd %f20, %f34
41210membar #Sync
41211stda %f32, [%i0 + 0 ] %asi
41212
41213P3696: !_MEMBAR (FP)
41214membar #StoreLoad
41215
41216P3697: !_LD [11] (Int)
41217lduw [%i3 + 12], %o3
41218! move %o3(lower) -> %o3(upper)
41219sllx %o3, 32, %o3
41220
41221P3698: !_LD [11] (Int)
41222lduw [%i3 + 12], %l3
41223! move %l3(lower) -> %o3(lower)
41224or %l3, %o3, %o3
41225
41226P3699: !_LD [19] (FP)
41227sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
41228sub %i0, %i2, %i2
41229ld [%i2 + 4], %f15
41230! 1 addresses covered
41231!---- flushing fp results buffer to %f30 ----
41232fmovd %f0, %f30
41233fmovd %f2, %f30
41234fmovd %f4, %f30
41235fmovd %f6, %f30
41236fmovd %f8, %f30
41237fmovd %f10, %f30
41238fmovd %f12, %f30
41239fmovd %f14, %f30
41240!--
41241
41242P3700: !_DWLD [0] (Int)
41243ldx [%i0 + 0], %o4
41244! move %o4(upper) -> %o4(upper)
41245! move %o4(lower) -> %o4(lower)
41246!---- flushing int results buffer----
41247mov %o0, %l5
41248mov %o1, %l5
41249mov %o2, %l5
41250mov %o3, %l5
41251mov %o4, %l5
41252
41253P3701: !_ST [12] (maybe <- 0x1800125) (Int)
41254sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
41255sub %i0, %i3, %i3
41256stw %l4, [%i3 + 0 ]
41257add %l4, 1, %l4
41258
41259P3702: !_DWST_BINIT [0] (maybe <- 0x1800126) (Int)
41260wr %g0, 0xe2, %asi
41261sllx %l4, 32, %l7
41262add %l4, 1, %l4
41263or %l7, %l4, %l7
41264stxa %l7, [%i0 + 0] %asi
41265add %l4, 1, %l4
41266
41267P3703: !_MEMBAR (Int)
41268membar #StoreLoad
41269
41270P3704: !_BLD [2] (FP)
41271wr %g0, 0xf0, %asi
41272ldda [%i0 + 0] %asi, %f0
41273membar #Sync
41274! 3 addresses covered
41275fmovs %f3, %f2
41276
41277P3705: !_MEMBAR (FP)
41278
41279P3706: !_DWST_BINIT [6] (maybe <- 0x1800128) (Int)
41280wr %g0, 0xe2, %asi
41281sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
41282add %i0, %i2, %i2
41283sllx %l4, 32, %l6
41284add %l4, 1, %l4
41285or %l6, %l4, %l6
41286stxa %l6, [%i2 + 0] %asi
41287add %l4, 1, %l4
41288
41289P3707: !_MEMBAR (Int)
41290membar #StoreLoad
41291
41292P3708: !_CASX [10] (maybe <- 0x180012a) (Int)
41293sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
41294sub %i0, %i3, %i3
41295ldx [%i3], %o0
41296! move %o0(upper) -> %o0(upper)
41297! move %o0(lower) -> %o0(lower)
41298mov %o0, %l3
41299sllx %l4, 32, %o1
41300add %l4, 1, %l4
41301or %l4, %o1, %o1
41302casx [%i3], %l3, %o1
41303! move %o1(upper) -> %o1(upper)
41304! move %o1(lower) -> %o1(lower)
41305add %l4, 1, %l4
41306
41307P3709: !_LD [22] (Int)
41308sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
41309sub %i0, %i2, %i2
41310lduw [%i2 + 4], %o2
41311! move %o2(lower) -> %o2(upper)
41312sllx %o2, 32, %o2
41313
41314P3710: !_MEMBAR (FP)
41315
41316P3711: !_BSTC [12] (maybe <- 0x410000a9) (FP)
41317wr %g0, 0xe0, %asi
41318sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
41319sub %i0, %i3, %i3
41320! preparing store val #0, next val will be in f32
41321fmovs %f16, %f20
41322fadds %f16, %f17, %f16
41323! preparing store val #1, next val will be in f33
41324fmovs %f16, %f21
41325fadds %f16, %f17, %f16
41326! preparing store val #2, next val will be in f35
41327fmovd %f20, %f32
41328fmovs %f16, %f21
41329fadds %f16, %f17, %f16
41330fmovd %f20, %f34
41331membar #Sync
41332stda %f32, [%i3 + 0 ] %asi
41333
41334P3712: !_MEMBAR (FP)
41335membar #StoreLoad
41336
41337P3713: !_BLD [8] (FP)
41338wr %g0, 0xf0, %asi
41339sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
41340add %i0, %i2, %i2
41341ldda [%i2 + 0] %asi, %f32
41342membar #Sync
41343! 3 addresses covered
41344fmovd %f32, %f18
41345fmovs %f18, %f3
41346fmovs %f19, %f4
41347fmovd %f34, %f18
41348fmovs %f19, %f5
41349
41350P3714: !_MEMBAR (FP) (CBR)
41351
41352! cbranch
41353andcc %l0, 1, %g0
41354be,pn %xcc, TARGET3714
41355nop
41356RET3714:
41357
41358! lfsr step begin
41359srlx %l0, 1, %l7
41360xnor %l7, %l0, %l7
41361sllx %l7, 63, %l7
41362or %l7, %l0, %l0
41363srlx %l0, 1, %l0
41364
41365
41366P3715: !_ST_BINIT [13] (maybe <- 0x180012c) (Int)
41367wr %g0, 0xe2, %asi
41368stwa %l4, [%i3 + 4] %asi
41369add %l4, 1, %l4
41370
41371P3716: !_MEMBAR (Int)
41372membar #StoreLoad
41373
41374P3717: !_PREFETCH [9] (Int)
41375sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
41376sub %i0, %i3, %i3
41377prefetch [%i3 + 0], 23
41378
41379P3718: !_CAS [13] (maybe <- 0x180012d) (Int)
41380sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
41381sub %i0, %i2, %i2
41382add %i2, 4, %o5
41383lduw [%o5], %l6
41384mov %l6, %l7
41385! move %l7(lower) -> %o2(lower)
41386or %l7, %o2, %o2
41387mov %l4, %o3
41388cas [%o5], %l7, %o3
41389! move %o3(lower) -> %o3(upper)
41390sllx %o3, 32, %o3
41391add %l4, 1, %l4
41392
41393P3719: !_DWST_BINIT [14] (maybe <- 0x180012e) (Int)
41394wr %g0, 0xe2, %asi
41395mov %l4, %l7
41396stxa %l7, [%i2 + 8] %asi
41397add %l4, 1, %l4
41398
41399P3720: !_MEMBAR (Int)
41400membar #StoreLoad
41401
41402P3721: !_REPLACEMENT [21] (Int) (Branch target of P3067)
41403sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
41404sub %i0, %i3, %i3
41405sethi %hi(0x20000), %l6
41406ld [%i3+0], %o5
41407st %o5, [%i3+0]
41408add %i3, %l6, %l7
41409ld [%l7+0], %o5
41410st %o5, [%l7+0]
41411add %l7, %l6, %l7
41412ld [%l7+0], %o5
41413st %o5, [%l7+0]
41414add %l7, %l6, %l7
41415ld [%l7+0], %o5
41416st %o5, [%l7+0]
41417add %l7, %l6, %l7
41418ld [%l7+0], %o5
41419st %o5, [%l7+0]
41420add %l7, %l6, %l7
41421ld [%l7+0], %o5
41422st %o5, [%l7+0]
41423add %l7, %l6, %l7
41424ld [%l7+0], %o5
41425st %o5, [%l7+0]
41426add %l7, %l6, %l7
41427ld [%l7+0], %o5
41428st %o5, [%l7+0]
41429ba P3722
41430nop
41431
41432TARGET3067:
41433ba RET3067
41434nop
41435
41436
41437P3722: !_ST_BINIT [13] (maybe <- 0x180012f) (Int)
41438wr %g0, 0xe2, %asi
41439stwa %l4, [%i2 + 4] %asi
41440add %l4, 1, %l4
41441
41442P3723: !_MEMBAR (Int)
41443membar #StoreLoad
41444
41445P3724: !_LD [3] (Int)
41446lduw [%i1 + 0], %l3
41447! move %l3(lower) -> %o3(lower)
41448or %l3, %o3, %o3
41449
41450P3725: !_CAS [23] (maybe <- 0x1800130) (Int)
41451sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
41452sub %i0, %i2, %i2
41453add %i2, 12, %l7
41454lduw [%l7], %o4
41455mov %o4, %l6
41456! move %l6(lower) -> %o4(upper)
41457sllx %l6, 32, %o4
41458mov %l4, %l3
41459cas [%l7], %l6, %l3
41460! move %l3(lower) -> %o4(lower)
41461srl %l3, 0, %l6
41462or %l6, %o4, %o4
41463!---- flushing int results buffer----
41464mov %o0, %l5
41465mov %o1, %l5
41466mov %o2, %l5
41467mov %o3, %l5
41468mov %o4, %l5
41469add %l4, 1, %l4
41470
41471P3726: !_MEMBAR (FP)
41472
41473P3727: !_BSTC [20] (maybe <- 0x410000ac) (FP)
41474wr %g0, 0xe0, %asi
41475sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
41476sub %i0, %i3, %i3
41477! preparing store val #0, next val will be in f32
41478fmovs %f16, %f20
41479fadds %f16, %f17, %f16
41480! preparing store val #1, next val will be in f33
41481fmovs %f16, %f21
41482fadds %f16, %f17, %f16
41483! preparing store val #2, next val will be in f35
41484fmovd %f20, %f32
41485fmovs %f16, %f21
41486fadds %f16, %f17, %f16
41487fmovd %f20, %f34
41488membar #Sync
41489stda %f32, [%i3 + 0 ] %asi
41490
41491P3728: !_MEMBAR (FP)
41492membar #StoreLoad
41493
41494P3729: !_LD [19] (Int)
41495lduw [%i3 + 4], %o0
41496! move %o0(lower) -> %o0(upper)
41497sllx %o0, 32, %o0
41498
41499P3730: !_PREFETCH [15] (Int)
41500sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
41501sub %i0, %i2, %i2
41502prefetch [%i2 + 0], 22
41503
41504P3731: !_CASX [12] (maybe <- 0x1800131) (Int) (Branch target of P3248)
41505sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
41506sub %i0, %i3, %i3
41507ldx [%i3], %l6
41508! move %l6(upper) -> %o0(lower)
41509srlx %l6, 32, %l7
41510or %l7, %o0, %o0
41511! move %l6(lower) -> %o1(upper)
41512sllx %l6, 32, %o1
41513mov %l6, %l7
41514sllx %l4, 32, %l6
41515add %l4, 1, %l4
41516or %l4, %l6, %l6
41517casx [%i3], %l7, %l6
41518! move %l6(upper) -> %o1(lower)
41519srlx %l6, 32, %l7
41520or %l7, %o1, %o1
41521! move %l6(lower) -> %o2(upper)
41522sllx %l6, 32, %o2
41523add %l4, 1, %l4
41524ba P3732
41525nop
41526
41527TARGET3248:
41528ba RET3248
41529nop
41530
41531
41532P3732: !_DWST_BINIT [15] (maybe <- 0x1800133) (Int) (Branch target of P3658)
41533wr %g0, 0xe2, %asi
41534sllx %l4, 32, %l7
41535add %l4, 1, %l4
41536or %l7, %l4, %l7
41537stxa %l7, [%i2 + 0] %asi
41538add %l4, 1, %l4
41539ba P3733
41540nop
41541
41542TARGET3658:
41543ba RET3658
41544nop
41545
41546
41547P3733: !_MEMBAR (Int)
41548membar #StoreLoad
41549
41550P3734: !_SWAP [15] (maybe <- 0x1800135) (Int)
41551mov %l4, %o5
41552swap [%i2 + 0], %o5
41553! move %o5(lower) -> %o2(lower)
41554srl %o5, 0, %l6
41555or %l6, %o2, %o2
41556add %l4, 1, %l4
41557
41558P3735: !_CASX [7] (maybe <- 0x1800136) (Int)
41559sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
41560add %i0, %i2, %i2
41561ldx [%i2], %o3
41562! move %o3(upper) -> %o3(upper)
41563! move %o3(lower) -> %o3(lower)
41564mov %o3, %l3
41565sllx %l4, 32, %o4
41566add %l4, 1, %l4
41567or %l4, %o4, %o4
41568casx [%i2], %l3, %o4
41569! move %o4(upper) -> %o4(upper)
41570! move %o4(lower) -> %o4(lower)
41571!---- flushing int results buffer----
41572mov %o0, %l5
41573mov %o1, %l5
41574mov %o2, %l5
41575mov %o3, %l5
41576mov %o4, %l5
41577add %l4, 1, %l4
41578
41579P3736: !_LD [16] (Int)
41580sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
41581sub %i0, %i3, %i3
41582lduw [%i3 + 4], %o0
41583! move %o0(lower) -> %o0(upper)
41584sllx %o0, 32, %o0
41585
41586P3737: !_SWAP [3] (maybe <- 0x1800138) (Int)
41587mov %l4, %l3
41588swap [%i1 + 0], %l3
41589! move %l3(lower) -> %o0(lower)
41590srl %l3, 0, %l7
41591or %l7, %o0, %o0
41592add %l4, 1, %l4
41593
41594P3738: !_DWST_BINIT [11] (maybe <- 0x1800139) (Int)
41595wr %g0, 0xe2, %asi
41596sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
41597sub %i0, %i2, %i2
41598mov %l4, %l6
41599stxa %l6, [%i2 + 8] %asi
41600add %l4, 1, %l4
41601
41602P3739: !_MEMBAR (Int)
41603membar #StoreLoad
41604
41605P3740: !_BLD [10] (FP)
41606wr %g0, 0xf0, %asi
41607ldda [%i2 + 0] %asi, %f32
41608membar #Sync
41609! 3 addresses covered
41610fmovd %f32, %f6
41611fmovd %f34, %f18
41612fmovs %f19, %f8
41613
41614P3741: !_MEMBAR (FP)
41615
41616P3742: !_BLD [0] (FP) (CBR)
41617wr %g0, 0xf0, %asi
41618ldda [%i0 + 0] %asi, %f32
41619membar #Sync
41620! 3 addresses covered
41621fmovd %f32, %f18
41622fmovs %f18, %f9
41623fmovs %f19, %f10
41624fmovd %f34, %f18
41625fmovs %f19, %f11
41626
41627! cbranch
41628andcc %l0, 1, %g0
41629be,pn %xcc, TARGET3742
41630nop
41631RET3742:
41632
41633! lfsr step begin
41634srlx %l0, 1, %l3
41635xnor %l3, %l0, %l3
41636sllx %l3, 63, %l3
41637or %l3, %l0, %l0
41638srlx %l0, 1, %l0
41639
41640
41641P3743: !_MEMBAR (FP)
41642
41643P3744: !_LDD [19] (Int)
41644sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
41645sub %i0, %i3, %i3
41646ldd [%i3 + 0], %l6
41647! move %l6(lower) -> %o1(upper)
41648sllx %l6, 32, %o1
41649! move %l7(lower) -> %o1(lower)
41650or %l7, %o1, %o1
41651
41652P3745: !_DWST_BINIT [14] (maybe <- 0x180013a) (Int)
41653wr %g0, 0xe2, %asi
41654sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
41655sub %i0, %i2, %i2
41656mov %l4, %l3
41657stxa %l3, [%i2 + 8] %asi
41658add %l4, 1, %l4
41659
41660P3746: !_MEMBAR (Int)
41661
41662P3747: !_BSTC [12] (maybe <- 0x410000af) (FP)
41663wr %g0, 0xe0, %asi
41664! preparing store val #0, next val will be in f32
41665fmovs %f16, %f20
41666fadds %f16, %f17, %f16
41667! preparing store val #1, next val will be in f33
41668fmovs %f16, %f21
41669fadds %f16, %f17, %f16
41670! preparing store val #2, next val will be in f35
41671fmovd %f20, %f32
41672fmovs %f16, %f21
41673fadds %f16, %f17, %f16
41674fmovd %f20, %f34
41675membar #Sync
41676stda %f32, [%i2 + 0 ] %asi
41677
41678P3748: !_MEMBAR (FP)
41679membar #StoreLoad
41680
41681P3749: !_DWLD [20] (Int)
41682ldx [%i3 + 8], %o2
41683! move %o2(lower) -> %o2(upper)
41684sllx %o2, 32, %o2
41685
41686P3750: !_ST_BINIT [7] (maybe <- 0x180013b) (Int)
41687wr %g0, 0xe2, %asi
41688sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
41689add %i0, %i3, %i3
41690stwa %l4, [%i3 + 4] %asi
41691add %l4, 1, %l4
41692
41693P3751: !_MEMBAR (Int)
41694membar #StoreLoad
41695
41696P3752: !_BLD [12] (FP)
41697wr %g0, 0xf0, %asi
41698ldda [%i2 + 0] %asi, %f32
41699membar #Sync
41700! 3 addresses covered
41701fmovd %f32, %f12
41702fmovd %f34, %f18
41703fmovs %f19, %f14
41704
41705P3753: !_MEMBAR (FP) (CBR)
41706
41707! cbranch
41708andcc %l0, 1, %g0
41709be,pn %xcc, TARGET3753
41710nop
41711RET3753:
41712
41713! lfsr step begin
41714srlx %l0, 1, %o5
41715xnor %o5, %l0, %o5
41716sllx %o5, 63, %o5
41717or %o5, %l0, %l0
41718srlx %l0, 1, %l0
41719
41720
41721P3754: !_LD [7] (Int)
41722lduw [%i3 + 4], %l6
41723! move %l6(lower) -> %o2(lower)
41724or %l6, %o2, %o2
41725
41726P3755: !_PREFETCH [13] (Int)
41727prefetch [%i2 + 4], 1
41728
41729P3756: !_LDD [17] (Int)
41730sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
41731sub %i0, %i2, %i2
41732ldd [%i2 + 8], %l6
41733! move %l7(lower) -> %o3(upper)
41734sllx %l7, 32, %o3
41735
41736P3757: !_REPLACEMENT [13] (Int)
41737sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
41738sub %i0, %i3, %i3
41739sethi %hi(0x20000), %l3
41740ld [%i3+4], %l7
41741st %l7, [%i3+4]
41742add %i3, %l3, %l6
41743ld [%l6+4], %l7
41744st %l7, [%l6+4]
41745add %l6, %l3, %l6
41746ld [%l6+4], %l7
41747st %l7, [%l6+4]
41748add %l6, %l3, %l6
41749ld [%l6+4], %l7
41750st %l7, [%l6+4]
41751add %l6, %l3, %l6
41752ld [%l6+4], %l7
41753st %l7, [%l6+4]
41754add %l6, %l3, %l6
41755ld [%l6+4], %l7
41756st %l7, [%l6+4]
41757add %l6, %l3, %l6
41758ld [%l6+4], %l7
41759st %l7, [%l6+4]
41760add %l6, %l3, %l6
41761ld [%l6+4], %l7
41762st %l7, [%l6+4]
41763
41764P3758: !_REPLACEMENT [5] (Int)
41765sethi %hi(0x20000), %o5
41766ld [%i3+12], %l6
41767st %l6, [%i3+12]
41768add %i3, %o5, %l3
41769ld [%l3+12], %l6
41770st %l6, [%l3+12]
41771add %l3, %o5, %l3
41772ld [%l3+12], %l6
41773st %l6, [%l3+12]
41774add %l3, %o5, %l3
41775ld [%l3+12], %l6
41776st %l6, [%l3+12]
41777add %l3, %o5, %l3
41778ld [%l3+12], %l6
41779st %l6, [%l3+12]
41780add %l3, %o5, %l3
41781ld [%l3+12], %l6
41782st %l6, [%l3+12]
41783add %l3, %o5, %l3
41784ld [%l3+12], %l6
41785st %l6, [%l3+12]
41786add %l3, %o5, %l3
41787ld [%l3+12], %l6
41788st %l6, [%l3+12]
41789
41790P3759: !_MEMBAR (FP)
41791membar #StoreLoad
41792
41793P3760: !_BLD [6] (FP)
41794wr %g0, 0xf0, %asi
41795sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
41796add %i0, %i2, %i2
41797ldda [%i2 + 0] %asi, %f32
41798membar #Sync
41799! 3 addresses covered
41800fmovd %f32, %f18
41801fmovs %f18, %f15
41802!---- flushing fp results buffer to %f30 ----
41803fmovd %f0, %f30
41804fmovd %f2, %f30
41805fmovd %f4, %f30
41806fmovd %f6, %f30
41807fmovd %f8, %f30
41808fmovd %f10, %f30
41809fmovd %f12, %f30
41810fmovd %f14, %f30
41811!--
41812fmovs %f19, %f0
41813fmovd %f34, %f18
41814fmovs %f19, %f1
41815
41816P3761: !_MEMBAR (FP)
41817
41818P3762: !_DWST [14] (maybe <- 0x180013c) (Int)
41819sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
41820sub %i0, %i3, %i3
41821mov %l4, %l7
41822stx %l7, [%i3 + 8]
41823add %l4, 1, %l4
41824
41825P3763: !_MEMBAR (FP)
41826membar #StoreLoad
41827
41828P3764: !_BLD [15] (FP)
41829wr %g0, 0xf0, %asi
41830sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
41831sub %i0, %i2, %i2
41832ldda [%i2 + 0] %asi, %f32
41833membar #Sync
41834! 3 addresses covered
41835fmovd %f32, %f2
41836fmovd %f34, %f18
41837fmovs %f19, %f4
41838
41839P3765: !_MEMBAR (FP)
41840
41841P3766: !_REPLACEMENT [21] (Int)
41842sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
41843sub %i0, %i3, %i3
41844sethi %hi(0x20000), %l6
41845ld [%i3+0], %o5
41846st %o5, [%i3+0]
41847add %i3, %l6, %l7
41848ld [%l7+0], %o5
41849st %o5, [%l7+0]
41850add %l7, %l6, %l7
41851ld [%l7+0], %o5
41852st %o5, [%l7+0]
41853add %l7, %l6, %l7
41854ld [%l7+0], %o5
41855st %o5, [%l7+0]
41856add %l7, %l6, %l7
41857ld [%l7+0], %o5
41858st %o5, [%l7+0]
41859add %l7, %l6, %l7
41860ld [%l7+0], %o5
41861st %o5, [%l7+0]
41862add %l7, %l6, %l7
41863ld [%l7+0], %o5
41864st %o5, [%l7+0]
41865add %l7, %l6, %l7
41866ld [%l7+0], %o5
41867st %o5, [%l7+0]
41868
41869P3767: !_DWST [5] (maybe <- 0x180013d) (Int)
41870mov %l4, %l3
41871stx %l3, [%i1 + 8]
41872add %l4, 1, %l4
41873
41874P3768: !_SWAP [1] (maybe <- 0x180013e) (Int)
41875mov %l4, %l6
41876swap [%i0 + 4], %l6
41877! move %l6(lower) -> %o3(lower)
41878srl %l6, 0, %o5
41879or %o5, %o3, %o3
41880add %l4, 1, %l4
41881
41882P3769: !_MEMBAR (FP)
41883
41884P3770: !_BSTC [18] (maybe <- 0x410000b2) (FP)
41885wr %g0, 0xe0, %asi
41886sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
41887sub %i0, %i2, %i2
41888! preparing store val #0, next val will be in f32
41889fmovs %f16, %f20
41890fadds %f16, %f17, %f16
41891! preparing store val #1, next val will be in f33
41892fmovs %f16, %f21
41893fadds %f16, %f17, %f16
41894! preparing store val #2, next val will be in f35
41895fmovd %f20, %f32
41896fmovs %f16, %f21
41897fadds %f16, %f17, %f16
41898fmovd %f20, %f34
41899membar #Sync
41900stda %f32, [%i2 + 0 ] %asi
41901
41902P3771: !_MEMBAR (FP)
41903
41904P3772: !_BSTC [16] (maybe <- 0x410000b5) (FP)
41905wr %g0, 0xe0, %asi
41906sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
41907sub %i0, %i3, %i3
41908! preparing store val #0, next val will be in f32
41909fmovs %f16, %f20
41910fadds %f16, %f17, %f16
41911! preparing store val #1, next val will be in f33
41912fmovs %f16, %f21
41913fadds %f16, %f17, %f16
41914! preparing store val #2, next val will be in f35
41915fmovd %f20, %f32
41916fmovs %f16, %f21
41917fadds %f16, %f17, %f16
41918fmovd %f20, %f34
41919membar #Sync
41920stda %f32, [%i3 + 0 ] %asi
41921
41922P3773: !_MEMBAR (FP)
41923membar #StoreLoad
41924
41925P3774: !_ST_BINIT [11] (maybe <- 0x180013f) (Int)
41926wr %g0, 0xe2, %asi
41927sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
41928sub %i0, %i2, %i2
41929stwa %l4, [%i2 + 12] %asi
41930add %l4, 1, %l4
41931
41932P3775: !_MEMBAR (Int)
41933membar #StoreLoad
41934
41935P3776: !_ST_BINIT [7] (maybe <- 0x1800140) (Int)
41936wr %g0, 0xe2, %asi
41937sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
41938add %i0, %i3, %i3
41939stwa %l4, [%i3 + 4] %asi
41940add %l4, 1, %l4
41941
41942P3777: !_MEMBAR (Int)
41943membar #StoreLoad
41944
41945P3778: !_BLD [9] (FP)
41946wr %g0, 0xf0, %asi
41947ldda [%i2 + 0] %asi, %f32
41948membar #Sync
41949! 3 addresses covered
41950fmovd %f32, %f18
41951fmovs %f18, %f5
41952fmovs %f19, %f6
41953fmovd %f34, %f18
41954fmovs %f19, %f7
41955
41956P3779: !_MEMBAR (FP)
41957
41958P3780: !_LDD [6] (Int)
41959ldd [%i3 + 0], %l6
41960! move %l6(lower) -> %o4(upper)
41961sllx %l6, 32, %o4
41962! move %l7(lower) -> %o4(lower)
41963or %l7, %o4, %o4
41964!---- flushing int results buffer----
41965mov %o0, %l5
41966mov %o1, %l5
41967mov %o2, %l5
41968mov %o3, %l5
41969mov %o4, %l5
41970
41971P3781: !_DWST [5] (maybe <- 0x1800141) (Int)
41972mov %l4, %l3
41973stx %l3, [%i1 + 8]
41974add %l4, 1, %l4
41975
41976P3782: !_MEMBAR (FP)
41977membar #StoreLoad
41978
41979P3783: !_BLD [17] (FP)
41980wr %g0, 0xf0, %asi
41981sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
41982sub %i0, %i2, %i2
41983ldda [%i2 + 0] %asi, %f32
41984membar #Sync
41985! 3 addresses covered
41986fmovd %f32, %f8
41987fmovd %f34, %f18
41988fmovs %f19, %f10
41989
41990P3784: !_MEMBAR (FP)
41991
41992P3785: !_ST_BINIT [4] (maybe <- 0x1800142) (Int) (LE)
41993wr %g0, 0xea, %asi
41994! Change single-word-level endianess (big endian <-> little endian)
41995sethi %hi(0xff00ff00), %l3
41996or %l3, %lo(0xff00ff00), %l3
41997and %l4, %l3, %l6
41998srl %l6, 8, %l6
41999sll %l4, 8, %o5
42000and %o5, %l3, %o5
42001or %o5, %l6, %o5
42002srl %o5, 16, %l6
42003sll %o5, 16, %o5
42004srl %o5, 0, %o5
42005or %o5, %l6, %o5
42006stwa %o5, [%i1 + 4] %asi
42007add %l4, 1, %l4
42008
42009P3786: !_MEMBAR (Int) (LE)
42010membar #StoreLoad
42011
42012P3787: !_PREFETCH [13] (Int)
42013sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
42014sub %i0, %i3, %i3
42015prefetch [%i3 + 4], 1
42016
42017P3788: !_SWAP [17] (maybe <- 0x1800143) (Int)
42018mov %l4, %o0
42019swap [%i2 + 12], %o0
42020! move %o0(lower) -> %o0(upper)
42021sllx %o0, 32, %o0
42022add %l4, 1, %l4
42023
42024P3789: !_DWLD [7] (Int)
42025sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
42026add %i0, %i2, %i2
42027ldx [%i2 + 0], %l7
42028! move %l7(upper) -> %o0(lower)
42029srlx %l7, 32, %l6
42030or %l6, %o0, %o0
42031! move %l7(lower) -> %o1(upper)
42032sllx %l7, 32, %o1
42033
42034P3790: !_LDD [0] (Int)
42035ldd [%i0 + 0], %l6
42036! move %l6(lower) -> %o1(lower)
42037or %l6, %o1, %o1
42038! move %l7(lower) -> %o2(upper)
42039sllx %l7, 32, %o2
42040
42041P3791: !_LD [12] (Int)
42042lduw [%i3 + 0], %l6
42043! move %l6(lower) -> %o2(lower)
42044or %l6, %o2, %o2
42045
42046P3792: !_DWLD [3] (Int) (CBR)
42047ldx [%i1 + 0], %o3
42048! move %o3(upper) -> %o3(upper)
42049! move %o3(lower) -> %o3(lower)
42050
42051! cbranch
42052andcc %l0, 1, %g0
42053be,pn %xcc, TARGET3792
42054nop
42055RET3792:
42056
42057! lfsr step begin
42058srlx %l0, 1, %l3
42059xnor %l3, %l0, %l3
42060sllx %l3, 63, %l3
42061or %l3, %l0, %l0
42062srlx %l0, 1, %l0
42063
42064
42065P3793: !_DWLD [4] (Int)
42066ldx [%i1 + 0], %o4
42067! move %o4(upper) -> %o4(upper)
42068! move %o4(lower) -> %o4(lower)
42069!---- flushing int results buffer----
42070mov %o0, %l5
42071mov %o1, %l5
42072mov %o2, %l5
42073mov %o3, %l5
42074mov %o4, %l5
42075
42076P3794: !_CAS [17] (maybe <- 0x1800144) (Int)
42077sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
42078sub %i0, %i3, %i3
42079add %i3, 12, %l3
42080lduw [%l3], %o0
42081mov %o0, %o5
42082! move %o5(lower) -> %o0(upper)
42083sllx %o5, 32, %o0
42084mov %l4, %l7
42085cas [%l3], %o5, %l7
42086! move %l7(lower) -> %o0(lower)
42087srl %l7, 0, %o5
42088or %o5, %o0, %o0
42089add %l4, 1, %l4
42090
42091P3795: !_CASX [0] (maybe <- 0x1800145) (Int)
42092ldx [%i0], %o1
42093! move %o1(upper) -> %o1(upper)
42094! move %o1(lower) -> %o1(lower)
42095mov %o1, %o5
42096sllx %l4, 32, %o2
42097add %l4, 1, %l4
42098or %l4, %o2, %o2
42099casx [%i0], %o5, %o2
42100! move %o2(upper) -> %o2(upper)
42101! move %o2(lower) -> %o2(lower)
42102add %l4, 1, %l4
42103
42104P3796: !_MEMBAR (FP)
42105
42106P3797: !_BSTC [18] (maybe <- 0x410000b8) (FP)
42107wr %g0, 0xe0, %asi
42108sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
42109sub %i0, %i2, %i2
42110! preparing store val #0, next val will be in f32
42111fmovs %f16, %f20
42112fadds %f16, %f17, %f16
42113! preparing store val #1, next val will be in f33
42114fmovs %f16, %f21
42115fadds %f16, %f17, %f16
42116! preparing store val #2, next val will be in f35
42117fmovd %f20, %f32
42118fmovs %f16, %f21
42119fadds %f16, %f17, %f16
42120fmovd %f20, %f34
42121membar #Sync
42122stda %f32, [%i2 + 0 ] %asi
42123
42124P3798: !_MEMBAR (FP)
42125
42126P3799: !_BST [5] (maybe <- 0x410000bb) (FP)
42127wr %g0, 0xf0, %asi
42128! preparing store val #0, next val will be in f32
42129fmovs %f16, %f20
42130fadds %f16, %f17, %f16
42131! preparing store val #1, next val will be in f33
42132fmovs %f16, %f21
42133fadds %f16, %f17, %f16
42134! preparing store val #2, next val will be in f35
42135fmovd %f20, %f32
42136fmovs %f16, %f21
42137fadds %f16, %f17, %f16
42138fmovd %f20, %f34
42139membar #Sync
42140stda %f32, [%i1 + 0 ] %asi
42141
42142P3800: !_MEMBAR (FP)
42143membar #StoreLoad
42144
42145P3801: !_ST_BINIT [17] (maybe <- 0x1800147) (Int)
42146wr %g0, 0xe2, %asi
42147stwa %l4, [%i3 + 12] %asi
42148add %l4, 1, %l4
42149
42150P3802: !_MEMBAR (Int)
42151membar #StoreLoad
42152
42153P3803: !_DWST_BINIT [8] (maybe <- 0x1800148) (Int)
42154wr %g0, 0xe2, %asi
42155sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
42156add %i0, %i3, %i3
42157mov %l4, %l3
42158stxa %l3, [%i3 + 8] %asi
42159add %l4, 1, %l4
42160
42161P3804: !_MEMBAR (Int)
42162membar #StoreLoad
42163
42164P3805: !_ST_BINIT [6] (maybe <- 0x1800149) (Int)
42165wr %g0, 0xe2, %asi
42166stwa %l4, [%i3 + 0] %asi
42167add %l4, 1, %l4
42168
42169P3806: !_MEMBAR (Int)
42170membar #StoreLoad
42171
42172P3807: !_LDD [0] (Int)
42173ldd [%i0 + 0], %l6
42174! move %l6(lower) -> %o3(upper)
42175sllx %l6, 32, %o3
42176! move %l7(lower) -> %o3(lower)
42177or %l7, %o3, %o3
42178
42179P3808: !_DWST_BINIT [18] (maybe <- 0x180014a) (Int)
42180wr %g0, 0xe2, %asi
42181sllx %l4, 32, %l3
42182add %l4, 1, %l4
42183or %l3, %l4, %l3
42184stxa %l3, [%i2 + 0] %asi
42185add %l4, 1, %l4
42186
42187P3809: !_MEMBAR (Int)
42188
42189P3810: !_BSTC [17] (maybe <- 0x410000be) (FP) (CBR)
42190wr %g0, 0xe0, %asi
42191sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
42192sub %i0, %i2, %i2
42193! preparing store val #0, next val will be in f32
42194fmovs %f16, %f20
42195fadds %f16, %f17, %f16
42196! preparing store val #1, next val will be in f33
42197fmovs %f16, %f21
42198fadds %f16, %f17, %f16
42199! preparing store val #2, next val will be in f35
42200fmovd %f20, %f32
42201fmovs %f16, %f21
42202fadds %f16, %f17, %f16
42203fmovd %f20, %f34
42204membar #Sync
42205stda %f32, [%i2 + 0 ] %asi
42206
42207! cbranch
42208andcc %l0, 1, %g0
42209be,pt %xcc, TARGET3810
42210nop
42211RET3810:
42212
42213! lfsr step begin
42214srlx %l0, 1, %l7
42215xnor %l7, %l0, %l7
42216sllx %l7, 63, %l7
42217or %l7, %l0, %l0
42218srlx %l0, 1, %l0
42219
42220
42221P3811: !_MEMBAR (FP)
42222membar #StoreLoad
42223
42224P3812: !_ST [20] (maybe <- 0x180014c) (Int)
42225sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
42226sub %i0, %i3, %i3
42227stw %l4, [%i3 + 12 ]
42228add %l4, 1, %l4
42229
42230P3813: !_MEMBAR (FP)
42231
42232P3814: !_BSTC [18] (maybe <- 0x410000c1) (FP)
42233wr %g0, 0xe0, %asi
42234! preparing store val #0, next val will be in f32
42235fmovs %f16, %f20
42236fadds %f16, %f17, %f16
42237! preparing store val #1, next val will be in f33
42238fmovs %f16, %f21
42239fadds %f16, %f17, %f16
42240! preparing store val #2, next val will be in f35
42241fmovd %f20, %f32
42242fmovs %f16, %f21
42243fadds %f16, %f17, %f16
42244fmovd %f20, %f34
42245membar #Sync
42246stda %f32, [%i3 + 0 ] %asi
42247
42248P3815: !_MEMBAR (FP)
42249membar #StoreLoad
42250
42251P3816: !_LD [14] (Int)
42252sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
42253sub %i0, %i2, %i2
42254lduw [%i2 + 12], %o4
42255! move %o4(lower) -> %o4(upper)
42256sllx %o4, 32, %o4
42257
42258P3817: !_CAS [5] (maybe <- 0x180014d) (Int)
42259add %i1, 12, %l3
42260lduw [%l3], %l7
42261mov %l7, %o5
42262! move %o5(lower) -> %o4(lower)
42263or %o5, %o4, %o4
42264!---- flushing int results buffer----
42265mov %o0, %l5
42266mov %o1, %l5
42267mov %o2, %l5
42268mov %o3, %l5
42269mov %o4, %l5
42270mov %l4, %o0
42271cas [%l3], %o5, %o0
42272! move %o0(lower) -> %o0(upper)
42273sllx %o0, 32, %o0
42274add %l4, 1, %l4
42275
42276P3818: !_CAS [6] (maybe <- 0x180014e) (Int)
42277sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
42278add %i0, %i3, %i3
42279lduw [%i3], %l7
42280mov %l7, %o5
42281! move %o5(lower) -> %o0(lower)
42282or %o5, %o0, %o0
42283mov %l4, %o1
42284cas [%i3], %o5, %o1
42285! move %o1(lower) -> %o1(upper)
42286sllx %o1, 32, %o1
42287add %l4, 1, %l4
42288
42289P3819: !_MEMBAR (FP)
42290
42291P3820: !_BSTC [20] (maybe <- 0x410000c4) (FP)
42292wr %g0, 0xe0, %asi
42293sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
42294sub %i0, %i2, %i2
42295! preparing store val #0, next val will be in f32
42296fmovs %f16, %f20
42297fadds %f16, %f17, %f16
42298! preparing store val #1, next val will be in f33
42299fmovs %f16, %f21
42300fadds %f16, %f17, %f16
42301! preparing store val #2, next val will be in f35
42302fmovd %f20, %f32
42303fmovs %f16, %f21
42304fadds %f16, %f17, %f16
42305fmovd %f20, %f34
42306membar #Sync
42307stda %f32, [%i2 + 0 ] %asi
42308
42309P3821: !_MEMBAR (FP)
42310membar #StoreLoad
42311
42312P3822: !_DWLD [16] (Int)
42313sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
42314sub %i0, %i3, %i3
42315ldx [%i3 + 0], %o5
42316! move %o5(upper) -> %o1(lower)
42317srlx %o5, 32, %l7
42318or %l7, %o1, %o1
42319! move %o5(lower) -> %o2(upper)
42320sllx %o5, 32, %o2
42321
42322P3823: !_LDD [1] (Int)
42323ldd [%i0 + 0], %l6
42324! move %l6(lower) -> %o2(lower)
42325or %l6, %o2, %o2
42326! move %l7(lower) -> %o3(upper)
42327sllx %l7, 32, %o3
42328
42329P3824: !_MEMBAR (FP)
42330
42331P3825: !_BST [9] (maybe <- 0x410000c7) (FP)
42332wr %g0, 0xf0, %asi
42333sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
42334sub %i0, %i2, %i2
42335! preparing store val #0, next val will be in f32
42336fmovs %f16, %f20
42337fadds %f16, %f17, %f16
42338! preparing store val #1, next val will be in f33
42339fmovs %f16, %f21
42340fadds %f16, %f17, %f16
42341! preparing store val #2, next val will be in f35
42342fmovd %f20, %f32
42343fmovs %f16, %f21
42344fadds %f16, %f17, %f16
42345fmovd %f20, %f34
42346membar #Sync
42347stda %f32, [%i2 + 0 ] %asi
42348
42349P3826: !_MEMBAR (FP)
42350membar #StoreLoad
42351
42352P3827: !_PREFETCH [2] (Int)
42353prefetch [%i0 + 12], 18
42354
42355P3828: !_DWST_BINIT [1] (maybe <- 0x180014f) (Int)
42356wr %g0, 0xe2, %asi
42357sllx %l4, 32, %o5
42358add %l4, 1, %l4
42359or %o5, %l4, %o5
42360stxa %o5, [%i0 + 0] %asi
42361add %l4, 1, %l4
42362
42363P3829: !_MEMBAR (Int)
42364
42365P3830: !_BST [21] (maybe <- 0x410000ca) (FP)
42366wr %g0, 0xf0, %asi
42367sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
42368sub %i0, %i3, %i3
42369! preparing store val #0, next val will be in f32
42370fmovs %f16, %f20
42371fadds %f16, %f17, %f16
42372! preparing store val #1, next val will be in f33
42373fmovs %f16, %f21
42374fadds %f16, %f17, %f16
42375! preparing store val #2, next val will be in f35
42376fmovd %f20, %f32
42377fmovs %f16, %f21
42378fadds %f16, %f17, %f16
42379fmovd %f20, %f34
42380membar #Sync
42381stda %f32, [%i3 + 0 ] %asi
42382
42383P3831: !_MEMBAR (FP)
42384membar #StoreLoad
42385
42386P3832: !_DWST_BINIT [7] (maybe <- 0x1800151) (Int)
42387wr %g0, 0xe2, %asi
42388sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
42389add %i0, %i2, %i2
42390sllx %l4, 32, %l6
42391add %l4, 1, %l4
42392or %l6, %l4, %l6
42393stxa %l6, [%i2 + 0] %asi
42394add %l4, 1, %l4
42395
42396P3833: !_MEMBAR (Int)
42397membar #StoreLoad
42398
42399P3834: !_CASX [3] (maybe <- 0x1800153) (Int)
42400ldx [%i1], %o5
42401! move %o5(upper) -> %o3(lower)
42402srlx %o5, 32, %l3
42403or %l3, %o3, %o3
42404! move %o5(lower) -> %o4(upper)
42405sllx %o5, 32, %o4
42406mov %o5, %l3
42407sllx %l4, 32, %o5
42408add %l4, 1, %l4
42409or %l4, %o5, %o5
42410casx [%i1], %l3, %o5
42411! move %o5(upper) -> %o4(lower)
42412srlx %o5, 32, %l3
42413or %l3, %o4, %o4
42414!---- flushing int results buffer----
42415mov %o0, %l5
42416mov %o1, %l5
42417mov %o2, %l5
42418mov %o3, %l5
42419mov %o4, %l5
42420! move %o5(lower) -> %o0(upper)
42421sllx %o5, 32, %o0
42422add %l4, 1, %l4
42423
42424P3835: !_ST_BINIT [3] (maybe <- 0x1800155) (Int)
42425wr %g0, 0xe2, %asi
42426stwa %l4, [%i1 + 0] %asi
42427add %l4, 1, %l4
42428
42429P3836: !_MEMBAR (Int)
42430
42431P3837: !_BST [23] (maybe <- 0x410000cd) (FP) (Branch target of P3301)
42432wr %g0, 0xf0, %asi
42433sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
42434sub %i0, %i3, %i3
42435! preparing store val #0, next val will be in f32
42436fmovs %f16, %f20
42437fadds %f16, %f17, %f16
42438! preparing store val #1, next val will be in f33
42439fmovs %f16, %f21
42440fadds %f16, %f17, %f16
42441! preparing store val #2, next val will be in f35
42442fmovd %f20, %f32
42443fmovs %f16, %f21
42444fadds %f16, %f17, %f16
42445fmovd %f20, %f34
42446membar #Sync
42447stda %f32, [%i3 + 0 ] %asi
42448ba P3838
42449nop
42450
42451TARGET3301:
42452ba RET3301
42453nop
42454
42455
42456P3838: !_MEMBAR (FP)
42457membar #StoreLoad
42458
42459P3839: !_DWST [3] (maybe <- 0x1800156) (Int)
42460sllx %l4, 32, %o5
42461add %l4, 1, %l4
42462or %o5, %l4, %o5
42463stx %o5, [%i1 + 0]
42464add %l4, 1, %l4
42465
42466P3840: !_LDD [6] (Int)
42467ldd [%i2 + 0], %l6
42468! move %l6(lower) -> %o0(lower)
42469or %l6, %o0, %o0
42470! move %l7(lower) -> %o1(upper)
42471sllx %l7, 32, %o1
42472
42473P3841: !_DWST [11] (maybe <- 0x1800158) (Int)
42474sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
42475sub %i0, %i2, %i2
42476mov %l4, %l3
42477stx %l3, [%i2 + 8]
42478add %l4, 1, %l4
42479
42480P3842: !_MEMBAR (FP) (Branch target of P3035)
42481ba P3843
42482nop
42483
42484TARGET3035:
42485ba RET3035
42486nop
42487
42488
42489P3843: !_BSTC [22] (maybe <- 0x410000d0) (FP)
42490wr %g0, 0xe0, %asi
42491! preparing store val #0, next val will be in f32
42492fmovs %f16, %f20
42493fadds %f16, %f17, %f16
42494! preparing store val #1, next val will be in f33
42495fmovs %f16, %f21
42496fadds %f16, %f17, %f16
42497! preparing store val #2, next val will be in f35
42498fmovd %f20, %f32
42499fmovs %f16, %f21
42500fadds %f16, %f17, %f16
42501fmovd %f20, %f34
42502membar #Sync
42503stda %f32, [%i3 + 0 ] %asi
42504
42505P3844: !_MEMBAR (FP)
42506membar #StoreLoad
42507
42508P3845: !_BLD [9] (FP)
42509wr %g0, 0xf0, %asi
42510ldda [%i2 + 0] %asi, %f32
42511membar #Sync
42512! 3 addresses covered
42513fmovd %f32, %f18
42514fmovs %f18, %f11
42515fmovs %f19, %f12
42516fmovd %f34, %f18
42517fmovs %f19, %f13
42518
42519P3846: !_MEMBAR (FP)
42520
42521P3847: !_BLD [14] (FP)
42522wr %g0, 0xf0, %asi
42523sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
42524sub %i0, %i3, %i3
42525ldda [%i3 + 0] %asi, %f32
42526membar #Sync
42527! 3 addresses covered
42528fmovd %f32, %f14
42529!---- flushing fp results buffer to %f30 ----
42530fmovd %f0, %f30
42531fmovd %f2, %f30
42532fmovd %f4, %f30
42533fmovd %f6, %f30
42534fmovd %f8, %f30
42535fmovd %f10, %f30
42536fmovd %f12, %f30
42537fmovd %f14, %f30
42538!--
42539fmovd %f34, %f18
42540fmovs %f19, %f0
42541
42542P3848: !_MEMBAR (FP)
42543
42544P3849: !_ST_BINIT [8] (maybe <- 0x1800159) (Int)
42545wr %g0, 0xe2, %asi
42546sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
42547add %i0, %i2, %i2
42548stwa %l4, [%i2 + 12] %asi
42549add %l4, 1, %l4
42550
42551P3850: !_MEMBAR (Int)
42552membar #StoreLoad
42553
42554P3851: !_DWST [19] (maybe <- 0x180015a) (Int)
42555sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
42556sub %i0, %i3, %i3
42557sllx %l4, 32, %l6
42558add %l4, 1, %l4
42559or %l6, %l4, %l6
42560stx %l6, [%i3 + 0]
42561add %l4, 1, %l4
42562
42563P3852: !_CASX [1] (maybe <- 0x180015c) (Int)
42564ldx [%i0], %o5
42565! move %o5(upper) -> %o1(lower)
42566srlx %o5, 32, %l3
42567or %l3, %o1, %o1
42568! move %o5(lower) -> %o2(upper)
42569sllx %o5, 32, %o2
42570mov %o5, %l3
42571sllx %l4, 32, %o5
42572add %l4, 1, %l4
42573or %l4, %o5, %o5
42574casx [%i0], %l3, %o5
42575! move %o5(upper) -> %o2(lower)
42576srlx %o5, 32, %l3
42577or %l3, %o2, %o2
42578! move %o5(lower) -> %o3(upper)
42579sllx %o5, 32, %o3
42580add %l4, 1, %l4
42581
42582P3853: !_CASX [17] (maybe <- 0x180015e) (Int)
42583sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
42584sub %i0, %i2, %i2
42585add %i2, 8, %l6
42586ldx [%l6], %o5
42587! move %o5(upper) -> %o3(lower)
42588srlx %o5, 32, %l3
42589or %l3, %o3, %o3
42590! move %o5(lower) -> %o4(upper)
42591sllx %o5, 32, %o4
42592mov %o5, %l3
42593mov %l4, %o5
42594casx [%l6], %l3, %o5
42595! move %o5(upper) -> %o4(lower)
42596srlx %o5, 32, %l3
42597or %l3, %o4, %o4
42598!---- flushing int results buffer----
42599mov %o0, %l5
42600mov %o1, %l5
42601mov %o2, %l5
42602mov %o3, %l5
42603mov %o4, %l5
42604! move %o5(lower) -> %o0(upper)
42605sllx %o5, 32, %o0
42606add %l4, 1, %l4
42607
42608P3854: !_REPLACEMENT [6] (Int)
42609sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
42610add %i0, %i3, %i3
42611sethi %hi(0x20000), %l3
42612ld [%i3+0], %l7
42613st %l7, [%i3+0]
42614add %i3, %l3, %l6
42615ld [%l6+0], %l7
42616st %l7, [%l6+0]
42617add %l6, %l3, %l6
42618ld [%l6+0], %l7
42619st %l7, [%l6+0]
42620add %l6, %l3, %l6
42621ld [%l6+0], %l7
42622st %l7, [%l6+0]
42623add %l6, %l3, %l6
42624ld [%l6+0], %l7
42625st %l7, [%l6+0]
42626add %l6, %l3, %l6
42627ld [%l6+0], %l7
42628st %l7, [%l6+0]
42629add %l6, %l3, %l6
42630ld [%l6+0], %l7
42631st %l7, [%l6+0]
42632add %l6, %l3, %l6
42633ld [%l6+0], %l7
42634st %l7, [%l6+0]
42635
42636P3855: !_MEMBAR (FP)
42637
42638P3856: !_BSTC [10] (maybe <- 0x410000d3) (FP)
42639wr %g0, 0xe0, %asi
42640sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
42641sub %i0, %i2, %i2
42642! preparing store val #0, next val will be in f32
42643fmovs %f16, %f20
42644fadds %f16, %f17, %f16
42645! preparing store val #1, next val will be in f33
42646fmovs %f16, %f21
42647fadds %f16, %f17, %f16
42648! preparing store val #2, next val will be in f35
42649fmovd %f20, %f32
42650fmovs %f16, %f21
42651fadds %f16, %f17, %f16
42652fmovd %f20, %f34
42653membar #Sync
42654stda %f32, [%i2 + 0 ] %asi
42655
42656P3857: !_MEMBAR (FP)
42657membar #StoreLoad
42658
42659P3858: !_DWLD [18] (Int)
42660sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
42661sub %i0, %i3, %i3
42662ldx [%i3 + 0], %o5
42663! move %o5(upper) -> %o0(lower)
42664srlx %o5, 32, %l7
42665or %l7, %o0, %o0
42666! move %o5(lower) -> %o1(upper)
42667sllx %o5, 32, %o1
42668
42669P3859: !_DWST [22] (maybe <- 0x410000d6) (FP)
42670sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
42671sub %i0, %i2, %i2
42672! preparing store val #0, next val will be in f20
42673fmovs %f16, %f20
42674fadds %f16, %f17, %f16
42675! preparing store val #1, next val will be in f21
42676fmovs %f16, %f21
42677fadds %f16, %f17, %f16
42678std %f20, [%i2 + 0]
42679
42680P3860: !_MEMBAR (FP)
42681
42682P3861: !_BSTC [15] (maybe <- 0x410000d8) (FP)
42683wr %g0, 0xe0, %asi
42684sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
42685sub %i0, %i3, %i3
42686! preparing store val #0, next val will be in f32
42687fmovs %f16, %f20
42688fadds %f16, %f17, %f16
42689! preparing store val #1, next val will be in f33
42690fmovs %f16, %f21
42691fadds %f16, %f17, %f16
42692! preparing store val #2, next val will be in f35
42693fmovd %f20, %f32
42694fmovs %f16, %f21
42695fadds %f16, %f17, %f16
42696fmovd %f20, %f34
42697membar #Sync
42698stda %f32, [%i3 + 0 ] %asi
42699
42700P3862: !_MEMBAR (FP)
42701membar #StoreLoad
42702
42703P3863: !_CASX [15] (maybe <- 0x180015f) (Int)
42704ldx [%i3], %l6
42705! move %l6(upper) -> %o1(lower)
42706srlx %l6, 32, %l7
42707or %l7, %o1, %o1
42708! move %l6(lower) -> %o2(upper)
42709sllx %l6, 32, %o2
42710mov %l6, %l7
42711sllx %l4, 32, %l6
42712add %l4, 1, %l4
42713or %l4, %l6, %l6
42714casx [%i3], %l7, %l6
42715! move %l6(upper) -> %o2(lower)
42716srlx %l6, 32, %l7
42717or %l7, %o2, %o2
42718! move %l6(lower) -> %o3(upper)
42719sllx %l6, 32, %o3
42720add %l4, 1, %l4
42721
42722P3864: !_SWAP [1] (maybe <- 0x1800161) (Int)
42723mov %l4, %l3
42724swap [%i0 + 4], %l3
42725! move %l3(lower) -> %o3(lower)
42726srl %l3, 0, %l7
42727or %l7, %o3, %o3
42728add %l4, 1, %l4
42729
42730P3865: !_CASX [19] (maybe <- 0x1800162) (Int)
42731sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
42732sub %i0, %i2, %i2
42733ldx [%i2], %o4
42734! move %o4(upper) -> %o4(upper)
42735! move %o4(lower) -> %o4(lower)
42736!---- flushing int results buffer----
42737mov %o0, %l5
42738mov %o1, %l5
42739mov %o2, %l5
42740mov %o3, %l5
42741mov %o4, %l5
42742mov %o4, %l6
42743sllx %l4, 32, %o0
42744add %l4, 1, %l4
42745or %l4, %o0, %o0
42746casx [%i2], %l6, %o0
42747! move %o0(upper) -> %o0(upper)
42748! move %o0(lower) -> %o0(lower)
42749add %l4, 1, %l4
42750
42751P3866: !_CASX [19] (maybe <- 0x1800164) (Int)
42752ldx [%i2], %o1
42753! move %o1(upper) -> %o1(upper)
42754! move %o1(lower) -> %o1(lower)
42755mov %o1, %l6
42756sllx %l4, 32, %o2
42757add %l4, 1, %l4
42758or %l4, %o2, %o2
42759casx [%i2], %l6, %o2
42760! move %o2(upper) -> %o2(upper)
42761! move %o2(lower) -> %o2(lower)
42762add %l4, 1, %l4
42763
42764P3867: !_DWLD [13] (Int)
42765sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
42766sub %i0, %i3, %i3
42767ldx [%i3 + 0], %o3
42768! move %o3(upper) -> %o3(upper)
42769! move %o3(lower) -> %o3(lower)
42770
42771P3868: !_MEMBAR (FP)
42772
42773P3869: !_BST [13] (maybe <- 0x410000db) (FP)
42774wr %g0, 0xf0, %asi
42775! preparing store val #0, next val will be in f32
42776fmovs %f16, %f20
42777fadds %f16, %f17, %f16
42778! preparing store val #1, next val will be in f33
42779fmovs %f16, %f21
42780fadds %f16, %f17, %f16
42781! preparing store val #2, next val will be in f35
42782fmovd %f20, %f32
42783fmovs %f16, %f21
42784fadds %f16, %f17, %f16
42785fmovd %f20, %f34
42786membar #Sync
42787stda %f32, [%i3 + 0 ] %asi
42788
42789P3870: !_MEMBAR (FP)
42790membar #StoreLoad
42791
42792P3871: !_BLD [21] (FP)
42793wr %g0, 0xf0, %asi
42794sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
42795sub %i0, %i2, %i2
42796ldda [%i2 + 0] %asi, %f32
42797membar #Sync
42798! 3 addresses covered
42799fmovd %f32, %f18
42800fmovs %f18, %f1
42801fmovs %f19, %f2
42802fmovd %f34, %f18
42803fmovs %f19, %f3
42804
42805P3872: !_MEMBAR (FP) (Branch target of P3456)
42806ba P3873
42807nop
42808
42809TARGET3456:
42810ba RET3456
42811nop
42812
42813
42814P3873: !_LD [16] (Int)
42815sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
42816sub %i0, %i3, %i3
42817lduw [%i3 + 4], %o4
42818! move %o4(lower) -> %o4(upper)
42819sllx %o4, 32, %o4
42820
42821P3874: !_MEMBAR (FP) (CBR)
42822
42823! cbranch
42824andcc %l0, 1, %g0
42825be,pn %xcc, TARGET3874
42826nop
42827RET3874:
42828
42829! lfsr step begin
42830srlx %l0, 1, %l3
42831xnor %l3, %l0, %l3
42832sllx %l3, 63, %l3
42833or %l3, %l0, %l0
42834srlx %l0, 1, %l0
42835
42836
42837P3875: !_BSTC [12] (maybe <- 0x410000de) (FP)
42838wr %g0, 0xe0, %asi
42839sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
42840sub %i0, %i2, %i2
42841! preparing store val #0, next val will be in f32
42842fmovs %f16, %f20
42843fadds %f16, %f17, %f16
42844! preparing store val #1, next val will be in f33
42845fmovs %f16, %f21
42846fadds %f16, %f17, %f16
42847! preparing store val #2, next val will be in f35
42848fmovd %f20, %f32
42849fmovs %f16, %f21
42850fadds %f16, %f17, %f16
42851fmovd %f20, %f34
42852membar #Sync
42853stda %f32, [%i2 + 0 ] %asi
42854
42855P3876: !_MEMBAR (FP)
42856membar #StoreLoad
42857
42858P3877: !_PREFETCH [22] (Int)
42859sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
42860sub %i0, %i3, %i3
42861prefetch [%i3 + 4], 24
42862
42863P3878: !_MEMBAR (FP)
42864
42865P3879: !_BSTC [23] (maybe <- 0x410000e1) (FP)
42866wr %g0, 0xe0, %asi
42867! preparing store val #0, next val will be in f32
42868fmovs %f16, %f20
42869fadds %f16, %f17, %f16
42870! preparing store val #1, next val will be in f33
42871fmovs %f16, %f21
42872fadds %f16, %f17, %f16
42873! preparing store val #2, next val will be in f35
42874fmovd %f20, %f32
42875fmovs %f16, %f21
42876fadds %f16, %f17, %f16
42877fmovd %f20, %f34
42878membar #Sync
42879stda %f32, [%i3 + 0 ] %asi
42880
42881P3880: !_MEMBAR (FP)
42882membar #StoreLoad
42883
42884P3881: !_LDD [4] (Int)
42885ldd [%i1 + 0], %l6
42886! move %l6(lower) -> %o4(lower)
42887or %l6, %o4, %o4
42888!---- flushing int results buffer----
42889mov %o0, %l5
42890mov %o1, %l5
42891mov %o2, %l5
42892mov %o3, %l5
42893mov %o4, %l5
42894! move %l7(lower) -> %o0(upper)
42895sllx %l7, 32, %o0
42896
42897P3882: !_MEMBAR (FP)
42898membar #StoreLoad
42899
42900P3883: !_BLD [13] (FP)
42901wr %g0, 0xf0, %asi
42902ldda [%i2 + 0] %asi, %f32
42903membar #Sync
42904! 3 addresses covered
42905fmovd %f32, %f4
42906fmovd %f34, %f18
42907fmovs %f19, %f6
42908
42909P3884: !_MEMBAR (FP)
42910
42911P3885: !_BLD [23] (FP)
42912wr %g0, 0xf0, %asi
42913ldda [%i3 + 0] %asi, %f32
42914membar #Sync
42915! 3 addresses covered
42916fmovd %f32, %f18
42917fmovs %f18, %f7
42918fmovs %f19, %f8
42919fmovd %f34, %f18
42920fmovs %f19, %f9
42921
42922P3886: !_MEMBAR (FP)
42923
42924P3887: !_CAS [0] (maybe <- 0x1800166) (Int)
42925lduw [%i0], %o5
42926mov %o5, %l3
42927! move %l3(lower) -> %o0(lower)
42928or %l3, %o0, %o0
42929mov %l4, %o1
42930cas [%i0], %l3, %o1
42931! move %o1(lower) -> %o1(upper)
42932sllx %o1, 32, %o1
42933add %l4, 1, %l4
42934
42935P3888: !_DWLD [0] (Int)
42936ldx [%i0 + 0], %l6
42937! move %l6(upper) -> %o1(lower)
42938srlx %l6, 32, %l3
42939or %l3, %o1, %o1
42940! move %l6(lower) -> %o2(upper)
42941sllx %l6, 32, %o2
42942
42943P3889: !_MEMBAR (FP)
42944membar #StoreLoad
42945
42946P3890: !_BLD [7] (FP)
42947wr %g0, 0xf0, %asi
42948sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
42949add %i0, %i2, %i2
42950ldda [%i2 + 0] %asi, %f32
42951membar #Sync
42952! 3 addresses covered
42953fmovd %f32, %f10
42954fmovd %f34, %f18
42955fmovs %f19, %f12
42956
42957P3891: !_MEMBAR (FP)
42958
42959P3892: !_LD [20] (Int) (Branch target of P3467)
42960sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
42961sub %i0, %i3, %i3
42962lduw [%i3 + 12], %o5
42963! move %o5(lower) -> %o2(lower)
42964or %o5, %o2, %o2
42965ba P3893
42966nop
42967
42968TARGET3467:
42969ba RET3467
42970nop
42971
42972
42973P3893: !_SWAP [15] (maybe <- 0x1800167) (Int)
42974sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
42975sub %i0, %i2, %i2
42976mov %l4, %o3
42977swap [%i2 + 0], %o3
42978! move %o3(lower) -> %o3(upper)
42979sllx %o3, 32, %o3
42980add %l4, 1, %l4
42981
42982P3894: !_CASX [20] (maybe <- 0x1800168) (Int)
42983add %i3, 8, %l3
42984ldx [%l3], %l7
42985! move %l7(upper) -> %o3(lower)
42986srlx %l7, 32, %o5
42987or %o5, %o3, %o3
42988! move %l7(lower) -> %o4(upper)
42989sllx %l7, 32, %o4
42990mov %l7, %o5
42991mov %l4, %l7
42992casx [%l3], %o5, %l7
42993! move %l7(upper) -> %o4(lower)
42994srlx %l7, 32, %o5
42995or %o5, %o4, %o4
42996!---- flushing int results buffer----
42997mov %o0, %l5
42998mov %o1, %l5
42999mov %o2, %l5
43000mov %o3, %l5
43001mov %o4, %l5
43002! move %l7(lower) -> %o0(upper)
43003sllx %l7, 32, %o0
43004add %l4, 1, %l4
43005
43006P3895: !_ST [22] (maybe <- 0x1800169) (Int)
43007sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
43008sub %i0, %i3, %i3
43009stw %l4, [%i3 + 4 ]
43010add %l4, 1, %l4
43011
43012P3896: !_MEMBAR (FP)
43013
43014P3897: !_BST [13] (maybe <- 0x410000e4) (FP)
43015wr %g0, 0xf0, %asi
43016sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
43017sub %i0, %i2, %i2
43018! preparing store val #0, next val will be in f32
43019fmovs %f16, %f20
43020fadds %f16, %f17, %f16
43021! preparing store val #1, next val will be in f33
43022fmovs %f16, %f21
43023fadds %f16, %f17, %f16
43024! preparing store val #2, next val will be in f35
43025fmovd %f20, %f32
43026fmovs %f16, %f21
43027fadds %f16, %f17, %f16
43028fmovd %f20, %f34
43029membar #Sync
43030stda %f32, [%i2 + 0 ] %asi
43031
43032P3898: !_MEMBAR (FP)
43033membar #StoreLoad
43034
43035P3899: !_LD [3] (Int)
43036lduw [%i1 + 0], %l7
43037! move %l7(lower) -> %o0(lower)
43038or %l7, %o0, %o0
43039
43040P3900: !_DWLD [12] (Int)
43041ldx [%i2 + 0], %o1
43042! move %o1(upper) -> %o1(upper)
43043! move %o1(lower) -> %o1(lower)
43044
43045P3901: !_ST [9] (maybe <- 0x180016a) (Int)
43046sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
43047sub %i0, %i3, %i3
43048stw %l4, [%i3 + 0 ]
43049add %l4, 1, %l4
43050
43051P3902: !_MEMBAR (FP)
43052
43053P3903: !_BST [12] (maybe <- 0x410000e7) (FP)
43054wr %g0, 0xf0, %asi
43055! preparing store val #0, next val will be in f32
43056fmovs %f16, %f20
43057fadds %f16, %f17, %f16
43058! preparing store val #1, next val will be in f33
43059fmovs %f16, %f21
43060fadds %f16, %f17, %f16
43061! preparing store val #2, next val will be in f35
43062fmovd %f20, %f32
43063fmovs %f16, %f21
43064fadds %f16, %f17, %f16
43065fmovd %f20, %f34
43066membar #Sync
43067stda %f32, [%i2 + 0 ] %asi
43068
43069P3904: !_MEMBAR (FP)
43070membar #StoreLoad
43071
43072P3905: !_SWAP [20] (maybe <- 0x180016b) (Int)
43073sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
43074sub %i0, %i2, %i2
43075mov %l4, %o2
43076swap [%i2 + 12], %o2
43077! move %o2(lower) -> %o2(upper)
43078sllx %o2, 32, %o2
43079add %l4, 1, %l4
43080
43081P3906: !_ST_BINIT [12] (maybe <- 0x180016c) (Int)
43082wr %g0, 0xe2, %asi
43083sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
43084sub %i0, %i3, %i3
43085stwa %l4, [%i3 + 0] %asi
43086add %l4, 1, %l4
43087
43088P3907: !_MEMBAR (Int)
43089membar #StoreLoad
43090
43091P3908: !_CASX [1] (maybe <- 0x180016d) (Int)
43092ldx [%i0], %l6
43093! move %l6(upper) -> %o2(lower)
43094srlx %l6, 32, %l7
43095or %l7, %o2, %o2
43096! move %l6(lower) -> %o3(upper)
43097sllx %l6, 32, %o3
43098mov %l6, %l7
43099sllx %l4, 32, %l6
43100add %l4, 1, %l4
43101or %l4, %l6, %l6
43102casx [%i0], %l7, %l6
43103! move %l6(upper) -> %o3(lower)
43104srlx %l6, 32, %l7
43105or %l7, %o3, %o3
43106! move %l6(lower) -> %o4(upper)
43107sllx %l6, 32, %o4
43108add %l4, 1, %l4
43109
43110P3909: !_DWST_BINIT [2] (maybe <- 0x180016f) (Int) (CBR)
43111wr %g0, 0xe2, %asi
43112mov %l4, %l7
43113stxa %l7, [%i0 + 8] %asi
43114add %l4, 1, %l4
43115
43116! cbranch
43117andcc %l0, 1, %g0
43118be,pt %xcc, TARGET3909
43119nop
43120RET3909:
43121
43122! lfsr step begin
43123srlx %l0, 1, %l6
43124xnor %l6, %l0, %l6
43125sllx %l6, 63, %l6
43126or %l6, %l0, %l0
43127srlx %l0, 1, %l0
43128
43129
43130P3910: !_MEMBAR (Int)
43131membar #StoreLoad
43132
43133P3911: !_ST [18] (maybe <- 0x1800170) (Int)
43134stw %l4, [%i2 + 0 ]
43135add %l4, 1, %l4
43136
43137P3912: !_MEMBAR (FP)
43138
43139P3913: !_BSTC [0] (maybe <- 0x410000ea) (FP)
43140wr %g0, 0xe0, %asi
43141! preparing store val #0, next val will be in f32
43142fmovs %f16, %f20
43143fadds %f16, %f17, %f16
43144! preparing store val #1, next val will be in f33
43145fmovs %f16, %f21
43146fadds %f16, %f17, %f16
43147! preparing store val #2, next val will be in f35
43148fmovd %f20, %f32
43149fmovs %f16, %f21
43150fadds %f16, %f17, %f16
43151fmovd %f20, %f34
43152membar #Sync
43153stda %f32, [%i0 + 0 ] %asi
43154
43155P3914: !_MEMBAR (FP)
43156membar #StoreLoad
43157
43158P3915: !_CAS [13] (maybe <- 0x1800171) (Int) (LE)
43159! Change single-word-level endianess (big endian <-> little endian)
43160sethi %hi(0xff00ff00), %l6
43161or %l6, %lo(0xff00ff00), %l6
43162and %l4, %l6, %l3
43163srl %l3, 8, %l3
43164sll %l4, 8, %l7
43165and %l7, %l6, %l7
43166or %l7, %l3, %l7
43167srl %l7, 16, %l3
43168sll %l7, 16, %l7
43169srl %l7, 0, %l7
43170or %l7, %l3, %l7
43171wr %g0, 0x88, %asi
43172add %i3, 4, %l6
43173lduwa [%l6] %asi, %o5
43174mov %o5, %l3
43175! move %l3(lower) -> %o4(lower)
43176or %l3, %o4, %o4
43177!---- flushing int results buffer----
43178mov %o0, %l5
43179mov %o1, %l5
43180mov %o2, %l5
43181mov %o3, %l5
43182mov %o4, %l5
43183mov %l7, %o0
43184casa [%l6] %asi, %l3, %o0
43185! move %o0(lower) -> %o0(upper)
43186sllx %o0, 32, %o0
43187add %l4, 1, %l4
43188
43189P3916: !_SWAP [0] (maybe <- 0x1800172) (Int)
43190mov %l4, %l7
43191swap [%i0 + 0], %l7
43192! move %l7(lower) -> %o0(lower)
43193srl %l7, 0, %l3
43194or %l3, %o0, %o0
43195add %l4, 1, %l4
43196
43197P3917: !_MEMBAR (FP)
43198membar #StoreLoad
43199
43200P3918: !_BLD [2] (FP) (CBR)
43201wr %g0, 0xf0, %asi
43202ldda [%i0 + 0] %asi, %f32
43203membar #Sync
43204! 3 addresses covered
43205fmovd %f32, %f18
43206fmovs %f18, %f13
43207fmovs %f19, %f14
43208fmovd %f34, %f18
43209fmovs %f19, %f15
43210!---- flushing fp results buffer to %f30 ----
43211fmovd %f0, %f30
43212fmovd %f2, %f30
43213fmovd %f4, %f30
43214fmovd %f6, %f30
43215fmovd %f8, %f30
43216fmovd %f10, %f30
43217fmovd %f12, %f30
43218fmovd %f14, %f30
43219!--
43220
43221! cbranch
43222andcc %l0, 1, %g0
43223be,pt %xcc, TARGET3918
43224nop
43225RET3918:
43226
43227! lfsr step begin
43228srlx %l0, 1, %o5
43229xnor %o5, %l0, %o5
43230sllx %o5, 63, %o5
43231or %o5, %l0, %l0
43232srlx %l0, 1, %l0
43233
43234
43235P3919: !_MEMBAR (FP)
43236
43237P3920: !_LDD [5] (Int)
43238ldd [%i1 + 8], %l6
43239! move %l7(lower) -> %o1(upper)
43240sllx %l7, 32, %o1
43241
43242P3921: !_SWAP [20] (maybe <- 0x1800173) (Int)
43243mov %l4, %l7
43244swap [%i2 + 12], %l7
43245! move %l7(lower) -> %o1(lower)
43246srl %l7, 0, %l3
43247or %l3, %o1, %o1
43248add %l4, 1, %l4
43249
43250P3922: !_MEMBAR (FP)
43251
43252P3923: !_BSTC [9] (maybe <- 0x410000ed) (FP)
43253wr %g0, 0xe0, %asi
43254sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
43255sub %i0, %i2, %i2
43256! preparing store val #0, next val will be in f32
43257fmovs %f16, %f20
43258fadds %f16, %f17, %f16
43259! preparing store val #1, next val will be in f33
43260fmovs %f16, %f21
43261fadds %f16, %f17, %f16
43262! preparing store val #2, next val will be in f35
43263fmovd %f20, %f32
43264fmovs %f16, %f21
43265fadds %f16, %f17, %f16
43266fmovd %f20, %f34
43267membar #Sync
43268stda %f32, [%i2 + 0 ] %asi
43269
43270P3924: !_MEMBAR (FP)
43271
43272P3925: !_BSTC [21] (maybe <- 0x410000f0) (FP)
43273wr %g0, 0xe0, %asi
43274sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
43275sub %i0, %i3, %i3
43276! preparing store val #0, next val will be in f32
43277fmovs %f16, %f20
43278fadds %f16, %f17, %f16
43279! preparing store val #1, next val will be in f33
43280fmovs %f16, %f21
43281fadds %f16, %f17, %f16
43282! preparing store val #2, next val will be in f35
43283fmovd %f20, %f32
43284fmovs %f16, %f21
43285fadds %f16, %f17, %f16
43286fmovd %f20, %f34
43287membar #Sync
43288stda %f32, [%i3 + 0 ] %asi
43289
43290P3926: !_MEMBAR (FP)
43291membar #StoreLoad
43292
43293P3927: !_BLD [7] (FP)
43294wr %g0, 0xf0, %asi
43295sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
43296add %i0, %i2, %i2
43297ldda [%i2 + 0] %asi, %f0
43298membar #Sync
43299! 3 addresses covered
43300fmovs %f3, %f2
43301
43302P3928: !_MEMBAR (FP)
43303
43304P3929: !_REPLACEMENT [4] (Int)
43305sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
43306sub %i0, %i3, %i3
43307sethi %hi(0x20000), %l6
43308ld [%i3+4], %o5
43309st %o5, [%i3+4]
43310add %i3, %l6, %l7
43311ld [%l7+4], %o5
43312st %o5, [%l7+4]
43313add %l7, %l6, %l7
43314ld [%l7+4], %o5
43315st %o5, [%l7+4]
43316add %l7, %l6, %l7
43317ld [%l7+4], %o5
43318st %o5, [%l7+4]
43319add %l7, %l6, %l7
43320ld [%l7+4], %o5
43321st %o5, [%l7+4]
43322add %l7, %l6, %l7
43323ld [%l7+4], %o5
43324st %o5, [%l7+4]
43325add %l7, %l6, %l7
43326ld [%l7+4], %o5
43327st %o5, [%l7+4]
43328add %l7, %l6, %l7
43329ld [%l7+4], %o5
43330st %o5, [%l7+4]
43331
43332P3930: !_DWST_BINIT [3] (maybe <- 0x1800174) (Int)
43333wr %g0, 0xe2, %asi
43334sllx %l4, 32, %l3
43335add %l4, 1, %l4
43336or %l3, %l4, %l3
43337stxa %l3, [%i1 + 0] %asi
43338add %l4, 1, %l4
43339
43340P3931: !_MEMBAR (Int)
43341membar #StoreLoad
43342
43343P3932: !_PREFETCH [23] (Int) (CBR)
43344sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
43345sub %i0, %i2, %i2
43346prefetch [%i2 + 12], 0
43347
43348! cbranch
43349andcc %l0, 1, %g0
43350be,pn %xcc, TARGET3932
43351nop
43352RET3932:
43353
43354! lfsr step begin
43355srlx %l0, 1, %o5
43356xnor %o5, %l0, %o5
43357sllx %o5, 63, %o5
43358or %o5, %l0, %l0
43359srlx %l0, 1, %l0
43360
43361
43362P3933: !_DWLD [6] (Int)
43363sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
43364add %i0, %i3, %i3
43365ldx [%i3 + 0], %o2
43366! move %o2(upper) -> %o2(upper)
43367! move %o2(lower) -> %o2(lower)
43368
43369P3934: !_CAS [3] (maybe <- 0x1800176) (Int)
43370lduw [%i1], %o3
43371mov %o3, %l7
43372! move %l7(lower) -> %o3(upper)
43373sllx %l7, 32, %o3
43374mov %l4, %l6
43375cas [%i1], %l7, %l6
43376! move %l6(lower) -> %o3(lower)
43377srl %l6, 0, %l7
43378or %l7, %o3, %o3
43379add %l4, 1, %l4
43380
43381P3935: !_LD [11] (Int)
43382sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
43383sub %i0, %i2, %i2
43384lduw [%i2 + 12], %o4
43385! move %o4(lower) -> %o4(upper)
43386sllx %o4, 32, %o4
43387
43388P3936: !_LD [0] (Int) (LE)
43389wr %g0, 0x88, %asi
43390lduwa [%i0 + 0] %asi, %l6
43391! move %l6(lower) -> %o4(lower)
43392or %l6, %o4, %o4
43393!---- flushing int results buffer----
43394mov %o0, %l5
43395mov %o1, %l5
43396mov %o2, %l5
43397mov %o3, %l5
43398mov %o4, %l5
43399
43400P3937: !_ST [1] (maybe <- 0x1800177) (Int)
43401stw %l4, [%i0 + 4 ]
43402add %l4, 1, %l4
43403
43404P3938: !_LD [17] (Int) (Branch target of P3385)
43405sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
43406sub %i0, %i3, %i3
43407lduw [%i3 + 12], %o0
43408! move %o0(lower) -> %o0(upper)
43409sllx %o0, 32, %o0
43410ba P3939
43411nop
43412
43413TARGET3385:
43414ba RET3385
43415nop
43416
43417
43418P3939: !_LD [5] (Int)
43419lduw [%i1 + 12], %l3
43420! move %l3(lower) -> %o0(lower)
43421or %l3, %o0, %o0
43422
43423P3940: !_MEMBAR (FP)
43424membar #StoreLoad
43425
43426P3941: !_BLD [7] (FP)
43427wr %g0, 0xf0, %asi
43428sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
43429add %i0, %i2, %i2
43430ldda [%i2 + 0] %asi, %f32
43431membar #Sync
43432! 3 addresses covered
43433fmovd %f32, %f18
43434fmovs %f18, %f3
43435fmovs %f19, %f4
43436fmovd %f34, %f18
43437fmovs %f19, %f5
43438
43439P3942: !_MEMBAR (FP)
43440
43441P3943: !_SWAP [0] (maybe <- 0x1800178) (Int)
43442mov %l4, %o1
43443swap [%i0 + 0], %o1
43444! move %o1(lower) -> %o1(upper)
43445sllx %o1, 32, %o1
43446add %l4, 1, %l4
43447
43448P3944: !_MEMBAR (FP)
43449membar #StoreLoad
43450
43451P3945: !_BLD [23] (FP)
43452wr %g0, 0xf0, %asi
43453sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
43454sub %i0, %i3, %i3
43455ldda [%i3 + 0] %asi, %f32
43456membar #Sync
43457! 3 addresses covered
43458fmovd %f32, %f6
43459fmovd %f34, %f18
43460fmovs %f19, %f8
43461
43462P3946: !_MEMBAR (FP)
43463
43464P3947: !_ST_BINIT [11] (maybe <- 0x1800179) (Int)
43465wr %g0, 0xe2, %asi
43466sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
43467sub %i0, %i2, %i2
43468stwa %l4, [%i2 + 12] %asi
43469add %l4, 1, %l4
43470
43471P3948: !_MEMBAR (Int)
43472membar #StoreLoad
43473
43474P3949: !_DWST [13] (maybe <- 0x180017a) (Int)
43475sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
43476sub %i0, %i3, %i3
43477sllx %l4, 32, %o5
43478add %l4, 1, %l4
43479or %o5, %l4, %o5
43480stx %o5, [%i3 + 0]
43481add %l4, 1, %l4
43482
43483P3950: !_LD [17] (Int)
43484sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
43485sub %i0, %i2, %i2
43486lduw [%i2 + 12], %o5
43487! move %o5(lower) -> %o1(lower)
43488or %o5, %o1, %o1
43489
43490P3951: !_ST [12] (maybe <- 0x180017c) (Int)
43491stw %l4, [%i3 + 0 ]
43492add %l4, 1, %l4
43493
43494P3952: !_MEMBAR (FP)
43495
43496P3953: !_BSTC [17] (maybe <- 0x410000f3) (FP)
43497wr %g0, 0xe0, %asi
43498! preparing store val #0, next val will be in f32
43499fmovs %f16, %f20
43500fadds %f16, %f17, %f16
43501! preparing store val #1, next val will be in f33
43502fmovs %f16, %f21
43503fadds %f16, %f17, %f16
43504! preparing store val #2, next val will be in f35
43505fmovd %f20, %f32
43506fmovs %f16, %f21
43507fadds %f16, %f17, %f16
43508fmovd %f20, %f34
43509membar #Sync
43510stda %f32, [%i2 + 0 ] %asi
43511
43512P3954: !_MEMBAR (FP)
43513membar #StoreLoad
43514
43515P3955: !_LDD [19] (Int)
43516sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
43517sub %i0, %i3, %i3
43518ldd [%i3 + 0], %l6
43519! move %l6(lower) -> %o2(upper)
43520sllx %l6, 32, %o2
43521! move %l7(lower) -> %o2(lower)
43522or %l7, %o2, %o2
43523
43524P3956: !_ST [18] (maybe <- 0x180017d) (Int)
43525stw %l4, [%i3 + 0 ]
43526add %l4, 1, %l4
43527
43528P3957: !_DWLD [18] (Int)
43529ldx [%i3 + 0], %o3
43530! move %o3(upper) -> %o3(upper)
43531! move %o3(lower) -> %o3(lower)
43532
43533P3958: !_MEMBAR (FP)
43534membar #StoreLoad
43535
43536P3959: !_BLD [0] (FP)
43537wr %g0, 0xf0, %asi
43538ldda [%i0 + 0] %asi, %f32
43539membar #Sync
43540! 3 addresses covered
43541fmovd %f32, %f18
43542fmovs %f18, %f9
43543fmovs %f19, %f10
43544fmovd %f34, %f18
43545fmovs %f19, %f11
43546
43547P3960: !_MEMBAR (FP)
43548
43549P3961: !_ST_BINIT [20] (maybe <- 0x180017e) (Int)
43550wr %g0, 0xe2, %asi
43551stwa %l4, [%i3 + 12] %asi
43552add %l4, 1, %l4
43553
43554P3962: !_MEMBAR (Int)
43555membar #StoreLoad
43556
43557P3963: !_LDD [23] (Int)
43558sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
43559sub %i0, %i2, %i2
43560ldd [%i2 + 8], %l6
43561! move %l7(lower) -> %o4(upper)
43562sllx %l7, 32, %o4
43563
43564P3964: !_LDD [17] (Int)
43565sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
43566sub %i0, %i3, %i3
43567ldd [%i3 + 8], %l6
43568! move %l7(lower) -> %o4(lower)
43569or %l7, %o4, %o4
43570!---- flushing int results buffer----
43571mov %o0, %l5
43572mov %o1, %l5
43573mov %o2, %l5
43574mov %o3, %l5
43575mov %o4, %l5
43576
43577P3965: !_SWAP [16] (maybe <- 0x180017f) (Int)
43578sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
43579sub %i0, %i2, %i2
43580mov %l4, %o0
43581swap [%i2 + 4], %o0
43582! move %o0(lower) -> %o0(upper)
43583sllx %o0, 32, %o0
43584add %l4, 1, %l4
43585
43586P3966: !_MEMBAR (FP)
43587
43588P3967: !_BST [9] (maybe <- 0x410000f6) (FP)
43589wr %g0, 0xf0, %asi
43590sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
43591sub %i0, %i3, %i3
43592! preparing store val #0, next val will be in f32
43593fmovs %f16, %f20
43594fadds %f16, %f17, %f16
43595! preparing store val #1, next val will be in f33
43596fmovs %f16, %f21
43597fadds %f16, %f17, %f16
43598! preparing store val #2, next val will be in f35
43599fmovd %f20, %f32
43600fmovs %f16, %f21
43601fadds %f16, %f17, %f16
43602fmovd %f20, %f34
43603membar #Sync
43604stda %f32, [%i3 + 0 ] %asi
43605
43606P3968: !_MEMBAR (FP)
43607membar #StoreLoad
43608
43609P3969: !_CAS [20] (maybe <- 0x1800180) (Int)
43610sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
43611sub %i0, %i2, %i2
43612add %i2, 12, %l3
43613lduw [%l3], %l7
43614mov %l7, %o5
43615! move %o5(lower) -> %o0(lower)
43616or %o5, %o0, %o0
43617mov %l4, %o1
43618cas [%l3], %o5, %o1
43619! move %o1(lower) -> %o1(upper)
43620sllx %o1, 32, %o1
43621add %l4, 1, %l4
43622
43623P3970: !_DWLD [2] (Int)
43624ldx [%i0 + 8], %l3
43625! move %l3(lower) -> %o1(lower)
43626srl %l3, 0, %o5
43627or %o5, %o1, %o1
43628
43629P3971: !_MEMBAR (FP)
43630membar #StoreLoad
43631
43632P3972: !_BLD [4] (FP)
43633wr %g0, 0xf0, %asi
43634ldda [%i1 + 0] %asi, %f32
43635membar #Sync
43636! 3 addresses covered
43637fmovd %f32, %f12
43638fmovd %f34, %f18
43639fmovs %f19, %f14
43640
43641P3973: !_MEMBAR (FP)
43642
43643P3974: !_DWLD [1] (Int)
43644ldx [%i0 + 0], %o2
43645! move %o2(upper) -> %o2(upper)
43646! move %o2(lower) -> %o2(lower)
43647
43648P3975: !_SWAP [16] (maybe <- 0x1800181) (Int)
43649sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
43650sub %i0, %i3, %i3
43651mov %l4, %o3
43652swap [%i3 + 4], %o3
43653! move %o3(lower) -> %o3(upper)
43654sllx %o3, 32, %o3
43655add %l4, 1, %l4
43656
43657P3976: !_LDD [8] (Int)
43658sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
43659add %i0, %i2, %i2
43660ldd [%i2 + 8], %l6
43661! move %l7(lower) -> %o3(lower)
43662or %l7, %o3, %o3
43663
43664P3977: !_SWAP [19] (maybe <- 0x1800182) (Int)
43665sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
43666sub %i0, %i3, %i3
43667mov %l4, %o4
43668swap [%i3 + 4], %o4
43669! move %o4(lower) -> %o4(upper)
43670sllx %o4, 32, %o4
43671add %l4, 1, %l4
43672
43673P3978: !_CAS [1] (maybe <- 0x1800183) (Int)
43674add %i0, 4, %l3
43675lduw [%l3], %l7
43676mov %l7, %o5
43677! move %o5(lower) -> %o4(lower)
43678or %o5, %o4, %o4
43679!---- flushing int results buffer----
43680mov %o0, %l5
43681mov %o1, %l5
43682mov %o2, %l5
43683mov %o3, %l5
43684mov %o4, %l5
43685mov %l4, %o0
43686cas [%l3], %o5, %o0
43687! move %o0(lower) -> %o0(upper)
43688sllx %o0, 32, %o0
43689add %l4, 1, %l4
43690
43691P3979: !_ST_BINIT [6] (maybe <- 0x1800184) (Int)
43692wr %g0, 0xe2, %asi
43693stwa %l4, [%i2 + 0] %asi
43694add %l4, 1, %l4
43695
43696P3980: !_MEMBAR (Int)
43697membar #StoreLoad
43698
43699P3981: !_LDD [22] (Int)
43700sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
43701sub %i0, %i2, %i2
43702ldd [%i2 + 0], %l6
43703! move %l6(lower) -> %o0(lower)
43704or %l6, %o0, %o0
43705! move %l7(lower) -> %o1(upper)
43706sllx %l7, 32, %o1
43707
43708P3982: !_MEMBAR (FP)
43709
43710P3983: !_BST [1] (maybe <- 0x410000f9) (FP)
43711wr %g0, 0xf0, %asi
43712! preparing store val #0, next val will be in f32
43713fmovs %f16, %f20
43714fadds %f16, %f17, %f16
43715! preparing store val #1, next val will be in f33
43716fmovs %f16, %f21
43717fadds %f16, %f17, %f16
43718! preparing store val #2, next val will be in f35
43719fmovd %f20, %f32
43720fmovs %f16, %f21
43721fadds %f16, %f17, %f16
43722fmovd %f20, %f34
43723membar #Sync
43724stda %f32, [%i0 + 0 ] %asi
43725
43726P3984: !_MEMBAR (FP)
43727membar #StoreLoad
43728
43729P3985: !_DWST_BINIT [11] (maybe <- 0x1800185) (Int)
43730wr %g0, 0xe2, %asi
43731sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
43732sub %i0, %i3, %i3
43733mov %l4, %o5
43734stxa %o5, [%i3 + 8] %asi
43735add %l4, 1, %l4
43736
43737P3986: !_MEMBAR (Int)
43738membar #StoreLoad
43739
43740P3987: !_LDD [2] (Int) (CBR)
43741ldd [%i0 + 8], %l6
43742! move %l7(lower) -> %o1(lower)
43743or %l7, %o1, %o1
43744
43745! cbranch
43746andcc %l0, 1, %g0
43747be,pn %xcc, TARGET3987
43748nop
43749RET3987:
43750
43751! lfsr step begin
43752srlx %l0, 1, %l3
43753xnor %l3, %l0, %l3
43754sllx %l3, 63, %l3
43755or %l3, %l0, %l0
43756srlx %l0, 1, %l0
43757
43758
43759P3988: !_LDD [10] (Int) (LE)
43760wr %g0, 0x88, %asi
43761ldda [%i3 + 0] %asi, %l6
43762! move %l6(lower) -> %o2(upper)
43763sllx %l6, 32, %o2
43764! move %l7(lower) -> %o2(lower)
43765or %l7, %o2, %o2
43766
43767P3989: !_ST [23] (maybe <- 0x1800186) (Int)
43768stw %l4, [%i2 + 12 ]
43769add %l4, 1, %l4
43770
43771P3990: !_DWST_BINIT [16] (maybe <- 0x1800187) (Int)
43772wr %g0, 0xe2, %asi
43773sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
43774sub %i0, %i2, %i2
43775sllx %l4, 32, %o5
43776add %l4, 1, %l4
43777or %o5, %l4, %o5
43778stxa %o5, [%i2 + 0] %asi
43779add %l4, 1, %l4
43780
43781P3991: !_MEMBAR (Int)
43782
43783P3992: !_BSTC [22] (maybe <- 0x410000fc) (FP)
43784wr %g0, 0xe0, %asi
43785sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
43786sub %i0, %i3, %i3
43787! preparing store val #0, next val will be in f32
43788fmovs %f16, %f20
43789fadds %f16, %f17, %f16
43790! preparing store val #1, next val will be in f33
43791fmovs %f16, %f21
43792fadds %f16, %f17, %f16
43793! preparing store val #2, next val will be in f35
43794fmovd %f20, %f32
43795fmovs %f16, %f21
43796fadds %f16, %f17, %f16
43797fmovd %f20, %f34
43798membar #Sync
43799stda %f32, [%i3 + 0 ] %asi
43800
43801P3993: !_MEMBAR (FP) (Branch target of P3360)
43802membar #StoreLoad
43803ba P3994
43804nop
43805
43806TARGET3360:
43807ba RET3360
43808nop
43809
43810
43811P3994: !_LDD [12] (Int) (CBR)
43812sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
43813sub %i0, %i2, %i2
43814ldd [%i2 + 0], %l6
43815! move %l6(lower) -> %o3(upper)
43816sllx %l6, 32, %o3
43817! move %l7(lower) -> %o3(lower)
43818or %l7, %o3, %o3
43819
43820! cbranch
43821andcc %l0, 1, %g0
43822be,pt %xcc, TARGET3994
43823nop
43824RET3994:
43825
43826! lfsr step begin
43827srlx %l0, 1, %l3
43828xnor %l3, %l0, %l3
43829sllx %l3, 63, %l3
43830or %l3, %l0, %l0
43831srlx %l0, 1, %l0
43832
43833
43834P3995: !_LD [23] (Int)
43835lduw [%i3 + 12], %o4
43836! move %o4(lower) -> %o4(upper)
43837sllx %o4, 32, %o4
43838
43839P3996: !_MEMBAR (FP)
43840
43841P3997: !_BSTC [22] (maybe <- 0x410000ff) (FP)
43842wr %g0, 0xe0, %asi
43843! preparing store val #0, next val will be in f32
43844fmovs %f16, %f20
43845fadds %f16, %f17, %f16
43846! preparing store val #1, next val will be in f33
43847fmovs %f16, %f21
43848fadds %f16, %f17, %f16
43849! preparing store val #2, next val will be in f35
43850fmovd %f20, %f32
43851fmovs %f16, %f21
43852fadds %f16, %f17, %f16
43853fmovd %f20, %f34
43854membar #Sync
43855stda %f32, [%i3 + 0 ] %asi
43856
43857P3998: !_MEMBAR (FP)
43858membar #StoreLoad
43859
43860P3999: !_ST_BINIT [1] (maybe <- 0x1800189) (Int)
43861wr %g0, 0xe2, %asi
43862stwa %l4, [%i0 + 4] %asi
43863add %l4, 1, %l4
43864
43865P4000: !_MEMBAR (Int)
43866
43867P4001: !_BSTC [17] (maybe <- 0x41000102) (FP)
43868wr %g0, 0xe0, %asi
43869sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
43870sub %i0, %i3, %i3
43871! preparing store val #0, next val will be in f32
43872fmovs %f16, %f20
43873fadds %f16, %f17, %f16
43874! preparing store val #1, next val will be in f33
43875fmovs %f16, %f21
43876fadds %f16, %f17, %f16
43877! preparing store val #2, next val will be in f35
43878fmovd %f20, %f32
43879fmovs %f16, %f21
43880fadds %f16, %f17, %f16
43881fmovd %f20, %f34
43882membar #Sync
43883stda %f32, [%i3 + 0 ] %asi
43884
43885P4002: !_MEMBAR (FP)
43886membar #StoreLoad
43887
43888P4003: !_DWST [9] (maybe <- 0x180018a) (Int)
43889sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
43890sub %i0, %i2, %i2
43891sllx %l4, 32, %l3
43892add %l4, 1, %l4
43893or %l3, %l4, %l3
43894stx %l3, [%i2 + 0]
43895add %l4, 1, %l4
43896
43897P4004: !_REPLACEMENT [12] (Int)
43898sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
43899sub %i0, %i3, %i3
43900sethi %hi(0x20000), %o5
43901ld [%i3+0], %l6
43902st %l6, [%i3+0]
43903add %i3, %o5, %l3
43904ld [%l3+0], %l6
43905st %l6, [%l3+0]
43906add %l3, %o5, %l3
43907ld [%l3+0], %l6
43908st %l6, [%l3+0]
43909add %l3, %o5, %l3
43910ld [%l3+0], %l6
43911st %l6, [%l3+0]
43912add %l3, %o5, %l3
43913ld [%l3+0], %l6
43914st %l6, [%l3+0]
43915add %l3, %o5, %l3
43916ld [%l3+0], %l6
43917st %l6, [%l3+0]
43918add %l3, %o5, %l3
43919ld [%l3+0], %l6
43920st %l6, [%l3+0]
43921add %l3, %o5, %l3
43922ld [%l3+0], %l6
43923st %l6, [%l3+0]
43924
43925P4005: !_MEMBAR (FP)
43926membar #StoreLoad
43927
43928P4006: !_BLD [10] (FP)
43929wr %g0, 0xf0, %asi
43930ldda [%i2 + 0] %asi, %f32
43931membar #Sync
43932! 3 addresses covered
43933fmovd %f32, %f18
43934fmovs %f18, %f15
43935!---- flushing fp results buffer to %f30 ----
43936fmovd %f0, %f30
43937fmovd %f2, %f30
43938fmovd %f4, %f30
43939fmovd %f6, %f30
43940fmovd %f8, %f30
43941fmovd %f10, %f30
43942fmovd %f12, %f30
43943fmovd %f14, %f30
43944!--
43945fmovs %f19, %f0
43946fmovd %f34, %f18
43947fmovs %f19, %f1
43948
43949P4007: !_MEMBAR (FP)
43950
43951P4008: !_LD [3] (Int) (Loop exit)
43952lduw [%i1 + 0], %o5
43953! move %o5(lower) -> %o4(lower)
43954or %o5, %o4, %o4
43955!---- flushing int results buffer----
43956mov %o0, %l5
43957mov %o1, %l5
43958mov %o2, %l5
43959mov %o3, %l5
43960mov %o4, %l5
43961!---- flushing fp results buffer to %f30 ----
43962fmovd %f0, %f30
43963!--
43964
43965sethi %hi(0x400000), %l3
43966add %i1, %l3, %i1
43967!-- End Aliased access: base register for region 1 (%i1) restored
43968loop_exit_3_0:
43969sub %l2, 1, %l2
43970cmp %l2, 0
43971bg loop_entry_3_0
43972nop
43973
43974P4009: !_MEMBAR (Int)
43975membar #StoreLoad
43976
43977END_NODES3: ! Test instruction sequence for CPU 3 ends
43978sethi %hi(0xdead0e0f), %l6
43979or %l6, %lo(0xdead0e0f), %l6
43980! move %l6(lower) -> %o0(upper)
43981sllx %l6, 32, %o0
43982sethi %hi(0xdead0e0f), %l6
43983or %l6, %lo(0xdead0e0f), %l6
43984stw %l6, [%i5]
43985ld [%i5], %f0
43986!---- flushing int results buffer----
43987mov %o0, %l5
43988!---- flushing fp results buffer to %f30 ----
43989fmovs %f0, %f30
43990!--
43991
43992restore
43993retl
43994nop
43995!-----------------
43996
43997! register usage:
43998! %i0 %i1 : base registers for first 2 regions
43999! %i2 %i3 : cache registers for 8 regions
44000! %i4 fixed pointer to per-cpu results area
44001! %l1 moving pointer to per-cpu FP results area
44002! %o7 moving pointer to per-cpu integer results area
44003! %i5 pointer to per-cpu private area
44004! %l0 holds lfsr, used as source of random bits
44005! %l2 loop count register
44006! %f16 running counter for unique fp store values
44007! %f17 holds increment value for fp counter
44008! %l4 running counter for unique integer store values (increment value is always 1)
44009! %l5 move-to register for load values (simulation only)
44010! %f30 move-to register for FP values (simulation only)
44011! %i4 holds the instructions count which is used for interrupt ordering
44012! %i4 holds the thread_id (OBP only)
44013! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage
44014! %l3 %l6 %l7 %o5 : 4 temporary registers
44015! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
44016! %f0-f15 FP results buffer registers
44017! %f32-f47 FP block load/store registers
44018
44019func4:
44020! instruction sequence begins
44021save %sp, -192, %sp
44022
44023! Force %i0-%i3 to be 64-byte aligned
44024add %i0, 63, %i0
44025andn %i0, 63, %i0
44026
44027add %i1, 63, %i1
44028andn %i1, 63, %i1
44029
44030add %i2, 63, %i2
44031andn %i2, 63, %i2
44032
44033add %i3, 63, %i3
44034andn %i3, 63, %i3
44035
44036add %i4, 63, %i4
44037andn %i4, 63, %i4
44038
44039add %i5, 63, %i5
44040andn %i5, 63, %i5
44041
44042
44043! Initialize pointer to FP load results area
44044mov %i4, %l1
44045
44046! Initialize pointer to integer load results area
44047sethi %hi(0x80000), %o7
44048or %o7, %lo(0x80000), %o7
44049add %o7, %l1, %o7
44050
44051! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info
44052mov 0x0, %i4
44053
44054! Initialize %f0-%f62 to 0xdeadbee0deadbee1
44055sethi %hi(0xdeadbee0), %l3
44056or %l3, %lo(0xdeadbee0), %l3
44057stw %l3, [%i5]
44058sethi %hi(0xdeadbee1), %l3
44059or %l3, %lo(0xdeadbee1), %l3
44060stw %l3, [%i5+4]
44061ldd [%i5], %f0
44062fmovd %f0, %f2
44063fmovd %f0, %f4
44064fmovd %f0, %f6
44065fmovd %f0, %f8
44066fmovd %f0, %f10
44067fmovd %f0, %f12
44068fmovd %f0, %f14
44069fmovd %f0, %f16
44070fmovd %f0, %f18
44071fmovd %f0, %f20
44072fmovd %f0, %f22
44073fmovd %f0, %f24
44074fmovd %f0, %f26
44075fmovd %f0, %f28
44076fmovd %f0, %f30
44077fmovd %f0, %f32
44078fmovd %f0, %f34
44079fmovd %f0, %f36
44080fmovd %f0, %f38
44081fmovd %f0, %f40
44082fmovd %f0, %f42
44083fmovd %f0, %f44
44084fmovd %f0, %f46
44085fmovd %f0, %f48
44086fmovd %f0, %f50
44087fmovd %f0, %f52
44088fmovd %f0, %f54
44089fmovd %f0, %f56
44090fmovd %f0, %f58
44091fmovd %f0, %f60
44092fmovd %f0, %f62
44093
44094! Signature for extract_loads script to start extracting load values for this stream
44095sethi %hi(0x04deade1), %l3
44096or %l3, %lo(0x04deade1), %l3
44097stw %l3, [%i5]
44098ld [%i5], %f16
44099
44100! Initialize running integer counter in register %l4
44101sethi %hi(0x2000001), %l4
44102or %l4, %lo(0x2000001), %l4
44103
44104! Initialize running FP counter in register %f16
44105sethi %hi(0x41800001), %l3
44106or %l3, %lo(0x41800001), %l3
44107stw %l3, [%i5]
44108ld [%i5], %f16
44109
44110! Initialize FP counter increment value in register %f17 (constant)
44111sethi %hi(0x36000000), %l3
44112or %l3, %lo(0x36000000), %l3
44113stw %l3, [%i5]
44114ld [%i5], %f17
44115
44116! Initialize LFSR to 0x5079^4
44117sethi %hi(0x5079), %l0
44118or %l0, %lo(0x5079), %l0
44119mulx %l0, %l0, %l0
44120mulx %l0, %l0, %l0
44121
44122BEGIN_NODES4: ! Test instruction sequence for ISTREAM 4 begins
44123
44124P4010: !_PREFETCH [22] (Int) (Loop entry) (LE)
44125sethi %hi(0x1), %l2
44126or %l2, %lo(0x1), %l2
44127loop_entry_4_0:
44128wr %g0, 0x88, %asi
44129sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
44130sub %i0, %i2, %i2
44131prefetcha [%i2 + 4] %asi, 22
44132
44133P4011: !_MEMBAR (FP)
44134membar #StoreLoad
44135
44136P4012: !_BLD [15] (FP)
44137wr %g0, 0xf0, %asi
44138sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
44139sub %i0, %i3, %i3
44140ldda [%i3 + 0] %asi, %f0
44141membar #Sync
44142! 3 addresses covered
44143fmovs %f3, %f2
44144
44145P4013: !_MEMBAR (FP)
44146
44147P4014: !_SWAP [12] (maybe <- 0x2000001) (Int)
44148sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
44149sub %i0, %i2, %i2
44150mov %l4, %o0
44151swap [%i2 + 0], %o0
44152! move %o0(lower) -> %o0(upper)
44153sllx %o0, 32, %o0
44154add %l4, 1, %l4
44155
44156P4015: !_DWLD [10] (Int) (LE)
44157wr %g0, 0x88, %asi
44158sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
44159sub %i0, %i3, %i3
44160ldxa [%i3 + 0] %asi, %l6
44161! move %l6(lower) -> %o0(lower)
44162srl %l6, 0, %l3
44163or %l3, %o0, %o0
44164! move %l6(upper) -> %o1(upper)
44165or %l6, %g0, %o1
44166
44167P4016: !_REPLACEMENT [3] (Int)
44168sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
44169sub %i0, %i2, %i2
44170sethi %hi(0x20000), %l7
44171ld [%i2+0], %l3
44172st %l3, [%i2+0]
44173add %i2, %l7, %o5
44174ld [%o5+0], %l3
44175st %l3, [%o5+0]
44176add %o5, %l7, %o5
44177ld [%o5+0], %l3
44178st %l3, [%o5+0]
44179add %o5, %l7, %o5
44180ld [%o5+0], %l3
44181st %l3, [%o5+0]
44182add %o5, %l7, %o5
44183ld [%o5+0], %l3
44184st %l3, [%o5+0]
44185add %o5, %l7, %o5
44186ld [%o5+0], %l3
44187st %l3, [%o5+0]
44188add %o5, %l7, %o5
44189ld [%o5+0], %l3
44190st %l3, [%o5+0]
44191add %o5, %l7, %o5
44192ld [%o5+0], %l3
44193st %l3, [%o5+0]
44194
44195P4017: !_ST [13] (maybe <- 0x2000002) (Int)
44196sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
44197sub %i0, %i3, %i3
44198stw %l4, [%i3 + 4 ]
44199add %l4, 1, %l4
44200
44201P4018: !_PREFETCH [2] (Int)
44202prefetch [%i0 + 12], 22
44203
44204P4019: !_MEMBAR (FP)
44205
44206P4020: !_BSTC [3] (maybe <- 0x41800001) (FP)
44207wr %g0, 0xe0, %asi
44208! preparing store val #0, next val will be in f32
44209fmovs %f16, %f20
44210fadds %f16, %f17, %f16
44211! preparing store val #1, next val will be in f33
44212fmovs %f16, %f21
44213fadds %f16, %f17, %f16
44214! preparing store val #2, next val will be in f35
44215fmovd %f20, %f32
44216fmovs %f16, %f21
44217fadds %f16, %f17, %f16
44218fmovd %f20, %f34
44219membar #Sync
44220stda %f32, [%i1 + 0 ] %asi
44221
44222P4021: !_MEMBAR (FP)
44223membar #StoreLoad
44224
44225P4022: !_SWAP [23] (maybe <- 0x2000003) (Int)
44226sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
44227sub %i0, %i2, %i2
44228mov %l4, %l6
44229swap [%i2 + 12], %l6
44230! move %l6(lower) -> %o1(lower)
44231srlx %o1, 32, %o1
44232sllx %o1, 32, %o1
44233srl %l6, 0, %o5
44234or %o5, %o1, %o1
44235add %l4, 1, %l4
44236
44237P4023: !_MEMBAR (FP)
44238membar #StoreLoad
44239
44240P4024: !_BLD [6] (FP)
44241wr %g0, 0xf0, %asi
44242sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
44243add %i0, %i3, %i3
44244ldda [%i3 + 0] %asi, %f32
44245membar #Sync
44246! 3 addresses covered
44247fmovd %f32, %f18
44248fmovs %f18, %f3
44249fmovs %f19, %f4
44250fmovd %f34, %f18
44251fmovs %f19, %f5
44252
44253P4025: !_MEMBAR (FP)
44254
44255P4026: !_BSTC [6] (maybe <- 0x41800004) (FP)
44256wr %g0, 0xe0, %asi
44257! preparing store val #0, next val will be in f32
44258fmovs %f16, %f20
44259fadds %f16, %f17, %f16
44260! preparing store val #1, next val will be in f33
44261fmovs %f16, %f21
44262fadds %f16, %f17, %f16
44263! preparing store val #2, next val will be in f35
44264fmovd %f20, %f32
44265fmovs %f16, %f21
44266fadds %f16, %f17, %f16
44267fmovd %f20, %f34
44268membar #Sync
44269stda %f32, [%i3 + 0 ] %asi
44270
44271P4027: !_MEMBAR (FP)
44272membar #StoreLoad
44273
44274P4028: !_DWST [12] (maybe <- 0x2000004) (Int)
44275sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
44276sub %i0, %i2, %i2
44277sllx %l4, 32, %l6
44278add %l4, 1, %l4
44279or %l6, %l4, %l6
44280stx %l6, [%i2 + 0]
44281add %l4, 1, %l4
44282
44283P4029: !_DWST [17] (maybe <- 0x2000006) (Int)
44284sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
44285sub %i0, %i3, %i3
44286mov %l4, %l3
44287stx %l3, [%i3 + 8]
44288add %l4, 1, %l4
44289
44290P4030: !_CASX [4] (maybe <- 0x2000007) (Int)
44291ldx [%i1], %o2
44292! move %o2(upper) -> %o2(upper)
44293! move %o2(lower) -> %o2(lower)
44294mov %o2, %o5
44295sllx %l4, 32, %o3
44296add %l4, 1, %l4
44297or %l4, %o3, %o3
44298casx [%i1], %o5, %o3
44299! move %o3(upper) -> %o3(upper)
44300! move %o3(lower) -> %o3(lower)
44301add %l4, 1, %l4
44302
44303P4031: !_ST_BINIT [16] (maybe <- 0x2000009) (Int)
44304wr %g0, 0xe2, %asi
44305stwa %l4, [%i3 + 4] %asi
44306add %l4, 1, %l4
44307
44308P4032: !_MEMBAR (Int)
44309membar #StoreLoad
44310
44311P4033: !_LDD [2] (Int)
44312ldd [%i0 + 8], %l6
44313! move %l7(lower) -> %o4(upper)
44314sllx %l7, 32, %o4
44315
44316P4034: !_CASX [22] (maybe <- 0x200000a) (Int)
44317sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
44318sub %i0, %i2, %i2
44319ldx [%i2], %o5
44320! move %o5(upper) -> %o4(lower)
44321srlx %o5, 32, %l3
44322or %l3, %o4, %o4
44323!---- flushing int results buffer----
44324mov %o0, %l5
44325mov %o1, %l5
44326mov %o2, %l5
44327mov %o3, %l5
44328mov %o4, %l5
44329! move %o5(lower) -> %o0(upper)
44330sllx %o5, 32, %o0
44331mov %o5, %l3
44332sllx %l4, 32, %o5
44333add %l4, 1, %l4
44334or %l4, %o5, %o5
44335casx [%i2], %l3, %o5
44336! move %o5(upper) -> %o0(lower)
44337srlx %o5, 32, %l3
44338or %l3, %o0, %o0
44339! move %o5(lower) -> %o1(upper)
44340sllx %o5, 32, %o1
44341add %l4, 1, %l4
44342
44343P4035: !_ST [0] (maybe <- 0x41800007) (FP)
44344! preparing store val #0, next val will be in f20
44345fmovs %f16, %f20
44346fadds %f16, %f17, %f16
44347st %f20, [%i0 + 0 ]
44348
44349P4036: !_ST_BINIT [9] (maybe <- 0x200000c) (Int) (LE)
44350wr %g0, 0xea, %asi
44351sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
44352sub %i0, %i3, %i3
44353! Change single-word-level endianess (big endian <-> little endian)
44354sethi %hi(0xff00ff00), %l3
44355or %l3, %lo(0xff00ff00), %l3
44356and %l4, %l3, %l6
44357srl %l6, 8, %l6
44358sll %l4, 8, %o5
44359and %o5, %l3, %o5
44360or %o5, %l6, %o5
44361srl %o5, 16, %l6
44362sll %o5, 16, %o5
44363srl %o5, 0, %o5
44364or %o5, %l6, %o5
44365stwa %o5, [%i3 + 0] %asi
44366add %l4, 1, %l4
44367
44368P4037: !_MEMBAR (Int) (LE)
44369membar #StoreLoad
44370
44371P4038: !_BLD [1] (FP) (Branch target of P4477)
44372wr %g0, 0xf0, %asi
44373ldda [%i0 + 0] %asi, %f32
44374membar #Sync
44375! 3 addresses covered
44376fmovd %f32, %f6
44377fmovd %f34, %f18
44378fmovs %f19, %f8
44379ba P4039
44380nop
44381
44382TARGET4477:
44383ba RET4477
44384nop
44385
44386
44387P4039: !_MEMBAR (FP)
44388
44389P4040: !_ST [3] (maybe <- 0x200000d) (Int)
44390stw %l4, [%i1 + 0 ]
44391add %l4, 1, %l4
44392
44393P4041: !_MEMBAR (FP) (CBR) (Branch target of P4041)
44394membar #StoreLoad
44395
44396! cbranch
44397andcc %l0, 1, %g0
44398be,pn %xcc, TARGET4041
44399nop
44400RET4041:
44401
44402! lfsr step begin
44403srlx %l0, 1, %l6
44404xnor %l6, %l0, %l6
44405sllx %l6, 63, %l6
44406or %l6, %l0, %l0
44407srlx %l0, 1, %l0
44408
44409ba P4042
44410nop
44411
44412TARGET4041:
44413ba RET4041
44414nop
44415
44416
44417P4042: !_BLD [9] (FP)
44418wr %g0, 0xf0, %asi
44419ldda [%i3 + 0] %asi, %f32
44420membar #Sync
44421! 3 addresses covered
44422fmovd %f32, %f18
44423fmovs %f18, %f9
44424fmovs %f19, %f10
44425fmovd %f34, %f18
44426fmovs %f19, %f11
44427
44428P4043: !_MEMBAR (FP) (CBR)
44429
44430! cbranch
44431andcc %l0, 1, %g0
44432be,pn %xcc, TARGET4043
44433nop
44434RET4043:
44435
44436! lfsr step begin
44437srlx %l0, 1, %l7
44438xnor %l7, %l0, %l7
44439sllx %l7, 63, %l7
44440or %l7, %l0, %l0
44441srlx %l0, 1, %l0
44442
44443
44444P4044: !_PREFETCH [16] (Int)
44445sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
44446sub %i0, %i2, %i2
44447prefetch [%i2 + 4], 3
44448
44449P4045: !_LD [15] (Int) (LE)
44450wr %g0, 0x88, %asi
44451lduwa [%i2 + 0] %asi, %l3
44452! move %l3(lower) -> %o1(lower)
44453or %l3, %o1, %o1
44454
44455P4046: !_CAS [9] (maybe <- 0x200000e) (Int)
44456lduw [%i3], %o2
44457mov %o2, %l6
44458! move %l6(lower) -> %o2(upper)
44459sllx %l6, 32, %o2
44460mov %l4, %l3
44461cas [%i3], %l6, %l3
44462! move %l3(lower) -> %o2(lower)
44463srl %l3, 0, %l6
44464or %l6, %o2, %o2
44465add %l4, 1, %l4
44466
44467P4047: !_MEMBAR (FP)
44468
44469P4048: !_BST [10] (maybe <- 0x41800008) (FP)
44470wr %g0, 0xf0, %asi
44471! preparing store val #0, next val will be in f32
44472fmovs %f16, %f20
44473fadds %f16, %f17, %f16
44474! preparing store val #1, next val will be in f33
44475fmovs %f16, %f21
44476fadds %f16, %f17, %f16
44477! preparing store val #2, next val will be in f35
44478fmovd %f20, %f32
44479fmovs %f16, %f21
44480fadds %f16, %f17, %f16
44481fmovd %f20, %f34
44482membar #Sync
44483stda %f32, [%i3 + 0 ] %asi
44484
44485P4049: !_MEMBAR (FP)
44486membar #StoreLoad
44487
44488P4050: !_DWST [20] (maybe <- 0x200000f) (Int) (LE)
44489wr %g0, 0x88, %asi
44490sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
44491sub %i0, %i3, %i3
44492! Change single-word-level endianess (big endian <-> little endian)
44493sethi %hi(0xff00ff00), %l3
44494or %l3, %lo(0xff00ff00), %l3
44495and %l4, %l3, %l7
44496srl %l7, 8, %l7
44497sll %l4, 8, %l6
44498and %l6, %l3, %l6
44499or %l6, %l7, %l6
44500srl %l6, 16, %l7
44501sll %l6, 16, %l6
44502srl %l6, 0, %l6
44503or %l6, %l7, %l6
44504sllx %l6, 32, %l6
44505stxa %l6, [%i3 + 8 ] %asi
44506add %l4, 1, %l4
44507
44508P4051: !_ST_BINIT [16] (maybe <- 0x2000010) (Int)
44509wr %g0, 0xe2, %asi
44510stwa %l4, [%i2 + 4] %asi
44511add %l4, 1, %l4
44512
44513P4052: !_MEMBAR (Int)
44514membar #StoreLoad
44515
44516P4053: !_DWST [11] (maybe <- 0x2000011) (Int)
44517sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
44518sub %i0, %i2, %i2
44519mov %l4, %l7
44520stx %l7, [%i2 + 8]
44521add %l4, 1, %l4
44522
44523P4054: !_ST_BINIT [17] (maybe <- 0x2000012) (Int)
44524wr %g0, 0xe2, %asi
44525sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
44526sub %i0, %i3, %i3
44527stwa %l4, [%i3 + 12] %asi
44528add %l4, 1, %l4
44529
44530P4055: !_MEMBAR (Int)
44531membar #StoreLoad
44532
44533P4056: !_LDD [14] (Int)
44534sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
44535sub %i0, %i2, %i2
44536ldd [%i2 + 8], %l6
44537! move %l7(lower) -> %o3(upper)
44538sllx %l7, 32, %o3
44539
44540P4057: !_ST [6] (maybe <- 0x2000013) (Int) (LE)
44541wr %g0, 0x88, %asi
44542sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
44543add %i0, %i3, %i3
44544! Change single-word-level endianess (big endian <-> little endian)
44545sethi %hi(0xff00ff00), %l6
44546or %l6, %lo(0xff00ff00), %l6
44547and %l4, %l6, %l7
44548srl %l7, 8, %l7
44549sll %l4, 8, %l3
44550and %l3, %l6, %l3
44551or %l3, %l7, %l3
44552srl %l3, 16, %l7
44553sll %l3, 16, %l3
44554srl %l3, 0, %l3
44555or %l3, %l7, %l3
44556stwa %l3, [%i3 + 0] %asi
44557add %l4, 1, %l4
44558
44559P4058: !_DWST [20] (maybe <- 0x2000014) (Int)
44560sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
44561sub %i0, %i2, %i2
44562mov %l4, %o5
44563stx %o5, [%i2 + 8]
44564add %l4, 1, %l4
44565
44566P4059: !_MEMBAR (FP)
44567
44568P4060: !_BSTC [20] (maybe <- 0x4180000b) (FP)
44569wr %g0, 0xe0, %asi
44570! preparing store val #0, next val will be in f32
44571fmovs %f16, %f20
44572fadds %f16, %f17, %f16
44573! preparing store val #1, next val will be in f33
44574fmovs %f16, %f21
44575fadds %f16, %f17, %f16
44576! preparing store val #2, next val will be in f35
44577fmovd %f20, %f32
44578fmovs %f16, %f21
44579fadds %f16, %f17, %f16
44580fmovd %f20, %f34
44581membar #Sync
44582stda %f32, [%i2 + 0 ] %asi
44583
44584P4061: !_MEMBAR (FP)
44585membar #StoreLoad
44586
44587P4062: !_ST_BINIT [5] (maybe <- 0x2000015) (Int) (Branch target of P4766)
44588wr %g0, 0xe2, %asi
44589stwa %l4, [%i1 + 12] %asi
44590add %l4, 1, %l4
44591ba P4063
44592nop
44593
44594TARGET4766:
44595ba RET4766
44596nop
44597
44598
44599P4063: !_MEMBAR (Int)
44600membar #StoreLoad
44601
44602P4064: !_CASX [1] (maybe <- 0x2000016) (Int)
44603ldx [%i0], %o5
44604! move %o5(upper) -> %o3(lower)
44605srlx %o5, 32, %l3
44606or %l3, %o3, %o3
44607! move %o5(lower) -> %o4(upper)
44608sllx %o5, 32, %o4
44609mov %o5, %l3
44610sllx %l4, 32, %o5
44611add %l4, 1, %l4
44612or %l4, %o5, %o5
44613casx [%i0], %l3, %o5
44614! move %o5(upper) -> %o4(lower)
44615srlx %o5, 32, %l3
44616or %l3, %o4, %o4
44617!---- flushing int results buffer----
44618mov %o0, %l5
44619mov %o1, %l5
44620mov %o2, %l5
44621mov %o3, %l5
44622mov %o4, %l5
44623! move %o5(lower) -> %o0(upper)
44624sllx %o5, 32, %o0
44625add %l4, 1, %l4
44626
44627P4065: !_ST [11] (maybe <- 0x2000018) (Int) (CBR)
44628sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
44629sub %i0, %i3, %i3
44630stw %l4, [%i3 + 12 ]
44631add %l4, 1, %l4
44632
44633! cbranch
44634andcc %l0, 1, %g0
44635be,pn %xcc, TARGET4065
44636nop
44637RET4065:
44638
44639! lfsr step begin
44640srlx %l0, 1, %o5
44641xnor %o5, %l0, %o5
44642sllx %o5, 63, %o5
44643or %o5, %l0, %l0
44644srlx %l0, 1, %l0
44645
44646
44647P4066: !_LD [5] (Int) (LE) (Branch target of P4517)
44648wr %g0, 0x88, %asi
44649lduwa [%i1 + 12] %asi, %l6
44650! move %l6(lower) -> %o0(lower)
44651or %l6, %o0, %o0
44652ba P4067
44653nop
44654
44655TARGET4517:
44656ba RET4517
44657nop
44658
44659
44660P4067: !_LD [23] (Int) (LE)
44661wr %g0, 0x88, %asi
44662sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
44663sub %i0, %i2, %i2
44664lduwa [%i2 + 12] %asi, %o1
44665! move %o1(lower) -> %o1(upper)
44666sllx %o1, 32, %o1
44667
44668P4068: !_LD [23] (Int)
44669lduw [%i2 + 12], %l6
44670! move %l6(lower) -> %o1(lower)
44671or %l6, %o1, %o1
44672
44673P4069: !_MEMBAR (FP)
44674
44675P4070: !_BST [6] (maybe <- 0x4180000e) (FP)
44676wr %g0, 0xf0, %asi
44677sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
44678add %i0, %i3, %i3
44679! preparing store val #0, next val will be in f32
44680fmovs %f16, %f20
44681fadds %f16, %f17, %f16
44682! preparing store val #1, next val will be in f33
44683fmovs %f16, %f21
44684fadds %f16, %f17, %f16
44685! preparing store val #2, next val will be in f35
44686fmovd %f20, %f32
44687fmovs %f16, %f21
44688fadds %f16, %f17, %f16
44689fmovd %f20, %f34
44690membar #Sync
44691stda %f32, [%i3 + 0 ] %asi
44692
44693P4071: !_MEMBAR (FP)
44694membar #StoreLoad
44695
44696P4072: !_DWLD [18] (Int)
44697sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
44698sub %i0, %i2, %i2
44699ldx [%i2 + 0], %o2
44700! move %o2(upper) -> %o2(upper)
44701! move %o2(lower) -> %o2(lower)
44702
44703P4073: !_MEMBAR (FP)
44704membar #StoreLoad
44705
44706P4074: !_BLD [8] (FP)
44707wr %g0, 0xf0, %asi
44708ldda [%i3 + 0] %asi, %f32
44709membar #Sync
44710! 3 addresses covered
44711fmovd %f32, %f12
44712fmovd %f34, %f18
44713fmovs %f19, %f14
44714
44715P4075: !_MEMBAR (FP)
44716
44717P4076: !_ST [16] (maybe <- 0x2000019) (Int)
44718sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
44719sub %i0, %i3, %i3
44720stw %l4, [%i3 + 4 ]
44721add %l4, 1, %l4
44722
44723P4077: !_PREFETCH [21] (Int)
44724sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
44725sub %i0, %i2, %i2
44726prefetch [%i2 + 0], 29
44727
44728P4078: !_DWST [8] (maybe <- 0x200001a) (Int)
44729sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
44730add %i0, %i3, %i3
44731mov %l4, %o5
44732stx %o5, [%i3 + 8]
44733add %l4, 1, %l4
44734
44735P4079: !_MEMBAR (FP)
44736membar #StoreLoad
44737
44738P4080: !_BLD [14] (FP)
44739wr %g0, 0xf0, %asi
44740sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
44741sub %i0, %i2, %i2
44742ldda [%i2 + 0] %asi, %f32
44743membar #Sync
44744! 3 addresses covered
44745fmovd %f32, %f18
44746fmovs %f18, %f15
44747!---- flushing fp results buffer to %f30 ----
44748fmovd %f0, %f30
44749fmovd %f2, %f30
44750fmovd %f4, %f30
44751fmovd %f6, %f30
44752fmovd %f8, %f30
44753fmovd %f10, %f30
44754fmovd %f12, %f30
44755fmovd %f14, %f30
44756!--
44757fmovs %f19, %f0
44758fmovd %f34, %f18
44759fmovs %f19, %f1
44760
44761P4081: !_MEMBAR (FP) (CBR)
44762
44763! cbranch
44764andcc %l0, 1, %g0
44765be,pt %xcc, TARGET4081
44766nop
44767RET4081:
44768
44769! lfsr step begin
44770srlx %l0, 1, %l7
44771xnor %l7, %l0, %l7
44772sllx %l7, 63, %l7
44773or %l7, %l0, %l0
44774srlx %l0, 1, %l0
44775
44776
44777P4082: !_DWST [6] (maybe <- 0x200001b) (Int)
44778sllx %l4, 32, %o5
44779add %l4, 1, %l4
44780or %o5, %l4, %o5
44781stx %o5, [%i3 + 0]
44782add %l4, 1, %l4
44783
44784P4083: !_MEMBAR (FP)
44785membar #StoreLoad
44786
44787P4084: !_BLD [3] (FP)
44788wr %g0, 0xf0, %asi
44789ldda [%i1 + 0] %asi, %f32
44790membar #Sync
44791! 3 addresses covered
44792fmovd %f32, %f2
44793fmovd %f34, %f18
44794fmovs %f19, %f4
44795
44796P4085: !_MEMBAR (FP) (Branch target of P4276)
44797ba P4086
44798nop
44799
44800TARGET4276:
44801ba RET4276
44802nop
44803
44804
44805P4086: !_CASX [9] (maybe <- 0x200001d) (Int)
44806sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
44807sub %i0, %i3, %i3
44808ldx [%i3], %o3
44809! move %o3(upper) -> %o3(upper)
44810! move %o3(lower) -> %o3(lower)
44811mov %o3, %l7
44812sllx %l4, 32, %o4
44813add %l4, 1, %l4
44814or %l4, %o4, %o4
44815casx [%i3], %l7, %o4
44816! move %o4(upper) -> %o4(upper)
44817! move %o4(lower) -> %o4(lower)
44818!---- flushing int results buffer----
44819mov %o0, %l5
44820mov %o1, %l5
44821mov %o2, %l5
44822mov %o3, %l5
44823mov %o4, %l5
44824add %l4, 1, %l4
44825
44826P4087: !_CAS [18] (maybe <- 0x200001f) (Int)
44827sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
44828sub %i0, %i2, %i2
44829lduw [%i2], %o0
44830mov %o0, %l7
44831! move %l7(lower) -> %o0(upper)
44832sllx %l7, 32, %o0
44833mov %l4, %l6
44834cas [%i2], %l7, %l6
44835! move %l6(lower) -> %o0(lower)
44836srl %l6, 0, %l7
44837or %l7, %o0, %o0
44838add %l4, 1, %l4
44839
44840P4088: !_ST_BINIT [3] (maybe <- 0x2000020) (Int)
44841wr %g0, 0xe2, %asi
44842stwa %l4, [%i1 + 0] %asi
44843add %l4, 1, %l4
44844
44845P4089: !_MEMBAR (Int)
44846
44847P4090: !_BSTC [8] (maybe <- 0x41800011) (FP)
44848wr %g0, 0xe0, %asi
44849sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
44850add %i0, %i3, %i3
44851! preparing store val #0, next val will be in f32
44852fmovs %f16, %f20
44853fadds %f16, %f17, %f16
44854! preparing store val #1, next val will be in f33
44855fmovs %f16, %f21
44856fadds %f16, %f17, %f16
44857! preparing store val #2, next val will be in f35
44858fmovd %f20, %f32
44859fmovs %f16, %f21
44860fadds %f16, %f17, %f16
44861fmovd %f20, %f34
44862membar #Sync
44863stda %f32, [%i3 + 0 ] %asi
44864
44865P4091: !_MEMBAR (FP)
44866membar #StoreLoad
44867
44868P4092: !_SWAP [6] (maybe <- 0x2000021) (Int)
44869mov %l4, %o1
44870swap [%i3 + 0], %o1
44871! move %o1(lower) -> %o1(upper)
44872sllx %o1, 32, %o1
44873add %l4, 1, %l4
44874
44875P4093: !_ST_BINIT [5] (maybe <- 0x2000022) (Int) (CBR)
44876wr %g0, 0xe2, %asi
44877stwa %l4, [%i1 + 12] %asi
44878add %l4, 1, %l4
44879
44880! cbranch
44881andcc %l0, 1, %g0
44882be,pt %xcc, TARGET4093
44883nop
44884RET4093:
44885
44886! lfsr step begin
44887srlx %l0, 1, %l7
44888xnor %l7, %l0, %l7
44889sllx %l7, 63, %l7
44890or %l7, %l0, %l0
44891srlx %l0, 1, %l0
44892
44893
44894P4094: !_MEMBAR (Int)
44895membar #StoreLoad
44896
44897P4095: !_REPLACEMENT [4] (Int)
44898sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
44899add %i0, %i2, %i2
44900sethi %hi(0x20000), %o5
44901ld [%i2+4], %l6
44902st %l6, [%i2+4]
44903add %i2, %o5, %l3
44904ld [%l3+4], %l6
44905st %l6, [%l3+4]
44906add %l3, %o5, %l3
44907ld [%l3+4], %l6
44908st %l6, [%l3+4]
44909add %l3, %o5, %l3
44910ld [%l3+4], %l6
44911st %l6, [%l3+4]
44912add %l3, %o5, %l3
44913ld [%l3+4], %l6
44914st %l6, [%l3+4]
44915add %l3, %o5, %l3
44916ld [%l3+4], %l6
44917st %l6, [%l3+4]
44918add %l3, %o5, %l3
44919ld [%l3+4], %l6
44920st %l6, [%l3+4]
44921add %l3, %o5, %l3
44922ld [%l3+4], %l6
44923st %l6, [%l3+4]
44924
44925P4096: !_LDD [19] (Int)
44926sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
44927sub %i0, %i3, %i3
44928ldd [%i3 + 0], %l6
44929! move %l6(lower) -> %o1(lower)
44930or %l6, %o1, %o1
44931! move %l7(lower) -> %o2(upper)
44932sllx %l7, 32, %o2
44933
44934P4097: !_CAS [20] (maybe <- 0x2000023) (Int)
44935add %i3, 12, %l6
44936lduw [%l6], %o5
44937mov %o5, %l3
44938! move %l3(lower) -> %o2(lower)
44939or %l3, %o2, %o2
44940mov %l4, %o3
44941cas [%l6], %l3, %o3
44942! move %o3(lower) -> %o3(upper)
44943sllx %o3, 32, %o3
44944add %l4, 1, %l4
44945
44946P4098: !_CASX [8] (maybe <- 0x2000024) (Int)
44947sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
44948add %i0, %i2, %i2
44949add %i2, 8, %l6
44950ldx [%l6], %o5
44951! move %o5(upper) -> %o3(lower)
44952srlx %o5, 32, %l3
44953or %l3, %o3, %o3
44954! move %o5(lower) -> %o4(upper)
44955sllx %o5, 32, %o4
44956mov %o5, %l3
44957mov %l4, %o5
44958casx [%l6], %l3, %o5
44959! move %o5(upper) -> %o4(lower)
44960srlx %o5, 32, %l3
44961or %l3, %o4, %o4
44962!---- flushing int results buffer----
44963mov %o0, %l5
44964mov %o1, %l5
44965mov %o2, %l5
44966mov %o3, %l5
44967mov %o4, %l5
44968! move %o5(lower) -> %o0(upper)
44969sllx %o5, 32, %o0
44970add %l4, 1, %l4
44971
44972P4099: !_LDD [18] (Int)
44973ldd [%i3 + 0], %l6
44974! move %l6(lower) -> %o0(lower)
44975or %l6, %o0, %o0
44976! move %l7(lower) -> %o1(upper)
44977sllx %l7, 32, %o1
44978
44979P4100: !_MEMBAR (FP)
44980
44981P4101: !_BSTC [13] (maybe <- 0x41800014) (FP) (CBR)
44982wr %g0, 0xe0, %asi
44983sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
44984sub %i0, %i3, %i3
44985! preparing store val #0, next val will be in f32
44986fmovs %f16, %f20
44987fadds %f16, %f17, %f16
44988! preparing store val #1, next val will be in f33
44989fmovs %f16, %f21
44990fadds %f16, %f17, %f16
44991! preparing store val #2, next val will be in f35
44992fmovd %f20, %f32
44993fmovs %f16, %f21
44994fadds %f16, %f17, %f16
44995fmovd %f20, %f34
44996membar #Sync
44997stda %f32, [%i3 + 0 ] %asi
44998
44999! cbranch
45000andcc %l0, 1, %g0
45001be,pt %xcc, TARGET4101
45002nop
45003RET4101:
45004
45005! lfsr step begin
45006srlx %l0, 1, %o5
45007xnor %o5, %l0, %o5
45008sllx %o5, 63, %o5
45009or %o5, %l0, %l0
45010srlx %l0, 1, %l0
45011
45012
45013P4102: !_MEMBAR (FP)
45014membar #StoreLoad
45015
45016P4103: !_LDD [2] (Int)
45017ldd [%i0 + 8], %l6
45018! move %l7(lower) -> %o1(lower)
45019or %l7, %o1, %o1
45020
45021P4104: !_CAS [21] (maybe <- 0x2000025) (Int)
45022sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i2
45023sub %i0, %i2, %i2
45024lduw [%i2], %o2
45025mov %o2, %l3
45026! move %l3(lower) -> %o2(upper)
45027sllx %l3, 32, %o2
45028mov %l4, %o5
45029cas [%i2], %l3, %o5
45030! move %o5(lower) -> %o2(lower)
45031srl %o5, 0, %l3
45032or %l3, %o2, %o2
45033add %l4, 1, %l4
45034
45035P4105: !_MEMBAR (FP) (Branch target of P4443)
45036ba P4106
45037nop
45038
45039TARGET4443:
45040ba RET4443
45041nop
45042
45043
45044P4106: !_BST [23] (maybe <- 0x41800017) (FP)
45045wr %g0, 0xf0, %asi
45046! preparing store val #0, next val will be in f32
45047fmovs %f16, %f20
45048fadds %f16, %f17, %f16
45049! preparing store val #1, next val will be in f33
45050fmovs %f16, %f21
45051fadds %f16, %f17, %f16
45052! preparing store val #2, next val will be in f35
45053fmovd %f20, %f32
45054fmovs %f16, %f21
45055fadds %f16, %f17, %f16
45056fmovd %f20, %f34
45057membar #Sync
45058stda %f32, [%i2 + 0 ] %asi
45059
45060P4107: !_MEMBAR (FP)
45061membar #StoreLoad
45062
45063P4108: !_LD [10] (Int)
45064sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
45065sub %i0, %i3, %i3
45066lduw [%i3 + 4], %o3
45067! move %o3(lower) -> %o3(upper)
45068sllx %o3, 32, %o3
45069
45070P4109: !_ST_BINIT [5] (maybe <- 0x2000026) (Int) (LE)
45071wr %g0, 0xea, %asi
45072! Change single-word-level endianess (big endian <-> little endian)
45073sethi %hi(0xff00ff00), %l7
45074or %l7, %lo(0xff00ff00), %l7
45075and %l4, %l7, %o5
45076srl %o5, 8, %o5
45077sll %l4, 8, %l6
45078and %l6, %l7, %l6
45079or %l6, %o5, %l6
45080srl %l6, 16, %o5
45081sll %l6, 16, %l6
45082srl %l6, 0, %l6
45083or %l6, %o5, %l6
45084stwa %l6, [%i1 + 12] %asi
45085add %l4, 1, %l4
45086
45087P4110: !_MEMBAR (Int) (LE)
45088
45089P4111: !_BST [2] (maybe <- 0x4180001a) (FP)
45090wr %g0, 0xf0, %asi
45091! preparing store val #0, next val will be in f32
45092fmovs %f16, %f20
45093fadds %f16, %f17, %f16
45094! preparing store val #1, next val will be in f33
45095fmovs %f16, %f21
45096fadds %f16, %f17, %f16
45097! preparing store val #2, next val will be in f35
45098fmovd %f20, %f32
45099fmovs %f16, %f21
45100fadds %f16, %f17, %f16
45101fmovd %f20, %f34
45102membar #Sync
45103stda %f32, [%i0 + 0 ] %asi
45104
45105P4112: !_MEMBAR (FP)
45106membar #StoreLoad
45107
45108P4113: !_LD [4] (FP)
45109ld [%i1 + 4], %f5
45110! 1 addresses covered
45111
45112P4114: !_ST_BINIT [11] (maybe <- 0x2000027) (Int) (LE)
45113wr %g0, 0xea, %asi
45114! Change single-word-level endianess (big endian <-> little endian)
45115sethi %hi(0xff00ff00), %l3
45116or %l3, %lo(0xff00ff00), %l3
45117and %l4, %l3, %l6
45118srl %l6, 8, %l6
45119sll %l4, 8, %o5
45120and %o5, %l3, %o5
45121or %o5, %l6, %o5
45122srl %o5, 16, %l6
45123sll %o5, 16, %o5
45124srl %o5, 0, %o5
45125or %o5, %l6, %o5
45126stwa %o5, [%i3 + 12] %asi
45127add %l4, 1, %l4
45128
45129P4115: !_MEMBAR (Int) (LE)
45130membar #StoreLoad
45131
45132P4116: !_ST [16] (maybe <- 0x2000028) (Int)
45133sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
45134sub %i0, %i2, %i2
45135stw %l4, [%i2 + 4 ]
45136add %l4, 1, %l4
45137
45138P4117: !_MEMBAR (FP)
45139
45140P4118: !_BST [0] (maybe <- 0x4180001d) (FP) (Branch target of P4101)
45141wr %g0, 0xf0, %asi
45142! preparing store val #0, next val will be in f32
45143fmovs %f16, %f20
45144fadds %f16, %f17, %f16
45145! preparing store val #1, next val will be in f33
45146fmovs %f16, %f21
45147fadds %f16, %f17, %f16
45148! preparing store val #2, next val will be in f35
45149fmovd %f20, %f32
45150fmovs %f16, %f21
45151fadds %f16, %f17, %f16
45152fmovd %f20, %f34
45153membar #Sync
45154stda %f32, [%i0 + 0 ] %asi
45155ba P4119
45156nop
45157
45158TARGET4101:
45159ba RET4101
45160nop
45161
45162
45163P4119: !_MEMBAR (FP)
45164membar #StoreLoad
45165
45166P4120: !_DWLD [23] (FP)
45167sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS2_O), %i3
45168sub %i0, %i3, %i3
45169ldd [%i3 + 8], %f6
45170! 1 addresses covered
45171fmovs %f7, %f6
45172
45173P4121: !_LD [7] (Int)
45174sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
45175add %i0, %i2, %i2
45176lduw [%i2 + 4], %l6
45177! move %l6(lower) -> %o3(lower)
45178or %l6, %o3, %o3
45179
45180P4122: !_ST [18] (maybe <- 0x2000029) (Int)
45181sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
45182sub %i0, %i3, %i3
45183stw %l4, [%i3 + 0 ]
45184add %l4, 1, %l4
45185
45186P4123: !_LD [17] (FP)
45187sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
45188sub %i0, %i2, %i2
45189ld [%i2 + 12], %f7
45190! 1 addresses covered
45191
45192P4124: !_LDD [2] (Int)
45193ldd [%i0 + 8], %l6
45194! move %l7(lower) -> %o4(upper)
45195sllx %l7, 32, %o4
45196
45197P4125: !_CASX [4] (maybe <- 0x200002a) (Int)
45198ldx [%i1], %o5
45199! move %o5(upper) -> %o4(lower)
45200srlx %o5, 32, %l3
45201or %l3, %o4, %o4
45202!---- flushing int results buffer----
45203mov %o0, %l5
45204mov %o1, %l5
45205mov %o2, %l5
45206mov %o3, %l5
45207mov %o4, %l5
45208! move %o5(lower) -> %o0(upper)
45209sllx %o5, 32, %o0
45210mov %o5, %l3
45211sllx %l4, 32, %o5
45212add %l4, 1, %l4
45213or %l4, %o5, %o5
45214casx [%i1], %l3, %o5
45215! move %o5(upper) -> %o0(lower)
45216srlx %o5, 32, %l3
45217or %l3, %o0, %o0
45218! move %o5(lower) -> %o1(upper)
45219sllx %o5, 32, %o1
45220add %l4, 1, %l4
45221
45222P4126: !_SWAP [4] (maybe <- 0x200002c) (Int)
45223mov %l4, %l7
45224swap [%i1 + 4], %l7
45225! move %l7(lower) -> %o1(lower)
45226srl %l7, 0, %l3
45227or %l3, %o1, %o1
45228add %l4, 1, %l4
45229
45230P4127: !_MEMBAR (FP) (Branch target of P4904)
45231ba P4128
45232nop
45233
45234TARGET4904:
45235ba RET4904
45236nop
45237
45238
45239P4128: !_BSTC [3] (maybe <- 0x41800020) (FP)
45240wr %g0, 0xe0, %asi
45241! preparing store val #0, next val will be in f32
45242fmovs %f16, %f20
45243fadds %f16, %f17, %f16
45244! preparing store val #1, next val will be in f33
45245fmovs %f16, %f21
45246fadds %f16, %f17, %f16
45247! preparing store val #2, next val will be in f35
45248fmovd %f20, %f32
45249fmovs %f16, %f21
45250fadds %f16, %f17, %f16
45251fmovd %f20, %f34
45252membar #Sync
45253stda %f32, [%i1 + 0 ] %asi
45254
45255P4129: !_MEMBAR (FP)
45256membar #StoreLoad
45257
45258P4130: !_ST [0] (maybe <- 0x200002d) (Int)
45259stw %l4, [%i0 + 0 ]
45260add %l4, 1, %l4
45261
45262P4131: !_LDD [18] (Int) (LE)
45263wr %g0, 0x88, %asi
45264ldda [%i3 + 0] %asi, %l6
45265! move %l6(lower) -> %o2(upper)
45266sllx %l6, 32, %o2
45267! move %l7(lower) -> %o2(lower)
45268or %l7, %o2, %o2
45269
45270P4132: !_LDD [10] (Int) (Branch target of P4601)
45271sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
45272sub %i0, %i3, %i3
45273ldd [%i3 + 0], %l6
45274! move %l6(lower) -> %o3(upper)
45275sllx %l6, 32, %o3
45276! move %l7(lower) -> %o3(lower)
45277or %l7, %o3, %o3
45278ba P4133
45279nop
45280
45281TARGET4601:
45282ba RET4601
45283nop
45284
45285
45286P4133: !_PREFETCH [13] (Int)
45287sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
45288sub %i0, %i2, %i2
45289prefetch [%i2 + 4], 3
45290
45291P4134: !_ST [19] (maybe <- 0x200002e) (Int)
45292sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
45293sub %i0, %i3, %i3
45294stw %l4, [%i3 + 4 ]
45295add %l4, 1, %l4
45296
45297P4135: !_DWST [1] (maybe <- 0x200002f) (Int)
45298sllx %l4, 32, %o5
45299add %l4, 1, %l4
45300or %o5, %l4, %o5
45301stx %o5, [%i0 + 0]
45302add %l4, 1, %l4
45303
45304P4136: !_DWST [2] (maybe <- 0x2000031) (Int)
45305mov %l4, %l7
45306stx %l7, [%i0 + 8]
45307add %l4, 1, %l4
45308
45309P4137: !_CAS [21] (maybe <- 0x2000032) (Int)
45310sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
45311sub %i0, %i2, %i2
45312lduw [%i2], %o4
45313mov %o4, %l7
45314! move %l7(lower) -> %o4(upper)
45315sllx %l7, 32, %o4
45316mov %l4, %l6
45317cas [%i2], %l7, %l6
45318! move %l6(lower) -> %o4(lower)
45319srl %l6, 0, %l7
45320or %l7, %o4, %o4
45321!---- flushing int results buffer----
45322mov %o0, %l5
45323mov %o1, %l5
45324mov %o2, %l5
45325mov %o3, %l5
45326mov %o4, %l5
45327add %l4, 1, %l4
45328
45329P4138: !_DWLD [10] (Int)
45330sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
45331sub %i0, %i3, %i3
45332ldx [%i3 + 0], %o0
45333! move %o0(upper) -> %o0(upper)
45334! move %o0(lower) -> %o0(lower)
45335
45336P4139: !_LD [15] (Int)
45337sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
45338sub %i0, %i2, %i2
45339lduw [%i2 + 0], %o1
45340! move %o1(lower) -> %o1(upper)
45341sllx %o1, 32, %o1
45342
45343P4140: !_ST_BINIT [20] (maybe <- 0x2000033) (Int)
45344wr %g0, 0xe2, %asi
45345sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
45346sub %i0, %i3, %i3
45347stwa %l4, [%i3 + 12] %asi
45348add %l4, 1, %l4
45349
45350P4141: !_MEMBAR (Int)
45351membar #StoreLoad
45352
45353P4142: !_PREFETCH [2] (Int)
45354prefetch [%i0 + 12], 22
45355
45356P4143: !_LDD [12] (Int)
45357sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
45358sub %i0, %i2, %i2
45359ldd [%i2 + 0], %l6
45360! move %l6(lower) -> %o1(lower)
45361or %l6, %o1, %o1
45362! move %l7(lower) -> %o2(upper)
45363sllx %l7, 32, %o2
45364
45365P4144: !_DWLD [10] (FP)
45366sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
45367sub %i0, %i3, %i3
45368ldd [%i3 + 0], %f8
45369! 2 addresses covered
45370
45371P4145: !_CAS [18] (maybe <- 0x2000034) (Int)
45372sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
45373sub %i0, %i2, %i2
45374lduw [%i2], %o5
45375mov %o5, %l3
45376! move %l3(lower) -> %o2(lower)
45377or %l3, %o2, %o2
45378mov %l4, %o3
45379cas [%i2], %l3, %o3
45380! move %o3(lower) -> %o3(upper)
45381sllx %o3, 32, %o3
45382add %l4, 1, %l4
45383
45384P4146: !_LDD [12] (Int)
45385sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
45386sub %i0, %i3, %i3
45387ldd [%i3 + 0], %l6
45388! move %l6(lower) -> %o3(lower)
45389or %l6, %o3, %o3
45390! move %l7(lower) -> %o4(upper)
45391sllx %l7, 32, %o4
45392
45393P4147: !_LDD [18] (Int)
45394ldd [%i2 + 0], %l6
45395! move %l6(lower) -> %o4(lower)
45396or %l6, %o4, %o4
45397!---- flushing int results buffer----
45398mov %o0, %l5
45399mov %o1, %l5
45400mov %o2, %l5
45401mov %o3, %l5
45402mov %o4, %l5
45403! move %l7(lower) -> %o0(upper)
45404sllx %l7, 32, %o0
45405
45406P4148: !_DWST_BINIT [7] (maybe <- 0x2000035) (Int)
45407wr %g0, 0xe2, %asi
45408sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
45409add %i0, %i2, %i2
45410sllx %l4, 32, %l3
45411add %l4, 1, %l4
45412or %l3, %l4, %l3
45413stxa %l3, [%i2 + 0] %asi
45414add %l4, 1, %l4
45415
45416P4149: !_MEMBAR (Int)
45417
45418P4150: !_BST [10] (maybe <- 0x41800023) (FP)
45419wr %g0, 0xf0, %asi
45420sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
45421sub %i0, %i3, %i3
45422! preparing store val #0, next val will be in f32
45423fmovs %f16, %f20
45424fadds %f16, %f17, %f16
45425! preparing store val #1, next val will be in f33
45426fmovs %f16, %f21
45427fadds %f16, %f17, %f16
45428! preparing store val #2, next val will be in f35
45429fmovd %f20, %f32
45430fmovs %f16, %f21
45431fadds %f16, %f17, %f16
45432fmovd %f20, %f34
45433membar #Sync
45434stda %f32, [%i3 + 0 ] %asi
45435
45436P4151: !_MEMBAR (FP)
45437membar #StoreLoad
45438
45439P4152: !_LD [20] (Int)
45440sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
45441sub %i0, %i2, %i2
45442lduw [%i2 + 12], %o5
45443! move %o5(lower) -> %o0(lower)
45444or %o5, %o0, %o0
45445
45446P4153: !_DWST_BINIT [22] (maybe <- 0x2000037) (Int)
45447wr %g0, 0xe2, %asi
45448sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
45449sub %i0, %i3, %i3
45450sllx %l4, 32, %l3
45451add %l4, 1, %l4
45452or %l3, %l4, %l3
45453stxa %l3, [%i3 + 0] %asi
45454add %l4, 1, %l4
45455
45456P4154: !_MEMBAR (Int)
45457membar #StoreLoad
45458
45459P4155: !_CASX [4] (maybe <- 0x2000039) (Int)
45460ldx [%i1], %o1
45461! move %o1(upper) -> %o1(upper)
45462! move %o1(lower) -> %o1(lower)
45463mov %o1, %o5
45464sllx %l4, 32, %o2
45465add %l4, 1, %l4
45466or %l4, %o2, %o2
45467casx [%i1], %o5, %o2
45468! move %o2(upper) -> %o2(upper)
45469! move %o2(lower) -> %o2(lower)
45470add %l4, 1, %l4
45471
45472P4156: !_DWST_BINIT [16] (maybe <- 0x200003b) (Int)
45473wr %g0, 0xe2, %asi
45474sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
45475sub %i0, %i2, %i2
45476sllx %l4, 32, %o5
45477add %l4, 1, %l4
45478or %o5, %l4, %o5
45479stxa %o5, [%i2 + 0] %asi
45480add %l4, 1, %l4
45481
45482P4157: !_MEMBAR (Int)
45483membar #StoreLoad
45484
45485P4158: !_PREFETCH [16] (Int)
45486prefetch [%i2 + 4], 22
45487
45488P4159: !_PREFETCH [4] (Int)
45489prefetch [%i1 + 4], 20
45490
45491P4160: !_LDD [12] (Int)
45492sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
45493sub %i0, %i3, %i3
45494ldd [%i3 + 0], %l6
45495! move %l6(lower) -> %o3(upper)
45496sllx %l6, 32, %o3
45497! move %l7(lower) -> %o3(lower)
45498or %l7, %o3, %o3
45499
45500P4161: !_DWST_BINIT [21] (maybe <- 0x200003d) (Int)
45501wr %g0, 0xe2, %asi
45502sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
45503sub %i0, %i2, %i2
45504sllx %l4, 32, %l3
45505add %l4, 1, %l4
45506or %l3, %l4, %l3
45507stxa %l3, [%i2 + 0] %asi
45508add %l4, 1, %l4
45509
45510P4162: !_MEMBAR (Int)
45511membar #StoreLoad
45512
45513P4163: !_PREFETCH [18] (Int)
45514sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
45515sub %i0, %i3, %i3
45516prefetch [%i3 + 0], 4
45517
45518P4164: !_ST [19] (maybe <- 0x200003f) (Int)
45519stw %l4, [%i3 + 4 ]
45520add %l4, 1, %l4
45521
45522P4165: !_DWST [15] (maybe <- 0x2000040) (Int)
45523sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
45524sub %i0, %i2, %i2
45525sllx %l4, 32, %l7
45526add %l4, 1, %l4
45527or %l7, %l4, %l7
45528stx %l7, [%i2 + 0]
45529add %l4, 1, %l4
45530
45531P4166: !_SWAP [23] (maybe <- 0x2000042) (Int)
45532sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
45533sub %i0, %i3, %i3
45534mov %l4, %o4
45535swap [%i3 + 12], %o4
45536! move %o4(lower) -> %o4(upper)
45537sllx %o4, 32, %o4
45538add %l4, 1, %l4
45539
45540P4167: !_DWST_BINIT [11] (maybe <- 0x2000043) (Int)
45541wr %g0, 0xe2, %asi
45542sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
45543sub %i0, %i2, %i2
45544mov %l4, %l3
45545stxa %l3, [%i2 + 8] %asi
45546add %l4, 1, %l4
45547
45548P4168: !_MEMBAR (Int)
45549membar #StoreLoad
45550
45551P4169: !_PREFETCH [7] (Int) (Branch target of P4268)
45552sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
45553add %i0, %i3, %i3
45554prefetch [%i3 + 4], 29
45555ba P4170
45556nop
45557
45558TARGET4268:
45559ba RET4268
45560nop
45561
45562
45563P4170: !_LD [21] (Int)
45564sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
45565sub %i0, %i2, %i2
45566lduw [%i2 + 0], %l3
45567! move %l3(lower) -> %o4(lower)
45568or %l3, %o4, %o4
45569!---- flushing int results buffer----
45570mov %o0, %l5
45571mov %o1, %l5
45572mov %o2, %l5
45573mov %o3, %l5
45574mov %o4, %l5
45575
45576P4171: !_MEMBAR (FP)
45577
45578P4172: !_BST [20] (maybe <- 0x41800026) (FP) (CBR)
45579wr %g0, 0xf0, %asi
45580sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
45581sub %i0, %i3, %i3
45582! preparing store val #0, next val will be in f32
45583fmovs %f16, %f20
45584fadds %f16, %f17, %f16
45585! preparing store val #1, next val will be in f33
45586fmovs %f16, %f21
45587fadds %f16, %f17, %f16
45588! preparing store val #2, next val will be in f35
45589fmovd %f20, %f32
45590fmovs %f16, %f21
45591fadds %f16, %f17, %f16
45592fmovd %f20, %f34
45593membar #Sync
45594stda %f32, [%i3 + 0 ] %asi
45595
45596! cbranch
45597andcc %l0, 1, %g0
45598be,pn %xcc, TARGET4172
45599nop
45600RET4172:
45601
45602! lfsr step begin
45603srlx %l0, 1, %l3
45604xnor %l3, %l0, %l3
45605sllx %l3, 63, %l3
45606or %l3, %l0, %l0
45607srlx %l0, 1, %l0
45608
45609
45610P4173: !_MEMBAR (FP)
45611membar #StoreLoad
45612
45613P4174: !_LD [13] (FP)
45614sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
45615sub %i0, %i2, %i2
45616ld [%i2 + 4], %f10
45617! 1 addresses covered
45618
45619P4175: !_DWLD [2] (Int)
45620ldx [%i0 + 8], %o0
45621! move %o0(lower) -> %o0(upper)
45622sllx %o0, 32, %o0
45623
45624P4176: !_DWST [12] (maybe <- 0x2000044) (Int) (Branch target of P4747)
45625sllx %l4, 32, %o5
45626add %l4, 1, %l4
45627or %o5, %l4, %o5
45628stx %o5, [%i2 + 0]
45629add %l4, 1, %l4
45630ba P4177
45631nop
45632
45633TARGET4747:
45634ba RET4747
45635nop
45636
45637
45638P4177: !_DWST [14] (maybe <- 0x41800029) (FP)
45639! preparing store val #0, next val will be in f21
45640fmovs %f16, %f21
45641fadds %f16, %f17, %f16
45642std %f20, [%i2 + 8]
45643
45644P4178: !_PREFETCH [22] (Int)
45645sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
45646sub %i0, %i3, %i3
45647prefetch [%i3 + 4], 1
45648
45649P4179: !_LD [1] (Int) (LE) (Branch target of P4345)
45650wr %g0, 0x88, %asi
45651lduwa [%i0 + 4] %asi, %l7
45652! move %l7(lower) -> %o0(lower)
45653or %l7, %o0, %o0
45654ba P4180
45655nop
45656
45657TARGET4345:
45658ba RET4345
45659nop
45660
45661
45662P4180: !_LD [19] (Int)
45663sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
45664sub %i0, %i2, %i2
45665lduw [%i2 + 4], %o1
45666! move %o1(lower) -> %o1(upper)
45667sllx %o1, 32, %o1
45668
45669P4181: !_REPLACEMENT [6] (Int)
45670sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
45671sub %i0, %i3, %i3
45672sethi %hi(0x20000), %l6
45673ld [%i3+0], %o5
45674st %o5, [%i3+0]
45675add %i3, %l6, %l7
45676ld [%l7+0], %o5
45677st %o5, [%l7+0]
45678add %l7, %l6, %l7
45679ld [%l7+0], %o5
45680st %o5, [%l7+0]
45681add %l7, %l6, %l7
45682ld [%l7+0], %o5
45683st %o5, [%l7+0]
45684add %l7, %l6, %l7
45685ld [%l7+0], %o5
45686st %o5, [%l7+0]
45687add %l7, %l6, %l7
45688ld [%l7+0], %o5
45689st %o5, [%l7+0]
45690add %l7, %l6, %l7
45691ld [%l7+0], %o5
45692st %o5, [%l7+0]
45693add %l7, %l6, %l7
45694ld [%l7+0], %o5
45695st %o5, [%l7+0]
45696
45697P4182: !_DWST_BINIT [12] (maybe <- 0x2000046) (Int)
45698wr %g0, 0xe2, %asi
45699sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
45700sub %i0, %i2, %i2
45701sllx %l4, 32, %l3
45702add %l4, 1, %l4
45703or %l3, %l4, %l3
45704stxa %l3, [%i2 + 0] %asi
45705add %l4, 1, %l4
45706
45707P4183: !_MEMBAR (Int)
45708membar #StoreLoad
45709
45710P4184: !_CAS [22] (maybe <- 0x2000048) (Int)
45711sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
45712sub %i0, %i3, %i3
45713add %i3, 4, %l3
45714lduw [%l3], %l7
45715mov %l7, %o5
45716! move %o5(lower) -> %o1(lower)
45717or %o5, %o1, %o1
45718mov %l4, %o2
45719cas [%l3], %o5, %o2
45720! move %o2(lower) -> %o2(upper)
45721sllx %o2, 32, %o2
45722add %l4, 1, %l4
45723
45724P4185: !_SWAP [7] (maybe <- 0x2000049) (Int)
45725sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
45726add %i0, %i2, %i2
45727mov %l4, %l6
45728swap [%i2 + 4], %l6
45729! move %l6(lower) -> %o2(lower)
45730srl %l6, 0, %o5
45731or %o5, %o2, %o2
45732add %l4, 1, %l4
45733
45734P4186: !_PREFETCH [13] (Int)
45735sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
45736sub %i0, %i3, %i3
45737prefetch [%i3 + 4], 1
45738
45739P4187: !_ST [23] (maybe <- 0x200004a) (Int)
45740sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
45741sub %i0, %i2, %i2
45742stw %l4, [%i2 + 12 ]
45743add %l4, 1, %l4
45744
45745P4188: !_CAS [15] (maybe <- 0x200004b) (Int)
45746sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
45747sub %i0, %i3, %i3
45748lduw [%i3], %o3
45749mov %o3, %l6
45750! move %l6(lower) -> %o3(upper)
45751sllx %l6, 32, %o3
45752mov %l4, %l3
45753cas [%i3], %l6, %l3
45754! move %l3(lower) -> %o3(lower)
45755srl %l3, 0, %l6
45756or %l6, %o3, %o3
45757add %l4, 1, %l4
45758
45759P4189: !_PREFETCH [15] (Int)
45760prefetch [%i3 + 0], 1
45761
45762P4190: !_CASX [3] (maybe <- 0x200004c) (Int)
45763ldx [%i1], %o4
45764! move %o4(upper) -> %o4(upper)
45765! move %o4(lower) -> %o4(lower)
45766!---- flushing int results buffer----
45767mov %o0, %l5
45768mov %o1, %l5
45769mov %o2, %l5
45770mov %o3, %l5
45771mov %o4, %l5
45772mov %o4, %l6
45773sllx %l4, 32, %o0
45774add %l4, 1, %l4
45775or %l4, %o0, %o0
45776casx [%i1], %l6, %o0
45777! move %o0(upper) -> %o0(upper)
45778! move %o0(lower) -> %o0(lower)
45779add %l4, 1, %l4
45780
45781P4191: !_CASX [17] (maybe <- 0x200004e) (Int)
45782add %i3, 8, %l7
45783ldx [%l7], %o1
45784! move %o1(upper) -> %o1(upper)
45785! move %o1(lower) -> %o1(lower)
45786mov %o1, %l6
45787mov %l4, %o2
45788casx [%l7], %l6, %o2
45789! move %o2(upper) -> %o2(upper)
45790! move %o2(lower) -> %o2(lower)
45791add %l4, 1, %l4
45792
45793P4192: !_MEMBAR (FP)
45794membar #StoreLoad
45795
45796P4193: !_BLD [8] (FP)
45797wr %g0, 0xf0, %asi
45798sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
45799add %i0, %i2, %i2
45800ldda [%i2 + 0] %asi, %f32
45801membar #Sync
45802! 3 addresses covered
45803fmovd %f32, %f18
45804fmovs %f18, %f11
45805fmovs %f19, %f12
45806fmovd %f34, %f18
45807fmovs %f19, %f13
45808
45809P4194: !_MEMBAR (FP)
45810
45811P4195: !_CASX [7] (maybe <- 0x200004f) (Int)
45812ldx [%i2], %o3
45813! move %o3(upper) -> %o3(upper)
45814! move %o3(lower) -> %o3(lower)
45815mov %o3, %l6
45816sllx %l4, 32, %o4
45817add %l4, 1, %l4
45818or %l4, %o4, %o4
45819casx [%i2], %l6, %o4
45820! move %o4(upper) -> %o4(upper)
45821! move %o4(lower) -> %o4(lower)
45822!---- flushing int results buffer----
45823mov %o0, %l5
45824mov %o1, %l5
45825mov %o2, %l5
45826mov %o3, %l5
45827mov %o4, %l5
45828add %l4, 1, %l4
45829
45830P4196: !_MEMBAR (FP)
45831
45832P4197: !_BST [16] (maybe <- 0x4180002a) (FP)
45833wr %g0, 0xf0, %asi
45834! preparing store val #0, next val will be in f32
45835fmovs %f16, %f20
45836fadds %f16, %f17, %f16
45837! preparing store val #1, next val will be in f33
45838fmovs %f16, %f21
45839fadds %f16, %f17, %f16
45840! preparing store val #2, next val will be in f35
45841fmovd %f20, %f32
45842fmovs %f16, %f21
45843fadds %f16, %f17, %f16
45844fmovd %f20, %f34
45845membar #Sync
45846stda %f32, [%i3 + 0 ] %asi
45847
45848P4198: !_MEMBAR (FP)
45849membar #StoreLoad
45850
45851P4199: !_CASX [17] (maybe <- 0x2000051) (Int) (LE)
45852! Change single-word-level endianess (big endian <-> little endian)
45853sethi %hi(0xff00ff00), %l6
45854or %l6, %lo(0xff00ff00), %l6
45855and %l4, %l6, %l3
45856srl %l3, 8, %l3
45857sll %l4, 8, %l7
45858and %l7, %l6, %l7
45859or %l7, %l3, %l7
45860srl %l7, 16, %l3
45861sll %l7, 16, %l7
45862srl %l7, 0, %l7
45863or %l7, %l3, %l7
45864sllx %l7, 32, %l7
45865wr %g0, 0x88, %asi
45866add %i3, 8, %l6
45867ldxa [%l6] %asi, %o5
45868! move %o5(lower) -> %o0(upper)
45869sllx %o5, 32, %o0
45870! move %o5(upper) -> %o0(lower)
45871srlx %o5, 32, %l3
45872or %l3, %o0, %o0
45873mov %o5, %l3
45874mov %l7, %o5
45875casxa [%l6] %asi, %l3, %o5
45876! move %o5(lower) -> %o1(upper)
45877sllx %o5, 32, %o1
45878! move %o5(upper) -> %o1(lower)
45879srlx %o5, 32, %l3
45880or %l3, %o1, %o1
45881add %l4, 1, %l4
45882
45883P4200: !_DWST [16] (maybe <- 0x2000052) (Int)
45884sllx %l4, 32, %l3
45885add %l4, 1, %l4
45886or %l3, %l4, %l3
45887stx %l3, [%i3 + 0]
45888add %l4, 1, %l4
45889
45890P4201: !_ST_BINIT [2] (maybe <- 0x2000054) (Int)
45891wr %g0, 0xe2, %asi
45892stwa %l4, [%i0 + 12] %asi
45893add %l4, 1, %l4
45894
45895P4202: !_MEMBAR (Int)
45896membar #StoreLoad
45897
45898P4203: !_CAS [10] (maybe <- 0x2000055) (Int)
45899sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
45900sub %i0, %i3, %i3
45901add %i3, 4, %l3
45902lduw [%l3], %o2
45903mov %o2, %o5
45904! move %o5(lower) -> %o2(upper)
45905sllx %o5, 32, %o2
45906mov %l4, %l7
45907cas [%l3], %o5, %l7
45908! move %l7(lower) -> %o2(lower)
45909srl %l7, 0, %o5
45910or %o5, %o2, %o2
45911add %l4, 1, %l4
45912
45913P4204: !_CAS [22] (maybe <- 0x2000056) (Int) (LE)
45914! Change single-word-level endianess (big endian <-> little endian)
45915sethi %hi(0xff00ff00), %l3
45916or %l3, %lo(0xff00ff00), %l3
45917and %l4, %l3, %o5
45918srl %o5, 8, %o5
45919sll %l4, 8, %l6
45920and %l6, %l3, %l6
45921or %l6, %o5, %l6
45922srl %l6, 16, %o5
45923sll %l6, 16, %l6
45924srl %l6, 0, %l6
45925or %l6, %o5, %l6
45926wr %g0, 0x88, %asi
45927sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
45928sub %i0, %i2, %i2
45929add %i2, 4, %l3
45930lduwa [%l3] %asi, %o3
45931mov %o3, %o5
45932! move %o5(lower) -> %o3(upper)
45933sllx %o5, 32, %o3
45934mov %l6, %l7
45935casa [%l3] %asi, %o5, %l7
45936! move %l7(lower) -> %o3(lower)
45937srl %l7, 0, %o5
45938or %o5, %o3, %o3
45939add %l4, 1, %l4
45940
45941P4205: !_DWLD [23] (FP)
45942ldd [%i2 + 8], %f14
45943! 1 addresses covered
45944fmovs %f15, %f14
45945
45946P4206: !_ST [14] (maybe <- 0x2000057) (Int)
45947sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
45948sub %i0, %i3, %i3
45949stw %l4, [%i3 + 12 ]
45950add %l4, 1, %l4
45951
45952P4207: !_PREFETCH [12] (Int)
45953prefetch [%i3 + 0], 1
45954
45955P4208: !_DWST_BINIT [15] (maybe <- 0x2000058) (Int)
45956wr %g0, 0xe2, %asi
45957sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
45958sub %i0, %i2, %i2
45959sllx %l4, 32, %l7
45960add %l4, 1, %l4
45961or %l7, %l4, %l7
45962stxa %l7, [%i2 + 0] %asi
45963add %l4, 1, %l4
45964
45965P4209: !_MEMBAR (Int)
45966
45967P4210: !_BST [8] (maybe <- 0x4180002d) (FP)
45968wr %g0, 0xf0, %asi
45969sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
45970add %i0, %i3, %i3
45971! preparing store val #0, next val will be in f32
45972fmovs %f16, %f20
45973fadds %f16, %f17, %f16
45974! preparing store val #1, next val will be in f33
45975fmovs %f16, %f21
45976fadds %f16, %f17, %f16
45977! preparing store val #2, next val will be in f35
45978fmovd %f20, %f32
45979fmovs %f16, %f21
45980fadds %f16, %f17, %f16
45981fmovd %f20, %f34
45982membar #Sync
45983stda %f32, [%i3 + 0 ] %asi
45984
45985P4211: !_MEMBAR (FP)
45986membar #StoreLoad
45987
45988P4212: !_BLD [2] (FP)
45989wr %g0, 0xf0, %asi
45990ldda [%i0 + 0] %asi, %f32
45991membar #Sync
45992! 3 addresses covered
45993fmovd %f32, %f18
45994fmovs %f18, %f15
45995!---- flushing fp results buffer to %f30 ----
45996fmovd %f0, %f30
45997fmovd %f2, %f30
45998fmovd %f4, %f30
45999fmovd %f6, %f30
46000fmovd %f8, %f30
46001fmovd %f10, %f30
46002fmovd %f12, %f30
46003fmovd %f14, %f30
46004!--
46005fmovs %f19, %f0
46006fmovd %f34, %f18
46007fmovs %f19, %f1
46008
46009P4213: !_MEMBAR (FP)
46010
46011P4214: !_SWAP [5] (maybe <- 0x200005a) (Int)
46012mov %l4, %o4
46013swap [%i1 + 12], %o4
46014! move %o4(lower) -> %o4(upper)
46015sllx %o4, 32, %o4
46016add %l4, 1, %l4
46017
46018P4215: !_REPLACEMENT [1] (Int)
46019sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
46020sub %i0, %i2, %i2
46021sethi %hi(0x20000), %o5
46022ld [%i2+4], %l6
46023st %l6, [%i2+4]
46024add %i2, %o5, %l3
46025ld [%l3+4], %l6
46026st %l6, [%l3+4]
46027add %l3, %o5, %l3
46028ld [%l3+4], %l6
46029st %l6, [%l3+4]
46030add %l3, %o5, %l3
46031ld [%l3+4], %l6
46032st %l6, [%l3+4]
46033add %l3, %o5, %l3
46034ld [%l3+4], %l6
46035st %l6, [%l3+4]
46036add %l3, %o5, %l3
46037ld [%l3+4], %l6
46038st %l6, [%l3+4]
46039add %l3, %o5, %l3
46040ld [%l3+4], %l6
46041st %l6, [%l3+4]
46042add %l3, %o5, %l3
46043ld [%l3+4], %l6
46044st %l6, [%l3+4]
46045
46046P4216: !_LDD [6] (Int)
46047ldd [%i3 + 0], %l6
46048! move %l6(lower) -> %o4(lower)
46049or %l6, %o4, %o4
46050!---- flushing int results buffer----
46051mov %o0, %l5
46052mov %o1, %l5
46053mov %o2, %l5
46054mov %o3, %l5
46055mov %o4, %l5
46056! move %l7(lower) -> %o0(upper)
46057sllx %l7, 32, %o0
46058
46059P4217: !_DWLD [9] (Int) (CBR)
46060sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
46061sub %i0, %i3, %i3
46062ldx [%i3 + 0], %l6
46063! move %l6(upper) -> %o0(lower)
46064srlx %l6, 32, %l3
46065or %l3, %o0, %o0
46066! move %l6(lower) -> %o1(upper)
46067sllx %l6, 32, %o1
46068
46069! cbranch
46070andcc %l0, 1, %g0
46071be,pt %xcc, TARGET4217
46072nop
46073RET4217:
46074
46075! lfsr step begin
46076srlx %l0, 1, %l7
46077xnor %l7, %l0, %l7
46078sllx %l7, 63, %l7
46079or %l7, %l0, %l0
46080srlx %l0, 1, %l0
46081
46082
46083P4218: !_CASX [14] (maybe <- 0x200005b) (Int)
46084sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
46085sub %i0, %i2, %i2
46086add %i2, 8, %l3
46087ldx [%l3], %l7
46088! move %l7(upper) -> %o1(lower)
46089srlx %l7, 32, %o5
46090or %o5, %o1, %o1
46091! move %l7(lower) -> %o2(upper)
46092sllx %l7, 32, %o2
46093mov %l7, %o5
46094mov %l4, %l7
46095casx [%l3], %o5, %l7
46096! move %l7(upper) -> %o2(lower)
46097srlx %l7, 32, %o5
46098or %o5, %o2, %o2
46099! move %l7(lower) -> %o3(upper)
46100sllx %l7, 32, %o3
46101add %l4, 1, %l4
46102
46103P4219: !_MEMBAR (FP)
46104
46105P4220: !_BSTC [19] (maybe <- 0x41800030) (FP)
46106wr %g0, 0xe0, %asi
46107sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
46108sub %i0, %i3, %i3
46109! preparing store val #0, next val will be in f32
46110fmovs %f16, %f20
46111fadds %f16, %f17, %f16
46112! preparing store val #1, next val will be in f33
46113fmovs %f16, %f21
46114fadds %f16, %f17, %f16
46115! preparing store val #2, next val will be in f35
46116fmovd %f20, %f32
46117fmovs %f16, %f21
46118fadds %f16, %f17, %f16
46119fmovd %f20, %f34
46120membar #Sync
46121stda %f32, [%i3 + 0 ] %asi
46122
46123P4221: !_MEMBAR (FP)
46124membar #StoreLoad
46125
46126P4222: !_ST_BINIT [19] (maybe <- 0x200005c) (Int)
46127wr %g0, 0xe2, %asi
46128stwa %l4, [%i3 + 4] %asi
46129add %l4, 1, %l4
46130
46131P4223: !_MEMBAR (Int)
46132membar #StoreLoad
46133
46134P4224: !_DWST [10] (maybe <- 0x200005d) (Int) (CBR)
46135sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
46136sub %i0, %i2, %i2
46137sllx %l4, 32, %l6
46138add %l4, 1, %l4
46139or %l6, %l4, %l6
46140stx %l6, [%i2 + 0]
46141add %l4, 1, %l4
46142
46143! cbranch
46144andcc %l0, 1, %g0
46145be,pn %xcc, TARGET4224
46146nop
46147RET4224:
46148
46149! lfsr step begin
46150srlx %l0, 1, %l3
46151xnor %l3, %l0, %l3
46152sllx %l3, 63, %l3
46153or %l3, %l0, %l0
46154srlx %l0, 1, %l0
46155
46156
46157P4225: !_SWAP [12] (maybe <- 0x200005f) (Int)
46158sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
46159sub %i0, %i3, %i3
46160mov %l4, %o5
46161swap [%i3 + 0], %o5
46162! move %o5(lower) -> %o3(lower)
46163srl %o5, 0, %l6
46164or %l6, %o3, %o3
46165add %l4, 1, %l4
46166
46167P4226: !_CASX [7] (maybe <- 0x2000060) (Int)
46168sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
46169add %i0, %i2, %i2
46170ldx [%i2], %o4
46171! move %o4(upper) -> %o4(upper)
46172! move %o4(lower) -> %o4(lower)
46173!---- flushing int results buffer----
46174mov %o0, %l5
46175mov %o1, %l5
46176mov %o2, %l5
46177mov %o3, %l5
46178mov %o4, %l5
46179mov %o4, %l3
46180sllx %l4, 32, %o0
46181add %l4, 1, %l4
46182or %l4, %o0, %o0
46183casx [%i2], %l3, %o0
46184! move %o0(upper) -> %o0(upper)
46185! move %o0(lower) -> %o0(lower)
46186add %l4, 1, %l4
46187
46188P4227: !_MEMBAR (FP)
46189
46190P4228: !_BST [20] (maybe <- 0x41800033) (FP)
46191wr %g0, 0xf0, %asi
46192sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
46193sub %i0, %i3, %i3
46194! preparing store val #0, next val will be in f32
46195fmovs %f16, %f20
46196fadds %f16, %f17, %f16
46197! preparing store val #1, next val will be in f33
46198fmovs %f16, %f21
46199fadds %f16, %f17, %f16
46200! preparing store val #2, next val will be in f35
46201fmovd %f20, %f32
46202fmovs %f16, %f21
46203fadds %f16, %f17, %f16
46204fmovd %f20, %f34
46205membar #Sync
46206stda %f32, [%i3 + 0 ] %asi
46207
46208P4229: !_MEMBAR (FP)
46209membar #StoreLoad
46210
46211P4230: !_ST [14] (maybe <- 0x2000062) (Int)
46212sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
46213sub %i0, %i2, %i2
46214stw %l4, [%i2 + 12 ]
46215add %l4, 1, %l4
46216
46217P4231: !_LD [18] (Int)
46218lduw [%i3 + 0], %o1
46219! move %o1(lower) -> %o1(upper)
46220sllx %o1, 32, %o1
46221
46222P4232: !_DWLD [2] (Int)
46223ldx [%i0 + 8], %l6
46224! move %l6(lower) -> %o1(lower)
46225srl %l6, 0, %l3
46226or %l3, %o1, %o1
46227
46228P4233: !_MEMBAR (FP)
46229membar #StoreLoad
46230
46231P4234: !_BLD [15] (FP)
46232wr %g0, 0xf0, %asi
46233sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
46234sub %i0, %i3, %i3
46235ldda [%i3 + 0] %asi, %f32
46236membar #Sync
46237! 3 addresses covered
46238fmovd %f32, %f2
46239fmovd %f34, %f18
46240fmovs %f19, %f4
46241
46242P4235: !_MEMBAR (FP)
46243
46244P4236: !_SWAP [1] (maybe <- 0x2000063) (Int)
46245mov %l4, %o2
46246swap [%i0 + 4], %o2
46247! move %o2(lower) -> %o2(upper)
46248sllx %o2, 32, %o2
46249add %l4, 1, %l4
46250
46251P4237: !_PREFETCH [23] (Int)
46252sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
46253sub %i0, %i2, %i2
46254prefetch [%i2 + 12], 0
46255
46256P4238: !_CASX [1] (maybe <- 0x2000064) (Int)
46257ldx [%i0], %l3
46258! move %l3(upper) -> %o2(lower)
46259srlx %l3, 32, %l6
46260or %l6, %o2, %o2
46261! move %l3(lower) -> %o3(upper)
46262sllx %l3, 32, %o3
46263mov %l3, %l6
46264sllx %l4, 32, %l3
46265add %l4, 1, %l4
46266or %l4, %l3, %l3
46267casx [%i0], %l6, %l3
46268! move %l3(upper) -> %o3(lower)
46269srlx %l3, 32, %l6
46270or %l6, %o3, %o3
46271! move %l3(lower) -> %o4(upper)
46272sllx %l3, 32, %o4
46273add %l4, 1, %l4
46274
46275P4239: !_LDD [22] (Int)
46276ldd [%i2 + 0], %l6
46277! move %l6(lower) -> %o4(lower)
46278or %l6, %o4, %o4
46279!---- flushing int results buffer----
46280mov %o0, %l5
46281mov %o1, %l5
46282mov %o2, %l5
46283mov %o3, %l5
46284mov %o4, %l5
46285! move %l7(lower) -> %o0(upper)
46286sllx %l7, 32, %o0
46287
46288P4240: !_LD [13] (Int)
46289sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
46290sub %i0, %i3, %i3
46291lduw [%i3 + 4], %l6
46292! move %l6(lower) -> %o0(lower)
46293or %l6, %o0, %o0
46294
46295P4241: !_SWAP [22] (maybe <- 0x2000066) (Int) (LE)
46296wr %g0, 0x88, %asi
46297mov %l4, %o1
46298! Change single-word-level endianess (big endian <-> little endian)
46299sethi %hi(0xff00ff00), %l7
46300or %l7, %lo(0xff00ff00), %l7
46301and %o1, %l7, %o5
46302srl %o5, 8, %o5
46303sll %o1, 8, %o1
46304and %o1, %l7, %o1
46305or %o1, %o5, %o1
46306srl %o1, 16, %o5
46307sll %o1, 16, %o1
46308srl %o1, 0, %o1
46309or %o1, %o5, %o1
46310swapa [%i2 + 4] %asi, %o1
46311! move %o1(lower) -> %o1(upper)
46312sllx %o1, 32, %o1
46313add %l4, 1, %l4
46314
46315P4242: !_DWST_BINIT [8] (maybe <- 0x2000067) (Int)
46316wr %g0, 0xe2, %asi
46317sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
46318add %i0, %i2, %i2
46319mov %l4, %l6
46320stxa %l6, [%i2 + 8] %asi
46321add %l4, 1, %l4
46322
46323P4243: !_MEMBAR (Int)
46324
46325P4244: !_BST [3] (maybe <- 0x41800036) (FP)
46326wr %g0, 0xf0, %asi
46327! preparing store val #0, next val will be in f32
46328fmovs %f16, %f20
46329fadds %f16, %f17, %f16
46330! preparing store val #1, next val will be in f33
46331fmovs %f16, %f21
46332fadds %f16, %f17, %f16
46333! preparing store val #2, next val will be in f35
46334fmovd %f20, %f32
46335fmovs %f16, %f21
46336fadds %f16, %f17, %f16
46337fmovd %f20, %f34
46338membar #Sync
46339stda %f32, [%i1 + 0 ] %asi
46340
46341P4245: !_MEMBAR (FP)
46342membar #StoreLoad
46343
46344P4246: !_ST [8] (maybe <- 0x2000068) (Int)
46345stw %l4, [%i2 + 12 ]
46346add %l4, 1, %l4
46347
46348P4247: !_MEMBAR (FP) (CBR)
46349
46350! cbranch
46351andcc %l0, 1, %g0
46352be,pn %xcc, TARGET4247
46353nop
46354RET4247:
46355
46356! lfsr step begin
46357srlx %l0, 1, %l7
46358xnor %l7, %l0, %l7
46359sllx %l7, 63, %l7
46360or %l7, %l0, %l0
46361srlx %l0, 1, %l0
46362
46363
46364P4248: !_BST [5] (maybe <- 0x41800039) (FP)
46365wr %g0, 0xf0, %asi
46366! preparing store val #0, next val will be in f32
46367fmovs %f16, %f20
46368fadds %f16, %f17, %f16
46369! preparing store val #1, next val will be in f33
46370fmovs %f16, %f21
46371fadds %f16, %f17, %f16
46372! preparing store val #2, next val will be in f35
46373fmovd %f20, %f32
46374fmovs %f16, %f21
46375fadds %f16, %f17, %f16
46376fmovd %f20, %f34
46377membar #Sync
46378stda %f32, [%i1 + 0 ] %asi
46379
46380P4249: !_MEMBAR (FP)
46381membar #StoreLoad
46382
46383P4250: !_DWST_BINIT [20] (maybe <- 0x2000069) (Int)
46384wr %g0, 0xe2, %asi
46385sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
46386sub %i0, %i3, %i3
46387mov %l4, %l7
46388stxa %l7, [%i3 + 8] %asi
46389add %l4, 1, %l4
46390
46391P4251: !_MEMBAR (Int)
46392membar #StoreLoad
46393
46394P4252: !_DWST [9] (maybe <- 0x200006a) (Int)
46395sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
46396sub %i0, %i2, %i2
46397sllx %l4, 32, %l6
46398add %l4, 1, %l4
46399or %l6, %l4, %l6
46400stx %l6, [%i2 + 0]
46401add %l4, 1, %l4
46402
46403P4253: !_PREFETCH [2] (Int)
46404prefetch [%i0 + 12], 21
46405
46406P4254: !_SWAP [13] (maybe <- 0x200006c) (Int)
46407sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
46408sub %i0, %i3, %i3
46409mov %l4, %l7
46410swap [%i3 + 4], %l7
46411! move %l7(lower) -> %o1(lower)
46412srl %l7, 0, %l3
46413or %l3, %o1, %o1
46414add %l4, 1, %l4
46415
46416P4255: !_PREFETCH [5] (Int)
46417prefetch [%i1 + 12], 21
46418
46419P4256: !_SWAP [0] (maybe <- 0x200006d) (Int)
46420mov %l4, %o2
46421swap [%i0 + 0], %o2
46422! move %o2(lower) -> %o2(upper)
46423sllx %o2, 32, %o2
46424add %l4, 1, %l4
46425
46426P4257: !_LDD [23] (Int)
46427sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
46428sub %i0, %i2, %i2
46429ldd [%i2 + 8], %l6
46430! move %l7(lower) -> %o2(lower)
46431or %l7, %o2, %o2
46432
46433P4258: !_LDD [3] (Int)
46434ldd [%i1 + 0], %l6
46435! move %l6(lower) -> %o3(upper)
46436sllx %l6, 32, %o3
46437! move %l7(lower) -> %o3(lower)
46438or %l7, %o3, %o3
46439
46440P4259: !_MEMBAR (FP)
46441membar #StoreLoad
46442
46443P4260: !_BLD [0] (FP)
46444wr %g0, 0xf0, %asi
46445ldda [%i0 + 0] %asi, %f32
46446membar #Sync
46447! 3 addresses covered
46448fmovd %f32, %f18
46449fmovs %f18, %f5
46450fmovs %f19, %f6
46451fmovd %f34, %f18
46452fmovs %f19, %f7
46453
46454P4261: !_MEMBAR (FP)
46455
46456P4262: !_SWAP [1] (maybe <- 0x200006e) (Int)
46457mov %l4, %o4
46458swap [%i0 + 4], %o4
46459! move %o4(lower) -> %o4(upper)
46460sllx %o4, 32, %o4
46461add %l4, 1, %l4
46462
46463P4263: !_CAS [22] (maybe <- 0x200006f) (Int)
46464add %i2, 4, %l3
46465lduw [%l3], %l7
46466mov %l7, %o5
46467! move %o5(lower) -> %o4(lower)
46468or %o5, %o4, %o4
46469!---- flushing int results buffer----
46470mov %o0, %l5
46471mov %o1, %l5
46472mov %o2, %l5
46473mov %o3, %l5
46474mov %o4, %l5
46475mov %l4, %o0
46476cas [%l3], %o5, %o0
46477! move %o0(lower) -> %o0(upper)
46478sllx %o0, 32, %o0
46479add %l4, 1, %l4
46480
46481P4264: !_MEMBAR (FP)
46482membar #StoreLoad
46483
46484P4265: !_BLD [20] (FP)
46485wr %g0, 0xf0, %asi
46486sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
46487sub %i0, %i3, %i3
46488ldda [%i3 + 0] %asi, %f32
46489membar #Sync
46490! 3 addresses covered
46491fmovd %f32, %f8
46492fmovd %f34, %f18
46493fmovs %f19, %f10
46494
46495P4266: !_MEMBAR (FP)
46496
46497P4267: !_CAS [13] (maybe <- 0x2000070) (Int)
46498sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
46499sub %i0, %i2, %i2
46500add %i2, 4, %l6
46501lduw [%l6], %o5
46502mov %o5, %l3
46503! move %l3(lower) -> %o0(lower)
46504or %l3, %o0, %o0
46505mov %l4, %o1
46506cas [%l6], %l3, %o1
46507! move %o1(lower) -> %o1(upper)
46508sllx %o1, 32, %o1
46509add %l4, 1, %l4
46510
46511P4268: !_DWST [11] (maybe <- 0x2000071) (Int) (CBR)
46512sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
46513sub %i0, %i3, %i3
46514mov %l4, %l3
46515stx %l3, [%i3 + 8]
46516add %l4, 1, %l4
46517
46518! cbranch
46519andcc %l0, 1, %g0
46520be,pt %xcc, TARGET4268
46521nop
46522RET4268:
46523
46524! lfsr step begin
46525srlx %l0, 1, %o5
46526xnor %o5, %l0, %o5
46527sllx %o5, 63, %o5
46528or %o5, %l0, %l0
46529srlx %l0, 1, %l0
46530
46531
46532P4269: !_MEMBAR (FP)
46533
46534P4270: !_BSTC [5] (maybe <- 0x4180003c) (FP)
46535wr %g0, 0xe0, %asi
46536! preparing store val #0, next val will be in f32
46537fmovs %f16, %f20
46538fadds %f16, %f17, %f16
46539! preparing store val #1, next val will be in f33
46540fmovs %f16, %f21
46541fadds %f16, %f17, %f16
46542! preparing store val #2, next val will be in f35
46543fmovd %f20, %f32
46544fmovs %f16, %f21
46545fadds %f16, %f17, %f16
46546fmovd %f20, %f34
46547membar #Sync
46548stda %f32, [%i1 + 0 ] %asi
46549
46550P4271: !_MEMBAR (FP)
46551membar #StoreLoad
46552
46553P4272: !_DWLD [5] (Int)
46554ldx [%i1 + 8], %l3
46555! move %l3(lower) -> %o1(lower)
46556srl %l3, 0, %o5
46557or %o5, %o1, %o1
46558
46559P4273: !_CAS [19] (maybe <- 0x2000072) (Int)
46560sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
46561sub %i0, %i2, %i2
46562add %i2, 4, %l7
46563lduw [%l7], %o2
46564mov %o2, %l6
46565! move %l6(lower) -> %o2(upper)
46566sllx %l6, 32, %o2
46567mov %l4, %l3
46568cas [%l7], %l6, %l3
46569! move %l3(lower) -> %o2(lower)
46570srl %l3, 0, %l6
46571or %l6, %o2, %o2
46572add %l4, 1, %l4
46573
46574P4274: !_CAS [21] (maybe <- 0x2000073) (Int)
46575sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
46576sub %i0, %i3, %i3
46577lduw [%i3], %o3
46578mov %o3, %l6
46579! move %l6(lower) -> %o3(upper)
46580sllx %l6, 32, %o3
46581mov %l4, %l3
46582cas [%i3], %l6, %l3
46583! move %l3(lower) -> %o3(lower)
46584srl %l3, 0, %l6
46585or %l6, %o3, %o3
46586add %l4, 1, %l4
46587
46588P4275: !_ST_BINIT [16] (maybe <- 0x2000074) (Int)
46589wr %g0, 0xe2, %asi
46590sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
46591sub %i0, %i2, %i2
46592stwa %l4, [%i2 + 4] %asi
46593add %l4, 1, %l4
46594
46595P4276: !_MEMBAR (Int) (CBR) (Branch target of P4678)
46596membar #StoreLoad
46597
46598! cbranch
46599andcc %l0, 1, %g0
46600be,pn %xcc, TARGET4276
46601nop
46602RET4276:
46603
46604! lfsr step begin
46605srlx %l0, 1, %l3
46606xnor %l3, %l0, %l3
46607sllx %l3, 63, %l3
46608or %l3, %l0, %l0
46609srlx %l0, 1, %l0
46610
46611ba P4277
46612nop
46613
46614TARGET4678:
46615ba RET4678
46616nop
46617
46618
46619P4277: !_DWST_BINIT [5] (maybe <- 0x2000075) (Int)
46620wr %g0, 0xe2, %asi
46621mov %l4, %l6
46622stxa %l6, [%i1 + 8] %asi
46623add %l4, 1, %l4
46624
46625P4278: !_MEMBAR (Int)
46626membar #StoreLoad
46627
46628P4279: !_DWST [4] (maybe <- 0x4180003f) (FP) (Branch target of P4657)
46629! preparing store val #0, next val will be in f20
46630fmovs %f16, %f20
46631fadds %f16, %f17, %f16
46632! preparing store val #1, next val will be in f21
46633fmovs %f16, %f21
46634fadds %f16, %f17, %f16
46635std %f20, [%i1 + 0]
46636ba P4280
46637nop
46638
46639TARGET4657:
46640ba RET4657
46641nop
46642
46643
46644P4280: !_LDD [1] (Int)
46645ldd [%i0 + 0], %l6
46646! move %l6(lower) -> %o4(upper)
46647sllx %l6, 32, %o4
46648! move %l7(lower) -> %o4(lower)
46649or %l7, %o4, %o4
46650!---- flushing int results buffer----
46651mov %o0, %l5
46652mov %o1, %l5
46653mov %o2, %l5
46654mov %o3, %l5
46655mov %o4, %l5
46656
46657P4281: !_REPLACEMENT [5] (Int)
46658sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
46659sub %i0, %i3, %i3
46660sethi %hi(0x20000), %l3
46661ld [%i3+12], %l7
46662st %l7, [%i3+12]
46663add %i3, %l3, %l6
46664ld [%l6+12], %l7
46665st %l7, [%l6+12]
46666add %l6, %l3, %l6
46667ld [%l6+12], %l7
46668st %l7, [%l6+12]
46669add %l6, %l3, %l6
46670ld [%l6+12], %l7
46671st %l7, [%l6+12]
46672add %l6, %l3, %l6
46673ld [%l6+12], %l7
46674st %l7, [%l6+12]
46675add %l6, %l3, %l6
46676ld [%l6+12], %l7
46677st %l7, [%l6+12]
46678add %l6, %l3, %l6
46679ld [%l6+12], %l7
46680st %l7, [%l6+12]
46681add %l6, %l3, %l6
46682ld [%l6+12], %l7
46683st %l7, [%l6+12]
46684
46685P4282: !_DWST [6] (maybe <- 0x2000076) (Int)
46686sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
46687add %i0, %i2, %i2
46688sllx %l4, 32, %o5
46689add %l4, 1, %l4
46690or %o5, %l4, %o5
46691stx %o5, [%i2 + 0]
46692add %l4, 1, %l4
46693
46694P4283: !_ST [11] (maybe <- 0x2000078) (Int)
46695sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
46696sub %i0, %i3, %i3
46697stw %l4, [%i3 + 12 ]
46698add %l4, 1, %l4
46699
46700P4284: !_MEMBAR (FP)
46701
46702P4285: !_BST [1] (maybe <- 0x41800041) (FP) (CBR)
46703wr %g0, 0xf0, %asi
46704! preparing store val #0, next val will be in f32
46705fmovs %f16, %f20
46706fadds %f16, %f17, %f16
46707! preparing store val #1, next val will be in f33
46708fmovs %f16, %f21
46709fadds %f16, %f17, %f16
46710! preparing store val #2, next val will be in f35
46711fmovd %f20, %f32
46712fmovs %f16, %f21
46713fadds %f16, %f17, %f16
46714fmovd %f20, %f34
46715membar #Sync
46716stda %f32, [%i0 + 0 ] %asi
46717
46718! cbranch
46719andcc %l0, 1, %g0
46720be,pn %xcc, TARGET4285
46721nop
46722RET4285:
46723
46724! lfsr step begin
46725srlx %l0, 1, %l3
46726xnor %l3, %l0, %l3
46727sllx %l3, 63, %l3
46728or %l3, %l0, %l0
46729srlx %l0, 1, %l0
46730
46731
46732P4286: !_MEMBAR (FP)
46733membar #StoreLoad
46734
46735P4287: !_DWLD [9] (Int)
46736ldx [%i3 + 0], %o0
46737! move %o0(upper) -> %o0(upper)
46738! move %o0(lower) -> %o0(lower)
46739
46740P4288: !_LDD [18] (Int)
46741sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
46742sub %i0, %i2, %i2
46743ldd [%i2 + 0], %l6
46744! move %l6(lower) -> %o1(upper)
46745sllx %l6, 32, %o1
46746! move %l7(lower) -> %o1(lower)
46747or %l7, %o1, %o1
46748
46749P4289: !_PREFETCH [21] (Int)
46750sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
46751sub %i0, %i3, %i3
46752prefetch [%i3 + 0], 23
46753
46754P4290: !_MEMBAR (FP)
46755
46756P4291: !_BST [13] (maybe <- 0x41800044) (FP)
46757wr %g0, 0xf0, %asi
46758sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
46759sub %i0, %i2, %i2
46760! preparing store val #0, next val will be in f32
46761fmovs %f16, %f20
46762fadds %f16, %f17, %f16
46763! preparing store val #1, next val will be in f33
46764fmovs %f16, %f21
46765fadds %f16, %f17, %f16
46766! preparing store val #2, next val will be in f35
46767fmovd %f20, %f32
46768fmovs %f16, %f21
46769fadds %f16, %f17, %f16
46770fmovd %f20, %f34
46771membar #Sync
46772stda %f32, [%i2 + 0 ] %asi
46773
46774P4292: !_MEMBAR (FP)
46775membar #StoreLoad
46776
46777P4293: !_DWST [14] (maybe <- 0x2000079) (Int)
46778mov %l4, %o5
46779stx %o5, [%i2 + 8]
46780add %l4, 1, %l4
46781
46782P4294: !_MEMBAR (FP)
46783
46784P4295: !_BSTC [19] (maybe <- 0x41800047) (FP)
46785wr %g0, 0xe0, %asi
46786sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
46787sub %i0, %i3, %i3
46788! preparing store val #0, next val will be in f32
46789fmovs %f16, %f20
46790fadds %f16, %f17, %f16
46791! preparing store val #1, next val will be in f33
46792fmovs %f16, %f21
46793fadds %f16, %f17, %f16
46794! preparing store val #2, next val will be in f35
46795fmovd %f20, %f32
46796fmovs %f16, %f21
46797fadds %f16, %f17, %f16
46798fmovd %f20, %f34
46799membar #Sync
46800stda %f32, [%i3 + 0 ] %asi
46801
46802P4296: !_MEMBAR (FP)
46803membar #StoreLoad
46804
46805P4297: !_DWST_BINIT [13] (maybe <- 0x200007a) (Int)
46806wr %g0, 0xe2, %asi
46807sllx %l4, 32, %l6
46808add %l4, 1, %l4
46809or %l6, %l4, %l6
46810stxa %l6, [%i2 + 0] %asi
46811add %l4, 1, %l4
46812
46813P4298: !_MEMBAR (Int) (CBR)
46814membar #StoreLoad
46815
46816! cbranch
46817andcc %l0, 1, %g0
46818be,pt %xcc, TARGET4298
46819nop
46820RET4298:
46821
46822! lfsr step begin
46823srlx %l0, 1, %l3
46824xnor %l3, %l0, %l3
46825sllx %l3, 63, %l3
46826or %l3, %l0, %l0
46827srlx %l0, 1, %l0
46828
46829
46830P4299: !_DWST [3] (maybe <- 0x4180004a) (FP)
46831! preparing store val #0, next val will be in f20
46832fmovs %f16, %f20
46833fadds %f16, %f17, %f16
46834! preparing store val #1, next val will be in f21
46835fmovs %f16, %f21
46836fadds %f16, %f17, %f16
46837std %f20, [%i1 + 0]
46838
46839P4300: !_MEMBAR (FP)
46840
46841P4301: !_BST [23] (maybe <- 0x4180004c) (FP)
46842wr %g0, 0xf0, %asi
46843sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
46844sub %i0, %i2, %i2
46845! preparing store val #0, next val will be in f32
46846fmovs %f16, %f20
46847fadds %f16, %f17, %f16
46848! preparing store val #1, next val will be in f33
46849fmovs %f16, %f21
46850fadds %f16, %f17, %f16
46851! preparing store val #2, next val will be in f35
46852fmovd %f20, %f32
46853fmovs %f16, %f21
46854fadds %f16, %f17, %f16
46855fmovd %f20, %f34
46856membar #Sync
46857stda %f32, [%i2 + 0 ] %asi
46858
46859P4302: !_MEMBAR (FP)
46860membar #StoreLoad
46861
46862P4303: !_DWST_BINIT [0] (maybe <- 0x200007c) (Int)
46863wr %g0, 0xe2, %asi
46864sllx %l4, 32, %o5
46865add %l4, 1, %l4
46866or %o5, %l4, %o5
46867stxa %o5, [%i0 + 0] %asi
46868add %l4, 1, %l4
46869
46870P4304: !_MEMBAR (Int)
46871membar #StoreLoad
46872
46873P4305: !_CAS [10] (maybe <- 0x200007e) (Int)
46874sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
46875sub %i0, %i3, %i3
46876add %i3, 4, %o5
46877lduw [%o5], %o2
46878mov %o2, %l7
46879! move %l7(lower) -> %o2(upper)
46880sllx %l7, 32, %o2
46881mov %l4, %l6
46882cas [%o5], %l7, %l6
46883! move %l6(lower) -> %o2(lower)
46884srl %l6, 0, %l7
46885or %l7, %o2, %o2
46886add %l4, 1, %l4
46887
46888P4306: !_LDD [12] (Int)
46889sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
46890sub %i0, %i2, %i2
46891ldd [%i2 + 0], %l6
46892! move %l6(lower) -> %o3(upper)
46893sllx %l6, 32, %o3
46894! move %l7(lower) -> %o3(lower)
46895or %l7, %o3, %o3
46896
46897P4307: !_LDD [8] (Int)
46898sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
46899add %i0, %i3, %i3
46900ldd [%i3 + 8], %l6
46901! move %l7(lower) -> %o4(upper)
46902sllx %l7, 32, %o4
46903
46904P4308: !_MEMBAR (FP)
46905
46906P4309: !_BSTC [2] (maybe <- 0x4180004f) (FP)
46907wr %g0, 0xe0, %asi
46908! preparing store val #0, next val will be in f32
46909fmovs %f16, %f20
46910fadds %f16, %f17, %f16
46911! preparing store val #1, next val will be in f33
46912fmovs %f16, %f21
46913fadds %f16, %f17, %f16
46914! preparing store val #2, next val will be in f35
46915fmovd %f20, %f32
46916fmovs %f16, %f21
46917fadds %f16, %f17, %f16
46918fmovd %f20, %f34
46919membar #Sync
46920stda %f32, [%i0 + 0 ] %asi
46921
46922P4310: !_MEMBAR (FP)
46923membar #StoreLoad
46924
46925P4311: !_BLD [20] (FP) (CBR)
46926wr %g0, 0xf0, %asi
46927sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
46928sub %i0, %i2, %i2
46929ldda [%i2 + 0] %asi, %f32
46930membar #Sync
46931! 3 addresses covered
46932fmovd %f32, %f18
46933fmovs %f18, %f11
46934fmovs %f19, %f12
46935fmovd %f34, %f18
46936fmovs %f19, %f13
46937
46938! cbranch
46939andcc %l0, 1, %g0
46940be,pn %xcc, TARGET4311
46941nop
46942RET4311:
46943
46944! lfsr step begin
46945srlx %l0, 1, %o5
46946xnor %o5, %l0, %o5
46947sllx %o5, 63, %o5
46948or %o5, %l0, %l0
46949srlx %l0, 1, %l0
46950
46951
46952P4312: !_MEMBAR (FP)
46953
46954P4313: !_DWST [23] (maybe <- 0x41800052) (FP)
46955sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
46956sub %i0, %i3, %i3
46957! preparing store val #0, next val will be in f21
46958fmovs %f16, %f21
46959fadds %f16, %f17, %f16
46960std %f20, [%i3 + 8]
46961
46962P4314: !_CASX [21] (maybe <- 0x200007f) (Int)
46963ldx [%i3], %l7
46964! move %l7(upper) -> %o4(lower)
46965srlx %l7, 32, %o5
46966or %o5, %o4, %o4
46967!---- flushing int results buffer----
46968mov %o0, %l5
46969mov %o1, %l5
46970mov %o2, %l5
46971mov %o3, %l5
46972mov %o4, %l5
46973! move %l7(lower) -> %o0(upper)
46974sllx %l7, 32, %o0
46975mov %l7, %o5
46976sllx %l4, 32, %l7
46977add %l4, 1, %l4
46978or %l4, %l7, %l7
46979casx [%i3], %o5, %l7
46980! move %l7(upper) -> %o0(lower)
46981srlx %l7, 32, %o5
46982or %o5, %o0, %o0
46983! move %l7(lower) -> %o1(upper)
46984sllx %l7, 32, %o1
46985add %l4, 1, %l4
46986
46987P4315: !_CAS [6] (maybe <- 0x2000081) (Int)
46988sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
46989add %i0, %i2, %i2
46990lduw [%i2], %l7
46991mov %l7, %o5
46992! move %o5(lower) -> %o1(lower)
46993or %o5, %o1, %o1
46994mov %l4, %o2
46995cas [%i2], %o5, %o2
46996! move %o2(lower) -> %o2(upper)
46997sllx %o2, 32, %o2
46998add %l4, 1, %l4
46999
47000P4316: !_DWST_BINIT [3] (maybe <- 0x2000082) (Int)
47001wr %g0, 0xe2, %asi
47002sllx %l4, 32, %o5
47003add %l4, 1, %l4
47004or %o5, %l4, %o5
47005stxa %o5, [%i1 + 0] %asi
47006add %l4, 1, %l4
47007
47008P4317: !_MEMBAR (Int)
47009membar #StoreLoad
47010
47011P4318: !_ST [18] (maybe <- 0x2000084) (Int)
47012sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
47013sub %i0, %i3, %i3
47014stw %l4, [%i3 + 0 ]
47015add %l4, 1, %l4
47016
47017P4319: !_CASX [3] (maybe <- 0x2000085) (Int) (LE) (Branch target of P4285)
47018sllx %l4, 32, %l7
47019add %l4, 1, %l4
47020or %l4, %l7, %l7
47021! Change double-word-level endianess (big endian <-> little endian)
47022sethi %hi(0xff00ff00), %l6
47023or %l6, %lo(0xff00ff00), %l6
47024sllx %l6, 32, %o5
47025or %l6, %o5, %l6
47026and %l7, %l6, %o5
47027srlx %o5, 8, %o5
47028sllx %l7, 8, %l7
47029and %l7, %l6, %l7
47030or %l7, %o5, %l7
47031sethi %hi(0xffff0000), %l6
47032srlx %l7, 16, %o5
47033andn %o5, %l6, %o5
47034andn %l7, %l6, %l7
47035sllx %l7, 16, %l7
47036or %l7, %o5, %l7
47037srlx %l7, 32, %o5
47038sllx %l7, 32, %l7
47039or %l7, %o5, %o5
47040wr %g0, 0x88, %asi
47041ldxa [%i1] %asi, %l3
47042! move %l3(lower) -> %o2(lower)
47043srl %l3, 0, %l6
47044or %l6, %o2, %o2
47045! move %l3(upper) -> %o3(upper)
47046or %l3, %g0, %o3
47047mov %l3, %l6
47048mov %o5, %l3
47049casxa [%i1] %asi, %l6, %l3
47050! move %l3(lower) -> %o3(lower)
47051srlx %o3, 32, %o3
47052sllx %o3, 32, %o3
47053srl %l3, 0, %l6
47054or %l6, %o3, %o3
47055! move %l3(upper) -> %o4(upper)
47056or %l3, %g0, %o4
47057add %l4, 1, %l4
47058ba P4320
47059nop
47060
47061TARGET4285:
47062ba RET4285
47063nop
47064
47065
47066P4320: !_REPLACEMENT [15] (Int)
47067sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
47068add %i0, %i2, %i2
47069sethi %hi(0x20000), %l6
47070ld [%i2+0], %o5
47071st %o5, [%i2+0]
47072add %i2, %l6, %l7
47073ld [%l7+0], %o5
47074st %o5, [%l7+0]
47075add %l7, %l6, %l7
47076ld [%l7+0], %o5
47077st %o5, [%l7+0]
47078add %l7, %l6, %l7
47079ld [%l7+0], %o5
47080st %o5, [%l7+0]
47081add %l7, %l6, %l7
47082ld [%l7+0], %o5
47083st %o5, [%l7+0]
47084add %l7, %l6, %l7
47085ld [%l7+0], %o5
47086st %o5, [%l7+0]
47087add %l7, %l6, %l7
47088ld [%l7+0], %o5
47089st %o5, [%l7+0]
47090add %l7, %l6, %l7
47091ld [%l7+0], %o5
47092st %o5, [%l7+0]
47093
47094P4321: !_PREFETCH [15] (Int)
47095sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
47096sub %i0, %i3, %i3
47097prefetch [%i3 + 0], 21
47098
47099P4322: !_CAS [4] (maybe <- 0x2000087) (Int)
47100add %i1, 4, %l6
47101lduw [%l6], %o5
47102mov %o5, %l3
47103! move %l3(lower) -> %o4(lower)
47104srlx %o4, 32, %o4
47105sllx %o4, 32, %o4
47106or %l3, %o4, %o4
47107!---- flushing int results buffer----
47108mov %o0, %l5
47109mov %o1, %l5
47110mov %o2, %l5
47111mov %o3, %l5
47112mov %o4, %l5
47113mov %l4, %o0
47114cas [%l6], %l3, %o0
47115! move %o0(lower) -> %o0(upper)
47116sllx %o0, 32, %o0
47117add %l4, 1, %l4
47118
47119P4323: !_SWAP [13] (maybe <- 0x2000088) (Int)
47120sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
47121sub %i0, %i2, %i2
47122mov %l4, %l7
47123swap [%i2 + 4], %l7
47124! move %l7(lower) -> %o0(lower)
47125srl %l7, 0, %l3
47126or %l3, %o0, %o0
47127add %l4, 1, %l4
47128
47129P4324: !_ST_BINIT [21] (maybe <- 0x2000089) (Int)
47130wr %g0, 0xe2, %asi
47131sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
47132sub %i0, %i3, %i3
47133stwa %l4, [%i3 + 0] %asi
47134add %l4, 1, %l4
47135
47136P4325: !_MEMBAR (Int)
47137membar #StoreLoad
47138
47139P4326: !_CASX [6] (maybe <- 0x200008a) (Int)
47140sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
47141add %i0, %i2, %i2
47142ldx [%i2], %o1
47143! move %o1(upper) -> %o1(upper)
47144! move %o1(lower) -> %o1(lower)
47145mov %o1, %l7
47146sllx %l4, 32, %o2
47147add %l4, 1, %l4
47148or %l4, %o2, %o2
47149casx [%i2], %l7, %o2
47150! move %o2(upper) -> %o2(upper)
47151! move %o2(lower) -> %o2(lower)
47152add %l4, 1, %l4
47153
47154P4327: !_ST_BINIT [0] (maybe <- 0x200008c) (Int)
47155wr %g0, 0xe2, %asi
47156stwa %l4, [%i0 + 0] %asi
47157add %l4, 1, %l4
47158
47159P4328: !_MEMBAR (Int)
47160membar #StoreLoad
47161
47162P4329: !_PREFETCH [11] (Int)
47163sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
47164sub %i0, %i3, %i3
47165prefetch [%i3 + 12], 30
47166
47167P4330: !_LDD [14] (Int)
47168sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
47169sub %i0, %i2, %i2
47170ldd [%i2 + 8], %l6
47171! move %l7(lower) -> %o3(upper)
47172sllx %l7, 32, %o3
47173
47174P4331: !_DWST_BINIT [14] (maybe <- 0x200008d) (Int)
47175wr %g0, 0xe2, %asi
47176mov %l4, %l3
47177stxa %l3, [%i2 + 8] %asi
47178add %l4, 1, %l4
47179
47180P4332: !_MEMBAR (Int)
47181membar #StoreLoad
47182
47183P4333: !_CAS [19] (maybe <- 0x200008e) (Int)
47184sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
47185sub %i0, %i3, %i3
47186add %i3, 4, %l3
47187lduw [%l3], %l7
47188mov %l7, %o5
47189! move %o5(lower) -> %o3(lower)
47190or %o5, %o3, %o3
47191mov %l4, %o4
47192cas [%l3], %o5, %o4
47193! move %o4(lower) -> %o4(upper)
47194sllx %o4, 32, %o4
47195add %l4, 1, %l4
47196
47197P4334: !_MEMBAR (FP)
47198
47199P4335: !_BSTC [23] (maybe <- 0x41800053) (FP)
47200wr %g0, 0xe0, %asi
47201sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
47202sub %i0, %i2, %i2
47203! preparing store val #0, next val will be in f32
47204fmovs %f16, %f20
47205fadds %f16, %f17, %f16
47206! preparing store val #1, next val will be in f33
47207fmovs %f16, %f21
47208fadds %f16, %f17, %f16
47209! preparing store val #2, next val will be in f35
47210fmovd %f20, %f32
47211fmovs %f16, %f21
47212fadds %f16, %f17, %f16
47213fmovd %f20, %f34
47214membar #Sync
47215stda %f32, [%i2 + 0 ] %asi
47216
47217P4336: !_MEMBAR (FP)
47218membar #StoreLoad
47219
47220P4337: !_ST [5] (maybe <- 0x200008f) (Int)
47221stw %l4, [%i1 + 12 ]
47222add %l4, 1, %l4
47223
47224P4338: !_ST [8] (maybe <- 0x41800056) (FP)
47225sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
47226add %i0, %i3, %i3
47227! preparing store val #0, next val will be in f20
47228fmovs %f16, %f20
47229fadds %f16, %f17, %f16
47230st %f20, [%i3 + 12 ]
47231
47232P4339: !_LD [13] (Int)
47233sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
47234sub %i0, %i2, %i2
47235lduw [%i2 + 4], %l6
47236! move %l6(lower) -> %o4(lower)
47237or %l6, %o4, %o4
47238!---- flushing int results buffer----
47239mov %o0, %l5
47240mov %o1, %l5
47241mov %o2, %l5
47242mov %o3, %l5
47243mov %o4, %l5
47244
47245P4340: !_PREFETCH [1] (Int)
47246prefetch [%i0 + 4], 23
47247
47248P4341: !_SWAP [6] (maybe <- 0x2000090) (Int)
47249mov %l4, %o0
47250swap [%i3 + 0], %o0
47251! move %o0(lower) -> %o0(upper)
47252sllx %o0, 32, %o0
47253add %l4, 1, %l4
47254
47255P4342: !_ST_BINIT [15] (maybe <- 0x2000091) (Int)
47256wr %g0, 0xe2, %asi
47257sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
47258sub %i0, %i3, %i3
47259stwa %l4, [%i3 + 0] %asi
47260add %l4, 1, %l4
47261
47262P4343: !_MEMBAR (Int)
47263
47264P4344: !_BST [14] (maybe <- 0x41800057) (FP)
47265wr %g0, 0xf0, %asi
47266! preparing store val #0, next val will be in f32
47267fmovs %f16, %f20
47268fadds %f16, %f17, %f16
47269! preparing store val #1, next val will be in f33
47270fmovs %f16, %f21
47271fadds %f16, %f17, %f16
47272! preparing store val #2, next val will be in f35
47273fmovd %f20, %f32
47274fmovs %f16, %f21
47275fadds %f16, %f17, %f16
47276fmovd %f20, %f34
47277membar #Sync
47278stda %f32, [%i2 + 0 ] %asi
47279
47280P4345: !_MEMBAR (FP) (CBR)
47281membar #StoreLoad
47282
47283! cbranch
47284andcc %l0, 1, %g0
47285be,pn %xcc, TARGET4345
47286nop
47287RET4345:
47288
47289! lfsr step begin
47290srlx %l0, 1, %o5
47291xnor %o5, %l0, %o5
47292sllx %o5, 63, %o5
47293or %o5, %l0, %l0
47294srlx %l0, 1, %l0
47295
47296
47297P4346: !_LD [13] (Int)
47298lduw [%i2 + 4], %l6
47299! move %l6(lower) -> %o0(lower)
47300or %l6, %o0, %o0
47301
47302P4347: !_PREFETCH [16] (Int) (CBR)
47303prefetch [%i3 + 4], 23
47304
47305! cbranch
47306andcc %l0, 1, %g0
47307be,pn %xcc, TARGET4347
47308nop
47309RET4347:
47310
47311! lfsr step begin
47312srlx %l0, 1, %l7
47313xnor %l7, %l0, %l7
47314sllx %l7, 63, %l7
47315or %l7, %l0, %l0
47316srlx %l0, 1, %l0
47317
47318
47319P4348: !_MEMBAR (FP)
47320
47321P4349: !_BST [18] (maybe <- 0x4180005a) (FP)
47322wr %g0, 0xf0, %asi
47323sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
47324sub %i0, %i2, %i2
47325! preparing store val #0, next val will be in f32
47326fmovs %f16, %f20
47327fadds %f16, %f17, %f16
47328! preparing store val #1, next val will be in f33
47329fmovs %f16, %f21
47330fadds %f16, %f17, %f16
47331! preparing store val #2, next val will be in f35
47332fmovd %f20, %f32
47333fmovs %f16, %f21
47334fadds %f16, %f17, %f16
47335fmovd %f20, %f34
47336membar #Sync
47337stda %f32, [%i2 + 0 ] %asi
47338
47339P4350: !_MEMBAR (FP)
47340membar #StoreLoad
47341
47342P4351: !_PREFETCH [3] (Int)
47343prefetch [%i1 + 0], 21
47344
47345P4352: !_DWST [3] (maybe <- 0x2000092) (Int)
47346sllx %l4, 32, %l7
47347add %l4, 1, %l4
47348or %l7, %l4, %l7
47349stx %l7, [%i1 + 0]
47350add %l4, 1, %l4
47351
47352P4353: !_PREFETCH [12] (Int)
47353sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
47354sub %i0, %i3, %i3
47355prefetch [%i3 + 0], 16
47356
47357P4354: !_MEMBAR (FP)
47358
47359P4355: !_BSTC [20] (maybe <- 0x4180005d) (FP)
47360wr %g0, 0xe0, %asi
47361! preparing store val #0, next val will be in f32
47362fmovs %f16, %f20
47363fadds %f16, %f17, %f16
47364! preparing store val #1, next val will be in f33
47365fmovs %f16, %f21
47366fadds %f16, %f17, %f16
47367! preparing store val #2, next val will be in f35
47368fmovd %f20, %f32
47369fmovs %f16, %f21
47370fadds %f16, %f17, %f16
47371fmovd %f20, %f34
47372membar #Sync
47373stda %f32, [%i2 + 0 ] %asi
47374
47375P4356: !_MEMBAR (FP) (CBR)
47376membar #StoreLoad
47377
47378! cbranch
47379andcc %l0, 1, %g0
47380be,pt %xcc, TARGET4356
47381nop
47382RET4356:
47383
47384! lfsr step begin
47385srlx %l0, 1, %l3
47386xnor %l3, %l0, %l3
47387sllx %l3, 63, %l3
47388or %l3, %l0, %l0
47389srlx %l0, 1, %l0
47390
47391
47392P4357: !_BLD [2] (FP)
47393wr %g0, 0xf0, %asi
47394ldda [%i0 + 0] %asi, %f32
47395membar #Sync
47396! 3 addresses covered
47397fmovd %f32, %f14
47398!---- flushing fp results buffer to %f30 ----
47399fmovd %f0, %f30
47400fmovd %f2, %f30
47401fmovd %f4, %f30
47402fmovd %f6, %f30
47403fmovd %f8, %f30
47404fmovd %f10, %f30
47405fmovd %f12, %f30
47406fmovd %f14, %f30
47407!--
47408fmovd %f34, %f18
47409fmovs %f19, %f0
47410
47411P4358: !_MEMBAR (FP)
47412
47413P4359: !_ST [0] (maybe <- 0x2000094) (Int)
47414stw %l4, [%i0 + 0 ]
47415add %l4, 1, %l4
47416
47417P4360: !_DWST_BINIT [11] (maybe <- 0x2000095) (Int)
47418wr %g0, 0xe2, %asi
47419sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
47420sub %i0, %i2, %i2
47421mov %l4, %l3
47422stxa %l3, [%i2 + 8] %asi
47423add %l4, 1, %l4
47424
47425P4361: !_MEMBAR (Int)
47426membar #StoreLoad
47427
47428P4362: !_DWST [12] (maybe <- 0x2000096) (Int)
47429sllx %l4, 32, %o5
47430add %l4, 1, %l4
47431or %o5, %l4, %o5
47432stx %o5, [%i3 + 0]
47433add %l4, 1, %l4
47434
47435P4363: !_CAS [0] (maybe <- 0x2000098) (Int)
47436lduw [%i0], %o1
47437mov %o1, %l7
47438! move %l7(lower) -> %o1(upper)
47439sllx %l7, 32, %o1
47440mov %l4, %l6
47441cas [%i0], %l7, %l6
47442! move %l6(lower) -> %o1(lower)
47443srl %l6, 0, %l7
47444or %l7, %o1, %o1
47445add %l4, 1, %l4
47446
47447P4364: !_PREFETCH [0] (Int)
47448prefetch [%i0 + 0], 20
47449
47450P4365: !_MEMBAR (FP) (Branch target of P4842)
47451ba P4366
47452nop
47453
47454TARGET4842:
47455ba RET4842
47456nop
47457
47458
47459P4366: !_BSTC [5] (maybe <- 0x41800060) (FP)
47460wr %g0, 0xe0, %asi
47461! preparing store val #0, next val will be in f32
47462fmovs %f16, %f20
47463fadds %f16, %f17, %f16
47464! preparing store val #1, next val will be in f33
47465fmovs %f16, %f21
47466fadds %f16, %f17, %f16
47467! preparing store val #2, next val will be in f35
47468fmovd %f20, %f32
47469fmovs %f16, %f21
47470fadds %f16, %f17, %f16
47471fmovd %f20, %f34
47472membar #Sync
47473stda %f32, [%i1 + 0 ] %asi
47474
47475P4367: !_MEMBAR (FP) (CBR)
47476membar #StoreLoad
47477
47478! cbranch
47479andcc %l0, 1, %g0
47480be,pn %xcc, TARGET4367
47481nop
47482RET4367:
47483
47484! lfsr step begin
47485srlx %l0, 1, %l6
47486xnor %l6, %l0, %l6
47487sllx %l6, 63, %l6
47488or %l6, %l0, %l0
47489srlx %l0, 1, %l0
47490
47491
47492P4368: !_BLD [3] (FP)
47493wr %g0, 0xf0, %asi
47494ldda [%i1 + 0] %asi, %f32
47495membar #Sync
47496! 3 addresses covered
47497fmovd %f32, %f18
47498fmovs %f18, %f1
47499fmovs %f19, %f2
47500fmovd %f34, %f18
47501fmovs %f19, %f3
47502
47503P4369: !_MEMBAR (FP)
47504
47505P4370: !_PREFETCH [2] (Int)
47506prefetch [%i0 + 12], 21
47507
47508P4371: !_ST [14] (maybe <- 0x2000099) (Int) (Branch target of P4709)
47509stw %l4, [%i3 + 12 ]
47510add %l4, 1, %l4
47511ba P4372
47512nop
47513
47514TARGET4709:
47515ba RET4709
47516nop
47517
47518
47519P4372: !_CAS [9] (maybe <- 0x200009a) (Int)
47520lduw [%i2], %o2
47521mov %o2, %l6
47522! move %l6(lower) -> %o2(upper)
47523sllx %l6, 32, %o2
47524mov %l4, %l3
47525cas [%i2], %l6, %l3
47526! move %l3(lower) -> %o2(lower)
47527srl %l3, 0, %l6
47528or %l6, %o2, %o2
47529add %l4, 1, %l4
47530
47531P4373: !_LD [3] (Int)
47532lduw [%i1 + 0], %o3
47533! move %o3(lower) -> %o3(upper)
47534sllx %o3, 32, %o3
47535
47536P4374: !_SWAP [15] (maybe <- 0x200009b) (Int)
47537sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
47538sub %i0, %i3, %i3
47539mov %l4, %l6
47540swap [%i3 + 0], %l6
47541! move %l6(lower) -> %o3(lower)
47542srl %l6, 0, %o5
47543or %o5, %o3, %o3
47544add %l4, 1, %l4
47545
47546P4375: !_CASX [14] (maybe <- 0x200009c) (Int) (Branch target of P4609)
47547sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
47548sub %i0, %i2, %i2
47549add %i2, 8, %o5
47550ldx [%o5], %o4
47551! move %o4(upper) -> %o4(upper)
47552! move %o4(lower) -> %o4(lower)
47553!---- flushing int results buffer----
47554mov %o0, %l5
47555mov %o1, %l5
47556mov %o2, %l5
47557mov %o3, %l5
47558mov %o4, %l5
47559mov %o4, %l7
47560mov %l4, %o0
47561casx [%o5], %l7, %o0
47562! move %o0(upper) -> %o0(upper)
47563! move %o0(lower) -> %o0(lower)
47564add %l4, 1, %l4
47565ba P4376
47566nop
47567
47568TARGET4609:
47569ba RET4609
47570nop
47571
47572
47573P4376: !_MEMBAR (FP)
47574
47575P4377: !_BST [13] (maybe <- 0x41800063) (FP)
47576wr %g0, 0xf0, %asi
47577! preparing store val #0, next val will be in f32
47578fmovs %f16, %f20
47579fadds %f16, %f17, %f16
47580! preparing store val #1, next val will be in f33
47581fmovs %f16, %f21
47582fadds %f16, %f17, %f16
47583! preparing store val #2, next val will be in f35
47584fmovd %f20, %f32
47585fmovs %f16, %f21
47586fadds %f16, %f17, %f16
47587fmovd %f20, %f34
47588membar #Sync
47589stda %f32, [%i2 + 0 ] %asi
47590
47591P4378: !_MEMBAR (FP)
47592membar #StoreLoad
47593
47594P4379: !_CASX [6] (maybe <- 0x200009d) (Int)
47595sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
47596add %i0, %i3, %i3
47597ldx [%i3], %o1
47598! move %o1(upper) -> %o1(upper)
47599! move %o1(lower) -> %o1(lower)
47600mov %o1, %l6
47601sllx %l4, 32, %o2
47602add %l4, 1, %l4
47603or %l4, %o2, %o2
47604casx [%i3], %l6, %o2
47605! move %o2(upper) -> %o2(upper)
47606! move %o2(lower) -> %o2(lower)
47607add %l4, 1, %l4
47608
47609P4380: !_DWST [23] (maybe <- 0x200009f) (Int)
47610sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
47611sub %i0, %i2, %i2
47612mov %l4, %l6
47613stx %l6, [%i2 + 8]
47614add %l4, 1, %l4
47615
47616P4381: !_DWST_BINIT [12] (maybe <- 0x20000a0) (Int)
47617wr %g0, 0xe2, %asi
47618sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
47619sub %i0, %i3, %i3
47620sllx %l4, 32, %l3
47621add %l4, 1, %l4
47622or %l3, %l4, %l3
47623stxa %l3, [%i3 + 0] %asi
47624add %l4, 1, %l4
47625
47626P4382: !_MEMBAR (Int)
47627membar #StoreLoad
47628
47629P4383: !_ST [2] (maybe <- 0x20000a2) (Int)
47630stw %l4, [%i0 + 12 ]
47631add %l4, 1, %l4
47632
47633P4384: !_SWAP [20] (maybe <- 0x20000a3) (Int)
47634sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
47635sub %i0, %i2, %i2
47636mov %l4, %o3
47637swap [%i2 + 12], %o3
47638! move %o3(lower) -> %o3(upper)
47639sllx %o3, 32, %o3
47640add %l4, 1, %l4
47641
47642P4385: !_PREFETCH [13] (Int)
47643prefetch [%i3 + 4], 1
47644
47645P4386: !_LDD [8] (Int)
47646sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
47647add %i0, %i3, %i3
47648ldd [%i3 + 8], %l6
47649! move %l7(lower) -> %o3(lower)
47650or %l7, %o3, %o3
47651
47652P4387: !_CAS [15] (maybe <- 0x20000a4) (Int)
47653sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
47654sub %i0, %i2, %i2
47655lduw [%i2], %o4
47656mov %o4, %l3
47657! move %l3(lower) -> %o4(upper)
47658sllx %l3, 32, %o4
47659mov %l4, %o5
47660cas [%i2], %l3, %o5
47661! move %o5(lower) -> %o4(lower)
47662srl %o5, 0, %l3
47663or %l3, %o4, %o4
47664!---- flushing int results buffer----
47665mov %o0, %l5
47666mov %o1, %l5
47667mov %o2, %l5
47668mov %o3, %l5
47669mov %o4, %l5
47670add %l4, 1, %l4
47671
47672P4388: !_MEMBAR (FP)
47673
47674P4389: !_BSTC [13] (maybe <- 0x41800066) (FP)
47675wr %g0, 0xe0, %asi
47676sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
47677sub %i0, %i3, %i3
47678! preparing store val #0, next val will be in f32
47679fmovs %f16, %f20
47680fadds %f16, %f17, %f16
47681! preparing store val #1, next val will be in f33
47682fmovs %f16, %f21
47683fadds %f16, %f17, %f16
47684! preparing store val #2, next val will be in f35
47685fmovd %f20, %f32
47686fmovs %f16, %f21
47687fadds %f16, %f17, %f16
47688fmovd %f20, %f34
47689membar #Sync
47690stda %f32, [%i3 + 0 ] %asi
47691
47692P4390: !_MEMBAR (FP)
47693membar #StoreLoad
47694
47695P4391: !_REPLACEMENT [7] (Int)
47696sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
47697sub %i0, %i2, %i2
47698sethi %hi(0x20000), %o5
47699ld [%i2+4], %l6
47700st %l6, [%i2+4]
47701add %i2, %o5, %l3
47702ld [%l3+4], %l6
47703st %l6, [%l3+4]
47704add %l3, %o5, %l3
47705ld [%l3+4], %l6
47706st %l6, [%l3+4]
47707add %l3, %o5, %l3
47708ld [%l3+4], %l6
47709st %l6, [%l3+4]
47710add %l3, %o5, %l3
47711ld [%l3+4], %l6
47712st %l6, [%l3+4]
47713add %l3, %o5, %l3
47714ld [%l3+4], %l6
47715st %l6, [%l3+4]
47716add %l3, %o5, %l3
47717ld [%l3+4], %l6
47718st %l6, [%l3+4]
47719add %l3, %o5, %l3
47720ld [%l3+4], %l6
47721st %l6, [%l3+4]
47722
47723P4392: !_CASX [22] (maybe <- 0x20000a5) (Int)
47724sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
47725sub %i0, %i3, %i3
47726ldx [%i3], %o0
47727! move %o0(upper) -> %o0(upper)
47728! move %o0(lower) -> %o0(lower)
47729mov %o0, %l7
47730sllx %l4, 32, %o1
47731add %l4, 1, %l4
47732or %l4, %o1, %o1
47733casx [%i3], %l7, %o1
47734! move %o1(upper) -> %o1(upper)
47735! move %o1(lower) -> %o1(lower)
47736add %l4, 1, %l4
47737
47738P4393: !_MEMBAR (FP)
47739
47740P4394: !_BST [6] (maybe <- 0x41800069) (FP)
47741wr %g0, 0xf0, %asi
47742sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
47743add %i0, %i2, %i2
47744! preparing store val #0, next val will be in f32
47745fmovs %f16, %f20
47746fadds %f16, %f17, %f16
47747! preparing store val #1, next val will be in f33
47748fmovs %f16, %f21
47749fadds %f16, %f17, %f16
47750! preparing store val #2, next val will be in f35
47751fmovd %f20, %f32
47752fmovs %f16, %f21
47753fadds %f16, %f17, %f16
47754fmovd %f20, %f34
47755membar #Sync
47756stda %f32, [%i2 + 0 ] %asi
47757
47758P4395: !_MEMBAR (FP)
47759membar #StoreLoad
47760
47761P4396: !_LDD [8] (Int) (LE)
47762wr %g0, 0x88, %asi
47763ldda [%i2 + 8] %asi, %l6
47764! move %l7(lower) -> %o2(upper)
47765sllx %l7, 32, %o2
47766
47767P4397: !_LD [22] (Int)
47768lduw [%i3 + 4], %l6
47769! move %l6(lower) -> %o2(lower)
47770or %l6, %o2, %o2
47771
47772P4398: !_ST_BINIT [11] (maybe <- 0x20000a7) (Int)
47773wr %g0, 0xe2, %asi
47774sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
47775sub %i0, %i3, %i3
47776stwa %l4, [%i3 + 12] %asi
47777add %l4, 1, %l4
47778
47779P4399: !_MEMBAR (Int)
47780membar #StoreLoad
47781
47782P4400: !_DWST_BINIT [10] (maybe <- 0x20000a8) (Int)
47783wr %g0, 0xe2, %asi
47784sllx %l4, 32, %l6
47785add %l4, 1, %l4
47786or %l6, %l4, %l6
47787stxa %l6, [%i3 + 0] %asi
47788add %l4, 1, %l4
47789
47790P4401: !_MEMBAR (Int)
47791membar #StoreLoad
47792
47793P4402: !_REPLACEMENT [5] (Int)
47794sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
47795sub %i0, %i2, %i2
47796sethi %hi(0x20000), %l3
47797ld [%i2+12], %l7
47798st %l7, [%i2+12]
47799add %i2, %l3, %l6
47800ld [%l6+12], %l7
47801st %l7, [%l6+12]
47802add %l6, %l3, %l6
47803ld [%l6+12], %l7
47804st %l7, [%l6+12]
47805add %l6, %l3, %l6
47806ld [%l6+12], %l7
47807st %l7, [%l6+12]
47808add %l6, %l3, %l6
47809ld [%l6+12], %l7
47810st %l7, [%l6+12]
47811add %l6, %l3, %l6
47812ld [%l6+12], %l7
47813st %l7, [%l6+12]
47814add %l6, %l3, %l6
47815ld [%l6+12], %l7
47816st %l7, [%l6+12]
47817add %l6, %l3, %l6
47818ld [%l6+12], %l7
47819st %l7, [%l6+12]
47820
47821P4403: !_ST [6] (maybe <- 0x20000aa) (Int)
47822sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
47823add %i0, %i3, %i3
47824stw %l4, [%i3 + 0 ]
47825add %l4, 1, %l4
47826
47827P4404: !_DWST_BINIT [0] (maybe <- 0x20000ab) (Int)
47828wr %g0, 0xe2, %asi
47829sllx %l4, 32, %l7
47830add %l4, 1, %l4
47831or %l7, %l4, %l7
47832stxa %l7, [%i0 + 0] %asi
47833add %l4, 1, %l4
47834
47835P4405: !_MEMBAR (Int)
47836
47837P4406: !_BSTC [18] (maybe <- 0x4180006c) (FP)
47838wr %g0, 0xe0, %asi
47839sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
47840sub %i0, %i2, %i2
47841! preparing store val #0, next val will be in f32
47842fmovs %f16, %f20
47843fadds %f16, %f17, %f16
47844! preparing store val #1, next val will be in f33
47845fmovs %f16, %f21
47846fadds %f16, %f17, %f16
47847! preparing store val #2, next val will be in f35
47848fmovd %f20, %f32
47849fmovs %f16, %f21
47850fadds %f16, %f17, %f16
47851fmovd %f20, %f34
47852membar #Sync
47853stda %f32, [%i2 + 0 ] %asi
47854
47855P4407: !_MEMBAR (FP)
47856membar #StoreLoad
47857
47858P4408: !_BLD [7] (FP)
47859wr %g0, 0xf0, %asi
47860ldda [%i3 + 0] %asi, %f32
47861membar #Sync
47862! 3 addresses covered
47863fmovd %f32, %f4
47864fmovd %f34, %f18
47865fmovs %f19, %f6
47866
47867P4409: !_MEMBAR (FP)
47868
47869P4410: !_CASX [22] (maybe <- 0x20000ad) (Int)
47870sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
47871sub %i0, %i3, %i3
47872ldx [%i3], %o3
47873! move %o3(upper) -> %o3(upper)
47874! move %o3(lower) -> %o3(lower)
47875mov %o3, %l3
47876sllx %l4, 32, %o4
47877add %l4, 1, %l4
47878or %l4, %o4, %o4
47879casx [%i3], %l3, %o4
47880! move %o4(upper) -> %o4(upper)
47881! move %o4(lower) -> %o4(lower)
47882!---- flushing int results buffer----
47883mov %o0, %l5
47884mov %o1, %l5
47885mov %o2, %l5
47886mov %o3, %l5
47887mov %o4, %l5
47888add %l4, 1, %l4
47889
47890P4411: !_ST [0] (maybe <- 0x20000af) (Int)
47891stw %l4, [%i0 + 0 ]
47892add %l4, 1, %l4
47893
47894P4412: !_SWAP [7] (maybe <- 0x20000b0) (Int)
47895sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
47896add %i0, %i2, %i2
47897mov %l4, %o0
47898swap [%i2 + 4], %o0
47899! move %o0(lower) -> %o0(upper)
47900sllx %o0, 32, %o0
47901add %l4, 1, %l4
47902
47903P4413: !_LDD [4] (Int) (CBR)
47904ldd [%i1 + 0], %l6
47905! move %l6(lower) -> %o0(lower)
47906or %l6, %o0, %o0
47907! move %l7(lower) -> %o1(upper)
47908sllx %l7, 32, %o1
47909
47910! cbranch
47911andcc %l0, 1, %g0
47912be,pt %xcc, TARGET4413
47913nop
47914RET4413:
47915
47916! lfsr step begin
47917srlx %l0, 1, %l3
47918xnor %l3, %l0, %l3
47919sllx %l3, 63, %l3
47920or %l3, %l0, %l0
47921srlx %l0, 1, %l0
47922
47923
47924P4414: !_MEMBAR (FP)
47925
47926P4415: !_BST [2] (maybe <- 0x4180006f) (FP)
47927wr %g0, 0xf0, %asi
47928! preparing store val #0, next val will be in f32
47929fmovs %f16, %f20
47930fadds %f16, %f17, %f16
47931! preparing store val #1, next val will be in f33
47932fmovs %f16, %f21
47933fadds %f16, %f17, %f16
47934! preparing store val #2, next val will be in f35
47935fmovd %f20, %f32
47936fmovs %f16, %f21
47937fadds %f16, %f17, %f16
47938fmovd %f20, %f34
47939membar #Sync
47940stda %f32, [%i0 + 0 ] %asi
47941
47942P4416: !_MEMBAR (FP)
47943membar #StoreLoad
47944
47945P4417: !_DWLD [0] (Int)
47946ldx [%i0 + 0], %l6
47947! move %l6(upper) -> %o1(lower)
47948srlx %l6, 32, %l3
47949or %l3, %o1, %o1
47950! move %l6(lower) -> %o2(upper)
47951sllx %l6, 32, %o2
47952
47953P4418: !_CAS [11] (maybe <- 0x20000b1) (Int) (CBR)
47954sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
47955sub %i0, %i3, %i3
47956add %i3, 12, %o5
47957lduw [%o5], %l6
47958mov %l6, %l7
47959! move %l7(lower) -> %o2(lower)
47960or %l7, %o2, %o2
47961mov %l4, %o3
47962cas [%o5], %l7, %o3
47963! move %o3(lower) -> %o3(upper)
47964sllx %o3, 32, %o3
47965add %l4, 1, %l4
47966
47967! cbranch
47968andcc %l0, 1, %g0
47969be,pn %xcc, TARGET4418
47970nop
47971RET4418:
47972
47973! lfsr step begin
47974srlx %l0, 1, %l7
47975xnor %l7, %l0, %l7
47976sllx %l7, 63, %l7
47977or %l7, %l0, %l0
47978srlx %l0, 1, %l0
47979
47980
47981P4419: !_MEMBAR (FP)
47982
47983P4420: !_BST [17] (maybe <- 0x41800072) (FP)
47984wr %g0, 0xf0, %asi
47985sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
47986sub %i0, %i2, %i2
47987! preparing store val #0, next val will be in f32
47988fmovs %f16, %f20
47989fadds %f16, %f17, %f16
47990! preparing store val #1, next val will be in f33
47991fmovs %f16, %f21
47992fadds %f16, %f17, %f16
47993! preparing store val #2, next val will be in f35
47994fmovd %f20, %f32
47995fmovs %f16, %f21
47996fadds %f16, %f17, %f16
47997fmovd %f20, %f34
47998membar #Sync
47999stda %f32, [%i2 + 0 ] %asi
48000
48001P4421: !_MEMBAR (FP)
48002membar #StoreLoad
48003
48004P4422: !_DWST [16] (maybe <- 0x20000b2) (Int)
48005sllx %l4, 32, %l7
48006add %l4, 1, %l4
48007or %l7, %l4, %l7
48008stx %l7, [%i2 + 0]
48009add %l4, 1, %l4
48010
48011P4423: !_LD [22] (Int)
48012sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
48013sub %i0, %i3, %i3
48014lduw [%i3 + 4], %l7
48015! move %l7(lower) -> %o3(lower)
48016or %l7, %o3, %o3
48017
48018P4424: !_DWST_BINIT [11] (maybe <- 0x20000b4) (Int)
48019wr %g0, 0xe2, %asi
48020sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
48021sub %i0, %i2, %i2
48022mov %l4, %o5
48023stxa %o5, [%i2 + 8] %asi
48024add %l4, 1, %l4
48025
48026P4425: !_MEMBAR (Int)
48027membar #StoreLoad
48028
48029P4426: !_REPLACEMENT [20] (Int)
48030sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
48031sub %i0, %i3, %i3
48032sethi %hi(0x20000), %l7
48033ld [%i3+12], %l3
48034st %l3, [%i3+12]
48035add %i3, %l7, %o5
48036ld [%o5+12], %l3
48037st %l3, [%o5+12]
48038add %o5, %l7, %o5
48039ld [%o5+12], %l3
48040st %l3, [%o5+12]
48041add %o5, %l7, %o5
48042ld [%o5+12], %l3
48043st %l3, [%o5+12]
48044add %o5, %l7, %o5
48045ld [%o5+12], %l3
48046st %l3, [%o5+12]
48047add %o5, %l7, %o5
48048ld [%o5+12], %l3
48049st %l3, [%o5+12]
48050add %o5, %l7, %o5
48051ld [%o5+12], %l3
48052st %l3, [%o5+12]
48053add %o5, %l7, %o5
48054ld [%o5+12], %l3
48055st %l3, [%o5+12]
48056
48057P4427: !_LDD [14] (Int)
48058sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
48059sub %i0, %i2, %i2
48060ldd [%i2 + 8], %l6
48061! move %l7(lower) -> %o4(upper)
48062sllx %l7, 32, %o4
48063
48064P4428: !_CAS [22] (maybe <- 0x20000b5) (Int)
48065sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
48066sub %i0, %i3, %i3
48067add %i3, 4, %l6
48068lduw [%l6], %o5
48069mov %o5, %l3
48070! move %l3(lower) -> %o4(lower)
48071or %l3, %o4, %o4
48072!---- flushing int results buffer----
48073mov %o0, %l5
48074mov %o1, %l5
48075mov %o2, %l5
48076mov %o3, %l5
48077mov %o4, %l5
48078mov %l4, %o0
48079cas [%l6], %l3, %o0
48080! move %o0(lower) -> %o0(upper)
48081sllx %o0, 32, %o0
48082add %l4, 1, %l4
48083
48084P4429: !_ST_BINIT [1] (maybe <- 0x20000b6) (Int)
48085wr %g0, 0xe2, %asi
48086stwa %l4, [%i0 + 4] %asi
48087add %l4, 1, %l4
48088
48089P4430: !_MEMBAR (Int)
48090membar #StoreLoad
48091
48092P4431: !_CASX [0] (maybe <- 0x20000b7) (Int)
48093ldx [%i0], %l7
48094! move %l7(upper) -> %o0(lower)
48095srlx %l7, 32, %o5
48096or %o5, %o0, %o0
48097! move %l7(lower) -> %o1(upper)
48098sllx %l7, 32, %o1
48099mov %l7, %o5
48100sllx %l4, 32, %l7
48101add %l4, 1, %l4
48102or %l4, %l7, %l7
48103casx [%i0], %o5, %l7
48104! move %l7(upper) -> %o1(lower)
48105srlx %l7, 32, %o5
48106or %o5, %o1, %o1
48107! move %l7(lower) -> %o2(upper)
48108sllx %l7, 32, %o2
48109add %l4, 1, %l4
48110
48111P4432: !_MEMBAR (FP)
48112membar #StoreLoad
48113
48114P4433: !_BLD [9] (FP)
48115wr %g0, 0xf0, %asi
48116sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
48117sub %i0, %i2, %i2
48118ldda [%i2 + 0] %asi, %f32
48119membar #Sync
48120! 3 addresses covered
48121fmovd %f32, %f18
48122fmovs %f18, %f7
48123fmovs %f19, %f8
48124fmovd %f34, %f18
48125fmovs %f19, %f9
48126
48127P4434: !_MEMBAR (FP)
48128
48129P4435: !_LD [21] (Int) (Branch target of P4671)
48130lduw [%i3 + 0], %l3
48131! move %l3(lower) -> %o2(lower)
48132or %l3, %o2, %o2
48133ba P4436
48134nop
48135
48136TARGET4671:
48137ba RET4671
48138nop
48139
48140
48141P4436: !_CASX [14] (maybe <- 0x20000b9) (Int) (Branch target of P4367)
48142sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
48143sub %i0, %i3, %i3
48144add %i3, 8, %l7
48145ldx [%l7], %o3
48146! move %o3(upper) -> %o3(upper)
48147! move %o3(lower) -> %o3(lower)
48148mov %o3, %l6
48149mov %l4, %o4
48150casx [%l7], %l6, %o4
48151! move %o4(upper) -> %o4(upper)
48152! move %o4(lower) -> %o4(lower)
48153!---- flushing int results buffer----
48154mov %o0, %l5
48155mov %o1, %l5
48156mov %o2, %l5
48157mov %o3, %l5
48158mov %o4, %l5
48159add %l4, 1, %l4
48160ba P4437
48161nop
48162
48163TARGET4367:
48164ba RET4367
48165nop
48166
48167
48168P4437: !_DWST_BINIT [1] (maybe <- 0x20000ba) (Int)
48169wr %g0, 0xe2, %asi
48170sllx %l4, 32, %l6
48171add %l4, 1, %l4
48172or %l6, %l4, %l6
48173stxa %l6, [%i0 + 0] %asi
48174add %l4, 1, %l4
48175
48176P4438: !_MEMBAR (Int) (CBR)
48177membar #StoreLoad
48178
48179! cbranch
48180andcc %l0, 1, %g0
48181be,pt %xcc, TARGET4438
48182nop
48183RET4438:
48184
48185! lfsr step begin
48186srlx %l0, 1, %l3
48187xnor %l3, %l0, %l3
48188sllx %l3, 63, %l3
48189or %l3, %l0, %l0
48190srlx %l0, 1, %l0
48191
48192
48193P4439: !_CAS [8] (maybe <- 0x20000bc) (Int)
48194sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
48195add %i0, %i2, %i2
48196add %i2, 12, %l7
48197lduw [%l7], %o0
48198mov %o0, %l6
48199! move %l6(lower) -> %o0(upper)
48200sllx %l6, 32, %o0
48201mov %l4, %l3
48202cas [%l7], %l6, %l3
48203! move %l3(lower) -> %o0(lower)
48204srl %l3, 0, %l6
48205or %l6, %o0, %o0
48206add %l4, 1, %l4
48207
48208P4440: !_CASX [7] (maybe <- 0x20000bd) (Int)
48209ldx [%i2], %o1
48210! move %o1(upper) -> %o1(upper)
48211! move %o1(lower) -> %o1(lower)
48212mov %o1, %l6
48213sllx %l4, 32, %o2
48214add %l4, 1, %l4
48215or %l4, %o2, %o2
48216casx [%i2], %l6, %o2
48217! move %o2(upper) -> %o2(upper)
48218! move %o2(lower) -> %o2(lower)
48219add %l4, 1, %l4
48220
48221P4441: !_CAS [12] (maybe <- 0x20000bf) (Int)
48222lduw [%i3], %o3
48223mov %o3, %l6
48224! move %l6(lower) -> %o3(upper)
48225sllx %l6, 32, %o3
48226mov %l4, %l3
48227cas [%i3], %l6, %l3
48228! move %l3(lower) -> %o3(lower)
48229srl %l3, 0, %l6
48230or %l6, %o3, %o3
48231add %l4, 1, %l4
48232
48233P4442: !_LD [12] (Int)
48234lduw [%i3 + 0], %o4
48235! move %o4(lower) -> %o4(upper)
48236sllx %o4, 32, %o4
48237
48238P4443: !_DWLD [23] (Int) (CBR)
48239sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
48240sub %i0, %i3, %i3
48241ldx [%i3 + 8], %l3
48242! move %l3(lower) -> %o4(lower)
48243srl %l3, 0, %o5
48244or %o5, %o4, %o4
48245!---- flushing int results buffer----
48246mov %o0, %l5
48247mov %o1, %l5
48248mov %o2, %l5
48249mov %o3, %l5
48250mov %o4, %l5
48251
48252! cbranch
48253andcc %l0, 1, %g0
48254be,pn %xcc, TARGET4443
48255nop
48256RET4443:
48257
48258! lfsr step begin
48259srlx %l0, 1, %l6
48260xnor %l6, %l0, %l6
48261sllx %l6, 63, %l6
48262or %l6, %l0, %l0
48263srlx %l0, 1, %l0
48264
48265
48266P4444: !_DWLD [17] (Int)
48267sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
48268sub %i0, %i2, %i2
48269ldx [%i2 + 8], %o0
48270! move %o0(lower) -> %o0(upper)
48271sllx %o0, 32, %o0
48272
48273P4445: !_MEMBAR (FP)
48274
48275P4446: !_BST [1] (maybe <- 0x41800075) (FP)
48276wr %g0, 0xf0, %asi
48277! preparing store val #0, next val will be in f32
48278fmovs %f16, %f20
48279fadds %f16, %f17, %f16
48280! preparing store val #1, next val will be in f33
48281fmovs %f16, %f21
48282fadds %f16, %f17, %f16
48283! preparing store val #2, next val will be in f35
48284fmovd %f20, %f32
48285fmovs %f16, %f21
48286fadds %f16, %f17, %f16
48287fmovd %f20, %f34
48288membar #Sync
48289stda %f32, [%i0 + 0 ] %asi
48290
48291P4447: !_MEMBAR (FP) (CBR)
48292membar #StoreLoad
48293
48294! cbranch
48295andcc %l0, 1, %g0
48296be,pn %xcc, TARGET4447
48297nop
48298RET4447:
48299
48300! lfsr step begin
48301srlx %l0, 1, %o5
48302xnor %o5, %l0, %o5
48303sllx %o5, 63, %o5
48304or %o5, %l0, %l0
48305srlx %l0, 1, %l0
48306
48307
48308P4448: !_LD [15] (Int)
48309lduw [%i2 + 0], %l6
48310! move %l6(lower) -> %o0(lower)
48311or %l6, %o0, %o0
48312
48313P4449: !_LD [19] (Int) (LE)
48314wr %g0, 0x88, %asi
48315sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
48316sub %i0, %i3, %i3
48317lduwa [%i3 + 4] %asi, %o1
48318! move %o1(lower) -> %o1(upper)
48319sllx %o1, 32, %o1
48320
48321P4450: !_PREFETCH [5] (Int) (CBR)
48322prefetch [%i1 + 12], 1
48323
48324! cbranch
48325andcc %l0, 1, %g0
48326be,pt %xcc, TARGET4450
48327nop
48328RET4450:
48329
48330! lfsr step begin
48331srlx %l0, 1, %l3
48332xnor %l3, %l0, %l3
48333sllx %l3, 63, %l3
48334or %l3, %l0, %l0
48335srlx %l0, 1, %l0
48336
48337
48338P4451: !_MEMBAR (FP)
48339
48340P4452: !_BST [22] (maybe <- 0x41800078) (FP)
48341wr %g0, 0xf0, %asi
48342sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
48343sub %i0, %i2, %i2
48344! preparing store val #0, next val will be in f32
48345fmovs %f16, %f20
48346fadds %f16, %f17, %f16
48347! preparing store val #1, next val will be in f33
48348fmovs %f16, %f21
48349fadds %f16, %f17, %f16
48350! preparing store val #2, next val will be in f35
48351fmovd %f20, %f32
48352fmovs %f16, %f21
48353fadds %f16, %f17, %f16
48354fmovd %f20, %f34
48355membar #Sync
48356stda %f32, [%i2 + 0 ] %asi
48357
48358P4453: !_MEMBAR (FP)
48359membar #StoreLoad
48360
48361P4454: !_REPLACEMENT [0] (Int)
48362sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
48363sub %i0, %i3, %i3
48364sethi %hi(0x20000), %l3
48365ld [%i3+0], %l7
48366st %l7, [%i3+0]
48367add %i3, %l3, %l6
48368ld [%l6+0], %l7
48369st %l7, [%l6+0]
48370add %l6, %l3, %l6
48371ld [%l6+0], %l7
48372st %l7, [%l6+0]
48373add %l6, %l3, %l6
48374ld [%l6+0], %l7
48375st %l7, [%l6+0]
48376add %l6, %l3, %l6
48377ld [%l6+0], %l7
48378st %l7, [%l6+0]
48379add %l6, %l3, %l6
48380ld [%l6+0], %l7
48381st %l7, [%l6+0]
48382add %l6, %l3, %l6
48383ld [%l6+0], %l7
48384st %l7, [%l6+0]
48385add %l6, %l3, %l6
48386ld [%l6+0], %l7
48387st %l7, [%l6+0]
48388
48389P4455: !_LD [12] (Int)
48390sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
48391sub %i0, %i2, %i2
48392lduw [%i2 + 0], %l3
48393! move %l3(lower) -> %o1(lower)
48394or %l3, %o1, %o1
48395
48396P4456: !_SWAP [23] (maybe <- 0x20000c0) (Int)
48397sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
48398sub %i0, %i3, %i3
48399mov %l4, %o2
48400swap [%i3 + 12], %o2
48401! move %o2(lower) -> %o2(upper)
48402sllx %o2, 32, %o2
48403add %l4, 1, %l4
48404
48405P4457: !_CAS [7] (maybe <- 0x20000c1) (Int)
48406sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
48407sub %i0, %i2, %i2
48408add %i2, 4, %l7
48409lduw [%l7], %l3
48410mov %l3, %l6
48411! move %l6(lower) -> %o2(lower)
48412or %l6, %o2, %o2
48413mov %l4, %o3
48414cas [%l7], %l6, %o3
48415! move %o3(lower) -> %o3(upper)
48416sllx %o3, 32, %o3
48417add %l4, 1, %l4
48418
48419P4458: !_DWST_BINIT [4] (maybe <- 0x20000c2) (Int)
48420wr %g0, 0xe2, %asi
48421sllx %l4, 32, %l6
48422add %l4, 1, %l4
48423or %l6, %l4, %l6
48424stxa %l6, [%i1 + 0] %asi
48425add %l4, 1, %l4
48426
48427P4459: !_MEMBAR (Int)
48428membar #StoreLoad
48429
48430P4460: !_PREFETCH [22] (Int)
48431prefetch [%i3 + 4], 2
48432
48433P4461: !_LDD [9] (Int)
48434sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
48435sub %i0, %i3, %i3
48436ldd [%i3 + 0], %l6
48437! move %l6(lower) -> %o3(lower)
48438or %l6, %o3, %o3
48439! move %l7(lower) -> %o4(upper)
48440sllx %l7, 32, %o4
48441
48442P4462: !_MEMBAR (FP)
48443membar #StoreLoad
48444
48445P4463: !_BLD [13] (FP)
48446wr %g0, 0xf0, %asi
48447sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
48448sub %i0, %i2, %i2
48449ldda [%i2 + 0] %asi, %f32
48450membar #Sync
48451! 3 addresses covered
48452fmovd %f32, %f10
48453fmovd %f34, %f18
48454fmovs %f19, %f12
48455
48456P4464: !_MEMBAR (FP)
48457
48458P4465: !_DWST [3] (maybe <- 0x20000c4) (Int)
48459sllx %l4, 32, %l3
48460add %l4, 1, %l4
48461or %l3, %l4, %l3
48462stx %l3, [%i1 + 0]
48463add %l4, 1, %l4
48464
48465P4466: !_LDD [10] (Int)
48466ldd [%i3 + 0], %l6
48467! move %l6(lower) -> %o4(lower)
48468or %l6, %o4, %o4
48469!---- flushing int results buffer----
48470mov %o0, %l5
48471mov %o1, %l5
48472mov %o2, %l5
48473mov %o3, %l5
48474mov %o4, %l5
48475! move %l7(lower) -> %o0(upper)
48476sllx %l7, 32, %o0
48477
48478P4467: !_LDD [23] (Int)
48479sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
48480sub %i0, %i3, %i3
48481ldd [%i3 + 8], %l6
48482! move %l7(lower) -> %o0(lower)
48483or %l7, %o0, %o0
48484
48485P4468: !_SWAP [18] (maybe <- 0x20000c6) (Int)
48486sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
48487sub %i0, %i2, %i2
48488mov %l4, %o1
48489swap [%i2 + 0], %o1
48490! move %o1(lower) -> %o1(upper)
48491sllx %o1, 32, %o1
48492add %l4, 1, %l4
48493
48494P4469: !_DWST_BINIT [19] (maybe <- 0x20000c7) (Int)
48495wr %g0, 0xe2, %asi
48496sllx %l4, 32, %o5
48497add %l4, 1, %l4
48498or %o5, %l4, %o5
48499stxa %o5, [%i2 + 0] %asi
48500add %l4, 1, %l4
48501
48502P4470: !_MEMBAR (Int)
48503membar #StoreLoad
48504
48505P4471: !_LD [21] (Int)
48506lduw [%i3 + 0], %o5
48507! move %o5(lower) -> %o1(lower)
48508or %o5, %o1, %o1
48509
48510P4472: !_LD [21] (Int)
48511lduw [%i3 + 0], %o2
48512! move %o2(lower) -> %o2(upper)
48513sllx %o2, 32, %o2
48514
48515P4473: !_REPLACEMENT [1] (Int) (Branch target of P4298)
48516sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
48517sub %i0, %i3, %i3
48518sethi %hi(0x20000), %l7
48519ld [%i3+4], %l3
48520st %l3, [%i3+4]
48521add %i3, %l7, %o5
48522ld [%o5+4], %l3
48523st %l3, [%o5+4]
48524add %o5, %l7, %o5
48525ld [%o5+4], %l3
48526st %l3, [%o5+4]
48527add %o5, %l7, %o5
48528ld [%o5+4], %l3
48529st %l3, [%o5+4]
48530add %o5, %l7, %o5
48531ld [%o5+4], %l3
48532st %l3, [%o5+4]
48533add %o5, %l7, %o5
48534ld [%o5+4], %l3
48535st %l3, [%o5+4]
48536add %o5, %l7, %o5
48537ld [%o5+4], %l3
48538st %l3, [%o5+4]
48539add %o5, %l7, %o5
48540ld [%o5+4], %l3
48541st %l3, [%o5+4]
48542ba P4474
48543nop
48544
48545TARGET4298:
48546ba RET4298
48547nop
48548
48549
48550P4474: !_MEMBAR (FP) (Branch target of P4093)
48551ba P4475
48552nop
48553
48554TARGET4093:
48555ba RET4093
48556nop
48557
48558
48559P4475: !_BST [4] (maybe <- 0x4180007b) (FP)
48560wr %g0, 0xf0, %asi
48561! preparing store val #0, next val will be in f32
48562fmovs %f16, %f20
48563fadds %f16, %f17, %f16
48564! preparing store val #1, next val will be in f33
48565fmovs %f16, %f21
48566fadds %f16, %f17, %f16
48567! preparing store val #2, next val will be in f35
48568fmovd %f20, %f32
48569fmovs %f16, %f21
48570fadds %f16, %f17, %f16
48571fmovd %f20, %f34
48572membar #Sync
48573stda %f32, [%i1 + 0 ] %asi
48574
48575P4476: !_MEMBAR (FP) (CBR)
48576membar #StoreLoad
48577
48578! cbranch
48579andcc %l0, 1, %g0
48580be,pt %xcc, TARGET4476
48581nop
48582RET4476:
48583
48584! lfsr step begin
48585srlx %l0, 1, %l3
48586xnor %l3, %l0, %l3
48587sllx %l3, 63, %l3
48588or %l3, %l0, %l0
48589srlx %l0, 1, %l0
48590
48591
48592P4477: !_PREFETCH [0] (Int) (CBR)
48593prefetch [%i0 + 0], 19
48594
48595! cbranch
48596andcc %l0, 1, %g0
48597be,pn %xcc, TARGET4477
48598nop
48599RET4477:
48600
48601! lfsr step begin
48602srlx %l0, 1, %l6
48603xnor %l6, %l0, %l6
48604sllx %l6, 63, %l6
48605or %l6, %l0, %l0
48606srlx %l0, 1, %l0
48607
48608
48609P4478: !_DWST [18] (maybe <- 0x20000c9) (Int)
48610sllx %l4, 32, %l7
48611add %l4, 1, %l4
48612or %l7, %l4, %l7
48613stx %l7, [%i2 + 0]
48614add %l4, 1, %l4
48615
48616P4479: !_SWAP [20] (maybe <- 0x20000cb) (Int) (LE)
48617wr %g0, 0x88, %asi
48618mov %l4, %o5
48619! Change single-word-level endianess (big endian <-> little endian)
48620sethi %hi(0xff00ff00), %l6
48621or %l6, %lo(0xff00ff00), %l6
48622and %o5, %l6, %l7
48623srl %l7, 8, %l7
48624sll %o5, 8, %o5
48625and %o5, %l6, %o5
48626or %o5, %l7, %o5
48627srl %o5, 16, %l7
48628sll %o5, 16, %o5
48629srl %o5, 0, %o5
48630or %o5, %l7, %o5
48631swapa [%i2 + 12] %asi, %o5
48632! move %o5(lower) -> %o2(lower)
48633srl %o5, 0, %l6
48634or %l6, %o2, %o2
48635add %l4, 1, %l4
48636
48637P4480: !_LDD [22] (Int)
48638sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
48639sub %i0, %i2, %i2
48640ldd [%i2 + 0], %l6
48641! move %l6(lower) -> %o3(upper)
48642sllx %l6, 32, %o3
48643! move %l7(lower) -> %o3(lower)
48644or %l7, %o3, %o3
48645
48646P4481: !_REPLACEMENT [1] (Int)
48647sethi %hi(0x20000), %l3
48648ld [%i3+4], %l7
48649st %l7, [%i3+4]
48650add %i3, %l3, %l6
48651ld [%l6+4], %l7
48652st %l7, [%l6+4]
48653add %l6, %l3, %l6
48654ld [%l6+4], %l7
48655st %l7, [%l6+4]
48656add %l6, %l3, %l6
48657ld [%l6+4], %l7
48658st %l7, [%l6+4]
48659add %l6, %l3, %l6
48660ld [%l6+4], %l7
48661st %l7, [%l6+4]
48662add %l6, %l3, %l6
48663ld [%l6+4], %l7
48664st %l7, [%l6+4]
48665add %l6, %l3, %l6
48666ld [%l6+4], %l7
48667st %l7, [%l6+4]
48668add %l6, %l3, %l6
48669ld [%l6+4], %l7
48670st %l7, [%l6+4]
48671
48672P4482: !_PREFETCH [19] (Int)
48673sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
48674sub %i0, %i3, %i3
48675prefetch [%i3 + 4], 22
48676
48677P4483: !_SWAP [13] (maybe <- 0x20000cc) (Int)
48678sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
48679sub %i0, %i2, %i2
48680mov %l4, %o4
48681swap [%i2 + 4], %o4
48682! move %o4(lower) -> %o4(upper)
48683sllx %o4, 32, %o4
48684add %l4, 1, %l4
48685
48686P4484: !_SWAP [21] (maybe <- 0x20000cd) (Int)
48687sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
48688sub %i0, %i3, %i3
48689mov %l4, %l3
48690swap [%i3 + 0], %l3
48691! move %l3(lower) -> %o4(lower)
48692srl %l3, 0, %l7
48693or %l7, %o4, %o4
48694!---- flushing int results buffer----
48695mov %o0, %l5
48696mov %o1, %l5
48697mov %o2, %l5
48698mov %o3, %l5
48699mov %o4, %l5
48700add %l4, 1, %l4
48701
48702P4485: !_DWST_BINIT [22] (maybe <- 0x20000ce) (Int)
48703wr %g0, 0xe2, %asi
48704sllx %l4, 32, %l6
48705add %l4, 1, %l4
48706or %l6, %l4, %l6
48707stxa %l6, [%i3 + 0] %asi
48708add %l4, 1, %l4
48709
48710P4486: !_MEMBAR (Int)
48711membar #StoreLoad
48712
48713P4487: !_SWAP [12] (maybe <- 0x20000d0) (Int)
48714mov %l4, %o0
48715swap [%i2 + 0], %o0
48716! move %o0(lower) -> %o0(upper)
48717sllx %o0, 32, %o0
48718add %l4, 1, %l4
48719
48720P4488: !_LDD [13] (Int)
48721ldd [%i2 + 0], %l6
48722! move %l6(lower) -> %o0(lower)
48723or %l6, %o0, %o0
48724! move %l7(lower) -> %o1(upper)
48725sllx %l7, 32, %o1
48726
48727P4489: !_MEMBAR (FP)
48728
48729P4490: !_BST [20] (maybe <- 0x4180007e) (FP)
48730wr %g0, 0xf0, %asi
48731sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
48732sub %i0, %i2, %i2
48733! preparing store val #0, next val will be in f32
48734fmovs %f16, %f20
48735fadds %f16, %f17, %f16
48736! preparing store val #1, next val will be in f33
48737fmovs %f16, %f21
48738fadds %f16, %f17, %f16
48739! preparing store val #2, next val will be in f35
48740fmovd %f20, %f32
48741fmovs %f16, %f21
48742fadds %f16, %f17, %f16
48743fmovd %f20, %f34
48744membar #Sync
48745stda %f32, [%i2 + 0 ] %asi
48746
48747P4491: !_MEMBAR (FP)
48748membar #StoreLoad
48749
48750P4492: !_CASX [4] (maybe <- 0x20000d1) (Int)
48751ldx [%i1], %l7
48752! move %l7(upper) -> %o1(lower)
48753srlx %l7, 32, %o5
48754or %o5, %o1, %o1
48755! move %l7(lower) -> %o2(upper)
48756sllx %l7, 32, %o2
48757mov %l7, %o5
48758sllx %l4, 32, %l7
48759add %l4, 1, %l4
48760or %l4, %l7, %l7
48761casx [%i1], %o5, %l7
48762! move %l7(upper) -> %o2(lower)
48763srlx %l7, 32, %o5
48764or %o5, %o2, %o2
48765! move %l7(lower) -> %o3(upper)
48766sllx %l7, 32, %o3
48767add %l4, 1, %l4
48768
48769P4493: !_PREFETCH [7] (Int)
48770sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
48771sub %i0, %i3, %i3
48772prefetch [%i3 + 4], 23
48773
48774P4494: !_MEMBAR (FP)
48775
48776P4495: !_BSTC [11] (maybe <- 0x41800081) (FP)
48777wr %g0, 0xe0, %asi
48778sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
48779sub %i0, %i2, %i2
48780! preparing store val #0, next val will be in f32
48781fmovs %f16, %f20
48782fadds %f16, %f17, %f16
48783! preparing store val #1, next val will be in f33
48784fmovs %f16, %f21
48785fadds %f16, %f17, %f16
48786! preparing store val #2, next val will be in f35
48787fmovd %f20, %f32
48788fmovs %f16, %f21
48789fadds %f16, %f17, %f16
48790fmovd %f20, %f34
48791membar #Sync
48792stda %f32, [%i2 + 0 ] %asi
48793
48794P4496: !_MEMBAR (FP)
48795membar #StoreLoad
48796
48797P4497: !_DWLD [18] (Int)
48798sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
48799sub %i0, %i3, %i3
48800ldx [%i3 + 0], %o5
48801! move %o5(upper) -> %o3(lower)
48802srlx %o5, 32, %l7
48803or %l7, %o3, %o3
48804! move %o5(lower) -> %o4(upper)
48805sllx %o5, 32, %o4
48806
48807P4498: !_DWST [9] (maybe <- 0x20000d3) (Int) (Branch target of P4438)
48808sllx %l4, 32, %l3
48809add %l4, 1, %l4
48810or %l3, %l4, %l3
48811stx %l3, [%i2 + 0]
48812add %l4, 1, %l4
48813ba P4499
48814nop
48815
48816TARGET4438:
48817ba RET4438
48818nop
48819
48820
48821P4499: !_MEMBAR (FP)
48822
48823P4500: !_BST [4] (maybe <- 0x41800084) (FP) (Branch target of P4684)
48824wr %g0, 0xf0, %asi
48825! preparing store val #0, next val will be in f32
48826fmovs %f16, %f20
48827fadds %f16, %f17, %f16
48828! preparing store val #1, next val will be in f33
48829fmovs %f16, %f21
48830fadds %f16, %f17, %f16
48831! preparing store val #2, next val will be in f35
48832fmovd %f20, %f32
48833fmovs %f16, %f21
48834fadds %f16, %f17, %f16
48835fmovd %f20, %f34
48836membar #Sync
48837stda %f32, [%i1 + 0 ] %asi
48838ba P4501
48839nop
48840
48841TARGET4684:
48842ba RET4684
48843nop
48844
48845
48846P4501: !_MEMBAR (FP)
48847membar #StoreLoad
48848
48849P4502: !_LD [17] (Int)
48850sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
48851sub %i0, %i2, %i2
48852lduw [%i2 + 12], %o5
48853! move %o5(lower) -> %o4(lower)
48854or %o5, %o4, %o4
48855!---- flushing int results buffer----
48856mov %o0, %l5
48857mov %o1, %l5
48858mov %o2, %l5
48859mov %o3, %l5
48860mov %o4, %l5
48861
48862P4503: !_LDD [11] (Int)
48863sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
48864sub %i0, %i3, %i3
48865ldd [%i3 + 8], %l6
48866! move %l7(lower) -> %o0(upper)
48867sllx %l7, 32, %o0
48868
48869P4504: !_SWAP [4] (maybe <- 0x20000d5) (Int)
48870mov %l4, %l7
48871swap [%i1 + 4], %l7
48872! move %l7(lower) -> %o0(lower)
48873srl %l7, 0, %l3
48874or %l3, %o0, %o0
48875add %l4, 1, %l4
48876
48877P4505: !_LD [0] (Int)
48878lduw [%i0 + 0], %o1
48879! move %o1(lower) -> %o1(upper)
48880sllx %o1, 32, %o1
48881
48882P4506: !_SWAP [14] (maybe <- 0x20000d6) (Int)
48883sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
48884sub %i0, %i2, %i2
48885mov %l4, %o5
48886swap [%i2 + 12], %o5
48887! move %o5(lower) -> %o1(lower)
48888srl %o5, 0, %l6
48889or %l6, %o1, %o1
48890add %l4, 1, %l4
48891
48892P4507: !_ST [5] (maybe <- 0x20000d7) (Int) (LE) (Branch target of P4847)
48893wr %g0, 0x88, %asi
48894! Change single-word-level endianess (big endian <-> little endian)
48895sethi %hi(0xff00ff00), %l6
48896or %l6, %lo(0xff00ff00), %l6
48897and %l4, %l6, %l7
48898srl %l7, 8, %l7
48899sll %l4, 8, %l3
48900and %l3, %l6, %l3
48901or %l3, %l7, %l3
48902srl %l3, 16, %l7
48903sll %l3, 16, %l3
48904srl %l3, 0, %l3
48905or %l3, %l7, %l3
48906stwa %l3, [%i1 + 12] %asi
48907add %l4, 1, %l4
48908ba P4508
48909nop
48910
48911TARGET4847:
48912ba RET4847
48913nop
48914
48915
48916P4508: !_DWST [14] (maybe <- 0x41800087) (FP)
48917! preparing store val #0, next val will be in f21
48918fmovs %f16, %f21
48919fadds %f16, %f17, %f16
48920std %f20, [%i2 + 8]
48921
48922P4509: !_LD [23] (Int)
48923sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
48924sub %i0, %i3, %i3
48925lduw [%i3 + 12], %o2
48926! move %o2(lower) -> %o2(upper)
48927sllx %o2, 32, %o2
48928
48929P4510: !_REPLACEMENT [0] (Int)
48930sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
48931sub %i0, %i2, %i2
48932sethi %hi(0x20000), %l3
48933ld [%i2+0], %l7
48934st %l7, [%i2+0]
48935add %i2, %l3, %l6
48936ld [%l6+0], %l7
48937st %l7, [%l6+0]
48938add %l6, %l3, %l6
48939ld [%l6+0], %l7
48940st %l7, [%l6+0]
48941add %l6, %l3, %l6
48942ld [%l6+0], %l7
48943st %l7, [%l6+0]
48944add %l6, %l3, %l6
48945ld [%l6+0], %l7
48946st %l7, [%l6+0]
48947add %l6, %l3, %l6
48948ld [%l6+0], %l7
48949st %l7, [%l6+0]
48950add %l6, %l3, %l6
48951ld [%l6+0], %l7
48952st %l7, [%l6+0]
48953add %l6, %l3, %l6
48954ld [%l6+0], %l7
48955st %l7, [%l6+0]
48956
48957P4511: !_DWST_BINIT [9] (maybe <- 0x20000d8) (Int) (LE)
48958wr %g0, 0xea, %asi
48959sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
48960sub %i0, %i3, %i3
48961sllx %l4, 32, %o5
48962add %l4, 1, %l4
48963or %o5, %l4, %l3
48964! Change double-word-level endianess (big endian <-> little endian)
48965sethi %hi(0xff00ff00), %l6
48966or %l6, %lo(0xff00ff00), %l6
48967sllx %l6, 32, %o5
48968or %l6, %o5, %l6
48969and %l3, %l6, %o5
48970srlx %o5, 8, %o5
48971sllx %l3, 8, %l3
48972and %l3, %l6, %l3
48973or %l3, %o5, %l3
48974sethi %hi(0xffff0000), %l6
48975srlx %l3, 16, %o5
48976andn %o5, %l6, %o5
48977andn %l3, %l6, %l3
48978sllx %l3, 16, %l3
48979or %l3, %o5, %l3
48980srlx %l3, 32, %o5
48981sllx %l3, 32, %l3
48982or %l3, %o5, %o5
48983stxa %o5, [%i3 + 0 ] %asi
48984add %l4, 1, %l4
48985
48986P4512: !_MEMBAR (Int) (LE)
48987membar #StoreLoad
48988
48989P4513: !_ST_BINIT [7] (maybe <- 0x20000da) (Int)
48990wr %g0, 0xe2, %asi
48991sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
48992sub %i0, %i2, %i2
48993stwa %l4, [%i2 + 4] %asi
48994add %l4, 1, %l4
48995
48996P4514: !_MEMBAR (Int)
48997membar #StoreLoad
48998
48999P4515: !_LDD [9] (Int) (LE)
49000wr %g0, 0x88, %asi
49001ldda [%i3 + 0] %asi, %l6
49002! move %l6(lower) -> %o2(lower)
49003or %l6, %o2, %o2
49004! move %l7(lower) -> %o3(upper)
49005sllx %l7, 32, %o3
49006
49007P4516: !_DWLD [19] (Int)
49008sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
49009sub %i0, %i3, %i3
49010ldx [%i3 + 0], %l6
49011! move %l6(upper) -> %o3(lower)
49012srlx %l6, 32, %l3
49013or %l3, %o3, %o3
49014! move %l6(lower) -> %o4(upper)
49015sllx %l6, 32, %o4
49016
49017P4517: !_CAS [5] (maybe <- 0x20000db) (Int) (CBR)
49018add %i1, 12, %o5
49019lduw [%o5], %l6
49020mov %l6, %l7
49021! move %l7(lower) -> %o4(lower)
49022or %l7, %o4, %o4
49023!---- flushing int results buffer----
49024mov %o0, %l5
49025mov %o1, %l5
49026mov %o2, %l5
49027mov %o3, %l5
49028mov %o4, %l5
49029mov %l4, %o0
49030cas [%o5], %l7, %o0
49031! move %o0(lower) -> %o0(upper)
49032sllx %o0, 32, %o0
49033add %l4, 1, %l4
49034
49035! cbranch
49036andcc %l0, 1, %g0
49037be,pn %xcc, TARGET4517
49038nop
49039RET4517:
49040
49041! lfsr step begin
49042srlx %l0, 1, %l7
49043xnor %l7, %l0, %l7
49044sllx %l7, 63, %l7
49045or %l7, %l0, %l0
49046srlx %l0, 1, %l0
49047
49048
49049P4518: !_DWST [1] (maybe <- 0x20000dc) (Int)
49050sllx %l4, 32, %o5
49051add %l4, 1, %l4
49052or %o5, %l4, %o5
49053stx %o5, [%i0 + 0]
49054add %l4, 1, %l4
49055
49056P4519: !_LD [18] (Int)
49057lduw [%i3 + 0], %o5
49058! move %o5(lower) -> %o0(lower)
49059or %o5, %o0, %o0
49060
49061P4520: !_DWST_BINIT [5] (maybe <- 0x20000de) (Int)
49062wr %g0, 0xe2, %asi
49063mov %l4, %l3
49064stxa %l3, [%i1 + 8] %asi
49065add %l4, 1, %l4
49066
49067P4521: !_MEMBAR (Int)
49068membar #StoreLoad
49069
49070P4522: !_DWST [6] (maybe <- 0x20000df) (Int)
49071sllx %l4, 32, %l3
49072add %l4, 1, %l4
49073or %l3, %l4, %l3
49074stx %l3, [%i2 + 0]
49075add %l4, 1, %l4
49076
49077P4523: !_MEMBAR (FP)
49078
49079P4524: !_BSTC [17] (maybe <- 0x41800088) (FP)
49080wr %g0, 0xe0, %asi
49081sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
49082sub %i0, %i2, %i2
49083! preparing store val #0, next val will be in f32
49084fmovs %f16, %f20
49085fadds %f16, %f17, %f16
49086! preparing store val #1, next val will be in f33
49087fmovs %f16, %f21
49088fadds %f16, %f17, %f16
49089! preparing store val #2, next val will be in f35
49090fmovd %f20, %f32
49091fmovs %f16, %f21
49092fadds %f16, %f17, %f16
49093fmovd %f20, %f34
49094membar #Sync
49095stda %f32, [%i2 + 0 ] %asi
49096
49097P4525: !_MEMBAR (FP)
49098membar #StoreLoad
49099
49100P4526: !_LD [9] (Int)
49101sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
49102sub %i0, %i3, %i3
49103lduw [%i3 + 0], %o1
49104! move %o1(lower) -> %o1(upper)
49105sllx %o1, 32, %o1
49106
49107P4527: !_MEMBAR (FP)
49108
49109P4528: !_BST [4] (maybe <- 0x4180008b) (FP)
49110wr %g0, 0xf0, %asi
49111! preparing store val #0, next val will be in f32
49112fmovs %f16, %f20
49113fadds %f16, %f17, %f16
49114! preparing store val #1, next val will be in f33
49115fmovs %f16, %f21
49116fadds %f16, %f17, %f16
49117! preparing store val #2, next val will be in f35
49118fmovd %f20, %f32
49119fmovs %f16, %f21
49120fadds %f16, %f17, %f16
49121fmovd %f20, %f34
49122membar #Sync
49123stda %f32, [%i1 + 0 ] %asi
49124
49125P4529: !_MEMBAR (FP)
49126membar #StoreLoad
49127
49128P4530: !_LD [0] (Int)
49129lduw [%i0 + 0], %l3
49130! move %l3(lower) -> %o1(lower)
49131or %l3, %o1, %o1
49132
49133P4531: !_MEMBAR (FP)
49134membar #StoreLoad
49135
49136P4532: !_BLD [15] (FP)
49137wr %g0, 0xf0, %asi
49138ldda [%i2 + 0] %asi, %f32
49139membar #Sync
49140! 3 addresses covered
49141fmovd %f32, %f18
49142fmovs %f18, %f13
49143fmovs %f19, %f14
49144fmovd %f34, %f18
49145fmovs %f19, %f15
49146!---- flushing fp results buffer to %f30 ----
49147fmovd %f0, %f30
49148fmovd %f2, %f30
49149fmovd %f4, %f30
49150fmovd %f6, %f30
49151fmovd %f8, %f30
49152fmovd %f10, %f30
49153fmovd %f12, %f30
49154fmovd %f14, %f30
49155!--
49156
49157P4533: !_MEMBAR (FP) (Branch target of P4217)
49158ba P4534
49159nop
49160
49161TARGET4217:
49162ba RET4217
49163nop
49164
49165
49166P4534: !_CASX [4] (maybe <- 0x20000e1) (Int)
49167ldx [%i1], %o2
49168! move %o2(upper) -> %o2(upper)
49169! move %o2(lower) -> %o2(lower)
49170mov %o2, %l6
49171sllx %l4, 32, %o3
49172add %l4, 1, %l4
49173or %l4, %o3, %o3
49174casx [%i1], %l6, %o3
49175! move %o3(upper) -> %o3(upper)
49176! move %o3(lower) -> %o3(lower)
49177add %l4, 1, %l4
49178
49179P4535: !_CAS [5] (maybe <- 0x20000e3) (Int)
49180add %i1, 12, %l7
49181lduw [%l7], %o4
49182mov %o4, %l6
49183! move %l6(lower) -> %o4(upper)
49184sllx %l6, 32, %o4
49185mov %l4, %l3
49186cas [%l7], %l6, %l3
49187! move %l3(lower) -> %o4(lower)
49188srl %l3, 0, %l6
49189or %l6, %o4, %o4
49190!---- flushing int results buffer----
49191mov %o0, %l5
49192mov %o1, %l5
49193mov %o2, %l5
49194mov %o3, %l5
49195mov %o4, %l5
49196add %l4, 1, %l4
49197
49198P4536: !_LD [3] (Int)
49199lduw [%i1 + 0], %o0
49200! move %o0(lower) -> %o0(upper)
49201sllx %o0, 32, %o0
49202
49203P4537: !_ST [7] (maybe <- 0x20000e4) (Int)
49204sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
49205sub %i0, %i2, %i2
49206stw %l4, [%i2 + 4 ]
49207add %l4, 1, %l4
49208
49209P4538: !_LDD [15] (Int) (Branch target of P4476)
49210sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
49211sub %i0, %i3, %i3
49212ldd [%i3 + 0], %l6
49213! move %l6(lower) -> %o0(lower)
49214or %l6, %o0, %o0
49215! move %l7(lower) -> %o1(upper)
49216sllx %l7, 32, %o1
49217ba P4539
49218nop
49219
49220TARGET4476:
49221ba RET4476
49222nop
49223
49224
49225P4539: !_LDD [12] (Int) (LE)
49226wr %g0, 0x88, %asi
49227sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
49228sub %i0, %i2, %i2
49229ldda [%i2 + 0] %asi, %l6
49230! move %l6(lower) -> %o1(lower)
49231or %l6, %o1, %o1
49232! move %l7(lower) -> %o2(upper)
49233sllx %l7, 32, %o2
49234
49235P4540: !_MEMBAR (FP)
49236membar #StoreLoad
49237
49238P4541: !_BLD [5] (FP)
49239wr %g0, 0xf0, %asi
49240ldda [%i1 + 0] %asi, %f0
49241membar #Sync
49242! 3 addresses covered
49243fmovs %f3, %f2
49244
49245P4542: !_MEMBAR (FP)
49246
49247P4543: !_DWLD [19] (Int)
49248sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
49249sub %i0, %i3, %i3
49250ldx [%i3 + 0], %l6
49251! move %l6(upper) -> %o2(lower)
49252srlx %l6, 32, %l3
49253or %l3, %o2, %o2
49254! move %l6(lower) -> %o3(upper)
49255sllx %l6, 32, %o3
49256
49257P4544: !_CASX [3] (maybe <- 0x20000e5) (Int)
49258ldx [%i1], %l6
49259! move %l6(upper) -> %o3(lower)
49260srlx %l6, 32, %l7
49261or %l7, %o3, %o3
49262! move %l6(lower) -> %o4(upper)
49263sllx %l6, 32, %o4
49264mov %l6, %l7
49265sllx %l4, 32, %l6
49266add %l4, 1, %l4
49267or %l4, %l6, %l6
49268casx [%i1], %l7, %l6
49269! move %l6(upper) -> %o4(lower)
49270srlx %l6, 32, %l7
49271or %l7, %o4, %o4
49272!---- flushing int results buffer----
49273mov %o0, %l5
49274mov %o1, %l5
49275mov %o2, %l5
49276mov %o3, %l5
49277mov %o4, %l5
49278! move %l6(lower) -> %o0(upper)
49279sllx %l6, 32, %o0
49280add %l4, 1, %l4
49281
49282P4545: !_CAS [9] (maybe <- 0x20000e7) (Int)
49283sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
49284sub %i0, %i2, %i2
49285lduw [%i2], %l6
49286mov %l6, %l7
49287! move %l7(lower) -> %o0(lower)
49288or %l7, %o0, %o0
49289mov %l4, %o1
49290cas [%i2], %l7, %o1
49291! move %o1(lower) -> %o1(upper)
49292sllx %o1, 32, %o1
49293add %l4, 1, %l4
49294
49295P4546: !_MEMBAR (FP)
49296
49297P4547: !_BSTC [13] (maybe <- 0x4180008e) (FP)
49298wr %g0, 0xe0, %asi
49299sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
49300sub %i0, %i3, %i3
49301! preparing store val #0, next val will be in f32
49302fmovs %f16, %f20
49303fadds %f16, %f17, %f16
49304! preparing store val #1, next val will be in f33
49305fmovs %f16, %f21
49306fadds %f16, %f17, %f16
49307! preparing store val #2, next val will be in f35
49308fmovd %f20, %f32
49309fmovs %f16, %f21
49310fadds %f16, %f17, %f16
49311fmovd %f20, %f34
49312membar #Sync
49313stda %f32, [%i3 + 0 ] %asi
49314
49315P4548: !_MEMBAR (FP)
49316membar #StoreLoad
49317
49318P4549: !_BLD [4] (FP)
49319wr %g0, 0xf0, %asi
49320ldda [%i1 + 0] %asi, %f32
49321membar #Sync
49322! 3 addresses covered
49323fmovd %f32, %f18
49324fmovs %f18, %f3
49325fmovs %f19, %f4
49326fmovd %f34, %f18
49327fmovs %f19, %f5
49328
49329P4550: !_MEMBAR (FP) (Branch target of P4946)
49330ba P4551
49331nop
49332
49333TARGET4946:
49334ba RET4946
49335nop
49336
49337
49338P4551: !_LDD [15] (Int)
49339sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
49340sub %i0, %i2, %i2
49341ldd [%i2 + 0], %l6
49342! move %l6(lower) -> %o1(lower)
49343or %l6, %o1, %o1
49344! move %l7(lower) -> %o2(upper)
49345sllx %l7, 32, %o2
49346
49347P4552: !_PREFETCH [2] (Int)
49348prefetch [%i0 + 12], 1
49349
49350P4553: !_MEMBAR (FP)
49351
49352P4554: !_BST [8] (maybe <- 0x41800091) (FP)
49353wr %g0, 0xf0, %asi
49354sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
49355sub %i0, %i3, %i3
49356! preparing store val #0, next val will be in f32
49357fmovs %f16, %f20
49358fadds %f16, %f17, %f16
49359! preparing store val #1, next val will be in f33
49360fmovs %f16, %f21
49361fadds %f16, %f17, %f16
49362! preparing store val #2, next val will be in f35
49363fmovd %f20, %f32
49364fmovs %f16, %f21
49365fadds %f16, %f17, %f16
49366fmovd %f20, %f34
49367membar #Sync
49368stda %f32, [%i3 + 0 ] %asi
49369
49370P4555: !_MEMBAR (FP)
49371membar #StoreLoad
49372
49373P4556: !_LDD [9] (Int)
49374sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
49375sub %i0, %i2, %i2
49376ldd [%i2 + 0], %l6
49377! move %l6(lower) -> %o2(lower)
49378or %l6, %o2, %o2
49379! move %l7(lower) -> %o3(upper)
49380sllx %l7, 32, %o3
49381
49382P4557: !_DWST_BINIT [14] (maybe <- 0x20000e8) (Int)
49383wr %g0, 0xe2, %asi
49384sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
49385sub %i0, %i3, %i3
49386mov %l4, %l3
49387stxa %l3, [%i3 + 8] %asi
49388add %l4, 1, %l4
49389
49390P4558: !_MEMBAR (Int)
49391membar #StoreLoad
49392
49393P4559: !_LDD [11] (Int)
49394ldd [%i2 + 8], %l6
49395! move %l7(lower) -> %o3(lower)
49396or %l7, %o3, %o3
49397
49398P4560: !_MEMBAR (FP)
49399membar #StoreLoad
49400
49401P4561: !_BLD [3] (FP)
49402wr %g0, 0xf0, %asi
49403ldda [%i1 + 0] %asi, %f32
49404membar #Sync
49405! 3 addresses covered
49406fmovd %f32, %f6
49407fmovd %f34, %f18
49408fmovs %f19, %f8
49409
49410P4562: !_MEMBAR (FP)
49411
49412P4563: !_SWAP [14] (maybe <- 0x20000e9) (Int)
49413mov %l4, %o4
49414swap [%i3 + 12], %o4
49415! move %o4(lower) -> %o4(upper)
49416sllx %o4, 32, %o4
49417add %l4, 1, %l4
49418
49419P4564: !_MEMBAR (FP)
49420
49421P4565: !_BSTC [22] (maybe <- 0x41800094) (FP)
49422wr %g0, 0xe0, %asi
49423sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
49424sub %i0, %i2, %i2
49425! preparing store val #0, next val will be in f32
49426fmovs %f16, %f20
49427fadds %f16, %f17, %f16
49428! preparing store val #1, next val will be in f33
49429fmovs %f16, %f21
49430fadds %f16, %f17, %f16
49431! preparing store val #2, next val will be in f35
49432fmovd %f20, %f32
49433fmovs %f16, %f21
49434fadds %f16, %f17, %f16
49435fmovd %f20, %f34
49436membar #Sync
49437stda %f32, [%i2 + 0 ] %asi
49438
49439P4566: !_MEMBAR (FP) (Branch target of P4736)
49440membar #StoreLoad
49441ba P4567
49442nop
49443
49444TARGET4736:
49445ba RET4736
49446nop
49447
49448
49449P4567: !_CAS [10] (maybe <- 0x20000ea) (Int)
49450sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
49451sub %i0, %i3, %i3
49452add %i3, 4, %o5
49453lduw [%o5], %l6
49454mov %l6, %l7
49455! move %l7(lower) -> %o4(lower)
49456or %l7, %o4, %o4
49457!---- flushing int results buffer----
49458mov %o0, %l5
49459mov %o1, %l5
49460mov %o2, %l5
49461mov %o3, %l5
49462mov %o4, %l5
49463mov %l4, %o0
49464cas [%o5], %l7, %o0
49465! move %o0(lower) -> %o0(upper)
49466sllx %o0, 32, %o0
49467add %l4, 1, %l4
49468
49469P4568: !_LD [7] (Int)
49470sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
49471sub %i0, %i2, %i2
49472lduw [%i2 + 4], %o5
49473! move %o5(lower) -> %o0(lower)
49474or %o5, %o0, %o0
49475
49476P4569: !_ST_BINIT [20] (maybe <- 0x20000eb) (Int)
49477wr %g0, 0xe2, %asi
49478sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
49479sub %i0, %i3, %i3
49480stwa %l4, [%i3 + 12] %asi
49481add %l4, 1, %l4
49482
49483P4570: !_MEMBAR (Int)
49484membar #StoreLoad
49485
49486P4571: !_ST_BINIT [19] (maybe <- 0x20000ec) (Int)
49487wr %g0, 0xe2, %asi
49488stwa %l4, [%i3 + 4] %asi
49489add %l4, 1, %l4
49490
49491P4572: !_MEMBAR (Int)
49492membar #StoreLoad
49493
49494P4573: !_ST_BINIT [13] (maybe <- 0x20000ed) (Int)
49495wr %g0, 0xe2, %asi
49496sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
49497sub %i0, %i2, %i2
49498stwa %l4, [%i2 + 4] %asi
49499add %l4, 1, %l4
49500
49501P4574: !_MEMBAR (Int)
49502membar #StoreLoad
49503
49504P4575: !_CAS [15] (maybe <- 0x20000ee) (Int)
49505sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
49506sub %i0, %i3, %i3
49507lduw [%i3], %o1
49508mov %o1, %l6
49509! move %l6(lower) -> %o1(upper)
49510sllx %l6, 32, %o1
49511mov %l4, %l3
49512cas [%i3], %l6, %l3
49513! move %l3(lower) -> %o1(lower)
49514srl %l3, 0, %l6
49515or %l6, %o1, %o1
49516add %l4, 1, %l4
49517
49518P4576: !_PREFETCH [7] (Int)
49519sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
49520sub %i0, %i2, %i2
49521prefetch [%i2 + 4], 1
49522
49523P4577: !_LDD [6] (Int)
49524ldd [%i2 + 0], %l6
49525! move %l6(lower) -> %o2(upper)
49526sllx %l6, 32, %o2
49527! move %l7(lower) -> %o2(lower)
49528or %l7, %o2, %o2
49529
49530P4578: !_ST_BINIT [18] (maybe <- 0x20000ef) (Int)
49531wr %g0, 0xe2, %asi
49532sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
49533sub %i0, %i3, %i3
49534stwa %l4, [%i3 + 0] %asi
49535add %l4, 1, %l4
49536
49537P4579: !_MEMBAR (Int)
49538membar #StoreLoad
49539
49540P4580: !_REPLACEMENT [19] (Int)
49541sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
49542sub %i0, %i2, %i2
49543sethi %hi(0x20000), %o5
49544ld [%i2+4], %l6
49545st %l6, [%i2+4]
49546add %i2, %o5, %l3
49547ld [%l3+4], %l6
49548st %l6, [%l3+4]
49549add %l3, %o5, %l3
49550ld [%l3+4], %l6
49551st %l6, [%l3+4]
49552add %l3, %o5, %l3
49553ld [%l3+4], %l6
49554st %l6, [%l3+4]
49555add %l3, %o5, %l3
49556ld [%l3+4], %l6
49557st %l6, [%l3+4]
49558add %l3, %o5, %l3
49559ld [%l3+4], %l6
49560st %l6, [%l3+4]
49561add %l3, %o5, %l3
49562ld [%l3+4], %l6
49563st %l6, [%l3+4]
49564add %l3, %o5, %l3
49565ld [%l3+4], %l6
49566st %l6, [%l3+4]
49567
49568P4581: !_ST_BINIT [18] (maybe <- 0x20000f0) (Int)
49569wr %g0, 0xe2, %asi
49570stwa %l4, [%i3 + 0] %asi
49571add %l4, 1, %l4
49572
49573P4582: !_MEMBAR (Int)
49574membar #StoreLoad
49575
49576P4583: !_DWST_BINIT [11] (maybe <- 0x20000f1) (Int)
49577wr %g0, 0xe2, %asi
49578sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
49579sub %i0, %i3, %i3
49580mov %l4, %l6
49581stxa %l6, [%i3 + 8] %asi
49582add %l4, 1, %l4
49583
49584P4584: !_MEMBAR (Int)
49585
49586P4585: !_BST [4] (maybe <- 0x41800097) (FP)
49587!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
49588!Logical addr: 4
49589
49590sethi %hi(0x200000), %l3
49591sub %i1, %l3, %i1
49592wr %g0, 0xf0, %asi
49593! preparing store val #0, next val will be in f32
49594fmovs %f16, %f20
49595fadds %f16, %f17, %f16
49596! preparing store val #1, next val will be in f33
49597fmovs %f16, %f21
49598fadds %f16, %f17, %f16
49599! preparing store val #2, next val will be in f35
49600fmovd %f20, %f32
49601fmovs %f16, %f21
49602fadds %f16, %f17, %f16
49603fmovd %f20, %f34
49604membar #Sync
49605stda %f32, [%i1 + 0 ] %asi
49606
49607P4586: !_MEMBAR (FP)
49608membar #StoreLoad
49609
49610P4587: !_PREFETCH [4] (Int)
49611prefetch [%i1 + 4], 3
49612
49613P4588: !_CASX [7] (maybe <- 0x20000f2) (Int) (LE)
49614sllx %l4, 32, %l6
49615add %l4, 1, %l4
49616or %l4, %l6, %l6
49617! Change double-word-level endianess (big endian <-> little endian)
49618sethi %hi(0xff00ff00), %l3
49619or %l3, %lo(0xff00ff00), %l3
49620sllx %l3, 32, %l7
49621or %l3, %l7, %l3
49622and %l6, %l3, %l7
49623srlx %l7, 8, %l7
49624sllx %l6, 8, %l6
49625and %l6, %l3, %l6
49626or %l6, %l7, %l6
49627sethi %hi(0xffff0000), %l3
49628srlx %l6, 16, %l7
49629andn %l7, %l3, %l7
49630andn %l6, %l3, %l6
49631sllx %l6, 16, %l6
49632or %l6, %l7, %l6
49633srlx %l6, 32, %l7
49634sllx %l6, 32, %l6
49635or %l6, %l7, %l7
49636wr %g0, 0x88, %asi
49637sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
49638sub %i0, %i2, %i2
49639ldxa [%i2] %asi, %o5
49640! move %o5(lower) -> %o3(upper)
49641sllx %o5, 32, %o3
49642! move %o5(upper) -> %o3(lower)
49643srlx %o5, 32, %l3
49644or %l3, %o3, %o3
49645mov %o5, %l3
49646mov %l7, %o5
49647casxa [%i2] %asi, %l3, %o5
49648! move %o5(lower) -> %o4(upper)
49649sllx %o5, 32, %o4
49650! move %o5(upper) -> %o4(lower)
49651srlx %o5, 32, %l3
49652or %l3, %o4, %o4
49653!---- flushing int results buffer----
49654mov %o0, %l5
49655mov %o1, %l5
49656mov %o2, %l5
49657mov %o3, %l5
49658mov %o4, %l5
49659add %l4, 1, %l4
49660
49661P4589: !_SWAP [10] (maybe <- 0x20000f4) (Int)
49662mov %l4, %o0
49663swap [%i3 + 4], %o0
49664! move %o0(lower) -> %o0(upper)
49665sllx %o0, 32, %o0
49666add %l4, 1, %l4
49667
49668P4590: !_REPLACEMENT [1] (Int)
49669sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
49670add %i0, %i3, %i3
49671sethi %hi(0x20000), %o5
49672ld [%i3+4], %l6
49673st %l6, [%i3+4]
49674add %i3, %o5, %l3
49675ld [%l3+4], %l6
49676st %l6, [%l3+4]
49677add %l3, %o5, %l3
49678ld [%l3+4], %l6
49679st %l6, [%l3+4]
49680add %l3, %o5, %l3
49681ld [%l3+4], %l6
49682st %l6, [%l3+4]
49683add %l3, %o5, %l3
49684ld [%l3+4], %l6
49685st %l6, [%l3+4]
49686add %l3, %o5, %l3
49687ld [%l3+4], %l6
49688st %l6, [%l3+4]
49689add %l3, %o5, %l3
49690ld [%l3+4], %l6
49691st %l6, [%l3+4]
49692add %l3, %o5, %l3
49693ld [%l3+4], %l6
49694st %l6, [%l3+4]
49695
49696P4591: !_ST [9] (maybe <- 0x20000f5) (Int)
49697sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
49698sub %i0, %i2, %i2
49699stw %l4, [%i2 + 0 ]
49700add %l4, 1, %l4
49701
49702P4592: !_MEMBAR (FP)
49703
49704P4593: !_BST [11] (maybe <- 0x4180009a) (FP)
49705wr %g0, 0xf0, %asi
49706! preparing store val #0, next val will be in f32
49707fmovs %f16, %f20
49708fadds %f16, %f17, %f16
49709! preparing store val #1, next val will be in f33
49710fmovs %f16, %f21
49711fadds %f16, %f17, %f16
49712! preparing store val #2, next val will be in f35
49713fmovd %f20, %f32
49714fmovs %f16, %f21
49715fadds %f16, %f17, %f16
49716fmovd %f20, %f34
49717membar #Sync
49718stda %f32, [%i2 + 0 ] %asi
49719
49720P4594: !_MEMBAR (FP)
49721membar #StoreLoad
49722
49723P4595: !_DWST [18] (maybe <- 0x20000f6) (Int)
49724sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
49725sub %i0, %i3, %i3
49726sllx %l4, 32, %l3
49727add %l4, 1, %l4
49728or %l3, %l4, %l3
49729stx %l3, [%i3 + 0]
49730add %l4, 1, %l4
49731
49732P4596: !_MEMBAR (FP)
49733
49734P4597: !_BST [17] (maybe <- 0x4180009d) (FP)
49735wr %g0, 0xf0, %asi
49736sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
49737sub %i0, %i2, %i2
49738! preparing store val #0, next val will be in f32
49739fmovs %f16, %f20
49740fadds %f16, %f17, %f16
49741! preparing store val #1, next val will be in f33
49742fmovs %f16, %f21
49743fadds %f16, %f17, %f16
49744! preparing store val #2, next val will be in f35
49745fmovd %f20, %f32
49746fmovs %f16, %f21
49747fadds %f16, %f17, %f16
49748fmovd %f20, %f34
49749membar #Sync
49750stda %f32, [%i2 + 0 ] %asi
49751
49752P4598: !_MEMBAR (FP)
49753membar #StoreLoad
49754
49755P4599: !_BLD [1] (FP)
49756wr %g0, 0xf0, %asi
49757ldda [%i0 + 0] %asi, %f32
49758membar #Sync
49759! 3 addresses covered
49760fmovd %f32, %f18
49761fmovs %f18, %f9
49762fmovs %f19, %f10
49763fmovd %f34, %f18
49764fmovs %f19, %f11
49765
49766P4600: !_MEMBAR (FP)
49767
49768P4601: !_PREFETCH [13] (Int) (CBR)
49769sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
49770sub %i0, %i3, %i3
49771prefetch [%i3 + 4], 16
49772
49773! cbranch
49774andcc %l0, 1, %g0
49775be,pn %xcc, TARGET4601
49776nop
49777RET4601:
49778
49779! lfsr step begin
49780srlx %l0, 1, %l7
49781xnor %l7, %l0, %l7
49782sllx %l7, 63, %l7
49783or %l7, %l0, %l0
49784srlx %l0, 1, %l0
49785
49786
49787P4602: !_ST [6] (maybe <- 0x20000f8) (Int)
49788sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
49789sub %i0, %i2, %i2
49790stw %l4, [%i2 + 0 ]
49791add %l4, 1, %l4
49792
49793P4603: !_MEMBAR (FP)
49794
49795P4604: !_BSTC [6] (maybe <- 0x418000a0) (FP) (Branch target of P4614)
49796wr %g0, 0xe0, %asi
49797! preparing store val #0, next val will be in f32
49798fmovs %f16, %f20
49799fadds %f16, %f17, %f16
49800! preparing store val #1, next val will be in f33
49801fmovs %f16, %f21
49802fadds %f16, %f17, %f16
49803! preparing store val #2, next val will be in f35
49804fmovd %f20, %f32
49805fmovs %f16, %f21
49806fadds %f16, %f17, %f16
49807fmovd %f20, %f34
49808membar #Sync
49809stda %f32, [%i2 + 0 ] %asi
49810ba P4605
49811nop
49812
49813TARGET4614:
49814ba RET4614
49815nop
49816
49817
49818P4605: !_MEMBAR (FP)
49819
49820P4606: !_BST [17] (maybe <- 0x418000a3) (FP)
49821wr %g0, 0xf0, %asi
49822sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
49823sub %i0, %i3, %i3
49824! preparing store val #0, next val will be in f32
49825fmovs %f16, %f20
49826fadds %f16, %f17, %f16
49827! preparing store val #1, next val will be in f33
49828fmovs %f16, %f21
49829fadds %f16, %f17, %f16
49830! preparing store val #2, next val will be in f35
49831fmovd %f20, %f32
49832fmovs %f16, %f21
49833fadds %f16, %f17, %f16
49834fmovd %f20, %f34
49835membar #Sync
49836stda %f32, [%i3 + 0 ] %asi
49837
49838P4607: !_MEMBAR (FP)
49839
49840P4608: !_BSTC [0] (maybe <- 0x418000a6) (FP)
49841wr %g0, 0xe0, %asi
49842! preparing store val #0, next val will be in f32
49843fmovs %f16, %f20
49844fadds %f16, %f17, %f16
49845! preparing store val #1, next val will be in f33
49846fmovs %f16, %f21
49847fadds %f16, %f17, %f16
49848! preparing store val #2, next val will be in f35
49849fmovd %f20, %f32
49850fmovs %f16, %f21
49851fadds %f16, %f17, %f16
49852fmovd %f20, %f34
49853membar #Sync
49854stda %f32, [%i0 + 0 ] %asi
49855
49856P4609: !_MEMBAR (FP) (CBR)
49857membar #StoreLoad
49858
49859! cbranch
49860andcc %l0, 1, %g0
49861be,pt %xcc, TARGET4609
49862nop
49863RET4609:
49864
49865! lfsr step begin
49866srlx %l0, 1, %o5
49867xnor %o5, %l0, %o5
49868sllx %o5, 63, %o5
49869or %o5, %l0, %l0
49870srlx %l0, 1, %l0
49871
49872
49873P4610: !_ST_BINIT [7] (maybe <- 0x20000f9) (Int)
49874wr %g0, 0xe2, %asi
49875stwa %l4, [%i2 + 4] %asi
49876add %l4, 1, %l4
49877
49878P4611: !_MEMBAR (Int)
49879membar #StoreLoad
49880
49881P4612: !_DWST [20] (maybe <- 0x20000fa) (Int)
49882sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
49883sub %i0, %i2, %i2
49884mov %l4, %o5
49885stx %o5, [%i2 + 8]
49886add %l4, 1, %l4
49887
49888P4613: !_LDD [7] (Int) (LE)
49889wr %g0, 0x88, %asi
49890sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
49891sub %i0, %i3, %i3
49892ldda [%i3 + 0] %asi, %l6
49893! move %l6(lower) -> %o0(lower)
49894or %l6, %o0, %o0
49895! move %l7(lower) -> %o1(upper)
49896sllx %l7, 32, %o1
49897
49898P4614: !_CAS [8] (maybe <- 0x20000fb) (Int) (CBR)
49899add %i3, 12, %l6
49900lduw [%l6], %o5
49901mov %o5, %l3
49902! move %l3(lower) -> %o1(lower)
49903or %l3, %o1, %o1
49904mov %l4, %o2
49905cas [%l6], %l3, %o2
49906! move %o2(lower) -> %o2(upper)
49907sllx %o2, 32, %o2
49908add %l4, 1, %l4
49909
49910! cbranch
49911andcc %l0, 1, %g0
49912be,pn %xcc, TARGET4614
49913nop
49914RET4614:
49915
49916! lfsr step begin
49917srlx %l0, 1, %l3
49918xnor %l3, %l0, %l3
49919sllx %l3, 63, %l3
49920or %l3, %l0, %l0
49921srlx %l0, 1, %l0
49922
49923
49924P4615: !_CAS [11] (maybe <- 0x20000fc) (Int)
49925sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
49926sub %i0, %i2, %i2
49927add %i2, 12, %l7
49928lduw [%l7], %l3
49929mov %l3, %l6
49930! move %l6(lower) -> %o2(lower)
49931or %l6, %o2, %o2
49932mov %l4, %o3
49933cas [%l7], %l6, %o3
49934! move %o3(lower) -> %o3(upper)
49935sllx %o3, 32, %o3
49936add %l4, 1, %l4
49937
49938P4616: !_DWLD [2] (Int)
49939ldx [%i0 + 8], %l7
49940! move %l7(lower) -> %o3(lower)
49941srl %l7, 0, %l6
49942or %l6, %o3, %o3
49943
49944P4617: !_DWST [2] (maybe <- 0x20000fd) (Int)
49945mov %l4, %o5
49946stx %o5, [%i0 + 8]
49947add %l4, 1, %l4
49948
49949P4618: !_LDD [7] (Int)
49950ldd [%i3 + 0], %l6
49951! move %l6(lower) -> %o4(upper)
49952sllx %l6, 32, %o4
49953! move %l7(lower) -> %o4(lower)
49954or %l7, %o4, %o4
49955!---- flushing int results buffer----
49956mov %o0, %l5
49957mov %o1, %l5
49958mov %o2, %l5
49959mov %o3, %l5
49960mov %o4, %l5
49961
49962P4619: !_ST_BINIT [6] (maybe <- 0x20000fe) (Int)
49963wr %g0, 0xe2, %asi
49964stwa %l4, [%i3 + 0] %asi
49965add %l4, 1, %l4
49966
49967P4620: !_MEMBAR (Int)
49968
49969P4621: !_BSTC [17] (maybe <- 0x418000a9) (FP)
49970wr %g0, 0xe0, %asi
49971sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
49972sub %i0, %i3, %i3
49973! preparing store val #0, next val will be in f32
49974fmovs %f16, %f20
49975fadds %f16, %f17, %f16
49976! preparing store val #1, next val will be in f33
49977fmovs %f16, %f21
49978fadds %f16, %f17, %f16
49979! preparing store val #2, next val will be in f35
49980fmovd %f20, %f32
49981fmovs %f16, %f21
49982fadds %f16, %f17, %f16
49983fmovd %f20, %f34
49984membar #Sync
49985stda %f32, [%i3 + 0 ] %asi
49986
49987P4622: !_MEMBAR (FP) (Branch target of P4081)
49988membar #StoreLoad
49989ba P4623
49990nop
49991
49992TARGET4081:
49993ba RET4081
49994nop
49995
49996
49997P4623: !_SWAP [11] (maybe <- 0x20000ff) (Int)
49998mov %l4, %o0
49999swap [%i2 + 12], %o0
50000! move %o0(lower) -> %o0(upper)
50001sllx %o0, 32, %o0
50002add %l4, 1, %l4
50003
50004P4624: !_DWST_BINIT [7] (maybe <- 0x2000100) (Int)
50005wr %g0, 0xe2, %asi
50006sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
50007sub %i0, %i2, %i2
50008sllx %l4, 32, %l6
50009add %l4, 1, %l4
50010or %l6, %l4, %l6
50011stxa %l6, [%i2 + 0] %asi
50012add %l4, 1, %l4
50013
50014P4625: !_MEMBAR (Int)
50015membar #StoreLoad
50016
50017P4626: !_CASX [19] (maybe <- 0x2000102) (Int)
50018sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
50019sub %i0, %i3, %i3
50020ldx [%i3], %o5
50021! move %o5(upper) -> %o0(lower)
50022srlx %o5, 32, %l3
50023or %l3, %o0, %o0
50024! move %o5(lower) -> %o1(upper)
50025sllx %o5, 32, %o1
50026mov %o5, %l3
50027sllx %l4, 32, %o5
50028add %l4, 1, %l4
50029or %l4, %o5, %o5
50030casx [%i3], %l3, %o5
50031! move %o5(upper) -> %o1(lower)
50032srlx %o5, 32, %l3
50033or %l3, %o1, %o1
50034! move %o5(lower) -> %o2(upper)
50035sllx %o5, 32, %o2
50036add %l4, 1, %l4
50037
50038P4627: !_DWST_BINIT [7] (maybe <- 0x2000104) (Int) (CBR)
50039wr %g0, 0xe2, %asi
50040sllx %l4, 32, %l3
50041add %l4, 1, %l4
50042or %l3, %l4, %l3
50043stxa %l3, [%i2 + 0] %asi
50044add %l4, 1, %l4
50045
50046! cbranch
50047andcc %l0, 1, %g0
50048be,pn %xcc, TARGET4627
50049nop
50050RET4627:
50051
50052! lfsr step begin
50053srlx %l0, 1, %o5
50054xnor %o5, %l0, %o5
50055sllx %o5, 63, %o5
50056or %o5, %l0, %l0
50057srlx %l0, 1, %l0
50058
50059
50060P4628: !_MEMBAR (Int)
50061membar #StoreLoad
50062
50063P4629: !_CAS [4] (maybe <- 0x2000106) (Int) (LE)
50064! Change single-word-level endianess (big endian <-> little endian)
50065sethi %hi(0xff00ff00), %l6
50066or %l6, %lo(0xff00ff00), %l6
50067and %l4, %l6, %l3
50068srl %l3, 8, %l3
50069sll %l4, 8, %l7
50070and %l7, %l6, %l7
50071or %l7, %l3, %l7
50072srl %l7, 16, %l3
50073sll %l7, 16, %l7
50074srl %l7, 0, %l7
50075or %l7, %l3, %l7
50076wr %g0, 0x88, %asi
50077add %i1, 4, %l6
50078lduwa [%l6] %asi, %o5
50079mov %o5, %l3
50080! move %l3(lower) -> %o2(lower)
50081or %l3, %o2, %o2
50082mov %l7, %o3
50083casa [%l6] %asi, %l3, %o3
50084! move %o3(lower) -> %o3(upper)
50085sllx %o3, 32, %o3
50086add %l4, 1, %l4
50087
50088P4630: !_LD [1] (Int)
50089lduw [%i0 + 4], %l6
50090! move %l6(lower) -> %o3(lower)
50091or %l6, %o3, %o3
50092
50093P4631: !_MEMBAR (FP)
50094membar #StoreLoad
50095
50096P4632: !_BLD [3] (FP)
50097wr %g0, 0xf0, %asi
50098ldda [%i1 + 0] %asi, %f32
50099membar #Sync
50100! 3 addresses covered
50101fmovd %f32, %f12
50102fmovd %f34, %f18
50103fmovs %f19, %f14
50104
50105P4633: !_MEMBAR (FP)
50106
50107P4634: !_DWST [13] (maybe <- 0x418000ac) (FP)
50108sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
50109sub %i0, %i2, %i2
50110! preparing store val #0, next val will be in f20
50111fmovs %f16, %f20
50112fadds %f16, %f17, %f16
50113! preparing store val #1, next val will be in f21
50114fmovs %f16, %f21
50115fadds %f16, %f17, %f16
50116std %f20, [%i2 + 0]
50117
50118P4635: !_LDD [4] (Int)
50119ldd [%i1 + 0], %l6
50120! move %l6(lower) -> %o4(upper)
50121sllx %l6, 32, %o4
50122! move %l7(lower) -> %o4(lower)
50123or %l7, %o4, %o4
50124!---- flushing int results buffer----
50125mov %o0, %l5
50126mov %o1, %l5
50127mov %o2, %l5
50128mov %o3, %l5
50129mov %o4, %l5
50130
50131P4636: !_DWLD [9] (FP)
50132sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
50133sub %i0, %i3, %i3
50134ldd [%i3 + 0], %f18
50135! 2 addresses covered
50136fmovs %f18, %f15
50137!---- flushing fp results buffer to %f30 ----
50138fmovd %f0, %f30
50139fmovd %f2, %f30
50140fmovd %f4, %f30
50141fmovd %f6, %f30
50142fmovd %f8, %f30
50143fmovd %f10, %f30
50144fmovd %f12, %f30
50145fmovd %f14, %f30
50146!--
50147fmovs %f19, %f0
50148
50149P4637: !_CAS [15] (maybe <- 0x2000107) (Int) (LE)
50150! Change single-word-level endianess (big endian <-> little endian)
50151sethi %hi(0xff00ff00), %l6
50152or %l6, %lo(0xff00ff00), %l6
50153and %l4, %l6, %l3
50154srl %l3, 8, %l3
50155sll %l4, 8, %l7
50156and %l7, %l6, %l7
50157or %l7, %l3, %l7
50158srl %l7, 16, %l3
50159sll %l7, 16, %l7
50160srl %l7, 0, %l7
50161or %l7, %l3, %l7
50162wr %g0, 0x88, %asi
50163sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
50164sub %i0, %i2, %i2
50165lduwa [%i2] %asi, %o0
50166mov %o0, %l3
50167! move %l3(lower) -> %o0(upper)
50168sllx %l3, 32, %o0
50169mov %l7, %o5
50170casa [%i2] %asi, %l3, %o5
50171! move %o5(lower) -> %o0(lower)
50172srl %o5, 0, %l3
50173or %l3, %o0, %o0
50174add %l4, 1, %l4
50175
50176P4638: !_ST_BINIT [9] (maybe <- 0x2000108) (Int)
50177wr %g0, 0xe2, %asi
50178stwa %l4, [%i3 + 0] %asi
50179add %l4, 1, %l4
50180
50181P4639: !_MEMBAR (Int)
50182membar #StoreLoad
50183
50184P4640: !_ST_BINIT [5] (maybe <- 0x2000109) (Int)
50185wr %g0, 0xe2, %asi
50186stwa %l4, [%i1 + 12] %asi
50187add %l4, 1, %l4
50188
50189P4641: !_MEMBAR (Int)
50190
50191P4642: !_BSTC [17] (maybe <- 0x418000ae) (FP)
50192wr %g0, 0xe0, %asi
50193! preparing store val #0, next val will be in f32
50194fmovs %f16, %f20
50195fadds %f16, %f17, %f16
50196! preparing store val #1, next val will be in f33
50197fmovs %f16, %f21
50198fadds %f16, %f17, %f16
50199! preparing store val #2, next val will be in f35
50200fmovd %f20, %f32
50201fmovs %f16, %f21
50202fadds %f16, %f17, %f16
50203fmovd %f20, %f34
50204membar #Sync
50205stda %f32, [%i2 + 0 ] %asi
50206
50207P4643: !_MEMBAR (FP)
50208membar #StoreLoad
50209
50210P4644: !_ST [0] (maybe <- 0x200010a) (Int)
50211stw %l4, [%i0 + 0 ]
50212add %l4, 1, %l4
50213
50214P4645: !_DWST_BINIT [1] (maybe <- 0x200010b) (Int) (LE)
50215wr %g0, 0xea, %asi
50216sllx %l4, 32, %l3
50217add %l4, 1, %l4
50218or %l3, %l4, %l6
50219! Change double-word-level endianess (big endian <-> little endian)
50220sethi %hi(0xff00ff00), %l7
50221or %l7, %lo(0xff00ff00), %l7
50222sllx %l7, 32, %l3
50223or %l7, %l3, %l7
50224and %l6, %l7, %l3
50225srlx %l3, 8, %l3
50226sllx %l6, 8, %l6
50227and %l6, %l7, %l6
50228or %l6, %l3, %l6
50229sethi %hi(0xffff0000), %l7
50230srlx %l6, 16, %l3
50231andn %l3, %l7, %l3
50232andn %l6, %l7, %l6
50233sllx %l6, 16, %l6
50234or %l6, %l3, %l6
50235srlx %l6, 32, %l3
50236sllx %l6, 32, %l6
50237or %l6, %l3, %l3
50238stxa %l3, [%i0 + 0 ] %asi
50239add %l4, 1, %l4
50240
50241P4646: !_MEMBAR (Int) (LE) (Branch target of P4762)
50242membar #StoreLoad
50243ba P4647
50244nop
50245
50246TARGET4762:
50247ba RET4762
50248nop
50249
50250
50251P4647: !_ST [3] (maybe <- 0x200010d) (Int) (LE)
50252wr %g0, 0x88, %asi
50253! Change single-word-level endianess (big endian <-> little endian)
50254sethi %hi(0xff00ff00), %l3
50255or %l3, %lo(0xff00ff00), %l3
50256and %l4, %l3, %l6
50257srl %l6, 8, %l6
50258sll %l4, 8, %o5
50259and %o5, %l3, %o5
50260or %o5, %l6, %o5
50261srl %o5, 16, %l6
50262sll %o5, 16, %o5
50263srl %o5, 0, %o5
50264or %o5, %l6, %o5
50265stwa %o5, [%i1 + 0] %asi
50266add %l4, 1, %l4
50267
50268P4648: !_SWAP [14] (maybe <- 0x200010e) (Int)
50269sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
50270sub %i0, %i3, %i3
50271mov %l4, %o1
50272swap [%i3 + 12], %o1
50273! move %o1(lower) -> %o1(upper)
50274sllx %o1, 32, %o1
50275add %l4, 1, %l4
50276
50277P4649: !_ST_BINIT [0] (maybe <- 0x200010f) (Int) (CBR)
50278wr %g0, 0xe2, %asi
50279stwa %l4, [%i0 + 0] %asi
50280add %l4, 1, %l4
50281
50282! cbranch
50283andcc %l0, 1, %g0
50284be,pn %xcc, TARGET4649
50285nop
50286RET4649:
50287
50288! lfsr step begin
50289srlx %l0, 1, %l6
50290xnor %l6, %l0, %l6
50291sllx %l6, 63, %l6
50292or %l6, %l0, %l0
50293srlx %l0, 1, %l0
50294
50295
50296P4650: !_MEMBAR (Int)
50297membar #StoreLoad
50298
50299P4651: !_PREFETCH [23] (Int)
50300sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
50301sub %i0, %i2, %i2
50302prefetch [%i2 + 12], 20
50303
50304P4652: !_CAS [23] (maybe <- 0x2000110) (Int)
50305add %i2, 12, %o5
50306lduw [%o5], %l6
50307mov %l6, %l7
50308! move %l7(lower) -> %o1(lower)
50309or %l7, %o1, %o1
50310mov %l4, %o2
50311cas [%o5], %l7, %o2
50312! move %o2(lower) -> %o2(upper)
50313sllx %o2, 32, %o2
50314add %l4, 1, %l4
50315
50316P4653: !_LDD [17] (Int)
50317sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
50318sub %i0, %i3, %i3
50319ldd [%i3 + 8], %l6
50320! move %l7(lower) -> %o2(lower)
50321or %l7, %o2, %o2
50322
50323P4654: !_DWST_BINIT [20] (maybe <- 0x2000111) (Int)
50324wr %g0, 0xe2, %asi
50325sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
50326sub %i0, %i2, %i2
50327mov %l4, %l3
50328stxa %l3, [%i2 + 8] %asi
50329add %l4, 1, %l4
50330
50331P4655: !_MEMBAR (Int)
50332membar #StoreLoad
50333
50334P4656: !_ST_BINIT [10] (maybe <- 0x2000112) (Int) (Branch target of P4311)
50335wr %g0, 0xe2, %asi
50336sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
50337sub %i0, %i3, %i3
50338stwa %l4, [%i3 + 4] %asi
50339add %l4, 1, %l4
50340ba P4657
50341nop
50342
50343TARGET4311:
50344ba RET4311
50345nop
50346
50347
50348P4657: !_MEMBAR (Int) (CBR)
50349membar #StoreLoad
50350
50351! cbranch
50352andcc %l0, 1, %g0
50353be,pn %xcc, TARGET4657
50354nop
50355RET4657:
50356
50357! lfsr step begin
50358srlx %l0, 1, %l7
50359xnor %l7, %l0, %l7
50360sllx %l7, 63, %l7
50361or %l7, %l0, %l0
50362srlx %l0, 1, %l0
50363
50364
50365P4658: !_DWLD [23] (Int)
50366sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
50367sub %i0, %i2, %i2
50368ldx [%i2 + 8], %o3
50369! move %o3(lower) -> %o3(upper)
50370sllx %o3, 32, %o3
50371
50372P4659: !_DWST_BINIT [10] (maybe <- 0x2000113) (Int)
50373wr %g0, 0xe2, %asi
50374sllx %l4, 32, %l6
50375add %l4, 1, %l4
50376or %l6, %l4, %l6
50377stxa %l6, [%i3 + 0] %asi
50378add %l4, 1, %l4
50379
50380P4660: !_MEMBAR (Int)
50381membar #StoreLoad
50382
50383P4661: !_BLD [14] (FP)
50384wr %g0, 0xf0, %asi
50385sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
50386sub %i0, %i3, %i3
50387ldda [%i3 + 0] %asi, %f32
50388membar #Sync
50389! 3 addresses covered
50390fmovd %f32, %f18
50391fmovs %f18, %f1
50392fmovs %f19, %f2
50393fmovd %f34, %f18
50394fmovs %f19, %f3
50395
50396P4662: !_MEMBAR (FP)
50397
50398P4663: !_DWST [17] (maybe <- 0x2000115) (Int)
50399sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
50400sub %i0, %i2, %i2
50401mov %l4, %l3
50402stx %l3, [%i2 + 8]
50403add %l4, 1, %l4
50404
50405P4664: !_DWST [6] (maybe <- 0x2000116) (Int)
50406sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
50407sub %i0, %i3, %i3
50408sllx %l4, 32, %o5
50409add %l4, 1, %l4
50410or %o5, %l4, %o5
50411stx %o5, [%i3 + 0]
50412add %l4, 1, %l4
50413
50414P4665: !_CASX [10] (maybe <- 0x2000118) (Int)
50415sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
50416sub %i0, %i2, %i2
50417ldx [%i2], %l6
50418! move %l6(upper) -> %o3(lower)
50419srlx %l6, 32, %l7
50420or %l7, %o3, %o3
50421! move %l6(lower) -> %o4(upper)
50422sllx %l6, 32, %o4
50423mov %l6, %l7
50424sllx %l4, 32, %l6
50425add %l4, 1, %l4
50426or %l4, %l6, %l6
50427casx [%i2], %l7, %l6
50428! move %l6(upper) -> %o4(lower)
50429srlx %l6, 32, %l7
50430or %l7, %o4, %o4
50431!---- flushing int results buffer----
50432mov %o0, %l5
50433mov %o1, %l5
50434mov %o2, %l5
50435mov %o3, %l5
50436mov %o4, %l5
50437! move %l6(lower) -> %o0(upper)
50438sllx %l6, 32, %o0
50439add %l4, 1, %l4
50440
50441P4666: !_LD [11] (Int)
50442lduw [%i2 + 12], %o5
50443! move %o5(lower) -> %o0(lower)
50444or %o5, %o0, %o0
50445
50446P4667: !_CAS [3] (maybe <- 0x200011a) (Int)
50447lduw [%i1], %o1
50448mov %o1, %l3
50449! move %l3(lower) -> %o1(upper)
50450sllx %l3, 32, %o1
50451mov %l4, %o5
50452cas [%i1], %l3, %o5
50453! move %o5(lower) -> %o1(lower)
50454srl %o5, 0, %l3
50455or %l3, %o1, %o1
50456add %l4, 1, %l4
50457
50458P4668: !_ST [20] (maybe <- 0x200011b) (Int)
50459sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
50460sub %i0, %i3, %i3
50461stw %l4, [%i3 + 12 ]
50462add %l4, 1, %l4
50463
50464P4669: !_MEMBAR (FP)
50465
50466P4670: !_BSTC [5] (maybe <- 0x418000b1) (FP)
50467wr %g0, 0xe0, %asi
50468! preparing store val #0, next val will be in f32
50469fmovs %f16, %f20
50470fadds %f16, %f17, %f16
50471! preparing store val #1, next val will be in f33
50472fmovs %f16, %f21
50473fadds %f16, %f17, %f16
50474! preparing store val #2, next val will be in f35
50475fmovd %f20, %f32
50476fmovs %f16, %f21
50477fadds %f16, %f17, %f16
50478fmovd %f20, %f34
50479membar #Sync
50480stda %f32, [%i1 + 0 ] %asi
50481
50482P4671: !_MEMBAR (FP) (CBR)
50483membar #StoreLoad
50484
50485! cbranch
50486andcc %l0, 1, %g0
50487be,pn %xcc, TARGET4671
50488nop
50489RET4671:
50490
50491! lfsr step begin
50492srlx %l0, 1, %l7
50493xnor %l7, %l0, %l7
50494sllx %l7, 63, %l7
50495or %l7, %l0, %l0
50496srlx %l0, 1, %l0
50497
50498
50499P4672: !_DWST [13] (maybe <- 0x200011c) (Int)
50500sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
50501sub %i0, %i2, %i2
50502sllx %l4, 32, %o5
50503add %l4, 1, %l4
50504or %o5, %l4, %o5
50505stx %o5, [%i2 + 0]
50506add %l4, 1, %l4
50507
50508P4673: !_LD [1] (Int)
50509lduw [%i0 + 4], %o2
50510! move %o2(lower) -> %o2(upper)
50511sllx %o2, 32, %o2
50512
50513P4674: !_LD [17] (Int)
50514sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
50515sub %i0, %i3, %i3
50516lduw [%i3 + 12], %l6
50517! move %l6(lower) -> %o2(lower)
50518or %l6, %o2, %o2
50519
50520P4675: !_DWLD [14] (Int)
50521ldx [%i2 + 8], %o3
50522! move %o3(lower) -> %o3(upper)
50523sllx %o3, 32, %o3
50524
50525P4676: !_CAS [23] (maybe <- 0x200011e) (Int)
50526sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
50527sub %i0, %i2, %i2
50528add %i2, 12, %l6
50529lduw [%l6], %o5
50530mov %o5, %l3
50531! move %l3(lower) -> %o3(lower)
50532or %l3, %o3, %o3
50533mov %l4, %o4
50534cas [%l6], %l3, %o4
50535! move %o4(lower) -> %o4(upper)
50536sllx %o4, 32, %o4
50537add %l4, 1, %l4
50538
50539P4677: !_DWST_BINIT [17] (maybe <- 0x200011f) (Int)
50540wr %g0, 0xe2, %asi
50541mov %l4, %l3
50542stxa %l3, [%i3 + 8] %asi
50543add %l4, 1, %l4
50544
50545P4678: !_MEMBAR (Int) (CBR)
50546membar #StoreLoad
50547
50548! cbranch
50549andcc %l0, 1, %g0
50550be,pt %xcc, TARGET4678
50551nop
50552RET4678:
50553
50554! lfsr step begin
50555srlx %l0, 1, %o5
50556xnor %o5, %l0, %o5
50557sllx %o5, 63, %o5
50558or %o5, %l0, %l0
50559srlx %l0, 1, %l0
50560
50561
50562P4679: !_REPLACEMENT [11] (Int)
50563sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
50564sub %i0, %i3, %i3
50565sethi %hi(0x20000), %l3
50566ld [%i3+12], %l7
50567st %l7, [%i3+12]
50568add %i3, %l3, %l6
50569ld [%l6+12], %l7
50570st %l7, [%l6+12]
50571add %l6, %l3, %l6
50572ld [%l6+12], %l7
50573st %l7, [%l6+12]
50574add %l6, %l3, %l6
50575ld [%l6+12], %l7
50576st %l7, [%l6+12]
50577add %l6, %l3, %l6
50578ld [%l6+12], %l7
50579st %l7, [%l6+12]
50580add %l6, %l3, %l6
50581ld [%l6+12], %l7
50582st %l7, [%l6+12]
50583add %l6, %l3, %l6
50584ld [%l6+12], %l7
50585st %l7, [%l6+12]
50586add %l6, %l3, %l6
50587ld [%l6+12], %l7
50588st %l7, [%l6+12]
50589
50590P4680: !_LD [16] (Int)
50591sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
50592sub %i0, %i2, %i2
50593lduw [%i2 + 4], %l3
50594! move %l3(lower) -> %o4(lower)
50595or %l3, %o4, %o4
50596!---- flushing int results buffer----
50597mov %o0, %l5
50598mov %o1, %l5
50599mov %o2, %l5
50600mov %o3, %l5
50601mov %o4, %l5
50602
50603P4681: !_DWST [2] (maybe <- 0x2000120) (Int)
50604mov %l4, %l6
50605stx %l6, [%i0 + 8]
50606add %l4, 1, %l4
50607
50608P4682: !_MEMBAR (FP)
50609
50610P4683: !_BSTC [21] (maybe <- 0x418000b4) (FP)
50611wr %g0, 0xe0, %asi
50612sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
50613sub %i0, %i3, %i3
50614! preparing store val #0, next val will be in f32
50615fmovs %f16, %f20
50616fadds %f16, %f17, %f16
50617! preparing store val #1, next val will be in f33
50618fmovs %f16, %f21
50619fadds %f16, %f17, %f16
50620! preparing store val #2, next val will be in f35
50621fmovd %f20, %f32
50622fmovs %f16, %f21
50623fadds %f16, %f17, %f16
50624fmovd %f20, %f34
50625membar #Sync
50626stda %f32, [%i3 + 0 ] %asi
50627
50628P4684: !_MEMBAR (FP) (CBR)
50629membar #StoreLoad
50630
50631! cbranch
50632andcc %l0, 1, %g0
50633be,pt %xcc, TARGET4684
50634nop
50635RET4684:
50636
50637! lfsr step begin
50638srlx %l0, 1, %o5
50639xnor %o5, %l0, %o5
50640sllx %o5, 63, %o5
50641or %o5, %l0, %l0
50642srlx %l0, 1, %l0
50643
50644
50645P4685: !_SWAP [13] (maybe <- 0x2000121) (Int)
50646sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
50647sub %i0, %i2, %i2
50648mov %l4, %o0
50649swap [%i2 + 4], %o0
50650! move %o0(lower) -> %o0(upper)
50651sllx %o0, 32, %o0
50652add %l4, 1, %l4
50653
50654P4686: !_SWAP [9] (maybe <- 0x2000122) (Int)
50655sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
50656sub %i0, %i3, %i3
50657mov %l4, %l6
50658swap [%i3 + 0], %l6
50659! move %l6(lower) -> %o0(lower)
50660srl %l6, 0, %o5
50661or %o5, %o0, %o0
50662add %l4, 1, %l4
50663
50664P4687: !_CAS [12] (maybe <- 0x2000123) (Int) (CBR)
50665lduw [%i2], %o1
50666mov %o1, %l7
50667! move %l7(lower) -> %o1(upper)
50668sllx %l7, 32, %o1
50669mov %l4, %l6
50670cas [%i2], %l7, %l6
50671! move %l6(lower) -> %o1(lower)
50672srl %l6, 0, %l7
50673or %l7, %o1, %o1
50674add %l4, 1, %l4
50675
50676! cbranch
50677andcc %l0, 1, %g0
50678be,pn %xcc, TARGET4687
50679nop
50680RET4687:
50681
50682! lfsr step begin
50683srlx %l0, 1, %l7
50684xnor %l7, %l0, %l7
50685sllx %l7, 63, %l7
50686or %l7, %l0, %l0
50687srlx %l0, 1, %l0
50688
50689
50690P4688: !_MEMBAR (FP)
50691membar #StoreLoad
50692
50693P4689: !_BLD [5] (FP)
50694wr %g0, 0xf0, %asi
50695ldda [%i1 + 0] %asi, %f32
50696membar #Sync
50697! 3 addresses covered
50698fmovd %f32, %f4
50699fmovd %f34, %f18
50700fmovs %f19, %f6
50701
50702P4690: !_MEMBAR (FP)
50703
50704P4691: !_ST_BINIT [21] (maybe <- 0x2000124) (Int)
50705wr %g0, 0xe2, %asi
50706sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
50707sub %i0, %i2, %i2
50708stwa %l4, [%i2 + 0] %asi
50709add %l4, 1, %l4
50710
50711P4692: !_MEMBAR (Int)
50712membar #StoreLoad
50713
50714P4693: !_DWST [17] (maybe <- 0x2000125) (Int)
50715sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
50716sub %i0, %i3, %i3
50717mov %l4, %l7
50718stx %l7, [%i3 + 8]
50719add %l4, 1, %l4
50720
50721P4694: !_DWST [18] (maybe <- 0x2000126) (Int)
50722sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
50723sub %i0, %i2, %i2
50724sllx %l4, 32, %l6
50725add %l4, 1, %l4
50726or %l6, %l4, %l6
50727stx %l6, [%i2 + 0]
50728add %l4, 1, %l4
50729
50730P4695: !_PREFETCH [11] (Int) (CBR)
50731sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
50732sub %i0, %i3, %i3
50733prefetch [%i3 + 12], 21
50734
50735! cbranch
50736andcc %l0, 1, %g0
50737be,pt %xcc, TARGET4695
50738nop
50739RET4695:
50740
50741! lfsr step begin
50742srlx %l0, 1, %l3
50743xnor %l3, %l0, %l3
50744sllx %l3, 63, %l3
50745or %l3, %l0, %l0
50746srlx %l0, 1, %l0
50747
50748
50749P4696: !_MEMBAR (FP)
50750
50751P4697: !_BSTC [22] (maybe <- 0x418000b7) (FP)
50752wr %g0, 0xe0, %asi
50753sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i2
50754sub %i0, %i2, %i2
50755! preparing store val #0, next val will be in f32
50756fmovs %f16, %f20
50757fadds %f16, %f17, %f16
50758! preparing store val #1, next val will be in f33
50759fmovs %f16, %f21
50760fadds %f16, %f17, %f16
50761! preparing store val #2, next val will be in f35
50762fmovd %f20, %f32
50763fmovs %f16, %f21
50764fadds %f16, %f17, %f16
50765fmovd %f20, %f34
50766membar #Sync
50767stda %f32, [%i2 + 0 ] %asi
50768
50769P4698: !_MEMBAR (FP)
50770membar #StoreLoad
50771
50772P4699: !_ST [10] (maybe <- 0x2000128) (Int) (LE)
50773wr %g0, 0x88, %asi
50774! Change single-word-level endianess (big endian <-> little endian)
50775sethi %hi(0xff00ff00), %l6
50776or %l6, %lo(0xff00ff00), %l6
50777and %l4, %l6, %l7
50778srl %l7, 8, %l7
50779sll %l4, 8, %l3
50780and %l3, %l6, %l3
50781or %l3, %l7, %l3
50782srl %l3, 16, %l7
50783sll %l3, 16, %l3
50784srl %l3, 0, %l3
50785or %l3, %l7, %l3
50786stwa %l3, [%i3 + 4] %asi
50787add %l4, 1, %l4
50788
50789P4700: !_DWST_BINIT [14] (maybe <- 0x2000129) (Int)
50790wr %g0, 0xe2, %asi
50791sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
50792sub %i0, %i3, %i3
50793mov %l4, %o5
50794stxa %o5, [%i3 + 8] %asi
50795add %l4, 1, %l4
50796
50797P4701: !_MEMBAR (Int)
50798membar #StoreLoad
50799
50800P4702: !_CASX [16] (maybe <- 0x200012a) (Int)
50801sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
50802sub %i0, %i2, %i2
50803ldx [%i2], %o2
50804! move %o2(upper) -> %o2(upper)
50805! move %o2(lower) -> %o2(lower)
50806mov %o2, %l7
50807sllx %l4, 32, %o3
50808add %l4, 1, %l4
50809or %l4, %o3, %o3
50810casx [%i2], %l7, %o3
50811! move %o3(upper) -> %o3(upper)
50812! move %o3(lower) -> %o3(lower)
50813add %l4, 1, %l4
50814
50815P4703: !_DWLD [21] (Int)
50816sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS3_O), %i3
50817sub %i0, %i3, %i3
50818ldx [%i3 + 0], %o4
50819! move %o4(upper) -> %o4(upper)
50820! move %o4(lower) -> %o4(lower)
50821!---- flushing int results buffer----
50822mov %o0, %l5
50823mov %o1, %l5
50824mov %o2, %l5
50825mov %o3, %l5
50826mov %o4, %l5
50827
50828P4704: !_DWST [19] (maybe <- 0x200012c) (Int)
50829sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
50830sub %i0, %i2, %i2
50831sllx %l4, 32, %l3
50832add %l4, 1, %l4
50833or %l3, %l4, %l3
50834stx %l3, [%i2 + 0]
50835add %l4, 1, %l4
50836
50837P4705: !_SWAP [12] (maybe <- 0x200012e) (Int)
50838sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
50839sub %i0, %i3, %i3
50840mov %l4, %o0
50841swap [%i3 + 0], %o0
50842! move %o0(lower) -> %o0(upper)
50843sllx %o0, 32, %o0
50844add %l4, 1, %l4
50845
50846P4706: !_REPLACEMENT [19] (Int)
50847sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
50848sub %i0, %i2, %i2
50849sethi %hi(0x20000), %l7
50850ld [%i2+4], %l3
50851st %l3, [%i2+4]
50852add %i2, %l7, %o5
50853ld [%o5+4], %l3
50854st %l3, [%o5+4]
50855add %o5, %l7, %o5
50856ld [%o5+4], %l3
50857st %l3, [%o5+4]
50858add %o5, %l7, %o5
50859ld [%o5+4], %l3
50860st %l3, [%o5+4]
50861add %o5, %l7, %o5
50862ld [%o5+4], %l3
50863st %l3, [%o5+4]
50864add %o5, %l7, %o5
50865ld [%o5+4], %l3
50866st %l3, [%o5+4]
50867add %o5, %l7, %o5
50868ld [%o5+4], %l3
50869st %l3, [%o5+4]
50870add %o5, %l7, %o5
50871ld [%o5+4], %l3
50872st %l3, [%o5+4]
50873
50874P4707: !_DWST [6] (maybe <- 0x200012f) (Int)
50875sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
50876sub %i0, %i3, %i3
50877sllx %l4, 32, %l6
50878add %l4, 1, %l4
50879or %l6, %l4, %l6
50880stx %l6, [%i3 + 0]
50881add %l4, 1, %l4
50882
50883P4708: !_LDD [11] (Int)
50884sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
50885sub %i0, %i2, %i2
50886ldd [%i2 + 8], %l6
50887! move %l7(lower) -> %o0(lower)
50888or %l7, %o0, %o0
50889
50890P4709: !_DWLD [16] (Int) (CBR)
50891sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
50892sub %i0, %i3, %i3
50893ldx [%i3 + 0], %o1
50894! move %o1(upper) -> %o1(upper)
50895! move %o1(lower) -> %o1(lower)
50896
50897! cbranch
50898andcc %l0, 1, %g0
50899be,pt %xcc, TARGET4709
50900nop
50901RET4709:
50902
50903! lfsr step begin
50904srlx %l0, 1, %l7
50905xnor %l7, %l0, %l7
50906sllx %l7, 63, %l7
50907or %l7, %l0, %l0
50908srlx %l0, 1, %l0
50909
50910
50911P4710: !_DWST_BINIT [9] (maybe <- 0x2000131) (Int) (LE)
50912wr %g0, 0xea, %asi
50913sllx %l4, 32, %o5
50914add %l4, 1, %l4
50915or %o5, %l4, %l3
50916! Change double-word-level endianess (big endian <-> little endian)
50917sethi %hi(0xff00ff00), %l6
50918or %l6, %lo(0xff00ff00), %l6
50919sllx %l6, 32, %o5
50920or %l6, %o5, %l6
50921and %l3, %l6, %o5
50922srlx %o5, 8, %o5
50923sllx %l3, 8, %l3
50924and %l3, %l6, %l3
50925or %l3, %o5, %l3
50926sethi %hi(0xffff0000), %l6
50927srlx %l3, 16, %o5
50928andn %o5, %l6, %o5
50929andn %l3, %l6, %l3
50930sllx %l3, 16, %l3
50931or %l3, %o5, %l3
50932srlx %l3, 32, %o5
50933sllx %l3, 32, %l3
50934or %l3, %o5, %o5
50935stxa %o5, [%i2 + 0 ] %asi
50936add %l4, 1, %l4
50937
50938P4711: !_MEMBAR (Int) (LE)
50939membar #StoreLoad
50940
50941P4712: !_LDD [18] (Int)
50942sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
50943sub %i0, %i2, %i2
50944ldd [%i2 + 0], %l6
50945! move %l6(lower) -> %o2(upper)
50946sllx %l6, 32, %o2
50947! move %l7(lower) -> %o2(lower)
50948or %l7, %o2, %o2
50949
50950P4713: !_CAS [22] (maybe <- 0x2000133) (Int)
50951sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
50952add %i0, %i3, %i3
50953add %i3, 4, %l7
50954lduw [%l7], %o3
50955mov %o3, %l6
50956! move %l6(lower) -> %o3(upper)
50957sllx %l6, 32, %o3
50958mov %l4, %l3
50959cas [%l7], %l6, %l3
50960! move %l3(lower) -> %o3(lower)
50961srl %l3, 0, %l6
50962or %l6, %o3, %o3
50963add %l4, 1, %l4
50964
50965P4714: !_REPLACEMENT [0] (Int)
50966sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
50967sub %i0, %i2, %i2
50968sethi %hi(0x20000), %l6
50969ld [%i2+0], %o5
50970st %o5, [%i2+0]
50971add %i2, %l6, %l7
50972ld [%l7+0], %o5
50973st %o5, [%l7+0]
50974add %l7, %l6, %l7
50975ld [%l7+0], %o5
50976st %o5, [%l7+0]
50977add %l7, %l6, %l7
50978ld [%l7+0], %o5
50979st %o5, [%l7+0]
50980add %l7, %l6, %l7
50981ld [%l7+0], %o5
50982st %o5, [%l7+0]
50983add %l7, %l6, %l7
50984ld [%l7+0], %o5
50985st %o5, [%l7+0]
50986add %l7, %l6, %l7
50987ld [%l7+0], %o5
50988st %o5, [%l7+0]
50989add %l7, %l6, %l7
50990ld [%l7+0], %o5
50991st %o5, [%l7+0]
50992
50993P4715: !_MEMBAR (FP)
50994
50995P4716: !_BST [18] (maybe <- 0x418000ba) (FP) (Branch target of P4418)
50996wr %g0, 0xf0, %asi
50997sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
50998sub %i0, %i3, %i3
50999! preparing store val #0, next val will be in f32
51000fmovs %f16, %f20
51001fadds %f16, %f17, %f16
51002! preparing store val #1, next val will be in f33
51003fmovs %f16, %f21
51004fadds %f16, %f17, %f16
51005! preparing store val #2, next val will be in f35
51006fmovd %f20, %f32
51007fmovs %f16, %f21
51008fadds %f16, %f17, %f16
51009fmovd %f20, %f34
51010membar #Sync
51011stda %f32, [%i3 + 0 ] %asi
51012ba P4717
51013nop
51014
51015TARGET4418:
51016ba RET4418
51017nop
51018
51019
51020P4717: !_MEMBAR (FP)
51021membar #StoreLoad
51022
51023P4718: !_PREFETCH [18] (Int)
51024prefetch [%i3 + 0], 31
51025
51026P4719: !_PREFETCH [13] (Int)
51027sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
51028sub %i0, %i2, %i2
51029prefetch [%i2 + 4], 30
51030
51031P4720: !_DWST_BINIT [8] (maybe <- 0x2000134) (Int)
51032wr %g0, 0xe2, %asi
51033sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
51034sub %i0, %i3, %i3
51035mov %l4, %o5
51036stxa %o5, [%i3 + 8] %asi
51037add %l4, 1, %l4
51038
51039P4721: !_MEMBAR (Int)
51040membar #StoreLoad
51041
51042P4722: !_DWLD [6] (Int)
51043ldx [%i3 + 0], %o4
51044! move %o4(upper) -> %o4(upper)
51045! move %o4(lower) -> %o4(lower)
51046!---- flushing int results buffer----
51047mov %o0, %l5
51048mov %o1, %l5
51049mov %o2, %l5
51050mov %o3, %l5
51051mov %o4, %l5
51052
51053P4723: !_CASX [14] (maybe <- 0x2000135) (Int)
51054add %i2, 8, %l6
51055ldx [%l6], %o0
51056! move %o0(upper) -> %o0(upper)
51057! move %o0(lower) -> %o0(lower)
51058mov %o0, %l3
51059mov %l4, %o1
51060casx [%l6], %l3, %o1
51061! move %o1(upper) -> %o1(upper)
51062! move %o1(lower) -> %o1(lower)
51063add %l4, 1, %l4
51064
51065P4724: !_ST [23] (maybe <- 0x2000136) (Int)
51066sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
51067add %i0, %i2, %i2
51068stw %l4, [%i2 + 12 ]
51069add %l4, 1, %l4
51070
51071P4725: !_LD [19] (Int)
51072sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
51073sub %i0, %i3, %i3
51074lduw [%i3 + 4], %o2
51075! move %o2(lower) -> %o2(upper)
51076sllx %o2, 32, %o2
51077
51078P4726: !_MEMBAR (FP) (Branch target of P4894)
51079membar #StoreLoad
51080ba P4727
51081nop
51082
51083TARGET4894:
51084ba RET4894
51085nop
51086
51087
51088P4727: !_BLD [4] (FP)
51089wr %g0, 0xf0, %asi
51090ldda [%i1 + 0] %asi, %f32
51091membar #Sync
51092! 3 addresses covered
51093fmovd %f32, %f18
51094fmovs %f18, %f7
51095fmovs %f19, %f8
51096fmovd %f34, %f18
51097fmovs %f19, %f9
51098
51099P4728: !_MEMBAR (FP)
51100
51101P4729: !_CAS [5] (maybe <- 0x2000137) (Int)
51102add %i1, 12, %l7
51103lduw [%l7], %l3
51104mov %l3, %l6
51105! move %l6(lower) -> %o2(lower)
51106or %l6, %o2, %o2
51107mov %l4, %o3
51108cas [%l7], %l6, %o3
51109! move %o3(lower) -> %o3(upper)
51110sllx %o3, 32, %o3
51111add %l4, 1, %l4
51112
51113P4730: !_CAS [5] (maybe <- 0x2000138) (Int) (Branch target of P4995)
51114add %i1, 12, %l7
51115lduw [%l7], %l3
51116mov %l3, %l6
51117! move %l6(lower) -> %o3(lower)
51118or %l6, %o3, %o3
51119mov %l4, %o4
51120cas [%l7], %l6, %o4
51121! move %o4(lower) -> %o4(upper)
51122sllx %o4, 32, %o4
51123add %l4, 1, %l4
51124ba P4731
51125nop
51126
51127TARGET4995:
51128ba RET4995
51129nop
51130
51131
51132P4731: !_MEMBAR (FP)
51133
51134P4732: !_BST [3] (maybe <- 0x418000bd) (FP)
51135wr %g0, 0xf0, %asi
51136! preparing store val #0, next val will be in f32
51137fmovs %f16, %f20
51138fadds %f16, %f17, %f16
51139! preparing store val #1, next val will be in f33
51140fmovs %f16, %f21
51141fadds %f16, %f17, %f16
51142! preparing store val #2, next val will be in f35
51143fmovd %f20, %f32
51144fmovs %f16, %f21
51145fadds %f16, %f17, %f16
51146fmovd %f20, %f34
51147membar #Sync
51148stda %f32, [%i1 + 0 ] %asi
51149
51150P4733: !_MEMBAR (FP)
51151membar #StoreLoad
51152
51153P4734: !_LD [15] (Int)
51154sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
51155sub %i0, %i2, %i2
51156lduw [%i2 + 0], %l6
51157! move %l6(lower) -> %o4(lower)
51158or %l6, %o4, %o4
51159!---- flushing int results buffer----
51160mov %o0, %l5
51161mov %o1, %l5
51162mov %o2, %l5
51163mov %o3, %l5
51164mov %o4, %l5
51165
51166P4735: !_MEMBAR (FP)
51167
51168P4736: !_BST [2] (maybe <- 0x418000c0) (FP) (CBR)
51169wr %g0, 0xf0, %asi
51170! preparing store val #0, next val will be in f32
51171fmovs %f16, %f20
51172fadds %f16, %f17, %f16
51173! preparing store val #1, next val will be in f33
51174fmovs %f16, %f21
51175fadds %f16, %f17, %f16
51176! preparing store val #2, next val will be in f35
51177fmovd %f20, %f32
51178fmovs %f16, %f21
51179fadds %f16, %f17, %f16
51180fmovd %f20, %f34
51181membar #Sync
51182stda %f32, [%i0 + 0 ] %asi
51183
51184! cbranch
51185andcc %l0, 1, %g0
51186be,pn %xcc, TARGET4736
51187nop
51188RET4736:
51189
51190! lfsr step begin
51191srlx %l0, 1, %l6
51192xnor %l6, %l0, %l6
51193sllx %l6, 63, %l6
51194or %l6, %l0, %l0
51195srlx %l0, 1, %l0
51196
51197
51198P4737: !_MEMBAR (FP)
51199membar #StoreLoad
51200
51201P4738: !_SWAP [6] (maybe <- 0x2000139) (Int) (Branch target of P4934)
51202sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
51203sub %i0, %i3, %i3
51204mov %l4, %o0
51205swap [%i3 + 0], %o0
51206! move %o0(lower) -> %o0(upper)
51207sllx %o0, 32, %o0
51208add %l4, 1, %l4
51209ba P4739
51210nop
51211
51212TARGET4934:
51213ba RET4934
51214nop
51215
51216
51217P4739: !_MEMBAR (FP)
51218membar #StoreLoad
51219
51220P4740: !_BLD [21] (FP)
51221wr %g0, 0xf0, %asi
51222sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
51223add %i0, %i2, %i2
51224ldda [%i2 + 0] %asi, %f32
51225membar #Sync
51226! 3 addresses covered
51227fmovd %f32, %f10
51228fmovd %f34, %f18
51229fmovs %f19, %f12
51230
51231P4741: !_MEMBAR (FP)
51232
51233P4742: !_DWST [11] (maybe <- 0x200013a) (Int)
51234sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
51235sub %i0, %i3, %i3
51236mov %l4, %l6
51237stx %l6, [%i3 + 8]
51238add %l4, 1, %l4
51239
51240P4743: !_CAS [1] (maybe <- 0x200013b) (Int)
51241add %i0, 4, %l6
51242lduw [%l6], %o5
51243mov %o5, %l3
51244! move %l3(lower) -> %o0(lower)
51245or %l3, %o0, %o0
51246mov %l4, %o1
51247cas [%l6], %l3, %o1
51248! move %o1(lower) -> %o1(upper)
51249sllx %o1, 32, %o1
51250add %l4, 1, %l4
51251
51252P4744: !_MEMBAR (FP)
51253
51254P4745: !_BSTC [4] (maybe <- 0x418000c3) (FP)
51255wr %g0, 0xe0, %asi
51256! preparing store val #0, next val will be in f32
51257fmovs %f16, %f20
51258fadds %f16, %f17, %f16
51259! preparing store val #1, next val will be in f33
51260fmovs %f16, %f21
51261fadds %f16, %f17, %f16
51262! preparing store val #2, next val will be in f35
51263fmovd %f20, %f32
51264fmovs %f16, %f21
51265fadds %f16, %f17, %f16
51266fmovd %f20, %f34
51267membar #Sync
51268stda %f32, [%i1 + 0 ] %asi
51269
51270P4746: !_MEMBAR (FP)
51271membar #StoreLoad
51272
51273P4747: !_REPLACEMENT [0] (Int) (CBR)
51274sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
51275sub %i0, %i2, %i2
51276sethi %hi(0x20000), %o5
51277ld [%i2+0], %l6
51278st %l6, [%i2+0]
51279add %i2, %o5, %l3
51280ld [%l3+0], %l6
51281st %l6, [%l3+0]
51282add %l3, %o5, %l3
51283ld [%l3+0], %l6
51284st %l6, [%l3+0]
51285add %l3, %o5, %l3
51286ld [%l3+0], %l6
51287st %l6, [%l3+0]
51288add %l3, %o5, %l3
51289ld [%l3+0], %l6
51290st %l6, [%l3+0]
51291add %l3, %o5, %l3
51292ld [%l3+0], %l6
51293st %l6, [%l3+0]
51294add %l3, %o5, %l3
51295ld [%l3+0], %l6
51296st %l6, [%l3+0]
51297add %l3, %o5, %l3
51298ld [%l3+0], %l6
51299st %l6, [%l3+0]
51300
51301! cbranch
51302andcc %l0, 1, %g0
51303be,pn %xcc, TARGET4747
51304nop
51305RET4747:
51306
51307! lfsr step begin
51308srlx %l0, 1, %l7
51309xnor %l7, %l0, %l7
51310sllx %l7, 63, %l7
51311or %l7, %l0, %l0
51312srlx %l0, 1, %l0
51313
51314
51315P4748: !_SWAP [8] (maybe <- 0x200013c) (Int)
51316sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
51317sub %i0, %i3, %i3
51318mov %l4, %l6
51319swap [%i3 + 12], %l6
51320! move %l6(lower) -> %o1(lower)
51321srl %l6, 0, %o5
51322or %o5, %o1, %o1
51323add %l4, 1, %l4
51324
51325P4749: !_LD [12] (Int)
51326sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
51327sub %i0, %i2, %i2
51328lduw [%i2 + 0], %o2
51329! move %o2(lower) -> %o2(upper)
51330sllx %o2, 32, %o2
51331
51332P4750: !_ST [16] (maybe <- 0x200013d) (Int)
51333sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
51334sub %i0, %i3, %i3
51335stw %l4, [%i3 + 4 ]
51336add %l4, 1, %l4
51337
51338P4751: !_DWST [19] (maybe <- 0x418000c6) (FP) (Branch target of P4065)
51339sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
51340sub %i0, %i2, %i2
51341! preparing store val #0, next val will be in f20
51342fmovs %f16, %f20
51343fadds %f16, %f17, %f16
51344! preparing store val #1, next val will be in f21
51345fmovs %f16, %f21
51346fadds %f16, %f17, %f16
51347std %f20, [%i2 + 0]
51348ba P4752
51349nop
51350
51351TARGET4065:
51352ba RET4065
51353nop
51354
51355
51356P4752: !_DWLD [20] (Int)
51357ldx [%i2 + 8], %o5
51358! move %o5(lower) -> %o2(lower)
51359srl %o5, 0, %l7
51360or %l7, %o2, %o2
51361
51362P4753: !_DWLD [18] (Int)
51363ldx [%i2 + 0], %o3
51364! move %o3(upper) -> %o3(upper)
51365! move %o3(lower) -> %o3(lower)
51366
51367P4754: !_CAS [19] (maybe <- 0x200013e) (Int)
51368add %i2, 4, %o5
51369lduw [%o5], %o4
51370mov %o4, %l7
51371! move %l7(lower) -> %o4(upper)
51372sllx %l7, 32, %o4
51373mov %l4, %l6
51374cas [%o5], %l7, %l6
51375! move %l6(lower) -> %o4(lower)
51376srl %l6, 0, %l7
51377or %l7, %o4, %o4
51378!---- flushing int results buffer----
51379mov %o0, %l5
51380mov %o1, %l5
51381mov %o2, %l5
51382mov %o3, %l5
51383mov %o4, %l5
51384add %l4, 1, %l4
51385
51386P4755: !_DWST_BINIT [13] (maybe <- 0x200013f) (Int)
51387wr %g0, 0xe2, %asi
51388sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
51389sub %i0, %i3, %i3
51390sllx %l4, 32, %l7
51391add %l4, 1, %l4
51392or %l7, %l4, %l7
51393stxa %l7, [%i3 + 0] %asi
51394add %l4, 1, %l4
51395
51396P4756: !_MEMBAR (Int)
51397membar #StoreLoad
51398
51399P4757: !_LD [18] (Int)
51400lduw [%i2 + 0], %o0
51401! move %o0(lower) -> %o0(upper)
51402sllx %o0, 32, %o0
51403
51404P4758: !_LDD [2] (Int)
51405ldd [%i0 + 8], %l6
51406! move %l7(lower) -> %o0(lower)
51407or %l7, %o0, %o0
51408
51409P4759: !_CAS [5] (maybe <- 0x2000141) (Int) (LE)
51410! Change single-word-level endianess (big endian <-> little endian)
51411sethi %hi(0xff00ff00), %l6
51412or %l6, %lo(0xff00ff00), %l6
51413and %l4, %l6, %l3
51414srl %l3, 8, %l3
51415sll %l4, 8, %l7
51416and %l7, %l6, %l7
51417or %l7, %l3, %l7
51418srl %l7, 16, %l3
51419sll %l7, 16, %l7
51420srl %l7, 0, %l7
51421or %l7, %l3, %l7
51422wr %g0, 0x88, %asi
51423add %i1, 12, %l6
51424lduwa [%l6] %asi, %o1
51425mov %o1, %l3
51426! move %l3(lower) -> %o1(upper)
51427sllx %l3, 32, %o1
51428mov %l7, %o5
51429casa [%l6] %asi, %l3, %o5
51430! move %o5(lower) -> %o1(lower)
51431srl %o5, 0, %l3
51432or %l3, %o1, %o1
51433add %l4, 1, %l4
51434
51435P4760: !_LDD [14] (Int) (LE)
51436wr %g0, 0x88, %asi
51437ldda [%i3 + 8] %asi, %l6
51438! move %l7(lower) -> %o2(upper)
51439sllx %l7, 32, %o2
51440
51441P4761: !_CAS [0] (maybe <- 0x2000142) (Int)
51442lduw [%i0], %o5
51443mov %o5, %l3
51444! move %l3(lower) -> %o2(lower)
51445or %l3, %o2, %o2
51446mov %l4, %o3
51447cas [%i0], %l3, %o3
51448! move %o3(lower) -> %o3(upper)
51449sllx %o3, 32, %o3
51450add %l4, 1, %l4
51451
51452P4762: !_DWLD [8] (Int) (LE) (CBR)
51453wr %g0, 0x88, %asi
51454sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
51455sub %i0, %i2, %i2
51456ldxa [%i2 + 8] %asi, %l6
51457! move %l6(upper) -> %o3(lower)
51458srlx %l6, 32, %l3
51459or %l3, %o3, %o3
51460
51461! cbranch
51462andcc %l0, 1, %g0
51463be,pt %xcc, TARGET4762
51464nop
51465RET4762:
51466
51467! lfsr step begin
51468srlx %l0, 1, %l7
51469xnor %l7, %l0, %l7
51470sllx %l7, 63, %l7
51471or %l7, %l0, %l0
51472srlx %l0, 1, %l0
51473
51474
51475P4763: !_LDD [4] (Int)
51476ldd [%i1 + 0], %l6
51477! move %l6(lower) -> %o4(upper)
51478sllx %l6, 32, %o4
51479! move %l7(lower) -> %o4(lower)
51480or %l7, %o4, %o4
51481!---- flushing int results buffer----
51482mov %o0, %l5
51483mov %o1, %l5
51484mov %o2, %l5
51485mov %o3, %l5
51486mov %o4, %l5
51487
51488P4764: !_CASX [6] (maybe <- 0x2000143) (Int)
51489ldx [%i2], %o0
51490! move %o0(upper) -> %o0(upper)
51491! move %o0(lower) -> %o0(lower)
51492mov %o0, %l3
51493sllx %l4, 32, %o1
51494add %l4, 1, %l4
51495or %l4, %o1, %o1
51496casx [%i2], %l3, %o1
51497! move %o1(upper) -> %o1(upper)
51498! move %o1(lower) -> %o1(lower)
51499add %l4, 1, %l4
51500
51501P4765: !_LDD [8] (Int)
51502ldd [%i2 + 8], %l6
51503! move %l7(lower) -> %o2(upper)
51504sllx %l7, 32, %o2
51505
51506P4766: !_DWST [13] (maybe <- 0x418000c8) (FP) (CBR)
51507! preparing store val #0, next val will be in f20
51508fmovs %f16, %f20
51509fadds %f16, %f17, %f16
51510! preparing store val #1, next val will be in f21
51511fmovs %f16, %f21
51512fadds %f16, %f17, %f16
51513std %f20, [%i3 + 0]
51514
51515! cbranch
51516andcc %l0, 1, %g0
51517be,pn %xcc, TARGET4766
51518nop
51519RET4766:
51520
51521! lfsr step begin
51522srlx %l0, 1, %o5
51523xnor %o5, %l0, %o5
51524sllx %o5, 63, %o5
51525or %o5, %l0, %l0
51526srlx %l0, 1, %l0
51527
51528
51529P4767: !_ST_BINIT [1] (maybe <- 0x2000145) (Int)
51530wr %g0, 0xe2, %asi
51531stwa %l4, [%i0 + 4] %asi
51532add %l4, 1, %l4
51533
51534P4768: !_MEMBAR (Int)
51535membar #StoreLoad
51536
51537P4769: !_SWAP [3] (maybe <- 0x2000146) (Int)
51538mov %l4, %l6
51539swap [%i1 + 0], %l6
51540! move %l6(lower) -> %o2(lower)
51541srl %l6, 0, %o5
51542or %o5, %o2, %o2
51543add %l4, 1, %l4
51544
51545P4770: !_ST [21] (maybe <- 0x2000147) (Int)
51546sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
51547add %i0, %i3, %i3
51548stw %l4, [%i3 + 0 ]
51549add %l4, 1, %l4
51550
51551P4771: !_DWST_BINIT [13] (maybe <- 0x2000148) (Int)
51552wr %g0, 0xe2, %asi
51553sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
51554sub %i0, %i2, %i2
51555sllx %l4, 32, %l6
51556add %l4, 1, %l4
51557or %l6, %l4, %l6
51558stxa %l6, [%i2 + 0] %asi
51559add %l4, 1, %l4
51560
51561P4772: !_MEMBAR (Int)
51562membar #StoreLoad
51563
51564P4773: !_ST_BINIT [2] (maybe <- 0x200014a) (Int)
51565wr %g0, 0xe2, %asi
51566stwa %l4, [%i0 + 12] %asi
51567add %l4, 1, %l4
51568
51569P4774: !_MEMBAR (Int)
51570membar #StoreLoad
51571
51572P4775: !_DWST_BINIT [18] (maybe <- 0x200014b) (Int) (LE)
51573wr %g0, 0xea, %asi
51574sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
51575sub %i0, %i3, %i3
51576sllx %l4, 32, %o5
51577add %l4, 1, %l4
51578or %o5, %l4, %l3
51579! Change double-word-level endianess (big endian <-> little endian)
51580sethi %hi(0xff00ff00), %l6
51581or %l6, %lo(0xff00ff00), %l6
51582sllx %l6, 32, %o5
51583or %l6, %o5, %l6
51584and %l3, %l6, %o5
51585srlx %o5, 8, %o5
51586sllx %l3, 8, %l3
51587and %l3, %l6, %l3
51588or %l3, %o5, %l3
51589sethi %hi(0xffff0000), %l6
51590srlx %l3, 16, %o5
51591andn %o5, %l6, %o5
51592andn %l3, %l6, %l3
51593sllx %l3, 16, %l3
51594or %l3, %o5, %l3
51595srlx %l3, 32, %o5
51596sllx %l3, 32, %l3
51597or %l3, %o5, %o5
51598stxa %o5, [%i3 + 0 ] %asi
51599add %l4, 1, %l4
51600
51601P4776: !_MEMBAR (Int) (LE)
51602membar #StoreLoad
51603
51604P4777: !_DWST_BINIT [4] (maybe <- 0x200014d) (Int)
51605!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
51606!Logical addr: 4
51607
51608sethi %hi(0x200000), %l7
51609sub %i1, %l7, %i1
51610wr %g0, 0xe2, %asi
51611sllx %l4, 32, %o5
51612add %l4, 1, %l4
51613or %o5, %l4, %o5
51614stxa %o5, [%i1 + 0] %asi
51615add %l4, 1, %l4
51616
51617P4778: !_MEMBAR (Int) (Branch target of P4687)
51618membar #StoreLoad
51619ba P4779
51620nop
51621
51622TARGET4687:
51623ba RET4687
51624nop
51625
51626
51627P4779: !_SWAP [1] (maybe <- 0x200014f) (Int)
51628mov %l4, %o3
51629swap [%i0 + 4], %o3
51630! move %o3(lower) -> %o3(upper)
51631sllx %o3, 32, %o3
51632add %l4, 1, %l4
51633
51634P4780: !_CAS [18] (maybe <- 0x2000150) (Int)
51635lduw [%i3], %l3
51636mov %l3, %l6
51637! move %l6(lower) -> %o3(lower)
51638or %l6, %o3, %o3
51639mov %l4, %o4
51640cas [%i3], %l6, %o4
51641! move %o4(lower) -> %o4(upper)
51642sllx %o4, 32, %o4
51643add %l4, 1, %l4
51644
51645P4781: !_LDD [17] (Int)
51646sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
51647sub %i0, %i2, %i2
51648ldd [%i2 + 8], %l6
51649! move %l7(lower) -> %o4(lower)
51650or %l7, %o4, %o4
51651!---- flushing int results buffer----
51652mov %o0, %l5
51653mov %o1, %l5
51654mov %o2, %l5
51655mov %o3, %l5
51656mov %o4, %l5
51657
51658P4782: !_DWST [3] (maybe <- 0x2000151) (Int)
51659sllx %l4, 32, %l3
51660add %l4, 1, %l4
51661or %l3, %l4, %l3
51662stx %l3, [%i1 + 0]
51663add %l4, 1, %l4
51664
51665P4783: !_MEMBAR (FP)
51666
51667P4784: !_BST [20] (maybe <- 0x418000ca) (FP)
51668wr %g0, 0xf0, %asi
51669! preparing store val #0, next val will be in f32
51670fmovs %f16, %f20
51671fadds %f16, %f17, %f16
51672! preparing store val #1, next val will be in f33
51673fmovs %f16, %f21
51674fadds %f16, %f17, %f16
51675! preparing store val #2, next val will be in f35
51676fmovd %f20, %f32
51677fmovs %f16, %f21
51678fadds %f16, %f17, %f16
51679fmovd %f20, %f34
51680membar #Sync
51681stda %f32, [%i3 + 0 ] %asi
51682
51683P4785: !_MEMBAR (FP)
51684
51685P4786: !_BSTC [0] (maybe <- 0x418000cd) (FP)
51686wr %g0, 0xe0, %asi
51687! preparing store val #0, next val will be in f32
51688fmovs %f16, %f20
51689fadds %f16, %f17, %f16
51690! preparing store val #1, next val will be in f33
51691fmovs %f16, %f21
51692fadds %f16, %f17, %f16
51693! preparing store val #2, next val will be in f35
51694fmovd %f20, %f32
51695fmovs %f16, %f21
51696fadds %f16, %f17, %f16
51697fmovd %f20, %f34
51698membar #Sync
51699stda %f32, [%i0 + 0 ] %asi
51700
51701P4787: !_MEMBAR (FP) (Branch target of P4695)
51702membar #StoreLoad
51703ba P4788
51704nop
51705
51706TARGET4695:
51707ba RET4695
51708nop
51709
51710
51711P4788: !_CASX [8] (maybe <- 0x2000153) (Int) (LE)
51712! Change single-word-level endianess (big endian <-> little endian)
51713sethi %hi(0xff00ff00), %l7
51714or %l7, %lo(0xff00ff00), %l7
51715and %l4, %l7, %l6
51716srl %l6, 8, %l6
51717sll %l4, 8, %o5
51718and %o5, %l7, %o5
51719or %o5, %l6, %o5
51720srl %o5, 16, %l6
51721sll %o5, 16, %o5
51722srl %o5, 0, %o5
51723or %o5, %l6, %o5
51724sllx %o5, 32, %o5
51725wr %g0, 0x88, %asi
51726sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
51727sub %i0, %i3, %i3
51728add %i3, 8, %l7
51729ldxa [%l7] %asi, %l3
51730! move %l3(lower) -> %o0(upper)
51731sllx %l3, 32, %o0
51732! move %l3(upper) -> %o0(lower)
51733srlx %l3, 32, %l6
51734or %l6, %o0, %o0
51735mov %l3, %l6
51736mov %o5, %l3
51737casxa [%l7] %asi, %l6, %l3
51738! move %l3(lower) -> %o1(upper)
51739sllx %l3, 32, %o1
51740! move %l3(upper) -> %o1(lower)
51741srlx %l3, 32, %l6
51742or %l6, %o1, %o1
51743add %l4, 1, %l4
51744
51745P4789: !_ST [4] (maybe <- 0x418000d0) (FP)
51746! preparing store val #0, next val will be in f20
51747fmovs %f16, %f20
51748fadds %f16, %f17, %f16
51749st %f20, [%i1 + 4 ]
51750
51751P4790: !_DWST [19] (maybe <- 0x2000154) (Int)
51752sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
51753sub %i0, %i2, %i2
51754sllx %l4, 32, %l3
51755add %l4, 1, %l4
51756or %l3, %l4, %l3
51757stx %l3, [%i2 + 0]
51758add %l4, 1, %l4
51759
51760P4791: !_REPLACEMENT [18] (Int) (Branch target of P4627)
51761sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
51762sub %i0, %i3, %i3
51763sethi %hi(0x20000), %o5
51764ld [%i3+0], %l6
51765st %l6, [%i3+0]
51766add %i3, %o5, %l3
51767ld [%l3+0], %l6
51768st %l6, [%l3+0]
51769add %l3, %o5, %l3
51770ld [%l3+0], %l6
51771st %l6, [%l3+0]
51772add %l3, %o5, %l3
51773ld [%l3+0], %l6
51774st %l6, [%l3+0]
51775add %l3, %o5, %l3
51776ld [%l3+0], %l6
51777st %l6, [%l3+0]
51778add %l3, %o5, %l3
51779ld [%l3+0], %l6
51780st %l6, [%l3+0]
51781add %l3, %o5, %l3
51782ld [%l3+0], %l6
51783st %l6, [%l3+0]
51784add %l3, %o5, %l3
51785ld [%l3+0], %l6
51786st %l6, [%l3+0]
51787ba P4792
51788nop
51789
51790TARGET4627:
51791ba RET4627
51792nop
51793
51794
51795P4792: !_DWST_BINIT [16] (maybe <- 0x2000156) (Int)
51796wr %g0, 0xe2, %asi
51797sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
51798sub %i0, %i2, %i2
51799sllx %l4, 32, %l7
51800add %l4, 1, %l4
51801or %l7, %l4, %l7
51802stxa %l7, [%i2 + 0] %asi
51803add %l4, 1, %l4
51804
51805P4793: !_MEMBAR (Int)
51806membar #StoreLoad
51807
51808P4794: !_SWAP [8] (maybe <- 0x2000158) (Int)
51809sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
51810sub %i0, %i3, %i3
51811mov %l4, %o2
51812swap [%i3 + 12], %o2
51813! move %o2(lower) -> %o2(upper)
51814sllx %o2, 32, %o2
51815add %l4, 1, %l4
51816
51817P4795: !_ST [23] (maybe <- 0x2000159) (Int)
51818sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
51819add %i0, %i2, %i2
51820stw %l4, [%i2 + 12 ]
51821add %l4, 1, %l4
51822
51823P4796: !_LDD [3] (Int)
51824ldd [%i1 + 0], %l6
51825! move %l6(lower) -> %o2(lower)
51826or %l6, %o2, %o2
51827! move %l7(lower) -> %o3(upper)
51828sllx %l7, 32, %o3
51829
51830P4797: !_LDD [9] (Int)
51831sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
51832sub %i0, %i3, %i3
51833ldd [%i3 + 0], %l6
51834! move %l6(lower) -> %o3(lower)
51835or %l6, %o3, %o3
51836! move %l7(lower) -> %o4(upper)
51837sllx %l7, 32, %o4
51838
51839P4798: !_PREFETCH [4] (Int)
51840prefetch [%i1 + 4], 19
51841
51842P4799: !_SWAP [11] (maybe <- 0x200015a) (Int)
51843mov %l4, %l7
51844swap [%i3 + 12], %l7
51845! move %l7(lower) -> %o4(lower)
51846srl %l7, 0, %l3
51847or %l3, %o4, %o4
51848!---- flushing int results buffer----
51849mov %o0, %l5
51850mov %o1, %l5
51851mov %o2, %l5
51852mov %o3, %l5
51853mov %o4, %l5
51854add %l4, 1, %l4
51855
51856P4800: !_CAS [8] (maybe <- 0x200015b) (Int)
51857sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
51858sub %i0, %i2, %i2
51859add %i2, 12, %l3
51860lduw [%l3], %o0
51861mov %o0, %o5
51862! move %o5(lower) -> %o0(upper)
51863sllx %o5, 32, %o0
51864mov %l4, %l7
51865cas [%l3], %o5, %l7
51866! move %l7(lower) -> %o0(lower)
51867srl %l7, 0, %o5
51868or %o5, %o0, %o0
51869add %l4, 1, %l4
51870
51871P4801: !_ST [20] (maybe <- 0x418000d1) (FP)
51872sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
51873sub %i0, %i3, %i3
51874! preparing store val #0, next val will be in f20
51875fmovs %f16, %f20
51876fadds %f16, %f17, %f16
51877st %f20, [%i3 + 12 ]
51878
51879P4802: !_CAS [22] (maybe <- 0x200015c) (Int) (CBR)
51880sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
51881add %i0, %i2, %i2
51882add %i2, 4, %o5
51883lduw [%o5], %o1
51884mov %o1, %l7
51885! move %l7(lower) -> %o1(upper)
51886sllx %l7, 32, %o1
51887mov %l4, %l6
51888cas [%o5], %l7, %l6
51889! move %l6(lower) -> %o1(lower)
51890srl %l6, 0, %l7
51891or %l7, %o1, %o1
51892add %l4, 1, %l4
51893
51894! cbranch
51895andcc %l0, 1, %g0
51896be,pn %xcc, TARGET4802
51897nop
51898RET4802:
51899
51900! lfsr step begin
51901srlx %l0, 1, %l7
51902xnor %l7, %l0, %l7
51903sllx %l7, 63, %l7
51904or %l7, %l0, %l0
51905srlx %l0, 1, %l0
51906
51907
51908P4803: !_ST [10] (maybe <- 0x200015d) (Int)
51909sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
51910sub %i0, %i3, %i3
51911stw %l4, [%i3 + 4 ]
51912add %l4, 1, %l4
51913
51914P4804: !_DWLD [3] (Int)
51915ldx [%i1 + 0], %o2
51916! move %o2(upper) -> %o2(upper)
51917! move %o2(lower) -> %o2(lower)
51918
51919P4805: !_CAS [7] (maybe <- 0x200015e) (Int)
51920sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
51921sub %i0, %i2, %i2
51922add %i2, 4, %l6
51923lduw [%l6], %o3
51924mov %o3, %l3
51925! move %l3(lower) -> %o3(upper)
51926sllx %l3, 32, %o3
51927mov %l4, %o5
51928cas [%l6], %l3, %o5
51929! move %o5(lower) -> %o3(lower)
51930srl %o5, 0, %l3
51931or %l3, %o3, %o3
51932add %l4, 1, %l4
51933
51934P4806: !_DWST_BINIT [12] (maybe <- 0x200015f) (Int)
51935wr %g0, 0xe2, %asi
51936sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
51937sub %i0, %i3, %i3
51938sllx %l4, 32, %l3
51939add %l4, 1, %l4
51940or %l3, %l4, %l3
51941stxa %l3, [%i3 + 0] %asi
51942add %l4, 1, %l4
51943
51944P4807: !_MEMBAR (Int)
51945membar #StoreLoad
51946
51947P4808: !_SWAP [18] (maybe <- 0x2000161) (Int) (Branch target of P4447)
51948sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
51949sub %i0, %i2, %i2
51950mov %l4, %o4
51951swap [%i2 + 0], %o4
51952! move %o4(lower) -> %o4(upper)
51953sllx %o4, 32, %o4
51954add %l4, 1, %l4
51955ba P4809
51956nop
51957
51958TARGET4447:
51959ba RET4447
51960nop
51961
51962
51963P4809: !_ST [5] (maybe <- 0x418000d2) (FP)
51964! preparing store val #0, next val will be in f20
51965fmovs %f16, %f20
51966fadds %f16, %f17, %f16
51967st %f20, [%i1 + 12 ]
51968
51969P4810: !_LD [9] (FP)
51970sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
51971sub %i0, %i3, %i3
51972ld [%i3 + 0], %f13
51973! 1 addresses covered
51974
51975P4811: !_MEMBAR (FP)
51976membar #StoreLoad
51977
51978P4812: !_BLD [8] (FP)
51979wr %g0, 0xf0, %asi
51980sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
51981sub %i0, %i2, %i2
51982ldda [%i2 + 0] %asi, %f32
51983membar #Sync
51984! 3 addresses covered
51985fmovd %f32, %f14
51986!---- flushing fp results buffer to %f30 ----
51987fmovd %f0, %f30
51988fmovd %f2, %f30
51989fmovd %f4, %f30
51990fmovd %f6, %f30
51991fmovd %f8, %f30
51992fmovd %f10, %f30
51993fmovd %f12, %f30
51994fmovd %f14, %f30
51995!--
51996fmovd %f34, %f18
51997fmovs %f19, %f0
51998
51999P4813: !_MEMBAR (FP)
52000
52001P4814: !_ST [14] (maybe <- 0x418000d3) (FP)
52002sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i3
52003sub %i0, %i3, %i3
52004! preparing store val #0, next val will be in f20
52005fmovs %f16, %f20
52006fadds %f16, %f17, %f16
52007st %f20, [%i3 + 12 ]
52008
52009P4815: !_MEMBAR (FP)
52010membar #StoreLoad
52011
52012P4816: !_BLD [4] (FP)
52013wr %g0, 0xf0, %asi
52014ldda [%i1 + 0] %asi, %f32
52015membar #Sync
52016! 3 addresses covered
52017fmovd %f32, %f18
52018fmovs %f18, %f1
52019fmovs %f19, %f2
52020fmovd %f34, %f18
52021fmovs %f19, %f3
52022
52023P4817: !_MEMBAR (FP)
52024
52025P4818: !_DWST [6] (maybe <- 0x2000162) (Int) (LE)
52026wr %g0, 0x88, %asi
52027sllx %l4, 32, %l3
52028add %l4, 1, %l4
52029or %l3, %l4, %l6
52030! Change double-word-level endianess (big endian <-> little endian)
52031sethi %hi(0xff00ff00), %l7
52032or %l7, %lo(0xff00ff00), %l7
52033sllx %l7, 32, %l3
52034or %l7, %l3, %l7
52035and %l6, %l7, %l3
52036srlx %l3, 8, %l3
52037sllx %l6, 8, %l6
52038and %l6, %l7, %l6
52039or %l6, %l3, %l6
52040sethi %hi(0xffff0000), %l7
52041srlx %l6, 16, %l3
52042andn %l3, %l7, %l3
52043andn %l6, %l7, %l6
52044sllx %l6, 16, %l6
52045or %l6, %l3, %l6
52046srlx %l6, 32, %l3
52047sllx %l6, 32, %l6
52048or %l6, %l3, %l3
52049stxa %l3, [%i2 + 0 ] %asi
52050add %l4, 1, %l4
52051
52052P4819: !_ST [21] (maybe <- 0x418000d4) (FP)
52053sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
52054add %i0, %i2, %i2
52055! preparing store val #0, next val will be in f20
52056fmovs %f16, %f20
52057fadds %f16, %f17, %f16
52058st %f20, [%i2 + 0 ]
52059
52060P4820: !_CAS [6] (maybe <- 0x2000164) (Int)
52061sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
52062sub %i0, %i3, %i3
52063lduw [%i3], %l6
52064mov %l6, %l7
52065! move %l7(lower) -> %o4(lower)
52066or %l7, %o4, %o4
52067!---- flushing int results buffer----
52068mov %o0, %l5
52069mov %o1, %l5
52070mov %o2, %l5
52071mov %o3, %l5
52072mov %o4, %l5
52073mov %l4, %o0
52074cas [%i3], %l7, %o0
52075! move %o0(lower) -> %o0(upper)
52076sllx %o0, 32, %o0
52077add %l4, 1, %l4
52078
52079P4821: !_LDD [17] (Int)
52080sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
52081sub %i0, %i2, %i2
52082ldd [%i2 + 8], %l6
52083! move %l7(lower) -> %o0(lower)
52084or %l7, %o0, %o0
52085
52086P4822: !_DWLD [8] (Int)
52087ldx [%i3 + 8], %o1
52088! move %o1(lower) -> %o1(upper)
52089sllx %o1, 32, %o1
52090
52091P4823: !_ST [8] (maybe <- 0x2000165) (Int)
52092stw %l4, [%i3 + 12 ]
52093add %l4, 1, %l4
52094
52095P4824: !_LD [21] (Int)
52096sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
52097add %i0, %i3, %i3
52098lduw [%i3 + 0], %l7
52099! move %l7(lower) -> %o1(lower)
52100or %l7, %o1, %o1
52101
52102P4825: !_CAS [22] (maybe <- 0x2000166) (Int)
52103add %i3, 4, %l3
52104lduw [%l3], %o2
52105mov %o2, %o5
52106! move %o5(lower) -> %o2(upper)
52107sllx %o5, 32, %o2
52108mov %l4, %l7
52109cas [%l3], %o5, %l7
52110! move %l7(lower) -> %o2(lower)
52111srl %l7, 0, %o5
52112or %o5, %o2, %o2
52113add %l4, 1, %l4
52114
52115P4826: !_LDD [14] (Int)
52116sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS3_O), %i2
52117sub %i0, %i2, %i2
52118ldd [%i2 + 8], %l6
52119! move %l7(lower) -> %o3(upper)
52120sllx %l7, 32, %o3
52121
52122P4827: !_DWST [15] (maybe <- 0x2000167) (Int)
52123sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
52124sub %i0, %i3, %i3
52125sllx %l4, 32, %l3
52126add %l4, 1, %l4
52127or %l3, %l4, %l3
52128stx %l3, [%i3 + 0]
52129add %l4, 1, %l4
52130
52131P4828: !_DWLD [16] (Int)
52132ldx [%i3 + 0], %l3
52133! move %l3(upper) -> %o3(lower)
52134srlx %l3, 32, %o5
52135or %o5, %o3, %o3
52136! move %l3(lower) -> %o4(upper)
52137sllx %l3, 32, %o4
52138
52139P4829: !_DWST [14] (maybe <- 0x2000169) (Int)
52140mov %l4, %l6
52141stx %l6, [%i2 + 8]
52142add %l4, 1, %l4
52143
52144P4830: !_DWST_BINIT [17] (maybe <- 0x200016a) (Int) (LE)
52145wr %g0, 0xea, %asi
52146! Change single-word-level endianess (big endian <-> little endian)
52147sethi %hi(0xff00ff00), %l3
52148or %l3, %lo(0xff00ff00), %l3
52149and %l4, %l3, %l7
52150srl %l7, 8, %l7
52151sll %l4, 8, %l6
52152and %l6, %l3, %l6
52153or %l6, %l7, %l6
52154srl %l6, 16, %l7
52155sll %l6, 16, %l6
52156srl %l6, 0, %l6
52157or %l6, %l7, %l6
52158sllx %l6, 32, %l6
52159stxa %l6, [%i3 + 8 ] %asi
52160add %l4, 1, %l4
52161
52162P4831: !_MEMBAR (Int) (LE)
52163membar #StoreLoad
52164
52165P4832: !_DWST_BINIT [10] (maybe <- 0x200016b) (Int)
52166wr %g0, 0xe2, %asi
52167sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
52168sub %i0, %i2, %i2
52169sllx %l4, 32, %o5
52170add %l4, 1, %l4
52171or %o5, %l4, %o5
52172stxa %o5, [%i2 + 0] %asi
52173add %l4, 1, %l4
52174
52175P4833: !_MEMBAR (Int)
52176membar #StoreLoad
52177
52178P4834: !_DWST [16] (maybe <- 0x418000d5) (FP)
52179! preparing store val #0, next val will be in f20
52180fmovs %f16, %f20
52181fadds %f16, %f17, %f16
52182! preparing store val #1, next val will be in f21
52183fmovs %f16, %f21
52184fadds %f16, %f17, %f16
52185std %f20, [%i3 + 0]
52186
52187P4835: !_DWST [20] (maybe <- 0x200016d) (Int)
52188sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
52189sub %i0, %i3, %i3
52190mov %l4, %l6
52191stx %l6, [%i3 + 8]
52192add %l4, 1, %l4
52193
52194P4836: !_PREFETCH [20] (Int)
52195prefetch [%i3 + 12], 0
52196
52197P4837: !_REPLACEMENT [17] (Int)
52198sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
52199sub %i0, %i2, %i2
52200sethi %hi(0x20000), %l3
52201ld [%i2+12], %l7
52202st %l7, [%i2+12]
52203add %i2, %l3, %l6
52204ld [%l6+12], %l7
52205st %l7, [%l6+12]
52206add %l6, %l3, %l6
52207ld [%l6+12], %l7
52208st %l7, [%l6+12]
52209add %l6, %l3, %l6
52210ld [%l6+12], %l7
52211st %l7, [%l6+12]
52212add %l6, %l3, %l6
52213ld [%l6+12], %l7
52214st %l7, [%l6+12]
52215add %l6, %l3, %l6
52216ld [%l6+12], %l7
52217st %l7, [%l6+12]
52218add %l6, %l3, %l6
52219ld [%l6+12], %l7
52220st %l7, [%l6+12]
52221add %l6, %l3, %l6
52222ld [%l6+12], %l7
52223st %l7, [%l6+12]
52224
52225P4838: !_LD [5] (Int)
52226lduw [%i1 + 12], %l3
52227! move %l3(lower) -> %o4(lower)
52228or %l3, %o4, %o4
52229!---- flushing int results buffer----
52230mov %o0, %l5
52231mov %o1, %l5
52232mov %o2, %l5
52233mov %o3, %l5
52234mov %o4, %l5
52235
52236P4839: !_ST_BINIT [17] (maybe <- 0x200016e) (Int) (Branch target of P4413)
52237wr %g0, 0xe2, %asi
52238sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
52239sub %i0, %i3, %i3
52240stwa %l4, [%i3 + 12] %asi
52241add %l4, 1, %l4
52242ba P4840
52243nop
52244
52245TARGET4413:
52246ba RET4413
52247nop
52248
52249
52250P4840: !_MEMBAR (Int)
52251membar #StoreLoad
52252
52253P4841: !_DWST [14] (maybe <- 0x200016f) (Int)
52254sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
52255add %i0, %i2, %i2
52256mov %l4, %l6
52257stx %l6, [%i2 + 8]
52258add %l4, 1, %l4
52259
52260P4842: !_ST [10] (maybe <- 0x2000170) (Int) (CBR)
52261sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
52262sub %i0, %i3, %i3
52263stw %l4, [%i3 + 4 ]
52264add %l4, 1, %l4
52265
52266! cbranch
52267andcc %l0, 1, %g0
52268be,pt %xcc, TARGET4842
52269nop
52270RET4842:
52271
52272! lfsr step begin
52273srlx %l0, 1, %o5
52274xnor %o5, %l0, %o5
52275sllx %o5, 63, %o5
52276or %o5, %l0, %l0
52277srlx %l0, 1, %l0
52278
52279
52280P4843: !_DWLD [19] (Int)
52281sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
52282sub %i0, %i2, %i2
52283ldx [%i2 + 0], %o0
52284! move %o0(upper) -> %o0(upper)
52285! move %o0(lower) -> %o0(lower)
52286
52287P4844: !_ST [7] (maybe <- 0x418000d7) (FP) (Branch target of P4649)
52288sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
52289sub %i0, %i3, %i3
52290! preparing store val #0, next val will be in f20
52291fmovs %f16, %f20
52292fadds %f16, %f17, %f16
52293st %f20, [%i3 + 4 ]
52294ba P4845
52295nop
52296
52297TARGET4649:
52298ba RET4649
52299nop
52300
52301
52302P4845: !_CASX [17] (maybe <- 0x2000171) (Int)
52303sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
52304sub %i0, %i2, %i2
52305add %i2, 8, %l7
52306ldx [%l7], %o1
52307! move %o1(upper) -> %o1(upper)
52308! move %o1(lower) -> %o1(lower)
52309mov %o1, %l6
52310mov %l4, %o2
52311casx [%l7], %l6, %o2
52312! move %o2(upper) -> %o2(upper)
52313! move %o2(lower) -> %o2(lower)
52314add %l4, 1, %l4
52315
52316P4846: !_SWAP [2] (maybe <- 0x2000172) (Int)
52317mov %l4, %o3
52318swap [%i0 + 12], %o3
52319! move %o3(lower) -> %o3(upper)
52320sllx %o3, 32, %o3
52321add %l4, 1, %l4
52322
52323P4847: !_REPLACEMENT [9] (Int) (CBR)
52324sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
52325sub %i0, %i3, %i3
52326sethi %hi(0x20000), %l3
52327ld [%i3+0], %l7
52328st %l7, [%i3+0]
52329add %i3, %l3, %l6
52330ld [%l6+0], %l7
52331st %l7, [%l6+0]
52332add %l6, %l3, %l6
52333ld [%l6+0], %l7
52334st %l7, [%l6+0]
52335add %l6, %l3, %l6
52336ld [%l6+0], %l7
52337st %l7, [%l6+0]
52338add %l6, %l3, %l6
52339ld [%l6+0], %l7
52340st %l7, [%l6+0]
52341add %l6, %l3, %l6
52342ld [%l6+0], %l7
52343st %l7, [%l6+0]
52344add %l6, %l3, %l6
52345ld [%l6+0], %l7
52346st %l7, [%l6+0]
52347add %l6, %l3, %l6
52348ld [%l6+0], %l7
52349st %l7, [%l6+0]
52350
52351! cbranch
52352andcc %l0, 1, %g0
52353be,pt %xcc, TARGET4847
52354nop
52355RET4847:
52356
52357! lfsr step begin
52358srlx %l0, 1, %o5
52359xnor %o5, %l0, %o5
52360sllx %o5, 63, %o5
52361or %o5, %l0, %l0
52362srlx %l0, 1, %l0
52363
52364
52365P4848: !_DWST_BINIT [10] (maybe <- 0x2000173) (Int)
52366wr %g0, 0xe2, %asi
52367sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
52368sub %i0, %i2, %i2
52369sllx %l4, 32, %l3
52370add %l4, 1, %l4
52371or %l3, %l4, %l3
52372stxa %l3, [%i2 + 0] %asi
52373add %l4, 1, %l4
52374
52375P4849: !_MEMBAR (Int)
52376membar #StoreLoad
52377
52378P4850: !_DWST [20] (maybe <- 0x2000175) (Int)
52379sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
52380sub %i0, %i3, %i3
52381mov %l4, %o5
52382stx %o5, [%i3 + 8]
52383add %l4, 1, %l4
52384
52385P4851: !_ST [19] (maybe <- 0x418000d8) (FP)
52386! preparing store val #0, next val will be in f20
52387fmovs %f16, %f20
52388fadds %f16, %f17, %f16
52389st %f20, [%i3 + 4 ]
52390
52391P4852: !_DWST [4] (maybe <- 0x2000176) (Int)
52392sllx %l4, 32, %l6
52393add %l4, 1, %l4
52394or %l6, %l4, %l6
52395stx %l6, [%i1 + 0]
52396add %l4, 1, %l4
52397
52398P4853: !_MEMBAR (FP)
52399
52400P4854: !_BSTC [2] (maybe <- 0x418000d9) (FP)
52401wr %g0, 0xe0, %asi
52402! preparing store val #0, next val will be in f32
52403fmovs %f16, %f20
52404fadds %f16, %f17, %f16
52405! preparing store val #1, next val will be in f33
52406fmovs %f16, %f21
52407fadds %f16, %f17, %f16
52408! preparing store val #2, next val will be in f35
52409fmovd %f20, %f32
52410fmovs %f16, %f21
52411fadds %f16, %f17, %f16
52412fmovd %f20, %f34
52413membar #Sync
52414stda %f32, [%i0 + 0 ] %asi
52415
52416P4855: !_MEMBAR (FP)
52417membar #StoreLoad
52418
52419P4856: !_DWLD [12] (Int)
52420sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
52421add %i0, %i2, %i2
52422ldx [%i2 + 0], %l3
52423! move %l3(upper) -> %o3(lower)
52424srlx %l3, 32, %o5
52425or %o5, %o3, %o3
52426! move %l3(lower) -> %o4(upper)
52427sllx %l3, 32, %o4
52428
52429P4857: !_MEMBAR (FP)
52430membar #StoreLoad
52431
52432P4858: !_BLD [5] (FP)
52433wr %g0, 0xf0, %asi
52434ldda [%i1 + 0] %asi, %f32
52435membar #Sync
52436! 3 addresses covered
52437fmovd %f32, %f4
52438fmovd %f34, %f18
52439fmovs %f19, %f6
52440
52441P4859: !_MEMBAR (FP)
52442
52443P4860: !_ST [17] (maybe <- 0x2000178) (Int)
52444sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
52445sub %i0, %i3, %i3
52446stw %l4, [%i3 + 12 ]
52447add %l4, 1, %l4
52448
52449P4861: !_CAS [22] (maybe <- 0x2000179) (Int)
52450sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
52451add %i0, %i2, %i2
52452add %i2, 4, %l6
52453lduw [%l6], %o5
52454mov %o5, %l3
52455! move %l3(lower) -> %o4(lower)
52456or %l3, %o4, %o4
52457!---- flushing int results buffer----
52458mov %o0, %l5
52459mov %o1, %l5
52460mov %o2, %l5
52461mov %o3, %l5
52462mov %o4, %l5
52463mov %l4, %o0
52464cas [%l6], %l3, %o0
52465! move %o0(lower) -> %o0(upper)
52466sllx %o0, 32, %o0
52467add %l4, 1, %l4
52468
52469P4862: !_MEMBAR (FP)
52470
52471P4863: !_BST [22] (maybe <- 0x418000dc) (FP)
52472wr %g0, 0xf0, %asi
52473! preparing store val #0, next val will be in f32
52474fmovs %f16, %f20
52475fadds %f16, %f17, %f16
52476! preparing store val #1, next val will be in f33
52477fmovs %f16, %f21
52478fadds %f16, %f17, %f16
52479! preparing store val #2, next val will be in f35
52480fmovd %f20, %f32
52481fmovs %f16, %f21
52482fadds %f16, %f17, %f16
52483fmovd %f20, %f34
52484membar #Sync
52485stda %f32, [%i2 + 0 ] %asi
52486
52487P4864: !_MEMBAR (FP)
52488membar #StoreLoad
52489
52490P4865: !_SWAP [12] (maybe <- 0x200017a) (Int)
52491sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
52492add %i0, %i3, %i3
52493mov %l4, %l6
52494swap [%i3 + 0], %l6
52495! move %l6(lower) -> %o0(lower)
52496srl %l6, 0, %o5
52497or %o5, %o0, %o0
52498add %l4, 1, %l4
52499
52500P4866: !_LD [4] (Int) (Branch target of P4867)
52501lduw [%i1 + 4], %o1
52502! move %o1(lower) -> %o1(upper)
52503sllx %o1, 32, %o1
52504ba P4867
52505nop
52506
52507TARGET4867:
52508ba RET4867
52509nop
52510
52511
52512P4867: !_DWST_BINIT [15] (maybe <- 0x200017b) (Int) (CBR)
52513wr %g0, 0xe2, %asi
52514sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
52515sub %i0, %i2, %i2
52516sllx %l4, 32, %l3
52517add %l4, 1, %l4
52518or %l3, %l4, %l3
52519stxa %l3, [%i2 + 0] %asi
52520add %l4, 1, %l4
52521
52522! cbranch
52523andcc %l0, 1, %g0
52524be,pt %xcc, TARGET4867
52525nop
52526RET4867:
52527
52528! lfsr step begin
52529srlx %l0, 1, %o5
52530xnor %o5, %l0, %o5
52531sllx %o5, 63, %o5
52532or %o5, %l0, %l0
52533srlx %l0, 1, %l0
52534
52535
52536P4868: !_MEMBAR (Int)
52537membar #StoreLoad
52538
52539P4869: !_CASX [2] (maybe <- 0x200017d) (Int)
52540add %i0, 8, %l6
52541ldx [%l6], %o5
52542! move %o5(upper) -> %o1(lower)
52543srlx %o5, 32, %l3
52544or %l3, %o1, %o1
52545! move %o5(lower) -> %o2(upper)
52546sllx %o5, 32, %o2
52547mov %o5, %l3
52548mov %l4, %o5
52549casx [%l6], %l3, %o5
52550! move %o5(upper) -> %o2(lower)
52551srlx %o5, 32, %l3
52552or %l3, %o2, %o2
52553! move %o5(lower) -> %o3(upper)
52554sllx %o5, 32, %o3
52555add %l4, 1, %l4
52556
52557P4870: !_MEMBAR (FP)
52558membar #StoreLoad
52559
52560P4871: !_BLD [13] (FP)
52561wr %g0, 0xf0, %asi
52562ldda [%i3 + 0] %asi, %f32
52563membar #Sync
52564! 3 addresses covered
52565fmovd %f32, %f18
52566fmovs %f18, %f7
52567fmovs %f19, %f8
52568fmovd %f34, %f18
52569fmovs %f19, %f9
52570
52571P4872: !_MEMBAR (FP)
52572
52573P4873: !_BLD [9] (FP)
52574wr %g0, 0xf0, %asi
52575sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
52576sub %i0, %i3, %i3
52577ldda [%i3 + 0] %asi, %f32
52578membar #Sync
52579! 3 addresses covered
52580fmovd %f32, %f10
52581fmovd %f34, %f18
52582fmovs %f19, %f12
52583
52584P4874: !_MEMBAR (FP) (CBR)
52585
52586! cbranch
52587andcc %l0, 1, %g0
52588be,pt %xcc, TARGET4874
52589nop
52590RET4874:
52591
52592! lfsr step begin
52593srlx %l0, 1, %l3
52594xnor %l3, %l0, %l3
52595sllx %l3, 63, %l3
52596or %l3, %l0, %l0
52597srlx %l0, 1, %l0
52598
52599
52600P4875: !_PREFETCH [11] (Int)
52601prefetch [%i3 + 12], 22
52602
52603P4876: !_LDD [13] (Int)
52604sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
52605add %i0, %i2, %i2
52606ldd [%i2 + 0], %l6
52607! move %l6(lower) -> %o3(lower)
52608or %l6, %o3, %o3
52609! move %l7(lower) -> %o4(upper)
52610sllx %l7, 32, %o4
52611
52612P4877: !_MEMBAR (FP)
52613
52614P4878: !_BST [7] (maybe <- 0x418000df) (FP)
52615wr %g0, 0xf0, %asi
52616sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
52617sub %i0, %i3, %i3
52618! preparing store val #0, next val will be in f32
52619fmovs %f16, %f20
52620fadds %f16, %f17, %f16
52621! preparing store val #1, next val will be in f33
52622fmovs %f16, %f21
52623fadds %f16, %f17, %f16
52624! preparing store val #2, next val will be in f35
52625fmovd %f20, %f32
52626fmovs %f16, %f21
52627fadds %f16, %f17, %f16
52628fmovd %f20, %f34
52629membar #Sync
52630stda %f32, [%i3 + 0 ] %asi
52631
52632P4879: !_MEMBAR (FP)
52633membar #StoreLoad
52634
52635P4880: !_ST [14] (maybe <- 0x200017e) (Int)
52636stw %l4, [%i2 + 12 ]
52637add %l4, 1, %l4
52638
52639P4881: !_CASX [5] (maybe <- 0x200017f) (Int)
52640add %i1, 8, %o5
52641ldx [%o5], %l6
52642! move %l6(upper) -> %o4(lower)
52643srlx %l6, 32, %l7
52644or %l7, %o4, %o4
52645!---- flushing int results buffer----
52646mov %o0, %l5
52647mov %o1, %l5
52648mov %o2, %l5
52649mov %o3, %l5
52650mov %o4, %l5
52651! move %l6(lower) -> %o0(upper)
52652sllx %l6, 32, %o0
52653mov %l6, %l7
52654mov %l4, %l6
52655casx [%o5], %l7, %l6
52656! move %l6(upper) -> %o0(lower)
52657srlx %l6, 32, %l7
52658or %l7, %o0, %o0
52659! move %l6(lower) -> %o1(upper)
52660sllx %l6, 32, %o1
52661add %l4, 1, %l4
52662
52663P4882: !_SWAP [16] (maybe <- 0x2000180) (Int)
52664sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
52665sub %i0, %i2, %i2
52666mov %l4, %l3
52667swap [%i2 + 4], %l3
52668! move %l3(lower) -> %o1(lower)
52669srl %l3, 0, %l7
52670or %l7, %o1, %o1
52671add %l4, 1, %l4
52672
52673P4883: !_DWST_BINIT [6] (maybe <- 0x2000181) (Int) (LE)
52674wr %g0, 0xea, %asi
52675sllx %l4, 32, %l6
52676add %l4, 1, %l4
52677or %l6, %l4, %l7
52678! Change double-word-level endianess (big endian <-> little endian)
52679sethi %hi(0xff00ff00), %o5
52680or %o5, %lo(0xff00ff00), %o5
52681sllx %o5, 32, %l6
52682or %o5, %l6, %o5
52683and %l7, %o5, %l6
52684srlx %l6, 8, %l6
52685sllx %l7, 8, %l7
52686and %l7, %o5, %l7
52687or %l7, %l6, %l7
52688sethi %hi(0xffff0000), %o5
52689srlx %l7, 16, %l6
52690andn %l6, %o5, %l6
52691andn %l7, %o5, %l7
52692sllx %l7, 16, %l7
52693or %l7, %l6, %l7
52694srlx %l7, 32, %l6
52695sllx %l7, 32, %l7
52696or %l7, %l6, %l6
52697stxa %l6, [%i3 + 0 ] %asi
52698add %l4, 1, %l4
52699
52700P4884: !_MEMBAR (Int) (LE)
52701
52702P4885: !_BSTC [8] (maybe <- 0x418000e2) (FP)
52703wr %g0, 0xe0, %asi
52704! preparing store val #0, next val will be in f32
52705fmovs %f16, %f20
52706fadds %f16, %f17, %f16
52707! preparing store val #1, next val will be in f33
52708fmovs %f16, %f21
52709fadds %f16, %f17, %f16
52710! preparing store val #2, next val will be in f35
52711fmovd %f20, %f32
52712fmovs %f16, %f21
52713fadds %f16, %f17, %f16
52714fmovd %f20, %f34
52715membar #Sync
52716stda %f32, [%i3 + 0 ] %asi
52717
52718P4886: !_MEMBAR (FP)
52719membar #StoreLoad
52720
52721P4887: !_CAS [17] (maybe <- 0x2000183) (Int)
52722add %i2, 12, %l3
52723lduw [%l3], %o2
52724mov %o2, %o5
52725! move %o5(lower) -> %o2(upper)
52726sllx %o5, 32, %o2
52727mov %l4, %l7
52728cas [%l3], %o5, %l7
52729! move %l7(lower) -> %o2(lower)
52730srl %l7, 0, %o5
52731or %o5, %o2, %o2
52732add %l4, 1, %l4
52733
52734P4888: !_ST_BINIT [22] (maybe <- 0x2000184) (Int)
52735wr %g0, 0xe2, %asi
52736sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
52737add %i0, %i3, %i3
52738stwa %l4, [%i3 + 4] %asi
52739add %l4, 1, %l4
52740
52741P4889: !_MEMBAR (Int)
52742membar #StoreLoad
52743
52744P4890: !_ST_BINIT [23] (maybe <- 0x2000185) (Int)
52745wr %g0, 0xe2, %asi
52746stwa %l4, [%i3 + 12] %asi
52747add %l4, 1, %l4
52748
52749P4891: !_MEMBAR (Int) (Branch target of P4247)
52750ba P4892
52751nop
52752
52753TARGET4247:
52754ba RET4247
52755nop
52756
52757
52758P4892: !_BSTC [16] (maybe <- 0x418000e5) (FP)
52759wr %g0, 0xe0, %asi
52760! preparing store val #0, next val will be in f32
52761fmovs %f16, %f20
52762fadds %f16, %f17, %f16
52763! preparing store val #1, next val will be in f33
52764fmovs %f16, %f21
52765fadds %f16, %f17, %f16
52766! preparing store val #2, next val will be in f35
52767fmovd %f20, %f32
52768fmovs %f16, %f21
52769fadds %f16, %f17, %f16
52770fmovd %f20, %f34
52771membar #Sync
52772stda %f32, [%i2 + 0 ] %asi
52773
52774P4893: !_MEMBAR (FP)
52775membar #StoreLoad
52776
52777P4894: !_SWAP [3] (maybe <- 0x2000186) (Int) (CBR)
52778mov %l4, %o3
52779swap [%i1 + 0], %o3
52780! move %o3(lower) -> %o3(upper)
52781sllx %o3, 32, %o3
52782add %l4, 1, %l4
52783
52784! cbranch
52785andcc %l0, 1, %g0
52786be,pn %xcc, TARGET4894
52787nop
52788RET4894:
52789
52790! lfsr step begin
52791srlx %l0, 1, %o5
52792xnor %o5, %l0, %o5
52793sllx %o5, 63, %o5
52794or %o5, %l0, %l0
52795srlx %l0, 1, %l0
52796
52797
52798P4895: !_MEMBAR (FP)
52799
52800P4896: !_BST [21] (maybe <- 0x418000e8) (FP) (Branch target of P4043)
52801wr %g0, 0xf0, %asi
52802! preparing store val #0, next val will be in f32
52803fmovs %f16, %f20
52804fadds %f16, %f17, %f16
52805! preparing store val #1, next val will be in f33
52806fmovs %f16, %f21
52807fadds %f16, %f17, %f16
52808! preparing store val #2, next val will be in f35
52809fmovd %f20, %f32
52810fmovs %f16, %f21
52811fadds %f16, %f17, %f16
52812fmovd %f20, %f34
52813membar #Sync
52814stda %f32, [%i3 + 0 ] %asi
52815ba P4897
52816nop
52817
52818TARGET4043:
52819ba RET4043
52820nop
52821
52822
52823P4897: !_MEMBAR (FP)
52824membar #StoreLoad
52825
52826P4898: !_DWLD [23] (Int)
52827ldx [%i3 + 8], %l3
52828! move %l3(lower) -> %o3(lower)
52829srl %l3, 0, %o5
52830or %o5, %o3, %o3
52831
52832P4899: !_MEMBAR (FP)
52833
52834P4900: !_BST [13] (maybe <- 0x418000eb) (FP)
52835wr %g0, 0xf0, %asi
52836sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
52837add %i0, %i2, %i2
52838! preparing store val #0, next val will be in f32
52839fmovs %f16, %f20
52840fadds %f16, %f17, %f16
52841! preparing store val #1, next val will be in f33
52842fmovs %f16, %f21
52843fadds %f16, %f17, %f16
52844! preparing store val #2, next val will be in f35
52845fmovd %f20, %f32
52846fmovs %f16, %f21
52847fadds %f16, %f17, %f16
52848fmovd %f20, %f34
52849membar #Sync
52850stda %f32, [%i2 + 0 ] %asi
52851
52852P4901: !_MEMBAR (FP)
52853membar #StoreLoad
52854
52855P4902: !_DWLD [5] (Int)
52856ldx [%i1 + 8], %o4
52857! move %o4(lower) -> %o4(upper)
52858sllx %o4, 32, %o4
52859
52860P4903: !_SWAP [3] (maybe <- 0x2000187) (Int)
52861mov %l4, %l3
52862swap [%i1 + 0], %l3
52863! move %l3(lower) -> %o4(lower)
52864srl %l3, 0, %l7
52865or %l7, %o4, %o4
52866!---- flushing int results buffer----
52867mov %o0, %l5
52868mov %o1, %l5
52869mov %o2, %l5
52870mov %o3, %l5
52871mov %o4, %l5
52872add %l4, 1, %l4
52873
52874P4904: !_MEMBAR (FP) (CBR)
52875
52876! cbranch
52877andcc %l0, 1, %g0
52878be,pn %xcc, TARGET4904
52879nop
52880RET4904:
52881
52882! lfsr step begin
52883srlx %l0, 1, %l6
52884xnor %l6, %l0, %l6
52885sllx %l6, 63, %l6
52886or %l6, %l0, %l0
52887srlx %l0, 1, %l0
52888
52889
52890P4905: !_BST [4] (maybe <- 0x418000ee) (FP)
52891!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #3
52892!Logical addr: 4
52893
52894sethi %hi(0x200000), %l7
52895sub %i1, %l7, %i1
52896wr %g0, 0xf0, %asi
52897! preparing store val #0, next val will be in f32
52898fmovs %f16, %f20
52899fadds %f16, %f17, %f16
52900! preparing store val #1, next val will be in f33
52901fmovs %f16, %f21
52902fadds %f16, %f17, %f16
52903! preparing store val #2, next val will be in f35
52904fmovd %f20, %f32
52905fmovs %f16, %f21
52906fadds %f16, %f17, %f16
52907fmovd %f20, %f34
52908membar #Sync
52909stda %f32, [%i1 + 0 ] %asi
52910
52911P4906: !_MEMBAR (FP)
52912membar #StoreLoad
52913
52914P4907: !_LD [17] (Int)
52915sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
52916sub %i0, %i3, %i3
52917lduw [%i3 + 12], %o0
52918! move %o0(lower) -> %o0(upper)
52919sllx %o0, 32, %o0
52920
52921P4908: !_CAS [4] (maybe <- 0x2000188) (Int)
52922add %i1, 4, %l6
52923lduw [%l6], %o5
52924mov %o5, %l3
52925! move %l3(lower) -> %o0(lower)
52926or %l3, %o0, %o0
52927mov %l4, %o1
52928cas [%l6], %l3, %o1
52929! move %o1(lower) -> %o1(upper)
52930sllx %o1, 32, %o1
52931add %l4, 1, %l4
52932
52933P4909: !_DWST [22] (maybe <- 0x2000189) (Int)
52934sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
52935add %i0, %i2, %i2
52936sllx %l4, 32, %l3
52937add %l4, 1, %l4
52938or %l3, %l4, %l3
52939stx %l3, [%i2 + 0]
52940add %l4, 1, %l4
52941
52942P4910: !_MEMBAR (FP)
52943
52944P4911: !_BST [15] (maybe <- 0x418000f1) (FP)
52945wr %g0, 0xf0, %asi
52946! preparing store val #0, next val will be in f32
52947fmovs %f16, %f20
52948fadds %f16, %f17, %f16
52949! preparing store val #1, next val will be in f33
52950fmovs %f16, %f21
52951fadds %f16, %f17, %f16
52952! preparing store val #2, next val will be in f35
52953fmovd %f20, %f32
52954fmovs %f16, %f21
52955fadds %f16, %f17, %f16
52956fmovd %f20, %f34
52957membar #Sync
52958stda %f32, [%i3 + 0 ] %asi
52959
52960P4912: !_MEMBAR (FP)
52961membar #StoreLoad
52962
52963P4913: !_ST_BINIT [18] (maybe <- 0x200018b) (Int)
52964wr %g0, 0xe2, %asi
52965sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
52966sub %i0, %i3, %i3
52967stwa %l4, [%i3 + 0] %asi
52968add %l4, 1, %l4
52969
52970P4914: !_MEMBAR (Int)
52971membar #StoreLoad
52972
52973P4915: !_REPLACEMENT [10] (Int)
52974sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
52975sub %i0, %i2, %i2
52976sethi %hi(0x20000), %l6
52977ld [%i2+4], %o5
52978st %o5, [%i2+4]
52979add %i2, %l6, %l7
52980ld [%l7+4], %o5
52981st %o5, [%l7+4]
52982add %l7, %l6, %l7
52983ld [%l7+4], %o5
52984st %o5, [%l7+4]
52985add %l7, %l6, %l7
52986ld [%l7+4], %o5
52987st %o5, [%l7+4]
52988add %l7, %l6, %l7
52989ld [%l7+4], %o5
52990st %o5, [%l7+4]
52991add %l7, %l6, %l7
52992ld [%l7+4], %o5
52993st %o5, [%l7+4]
52994add %l7, %l6, %l7
52995ld [%l7+4], %o5
52996st %o5, [%l7+4]
52997add %l7, %l6, %l7
52998ld [%l7+4], %o5
52999st %o5, [%l7+4]
53000
53001P4916: !_CASX [5] (maybe <- 0x200018c) (Int)
53002add %i1, 8, %l6
53003ldx [%l6], %o5
53004! move %o5(upper) -> %o1(lower)
53005srlx %o5, 32, %l3
53006or %l3, %o1, %o1
53007! move %o5(lower) -> %o2(upper)
53008sllx %o5, 32, %o2
53009mov %o5, %l3
53010mov %l4, %o5
53011casx [%l6], %l3, %o5
53012! move %o5(upper) -> %o2(lower)
53013srlx %o5, 32, %l3
53014or %l3, %o2, %o2
53015! move %o5(lower) -> %o3(upper)
53016sllx %o5, 32, %o3
53017add %l4, 1, %l4
53018
53019P4917: !_ST [11] (maybe <- 0x200018d) (Int)
53020sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
53021sub %i0, %i3, %i3
53022stw %l4, [%i3 + 12 ]
53023add %l4, 1, %l4
53024
53025P4918: !_PREFETCH [11] (Int)
53026prefetch [%i3 + 12], 19
53027
53028P4919: !_SWAP [7] (maybe <- 0x200018e) (Int)
53029sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
53030sub %i0, %i2, %i2
53031mov %l4, %l6
53032swap [%i2 + 4], %l6
53033! move %l6(lower) -> %o3(lower)
53034srl %l6, 0, %o5
53035or %o5, %o3, %o3
53036add %l4, 1, %l4
53037
53038P4920: !_DWST [22] (maybe <- 0x200018f) (Int)
53039sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
53040add %i0, %i3, %i3
53041sllx %l4, 32, %l7
53042add %l4, 1, %l4
53043or %l7, %l4, %l7
53044stx %l7, [%i3 + 0]
53045add %l4, 1, %l4
53046
53047P4921: !_LDD [0] (Int) (Branch target of P4450)
53048ldd [%i0 + 0], %l6
53049! move %l6(lower) -> %o4(upper)
53050sllx %l6, 32, %o4
53051! move %l7(lower) -> %o4(lower)
53052or %l7, %o4, %o4
53053!---- flushing int results buffer----
53054mov %o0, %l5
53055mov %o1, %l5
53056mov %o2, %l5
53057mov %o3, %l5
53058mov %o4, %l5
53059ba P4922
53060nop
53061
53062TARGET4450:
53063ba RET4450
53064nop
53065
53066
53067P4922: !_LDD [0] (Int)
53068ldd [%i0 + 0], %l6
53069! move %l6(lower) -> %o0(upper)
53070sllx %l6, 32, %o0
53071! move %l7(lower) -> %o0(lower)
53072or %l7, %o0, %o0
53073
53074P4923: !_ST [0] (maybe <- 0x418000f4) (FP)
53075! preparing store val #0, next val will be in f20
53076fmovs %f16, %f20
53077fadds %f16, %f17, %f16
53078st %f20, [%i0 + 0 ]
53079
53080P4924: !_LD [19] (Int)
53081sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
53082sub %i0, %i2, %i2
53083lduw [%i2 + 4], %o1
53084! move %o1(lower) -> %o1(upper)
53085sllx %o1, 32, %o1
53086
53087P4925: !_SWAP [5] (maybe <- 0x2000191) (Int)
53088mov %l4, %o5
53089swap [%i1 + 12], %o5
53090! move %o5(lower) -> %o1(lower)
53091srl %o5, 0, %l6
53092or %l6, %o1, %o1
53093add %l4, 1, %l4
53094
53095P4926: !_ST [1] (maybe <- 0x2000192) (Int)
53096stw %l4, [%i0 + 4 ]
53097add %l4, 1, %l4
53098
53099P4927: !_LD [10] (FP)
53100sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
53101sub %i0, %i3, %i3
53102ld [%i3 + 4], %f13
53103! 1 addresses covered
53104
53105P4928: !_REPLACEMENT [7] (Int)
53106sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
53107sub %i0, %i2, %i2
53108sethi %hi(0x20000), %o5
53109ld [%i2+4], %l6
53110st %l6, [%i2+4]
53111add %i2, %o5, %l3
53112ld [%l3+4], %l6
53113st %l6, [%l3+4]
53114add %l3, %o5, %l3
53115ld [%l3+4], %l6
53116st %l6, [%l3+4]
53117add %l3, %o5, %l3
53118ld [%l3+4], %l6
53119st %l6, [%l3+4]
53120add %l3, %o5, %l3
53121ld [%l3+4], %l6
53122st %l6, [%l3+4]
53123add %l3, %o5, %l3
53124ld [%l3+4], %l6
53125st %l6, [%l3+4]
53126add %l3, %o5, %l3
53127ld [%l3+4], %l6
53128st %l6, [%l3+4]
53129add %l3, %o5, %l3
53130ld [%l3+4], %l6
53131st %l6, [%l3+4]
53132
53133P4929: !_PREFETCH [7] (Int)
53134sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
53135sub %i0, %i3, %i3
53136prefetch [%i3 + 4], 1
53137
53138P4930: !_MEMBAR (FP)
53139
53140P4931: !_BST [0] (maybe <- 0x418000f5) (FP)
53141wr %g0, 0xf0, %asi
53142! preparing store val #0, next val will be in f32
53143fmovs %f16, %f20
53144fadds %f16, %f17, %f16
53145! preparing store val #1, next val will be in f33
53146fmovs %f16, %f21
53147fadds %f16, %f17, %f16
53148! preparing store val #2, next val will be in f35
53149fmovd %f20, %f32
53150fmovs %f16, %f21
53151fadds %f16, %f17, %f16
53152fmovd %f20, %f34
53153membar #Sync
53154stda %f32, [%i0 + 0 ] %asi
53155
53156P4932: !_MEMBAR (FP)
53157membar #StoreLoad
53158
53159P4933: !_ST [0] (maybe <- 0x2000193) (Int)
53160stw %l4, [%i0 + 0 ]
53161add %l4, 1, %l4
53162
53163P4934: !_LD [18] (Int) (CBR)
53164sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
53165sub %i0, %i2, %i2
53166lduw [%i2 + 0], %o2
53167! move %o2(lower) -> %o2(upper)
53168sllx %o2, 32, %o2
53169
53170! cbranch
53171andcc %l0, 1, %g0
53172be,pt %xcc, TARGET4934
53173nop
53174RET4934:
53175
53176! lfsr step begin
53177srlx %l0, 1, %l7
53178xnor %l7, %l0, %l7
53179sllx %l7, 63, %l7
53180or %l7, %l0, %l0
53181srlx %l0, 1, %l0
53182
53183
53184P4935: !_LDD [5] (Int)
53185ldd [%i1 + 8], %l6
53186! move %l7(lower) -> %o2(lower)
53187or %l7, %o2, %o2
53188
53189P4936: !_ST_BINIT [6] (maybe <- 0x2000194) (Int) (LE)
53190wr %g0, 0xea, %asi
53191! Change single-word-level endianess (big endian <-> little endian)
53192sethi %hi(0xff00ff00), %l6
53193or %l6, %lo(0xff00ff00), %l6
53194and %l4, %l6, %l7
53195srl %l7, 8, %l7
53196sll %l4, 8, %l3
53197and %l3, %l6, %l3
53198or %l3, %l7, %l3
53199srl %l3, 16, %l7
53200sll %l3, 16, %l3
53201srl %l3, 0, %l3
53202or %l3, %l7, %l3
53203stwa %l3, [%i3 + 0] %asi
53204add %l4, 1, %l4
53205
53206P4937: !_MEMBAR (Int) (LE)
53207membar #StoreLoad
53208
53209P4938: !_ST [20] (maybe <- 0x2000195) (Int) (Branch target of P4224)
53210stw %l4, [%i2 + 12 ]
53211add %l4, 1, %l4
53212ba P4939
53213nop
53214
53215TARGET4224:
53216ba RET4224
53217nop
53218
53219
53220P4939: !_PREFETCH [12] (Int) (LE) (Branch target of P4356)
53221wr %g0, 0x88, %asi
53222sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
53223add %i0, %i3, %i3
53224prefetcha [%i3 + 0] %asi, 22
53225ba P4940
53226nop
53227
53228TARGET4356:
53229ba RET4356
53230nop
53231
53232
53233P4940: !_DWST [3] (maybe <- 0x2000196) (Int)
53234sllx %l4, 32, %l7
53235add %l4, 1, %l4
53236or %l7, %l4, %l7
53237stx %l7, [%i1 + 0]
53238add %l4, 1, %l4
53239
53240P4941: !_CASX [17] (maybe <- 0x2000198) (Int)
53241sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
53242sub %i0, %i2, %i2
53243add %i2, 8, %l7
53244ldx [%l7], %o3
53245! move %o3(upper) -> %o3(upper)
53246! move %o3(lower) -> %o3(lower)
53247mov %o3, %l6
53248mov %l4, %o4
53249casx [%l7], %l6, %o4
53250! move %o4(upper) -> %o4(upper)
53251! move %o4(lower) -> %o4(lower)
53252!---- flushing int results buffer----
53253mov %o0, %l5
53254mov %o1, %l5
53255mov %o2, %l5
53256mov %o3, %l5
53257mov %o4, %l5
53258add %l4, 1, %l4
53259
53260P4942: !_REPLACEMENT [9] (Int)
53261sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
53262add %i0, %i3, %i3
53263sethi %hi(0x20000), %l6
53264ld [%i3+0], %o5
53265st %o5, [%i3+0]
53266add %i3, %l6, %l7
53267ld [%l7+0], %o5
53268st %o5, [%l7+0]
53269add %l7, %l6, %l7
53270ld [%l7+0], %o5
53271st %o5, [%l7+0]
53272add %l7, %l6, %l7
53273ld [%l7+0], %o5
53274st %o5, [%l7+0]
53275add %l7, %l6, %l7
53276ld [%l7+0], %o5
53277st %o5, [%l7+0]
53278add %l7, %l6, %l7
53279ld [%l7+0], %o5
53280st %o5, [%l7+0]
53281add %l7, %l6, %l7
53282ld [%l7+0], %o5
53283st %o5, [%l7+0]
53284add %l7, %l6, %l7
53285ld [%l7+0], %o5
53286st %o5, [%l7+0]
53287
53288P4943: !_LDD [22] (Int)
53289sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
53290add %i0, %i2, %i2
53291ldd [%i2 + 0], %l6
53292! move %l6(lower) -> %o0(upper)
53293sllx %l6, 32, %o0
53294! move %l7(lower) -> %o0(lower)
53295or %l7, %o0, %o0
53296
53297P4944: !_ST_BINIT [5] (maybe <- 0x2000199) (Int)
53298wr %g0, 0xe2, %asi
53299stwa %l4, [%i1 + 12] %asi
53300add %l4, 1, %l4
53301
53302P4945: !_MEMBAR (Int)
53303membar #StoreLoad
53304
53305P4946: !_BLD [11] (FP) (CBR)
53306wr %g0, 0xf0, %asi
53307sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
53308sub %i0, %i3, %i3
53309ldda [%i3 + 0] %asi, %f32
53310membar #Sync
53311! 3 addresses covered
53312fmovd %f32, %f14
53313!---- flushing fp results buffer to %f30 ----
53314fmovd %f0, %f30
53315fmovd %f2, %f30
53316fmovd %f4, %f30
53317fmovd %f6, %f30
53318fmovd %f8, %f30
53319fmovd %f10, %f30
53320fmovd %f12, %f30
53321fmovd %f14, %f30
53322!--
53323fmovd %f34, %f18
53324fmovs %f19, %f0
53325
53326! cbranch
53327andcc %l0, 1, %g0
53328be,pt %xcc, TARGET4946
53329nop
53330RET4946:
53331
53332! lfsr step begin
53333srlx %l0, 1, %o5
53334xnor %o5, %l0, %o5
53335sllx %o5, 63, %o5
53336or %o5, %l0, %l0
53337srlx %l0, 1, %l0
53338
53339
53340P4947: !_MEMBAR (FP)
53341
53342P4948: !_DWLD [21] (Int)
53343ldx [%i2 + 0], %o1
53344! move %o1(upper) -> %o1(upper)
53345! move %o1(lower) -> %o1(lower)
53346
53347P4949: !_SWAP [8] (maybe <- 0x200019a) (Int)
53348sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
53349sub %i0, %i2, %i2
53350mov %l4, %o2
53351swap [%i2 + 12], %o2
53352! move %o2(lower) -> %o2(upper)
53353sllx %o2, 32, %o2
53354add %l4, 1, %l4
53355
53356P4950: !_DWLD [16] (Int)
53357sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
53358sub %i0, %i3, %i3
53359ldx [%i3 + 0], %l7
53360! move %l7(upper) -> %o2(lower)
53361srlx %l7, 32, %l6
53362or %l6, %o2, %o2
53363! move %l7(lower) -> %o3(upper)
53364sllx %l7, 32, %o3
53365
53366P4951: !_LDD [7] (Int) (LE)
53367wr %g0, 0x88, %asi
53368ldda [%i2 + 0] %asi, %l6
53369! move %l6(lower) -> %o3(lower)
53370or %l6, %o3, %o3
53371! move %l7(lower) -> %o4(upper)
53372sllx %l7, 32, %o4
53373
53374P4952: !_DWST_BINIT [12] (maybe <- 0x200019b) (Int)
53375wr %g0, 0xe2, %asi
53376sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
53377add %i0, %i2, %i2
53378sllx %l4, 32, %l3
53379add %l4, 1, %l4
53380or %l3, %l4, %l3
53381stxa %l3, [%i2 + 0] %asi
53382add %l4, 1, %l4
53383
53384P4953: !_MEMBAR (Int)
53385membar #StoreLoad
53386
53387P4954: !_LDD [5] (Int)
53388ldd [%i1 + 8], %l6
53389! move %l7(lower) -> %o4(lower)
53390or %l7, %o4, %o4
53391!---- flushing int results buffer----
53392mov %o0, %l5
53393mov %o1, %l5
53394mov %o2, %l5
53395mov %o3, %l5
53396mov %o4, %l5
53397
53398P4955: !_DWST_BINIT [20] (maybe <- 0x200019d) (Int) (Branch target of P4874)
53399wr %g0, 0xe2, %asi
53400sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
53401sub %i0, %i3, %i3
53402mov %l4, %l3
53403stxa %l3, [%i3 + 8] %asi
53404add %l4, 1, %l4
53405ba P4956
53406nop
53407
53408TARGET4874:
53409ba RET4874
53410nop
53411
53412
53413P4956: !_MEMBAR (Int) (Branch target of P4802)
53414membar #StoreLoad
53415ba P4957
53416nop
53417
53418TARGET4802:
53419ba RET4802
53420nop
53421
53422
53423P4957: !_ST_BINIT [7] (maybe <- 0x200019e) (Int)
53424wr %g0, 0xe2, %asi
53425sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
53426sub %i0, %i2, %i2
53427stwa %l4, [%i2 + 4] %asi
53428add %l4, 1, %l4
53429
53430P4958: !_MEMBAR (Int)
53431membar #StoreLoad
53432
53433P4959: !_DWST [11] (maybe <- 0x200019f) (Int)
53434sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
53435sub %i0, %i3, %i3
53436mov %l4, %l7
53437stx %l7, [%i3 + 8]
53438add %l4, 1, %l4
53439
53440P4960: !_SWAP [14] (maybe <- 0x20001a0) (Int)
53441sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
53442add %i0, %i2, %i2
53443mov %l4, %o0
53444swap [%i2 + 12], %o0
53445! move %o0(lower) -> %o0(upper)
53446sllx %o0, 32, %o0
53447add %l4, 1, %l4
53448
53449P4961: !_MEMBAR (FP)
53450membar #StoreLoad
53451
53452P4962: !_BLD [9] (FP)
53453wr %g0, 0xf0, %asi
53454ldda [%i3 + 0] %asi, %f32
53455membar #Sync
53456! 3 addresses covered
53457fmovd %f32, %f18
53458fmovs %f18, %f1
53459fmovs %f19, %f2
53460fmovd %f34, %f18
53461fmovs %f19, %f3
53462
53463P4963: !_MEMBAR (FP)
53464
53465P4964: !_LD [2] (Int)
53466lduw [%i0 + 12], %l6
53467! move %l6(lower) -> %o0(lower)
53468or %l6, %o0, %o0
53469
53470P4965: !_LD [0] (Int)
53471lduw [%i0 + 0], %o1
53472! move %o1(lower) -> %o1(upper)
53473sllx %o1, 32, %o1
53474
53475P4966: !_LDD [1] (Int)
53476ldd [%i0 + 0], %l6
53477! move %l6(lower) -> %o1(lower)
53478or %l6, %o1, %o1
53479! move %l7(lower) -> %o2(upper)
53480sllx %l7, 32, %o2
53481
53482P4967: !_MEMBAR (FP)
53483
53484P4968: !_BSTC [11] (maybe <- 0x418000f8) (FP)
53485wr %g0, 0xe0, %asi
53486! preparing store val #0, next val will be in f32
53487fmovs %f16, %f20
53488fadds %f16, %f17, %f16
53489! preparing store val #1, next val will be in f33
53490fmovs %f16, %f21
53491fadds %f16, %f17, %f16
53492! preparing store val #2, next val will be in f35
53493fmovd %f20, %f32
53494fmovs %f16, %f21
53495fadds %f16, %f17, %f16
53496fmovd %f20, %f34
53497membar #Sync
53498stda %f32, [%i3 + 0 ] %asi
53499
53500P4969: !_MEMBAR (FP)
53501
53502P4970: !_BST [13] (maybe <- 0x418000fb) (FP)
53503wr %g0, 0xf0, %asi
53504! preparing store val #0, next val will be in f32
53505fmovs %f16, %f20
53506fadds %f16, %f17, %f16
53507! preparing store val #1, next val will be in f33
53508fmovs %f16, %f21
53509fadds %f16, %f17, %f16
53510! preparing store val #2, next val will be in f35
53511fmovd %f20, %f32
53512fmovs %f16, %f21
53513fadds %f16, %f17, %f16
53514fmovd %f20, %f34
53515membar #Sync
53516stda %f32, [%i2 + 0 ] %asi
53517
53518P4971: !_MEMBAR (FP)
53519membar #StoreLoad
53520
53521P4972: !_DWST_BINIT [0] (maybe <- 0x20001a1) (Int)
53522wr %g0, 0xe2, %asi
53523sllx %l4, 32, %o5
53524add %l4, 1, %l4
53525or %o5, %l4, %o5
53526stxa %o5, [%i0 + 0] %asi
53527add %l4, 1, %l4
53528
53529P4973: !_MEMBAR (Int)
53530
53531P4974: !_BSTC [4] (maybe <- 0x418000fe) (FP)
53532wr %g0, 0xe0, %asi
53533! preparing store val #0, next val will be in f32
53534fmovs %f16, %f20
53535fadds %f16, %f17, %f16
53536! preparing store val #1, next val will be in f33
53537fmovs %f16, %f21
53538fadds %f16, %f17, %f16
53539! preparing store val #2, next val will be in f35
53540fmovd %f20, %f32
53541fmovs %f16, %f21
53542fadds %f16, %f17, %f16
53543fmovd %f20, %f34
53544membar #Sync
53545stda %f32, [%i1 + 0 ] %asi
53546
53547P4975: !_MEMBAR (FP)
53548
53549P4976: !_BSTC [23] (maybe <- 0x41800101) (FP)
53550wr %g0, 0xe0, %asi
53551sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
53552add %i0, %i3, %i3
53553! preparing store val #0, next val will be in f32
53554fmovs %f16, %f20
53555fadds %f16, %f17, %f16
53556! preparing store val #1, next val will be in f33
53557fmovs %f16, %f21
53558fadds %f16, %f17, %f16
53559! preparing store val #2, next val will be in f35
53560fmovd %f20, %f32
53561fmovs %f16, %f21
53562fadds %f16, %f17, %f16
53563fmovd %f20, %f34
53564membar #Sync
53565stda %f32, [%i3 + 0 ] %asi
53566
53567P4977: !_MEMBAR (FP) (Branch target of P4172)
53568membar #StoreLoad
53569ba P4978
53570nop
53571
53572TARGET4172:
53573ba RET4172
53574nop
53575
53576
53577P4978: !_LD [12] (Int)
53578lduw [%i2 + 0], %l6
53579! move %l6(lower) -> %o2(lower)
53580or %l6, %o2, %o2
53581
53582P4979: !_REPLACEMENT [18] (Int)
53583sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
53584add %i0, %i2, %i2
53585sethi %hi(0x20000), %l7
53586ld [%i2+0], %l3
53587st %l3, [%i2+0]
53588add %i2, %l7, %o5
53589ld [%o5+0], %l3
53590st %l3, [%o5+0]
53591add %o5, %l7, %o5
53592ld [%o5+0], %l3
53593st %l3, [%o5+0]
53594add %o5, %l7, %o5
53595ld [%o5+0], %l3
53596st %l3, [%o5+0]
53597add %o5, %l7, %o5
53598ld [%o5+0], %l3
53599st %l3, [%o5+0]
53600add %o5, %l7, %o5
53601ld [%o5+0], %l3
53602st %l3, [%o5+0]
53603add %o5, %l7, %o5
53604ld [%o5+0], %l3
53605st %l3, [%o5+0]
53606add %o5, %l7, %o5
53607ld [%o5+0], %l3
53608st %l3, [%o5+0]
53609
53610P4980: !_ST [1] (maybe <- 0x20001a3) (Int)
53611stw %l4, [%i0 + 4 ]
53612add %l4, 1, %l4
53613
53614P4981: !_MEMBAR (FP)
53615membar #StoreLoad
53616
53617P4982: !_BLD [11] (FP)
53618wr %g0, 0xf0, %asi
53619sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
53620sub %i0, %i3, %i3
53621ldda [%i3 + 0] %asi, %f32
53622membar #Sync
53623! 3 addresses covered
53624fmovd %f32, %f4
53625fmovd %f34, %f18
53626fmovs %f19, %f6
53627
53628P4983: !_MEMBAR (FP)
53629
53630P4984: !_PREFETCH [9] (Int)
53631prefetch [%i3 + 0], 20
53632
53633P4985: !_CASX [6] (maybe <- 0x20001a4) (Int)
53634sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
53635sub %i0, %i2, %i2
53636ldx [%i2], %o3
53637! move %o3(upper) -> %o3(upper)
53638! move %o3(lower) -> %o3(lower)
53639mov %o3, %l3
53640sllx %l4, 32, %o4
53641add %l4, 1, %l4
53642or %l4, %o4, %o4
53643casx [%i2], %l3, %o4
53644! move %o4(upper) -> %o4(upper)
53645! move %o4(lower) -> %o4(lower)
53646!---- flushing int results buffer----
53647mov %o0, %l5
53648mov %o1, %l5
53649mov %o2, %l5
53650mov %o3, %l5
53651mov %o4, %l5
53652add %l4, 1, %l4
53653
53654P4986: !_LD [10] (FP)
53655ld [%i3 + 4], %f7
53656! 1 addresses covered
53657
53658P4987: !_ST_BINIT [12] (maybe <- 0x20001a6) (Int)
53659wr %g0, 0xe2, %asi
53660sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
53661add %i0, %i3, %i3
53662stwa %l4, [%i3 + 0] %asi
53663add %l4, 1, %l4
53664
53665P4988: !_MEMBAR (Int)
53666membar #StoreLoad
53667
53668P4989: !_CAS [14] (maybe <- 0x20001a7) (Int)
53669add %i3, 12, %l3
53670lduw [%l3], %o0
53671mov %o0, %o5
53672! move %o5(lower) -> %o0(upper)
53673sllx %o5, 32, %o0
53674mov %l4, %l7
53675cas [%l3], %o5, %l7
53676! move %l7(lower) -> %o0(lower)
53677srl %l7, 0, %o5
53678or %o5, %o0, %o0
53679add %l4, 1, %l4
53680
53681P4990: !_LDD [12] (Int)
53682ldd [%i3 + 0], %l6
53683! move %l6(lower) -> %o1(upper)
53684sllx %l6, 32, %o1
53685! move %l7(lower) -> %o1(lower)
53686or %l7, %o1, %o1
53687
53688P4991: !_SWAP [2] (maybe <- 0x20001a8) (Int)
53689mov %l4, %o2
53690swap [%i0 + 12], %o2
53691! move %o2(lower) -> %o2(upper)
53692sllx %o2, 32, %o2
53693add %l4, 1, %l4
53694
53695P4992: !_SWAP [8] (maybe <- 0x20001a9) (Int)
53696mov %l4, %l6
53697swap [%i2 + 12], %l6
53698! move %l6(lower) -> %o2(lower)
53699srl %l6, 0, %o5
53700or %o5, %o2, %o2
53701add %l4, 1, %l4
53702
53703P4993: !_CAS [18] (maybe <- 0x20001aa) (Int)
53704sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
53705sub %i0, %i2, %i2
53706lduw [%i2], %o3
53707mov %o3, %l7
53708! move %l7(lower) -> %o3(upper)
53709sllx %l7, 32, %o3
53710mov %l4, %l6
53711cas [%i2], %l7, %l6
53712! move %l6(lower) -> %o3(lower)
53713srl %l6, 0, %l7
53714or %l7, %o3, %o3
53715add %l4, 1, %l4
53716
53717P4994: !_CAS [3] (maybe <- 0x20001ab) (Int)
53718lduw [%i1], %o4
53719mov %o4, %l7
53720! move %l7(lower) -> %o4(upper)
53721sllx %l7, 32, %o4
53722mov %l4, %l6
53723cas [%i1], %l7, %l6
53724! move %l6(lower) -> %o4(lower)
53725srl %l6, 0, %l7
53726or %l7, %o4, %o4
53727!---- flushing int results buffer----
53728mov %o0, %l5
53729mov %o1, %l5
53730mov %o2, %l5
53731mov %o3, %l5
53732mov %o4, %l5
53733add %l4, 1, %l4
53734
53735P4995: !_ST_BINIT [2] (maybe <- 0x20001ac) (Int) (CBR)
53736wr %g0, 0xe2, %asi
53737stwa %l4, [%i0 + 12] %asi
53738add %l4, 1, %l4
53739
53740! cbranch
53741andcc %l0, 1, %g0
53742be,pt %xcc, TARGET4995
53743nop
53744RET4995:
53745
53746! lfsr step begin
53747srlx %l0, 1, %l6
53748xnor %l6, %l0, %l6
53749sllx %l6, 63, %l6
53750or %l6, %l0, %l0
53751srlx %l0, 1, %l0
53752
53753
53754P4996: !_MEMBAR (Int)
53755membar #StoreLoad
53756
53757P4997: !_DWST_BINIT [0] (maybe <- 0x20001ad) (Int)
53758wr %g0, 0xe2, %asi
53759sllx %l4, 32, %l7
53760add %l4, 1, %l4
53761or %l7, %l4, %l7
53762stxa %l7, [%i0 + 0] %asi
53763add %l4, 1, %l4
53764
53765P4998: !_MEMBAR (Int)
53766membar #StoreLoad
53767
53768P4999: !_PREFETCH [17] (Int)
53769sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
53770sub %i0, %i3, %i3
53771prefetch [%i3 + 12], 4
53772
53773P5000: !_CAS [14] (maybe <- 0x20001af) (Int)
53774sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
53775add %i0, %i2, %i2
53776add %i2, 12, %l7
53777lduw [%l7], %o0
53778mov %o0, %l6
53779! move %l6(lower) -> %o0(upper)
53780sllx %l6, 32, %o0
53781mov %l4, %l3
53782cas [%l7], %l6, %l3
53783! move %l3(lower) -> %o0(lower)
53784srl %l3, 0, %l6
53785or %l6, %o0, %o0
53786add %l4, 1, %l4
53787
53788P5001: !_MEMBAR (FP)
53789membar #StoreLoad
53790
53791P5002: !_BLD [14] (FP)
53792wr %g0, 0xf0, %asi
53793ldda [%i2 + 0] %asi, %f32
53794membar #Sync
53795! 3 addresses covered
53796fmovd %f32, %f8
53797fmovd %f34, %f18
53798fmovs %f19, %f10
53799
53800P5003: !_MEMBAR (FP) (Branch target of P4347)
53801ba P5004
53802nop
53803
53804TARGET4347:
53805ba RET4347
53806nop
53807
53808
53809P5004: !_LD [0] (Int)
53810lduw [%i0 + 0], %o1
53811! move %o1(lower) -> %o1(upper)
53812sllx %o1, 32, %o1
53813
53814P5005: !_MEMBAR (FP)
53815membar #StoreLoad
53816
53817P5006: !_BLD [7] (FP)
53818wr %g0, 0xf0, %asi
53819sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
53820sub %i0, %i3, %i3
53821ldda [%i3 + 0] %asi, %f32
53822membar #Sync
53823! 3 addresses covered
53824fmovd %f32, %f18
53825fmovs %f18, %f11
53826fmovs %f19, %f12
53827fmovd %f34, %f18
53828fmovs %f19, %f13
53829
53830P5007: !_MEMBAR (FP)
53831
53832P5008: !_DWST [0] (maybe <- 0x20001b0) (Int)
53833sllx %l4, 32, %o5
53834add %l4, 1, %l4
53835or %o5, %l4, %o5
53836stx %o5, [%i0 + 0]
53837add %l4, 1, %l4
53838
53839P5009: !_MEMBAR (FP)
53840
53841P5010: !_BST [20] (maybe <- 0x41800104) (FP)
53842wr %g0, 0xf0, %asi
53843sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
53844sub %i0, %i2, %i2
53845! preparing store val #0, next val will be in f32
53846fmovs %f16, %f20
53847fadds %f16, %f17, %f16
53848! preparing store val #1, next val will be in f33
53849fmovs %f16, %f21
53850fadds %f16, %f17, %f16
53851! preparing store val #2, next val will be in f35
53852fmovd %f20, %f32
53853fmovs %f16, %f21
53854fadds %f16, %f17, %f16
53855fmovd %f20, %f34
53856membar #Sync
53857stda %f32, [%i2 + 0 ] %asi
53858
53859P5011: !_MEMBAR (FP)
53860membar #StoreLoad
53861
53862P5012: !_LD [3] (Int) (Loop exit)
53863lduw [%i1 + 0], %l7
53864! move %l7(lower) -> %o1(lower)
53865or %l7, %o1, %o1
53866!---- flushing int results buffer----
53867mov %o0, %l5
53868mov %o1, %l5
53869!---- flushing fp results buffer to %f30 ----
53870fmovd %f0, %f30
53871fmovd %f2, %f30
53872fmovd %f4, %f30
53873fmovd %f6, %f30
53874fmovd %f8, %f30
53875fmovd %f10, %f30
53876fmovd %f12, %f30
53877!--
53878
53879sethi %hi(0x600000), %o5
53880add %i1, %o5, %i1
53881!-- End Aliased access: base register for region 1 (%i1) restored
53882loop_exit_4_0:
53883sub %l2, 1, %l2
53884cmp %l2, 0
53885bg loop_entry_4_0
53886nop
53887
53888P5013: !_MEMBAR (Int)
53889membar #StoreLoad
53890
53891END_NODES4: ! Test instruction sequence for CPU 4 ends
53892sethi %hi(0xdead0e0f), %l3
53893or %l3, %lo(0xdead0e0f), %l3
53894! move %l3(lower) -> %o0(upper)
53895sllx %l3, 32, %o0
53896sethi %hi(0xdead0e0f), %l3
53897or %l3, %lo(0xdead0e0f), %l3
53898stw %l3, [%i5]
53899ld [%i5], %f0
53900!---- flushing int results buffer----
53901mov %o0, %l5
53902!---- flushing fp results buffer to %f30 ----
53903fmovs %f0, %f30
53904!--
53905
53906restore
53907retl
53908nop
53909!-----------------
53910
53911! register usage:
53912! %i0 %i1 : base registers for first 2 regions
53913! %i2 %i3 : cache registers for 8 regions
53914! %i4 fixed pointer to per-cpu results area
53915! %l1 moving pointer to per-cpu FP results area
53916! %o7 moving pointer to per-cpu integer results area
53917! %i5 pointer to per-cpu private area
53918! %l0 holds lfsr, used as source of random bits
53919! %l2 loop count register
53920! %f16 running counter for unique fp store values
53921! %f17 holds increment value for fp counter
53922! %l4 running counter for unique integer store values (increment value is always 1)
53923! %l5 move-to register for load values (simulation only)
53924! %f30 move-to register for FP values (simulation only)
53925! %i4 holds the instructions count which is used for interrupt ordering
53926! %i4 holds the thread_id (OBP only)
53927! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage
53928! %l3 %l6 %l7 %o5 : 4 temporary registers
53929! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
53930! %f0-f15 FP results buffer registers
53931! %f32-f47 FP block load/store registers
53932
53933func5:
53934! instruction sequence begins
53935save %sp, -192, %sp
53936
53937! Force %i0-%i3 to be 64-byte aligned
53938add %i0, 63, %i0
53939andn %i0, 63, %i0
53940
53941add %i1, 63, %i1
53942andn %i1, 63, %i1
53943
53944add %i2, 63, %i2
53945andn %i2, 63, %i2
53946
53947add %i3, 63, %i3
53948andn %i3, 63, %i3
53949
53950add %i4, 63, %i4
53951andn %i4, 63, %i4
53952
53953add %i5, 63, %i5
53954andn %i5, 63, %i5
53955
53956
53957! Initialize pointer to FP load results area
53958mov %i4, %l1
53959
53960! Initialize pointer to integer load results area
53961sethi %hi(0x80000), %o7
53962or %o7, %lo(0x80000), %o7
53963add %o7, %l1, %o7
53964
53965! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info
53966mov 0x0, %i4
53967
53968! Initialize %f0-%f62 to 0xdeadbee0deadbee1
53969sethi %hi(0xdeadbee0), %o5
53970or %o5, %lo(0xdeadbee0), %o5
53971stw %o5, [%i5]
53972sethi %hi(0xdeadbee1), %o5
53973or %o5, %lo(0xdeadbee1), %o5
53974stw %o5, [%i5+4]
53975ldd [%i5], %f0
53976fmovd %f0, %f2
53977fmovd %f0, %f4
53978fmovd %f0, %f6
53979fmovd %f0, %f8
53980fmovd %f0, %f10
53981fmovd %f0, %f12
53982fmovd %f0, %f14
53983fmovd %f0, %f16
53984fmovd %f0, %f18
53985fmovd %f0, %f20
53986fmovd %f0, %f22
53987fmovd %f0, %f24
53988fmovd %f0, %f26
53989fmovd %f0, %f28
53990fmovd %f0, %f30
53991fmovd %f0, %f32
53992fmovd %f0, %f34
53993fmovd %f0, %f36
53994fmovd %f0, %f38
53995fmovd %f0, %f40
53996fmovd %f0, %f42
53997fmovd %f0, %f44
53998fmovd %f0, %f46
53999fmovd %f0, %f48
54000fmovd %f0, %f50
54001fmovd %f0, %f52
54002fmovd %f0, %f54
54003fmovd %f0, %f56
54004fmovd %f0, %f58
54005fmovd %f0, %f60
54006fmovd %f0, %f62
54007
54008! Signature for extract_loads script to start extracting load values for this stream
54009sethi %hi(0x05deade1), %o5
54010or %o5, %lo(0x05deade1), %o5
54011stw %o5, [%i5]
54012ld [%i5], %f16
54013
54014! Initialize running integer counter in register %l4
54015sethi %hi(0x2800001), %l4
54016or %l4, %lo(0x2800001), %l4
54017
54018! Initialize running FP counter in register %f16
54019sethi %hi(0x42000001), %o5
54020or %o5, %lo(0x42000001), %o5
54021stw %o5, [%i5]
54022ld [%i5], %f16
54023
54024! Initialize FP counter increment value in register %f17 (constant)
54025sethi %hi(0x36800000), %o5
54026or %o5, %lo(0x36800000), %o5
54027stw %o5, [%i5]
54028ld [%i5], %f17
54029
54030! Initialize LFSR to 0x23e4^4
54031sethi %hi(0x23e4), %l0
54032or %l0, %lo(0x23e4), %l0
54033mulx %l0, %l0, %l0
54034mulx %l0, %l0, %l0
54035
54036BEGIN_NODES5: ! Test instruction sequence for ISTREAM 5 begins
54037
54038P5014: !_ST [7] (maybe <- 0x2800001) (Int) (Loop entry) (CBR) (Branch target of P5201)
54039sethi %hi(0x1), %l2
54040or %l2, %lo(0x1), %l2
54041loop_entry_5_0:
54042sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
54043sub %i0, %i3, %i3
54044stw %l4, [%i3 + 4 ]
54045add %l4, 1, %l4
54046
54047! cbranch
54048andcc %l0, 1, %g0
54049be,pn %xcc, TARGET5014
54050nop
54051RET5014:
54052
54053! lfsr step begin
54054srlx %l0, 1, %o5
54055xnor %o5, %l0, %o5
54056sllx %o5, 63, %o5
54057or %o5, %l0, %l0
54058srlx %l0, 1, %l0
54059
54060ba P5015
54061nop
54062
54063TARGET5201:
54064ba RET5201
54065nop
54066
54067
54068P5015: !_REPLACEMENT [5] (Int)
54069sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
54070sub %i0, %i2, %i2
54071sethi %hi(0x20000), %l3
54072ld [%i2+12], %l7
54073st %l7, [%i2+12]
54074add %i2, %l3, %l6
54075ld [%l6+12], %l7
54076st %l7, [%l6+12]
54077add %l6, %l3, %l6
54078ld [%l6+12], %l7
54079st %l7, [%l6+12]
54080add %l6, %l3, %l6
54081ld [%l6+12], %l7
54082st %l7, [%l6+12]
54083add %l6, %l3, %l6
54084ld [%l6+12], %l7
54085st %l7, [%l6+12]
54086add %l6, %l3, %l6
54087ld [%l6+12], %l7
54088st %l7, [%l6+12]
54089add %l6, %l3, %l6
54090ld [%l6+12], %l7
54091st %l7, [%l6+12]
54092add %l6, %l3, %l6
54093ld [%l6+12], %l7
54094st %l7, [%l6+12]
54095
54096P5016: !_SWAP [9] (maybe <- 0x2800002) (Int) (CBR) (Branch target of P5795)
54097sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
54098sub %i0, %i3, %i3
54099mov %l4, %o0
54100swap [%i3 + 0], %o0
54101! move %o0(lower) -> %o0(upper)
54102sllx %o0, 32, %o0
54103add %l4, 1, %l4
54104
54105! cbranch
54106andcc %l0, 1, %g0
54107be,pt %xcc, TARGET5016
54108nop
54109RET5016:
54110
54111! lfsr step begin
54112srlx %l0, 1, %l7
54113xnor %l7, %l0, %l7
54114sllx %l7, 63, %l7
54115or %l7, %l0, %l0
54116srlx %l0, 1, %l0
54117
54118ba P5017
54119nop
54120
54121TARGET5795:
54122ba RET5795
54123nop
54124
54125
54126P5017: !_DWLD [17] (Int)
54127sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
54128sub %i0, %i2, %i2
54129ldx [%i2 + 8], %l3
54130! move %l3(lower) -> %o0(lower)
54131srl %l3, 0, %o5
54132or %o5, %o0, %o0
54133
54134P5018: !_MEMBAR (FP)
54135
54136P5019: !_BST [7] (maybe <- 0x42000001) (FP)
54137wr %g0, 0xf0, %asi
54138sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
54139sub %i0, %i3, %i3
54140! preparing store val #0, next val will be in f32
54141fmovs %f16, %f20
54142fadds %f16, %f17, %f16
54143! preparing store val #1, next val will be in f33
54144fmovs %f16, %f21
54145fadds %f16, %f17, %f16
54146! preparing store val #2, next val will be in f35
54147fmovd %f20, %f32
54148fmovs %f16, %f21
54149fadds %f16, %f17, %f16
54150fmovd %f20, %f34
54151membar #Sync
54152stda %f32, [%i3 + 0 ] %asi
54153
54154P5020: !_MEMBAR (FP)
54155membar #StoreLoad
54156
54157P5021: !_SWAP [10] (maybe <- 0x2800003) (Int)
54158sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
54159sub %i0, %i2, %i2
54160mov %l4, %o1
54161swap [%i2 + 4], %o1
54162! move %o1(lower) -> %o1(upper)
54163sllx %o1, 32, %o1
54164add %l4, 1, %l4
54165
54166P5022: !_REPLACEMENT [17] (Int)
54167sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
54168sub %i0, %i3, %i3
54169sethi %hi(0x20000), %o5
54170ld [%i3+12], %l6
54171st %l6, [%i3+12]
54172add %i3, %o5, %l3
54173ld [%l3+12], %l6
54174st %l6, [%l3+12]
54175add %l3, %o5, %l3
54176ld [%l3+12], %l6
54177st %l6, [%l3+12]
54178add %l3, %o5, %l3
54179ld [%l3+12], %l6
54180st %l6, [%l3+12]
54181add %l3, %o5, %l3
54182ld [%l3+12], %l6
54183st %l6, [%l3+12]
54184add %l3, %o5, %l3
54185ld [%l3+12], %l6
54186st %l6, [%l3+12]
54187add %l3, %o5, %l3
54188ld [%l3+12], %l6
54189st %l6, [%l3+12]
54190add %l3, %o5, %l3
54191ld [%l3+12], %l6
54192st %l6, [%l3+12]
54193
54194P5023: !_DWST [19] (maybe <- 0x2800004) (Int) (CBR)
54195sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
54196sub %i0, %i2, %i2
54197sllx %l4, 32, %l7
54198add %l4, 1, %l4
54199or %l7, %l4, %l7
54200stx %l7, [%i2 + 0]
54201add %l4, 1, %l4
54202
54203! cbranch
54204andcc %l0, 1, %g0
54205be,pn %xcc, TARGET5023
54206nop
54207RET5023:
54208
54209! lfsr step begin
54210srlx %l0, 1, %l6
54211xnor %l6, %l0, %l6
54212sllx %l6, 63, %l6
54213or %l6, %l0, %l0
54214srlx %l0, 1, %l0
54215
54216
54217P5024: !_DWST [10] (maybe <- 0x2800006) (Int)
54218sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
54219sub %i0, %i3, %i3
54220sllx %l4, 32, %l7
54221add %l4, 1, %l4
54222or %l7, %l4, %l7
54223stx %l7, [%i3 + 0]
54224add %l4, 1, %l4
54225
54226P5025: !_ST_BINIT [0] (maybe <- 0x2800008) (Int)
54227wr %g0, 0xe2, %asi
54228stwa %l4, [%i0 + 0] %asi
54229add %l4, 1, %l4
54230
54231P5026: !_MEMBAR (Int)
54232membar #StoreLoad
54233
54234P5027: !_CAS [5] (maybe <- 0x2800009) (Int)
54235add %i1, 12, %l6
54236lduw [%l6], %o5
54237mov %o5, %l3
54238! move %l3(lower) -> %o1(lower)
54239or %l3, %o1, %o1
54240mov %l4, %o2
54241cas [%l6], %l3, %o2
54242! move %o2(lower) -> %o2(upper)
54243sllx %o2, 32, %o2
54244add %l4, 1, %l4
54245
54246P5028: !_DWST [12] (maybe <- 0x280000a) (Int)
54247sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
54248add %i0, %i2, %i2
54249sllx %l4, 32, %l3
54250add %l4, 1, %l4
54251or %l3, %l4, %l3
54252stx %l3, [%i2 + 0]
54253add %l4, 1, %l4
54254
54255P5029: !_DWST [2] (maybe <- 0x280000c) (Int)
54256mov %l4, %o5
54257stx %o5, [%i0 + 8]
54258add %l4, 1, %l4
54259
54260P5030: !_ST_BINIT [18] (maybe <- 0x280000d) (Int)
54261wr %g0, 0xe2, %asi
54262sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
54263sub %i0, %i3, %i3
54264stwa %l4, [%i3 + 0] %asi
54265add %l4, 1, %l4
54266
54267P5031: !_MEMBAR (Int)
54268membar #StoreLoad
54269
54270P5032: !_ST [9] (maybe <- 0x280000e) (Int)
54271sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
54272sub %i0, %i2, %i2
54273stw %l4, [%i2 + 0 ]
54274add %l4, 1, %l4
54275
54276P5033: !_LDD [16] (Int)
54277sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
54278sub %i0, %i3, %i3
54279ldd [%i3 + 0], %l6
54280! move %l6(lower) -> %o2(lower)
54281or %l6, %o2, %o2
54282! move %l7(lower) -> %o3(upper)
54283sllx %l7, 32, %o3
54284
54285P5034: !_ST [3] (maybe <- 0x280000f) (Int)
54286stw %l4, [%i1 + 0 ]
54287add %l4, 1, %l4
54288
54289P5035: !_ST [0] (maybe <- 0x42000004) (FP)
54290! preparing store val #0, next val will be in f20
54291fmovs %f16, %f20
54292fadds %f16, %f17, %f16
54293st %f20, [%i0 + 0 ]
54294
54295P5036: !_MEMBAR (FP)
54296
54297P5037: !_BST [21] (maybe <- 0x42000005) (FP)
54298wr %g0, 0xf0, %asi
54299sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
54300add %i0, %i2, %i2
54301! preparing store val #0, next val will be in f32
54302fmovs %f16, %f20
54303fadds %f16, %f17, %f16
54304! preparing store val #1, next val will be in f33
54305fmovs %f16, %f21
54306fadds %f16, %f17, %f16
54307! preparing store val #2, next val will be in f35
54308fmovd %f20, %f32
54309fmovs %f16, %f21
54310fadds %f16, %f17, %f16
54311fmovd %f20, %f34
54312membar #Sync
54313stda %f32, [%i2 + 0 ] %asi
54314
54315P5038: !_MEMBAR (FP)
54316membar #StoreLoad
54317
54318P5039: !_LDD [16] (Int) (LE)
54319wr %g0, 0x88, %asi
54320ldda [%i3 + 0] %asi, %l6
54321! move %l6(lower) -> %o3(lower)
54322or %l6, %o3, %o3
54323! move %l7(lower) -> %o4(upper)
54324sllx %l7, 32, %o4
54325
54326P5040: !_DWST [9] (maybe <- 0x2800010) (Int)
54327sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
54328sub %i0, %i3, %i3
54329sllx %l4, 32, %l3
54330add %l4, 1, %l4
54331or %l3, %l4, %l3
54332stx %l3, [%i3 + 0]
54333add %l4, 1, %l4
54334
54335P5041: !_SWAP [7] (maybe <- 0x2800012) (Int)
54336sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
54337sub %i0, %i2, %i2
54338mov %l4, %l6
54339swap [%i2 + 4], %l6
54340! move %l6(lower) -> %o4(lower)
54341srl %l6, 0, %o5
54342or %o5, %o4, %o4
54343!---- flushing int results buffer----
54344mov %o0, %l5
54345mov %o1, %l5
54346mov %o2, %l5
54347mov %o3, %l5
54348mov %o4, %l5
54349add %l4, 1, %l4
54350
54351P5042: !_LD [6] (Int)
54352lduw [%i2 + 0], %o0
54353! move %o0(lower) -> %o0(upper)
54354sllx %o0, 32, %o0
54355
54356P5043: !_DWLD [4] (Int)
54357ldx [%i1 + 0], %l6
54358! move %l6(upper) -> %o0(lower)
54359srlx %l6, 32, %l3
54360or %l3, %o0, %o0
54361! move %l6(lower) -> %o1(upper)
54362sllx %l6, 32, %o1
54363
54364P5044: !_MEMBAR (FP)
54365membar #StoreLoad
54366
54367P5045: !_BLD [17] (FP)
54368wr %g0, 0xf0, %asi
54369sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
54370sub %i0, %i3, %i3
54371ldda [%i3 + 0] %asi, %f0
54372membar #Sync
54373! 3 addresses covered
54374fmovs %f3, %f2
54375
54376P5046: !_MEMBAR (FP) (Branch target of P5239)
54377ba P5047
54378nop
54379
54380TARGET5239:
54381ba RET5239
54382nop
54383
54384
54385P5047: !_REPLACEMENT [17] (Int)
54386sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
54387sub %i0, %i2, %i2
54388sethi %hi(0x20000), %l7
54389ld [%i2+12], %l3
54390st %l3, [%i2+12]
54391add %i2, %l7, %o5
54392ld [%o5+12], %l3
54393st %l3, [%o5+12]
54394add %o5, %l7, %o5
54395ld [%o5+12], %l3
54396st %l3, [%o5+12]
54397add %o5, %l7, %o5
54398ld [%o5+12], %l3
54399st %l3, [%o5+12]
54400add %o5, %l7, %o5
54401ld [%o5+12], %l3
54402st %l3, [%o5+12]
54403add %o5, %l7, %o5
54404ld [%o5+12], %l3
54405st %l3, [%o5+12]
54406add %o5, %l7, %o5
54407ld [%o5+12], %l3
54408st %l3, [%o5+12]
54409add %o5, %l7, %o5
54410ld [%o5+12], %l3
54411st %l3, [%o5+12]
54412
54413P5048: !_LD [17] (Int)
54414lduw [%i3 + 12], %l7
54415! move %l7(lower) -> %o1(lower)
54416or %l7, %o1, %o1
54417
54418P5049: !_MEMBAR (FP)
54419membar #StoreLoad
54420
54421P5050: !_BLD [14] (FP)
54422wr %g0, 0xf0, %asi
54423sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
54424add %i0, %i3, %i3
54425ldda [%i3 + 0] %asi, %f32
54426membar #Sync
54427! 3 addresses covered
54428fmovd %f32, %f18
54429fmovs %f18, %f3
54430fmovs %f19, %f4
54431fmovd %f34, %f18
54432fmovs %f19, %f5
54433
54434P5051: !_MEMBAR (FP)
54435
54436P5052: !_PREFETCH [7] (Int)
54437sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
54438sub %i0, %i2, %i2
54439prefetch [%i2 + 4], 2
54440
54441P5053: !_LD [5] (Int)
54442lduw [%i1 + 12], %o2
54443! move %o2(lower) -> %o2(upper)
54444sllx %o2, 32, %o2
54445
54446P5054: !_ST_BINIT [1] (maybe <- 0x2800013) (Int)
54447wr %g0, 0xe2, %asi
54448stwa %l4, [%i0 + 4] %asi
54449add %l4, 1, %l4
54450
54451P5055: !_MEMBAR (Int)
54452membar #StoreLoad
54453
54454P5056: !_DWST_BINIT [17] (maybe <- 0x2800014) (Int) (Branch target of P5436)
54455wr %g0, 0xe2, %asi
54456sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
54457sub %i0, %i3, %i3
54458mov %l4, %l3
54459stxa %l3, [%i3 + 8] %asi
54460add %l4, 1, %l4
54461ba P5057
54462nop
54463
54464TARGET5436:
54465ba RET5436
54466nop
54467
54468
54469P5057: !_MEMBAR (Int)
54470membar #StoreLoad
54471
54472P5058: !_DWST [2] (maybe <- 0x2800015) (Int)
54473mov %l4, %o5
54474stx %o5, [%i0 + 8]
54475add %l4, 1, %l4
54476
54477P5059: !_CAS [18] (maybe <- 0x2800016) (Int)
54478sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
54479sub %i0, %i2, %i2
54480lduw [%i2], %l6
54481mov %l6, %l7
54482! move %l7(lower) -> %o2(lower)
54483or %l7, %o2, %o2
54484mov %l4, %o3
54485cas [%i2], %l7, %o3
54486! move %o3(lower) -> %o3(upper)
54487sllx %o3, 32, %o3
54488add %l4, 1, %l4
54489
54490P5060: !_CASX [15] (maybe <- 0x2800017) (Int)
54491ldx [%i3], %l6
54492! move %l6(upper) -> %o3(lower)
54493srlx %l6, 32, %l7
54494or %l7, %o3, %o3
54495! move %l6(lower) -> %o4(upper)
54496sllx %l6, 32, %o4
54497mov %l6, %l7
54498sllx %l4, 32, %l6
54499add %l4, 1, %l4
54500or %l4, %l6, %l6
54501casx [%i3], %l7, %l6
54502! move %l6(upper) -> %o4(lower)
54503srlx %l6, 32, %l7
54504or %l7, %o4, %o4
54505!---- flushing int results buffer----
54506mov %o0, %l5
54507mov %o1, %l5
54508mov %o2, %l5
54509mov %o3, %l5
54510mov %o4, %l5
54511! move %l6(lower) -> %o0(upper)
54512sllx %l6, 32, %o0
54513add %l4, 1, %l4
54514
54515P5061: !_PREFETCH [2] (Int)
54516prefetch [%i0 + 12], 20
54517
54518P5062: !_DWST_BINIT [1] (maybe <- 0x2800019) (Int)
54519wr %g0, 0xe2, %asi
54520sllx %l4, 32, %l7
54521add %l4, 1, %l4
54522or %l7, %l4, %l7
54523stxa %l7, [%i0 + 0] %asi
54524add %l4, 1, %l4
54525
54526P5063: !_MEMBAR (Int)
54527membar #StoreLoad
54528
54529P5064: !_BLD [3] (FP)
54530wr %g0, 0xf0, %asi
54531ldda [%i1 + 0] %asi, %f32
54532membar #Sync
54533! 3 addresses covered
54534fmovd %f32, %f6
54535fmovd %f34, %f18
54536fmovs %f19, %f8
54537
54538P5065: !_MEMBAR (FP)
54539
54540P5066: !_LD [18] (Int)
54541lduw [%i2 + 0], %l7
54542! move %l7(lower) -> %o0(lower)
54543or %l7, %o0, %o0
54544
54545P5067: !_LDD [22] (Int) (CBR)
54546sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
54547add %i0, %i3, %i3
54548ldd [%i3 + 0], %l6
54549! move %l6(lower) -> %o1(upper)
54550sllx %l6, 32, %o1
54551! move %l7(lower) -> %o1(lower)
54552or %l7, %o1, %o1
54553
54554! cbranch
54555andcc %l0, 1, %g0
54556be,pt %xcc, TARGET5067
54557nop
54558RET5067:
54559
54560! lfsr step begin
54561srlx %l0, 1, %l3
54562xnor %l3, %l0, %l3
54563sllx %l3, 63, %l3
54564or %l3, %l0, %l0
54565srlx %l0, 1, %l0
54566
54567
54568P5068: !_DWST_BINIT [2] (maybe <- 0x280001b) (Int)
54569wr %g0, 0xe2, %asi
54570mov %l4, %l6
54571stxa %l6, [%i0 + 8] %asi
54572add %l4, 1, %l4
54573
54574P5069: !_MEMBAR (Int)
54575membar #StoreLoad
54576
54577P5070: !_LDD [7] (Int)
54578sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
54579sub %i0, %i2, %i2
54580ldd [%i2 + 0], %l6
54581! move %l6(lower) -> %o2(upper)
54582sllx %l6, 32, %o2
54583! move %l7(lower) -> %o2(lower)
54584or %l7, %o2, %o2
54585
54586P5071: !_ST_BINIT [15] (maybe <- 0x280001c) (Int) (LE)
54587wr %g0, 0xea, %asi
54588sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
54589sub %i0, %i3, %i3
54590! Change single-word-level endianess (big endian <-> little endian)
54591sethi %hi(0xff00ff00), %l6
54592or %l6, %lo(0xff00ff00), %l6
54593and %l4, %l6, %l7
54594srl %l7, 8, %l7
54595sll %l4, 8, %l3
54596and %l3, %l6, %l3
54597or %l3, %l7, %l3
54598srl %l3, 16, %l7
54599sll %l3, 16, %l3
54600srl %l3, 0, %l3
54601or %l3, %l7, %l3
54602stwa %l3, [%i3 + 0] %asi
54603add %l4, 1, %l4
54604
54605P5072: !_MEMBAR (Int) (LE)
54606membar #StoreLoad
54607
54608P5073: !_LDD [4] (Int)
54609ldd [%i1 + 0], %l6
54610! move %l6(lower) -> %o3(upper)
54611sllx %l6, 32, %o3
54612! move %l7(lower) -> %o3(lower)
54613or %l7, %o3, %o3
54614
54615P5074: !_ST [15] (maybe <- 0x280001d) (Int)
54616stw %l4, [%i3 + 0 ]
54617add %l4, 1, %l4
54618
54619P5075: !_MEMBAR (FP)
54620membar #StoreLoad
54621
54622P5076: !_BLD [10] (FP)
54623wr %g0, 0xf0, %asi
54624sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
54625sub %i0, %i2, %i2
54626ldda [%i2 + 0] %asi, %f32
54627membar #Sync
54628! 3 addresses covered
54629fmovd %f32, %f18
54630fmovs %f18, %f9
54631fmovs %f19, %f10
54632fmovd %f34, %f18
54633fmovs %f19, %f11
54634
54635P5077: !_MEMBAR (FP)
54636
54637P5078: !_DWLD [14] (Int)
54638sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
54639add %i0, %i3, %i3
54640ldx [%i3 + 8], %o4
54641! move %o4(lower) -> %o4(upper)
54642sllx %o4, 32, %o4
54643
54644P5079: !_MEMBAR (FP) (CBR)
54645
54646! cbranch
54647andcc %l0, 1, %g0
54648be,pn %xcc, TARGET5079
54649nop
54650RET5079:
54651
54652! lfsr step begin
54653srlx %l0, 1, %l7
54654xnor %l7, %l0, %l7
54655sllx %l7, 63, %l7
54656or %l7, %l0, %l0
54657srlx %l0, 1, %l0
54658
54659
54660P5080: !_BST [6] (maybe <- 0x42000008) (FP)
54661wr %g0, 0xf0, %asi
54662sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
54663sub %i0, %i2, %i2
54664! preparing store val #0, next val will be in f32
54665fmovs %f16, %f20
54666fadds %f16, %f17, %f16
54667! preparing store val #1, next val will be in f33
54668fmovs %f16, %f21
54669fadds %f16, %f17, %f16
54670! preparing store val #2, next val will be in f35
54671fmovd %f20, %f32
54672fmovs %f16, %f21
54673fadds %f16, %f17, %f16
54674fmovd %f20, %f34
54675membar #Sync
54676stda %f32, [%i2 + 0 ] %asi
54677
54678P5081: !_MEMBAR (FP)
54679membar #StoreLoad
54680
54681P5082: !_SWAP [23] (maybe <- 0x280001e) (Int) (Branch target of P5067)
54682sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
54683add %i0, %i3, %i3
54684mov %l4, %l3
54685swap [%i3 + 12], %l3
54686! move %l3(lower) -> %o4(lower)
54687srl %l3, 0, %l7
54688or %l7, %o4, %o4
54689!---- flushing int results buffer----
54690mov %o0, %l5
54691mov %o1, %l5
54692mov %o2, %l5
54693mov %o3, %l5
54694mov %o4, %l5
54695add %l4, 1, %l4
54696ba P5083
54697nop
54698
54699TARGET5067:
54700ba RET5067
54701nop
54702
54703
54704P5083: !_CAS [13] (maybe <- 0x280001f) (Int)
54705sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
54706add %i0, %i2, %i2
54707add %i2, 4, %l7
54708lduw [%l7], %o0
54709mov %o0, %l6
54710! move %l6(lower) -> %o0(upper)
54711sllx %l6, 32, %o0
54712mov %l4, %l3
54713cas [%l7], %l6, %l3
54714! move %l3(lower) -> %o0(lower)
54715srl %l3, 0, %l6
54716or %l6, %o0, %o0
54717add %l4, 1, %l4
54718
54719P5084: !_CAS [22] (maybe <- 0x2800020) (Int)
54720add %i3, 4, %l7
54721lduw [%l7], %o1
54722mov %o1, %l6
54723! move %l6(lower) -> %o1(upper)
54724sllx %l6, 32, %o1
54725mov %l4, %l3
54726cas [%l7], %l6, %l3
54727! move %l3(lower) -> %o1(lower)
54728srl %l3, 0, %l6
54729or %l6, %o1, %o1
54730add %l4, 1, %l4
54731
54732P5085: !_DWST_BINIT [10] (maybe <- 0x2800021) (Int) (LE)
54733wr %g0, 0xea, %asi
54734sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
54735sub %i0, %i3, %i3
54736sllx %l4, 32, %l6
54737add %l4, 1, %l4
54738or %l6, %l4, %l7
54739! Change double-word-level endianess (big endian <-> little endian)
54740sethi %hi(0xff00ff00), %o5
54741or %o5, %lo(0xff00ff00), %o5
54742sllx %o5, 32, %l6
54743or %o5, %l6, %o5
54744and %l7, %o5, %l6
54745srlx %l6, 8, %l6
54746sllx %l7, 8, %l7
54747and %l7, %o5, %l7
54748or %l7, %l6, %l7
54749sethi %hi(0xffff0000), %o5
54750srlx %l7, 16, %l6
54751andn %l6, %o5, %l6
54752andn %l7, %o5, %l7
54753sllx %l7, 16, %l7
54754or %l7, %l6, %l7
54755srlx %l7, 32, %l6
54756sllx %l7, 32, %l7
54757or %l7, %l6, %l6
54758stxa %l6, [%i3 + 0 ] %asi
54759add %l4, 1, %l4
54760
54761P5086: !_MEMBAR (Int) (LE) (CBR)
54762membar #StoreLoad
54763
54764! cbranch
54765andcc %l0, 1, %g0
54766be,pn %xcc, TARGET5086
54767nop
54768RET5086:
54769
54770! lfsr step begin
54771srlx %l0, 1, %l3
54772xnor %l3, %l0, %l3
54773sllx %l3, 63, %l3
54774or %l3, %l0, %l0
54775srlx %l0, 1, %l0
54776
54777
54778P5087: !_LDD [7] (Int)
54779sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
54780sub %i0, %i2, %i2
54781ldd [%i2 + 0], %l6
54782! move %l6(lower) -> %o2(upper)
54783sllx %l6, 32, %o2
54784! move %l7(lower) -> %o2(lower)
54785or %l7, %o2, %o2
54786
54787P5088: !_ST [10] (maybe <- 0x2800023) (Int)
54788stw %l4, [%i3 + 4 ]
54789add %l4, 1, %l4
54790
54791P5089: !_DWLD [23] (Int)
54792sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
54793add %i0, %i3, %i3
54794ldx [%i3 + 8], %o3
54795! move %o3(lower) -> %o3(upper)
54796sllx %o3, 32, %o3
54797
54798P5090: !_MEMBAR (FP)
54799
54800P5091: !_BSTC [22] (maybe <- 0x4200000b) (FP)
54801wr %g0, 0xe0, %asi
54802! preparing store val #0, next val will be in f32
54803fmovs %f16, %f20
54804fadds %f16, %f17, %f16
54805! preparing store val #1, next val will be in f33
54806fmovs %f16, %f21
54807fadds %f16, %f17, %f16
54808! preparing store val #2, next val will be in f35
54809fmovd %f20, %f32
54810fmovs %f16, %f21
54811fadds %f16, %f17, %f16
54812fmovd %f20, %f34
54813membar #Sync
54814stda %f32, [%i3 + 0 ] %asi
54815
54816P5092: !_MEMBAR (FP)
54817membar #StoreLoad
54818
54819P5093: !_CASX [10] (maybe <- 0x2800024) (Int)
54820sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i2
54821sub %i0, %i2, %i2
54822ldx [%i2], %o5
54823! move %o5(upper) -> %o3(lower)
54824srlx %o5, 32, %l3
54825or %l3, %o3, %o3
54826! move %o5(lower) -> %o4(upper)
54827sllx %o5, 32, %o4
54828mov %o5, %l3
54829sllx %l4, 32, %o5
54830add %l4, 1, %l4
54831or %l4, %o5, %o5
54832casx [%i2], %l3, %o5
54833! move %o5(upper) -> %o4(lower)
54834srlx %o5, 32, %l3
54835or %l3, %o4, %o4
54836!---- flushing int results buffer----
54837mov %o0, %l5
54838mov %o1, %l5
54839mov %o2, %l5
54840mov %o3, %l5
54841mov %o4, %l5
54842! move %o5(lower) -> %o0(upper)
54843sllx %o5, 32, %o0
54844add %l4, 1, %l4
54845
54846P5094: !_MEMBAR (FP)
54847
54848P5095: !_BST [3] (maybe <- 0x4200000e) (FP)
54849wr %g0, 0xf0, %asi
54850! preparing store val #0, next val will be in f32
54851fmovs %f16, %f20
54852fadds %f16, %f17, %f16
54853! preparing store val #1, next val will be in f33
54854fmovs %f16, %f21
54855fadds %f16, %f17, %f16
54856! preparing store val #2, next val will be in f35
54857fmovd %f20, %f32
54858fmovs %f16, %f21
54859fadds %f16, %f17, %f16
54860fmovd %f20, %f34
54861membar #Sync
54862stda %f32, [%i1 + 0 ] %asi
54863
54864P5096: !_MEMBAR (FP)
54865membar #StoreLoad
54866
54867P5097: !_ST [9] (maybe <- 0x2800026) (Int)
54868stw %l4, [%i2 + 0 ]
54869add %l4, 1, %l4
54870
54871P5098: !_REPLACEMENT [17] (Int)
54872sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
54873add %i0, %i3, %i3
54874sethi %hi(0x20000), %l7
54875ld [%i3+12], %l3
54876st %l3, [%i3+12]
54877add %i3, %l7, %o5
54878ld [%o5+12], %l3
54879st %l3, [%o5+12]
54880add %o5, %l7, %o5
54881ld [%o5+12], %l3
54882st %l3, [%o5+12]
54883add %o5, %l7, %o5
54884ld [%o5+12], %l3
54885st %l3, [%o5+12]
54886add %o5, %l7, %o5
54887ld [%o5+12], %l3
54888st %l3, [%o5+12]
54889add %o5, %l7, %o5
54890ld [%o5+12], %l3
54891st %l3, [%o5+12]
54892add %o5, %l7, %o5
54893ld [%o5+12], %l3
54894st %l3, [%o5+12]
54895add %o5, %l7, %o5
54896ld [%o5+12], %l3
54897st %l3, [%o5+12]
54898
54899P5099: !_ST [13] (maybe <- 0x2800027) (Int)
54900sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
54901add %i0, %i2, %i2
54902stw %l4, [%i2 + 4 ]
54903add %l4, 1, %l4
54904
54905P5100: !_DWST_BINIT [10] (maybe <- 0x2800028) (Int)
54906wr %g0, 0xe2, %asi
54907sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
54908sub %i0, %i3, %i3
54909sllx %l4, 32, %l3
54910add %l4, 1, %l4
54911or %l3, %l4, %l3
54912stxa %l3, [%i3 + 0] %asi
54913add %l4, 1, %l4
54914
54915P5101: !_MEMBAR (Int)
54916
54917P5102: !_BSTC [11] (maybe <- 0x42000011) (FP)
54918wr %g0, 0xe0, %asi
54919! preparing store val #0, next val will be in f32
54920fmovs %f16, %f20
54921fadds %f16, %f17, %f16
54922! preparing store val #1, next val will be in f33
54923fmovs %f16, %f21
54924fadds %f16, %f17, %f16
54925! preparing store val #2, next val will be in f35
54926fmovd %f20, %f32
54927fmovs %f16, %f21
54928fadds %f16, %f17, %f16
54929fmovd %f20, %f34
54930membar #Sync
54931stda %f32, [%i3 + 0 ] %asi
54932
54933P5103: !_MEMBAR (FP) (CBR)
54934
54935! cbranch
54936andcc %l0, 1, %g0
54937be,pt %xcc, TARGET5103
54938nop
54939RET5103:
54940
54941! lfsr step begin
54942srlx %l0, 1, %l7
54943xnor %l7, %l0, %l7
54944sllx %l7, 63, %l7
54945or %l7, %l0, %l0
54946srlx %l0, 1, %l0
54947
54948
54949P5104: !_BST [0] (maybe <- 0x42000014) (FP)
54950wr %g0, 0xf0, %asi
54951! preparing store val #0, next val will be in f32
54952fmovs %f16, %f20
54953fadds %f16, %f17, %f16
54954! preparing store val #1, next val will be in f33
54955fmovs %f16, %f21
54956fadds %f16, %f17, %f16
54957! preparing store val #2, next val will be in f35
54958fmovd %f20, %f32
54959fmovs %f16, %f21
54960fadds %f16, %f17, %f16
54961fmovd %f20, %f34
54962membar #Sync
54963stda %f32, [%i0 + 0 ] %asi
54964
54965P5105: !_MEMBAR (FP)
54966membar #StoreLoad
54967
54968P5106: !_PREFETCH [5] (Int) (CBR)
54969prefetch [%i1 + 12], 22
54970
54971! cbranch
54972andcc %l0, 1, %g0
54973be,pn %xcc, TARGET5106
54974nop
54975RET5106:
54976
54977! lfsr step begin
54978srlx %l0, 1, %l7
54979xnor %l7, %l0, %l7
54980sllx %l7, 63, %l7
54981or %l7, %l0, %l0
54982srlx %l0, 1, %l0
54983
54984
54985P5107: !_MEMBAR (FP)
54986
54987P5108: !_BSTC [17] (maybe <- 0x42000017) (FP)
54988wr %g0, 0xe0, %asi
54989sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
54990sub %i0, %i2, %i2
54991! preparing store val #0, next val will be in f32
54992fmovs %f16, %f20
54993fadds %f16, %f17, %f16
54994! preparing store val #1, next val will be in f33
54995fmovs %f16, %f21
54996fadds %f16, %f17, %f16
54997! preparing store val #2, next val will be in f35
54998fmovd %f20, %f32
54999fmovs %f16, %f21
55000fadds %f16, %f17, %f16
55001fmovd %f20, %f34
55002membar #Sync
55003stda %f32, [%i2 + 0 ] %asi
55004
55005P5109: !_MEMBAR (FP)
55006
55007P5110: !_BSTC [21] (maybe <- 0x4200001a) (FP) (Branch target of P5023)
55008wr %g0, 0xe0, %asi
55009sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
55010add %i0, %i3, %i3
55011! preparing store val #0, next val will be in f32
55012fmovs %f16, %f20
55013fadds %f16, %f17, %f16
55014! preparing store val #1, next val will be in f33
55015fmovs %f16, %f21
55016fadds %f16, %f17, %f16
55017! preparing store val #2, next val will be in f35
55018fmovd %f20, %f32
55019fmovs %f16, %f21
55020fadds %f16, %f17, %f16
55021fmovd %f20, %f34
55022membar #Sync
55023stda %f32, [%i3 + 0 ] %asi
55024ba P5111
55025nop
55026
55027TARGET5023:
55028ba RET5023
55029nop
55030
55031
55032P5111: !_MEMBAR (FP) (Branch target of P5612)
55033membar #StoreLoad
55034ba P5112
55035nop
55036
55037TARGET5612:
55038ba RET5612
55039nop
55040
55041
55042P5112: !_LDD [4] (Int)
55043ldd [%i1 + 0], %l6
55044! move %l6(lower) -> %o0(lower)
55045or %l6, %o0, %o0
55046! move %l7(lower) -> %o1(upper)
55047sllx %l7, 32, %o1
55048
55049P5113: !_DWLD [19] (Int)
55050sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
55051sub %i0, %i2, %i2
55052ldx [%i2 + 0], %l6
55053! move %l6(upper) -> %o1(lower)
55054srlx %l6, 32, %l3
55055or %l3, %o1, %o1
55056! move %l6(lower) -> %o2(upper)
55057sllx %l6, 32, %o2
55058
55059P5114: !_DWST_BINIT [19] (maybe <- 0x280002a) (Int) (Branch target of P5079)
55060wr %g0, 0xe2, %asi
55061sllx %l4, 32, %l7
55062add %l4, 1, %l4
55063or %l7, %l4, %l7
55064stxa %l7, [%i2 + 0] %asi
55065add %l4, 1, %l4
55066ba P5115
55067nop
55068
55069TARGET5079:
55070ba RET5079
55071nop
55072
55073
55074P5115: !_MEMBAR (Int)
55075membar #StoreLoad
55076
55077P5116: !_ST [11] (maybe <- 0x280002c) (Int)
55078sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS3_O), %i3
55079sub %i0, %i3, %i3
55080stw %l4, [%i3 + 12 ]
55081add %l4, 1, %l4
55082
55083P5117: !_LD [12] (Int)
55084sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
55085add %i0, %i2, %i2
55086lduw [%i2 + 0], %l6
55087! move %l6(lower) -> %o2(lower)
55088or %l6, %o2, %o2
55089
55090P5118: !_LD [14] (Int)
55091lduw [%i2 + 12], %o3
55092! move %o3(lower) -> %o3(upper)
55093sllx %o3, 32, %o3
55094
55095P5119: !_MEMBAR (FP)
55096
55097P5120: !_BSTC [14] (maybe <- 0x4200001d) (FP)
55098wr %g0, 0xe0, %asi
55099! preparing store val #0, next val will be in f32
55100fmovs %f16, %f20
55101fadds %f16, %f17, %f16
55102! preparing store val #1, next val will be in f33
55103fmovs %f16, %f21
55104fadds %f16, %f17, %f16
55105! preparing store val #2, next val will be in f35
55106fmovd %f20, %f32
55107fmovs %f16, %f21
55108fadds %f16, %f17, %f16
55109fmovd %f20, %f34
55110membar #Sync
55111stda %f32, [%i2 + 0 ] %asi
55112
55113P5121: !_MEMBAR (FP) (Branch target of P5216)
55114membar #StoreLoad
55115ba P5122
55116nop
55117
55118TARGET5216:
55119ba RET5216
55120nop
55121
55122
55123P5122: !_DWST_BINIT [17] (maybe <- 0x280002d) (Int)
55124wr %g0, 0xe2, %asi
55125sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
55126sub %i0, %i3, %i3
55127mov %l4, %o5
55128stxa %o5, [%i3 + 8] %asi
55129add %l4, 1, %l4
55130
55131P5123: !_MEMBAR (Int)
55132membar #StoreLoad
55133
55134P5124: !_BLD [3] (FP)
55135wr %g0, 0xf0, %asi
55136ldda [%i1 + 0] %asi, %f32
55137membar #Sync
55138! 3 addresses covered
55139fmovd %f32, %f12
55140fmovd %f34, %f18
55141fmovs %f19, %f14
55142
55143P5125: !_MEMBAR (FP)
55144
55145P5126: !_BSTC [7] (maybe <- 0x42000020) (FP)
55146wr %g0, 0xe0, %asi
55147sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
55148sub %i0, %i2, %i2
55149! preparing store val #0, next val will be in f32
55150fmovs %f16, %f20
55151fadds %f16, %f17, %f16
55152! preparing store val #1, next val will be in f33
55153fmovs %f16, %f21
55154fadds %f16, %f17, %f16
55155! preparing store val #2, next val will be in f35
55156fmovd %f20, %f32
55157fmovs %f16, %f21
55158fadds %f16, %f17, %f16
55159fmovd %f20, %f34
55160membar #Sync
55161stda %f32, [%i2 + 0 ] %asi
55162
55163P5127: !_MEMBAR (FP)
55164membar #StoreLoad
55165
55166P5128: !_LD [0] (Int)
55167lduw [%i0 + 0], %l7
55168! move %l7(lower) -> %o3(lower)
55169or %l7, %o3, %o3
55170
55171P5129: !_ST_BINIT [21] (maybe <- 0x280002e) (Int)
55172wr %g0, 0xe2, %asi
55173sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
55174add %i0, %i3, %i3
55175stwa %l4, [%i3 + 0] %asi
55176add %l4, 1, %l4
55177
55178P5130: !_MEMBAR (Int)
55179
55180P5131: !_BST [22] (maybe <- 0x42000023) (FP)
55181wr %g0, 0xf0, %asi
55182! preparing store val #0, next val will be in f32
55183fmovs %f16, %f20
55184fadds %f16, %f17, %f16
55185! preparing store val #1, next val will be in f33
55186fmovs %f16, %f21
55187fadds %f16, %f17, %f16
55188! preparing store val #2, next val will be in f35
55189fmovd %f20, %f32
55190fmovs %f16, %f21
55191fadds %f16, %f17, %f16
55192fmovd %f20, %f34
55193membar #Sync
55194stda %f32, [%i3 + 0 ] %asi
55195
55196P5132: !_MEMBAR (FP)
55197membar #StoreLoad
55198
55199P5133: !_DWST_BINIT [5] (maybe <- 0x280002f) (Int)
55200wr %g0, 0xe2, %asi
55201mov %l4, %l6
55202stxa %l6, [%i1 + 8] %asi
55203add %l4, 1, %l4
55204
55205P5134: !_MEMBAR (Int)
55206membar #StoreLoad
55207
55208P5135: !_DWST [0] (maybe <- 0x2800030) (Int)
55209sllx %l4, 32, %l3
55210add %l4, 1, %l4
55211or %l3, %l4, %l3
55212stx %l3, [%i0 + 0]
55213add %l4, 1, %l4
55214
55215P5136: !_LD [19] (FP)
55216sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
55217sub %i0, %i2, %i2
55218ld [%i2 + 4], %f15
55219! 1 addresses covered
55220!---- flushing fp results buffer to %f30 ----
55221fmovd %f0, %f30
55222fmovd %f2, %f30
55223fmovd %f4, %f30
55224fmovd %f6, %f30
55225fmovd %f8, %f30
55226fmovd %f10, %f30
55227fmovd %f12, %f30
55228fmovd %f14, %f30
55229!--
55230
55231P5137: !_LD [5] (Int)
55232lduw [%i1 + 12], %o4
55233! move %o4(lower) -> %o4(upper)
55234sllx %o4, 32, %o4
55235
55236P5138: !_LDD [17] (Int)
55237sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
55238sub %i0, %i3, %i3
55239ldd [%i3 + 8], %l6
55240! move %l7(lower) -> %o4(lower)
55241or %l7, %o4, %o4
55242!---- flushing int results buffer----
55243mov %o0, %l5
55244mov %o1, %l5
55245mov %o2, %l5
55246mov %o3, %l5
55247mov %o4, %l5
55248
55249P5139: !_ST_BINIT [21] (maybe <- 0x2800032) (Int)
55250wr %g0, 0xe2, %asi
55251sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
55252add %i0, %i2, %i2
55253stwa %l4, [%i2 + 0] %asi
55254add %l4, 1, %l4
55255
55256P5140: !_MEMBAR (Int)
55257membar #StoreLoad
55258
55259P5141: !_DWST [11] (maybe <- 0x2800033) (Int) (LE)
55260wr %g0, 0x88, %asi
55261sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
55262add %i0, %i3, %i3
55263! Change single-word-level endianess (big endian <-> little endian)
55264sethi %hi(0xff00ff00), %l3
55265or %l3, %lo(0xff00ff00), %l3
55266and %l4, %l3, %l7
55267srl %l7, 8, %l7
55268sll %l4, 8, %l6
55269and %l6, %l3, %l6
55270or %l6, %l7, %l6
55271srl %l6, 16, %l7
55272sll %l6, 16, %l6
55273srl %l6, 0, %l6
55274or %l6, %l7, %l6
55275sllx %l6, 32, %l6
55276stxa %l6, [%i3 + 8 ] %asi
55277add %l4, 1, %l4
55278
55279P5142: !_ST [10] (maybe <- 0x2800034) (Int)
55280stw %l4, [%i3 + 4 ]
55281add %l4, 1, %l4
55282
55283P5143: !_PREFETCH [17] (Int)
55284sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
55285sub %i0, %i2, %i2
55286prefetch [%i2 + 12], 1
55287
55288P5144: !_DWLD [21] (Int)
55289sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
55290add %i0, %i3, %i3
55291ldx [%i3 + 0], %o0
55292! move %o0(upper) -> %o0(upper)
55293! move %o0(lower) -> %o0(lower)
55294
55295P5145: !_ST [11] (maybe <- 0x2800035) (Int)
55296sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
55297add %i0, %i2, %i2
55298stw %l4, [%i2 + 12 ]
55299add %l4, 1, %l4
55300
55301P5146: !_ST_BINIT [10] (maybe <- 0x2800036) (Int)
55302wr %g0, 0xe2, %asi
55303stwa %l4, [%i2 + 4] %asi
55304add %l4, 1, %l4
55305
55306P5147: !_MEMBAR (Int)
55307
55308P5148: !_BSTC [18] (maybe <- 0x42000026) (FP)
55309wr %g0, 0xe0, %asi
55310sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
55311sub %i0, %i3, %i3
55312! preparing store val #0, next val will be in f32
55313fmovs %f16, %f20
55314fadds %f16, %f17, %f16
55315! preparing store val #1, next val will be in f33
55316fmovs %f16, %f21
55317fadds %f16, %f17, %f16
55318! preparing store val #2, next val will be in f35
55319fmovd %f20, %f32
55320fmovs %f16, %f21
55321fadds %f16, %f17, %f16
55322fmovd %f20, %f34
55323membar #Sync
55324stda %f32, [%i3 + 0 ] %asi
55325
55326P5149: !_MEMBAR (FP)
55327membar #StoreLoad
55328
55329P5150: !_SWAP [7] (maybe <- 0x2800037) (Int)
55330sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
55331sub %i0, %i2, %i2
55332mov %l4, %o1
55333swap [%i2 + 4], %o1
55334! move %o1(lower) -> %o1(upper)
55335sllx %o1, 32, %o1
55336add %l4, 1, %l4
55337
55338P5151: !_REPLACEMENT [22] (Int)
55339sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
55340sub %i0, %i3, %i3
55341sethi %hi(0x20000), %l3
55342ld [%i3+4], %l7
55343st %l7, [%i3+4]
55344add %i3, %l3, %l6
55345ld [%l6+4], %l7
55346st %l7, [%l6+4]
55347add %l6, %l3, %l6
55348ld [%l6+4], %l7
55349st %l7, [%l6+4]
55350add %l6, %l3, %l6
55351ld [%l6+4], %l7
55352st %l7, [%l6+4]
55353add %l6, %l3, %l6
55354ld [%l6+4], %l7
55355st %l7, [%l6+4]
55356add %l6, %l3, %l6
55357ld [%l6+4], %l7
55358st %l7, [%l6+4]
55359add %l6, %l3, %l6
55360ld [%l6+4], %l7
55361st %l7, [%l6+4]
55362add %l6, %l3, %l6
55363ld [%l6+4], %l7
55364st %l7, [%l6+4]
55365
55366P5152: !_DWLD [7] (Int)
55367ldx [%i2 + 0], %l3
55368! move %l3(upper) -> %o1(lower)
55369srlx %l3, 32, %o5
55370or %o5, %o1, %o1
55371! move %l3(lower) -> %o2(upper)
55372sllx %l3, 32, %o2
55373
55374P5153: !_MEMBAR (FP)
55375
55376P5154: !_BSTC [0] (maybe <- 0x42000029) (FP)
55377wr %g0, 0xe0, %asi
55378! preparing store val #0, next val will be in f32
55379fmovs %f16, %f20
55380fadds %f16, %f17, %f16
55381! preparing store val #1, next val will be in f33
55382fmovs %f16, %f21
55383fadds %f16, %f17, %f16
55384! preparing store val #2, next val will be in f35
55385fmovd %f20, %f32
55386fmovs %f16, %f21
55387fadds %f16, %f17, %f16
55388fmovd %f20, %f34
55389membar #Sync
55390stda %f32, [%i0 + 0 ] %asi
55391
55392P5155: !_MEMBAR (FP)
55393membar #StoreLoad
55394
55395P5156: !_LD [2] (Int)
55396lduw [%i0 + 12], %l6
55397! move %l6(lower) -> %o2(lower)
55398or %l6, %o2, %o2
55399
55400P5157: !_CASX [6] (maybe <- 0x2800038) (Int)
55401ldx [%i2], %o3
55402! move %o3(upper) -> %o3(upper)
55403! move %o3(lower) -> %o3(lower)
55404mov %o3, %l7
55405sllx %l4, 32, %o4
55406add %l4, 1, %l4
55407or %l4, %o4, %o4
55408casx [%i2], %l7, %o4
55409! move %o4(upper) -> %o4(upper)
55410! move %o4(lower) -> %o4(lower)
55411!---- flushing int results buffer----
55412mov %o0, %l5
55413mov %o1, %l5
55414mov %o2, %l5
55415mov %o3, %l5
55416mov %o4, %l5
55417add %l4, 1, %l4
55418
55419P5158: !_DWST_BINIT [10] (maybe <- 0x280003a) (Int)
55420wr %g0, 0xe2, %asi
55421sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
55422add %i0, %i2, %i2
55423sllx %l4, 32, %l7
55424add %l4, 1, %l4
55425or %l7, %l4, %l7
55426stxa %l7, [%i2 + 0] %asi
55427add %l4, 1, %l4
55428
55429P5159: !_MEMBAR (Int)
55430membar #StoreLoad
55431
55432P5160: !_DWLD [7] (Int)
55433sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
55434sub %i0, %i3, %i3
55435ldx [%i3 + 0], %o0
55436! move %o0(upper) -> %o0(upper)
55437! move %o0(lower) -> %o0(lower)
55438
55439P5161: !_MEMBAR (FP)
55440
55441P5162: !_BSTC [15] (maybe <- 0x4200002c) (FP)
55442wr %g0, 0xe0, %asi
55443sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
55444sub %i0, %i2, %i2
55445! preparing store val #0, next val will be in f32
55446fmovs %f16, %f20
55447fadds %f16, %f17, %f16
55448! preparing store val #1, next val will be in f33
55449fmovs %f16, %f21
55450fadds %f16, %f17, %f16
55451! preparing store val #2, next val will be in f35
55452fmovd %f20, %f32
55453fmovs %f16, %f21
55454fadds %f16, %f17, %f16
55455fmovd %f20, %f34
55456membar #Sync
55457stda %f32, [%i2 + 0 ] %asi
55458
55459P5163: !_MEMBAR (FP)
55460membar #StoreLoad
55461
55462P5164: !_LD [4] (Int)
55463lduw [%i1 + 4], %o1
55464! move %o1(lower) -> %o1(upper)
55465sllx %o1, 32, %o1
55466
55467P5165: !_PREFETCH [19] (Int)
55468sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
55469sub %i0, %i3, %i3
55470prefetch [%i3 + 4], 23
55471
55472P5166: !_LDD [7] (Int)
55473sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
55474sub %i0, %i2, %i2
55475ldd [%i2 + 0], %l6
55476! move %l6(lower) -> %o1(lower)
55477or %l6, %o1, %o1
55478! move %l7(lower) -> %o2(upper)
55479sllx %l7, 32, %o2
55480
55481P5167: !_REPLACEMENT [0] (Int)
55482sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
55483sub %i0, %i3, %i3
55484sethi %hi(0x20000), %l3
55485ld [%i3+0], %l7
55486st %l7, [%i3+0]
55487add %i3, %l3, %l6
55488ld [%l6+0], %l7
55489st %l7, [%l6+0]
55490add %l6, %l3, %l6
55491ld [%l6+0], %l7
55492st %l7, [%l6+0]
55493add %l6, %l3, %l6
55494ld [%l6+0], %l7
55495st %l7, [%l6+0]
55496add %l6, %l3, %l6
55497ld [%l6+0], %l7
55498st %l7, [%l6+0]
55499add %l6, %l3, %l6
55500ld [%l6+0], %l7
55501st %l7, [%l6+0]
55502add %l6, %l3, %l6
55503ld [%l6+0], %l7
55504st %l7, [%l6+0]
55505add %l6, %l3, %l6
55506ld [%l6+0], %l7
55507st %l7, [%l6+0]
55508
55509P5168: !_PREFETCH [7] (Int) (Branch target of P5016)
55510prefetch [%i2 + 4], 21
55511ba P5169
55512nop
55513
55514TARGET5016:
55515ba RET5016
55516nop
55517
55518
55519P5169: !_CASX [14] (maybe <- 0x280003c) (Int)
55520sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
55521add %i0, %i2, %i2
55522add %i2, 8, %l3
55523ldx [%l3], %l7
55524! move %l7(upper) -> %o2(lower)
55525srlx %l7, 32, %o5
55526or %o5, %o2, %o2
55527! move %l7(lower) -> %o3(upper)
55528sllx %l7, 32, %o3
55529mov %l7, %o5
55530mov %l4, %l7
55531casx [%l3], %o5, %l7
55532! move %l7(upper) -> %o3(lower)
55533srlx %l7, 32, %o5
55534or %o5, %o3, %o3
55535! move %l7(lower) -> %o4(upper)
55536sllx %l7, 32, %o4
55537add %l4, 1, %l4
55538
55539P5170: !_DWST_BINIT [7] (maybe <- 0x280003d) (Int)
55540wr %g0, 0xe2, %asi
55541sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
55542sub %i0, %i3, %i3
55543sllx %l4, 32, %o5
55544add %l4, 1, %l4
55545or %o5, %l4, %o5
55546stxa %o5, [%i3 + 0] %asi
55547add %l4, 1, %l4
55548
55549P5171: !_MEMBAR (Int)
55550membar #StoreLoad
55551
55552P5172: !_DWST [17] (maybe <- 0x280003f) (Int)
55553sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
55554sub %i0, %i2, %i2
55555mov %l4, %l7
55556stx %l7, [%i2 + 8]
55557add %l4, 1, %l4
55558
55559P5173: !_CASX [3] (maybe <- 0x2800040) (Int)
55560ldx [%i1], %l3
55561! move %l3(upper) -> %o4(lower)
55562srlx %l3, 32, %l6
55563or %l6, %o4, %o4
55564!---- flushing int results buffer----
55565mov %o0, %l5
55566mov %o1, %l5
55567mov %o2, %l5
55568mov %o3, %l5
55569mov %o4, %l5
55570! move %l3(lower) -> %o0(upper)
55571sllx %l3, 32, %o0
55572mov %l3, %l6
55573sllx %l4, 32, %l3
55574add %l4, 1, %l4
55575or %l4, %l3, %l3
55576casx [%i1], %l6, %l3
55577! move %l3(upper) -> %o0(lower)
55578srlx %l3, 32, %l6
55579or %l6, %o0, %o0
55580! move %l3(lower) -> %o1(upper)
55581sllx %l3, 32, %o1
55582add %l4, 1, %l4
55583
55584P5174: !_DWST_BINIT [10] (maybe <- 0x2800042) (Int)
55585wr %g0, 0xe2, %asi
55586sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
55587add %i0, %i3, %i3
55588sllx %l4, 32, %l6
55589add %l4, 1, %l4
55590or %l6, %l4, %l6
55591stxa %l6, [%i3 + 0] %asi
55592add %l4, 1, %l4
55593
55594P5175: !_MEMBAR (Int)
55595membar #StoreLoad
55596
55597P5176: !_ST_BINIT [22] (maybe <- 0x2800044) (Int)
55598wr %g0, 0xe2, %asi
55599sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
55600add %i0, %i2, %i2
55601stwa %l4, [%i2 + 4] %asi
55602add %l4, 1, %l4
55603
55604P5177: !_MEMBAR (Int)
55605membar #StoreLoad
55606
55607P5178: !_ST [4] (maybe <- 0x2800045) (Int)
55608stw %l4, [%i1 + 4 ]
55609add %l4, 1, %l4
55610
55611P5179: !_MEMBAR (FP)
55612
55613P5180: !_BST [9] (maybe <- 0x4200002f) (FP)
55614wr %g0, 0xf0, %asi
55615! preparing store val #0, next val will be in f32
55616fmovs %f16, %f20
55617fadds %f16, %f17, %f16
55618! preparing store val #1, next val will be in f33
55619fmovs %f16, %f21
55620fadds %f16, %f17, %f16
55621! preparing store val #2, next val will be in f35
55622fmovd %f20, %f32
55623fmovs %f16, %f21
55624fadds %f16, %f17, %f16
55625fmovd %f20, %f34
55626membar #Sync
55627stda %f32, [%i3 + 0 ] %asi
55628
55629P5181: !_MEMBAR (FP)
55630membar #StoreLoad
55631
55632P5182: !_DWST_BINIT [21] (maybe <- 0x2800046) (Int)
55633wr %g0, 0xe2, %asi
55634sllx %l4, 32, %l6
55635add %l4, 1, %l4
55636or %l6, %l4, %l6
55637stxa %l6, [%i2 + 0] %asi
55638add %l4, 1, %l4
55639
55640P5183: !_MEMBAR (Int)
55641membar #StoreLoad
55642
55643P5184: !_DWST_BINIT [12] (maybe <- 0x2800048) (Int)
55644wr %g0, 0xe2, %asi
55645sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i3
55646add %i0, %i3, %i3
55647sllx %l4, 32, %l3
55648add %l4, 1, %l4
55649or %l3, %l4, %l3
55650stxa %l3, [%i3 + 0] %asi
55651add %l4, 1, %l4
55652
55653P5185: !_MEMBAR (Int)
55654membar #StoreLoad
55655
55656P5186: !_CASX [22] (maybe <- 0x280004a) (Int)
55657ldx [%i2], %l7
55658! move %l7(upper) -> %o1(lower)
55659srlx %l7, 32, %o5
55660or %o5, %o1, %o1
55661! move %l7(lower) -> %o2(upper)
55662sllx %l7, 32, %o2
55663mov %l7, %o5
55664sllx %l4, 32, %l7
55665add %l4, 1, %l4
55666or %l4, %l7, %l7
55667casx [%i2], %o5, %l7
55668! move %l7(upper) -> %o2(lower)
55669srlx %l7, 32, %o5
55670or %o5, %o2, %o2
55671! move %l7(lower) -> %o3(upper)
55672sllx %l7, 32, %o3
55673add %l4, 1, %l4
55674
55675P5187: !_DWST [10] (maybe <- 0x280004c) (Int)
55676sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
55677add %i0, %i2, %i2
55678sllx %l4, 32, %o5
55679add %l4, 1, %l4
55680or %o5, %l4, %o5
55681stx %o5, [%i2 + 0]
55682add %l4, 1, %l4
55683
55684P5188: !_LD [2] (Int)
55685lduw [%i0 + 12], %o5
55686! move %o5(lower) -> %o3(lower)
55687or %o5, %o3, %o3
55688
55689P5189: !_ST_BINIT [18] (maybe <- 0x280004e) (Int)
55690wr %g0, 0xe2, %asi
55691sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
55692sub %i0, %i3, %i3
55693stwa %l4, [%i3 + 0] %asi
55694add %l4, 1, %l4
55695
55696P5190: !_MEMBAR (Int)
55697membar #StoreLoad
55698
55699P5191: !_DWLD [7] (Int)
55700sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
55701sub %i0, %i2, %i2
55702ldx [%i2 + 0], %o4
55703! move %o4(upper) -> %o4(upper)
55704! move %o4(lower) -> %o4(lower)
55705!---- flushing int results buffer----
55706mov %o0, %l5
55707mov %o1, %l5
55708mov %o2, %l5
55709mov %o3, %l5
55710mov %o4, %l5
55711
55712P5192: !_PREFETCH [3] (Int)
55713prefetch [%i1 + 0], 21
55714
55715P5193: !_PREFETCH [11] (Int)
55716sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
55717add %i0, %i3, %i3
55718prefetch [%i3 + 12], 19
55719
55720P5194: !_DWST [12] (maybe <- 0x280004f) (Int)
55721sethi %hi(REGION4_ALIAS0_O-REGION0_ALIAS0_O), %i2
55722add %i0, %i2, %i2
55723sllx %l4, 32, %l6
55724add %l4, 1, %l4
55725or %l6, %l4, %l6
55726stx %l6, [%i2 + 0]
55727add %l4, 1, %l4
55728
55729P5195: !_DWST_BINIT [0] (maybe <- 0x2800051) (Int)
55730wr %g0, 0xe2, %asi
55731sllx %l4, 32, %l3
55732add %l4, 1, %l4
55733or %l3, %l4, %l3
55734stxa %l3, [%i0 + 0] %asi
55735add %l4, 1, %l4
55736
55737P5196: !_MEMBAR (Int)
55738membar #StoreLoad
55739
55740P5197: !_PREFETCH [4] (Int)
55741prefetch [%i1 + 4], 2
55742
55743P5198: !_CASX [15] (maybe <- 0x2800053) (Int)
55744sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
55745sub %i0, %i3, %i3
55746ldx [%i3], %o0
55747! move %o0(upper) -> %o0(upper)
55748! move %o0(lower) -> %o0(lower)
55749mov %o0, %o5
55750sllx %l4, 32, %o1
55751add %l4, 1, %l4
55752or %l4, %o1, %o1
55753casx [%i3], %o5, %o1
55754! move %o1(upper) -> %o1(upper)
55755! move %o1(lower) -> %o1(lower)
55756add %l4, 1, %l4
55757
55758P5199: !_MEMBAR (FP)
55759
55760P5200: !_BSTC [16] (maybe <- 0x42000032) (FP)
55761wr %g0, 0xe0, %asi
55762! preparing store val #0, next val will be in f32
55763fmovs %f16, %f20
55764fadds %f16, %f17, %f16
55765! preparing store val #1, next val will be in f33
55766fmovs %f16, %f21
55767fadds %f16, %f17, %f16
55768! preparing store val #2, next val will be in f35
55769fmovd %f20, %f32
55770fmovs %f16, %f21
55771fadds %f16, %f17, %f16
55772fmovd %f20, %f34
55773membar #Sync
55774stda %f32, [%i3 + 0 ] %asi
55775
55776P5201: !_MEMBAR (FP) (CBR)
55777membar #StoreLoad
55778
55779! cbranch
55780andcc %l0, 1, %g0
55781be,pt %xcc, TARGET5201
55782nop
55783RET5201:
55784
55785! lfsr step begin
55786srlx %l0, 1, %l7
55787xnor %l7, %l0, %l7
55788sllx %l7, 63, %l7
55789or %l7, %l0, %l0
55790srlx %l0, 1, %l0
55791
55792
55793P5202: !_BLD [7] (FP)
55794wr %g0, 0xf0, %asi
55795sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
55796sub %i0, %i2, %i2
55797ldda [%i2 + 0] %asi, %f0
55798membar #Sync
55799! 3 addresses covered
55800fmovs %f3, %f2
55801
55802P5203: !_MEMBAR (FP)
55803
55804P5204: !_DWLD [18] (FP)
55805sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
55806sub %i0, %i3, %i3
55807ldd [%i3 + 0], %f18
55808! 2 addresses covered
55809fmovs %f18, %f3
55810fmovs %f19, %f4
55811
55812P5205: !_DWLD [12] (Int)
55813sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
55814sub %i0, %i2, %i2
55815ldx [%i2 + 0], %o2
55816! move %o2(upper) -> %o2(upper)
55817! move %o2(lower) -> %o2(lower)
55818
55819P5206: !_ST_BINIT [12] (maybe <- 0x2800055) (Int)
55820wr %g0, 0xe2, %asi
55821stwa %l4, [%i2 + 0] %asi
55822add %l4, 1, %l4
55823
55824P5207: !_MEMBAR (Int)
55825membar #StoreLoad
55826
55827P5208: !_CAS [3] (maybe <- 0x2800056) (Int)
55828lduw [%i1], %o3
55829mov %o3, %l6
55830! move %l6(lower) -> %o3(upper)
55831sllx %l6, 32, %o3
55832mov %l4, %l3
55833cas [%i1], %l6, %l3
55834! move %l3(lower) -> %o3(lower)
55835srl %l3, 0, %l6
55836or %l6, %o3, %o3
55837add %l4, 1, %l4
55838
55839P5209: !_PREFETCH [7] (Int)
55840sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
55841sub %i0, %i3, %i3
55842prefetch [%i3 + 4], 22
55843
55844P5210: !_SWAP [8] (maybe <- 0x2800057) (Int)
55845mov %l4, %o4
55846swap [%i3 + 12], %o4
55847! move %o4(lower) -> %o4(upper)
55848sllx %o4, 32, %o4
55849add %l4, 1, %l4
55850
55851P5211: !_CASX [15] (maybe <- 0x2800058) (Int)
55852sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
55853sub %i0, %i2, %i2
55854ldx [%i2], %o5
55855! move %o5(upper) -> %o4(lower)
55856srlx %o5, 32, %l3
55857or %l3, %o4, %o4
55858!---- flushing int results buffer----
55859mov %o0, %l5
55860mov %o1, %l5
55861mov %o2, %l5
55862mov %o3, %l5
55863mov %o4, %l5
55864! move %o5(lower) -> %o0(upper)
55865sllx %o5, 32, %o0
55866mov %o5, %l3
55867sllx %l4, 32, %o5
55868add %l4, 1, %l4
55869or %l4, %o5, %o5
55870casx [%i2], %l3, %o5
55871! move %o5(upper) -> %o0(lower)
55872srlx %o5, 32, %l3
55873or %l3, %o0, %o0
55874! move %o5(lower) -> %o1(upper)
55875sllx %o5, 32, %o1
55876add %l4, 1, %l4
55877
55878P5212: !_MEMBAR (FP)
55879
55880P5213: !_BST [1] (maybe <- 0x42000035) (FP)
55881wr %g0, 0xf0, %asi
55882! preparing store val #0, next val will be in f32
55883fmovs %f16, %f20
55884fadds %f16, %f17, %f16
55885! preparing store val #1, next val will be in f33
55886fmovs %f16, %f21
55887fadds %f16, %f17, %f16
55888! preparing store val #2, next val will be in f35
55889fmovd %f20, %f32
55890fmovs %f16, %f21
55891fadds %f16, %f17, %f16
55892fmovd %f20, %f34
55893membar #Sync
55894stda %f32, [%i0 + 0 ] %asi
55895
55896P5214: !_MEMBAR (FP)
55897membar #StoreLoad
55898
55899P5215: !_LD [1] (Int)
55900lduw [%i0 + 4], %l3
55901! move %l3(lower) -> %o1(lower)
55902or %l3, %o1, %o1
55903
55904P5216: !_PREFETCH [2] (Int) (CBR)
55905prefetch [%i0 + 12], 1
55906
55907! cbranch
55908andcc %l0, 1, %g0
55909be,pt %xcc, TARGET5216
55910nop
55911RET5216:
55912
55913! lfsr step begin
55914srlx %l0, 1, %l6
55915xnor %l6, %l0, %l6
55916sllx %l6, 63, %l6
55917or %l6, %l0, %l0
55918srlx %l0, 1, %l0
55919
55920
55921P5217: !_DWLD [19] (Int)
55922sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
55923sub %i0, %i3, %i3
55924ldx [%i3 + 0], %o2
55925! move %o2(upper) -> %o2(upper)
55926! move %o2(lower) -> %o2(lower)
55927
55928P5218: !_REPLACEMENT [2] (Int)
55929sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
55930add %i0, %i2, %i2
55931sethi %hi(0x20000), %l3
55932ld [%i2+12], %l7
55933st %l7, [%i2+12]
55934add %i2, %l3, %l6
55935ld [%l6+12], %l7
55936st %l7, [%l6+12]
55937add %l6, %l3, %l6
55938ld [%l6+12], %l7
55939st %l7, [%l6+12]
55940add %l6, %l3, %l6
55941ld [%l6+12], %l7
55942st %l7, [%l6+12]
55943add %l6, %l3, %l6
55944ld [%l6+12], %l7
55945st %l7, [%l6+12]
55946add %l6, %l3, %l6
55947ld [%l6+12], %l7
55948st %l7, [%l6+12]
55949add %l6, %l3, %l6
55950ld [%l6+12], %l7
55951st %l7, [%l6+12]
55952add %l6, %l3, %l6
55953ld [%l6+12], %l7
55954st %l7, [%l6+12]
55955
55956P5219: !_PREFETCH [13] (Int)
55957sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
55958sub %i0, %i3, %i3
55959prefetch [%i3 + 4], 22
55960
55961P5220: !_ST_BINIT [14] (maybe <- 0x280005a) (Int) (LE)
55962wr %g0, 0xea, %asi
55963! Change single-word-level endianess (big endian <-> little endian)
55964sethi %hi(0xff00ff00), %l3
55965or %l3, %lo(0xff00ff00), %l3
55966and %l4, %l3, %l6
55967srl %l6, 8, %l6
55968sll %l4, 8, %o5
55969and %o5, %l3, %o5
55970or %o5, %l6, %o5
55971srl %o5, 16, %l6
55972sll %o5, 16, %o5
55973srl %o5, 0, %o5
55974or %o5, %l6, %o5
55975stwa %o5, [%i3 + 12] %asi
55976add %l4, 1, %l4
55977
55978P5221: !_MEMBAR (Int) (LE)
55979membar #StoreLoad
55980
55981P5222: !_ST [3] (maybe <- 0x280005b) (Int)
55982stw %l4, [%i1 + 0 ]
55983add %l4, 1, %l4
55984
55985P5223: !_ST_BINIT [3] (maybe <- 0x280005c) (Int)
55986wr %g0, 0xe2, %asi
55987stwa %l4, [%i1 + 0] %asi
55988add %l4, 1, %l4
55989
55990P5224: !_MEMBAR (Int)
55991
55992P5225: !_BST [12] (maybe <- 0x42000038) (FP)
55993wr %g0, 0xf0, %asi
55994! preparing store val #0, next val will be in f32
55995fmovs %f16, %f20
55996fadds %f16, %f17, %f16
55997! preparing store val #1, next val will be in f33
55998fmovs %f16, %f21
55999fadds %f16, %f17, %f16
56000! preparing store val #2, next val will be in f35
56001fmovd %f20, %f32
56002fmovs %f16, %f21
56003fadds %f16, %f17, %f16
56004fmovd %f20, %f34
56005membar #Sync
56006stda %f32, [%i3 + 0 ] %asi
56007
56008P5226: !_MEMBAR (FP)
56009membar #StoreLoad
56010
56011P5227: !_CAS [10] (maybe <- 0x280005d) (Int) (CBR)
56012sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
56013add %i0, %i2, %i2
56014add %i2, 4, %l3
56015lduw [%l3], %o3
56016mov %o3, %o5
56017! move %o5(lower) -> %o3(upper)
56018sllx %o5, 32, %o3
56019mov %l4, %l7
56020cas [%l3], %o5, %l7
56021! move %l7(lower) -> %o3(lower)
56022srl %l7, 0, %o5
56023or %o5, %o3, %o3
56024add %l4, 1, %l4
56025
56026! cbranch
56027andcc %l0, 1, %g0
56028be,pn %xcc, TARGET5227
56029nop
56030RET5227:
56031
56032! lfsr step begin
56033srlx %l0, 1, %o5
56034xnor %o5, %l0, %o5
56035sllx %o5, 63, %o5
56036or %o5, %l0, %l0
56037srlx %l0, 1, %l0
56038
56039
56040P5228: !_DWST [8] (maybe <- 0x280005e) (Int)
56041sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
56042sub %i0, %i3, %i3
56043mov %l4, %l3
56044stx %l3, [%i3 + 8]
56045add %l4, 1, %l4
56046
56047P5229: !_MEMBAR (FP)
56048membar #StoreLoad
56049
56050P5230: !_BLD [9] (FP)
56051wr %g0, 0xf0, %asi
56052ldda [%i2 + 0] %asi, %f32
56053membar #Sync
56054! 3 addresses covered
56055fmovd %f32, %f18
56056fmovs %f18, %f5
56057fmovs %f19, %f6
56058fmovd %f34, %f18
56059fmovs %f19, %f7
56060
56061P5231: !_MEMBAR (FP)
56062
56063P5232: !_ST [2] (maybe <- 0x280005f) (Int)
56064stw %l4, [%i0 + 12 ]
56065add %l4, 1, %l4
56066
56067P5233: !_REPLACEMENT [15] (Int)
56068sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
56069sub %i0, %i2, %i2
56070sethi %hi(0x20000), %l7
56071ld [%i2+0], %l3
56072st %l3, [%i2+0]
56073add %i2, %l7, %o5
56074ld [%o5+0], %l3
56075st %l3, [%o5+0]
56076add %o5, %l7, %o5
56077ld [%o5+0], %l3
56078st %l3, [%o5+0]
56079add %o5, %l7, %o5
56080ld [%o5+0], %l3
56081st %l3, [%o5+0]
56082add %o5, %l7, %o5
56083ld [%o5+0], %l3
56084st %l3, [%o5+0]
56085add %o5, %l7, %o5
56086ld [%o5+0], %l3
56087st %l3, [%o5+0]
56088add %o5, %l7, %o5
56089ld [%o5+0], %l3
56090st %l3, [%o5+0]
56091add %o5, %l7, %o5
56092ld [%o5+0], %l3
56093st %l3, [%o5+0]
56094
56095P5234: !_MEMBAR (FP)
56096membar #StoreLoad
56097
56098P5235: !_BLD [10] (FP)
56099wr %g0, 0xf0, %asi
56100sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
56101add %i0, %i3, %i3
56102ldda [%i3 + 0] %asi, %f32
56103membar #Sync
56104! 3 addresses covered
56105fmovd %f32, %f8
56106fmovd %f34, %f18
56107fmovs %f19, %f10
56108
56109P5236: !_MEMBAR (FP)
56110
56111P5237: !_PREFETCH [6] (Int)
56112sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
56113sub %i0, %i2, %i2
56114prefetch [%i2 + 0], 22
56115
56116P5238: !_DWST [20] (maybe <- 0x4200003b) (FP)
56117sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
56118sub %i0, %i3, %i3
56119! preparing store val #0, next val will be in f21
56120fmovs %f16, %f21
56121fadds %f16, %f17, %f16
56122std %f20, [%i3 + 8]
56123
56124P5239: !_SWAP [9] (maybe <- 0x2800060) (Int) (CBR)
56125sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
56126add %i0, %i2, %i2
56127mov %l4, %o4
56128swap [%i2 + 0], %o4
56129! move %o4(lower) -> %o4(upper)
56130sllx %o4, 32, %o4
56131add %l4, 1, %l4
56132
56133! cbranch
56134andcc %l0, 1, %g0
56135be,pn %xcc, TARGET5239
56136nop
56137RET5239:
56138
56139! lfsr step begin
56140srlx %l0, 1, %o5
56141xnor %o5, %l0, %o5
56142sllx %o5, 63, %o5
56143or %o5, %l0, %l0
56144srlx %l0, 1, %l0
56145
56146
56147P5240: !_MEMBAR (FP)
56148
56149P5241: !_BSTC [9] (maybe <- 0x4200003c) (FP)
56150wr %g0, 0xe0, %asi
56151! preparing store val #0, next val will be in f32
56152fmovs %f16, %f20
56153fadds %f16, %f17, %f16
56154! preparing store val #1, next val will be in f33
56155fmovs %f16, %f21
56156fadds %f16, %f17, %f16
56157! preparing store val #2, next val will be in f35
56158fmovd %f20, %f32
56159fmovs %f16, %f21
56160fadds %f16, %f17, %f16
56161fmovd %f20, %f34
56162membar #Sync
56163stda %f32, [%i2 + 0 ] %asi
56164
56165P5242: !_MEMBAR (FP)
56166membar #StoreLoad
56167
56168P5243: !_DWST [18] (maybe <- 0x2800061) (Int)
56169sllx %l4, 32, %o5
56170add %l4, 1, %l4
56171or %o5, %l4, %o5
56172stx %o5, [%i3 + 0]
56173add %l4, 1, %l4
56174
56175P5244: !_ST [20] (maybe <- 0x2800063) (Int) (CBR)
56176stw %l4, [%i3 + 12 ]
56177add %l4, 1, %l4
56178
56179! cbranch
56180andcc %l0, 1, %g0
56181be,pn %xcc, TARGET5244
56182nop
56183RET5244:
56184
56185! lfsr step begin
56186srlx %l0, 1, %l6
56187xnor %l6, %l0, %l6
56188sllx %l6, 63, %l6
56189or %l6, %l0, %l0
56190srlx %l0, 1, %l0
56191
56192
56193P5245: !_ST [18] (maybe <- 0x2800064) (Int)
56194stw %l4, [%i3 + 0 ]
56195add %l4, 1, %l4
56196
56197P5246: !_LD [11] (Int)
56198lduw [%i2 + 12], %l7
56199! move %l7(lower) -> %o4(lower)
56200or %l7, %o4, %o4
56201!---- flushing int results buffer----
56202mov %o0, %l5
56203mov %o1, %l5
56204mov %o2, %l5
56205mov %o3, %l5
56206mov %o4, %l5
56207
56208P5247: !_PREFETCH [16] (Int)
56209sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
56210sub %i0, %i3, %i3
56211prefetch [%i3 + 4], 4
56212
56213P5248: !_DWST_BINIT [8] (maybe <- 0x2800065) (Int)
56214wr %g0, 0xe2, %asi
56215sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
56216sub %i0, %i2, %i2
56217mov %l4, %o5
56218stxa %o5, [%i2 + 8] %asi
56219add %l4, 1, %l4
56220
56221P5249: !_MEMBAR (Int)
56222
56223P5250: !_BSTC [9] (maybe <- 0x4200003f) (FP)
56224wr %g0, 0xe0, %asi
56225sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
56226add %i0, %i3, %i3
56227! preparing store val #0, next val will be in f32
56228fmovs %f16, %f20
56229fadds %f16, %f17, %f16
56230! preparing store val #1, next val will be in f33
56231fmovs %f16, %f21
56232fadds %f16, %f17, %f16
56233! preparing store val #2, next val will be in f35
56234fmovd %f20, %f32
56235fmovs %f16, %f21
56236fadds %f16, %f17, %f16
56237fmovd %f20, %f34
56238membar #Sync
56239stda %f32, [%i3 + 0 ] %asi
56240
56241P5251: !_MEMBAR (FP)
56242membar #StoreLoad
56243
56244P5252: !_DWST [21] (maybe <- 0x42000042) (FP)
56245sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
56246add %i0, %i2, %i2
56247! preparing store val #0, next val will be in f20
56248fmovs %f16, %f20
56249fadds %f16, %f17, %f16
56250! preparing store val #1, next val will be in f21
56251fmovs %f16, %f21
56252fadds %f16, %f17, %f16
56253std %f20, [%i2 + 0]
56254
56255P5253: !_MEMBAR (FP)
56256membar #StoreLoad
56257
56258P5254: !_BLD [5] (FP)
56259wr %g0, 0xf0, %asi
56260ldda [%i1 + 0] %asi, %f32
56261membar #Sync
56262! 3 addresses covered
56263fmovd %f32, %f18
56264fmovs %f18, %f11
56265fmovs %f19, %f12
56266fmovd %f34, %f18
56267fmovs %f19, %f13
56268
56269P5255: !_MEMBAR (FP)
56270
56271P5256: !_PREFETCH [14] (Int)
56272sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
56273sub %i0, %i3, %i3
56274prefetch [%i3 + 12], 3
56275
56276P5257: !_MEMBAR (FP)
56277membar #StoreLoad
56278
56279P5258: !_BLD [2] (FP)
56280wr %g0, 0xf0, %asi
56281ldda [%i0 + 0] %asi, %f32
56282membar #Sync
56283! 3 addresses covered
56284fmovd %f32, %f14
56285!---- flushing fp results buffer to %f30 ----
56286fmovd %f0, %f30
56287fmovd %f2, %f30
56288fmovd %f4, %f30
56289fmovd %f6, %f30
56290fmovd %f8, %f30
56291fmovd %f10, %f30
56292fmovd %f12, %f30
56293fmovd %f14, %f30
56294!--
56295fmovd %f34, %f18
56296fmovs %f19, %f0
56297
56298P5259: !_MEMBAR (FP)
56299
56300P5260: !_SWAP [3] (maybe <- 0x2800066) (Int)
56301mov %l4, %o0
56302swap [%i1 + 0], %o0
56303! move %o0(lower) -> %o0(upper)
56304sllx %o0, 32, %o0
56305add %l4, 1, %l4
56306
56307P5261: !_DWST_BINIT [17] (maybe <- 0x2800067) (Int)
56308wr %g0, 0xe2, %asi
56309sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
56310sub %i0, %i2, %i2
56311mov %l4, %o5
56312stxa %o5, [%i2 + 8] %asi
56313add %l4, 1, %l4
56314
56315P5262: !_MEMBAR (Int)
56316
56317P5263: !_BST [14] (maybe <- 0x42000044) (FP)
56318wr %g0, 0xf0, %asi
56319! preparing store val #0, next val will be in f32
56320fmovs %f16, %f20
56321fadds %f16, %f17, %f16
56322! preparing store val #1, next val will be in f33
56323fmovs %f16, %f21
56324fadds %f16, %f17, %f16
56325! preparing store val #2, next val will be in f35
56326fmovd %f20, %f32
56327fmovs %f16, %f21
56328fadds %f16, %f17, %f16
56329fmovd %f20, %f34
56330membar #Sync
56331stda %f32, [%i3 + 0 ] %asi
56332
56333P5264: !_MEMBAR (FP)
56334
56335P5265: !_BST [9] (maybe <- 0x42000047) (FP)
56336wr %g0, 0xf0, %asi
56337sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
56338add %i0, %i3, %i3
56339! preparing store val #0, next val will be in f32
56340fmovs %f16, %f20
56341fadds %f16, %f17, %f16
56342! preparing store val #1, next val will be in f33
56343fmovs %f16, %f21
56344fadds %f16, %f17, %f16
56345! preparing store val #2, next val will be in f35
56346fmovd %f20, %f32
56347fmovs %f16, %f21
56348fadds %f16, %f17, %f16
56349fmovd %f20, %f34
56350membar #Sync
56351stda %f32, [%i3 + 0 ] %asi
56352
56353P5266: !_MEMBAR (FP)
56354membar #StoreLoad
56355
56356P5267: !_CAS [14] (maybe <- 0x2800068) (Int)
56357sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
56358sub %i0, %i2, %i2
56359add %i2, 12, %l6
56360lduw [%l6], %o5
56361mov %o5, %l3
56362! move %l3(lower) -> %o0(lower)
56363or %l3, %o0, %o0
56364mov %l4, %o1
56365cas [%l6], %l3, %o1
56366! move %o1(lower) -> %o1(upper)
56367sllx %o1, 32, %o1
56368add %l4, 1, %l4
56369
56370P5268: !_ST [21] (maybe <- 0x2800069) (Int)
56371sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
56372add %i0, %i3, %i3
56373stw %l4, [%i3 + 0 ]
56374add %l4, 1, %l4
56375
56376P5269: !_MEMBAR (FP)
56377
56378P5270: !_BSTC [11] (maybe <- 0x4200004a) (FP)
56379wr %g0, 0xe0, %asi
56380sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
56381add %i0, %i2, %i2
56382! preparing store val #0, next val will be in f32
56383fmovs %f16, %f20
56384fadds %f16, %f17, %f16
56385! preparing store val #1, next val will be in f33
56386fmovs %f16, %f21
56387fadds %f16, %f17, %f16
56388! preparing store val #2, next val will be in f35
56389fmovd %f20, %f32
56390fmovs %f16, %f21
56391fadds %f16, %f17, %f16
56392fmovd %f20, %f34
56393membar #Sync
56394stda %f32, [%i2 + 0 ] %asi
56395
56396P5271: !_MEMBAR (FP)
56397membar #StoreLoad
56398
56399P5272: !_REPLACEMENT [1] (Int)
56400sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
56401add %i0, %i3, %i3
56402sethi %hi(0x20000), %o5
56403ld [%i3+4], %l6
56404st %l6, [%i3+4]
56405add %i3, %o5, %l3
56406ld [%l3+4], %l6
56407st %l6, [%l3+4]
56408add %l3, %o5, %l3
56409ld [%l3+4], %l6
56410st %l6, [%l3+4]
56411add %l3, %o5, %l3
56412ld [%l3+4], %l6
56413st %l6, [%l3+4]
56414add %l3, %o5, %l3
56415ld [%l3+4], %l6
56416st %l6, [%l3+4]
56417add %l3, %o5, %l3
56418ld [%l3+4], %l6
56419st %l6, [%l3+4]
56420add %l3, %o5, %l3
56421ld [%l3+4], %l6
56422st %l6, [%l3+4]
56423add %l3, %o5, %l3
56424ld [%l3+4], %l6
56425st %l6, [%l3+4]
56426
56427P5273: !_DWLD [12] (Int)
56428sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
56429sub %i0, %i2, %i2
56430ldx [%i2 + 0], %o5
56431! move %o5(upper) -> %o1(lower)
56432srlx %o5, 32, %l7
56433or %l7, %o1, %o1
56434! move %o5(lower) -> %o2(upper)
56435sllx %o5, 32, %o2
56436
56437P5274: !_PREFETCH [17] (Int)
56438sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
56439sub %i0, %i3, %i3
56440prefetch [%i3 + 12], 2
56441
56442P5275: !_MEMBAR (FP)
56443membar #StoreLoad
56444
56445P5276: !_BLD [11] (FP)
56446wr %g0, 0xf0, %asi
56447sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
56448add %i0, %i2, %i2
56449ldda [%i2 + 0] %asi, %f32
56450membar #Sync
56451! 3 addresses covered
56452fmovd %f32, %f18
56453fmovs %f18, %f1
56454fmovs %f19, %f2
56455fmovd %f34, %f18
56456fmovs %f19, %f3
56457
56458P5277: !_MEMBAR (FP)
56459
56460P5278: !_CAS [8] (maybe <- 0x280006a) (Int)
56461sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
56462sub %i0, %i3, %i3
56463add %i3, 12, %l6
56464lduw [%l6], %o5
56465mov %o5, %l3
56466! move %l3(lower) -> %o2(lower)
56467or %l3, %o2, %o2
56468mov %l4, %o3
56469cas [%l6], %l3, %o3
56470! move %o3(lower) -> %o3(upper)
56471sllx %o3, 32, %o3
56472add %l4, 1, %l4
56473
56474P5279: !_DWLD [16] (Int)
56475sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
56476sub %i0, %i2, %i2
56477ldx [%i2 + 0], %l6
56478! move %l6(upper) -> %o3(lower)
56479srlx %l6, 32, %l3
56480or %l3, %o3, %o3
56481! move %l6(lower) -> %o4(upper)
56482sllx %l6, 32, %o4
56483
56484P5280: !_DWST_BINIT [11] (maybe <- 0x280006b) (Int)
56485wr %g0, 0xe2, %asi
56486sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
56487add %i0, %i3, %i3
56488mov %l4, %l7
56489stxa %l7, [%i3 + 8] %asi
56490add %l4, 1, %l4
56491
56492P5281: !_MEMBAR (Int)
56493membar #StoreLoad
56494
56495P5282: !_DWST [16] (maybe <- 0x280006c) (Int)
56496sllx %l4, 32, %l6
56497add %l4, 1, %l4
56498or %l6, %l4, %l6
56499stx %l6, [%i2 + 0]
56500add %l4, 1, %l4
56501
56502P5283: !_PREFETCH [6] (Int)
56503sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
56504sub %i0, %i2, %i2
56505prefetch [%i2 + 0], 24
56506
56507P5284: !_ST [4] (maybe <- 0x280006e) (Int)
56508stw %l4, [%i1 + 4 ]
56509add %l4, 1, %l4
56510
56511P5285: !_SWAP [7] (maybe <- 0x280006f) (Int)
56512mov %l4, %l6
56513swap [%i2 + 4], %l6
56514! move %l6(lower) -> %o4(lower)
56515srl %l6, 0, %o5
56516or %o5, %o4, %o4
56517!---- flushing int results buffer----
56518mov %o0, %l5
56519mov %o1, %l5
56520mov %o2, %l5
56521mov %o3, %l5
56522mov %o4, %l5
56523add %l4, 1, %l4
56524
56525P5286: !_LD [11] (Int)
56526lduw [%i3 + 12], %o0
56527! move %o0(lower) -> %o0(upper)
56528sllx %o0, 32, %o0
56529
56530P5287: !_CASX [7] (maybe <- 0x2800070) (Int)
56531ldx [%i2], %o5
56532! move %o5(upper) -> %o0(lower)
56533srlx %o5, 32, %l3
56534or %l3, %o0, %o0
56535! move %o5(lower) -> %o1(upper)
56536sllx %o5, 32, %o1
56537mov %o5, %l3
56538sllx %l4, 32, %o5
56539add %l4, 1, %l4
56540or %l4, %o5, %o5
56541casx [%i2], %l3, %o5
56542! move %o5(upper) -> %o1(lower)
56543srlx %o5, 32, %l3
56544or %l3, %o1, %o1
56545! move %o5(lower) -> %o2(upper)
56546sllx %o5, 32, %o2
56547add %l4, 1, %l4
56548
56549P5288: !_MEMBAR (FP)
56550
56551P5289: !_BSTC [9] (maybe <- 0x4200004d) (FP)
56552wr %g0, 0xe0, %asi
56553! preparing store val #0, next val will be in f32
56554fmovs %f16, %f20
56555fadds %f16, %f17, %f16
56556! preparing store val #1, next val will be in f33
56557fmovs %f16, %f21
56558fadds %f16, %f17, %f16
56559! preparing store val #2, next val will be in f35
56560fmovd %f20, %f32
56561fmovs %f16, %f21
56562fadds %f16, %f17, %f16
56563fmovd %f20, %f34
56564membar #Sync
56565stda %f32, [%i3 + 0 ] %asi
56566
56567P5290: !_MEMBAR (FP)
56568
56569P5291: !_BSTC [8] (maybe <- 0x42000050) (FP)
56570wr %g0, 0xe0, %asi
56571! preparing store val #0, next val will be in f32
56572fmovs %f16, %f20
56573fadds %f16, %f17, %f16
56574! preparing store val #1, next val will be in f33
56575fmovs %f16, %f21
56576fadds %f16, %f17, %f16
56577! preparing store val #2, next val will be in f35
56578fmovd %f20, %f32
56579fmovs %f16, %f21
56580fadds %f16, %f17, %f16
56581fmovd %f20, %f34
56582membar #Sync
56583stda %f32, [%i2 + 0 ] %asi
56584
56585P5292: !_MEMBAR (FP)
56586
56587P5293: !_BST [18] (maybe <- 0x42000053) (FP)
56588wr %g0, 0xf0, %asi
56589sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
56590sub %i0, %i3, %i3
56591! preparing store val #0, next val will be in f32
56592fmovs %f16, %f20
56593fadds %f16, %f17, %f16
56594! preparing store val #1, next val will be in f33
56595fmovs %f16, %f21
56596fadds %f16, %f17, %f16
56597! preparing store val #2, next val will be in f35
56598fmovd %f20, %f32
56599fmovs %f16, %f21
56600fadds %f16, %f17, %f16
56601fmovd %f20, %f34
56602membar #Sync
56603stda %f32, [%i3 + 0 ] %asi
56604
56605P5294: !_MEMBAR (FP)
56606membar #StoreLoad
56607
56608P5295: !_ST [1] (maybe <- 0x2800072) (Int) (CBR)
56609stw %l4, [%i0 + 4 ]
56610add %l4, 1, %l4
56611
56612! cbranch
56613andcc %l0, 1, %g0
56614be,pn %xcc, TARGET5295
56615nop
56616RET5295:
56617
56618! lfsr step begin
56619srlx %l0, 1, %l3
56620xnor %l3, %l0, %l3
56621sllx %l3, 63, %l3
56622or %l3, %l0, %l0
56623srlx %l0, 1, %l0
56624
56625
56626P5296: !_SWAP [17] (maybe <- 0x2800073) (Int)
56627sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
56628sub %i0, %i2, %i2
56629mov %l4, %o5
56630swap [%i2 + 12], %o5
56631! move %o5(lower) -> %o2(lower)
56632srl %o5, 0, %l6
56633or %l6, %o2, %o2
56634add %l4, 1, %l4
56635
56636P5297: !_MEMBAR (FP)
56637
56638P5298: !_BSTC [22] (maybe <- 0x42000056) (FP)
56639wr %g0, 0xe0, %asi
56640sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
56641add %i0, %i3, %i3
56642! preparing store val #0, next val will be in f32
56643fmovs %f16, %f20
56644fadds %f16, %f17, %f16
56645! preparing store val #1, next val will be in f33
56646fmovs %f16, %f21
56647fadds %f16, %f17, %f16
56648! preparing store val #2, next val will be in f35
56649fmovd %f20, %f32
56650fmovs %f16, %f21
56651fadds %f16, %f17, %f16
56652fmovd %f20, %f34
56653membar #Sync
56654stda %f32, [%i3 + 0 ] %asi
56655
56656P5299: !_MEMBAR (FP)
56657membar #StoreLoad
56658
56659P5300: !_SWAP [22] (maybe <- 0x2800074) (Int)
56660mov %l4, %o3
56661swap [%i3 + 4], %o3
56662! move %o3(lower) -> %o3(upper)
56663sllx %o3, 32, %o3
56664add %l4, 1, %l4
56665
56666P5301: !_DWST [14] (maybe <- 0x2800075) (Int)
56667sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
56668sub %i0, %i2, %i2
56669mov %l4, %l7
56670stx %l7, [%i2 + 8]
56671add %l4, 1, %l4
56672
56673P5302: !_MEMBAR (FP)
56674
56675P5303: !_BST [17] (maybe <- 0x42000059) (FP)
56676wr %g0, 0xf0, %asi
56677sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
56678sub %i0, %i3, %i3
56679! preparing store val #0, next val will be in f32
56680fmovs %f16, %f20
56681fadds %f16, %f17, %f16
56682! preparing store val #1, next val will be in f33
56683fmovs %f16, %f21
56684fadds %f16, %f17, %f16
56685! preparing store val #2, next val will be in f35
56686fmovd %f20, %f32
56687fmovs %f16, %f21
56688fadds %f16, %f17, %f16
56689fmovd %f20, %f34
56690membar #Sync
56691stda %f32, [%i3 + 0 ] %asi
56692
56693P5304: !_MEMBAR (FP)
56694membar #StoreLoad
56695
56696P5305: !_BLD [10] (FP)
56697wr %g0, 0xf0, %asi
56698sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
56699add %i0, %i2, %i2
56700ldda [%i2 + 0] %asi, %f32
56701membar #Sync
56702! 3 addresses covered
56703fmovd %f32, %f4
56704fmovd %f34, %f18
56705fmovs %f19, %f6
56706
56707P5306: !_MEMBAR (FP)
56708
56709P5307: !_DWLD [12] (Int)
56710sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
56711sub %i0, %i3, %i3
56712ldx [%i3 + 0], %l6
56713! move %l6(upper) -> %o3(lower)
56714srlx %l6, 32, %l3
56715or %l3, %o3, %o3
56716! move %l6(lower) -> %o4(upper)
56717sllx %l6, 32, %o4
56718
56719P5308: !_LDD [15] (Int)
56720sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
56721sub %i0, %i2, %i2
56722ldd [%i2 + 0], %l6
56723! move %l6(lower) -> %o4(lower)
56724or %l6, %o4, %o4
56725!---- flushing int results buffer----
56726mov %o0, %l5
56727mov %o1, %l5
56728mov %o2, %l5
56729mov %o3, %l5
56730mov %o4, %l5
56731! move %l7(lower) -> %o0(upper)
56732sllx %l7, 32, %o0
56733
56734P5309: !_DWST_BINIT [23] (maybe <- 0x2800076) (Int)
56735wr %g0, 0xe2, %asi
56736sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
56737add %i0, %i3, %i3
56738mov %l4, %l3
56739stxa %l3, [%i3 + 8] %asi
56740add %l4, 1, %l4
56741
56742P5310: !_MEMBAR (Int)
56743
56744P5311: !_BSTC [3] (maybe <- 0x4200005c) (FP)
56745wr %g0, 0xe0, %asi
56746! preparing store val #0, next val will be in f32
56747fmovs %f16, %f20
56748fadds %f16, %f17, %f16
56749! preparing store val #1, next val will be in f33
56750fmovs %f16, %f21
56751fadds %f16, %f17, %f16
56752! preparing store val #2, next val will be in f35
56753fmovd %f20, %f32
56754fmovs %f16, %f21
56755fadds %f16, %f17, %f16
56756fmovd %f20, %f34
56757membar #Sync
56758stda %f32, [%i1 + 0 ] %asi
56759
56760P5312: !_MEMBAR (FP)
56761membar #StoreLoad
56762
56763P5313: !_DWST [11] (maybe <- 0x2800077) (Int)
56764sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
56765add %i0, %i2, %i2
56766mov %l4, %l7
56767stx %l7, [%i2 + 8]
56768add %l4, 1, %l4
56769
56770P5314: !_SWAP [19] (maybe <- 0x2800078) (Int) (Branch target of P5873)
56771sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
56772sub %i0, %i3, %i3
56773mov %l4, %o5
56774swap [%i3 + 4], %o5
56775! move %o5(lower) -> %o0(lower)
56776srl %o5, 0, %l6
56777or %l6, %o0, %o0
56778add %l4, 1, %l4
56779ba P5315
56780nop
56781
56782TARGET5873:
56783ba RET5873
56784nop
56785
56786
56787P5315: !_LDD [19] (Int)
56788ldd [%i3 + 0], %l6
56789! move %l6(lower) -> %o1(upper)
56790sllx %l6, 32, %o1
56791! move %l7(lower) -> %o1(lower)
56792or %l7, %o1, %o1
56793
56794P5316: !_CAS [1] (maybe <- 0x2800079) (Int)
56795add %i0, 4, %l6
56796lduw [%l6], %o2
56797mov %o2, %l3
56798! move %l3(lower) -> %o2(upper)
56799sllx %l3, 32, %o2
56800mov %l4, %o5
56801cas [%l6], %l3, %o5
56802! move %o5(lower) -> %o2(lower)
56803srl %o5, 0, %l3
56804or %l3, %o2, %o2
56805add %l4, 1, %l4
56806
56807P5317: !_DWST_BINIT [9] (maybe <- 0x280007a) (Int)
56808wr %g0, 0xe2, %asi
56809sllx %l4, 32, %l3
56810add %l4, 1, %l4
56811or %l3, %l4, %l3
56812stxa %l3, [%i2 + 0] %asi
56813add %l4, 1, %l4
56814
56815P5318: !_MEMBAR (Int)
56816membar #StoreLoad
56817
56818P5319: !_DWLD [23] (Int)
56819sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
56820add %i0, %i2, %i2
56821ldx [%i2 + 8], %o3
56822! move %o3(lower) -> %o3(upper)
56823sllx %o3, 32, %o3
56824
56825P5320: !_ST [7] (maybe <- 0x280007c) (Int)
56826sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
56827sub %i0, %i3, %i3
56828stw %l4, [%i3 + 4 ]
56829add %l4, 1, %l4
56830
56831P5321: !_DWLD [20] (Int)
56832sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
56833sub %i0, %i2, %i2
56834ldx [%i2 + 8], %l6
56835! move %l6(lower) -> %o3(lower)
56836srl %l6, 0, %l3
56837or %l3, %o3, %o3
56838
56839P5322: !_LD [22] (Int)
56840sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
56841add %i0, %i3, %i3
56842lduw [%i3 + 4], %o4
56843! move %o4(lower) -> %o4(upper)
56844sllx %o4, 32, %o4
56845
56846P5323: !_REPLACEMENT [10] (Int)
56847sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
56848sub %i0, %i2, %i2
56849sethi %hi(0x20000), %l3
56850ld [%i2+4], %l7
56851st %l7, [%i2+4]
56852add %i2, %l3, %l6
56853ld [%l6+4], %l7
56854st %l7, [%l6+4]
56855add %l6, %l3, %l6
56856ld [%l6+4], %l7
56857st %l7, [%l6+4]
56858add %l6, %l3, %l6
56859ld [%l6+4], %l7
56860st %l7, [%l6+4]
56861add %l6, %l3, %l6
56862ld [%l6+4], %l7
56863st %l7, [%l6+4]
56864add %l6, %l3, %l6
56865ld [%l6+4], %l7
56866st %l7, [%l6+4]
56867add %l6, %l3, %l6
56868ld [%l6+4], %l7
56869st %l7, [%l6+4]
56870add %l6, %l3, %l6
56871ld [%l6+4], %l7
56872st %l7, [%l6+4]
56873
56874P5324: !_ST_BINIT [8] (maybe <- 0x280007d) (Int)
56875wr %g0, 0xe2, %asi
56876sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
56877sub %i0, %i3, %i3
56878stwa %l4, [%i3 + 12] %asi
56879add %l4, 1, %l4
56880
56881P5325: !_MEMBAR (Int)
56882membar #StoreLoad
56883
56884P5326: !_CASX [20] (maybe <- 0x280007e) (Int)
56885sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
56886sub %i0, %i2, %i2
56887add %i2, 8, %o5
56888ldx [%o5], %l6
56889! move %l6(upper) -> %o4(lower)
56890srlx %l6, 32, %l7
56891or %l7, %o4, %o4
56892!---- flushing int results buffer----
56893mov %o0, %l5
56894mov %o1, %l5
56895mov %o2, %l5
56896mov %o3, %l5
56897mov %o4, %l5
56898! move %l6(lower) -> %o0(upper)
56899sllx %l6, 32, %o0
56900mov %l6, %l7
56901mov %l4, %l6
56902casx [%o5], %l7, %l6
56903! move %l6(upper) -> %o0(lower)
56904srlx %l6, 32, %l7
56905or %l7, %o0, %o0
56906! move %l6(lower) -> %o1(upper)
56907sllx %l6, 32, %o1
56908add %l4, 1, %l4
56909
56910P5327: !_LDD [7] (Int)
56911ldd [%i3 + 0], %l6
56912! move %l6(lower) -> %o1(lower)
56913or %l6, %o1, %o1
56914! move %l7(lower) -> %o2(upper)
56915sllx %l7, 32, %o2
56916
56917P5328: !_PREFETCH [4] (Int)
56918prefetch [%i1 + 4], 2
56919
56920P5329: !_ST [19] (maybe <- 0x280007f) (Int) (LE)
56921wr %g0, 0x88, %asi
56922! Change single-word-level endianess (big endian <-> little endian)
56923sethi %hi(0xff00ff00), %l6
56924or %l6, %lo(0xff00ff00), %l6
56925and %l4, %l6, %l7
56926srl %l7, 8, %l7
56927sll %l4, 8, %l3
56928and %l3, %l6, %l3
56929or %l3, %l7, %l3
56930srl %l3, 16, %l7
56931sll %l3, 16, %l3
56932srl %l3, 0, %l3
56933or %l3, %l7, %l3
56934stwa %l3, [%i2 + 4] %asi
56935add %l4, 1, %l4
56936
56937P5330: !_ST_BINIT [22] (maybe <- 0x2800080) (Int)
56938wr %g0, 0xe2, %asi
56939sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
56940add %i0, %i3, %i3
56941stwa %l4, [%i3 + 4] %asi
56942add %l4, 1, %l4
56943
56944P5331: !_MEMBAR (Int)
56945membar #StoreLoad
56946
56947P5332: !_ST [10] (maybe <- 0x2800081) (Int)
56948sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
56949add %i0, %i2, %i2
56950stw %l4, [%i2 + 4 ]
56951add %l4, 1, %l4
56952
56953P5333: !_LD [7] (Int)
56954sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
56955sub %i0, %i3, %i3
56956lduw [%i3 + 4], %o5
56957! move %o5(lower) -> %o2(lower)
56958or %o5, %o2, %o2
56959
56960P5334: !_SWAP [10] (maybe <- 0x2800082) (Int)
56961mov %l4, %o3
56962swap [%i2 + 4], %o3
56963! move %o3(lower) -> %o3(upper)
56964sllx %o3, 32, %o3
56965add %l4, 1, %l4
56966
56967P5335: !_MEMBAR (FP)
56968
56969P5336: !_BST [10] (maybe <- 0x4200005f) (FP)
56970wr %g0, 0xf0, %asi
56971! preparing store val #0, next val will be in f32
56972fmovs %f16, %f20
56973fadds %f16, %f17, %f16
56974! preparing store val #1, next val will be in f33
56975fmovs %f16, %f21
56976fadds %f16, %f17, %f16
56977! preparing store val #2, next val will be in f35
56978fmovd %f20, %f32
56979fmovs %f16, %f21
56980fadds %f16, %f17, %f16
56981fmovd %f20, %f34
56982membar #Sync
56983stda %f32, [%i2 + 0 ] %asi
56984
56985P5337: !_MEMBAR (FP)
56986membar #StoreLoad
56987
56988P5338: !_CASX [4] (maybe <- 0x2800083) (Int)
56989ldx [%i1], %l6
56990! move %l6(upper) -> %o3(lower)
56991srlx %l6, 32, %l7
56992or %l7, %o3, %o3
56993! move %l6(lower) -> %o4(upper)
56994sllx %l6, 32, %o4
56995mov %l6, %l7
56996sllx %l4, 32, %l6
56997add %l4, 1, %l4
56998or %l4, %l6, %l6
56999casx [%i1], %l7, %l6
57000! move %l6(upper) -> %o4(lower)
57001srlx %l6, 32, %l7
57002or %l7, %o4, %o4
57003!---- flushing int results buffer----
57004mov %o0, %l5
57005mov %o1, %l5
57006mov %o2, %l5
57007mov %o3, %l5
57008mov %o4, %l5
57009! move %l6(lower) -> %o0(upper)
57010sllx %l6, 32, %o0
57011add %l4, 1, %l4
57012
57013P5339: !_ST_BINIT [2] (maybe <- 0x2800085) (Int)
57014wr %g0, 0xe2, %asi
57015stwa %l4, [%i0 + 12] %asi
57016add %l4, 1, %l4
57017
57018P5340: !_MEMBAR (Int)
57019membar #StoreLoad
57020
57021P5341: !_DWST [4] (maybe <- 0x2800086) (Int)
57022sllx %l4, 32, %l6
57023add %l4, 1, %l4
57024or %l6, %l4, %l6
57025stx %l6, [%i1 + 0]
57026add %l4, 1, %l4
57027
57028P5342: !_LDD [9] (Int)
57029ldd [%i2 + 0], %l6
57030! move %l6(lower) -> %o0(lower)
57031or %l6, %o0, %o0
57032! move %l7(lower) -> %o1(upper)
57033sllx %l7, 32, %o1
57034
57035P5343: !_REPLACEMENT [13] (Int)
57036sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
57037sub %i0, %i2, %i2
57038sethi %hi(0x20000), %l3
57039ld [%i2+4], %l7
57040st %l7, [%i2+4]
57041add %i2, %l3, %l6
57042ld [%l6+4], %l7
57043st %l7, [%l6+4]
57044add %l6, %l3, %l6
57045ld [%l6+4], %l7
57046st %l7, [%l6+4]
57047add %l6, %l3, %l6
57048ld [%l6+4], %l7
57049st %l7, [%l6+4]
57050add %l6, %l3, %l6
57051ld [%l6+4], %l7
57052st %l7, [%l6+4]
57053add %l6, %l3, %l6
57054ld [%l6+4], %l7
57055st %l7, [%l6+4]
57056add %l6, %l3, %l6
57057ld [%l6+4], %l7
57058st %l7, [%l6+4]
57059add %l6, %l3, %l6
57060ld [%l6+4], %l7
57061st %l7, [%l6+4]
57062
57063P5344: !_LDD [0] (Int) (Branch target of P5086)
57064ldd [%i0 + 0], %l6
57065! move %l6(lower) -> %o1(lower)
57066or %l6, %o1, %o1
57067! move %l7(lower) -> %o2(upper)
57068sllx %l7, 32, %o2
57069ba P5345
57070nop
57071
57072TARGET5086:
57073ba RET5086
57074nop
57075
57076
57077P5345: !_MEMBAR (FP)
57078
57079P5346: !_BSTC [13] (maybe <- 0x42000062) (FP)
57080wr %g0, 0xe0, %asi
57081sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
57082sub %i0, %i3, %i3
57083! preparing store val #0, next val will be in f32
57084fmovs %f16, %f20
57085fadds %f16, %f17, %f16
57086! preparing store val #1, next val will be in f33
57087fmovs %f16, %f21
57088fadds %f16, %f17, %f16
57089! preparing store val #2, next val will be in f35
57090fmovd %f20, %f32
57091fmovs %f16, %f21
57092fadds %f16, %f17, %f16
57093fmovd %f20, %f34
57094membar #Sync
57095stda %f32, [%i3 + 0 ] %asi
57096
57097P5347: !_MEMBAR (FP)
57098membar #StoreLoad
57099
57100P5348: !_LDD [8] (Int) (CBR)
57101sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
57102sub %i0, %i2, %i2
57103ldd [%i2 + 8], %l6
57104! move %l7(lower) -> %o2(lower)
57105or %l7, %o2, %o2
57106
57107! cbranch
57108andcc %l0, 1, %g0
57109be,pn %xcc, TARGET5348
57110nop
57111RET5348:
57112
57113! lfsr step begin
57114srlx %l0, 1, %l3
57115xnor %l3, %l0, %l3
57116sllx %l3, 63, %l3
57117or %l3, %l0, %l0
57118srlx %l0, 1, %l0
57119
57120
57121P5349: !_ST [20] (maybe <- 0x2800088) (Int)
57122sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
57123sub %i0, %i3, %i3
57124stw %l4, [%i3 + 12 ]
57125add %l4, 1, %l4
57126
57127P5350: !_DWST_BINIT [22] (maybe <- 0x2800089) (Int) (CBR)
57128wr %g0, 0xe2, %asi
57129sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
57130add %i0, %i2, %i2
57131sllx %l4, 32, %l3
57132add %l4, 1, %l4
57133or %l3, %l4, %l3
57134stxa %l3, [%i2 + 0] %asi
57135add %l4, 1, %l4
57136
57137! cbranch
57138andcc %l0, 1, %g0
57139be,pn %xcc, TARGET5350
57140nop
57141RET5350:
57142
57143! lfsr step begin
57144srlx %l0, 1, %o5
57145xnor %o5, %l0, %o5
57146sllx %o5, 63, %o5
57147or %o5, %l0, %l0
57148srlx %l0, 1, %l0
57149
57150
57151P5351: !_MEMBAR (Int)
57152membar #StoreLoad
57153
57154P5352: !_ST_BINIT [22] (maybe <- 0x280008b) (Int)
57155wr %g0, 0xe2, %asi
57156stwa %l4, [%i2 + 4] %asi
57157add %l4, 1, %l4
57158
57159P5353: !_MEMBAR (Int)
57160membar #StoreLoad
57161
57162P5354: !_PREFETCH [23] (Int)
57163prefetch [%i2 + 12], 29
57164
57165P5355: !_MEMBAR (FP)
57166
57167P5356: !_BSTC [20] (maybe <- 0x42000065) (FP)
57168wr %g0, 0xe0, %asi
57169! preparing store val #0, next val will be in f32
57170fmovs %f16, %f20
57171fadds %f16, %f17, %f16
57172! preparing store val #1, next val will be in f33
57173fmovs %f16, %f21
57174fadds %f16, %f17, %f16
57175! preparing store val #2, next val will be in f35
57176fmovd %f20, %f32
57177fmovs %f16, %f21
57178fadds %f16, %f17, %f16
57179fmovd %f20, %f34
57180membar #Sync
57181stda %f32, [%i3 + 0 ] %asi
57182
57183P5357: !_MEMBAR (FP)
57184membar #StoreLoad
57185
57186P5358: !_DWST_BINIT [22] (maybe <- 0x280008c) (Int)
57187wr %g0, 0xe2, %asi
57188sllx %l4, 32, %l7
57189add %l4, 1, %l4
57190or %l7, %l4, %l7
57191stxa %l7, [%i2 + 0] %asi
57192add %l4, 1, %l4
57193
57194P5359: !_MEMBAR (Int)
57195membar #StoreLoad
57196
57197P5360: !_CAS [2] (maybe <- 0x280008e) (Int)
57198add %i0, 12, %l7
57199lduw [%l7], %o3
57200mov %o3, %l6
57201! move %l6(lower) -> %o3(upper)
57202sllx %l6, 32, %o3
57203mov %l4, %l3
57204cas [%l7], %l6, %l3
57205! move %l3(lower) -> %o3(lower)
57206srl %l3, 0, %l6
57207or %l6, %o3, %o3
57208add %l4, 1, %l4
57209
57210P5361: !_MEMBAR (FP)
57211
57212P5362: !_BST [22] (maybe <- 0x42000068) (FP)
57213wr %g0, 0xf0, %asi
57214! preparing store val #0, next val will be in f32
57215fmovs %f16, %f20
57216fadds %f16, %f17, %f16
57217! preparing store val #1, next val will be in f33
57218fmovs %f16, %f21
57219fadds %f16, %f17, %f16
57220! preparing store val #2, next val will be in f35
57221fmovd %f20, %f32
57222fmovs %f16, %f21
57223fadds %f16, %f17, %f16
57224fmovd %f20, %f34
57225membar #Sync
57226stda %f32, [%i2 + 0 ] %asi
57227
57228P5363: !_MEMBAR (FP)
57229membar #StoreLoad
57230
57231P5364: !_SWAP [4] (maybe <- 0x280008f) (Int)
57232mov %l4, %o4
57233swap [%i1 + 4], %o4
57234! move %o4(lower) -> %o4(upper)
57235sllx %o4, 32, %o4
57236add %l4, 1, %l4
57237
57238P5365: !_ST_BINIT [18] (maybe <- 0x2800090) (Int)
57239wr %g0, 0xe2, %asi
57240stwa %l4, [%i3 + 0] %asi
57241add %l4, 1, %l4
57242
57243P5366: !_MEMBAR (Int) (CBR)
57244membar #StoreLoad
57245
57246! cbranch
57247andcc %l0, 1, %g0
57248be,pn %xcc, TARGET5366
57249nop
57250RET5366:
57251
57252! lfsr step begin
57253srlx %l0, 1, %l7
57254xnor %l7, %l0, %l7
57255sllx %l7, 63, %l7
57256or %l7, %l0, %l0
57257srlx %l0, 1, %l0
57258
57259
57260P5367: !_REPLACEMENT [23] (Int) (CBR)
57261sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
57262add %i0, %i3, %i3
57263sethi %hi(0x20000), %o5
57264ld [%i3+12], %l6
57265st %l6, [%i3+12]
57266add %i3, %o5, %l3
57267ld [%l3+12], %l6
57268st %l6, [%l3+12]
57269add %l3, %o5, %l3
57270ld [%l3+12], %l6
57271st %l6, [%l3+12]
57272add %l3, %o5, %l3
57273ld [%l3+12], %l6
57274st %l6, [%l3+12]
57275add %l3, %o5, %l3
57276ld [%l3+12], %l6
57277st %l6, [%l3+12]
57278add %l3, %o5, %l3
57279ld [%l3+12], %l6
57280st %l6, [%l3+12]
57281add %l3, %o5, %l3
57282ld [%l3+12], %l6
57283st %l6, [%l3+12]
57284add %l3, %o5, %l3
57285ld [%l3+12], %l6
57286st %l6, [%l3+12]
57287
57288! cbranch
57289andcc %l0, 1, %g0
57290be,pt %xcc, TARGET5367
57291nop
57292RET5367:
57293
57294! lfsr step begin
57295srlx %l0, 1, %l7
57296xnor %l7, %l0, %l7
57297sllx %l7, 63, %l7
57298or %l7, %l0, %l0
57299srlx %l0, 1, %l0
57300
57301
57302P5368: !_REPLACEMENT [7] (Int)
57303sethi %hi(0x20000), %o5
57304ld [%i3+4], %l6
57305st %l6, [%i3+4]
57306add %i3, %o5, %l3
57307ld [%l3+4], %l6
57308st %l6, [%l3+4]
57309add %l3, %o5, %l3
57310ld [%l3+4], %l6
57311st %l6, [%l3+4]
57312add %l3, %o5, %l3
57313ld [%l3+4], %l6
57314st %l6, [%l3+4]
57315add %l3, %o5, %l3
57316ld [%l3+4], %l6
57317st %l6, [%l3+4]
57318add %l3, %o5, %l3
57319ld [%l3+4], %l6
57320st %l6, [%l3+4]
57321add %l3, %o5, %l3
57322ld [%l3+4], %l6
57323st %l6, [%l3+4]
57324add %l3, %o5, %l3
57325ld [%l3+4], %l6
57326st %l6, [%l3+4]
57327
57328P5369: !_PREFETCH [19] (Int)
57329sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
57330sub %i0, %i2, %i2
57331prefetch [%i2 + 4], 1
57332
57333P5370: !_CAS [3] (maybe <- 0x2800091) (Int)
57334lduw [%i1], %l6
57335mov %l6, %l7
57336! move %l7(lower) -> %o4(lower)
57337or %l7, %o4, %o4
57338!---- flushing int results buffer----
57339mov %o0, %l5
57340mov %o1, %l5
57341mov %o2, %l5
57342mov %o3, %l5
57343mov %o4, %l5
57344mov %l4, %o0
57345cas [%i1], %l7, %o0
57346! move %o0(lower) -> %o0(upper)
57347sllx %o0, 32, %o0
57348add %l4, 1, %l4
57349
57350P5371: !_MEMBAR (FP)
57351
57352P5372: !_BSTC [1] (maybe <- 0x4200006b) (FP)
57353wr %g0, 0xe0, %asi
57354! preparing store val #0, next val will be in f32
57355fmovs %f16, %f20
57356fadds %f16, %f17, %f16
57357! preparing store val #1, next val will be in f33
57358fmovs %f16, %f21
57359fadds %f16, %f17, %f16
57360! preparing store val #2, next val will be in f35
57361fmovd %f20, %f32
57362fmovs %f16, %f21
57363fadds %f16, %f17, %f16
57364fmovd %f20, %f34
57365membar #Sync
57366stda %f32, [%i0 + 0 ] %asi
57367
57368P5373: !_MEMBAR (FP)
57369membar #StoreLoad
57370
57371P5374: !_PREFETCH [2] (Int)
57372prefetch [%i0 + 12], 1
57373
57374P5375: !_ST_BINIT [22] (maybe <- 0x2800092) (Int)
57375wr %g0, 0xe2, %asi
57376sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
57377add %i0, %i3, %i3
57378stwa %l4, [%i3 + 4] %asi
57379add %l4, 1, %l4
57380
57381P5376: !_MEMBAR (Int)
57382membar #StoreLoad
57383
57384P5377: !_BLD [15] (FP)
57385wr %g0, 0xf0, %asi
57386sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
57387sub %i0, %i2, %i2
57388ldda [%i2 + 0] %asi, %f32
57389membar #Sync
57390! 3 addresses covered
57391fmovd %f32, %f18
57392fmovs %f18, %f7
57393fmovs %f19, %f8
57394fmovd %f34, %f18
57395fmovs %f19, %f9
57396
57397P5378: !_MEMBAR (FP)
57398
57399P5379: !_BLD [4] (FP)
57400wr %g0, 0xf0, %asi
57401ldda [%i1 + 0] %asi, %f32
57402membar #Sync
57403! 3 addresses covered
57404fmovd %f32, %f10
57405fmovd %f34, %f18
57406fmovs %f19, %f12
57407
57408P5380: !_MEMBAR (FP)
57409
57410P5381: !_LD [15] (Int)
57411lduw [%i2 + 0], %l6
57412! move %l6(lower) -> %o0(lower)
57413or %l6, %o0, %o0
57414
57415P5382: !_DWLD [13] (FP)
57416sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
57417sub %i0, %i3, %i3
57418ldd [%i3 + 0], %f18
57419! 2 addresses covered
57420fmovs %f18, %f13
57421fmovs %f19, %f14
57422
57423P5383: !_CAS [4] (maybe <- 0x2800093) (Int) (LE)
57424! Change single-word-level endianess (big endian <-> little endian)
57425sethi %hi(0xff00ff00), %o5
57426or %o5, %lo(0xff00ff00), %o5
57427and %l4, %o5, %l7
57428srl %l7, 8, %l7
57429sll %l4, 8, %l3
57430and %l3, %o5, %l3
57431or %l3, %l7, %l3
57432srl %l3, 16, %l7
57433sll %l3, 16, %l3
57434srl %l3, 0, %l3
57435or %l3, %l7, %l3
57436wr %g0, 0x88, %asi
57437add %i1, 4, %o5
57438lduwa [%o5] %asi, %o1
57439mov %o1, %l7
57440! move %l7(lower) -> %o1(upper)
57441sllx %l7, 32, %o1
57442mov %l3, %l6
57443casa [%o5] %asi, %l7, %l6
57444! move %l6(lower) -> %o1(lower)
57445srl %l6, 0, %l7
57446or %l7, %o1, %o1
57447add %l4, 1, %l4
57448
57449P5384: !_MEMBAR (FP)
57450membar #StoreLoad
57451
57452P5385: !_BLD [20] (FP)
57453wr %g0, 0xf0, %asi
57454sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
57455sub %i0, %i2, %i2
57456ldda [%i2 + 0] %asi, %f32
57457membar #Sync
57458! 3 addresses covered
57459fmovd %f32, %f18
57460fmovs %f18, %f15
57461!---- flushing fp results buffer to %f30 ----
57462fmovd %f0, %f30
57463fmovd %f2, %f30
57464fmovd %f4, %f30
57465fmovd %f6, %f30
57466fmovd %f8, %f30
57467fmovd %f10, %f30
57468fmovd %f12, %f30
57469fmovd %f14, %f30
57470!--
57471fmovs %f19, %f0
57472fmovd %f34, %f18
57473fmovs %f19, %f1
57474
57475P5386: !_MEMBAR (FP)
57476
57477P5387: !_ST_BINIT [19] (maybe <- 0x2800094) (Int)
57478wr %g0, 0xe2, %asi
57479stwa %l4, [%i2 + 4] %asi
57480add %l4, 1, %l4
57481
57482P5388: !_MEMBAR (Int)
57483
57484P5389: !_BSTC [2] (maybe <- 0x4200006e) (FP)
57485wr %g0, 0xe0, %asi
57486! preparing store val #0, next val will be in f32
57487fmovs %f16, %f20
57488fadds %f16, %f17, %f16
57489! preparing store val #1, next val will be in f33
57490fmovs %f16, %f21
57491fadds %f16, %f17, %f16
57492! preparing store val #2, next val will be in f35
57493fmovd %f20, %f32
57494fmovs %f16, %f21
57495fadds %f16, %f17, %f16
57496fmovd %f20, %f34
57497membar #Sync
57498stda %f32, [%i0 + 0 ] %asi
57499
57500P5390: !_MEMBAR (FP)
57501membar #StoreLoad
57502
57503P5391: !_ST_BINIT [14] (maybe <- 0x2800095) (Int)
57504wr %g0, 0xe2, %asi
57505stwa %l4, [%i3 + 12] %asi
57506add %l4, 1, %l4
57507
57508P5392: !_MEMBAR (Int)
57509membar #StoreLoad
57510
57511P5393: !_SWAP [4] (maybe <- 0x2800096) (Int)
57512mov %l4, %o2
57513swap [%i1 + 4], %o2
57514! move %o2(lower) -> %o2(upper)
57515sllx %o2, 32, %o2
57516add %l4, 1, %l4
57517
57518P5394: !_CASX [6] (maybe <- 0x2800097) (Int)
57519sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
57520sub %i0, %i3, %i3
57521ldx [%i3], %l6
57522! move %l6(upper) -> %o2(lower)
57523srlx %l6, 32, %l7
57524or %l7, %o2, %o2
57525! move %l6(lower) -> %o3(upper)
57526sllx %l6, 32, %o3
57527mov %l6, %l7
57528sllx %l4, 32, %l6
57529add %l4, 1, %l4
57530or %l4, %l6, %l6
57531casx [%i3], %l7, %l6
57532! move %l6(upper) -> %o3(lower)
57533srlx %l6, 32, %l7
57534or %l7, %o3, %o3
57535! move %l6(lower) -> %o4(upper)
57536sllx %l6, 32, %o4
57537add %l4, 1, %l4
57538
57539P5395: !_DWST [3] (maybe <- 0x42000071) (FP)
57540! preparing store val #0, next val will be in f20
57541fmovs %f16, %f20
57542fadds %f16, %f17, %f16
57543! preparing store val #1, next val will be in f21
57544fmovs %f16, %f21
57545fadds %f16, %f17, %f16
57546std %f20, [%i1 + 0]
57547
57548P5396: !_PREFETCH [16] (Int)
57549sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
57550sub %i0, %i2, %i2
57551prefetch [%i2 + 4], 23
57552
57553P5397: !_LDD [3] (Int)
57554!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
57555!Logical addr: 3
57556
57557sethi %hi(0x200000), %l6
57558sub %i1, %l6, %i1
57559ldd [%i1 + 0], %l6
57560! move %l6(lower) -> %o4(lower)
57561or %l6, %o4, %o4
57562!---- flushing int results buffer----
57563mov %o0, %l5
57564mov %o1, %l5
57565mov %o2, %l5
57566mov %o3, %l5
57567mov %o4, %l5
57568! move %l7(lower) -> %o0(upper)
57569sllx %l7, 32, %o0
57570
57571P5398: !_CASX [13] (maybe <- 0x2800099) (Int)
57572sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
57573sub %i0, %i3, %i3
57574ldx [%i3], %o5
57575! move %o5(upper) -> %o0(lower)
57576srlx %o5, 32, %l3
57577or %l3, %o0, %o0
57578! move %o5(lower) -> %o1(upper)
57579sllx %o5, 32, %o1
57580mov %o5, %l3
57581sllx %l4, 32, %o5
57582add %l4, 1, %l4
57583or %l4, %o5, %o5
57584casx [%i3], %l3, %o5
57585! move %o5(upper) -> %o1(lower)
57586srlx %o5, 32, %l3
57587or %l3, %o1, %o1
57588! move %o5(lower) -> %o2(upper)
57589sllx %o5, 32, %o2
57590add %l4, 1, %l4
57591
57592P5399: !_LD [12] (Int)
57593lduw [%i3 + 0], %l6
57594! move %l6(lower) -> %o2(lower)
57595or %l6, %o2, %o2
57596
57597P5400: !_ST [21] (maybe <- 0x280009b) (Int)
57598sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
57599add %i0, %i2, %i2
57600stw %l4, [%i2 + 0 ]
57601add %l4, 1, %l4
57602
57603P5401: !_SWAP [1] (maybe <- 0x280009c) (Int)
57604mov %l4, %o3
57605swap [%i0 + 4], %o3
57606! move %o3(lower) -> %o3(upper)
57607sllx %o3, 32, %o3
57608add %l4, 1, %l4
57609
57610P5402: !_SWAP [19] (maybe <- 0x280009d) (Int)
57611sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
57612sub %i0, %i3, %i3
57613mov %l4, %l7
57614swap [%i3 + 4], %l7
57615! move %l7(lower) -> %o3(lower)
57616srl %l7, 0, %l3
57617or %l3, %o3, %o3
57618add %l4, 1, %l4
57619
57620P5403: !_ST_BINIT [2] (maybe <- 0x280009e) (Int)
57621wr %g0, 0xe2, %asi
57622stwa %l4, [%i0 + 12] %asi
57623add %l4, 1, %l4
57624
57625P5404: !_MEMBAR (Int) (CBR)
57626membar #StoreLoad
57627
57628! cbranch
57629andcc %l0, 1, %g0
57630be,pt %xcc, TARGET5404
57631nop
57632RET5404:
57633
57634! lfsr step begin
57635srlx %l0, 1, %l7
57636xnor %l7, %l0, %l7
57637sllx %l7, 63, %l7
57638or %l7, %l0, %l0
57639srlx %l0, 1, %l0
57640
57641
57642P5405: !_CASX [8] (maybe <- 0x280009f) (Int)
57643sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
57644sub %i0, %i2, %i2
57645add %i2, 8, %l3
57646ldx [%l3], %o4
57647! move %o4(upper) -> %o4(upper)
57648! move %o4(lower) -> %o4(lower)
57649!---- flushing int results buffer----
57650mov %o0, %l5
57651mov %o1, %l5
57652mov %o2, %l5
57653mov %o3, %l5
57654mov %o4, %l5
57655mov %o4, %o5
57656mov %l4, %o0
57657casx [%l3], %o5, %o0
57658! move %o0(upper) -> %o0(upper)
57659! move %o0(lower) -> %o0(lower)
57660add %l4, 1, %l4
57661
57662P5406: !_ST [8] (maybe <- 0x28000a0) (Int)
57663stw %l4, [%i2 + 12 ]
57664add %l4, 1, %l4
57665
57666P5407: !_SWAP [17] (maybe <- 0x28000a1) (Int)
57667sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
57668sub %i0, %i3, %i3
57669mov %l4, %o1
57670swap [%i3 + 12], %o1
57671! move %o1(lower) -> %o1(upper)
57672sllx %o1, 32, %o1
57673add %l4, 1, %l4
57674
57675P5408: !_ST_BINIT [5] (maybe <- 0x28000a2) (Int)
57676wr %g0, 0xe2, %asi
57677stwa %l4, [%i1 + 12] %asi
57678add %l4, 1, %l4
57679
57680P5409: !_MEMBAR (Int)
57681membar #StoreLoad
57682
57683P5410: !_DWLD [4] (Int)
57684ldx [%i1 + 0], %l6
57685! move %l6(upper) -> %o1(lower)
57686srlx %l6, 32, %l3
57687or %l3, %o1, %o1
57688! move %l6(lower) -> %o2(upper)
57689sllx %l6, 32, %o2
57690
57691P5411: !_LD [6] (Int) (LE)
57692wr %g0, 0x88, %asi
57693lduwa [%i2 + 0] %asi, %o5
57694! move %o5(lower) -> %o2(lower)
57695or %o5, %o2, %o2
57696
57697P5412: !_ST_BINIT [1] (maybe <- 0x28000a3) (Int)
57698wr %g0, 0xe2, %asi
57699stwa %l4, [%i0 + 4] %asi
57700add %l4, 1, %l4
57701
57702P5413: !_MEMBAR (Int)
57703membar #StoreLoad
57704
57705P5414: !_DWLD [14] (FP)
57706sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
57707sub %i0, %i2, %i2
57708ldd [%i2 + 8], %f2
57709! 1 addresses covered
57710fmovs %f3, %f2
57711
57712P5415: !_LDD [20] (Int) (Branch target of P5655)
57713sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
57714sub %i0, %i3, %i3
57715ldd [%i3 + 8], %l6
57716! move %l7(lower) -> %o3(upper)
57717sllx %l7, 32, %o3
57718ba P5416
57719nop
57720
57721TARGET5655:
57722ba RET5655
57723nop
57724
57725
57726P5416: !_PREFETCH [10] (Int)
57727sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
57728add %i0, %i2, %i2
57729prefetch [%i2 + 4], 0
57730
57731P5417: !_LDD [8] (Int)
57732sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
57733sub %i0, %i3, %i3
57734ldd [%i3 + 8], %l6
57735! move %l7(lower) -> %o3(lower)
57736or %l7, %o3, %o3
57737
57738P5418: !_MEMBAR (FP) (Branch target of P5348)
57739membar #StoreLoad
57740ba P5419
57741nop
57742
57743TARGET5348:
57744ba RET5348
57745nop
57746
57747
57748P5419: !_BLD [23] (FP)
57749wr %g0, 0xf0, %asi
57750sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
57751add %i0, %i2, %i2
57752ldda [%i2 + 0] %asi, %f32
57753membar #Sync
57754! 3 addresses covered
57755fmovd %f32, %f18
57756fmovs %f18, %f3
57757fmovs %f19, %f4
57758fmovd %f34, %f18
57759fmovs %f19, %f5
57760
57761P5420: !_MEMBAR (FP)
57762
57763P5421: !_DWLD [15] (Int)
57764sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
57765sub %i0, %i3, %i3
57766ldx [%i3 + 0], %o4
57767! move %o4(upper) -> %o4(upper)
57768! move %o4(lower) -> %o4(lower)
57769!---- flushing int results buffer----
57770mov %o0, %l5
57771mov %o1, %l5
57772mov %o2, %l5
57773mov %o3, %l5
57774mov %o4, %l5
57775
57776P5422: !_SWAP [9] (maybe <- 0x28000a4) (Int)
57777sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
57778add %i0, %i2, %i2
57779mov %l4, %o0
57780swap [%i2 + 0], %o0
57781! move %o0(lower) -> %o0(upper)
57782sllx %o0, 32, %o0
57783add %l4, 1, %l4
57784
57785P5423: !_LDD [2] (Int)
57786ldd [%i0 + 8], %l6
57787! move %l7(lower) -> %o0(lower)
57788or %l7, %o0, %o0
57789
57790P5424: !_PREFETCH [8] (Int)
57791sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
57792sub %i0, %i3, %i3
57793prefetch [%i3 + 12], 20
57794
57795P5425: !_DWST_BINIT [5] (maybe <- 0x28000a5) (Int)
57796wr %g0, 0xe2, %asi
57797mov %l4, %l3
57798stxa %l3, [%i1 + 8] %asi
57799add %l4, 1, %l4
57800
57801P5426: !_MEMBAR (Int)
57802membar #StoreLoad
57803
57804P5427: !_DWST [5] (maybe <- 0x28000a6) (Int)
57805mov %l4, %o5
57806stx %o5, [%i1 + 8]
57807add %l4, 1, %l4
57808
57809P5428: !_CASX [20] (maybe <- 0x28000a7) (Int)
57810sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
57811sub %i0, %i2, %i2
57812add %i2, 8, %o5
57813ldx [%o5], %o1
57814! move %o1(upper) -> %o1(upper)
57815! move %o1(lower) -> %o1(lower)
57816mov %o1, %l7
57817mov %l4, %o2
57818casx [%o5], %l7, %o2
57819! move %o2(upper) -> %o2(upper)
57820! move %o2(lower) -> %o2(lower)
57821add %l4, 1, %l4
57822
57823P5429: !_MEMBAR (FP)
57824
57825P5430: !_BSTC [2] (maybe <- 0x42000073) (FP)
57826wr %g0, 0xe0, %asi
57827! preparing store val #0, next val will be in f32
57828fmovs %f16, %f20
57829fadds %f16, %f17, %f16
57830! preparing store val #1, next val will be in f33
57831fmovs %f16, %f21
57832fadds %f16, %f17, %f16
57833! preparing store val #2, next val will be in f35
57834fmovd %f20, %f32
57835fmovs %f16, %f21
57836fadds %f16, %f17, %f16
57837fmovd %f20, %f34
57838membar #Sync
57839stda %f32, [%i0 + 0 ] %asi
57840
57841P5431: !_MEMBAR (FP)
57842membar #StoreLoad
57843
57844P5432: !_DWST_BINIT [11] (maybe <- 0x28000a8) (Int)
57845wr %g0, 0xe2, %asi
57846sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
57847add %i0, %i3, %i3
57848mov %l4, %l6
57849stxa %l6, [%i3 + 8] %asi
57850add %l4, 1, %l4
57851
57852P5433: !_MEMBAR (Int)
57853membar #StoreLoad
57854
57855P5434: !_LD [14] (Int)
57856sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
57857sub %i0, %i2, %i2
57858lduw [%i2 + 12], %o3
57859! move %o3(lower) -> %o3(upper)
57860sllx %o3, 32, %o3
57861
57862P5435: !_ST_BINIT [3] (maybe <- 0x28000a9) (Int)
57863wr %g0, 0xe2, %asi
57864stwa %l4, [%i1 + 0] %asi
57865add %l4, 1, %l4
57866
57867P5436: !_MEMBAR (Int) (CBR)
57868membar #StoreLoad
57869
57870! cbranch
57871andcc %l0, 1, %g0
57872be,pt %xcc, TARGET5436
57873nop
57874RET5436:
57875
57876! lfsr step begin
57877srlx %l0, 1, %l6
57878xnor %l6, %l0, %l6
57879sllx %l6, 63, %l6
57880or %l6, %l0, %l0
57881srlx %l0, 1, %l0
57882
57883
57884P5437: !_DWST [7] (maybe <- 0x28000aa) (Int)
57885sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
57886sub %i0, %i3, %i3
57887sllx %l4, 32, %l7
57888add %l4, 1, %l4
57889or %l7, %l4, %l7
57890stx %l7, [%i3 + 0]
57891add %l4, 1, %l4
57892
57893P5438: !_LDD [7] (Int) (LE)
57894wr %g0, 0x88, %asi
57895ldda [%i3 + 0] %asi, %l6
57896! move %l6(lower) -> %o3(lower)
57897or %l6, %o3, %o3
57898! move %l7(lower) -> %o4(upper)
57899sllx %l7, 32, %o4
57900
57901P5439: !_DWLD [16] (Int)
57902sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
57903sub %i0, %i2, %i2
57904ldx [%i2 + 0], %l6
57905! move %l6(upper) -> %o4(lower)
57906srlx %l6, 32, %l3
57907or %l3, %o4, %o4
57908!---- flushing int results buffer----
57909mov %o0, %l5
57910mov %o1, %l5
57911mov %o2, %l5
57912mov %o3, %l5
57913mov %o4, %l5
57914! move %l6(lower) -> %o0(upper)
57915sllx %l6, 32, %o0
57916
57917P5440: !_LDD [6] (Int) (CBR)
57918ldd [%i3 + 0], %l6
57919! move %l6(lower) -> %o0(lower)
57920or %l6, %o0, %o0
57921! move %l7(lower) -> %o1(upper)
57922sllx %l7, 32, %o1
57923
57924! cbranch
57925andcc %l0, 1, %g0
57926be,pt %xcc, TARGET5440
57927nop
57928RET5440:
57929
57930! lfsr step begin
57931srlx %l0, 1, %l3
57932xnor %l3, %l0, %l3
57933sllx %l3, 63, %l3
57934or %l3, %l0, %l0
57935srlx %l0, 1, %l0
57936
57937
57938P5441: !_CAS [23] (maybe <- 0x28000ac) (Int)
57939sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
57940add %i0, %i3, %i3
57941add %i3, 12, %l7
57942lduw [%l7], %l3
57943mov %l3, %l6
57944! move %l6(lower) -> %o1(lower)
57945or %l6, %o1, %o1
57946mov %l4, %o2
57947cas [%l7], %l6, %o2
57948! move %o2(lower) -> %o2(upper)
57949sllx %o2, 32, %o2
57950add %l4, 1, %l4
57951
57952P5442: !_ST_BINIT [2] (maybe <- 0x28000ad) (Int) (Branch target of P5106)
57953wr %g0, 0xe2, %asi
57954stwa %l4, [%i0 + 12] %asi
57955add %l4, 1, %l4
57956ba P5443
57957nop
57958
57959TARGET5106:
57960ba RET5106
57961nop
57962
57963
57964P5443: !_MEMBAR (Int)
57965membar #StoreLoad
57966
57967P5444: !_ST [8] (maybe <- 0x28000ae) (Int)
57968sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
57969sub %i0, %i2, %i2
57970stw %l4, [%i2 + 12 ]
57971add %l4, 1, %l4
57972
57973P5445: !_DWST [22] (maybe <- 0x42000076) (FP) (CBR)
57974! preparing store val #0, next val will be in f20
57975fmovs %f16, %f20
57976fadds %f16, %f17, %f16
57977! preparing store val #1, next val will be in f21
57978fmovs %f16, %f21
57979fadds %f16, %f17, %f16
57980std %f20, [%i3 + 0]
57981
57982! cbranch
57983andcc %l0, 1, %g0
57984be,pn %xcc, TARGET5445
57985nop
57986RET5445:
57987
57988! lfsr step begin
57989srlx %l0, 1, %l7
57990xnor %l7, %l0, %l7
57991sllx %l7, 63, %l7
57992or %l7, %l0, %l0
57993srlx %l0, 1, %l0
57994
57995
57996P5446: !_PREFETCH [15] (Int)
57997sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
57998sub %i0, %i3, %i3
57999prefetch [%i3 + 0], 31
58000
58001P5447: !_MEMBAR (FP)
58002
58003P5448: !_BST [12] (maybe <- 0x42000078) (FP)
58004wr %g0, 0xf0, %asi
58005sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
58006sub %i0, %i2, %i2
58007! preparing store val #0, next val will be in f32
58008fmovs %f16, %f20
58009fadds %f16, %f17, %f16
58010! preparing store val #1, next val will be in f33
58011fmovs %f16, %f21
58012fadds %f16, %f17, %f16
58013! preparing store val #2, next val will be in f35
58014fmovd %f20, %f32
58015fmovs %f16, %f21
58016fadds %f16, %f17, %f16
58017fmovd %f20, %f34
58018membar #Sync
58019stda %f32, [%i2 + 0 ] %asi
58020
58021P5449: !_MEMBAR (FP)
58022membar #StoreLoad
58023
58024P5450: !_DWLD [7] (Int)
58025sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
58026sub %i0, %i3, %i3
58027ldx [%i3 + 0], %o5
58028! move %o5(upper) -> %o2(lower)
58029srlx %o5, 32, %l7
58030or %l7, %o2, %o2
58031! move %o5(lower) -> %o3(upper)
58032sllx %o5, 32, %o3
58033
58034P5451: !_ST_BINIT [21] (maybe <- 0x28000af) (Int) (LE)
58035wr %g0, 0xea, %asi
58036sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
58037add %i0, %i2, %i2
58038! Change single-word-level endianess (big endian <-> little endian)
58039sethi %hi(0xff00ff00), %l6
58040or %l6, %lo(0xff00ff00), %l6
58041and %l4, %l6, %l7
58042srl %l7, 8, %l7
58043sll %l4, 8, %l3
58044and %l3, %l6, %l3
58045or %l3, %l7, %l3
58046srl %l3, 16, %l7
58047sll %l3, 16, %l3
58048srl %l3, 0, %l3
58049or %l3, %l7, %l3
58050stwa %l3, [%i2 + 0] %asi
58051add %l4, 1, %l4
58052
58053P5452: !_MEMBAR (Int) (LE)
58054membar #StoreLoad
58055
58056P5453: !_LDD [12] (Int)
58057sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
58058sub %i0, %i3, %i3
58059ldd [%i3 + 0], %l6
58060! move %l6(lower) -> %o3(lower)
58061or %l6, %o3, %o3
58062! move %l7(lower) -> %o4(upper)
58063sllx %l7, 32, %o4
58064
58065P5454: !_PREFETCH [19] (Int)
58066sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
58067sub %i0, %i2, %i2
58068prefetch [%i2 + 4], 26
58069
58070P5455: !_DWLD [13] (FP)
58071ldd [%i3 + 0], %f6
58072! 2 addresses covered
58073
58074P5456: !_PREFETCH [14] (Int)
58075prefetch [%i3 + 12], 30
58076
58077P5457: !_LDD [20] (Int)
58078ldd [%i2 + 8], %l6
58079! move %l7(lower) -> %o4(lower)
58080or %l7, %o4, %o4
58081!---- flushing int results buffer----
58082mov %o0, %l5
58083mov %o1, %l5
58084mov %o2, %l5
58085mov %o3, %l5
58086mov %o4, %l5
58087
58088P5458: !_CAS [19] (maybe <- 0x28000b0) (Int)
58089add %i2, 4, %l6
58090lduw [%l6], %o0
58091mov %o0, %l3
58092! move %l3(lower) -> %o0(upper)
58093sllx %l3, 32, %o0
58094mov %l4, %o5
58095cas [%l6], %l3, %o5
58096! move %o5(lower) -> %o0(lower)
58097srl %o5, 0, %l3
58098or %l3, %o0, %o0
58099add %l4, 1, %l4
58100
58101P5459: !_DWST [14] (maybe <- 0x28000b1) (Int)
58102mov %l4, %l3
58103stx %l3, [%i3 + 8]
58104add %l4, 1, %l4
58105
58106P5460: !_CAS [14] (maybe <- 0x28000b2) (Int)
58107add %i3, 12, %l3
58108lduw [%l3], %o1
58109mov %o1, %o5
58110! move %o5(lower) -> %o1(upper)
58111sllx %o5, 32, %o1
58112mov %l4, %l7
58113cas [%l3], %o5, %l7
58114! move %l7(lower) -> %o1(lower)
58115srl %l7, 0, %o5
58116or %o5, %o1, %o1
58117add %l4, 1, %l4
58118
58119P5461: !_DWST_BINIT [7] (maybe <- 0x28000b3) (Int) (LE)
58120wr %g0, 0xea, %asi
58121sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
58122sub %i0, %i3, %i3
58123sllx %l4, 32, %l3
58124add %l4, 1, %l4
58125or %l3, %l4, %l6
58126! Change double-word-level endianess (big endian <-> little endian)
58127sethi %hi(0xff00ff00), %l7
58128or %l7, %lo(0xff00ff00), %l7
58129sllx %l7, 32, %l3
58130or %l7, %l3, %l7
58131and %l6, %l7, %l3
58132srlx %l3, 8, %l3
58133sllx %l6, 8, %l6
58134and %l6, %l7, %l6
58135or %l6, %l3, %l6
58136sethi %hi(0xffff0000), %l7
58137srlx %l6, 16, %l3
58138andn %l3, %l7, %l3
58139andn %l6, %l7, %l6
58140sllx %l6, 16, %l6
58141or %l6, %l3, %l6
58142srlx %l6, 32, %l3
58143sllx %l6, 32, %l6
58144or %l6, %l3, %l3
58145stxa %l3, [%i3 + 0 ] %asi
58146add %l4, 1, %l4
58147
58148P5462: !_MEMBAR (Int) (LE)
58149membar #StoreLoad
58150
58151P5463: !_ST_BINIT [5] (maybe <- 0x28000b5) (Int)
58152wr %g0, 0xe2, %asi
58153stwa %l4, [%i1 + 12] %asi
58154add %l4, 1, %l4
58155
58156P5464: !_MEMBAR (Int)
58157membar #StoreLoad
58158
58159P5465: !_LDD [21] (Int)
58160sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
58161add %i0, %i2, %i2
58162ldd [%i2 + 0], %l6
58163! move %l6(lower) -> %o2(upper)
58164sllx %l6, 32, %o2
58165! move %l7(lower) -> %o2(lower)
58166or %l7, %o2, %o2
58167
58168P5466: !_CAS [19] (maybe <- 0x28000b6) (Int)
58169sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
58170sub %i0, %i3, %i3
58171add %i3, 4, %l6
58172lduw [%l6], %o3
58173mov %o3, %l3
58174! move %l3(lower) -> %o3(upper)
58175sllx %l3, 32, %o3
58176mov %l4, %o5
58177cas [%l6], %l3, %o5
58178! move %o5(lower) -> %o3(lower)
58179srl %o5, 0, %l3
58180or %l3, %o3, %o3
58181add %l4, 1, %l4
58182
58183P5467: !_CAS [13] (maybe <- 0x28000b7) (Int)
58184sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
58185sub %i0, %i2, %i2
58186add %i2, 4, %l6
58187lduw [%l6], %o4
58188mov %o4, %l3
58189! move %l3(lower) -> %o4(upper)
58190sllx %l3, 32, %o4
58191mov %l4, %o5
58192cas [%l6], %l3, %o5
58193! move %o5(lower) -> %o4(lower)
58194srl %o5, 0, %l3
58195or %l3, %o4, %o4
58196!---- flushing int results buffer----
58197mov %o0, %l5
58198mov %o1, %l5
58199mov %o2, %l5
58200mov %o3, %l5
58201mov %o4, %l5
58202add %l4, 1, %l4
58203
58204P5468: !_DWST [12] (maybe <- 0x28000b8) (Int)
58205sllx %l4, 32, %l3
58206add %l4, 1, %l4
58207or %l3, %l4, %l3
58208stx %l3, [%i2 + 0]
58209add %l4, 1, %l4
58210
58211P5469: !_LD [12] (Int)
58212lduw [%i2 + 0], %o0
58213! move %o0(lower) -> %o0(upper)
58214sllx %o0, 32, %o0
58215
58216P5470: !_PREFETCH [3] (Int)
58217prefetch [%i1 + 0], 30
58218
58219P5471: !_CASX [17] (maybe <- 0x28000ba) (Int)
58220sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
58221sub %i0, %i3, %i3
58222add %i3, 8, %l7
58223ldx [%l7], %l3
58224! move %l3(upper) -> %o0(lower)
58225srlx %l3, 32, %l6
58226or %l6, %o0, %o0
58227! move %l3(lower) -> %o1(upper)
58228sllx %l3, 32, %o1
58229mov %l3, %l6
58230mov %l4, %l3
58231casx [%l7], %l6, %l3
58232! move %l3(upper) -> %o1(lower)
58233srlx %l3, 32, %l6
58234or %l6, %o1, %o1
58235! move %l3(lower) -> %o2(upper)
58236sllx %l3, 32, %o2
58237add %l4, 1, %l4
58238
58239P5472: !_SWAP [3] (maybe <- 0x28000bb) (Int)
58240mov %l4, %o5
58241swap [%i1 + 0], %o5
58242! move %o5(lower) -> %o2(lower)
58243srl %o5, 0, %l6
58244or %l6, %o2, %o2
58245add %l4, 1, %l4
58246
58247P5473: !_LDD [11] (Int)
58248sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
58249add %i0, %i2, %i2
58250ldd [%i2 + 8], %l6
58251! move %l7(lower) -> %o3(upper)
58252sllx %l7, 32, %o3
58253
58254P5474: !_SWAP [12] (maybe <- 0x28000bc) (Int)
58255sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
58256sub %i0, %i3, %i3
58257mov %l4, %l7
58258swap [%i3 + 0], %l7
58259! move %l7(lower) -> %o3(lower)
58260srl %l7, 0, %l3
58261or %l3, %o3, %o3
58262add %l4, 1, %l4
58263
58264P5475: !_DWST_BINIT [19] (maybe <- 0x28000bd) (Int)
58265wr %g0, 0xe2, %asi
58266sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
58267sub %i0, %i2, %i2
58268sllx %l4, 32, %o5
58269add %l4, 1, %l4
58270or %o5, %l4, %o5
58271stxa %o5, [%i2 + 0] %asi
58272add %l4, 1, %l4
58273
58274P5476: !_MEMBAR (Int)
58275membar #StoreLoad
58276
58277P5477: !_CAS [3] (maybe <- 0x28000bf) (Int)
58278lduw [%i1], %o4
58279mov %o4, %l7
58280! move %l7(lower) -> %o4(upper)
58281sllx %l7, 32, %o4
58282mov %l4, %l6
58283cas [%i1], %l7, %l6
58284! move %l6(lower) -> %o4(lower)
58285srl %l6, 0, %l7
58286or %l7, %o4, %o4
58287!---- flushing int results buffer----
58288mov %o0, %l5
58289mov %o1, %l5
58290mov %o2, %l5
58291mov %o3, %l5
58292mov %o4, %l5
58293add %l4, 1, %l4
58294
58295P5478: !_ST [20] (maybe <- 0x28000c0) (Int)
58296stw %l4, [%i2 + 12 ]
58297add %l4, 1, %l4
58298
58299P5479: !_DWST_BINIT [20] (maybe <- 0x28000c1) (Int)
58300wr %g0, 0xe2, %asi
58301mov %l4, %l6
58302stxa %l6, [%i2 + 8] %asi
58303add %l4, 1, %l4
58304
58305P5480: !_MEMBAR (Int) (CBR)
58306membar #StoreLoad
58307
58308! cbranch
58309andcc %l0, 1, %g0
58310be,pn %xcc, TARGET5480
58311nop
58312RET5480:
58313
58314! lfsr step begin
58315srlx %l0, 1, %l3
58316xnor %l3, %l0, %l3
58317sllx %l3, 63, %l3
58318or %l3, %l0, %l0
58319srlx %l0, 1, %l0
58320
58321
58322P5481: !_ST_BINIT [22] (maybe <- 0x28000c2) (Int)
58323wr %g0, 0xe2, %asi
58324sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
58325add %i0, %i3, %i3
58326stwa %l4, [%i3 + 4] %asi
58327add %l4, 1, %l4
58328
58329P5482: !_MEMBAR (Int) (Branch target of P5440)
58330membar #StoreLoad
58331ba P5483
58332nop
58333
58334TARGET5440:
58335ba RET5440
58336nop
58337
58338
58339P5483: !_BLD [6] (FP)
58340wr %g0, 0xf0, %asi
58341sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
58342sub %i0, %i2, %i2
58343ldda [%i2 + 0] %asi, %f32
58344membar #Sync
58345! 3 addresses covered
58346fmovd %f32, %f8
58347fmovd %f34, %f18
58348fmovs %f19, %f10
58349
58350P5484: !_MEMBAR (FP)
58351
58352P5485: !_CAS [14] (maybe <- 0x28000c3) (Int)
58353sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
58354sub %i0, %i3, %i3
58355add %i3, 12, %l6
58356lduw [%l6], %o0
58357mov %o0, %l3
58358! move %l3(lower) -> %o0(upper)
58359sllx %l3, 32, %o0
58360mov %l4, %o5
58361cas [%l6], %l3, %o5
58362! move %o5(lower) -> %o0(lower)
58363srl %o5, 0, %l3
58364or %l3, %o0, %o0
58365add %l4, 1, %l4
58366
58367P5486: !_ST_BINIT [2] (maybe <- 0x28000c4) (Int)
58368wr %g0, 0xe2, %asi
58369stwa %l4, [%i0 + 12] %asi
58370add %l4, 1, %l4
58371
58372P5487: !_MEMBAR (Int)
58373membar #StoreLoad
58374
58375P5488: !_LDD [12] (Int) (CBR)
58376ldd [%i3 + 0], %l6
58377! move %l6(lower) -> %o1(upper)
58378sllx %l6, 32, %o1
58379! move %l7(lower) -> %o1(lower)
58380or %l7, %o1, %o1
58381
58382! cbranch
58383andcc %l0, 1, %g0
58384be,pt %xcc, TARGET5488
58385nop
58386RET5488:
58387
58388! lfsr step begin
58389srlx %l0, 1, %l3
58390xnor %l3, %l0, %l3
58391sllx %l3, 63, %l3
58392or %l3, %l0, %l0
58393srlx %l0, 1, %l0
58394
58395
58396P5489: !_REPLACEMENT [20] (Int)
58397sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
58398add %i0, %i2, %i2
58399sethi %hi(0x20000), %l6
58400ld [%i2+12], %o5
58401st %o5, [%i2+12]
58402add %i2, %l6, %l7
58403ld [%l7+12], %o5
58404st %o5, [%l7+12]
58405add %l7, %l6, %l7
58406ld [%l7+12], %o5
58407st %o5, [%l7+12]
58408add %l7, %l6, %l7
58409ld [%l7+12], %o5
58410st %o5, [%l7+12]
58411add %l7, %l6, %l7
58412ld [%l7+12], %o5
58413st %o5, [%l7+12]
58414add %l7, %l6, %l7
58415ld [%l7+12], %o5
58416st %o5, [%l7+12]
58417add %l7, %l6, %l7
58418ld [%l7+12], %o5
58419st %o5, [%l7+12]
58420add %l7, %l6, %l7
58421ld [%l7+12], %o5
58422st %o5, [%l7+12]
58423
58424P5490: !_ST [3] (maybe <- 0x28000c5) (Int)
58425stw %l4, [%i1 + 0 ]
58426add %l4, 1, %l4
58427
58428P5491: !_DWST [2] (maybe <- 0x28000c6) (Int)
58429mov %l4, %o5
58430stx %o5, [%i0 + 8]
58431add %l4, 1, %l4
58432
58433P5492: !_MEMBAR (FP)
58434membar #StoreLoad
58435
58436P5493: !_BLD [6] (FP)
58437wr %g0, 0xf0, %asi
58438sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
58439sub %i0, %i3, %i3
58440ldda [%i3 + 0] %asi, %f32
58441membar #Sync
58442! 3 addresses covered
58443fmovd %f32, %f18
58444fmovs %f18, %f11
58445fmovs %f19, %f12
58446fmovd %f34, %f18
58447fmovs %f19, %f13
58448
58449P5494: !_MEMBAR (FP)
58450
58451P5495: !_SWAP [3] (maybe <- 0x28000c7) (Int)
58452mov %l4, %o2
58453swap [%i1 + 0], %o2
58454! move %o2(lower) -> %o2(upper)
58455sllx %o2, 32, %o2
58456add %l4, 1, %l4
58457
58458P5496: !_CASX [5] (maybe <- 0x28000c8) (Int)
58459add %i1, 8, %l7
58460ldx [%l7], %l3
58461! move %l3(upper) -> %o2(lower)
58462srlx %l3, 32, %l6
58463or %l6, %o2, %o2
58464! move %l3(lower) -> %o3(upper)
58465sllx %l3, 32, %o3
58466mov %l3, %l6
58467mov %l4, %l3
58468casx [%l7], %l6, %l3
58469! move %l3(upper) -> %o3(lower)
58470srlx %l3, 32, %l6
58471or %l6, %o3, %o3
58472! move %l3(lower) -> %o4(upper)
58473sllx %l3, 32, %o4
58474add %l4, 1, %l4
58475
58476P5497: !_DWLD [14] (Int)
58477sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
58478sub %i0, %i2, %i2
58479ldx [%i2 + 8], %l7
58480! move %l7(lower) -> %o4(lower)
58481srl %l7, 0, %l6
58482or %l6, %o4, %o4
58483!---- flushing int results buffer----
58484mov %o0, %l5
58485mov %o1, %l5
58486mov %o2, %l5
58487mov %o3, %l5
58488mov %o4, %l5
58489
58490P5498: !_DWST_BINIT [19] (maybe <- 0x28000c9) (Int)
58491wr %g0, 0xe2, %asi
58492sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
58493sub %i0, %i3, %i3
58494sllx %l4, 32, %o5
58495add %l4, 1, %l4
58496or %o5, %l4, %o5
58497stxa %o5, [%i3 + 0] %asi
58498add %l4, 1, %l4
58499
58500P5499: !_MEMBAR (Int)
58501membar #StoreLoad
58502
58503P5500: !_BLD [14] (FP)
58504wr %g0, 0xf0, %asi
58505ldda [%i2 + 0] %asi, %f32
58506membar #Sync
58507! 3 addresses covered
58508fmovd %f32, %f14
58509!---- flushing fp results buffer to %f30 ----
58510fmovd %f0, %f30
58511fmovd %f2, %f30
58512fmovd %f4, %f30
58513fmovd %f6, %f30
58514fmovd %f8, %f30
58515fmovd %f10, %f30
58516fmovd %f12, %f30
58517fmovd %f14, %f30
58518!--
58519fmovd %f34, %f18
58520fmovs %f19, %f0
58521
58522P5501: !_MEMBAR (FP)
58523
58524P5502: !_DWST_BINIT [0] (maybe <- 0x28000cb) (Int)
58525wr %g0, 0xe2, %asi
58526sllx %l4, 32, %l7
58527add %l4, 1, %l4
58528or %l7, %l4, %l7
58529stxa %l7, [%i0 + 0] %asi
58530add %l4, 1, %l4
58531
58532P5503: !_MEMBAR (Int)
58533membar #StoreLoad
58534
58535P5504: !_PREFETCH [22] (Int)
58536sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
58537add %i0, %i2, %i2
58538prefetch [%i2 + 4], 22
58539
58540P5505: !_ST_BINIT [15] (maybe <- 0x28000cd) (Int)
58541wr %g0, 0xe2, %asi
58542sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
58543sub %i0, %i3, %i3
58544stwa %l4, [%i3 + 0] %asi
58545add %l4, 1, %l4
58546
58547P5506: !_MEMBAR (Int)
58548membar #StoreLoad
58549
58550P5507: !_CASX [2] (maybe <- 0x28000ce) (Int)
58551add %i0, 8, %l6
58552ldx [%l6], %o0
58553! move %o0(upper) -> %o0(upper)
58554! move %o0(lower) -> %o0(lower)
58555mov %o0, %l3
58556mov %l4, %o1
58557casx [%l6], %l3, %o1
58558! move %o1(upper) -> %o1(upper)
58559! move %o1(lower) -> %o1(lower)
58560add %l4, 1, %l4
58561
58562P5508: !_MEMBAR (FP)
58563
58564P5509: !_BST [12] (maybe <- 0x4200007b) (FP) (CBR)
58565wr %g0, 0xf0, %asi
58566sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
58567sub %i0, %i2, %i2
58568! preparing store val #0, next val will be in f32
58569fmovs %f16, %f20
58570fadds %f16, %f17, %f16
58571! preparing store val #1, next val will be in f33
58572fmovs %f16, %f21
58573fadds %f16, %f17, %f16
58574! preparing store val #2, next val will be in f35
58575fmovd %f20, %f32
58576fmovs %f16, %f21
58577fadds %f16, %f17, %f16
58578fmovd %f20, %f34
58579membar #Sync
58580stda %f32, [%i2 + 0 ] %asi
58581
58582! cbranch
58583andcc %l0, 1, %g0
58584be,pn %xcc, TARGET5509
58585nop
58586RET5509:
58587
58588! lfsr step begin
58589srlx %l0, 1, %o5
58590xnor %o5, %l0, %o5
58591sllx %o5, 63, %o5
58592or %o5, %l0, %l0
58593srlx %l0, 1, %l0
58594
58595
58596P5510: !_MEMBAR (FP)
58597membar #StoreLoad
58598
58599P5511: !_SWAP [21] (maybe <- 0x28000cf) (Int) (CBR)
58600sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
58601add %i0, %i3, %i3
58602mov %l4, %o2
58603swap [%i3 + 0], %o2
58604! move %o2(lower) -> %o2(upper)
58605sllx %o2, 32, %o2
58606add %l4, 1, %l4
58607
58608! cbranch
58609andcc %l0, 1, %g0
58610be,pn %xcc, TARGET5511
58611nop
58612RET5511:
58613
58614! lfsr step begin
58615srlx %l0, 1, %o5
58616xnor %o5, %l0, %o5
58617sllx %o5, 63, %o5
58618or %o5, %l0, %l0
58619srlx %l0, 1, %l0
58620
58621
58622P5512: !_CAS [17] (maybe <- 0x28000d0) (Int)
58623sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
58624sub %i0, %i2, %i2
58625add %i2, 12, %l6
58626lduw [%l6], %o5
58627mov %o5, %l3
58628! move %l3(lower) -> %o2(lower)
58629or %l3, %o2, %o2
58630mov %l4, %o3
58631cas [%l6], %l3, %o3
58632! move %o3(lower) -> %o3(upper)
58633sllx %o3, 32, %o3
58634add %l4, 1, %l4
58635
58636P5513: !_ST_BINIT [11] (maybe <- 0x28000d1) (Int)
58637wr %g0, 0xe2, %asi
58638sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
58639add %i0, %i3, %i3
58640stwa %l4, [%i3 + 12] %asi
58641add %l4, 1, %l4
58642
58643P5514: !_MEMBAR (Int)
58644membar #StoreLoad
58645
58646P5515: !_LDD [0] (Int)
58647ldd [%i0 + 0], %l6
58648! move %l6(lower) -> %o3(lower)
58649or %l6, %o3, %o3
58650! move %l7(lower) -> %o4(upper)
58651sllx %l7, 32, %o4
58652
58653P5516: !_ST [7] (maybe <- 0x28000d2) (Int)
58654sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
58655sub %i0, %i2, %i2
58656stw %l4, [%i2 + 4 ]
58657add %l4, 1, %l4
58658
58659P5517: !_SWAP [19] (maybe <- 0x28000d3) (Int)
58660sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
58661sub %i0, %i3, %i3
58662mov %l4, %l6
58663swap [%i3 + 4], %l6
58664! move %l6(lower) -> %o4(lower)
58665srl %l6, 0, %o5
58666or %o5, %o4, %o4
58667!---- flushing int results buffer----
58668mov %o0, %l5
58669mov %o1, %l5
58670mov %o2, %l5
58671mov %o3, %l5
58672mov %o4, %l5
58673add %l4, 1, %l4
58674
58675P5518: !_MEMBAR (FP) (Branch target of P5892)
58676ba P5519
58677nop
58678
58679TARGET5892:
58680ba RET5892
58681nop
58682
58683
58684P5519: !_BSTC [0] (maybe <- 0x4200007e) (FP) (Branch target of P5350)
58685wr %g0, 0xe0, %asi
58686! preparing store val #0, next val will be in f32
58687fmovs %f16, %f20
58688fadds %f16, %f17, %f16
58689! preparing store val #1, next val will be in f33
58690fmovs %f16, %f21
58691fadds %f16, %f17, %f16
58692! preparing store val #2, next val will be in f35
58693fmovd %f20, %f32
58694fmovs %f16, %f21
58695fadds %f16, %f17, %f16
58696fmovd %f20, %f34
58697membar #Sync
58698stda %f32, [%i0 + 0 ] %asi
58699ba P5520
58700nop
58701
58702TARGET5350:
58703ba RET5350
58704nop
58705
58706
58707P5520: !_MEMBAR (FP)
58708membar #StoreLoad
58709
58710P5521: !_ST [3] (maybe <- 0x42000081) (FP) (Branch target of P5660)
58711! preparing store val #0, next val will be in f20
58712fmovs %f16, %f20
58713fadds %f16, %f17, %f16
58714st %f20, [%i1 + 0 ]
58715ba P5522
58716nop
58717
58718TARGET5660:
58719ba RET5660
58720nop
58721
58722
58723P5522: !_MEMBAR (FP)
58724
58725P5523: !_BST [23] (maybe <- 0x42000082) (FP)
58726wr %g0, 0xf0, %asi
58727sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
58728add %i0, %i2, %i2
58729! preparing store val #0, next val will be in f32
58730fmovs %f16, %f20
58731fadds %f16, %f17, %f16
58732! preparing store val #1, next val will be in f33
58733fmovs %f16, %f21
58734fadds %f16, %f17, %f16
58735! preparing store val #2, next val will be in f35
58736fmovd %f20, %f32
58737fmovs %f16, %f21
58738fadds %f16, %f17, %f16
58739fmovd %f20, %f34
58740membar #Sync
58741stda %f32, [%i2 + 0 ] %asi
58742
58743P5524: !_MEMBAR (FP)
58744
58745P5525: !_BST [3] (maybe <- 0x42000085) (FP)
58746!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
58747!Logical addr: 3
58748
58749sethi %hi(0x200000), %o5
58750sub %i1, %o5, %i1
58751wr %g0, 0xf0, %asi
58752! preparing store val #0, next val will be in f32
58753fmovs %f16, %f20
58754fadds %f16, %f17, %f16
58755! preparing store val #1, next val will be in f33
58756fmovs %f16, %f21
58757fadds %f16, %f17, %f16
58758! preparing store val #2, next val will be in f35
58759fmovd %f20, %f32
58760fmovs %f16, %f21
58761fadds %f16, %f17, %f16
58762fmovd %f20, %f34
58763membar #Sync
58764stda %f32, [%i1 + 0 ] %asi
58765
58766P5526: !_MEMBAR (FP)
58767membar #StoreLoad
58768
58769P5527: !_LDD [10] (Int)
58770sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
58771add %i0, %i3, %i3
58772ldd [%i3 + 0], %l6
58773! move %l6(lower) -> %o0(upper)
58774sllx %l6, 32, %o0
58775! move %l7(lower) -> %o0(lower)
58776or %l7, %o0, %o0
58777
58778P5528: !_DWST [17] (maybe <- 0x28000d4) (Int)
58779sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
58780sub %i0, %i2, %i2
58781mov %l4, %l3
58782stx %l3, [%i2 + 8]
58783add %l4, 1, %l4
58784
58785P5529: !_LDD [18] (Int)
58786sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
58787sub %i0, %i3, %i3
58788ldd [%i3 + 0], %l6
58789! move %l6(lower) -> %o1(upper)
58790sllx %l6, 32, %o1
58791! move %l7(lower) -> %o1(lower)
58792or %l7, %o1, %o1
58793
58794P5530: !_CAS [8] (maybe <- 0x28000d5) (Int)
58795sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
58796sub %i0, %i2, %i2
58797add %i2, 12, %l6
58798lduw [%l6], %o2
58799mov %o2, %l3
58800! move %l3(lower) -> %o2(upper)
58801sllx %l3, 32, %o2
58802mov %l4, %o5
58803cas [%l6], %l3, %o5
58804! move %o5(lower) -> %o2(lower)
58805srl %o5, 0, %l3
58806or %l3, %o2, %o2
58807add %l4, 1, %l4
58808
58809P5531: !_DWST [13] (maybe <- 0x28000d6) (Int)
58810sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
58811sub %i0, %i3, %i3
58812sllx %l4, 32, %l3
58813add %l4, 1, %l4
58814or %l3, %l4, %l3
58815stx %l3, [%i3 + 0]
58816add %l4, 1, %l4
58817
58818P5532: !_SWAP [6] (maybe <- 0x28000d8) (Int)
58819mov %l4, %o3
58820swap [%i2 + 0], %o3
58821! move %o3(lower) -> %o3(upper)
58822sllx %o3, 32, %o3
58823add %l4, 1, %l4
58824
58825P5533: !_DWST_BINIT [5] (maybe <- 0x28000d9) (Int)
58826wr %g0, 0xe2, %asi
58827mov %l4, %l7
58828stxa %l7, [%i1 + 8] %asi
58829add %l4, 1, %l4
58830
58831P5534: !_MEMBAR (Int)
58832membar #StoreLoad
58833
58834P5535: !_SWAP [16] (maybe <- 0x28000da) (Int)
58835sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
58836sub %i0, %i2, %i2
58837mov %l4, %o5
58838swap [%i2 + 4], %o5
58839! move %o5(lower) -> %o3(lower)
58840srl %o5, 0, %l6
58841or %l6, %o3, %o3
58842add %l4, 1, %l4
58843
58844P5536: !_LDD [18] (Int)
58845sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
58846sub %i0, %i3, %i3
58847ldd [%i3 + 0], %l6
58848! move %l6(lower) -> %o4(upper)
58849sllx %l6, 32, %o4
58850! move %l7(lower) -> %o4(lower)
58851or %l7, %o4, %o4
58852!---- flushing int results buffer----
58853mov %o0, %l5
58854mov %o1, %l5
58855mov %o2, %l5
58856mov %o3, %l5
58857mov %o4, %l5
58858
58859P5537: !_PREFETCH [11] (Int) (LE)
58860wr %g0, 0x88, %asi
58861sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
58862add %i0, %i2, %i2
58863prefetcha [%i2 + 12] %asi, 22
58864
58865P5538: !_ST_BINIT [9] (maybe <- 0x28000db) (Int)
58866wr %g0, 0xe2, %asi
58867stwa %l4, [%i2 + 0] %asi
58868add %l4, 1, %l4
58869
58870P5539: !_MEMBAR (Int)
58871membar #StoreLoad
58872
58873P5540: !_PREFETCH [9] (Int)
58874prefetch [%i2 + 0], 4
58875
58876P5541: !_SWAP [0] (maybe <- 0x28000dc) (Int)
58877mov %l4, %o0
58878swap [%i0 + 0], %o0
58879! move %o0(lower) -> %o0(upper)
58880sllx %o0, 32, %o0
58881add %l4, 1, %l4
58882
58883P5542: !_CASX [10] (maybe <- 0x28000dd) (Int) (Branch target of P5509)
58884ldx [%i2], %l6
58885! move %l6(upper) -> %o0(lower)
58886srlx %l6, 32, %l7
58887or %l7, %o0, %o0
58888! move %l6(lower) -> %o1(upper)
58889sllx %l6, 32, %o1
58890mov %l6, %l7
58891sllx %l4, 32, %l6
58892add %l4, 1, %l4
58893or %l4, %l6, %l6
58894casx [%i2], %l7, %l6
58895! move %l6(upper) -> %o1(lower)
58896srlx %l6, 32, %l7
58897or %l7, %o1, %o1
58898! move %l6(lower) -> %o2(upper)
58899sllx %l6, 32, %o2
58900add %l4, 1, %l4
58901ba P5543
58902nop
58903
58904TARGET5509:
58905ba RET5509
58906nop
58907
58908
58909P5543: !_CASX [3] (maybe <- 0x28000df) (Int) (Branch target of P5488)
58910ldx [%i1], %l6
58911! move %l6(upper) -> %o2(lower)
58912srlx %l6, 32, %l7
58913or %l7, %o2, %o2
58914! move %l6(lower) -> %o3(upper)
58915sllx %l6, 32, %o3
58916mov %l6, %l7
58917sllx %l4, 32, %l6
58918add %l4, 1, %l4
58919or %l4, %l6, %l6
58920casx [%i1], %l7, %l6
58921! move %l6(upper) -> %o3(lower)
58922srlx %l6, 32, %l7
58923or %l7, %o3, %o3
58924! move %l6(lower) -> %o4(upper)
58925sllx %l6, 32, %o4
58926add %l4, 1, %l4
58927ba P5544
58928nop
58929
58930TARGET5488:
58931ba RET5488
58932nop
58933
58934
58935P5544: !_MEMBAR (FP)
58936membar #StoreLoad
58937
58938P5545: !_BLD [23] (FP)
58939wr %g0, 0xf0, %asi
58940sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
58941add %i0, %i3, %i3
58942ldda [%i3 + 0] %asi, %f32
58943membar #Sync
58944! 3 addresses covered
58945fmovd %f32, %f18
58946fmovs %f18, %f1
58947fmovs %f19, %f2
58948fmovd %f34, %f18
58949fmovs %f19, %f3
58950
58951P5546: !_MEMBAR (FP)
58952
58953P5547: !_LD [17] (Int)
58954sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
58955sub %i0, %i2, %i2
58956lduw [%i2 + 12], %o5
58957! move %o5(lower) -> %o4(lower)
58958or %o5, %o4, %o4
58959!---- flushing int results buffer----
58960mov %o0, %l5
58961mov %o1, %l5
58962mov %o2, %l5
58963mov %o3, %l5
58964mov %o4, %l5
58965
58966P5548: !_DWLD [15] (Int)
58967ldx [%i2 + 0], %o0
58968! move %o0(upper) -> %o0(upper)
58969! move %o0(lower) -> %o0(lower)
58970
58971P5549: !_MEMBAR (FP)
58972membar #StoreLoad
58973
58974P5550: !_BLD [12] (FP)
58975wr %g0, 0xf0, %asi
58976sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
58977sub %i0, %i3, %i3
58978ldda [%i3 + 0] %asi, %f32
58979membar #Sync
58980! 3 addresses covered
58981fmovd %f32, %f4
58982fmovd %f34, %f18
58983fmovs %f19, %f6
58984
58985P5551: !_MEMBAR (FP)
58986
58987P5552: !_SWAP [17] (maybe <- 0x28000e1) (Int)
58988mov %l4, %o1
58989swap [%i2 + 12], %o1
58990! move %o1(lower) -> %o1(upper)
58991sllx %o1, 32, %o1
58992add %l4, 1, %l4
58993
58994P5553: !_DWST_BINIT [10] (maybe <- 0x28000e2) (Int) (LE)
58995wr %g0, 0xea, %asi
58996sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
58997add %i0, %i2, %i2
58998sllx %l4, 32, %l6
58999add %l4, 1, %l4
59000or %l6, %l4, %l7
59001! Change double-word-level endianess (big endian <-> little endian)
59002sethi %hi(0xff00ff00), %o5
59003or %o5, %lo(0xff00ff00), %o5
59004sllx %o5, 32, %l6
59005or %o5, %l6, %o5
59006and %l7, %o5, %l6
59007srlx %l6, 8, %l6
59008sllx %l7, 8, %l7
59009and %l7, %o5, %l7
59010or %l7, %l6, %l7
59011sethi %hi(0xffff0000), %o5
59012srlx %l7, 16, %l6
59013andn %l6, %o5, %l6
59014andn %l7, %o5, %l7
59015sllx %l7, 16, %l7
59016or %l7, %l6, %l7
59017srlx %l7, 32, %l6
59018sllx %l7, 32, %l7
59019or %l7, %l6, %l6
59020stxa %l6, [%i2 + 0 ] %asi
59021add %l4, 1, %l4
59022
59023P5554: !_MEMBAR (Int) (LE)
59024membar #StoreLoad
59025
59026P5555: !_DWST_BINIT [8] (maybe <- 0x28000e4) (Int) (CBR)
59027wr %g0, 0xe2, %asi
59028sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
59029sub %i0, %i3, %i3
59030mov %l4, %l3
59031stxa %l3, [%i3 + 8] %asi
59032add %l4, 1, %l4
59033
59034! cbranch
59035andcc %l0, 1, %g0
59036be,pt %xcc, TARGET5555
59037nop
59038RET5555:
59039
59040! lfsr step begin
59041srlx %l0, 1, %o5
59042xnor %o5, %l0, %o5
59043sllx %o5, 63, %o5
59044or %o5, %l0, %l0
59045srlx %l0, 1, %l0
59046
59047
59048P5556: !_MEMBAR (Int)
59049membar #StoreLoad
59050
59051P5557: !_LD [19] (Int)
59052sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
59053sub %i0, %i2, %i2
59054lduw [%i2 + 4], %l6
59055! move %l6(lower) -> %o1(lower)
59056or %l6, %o1, %o1
59057
59058P5558: !_DWLD [12] (Int)
59059sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
59060sub %i0, %i3, %i3
59061ldx [%i3 + 0], %o2
59062! move %o2(upper) -> %o2(upper)
59063! move %o2(lower) -> %o2(lower)
59064
59065P5559: !_DWLD [11] (Int)
59066sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
59067add %i0, %i2, %i2
59068ldx [%i2 + 8], %o3
59069! move %o3(lower) -> %o3(upper)
59070sllx %o3, 32, %o3
59071
59072P5560: !_ST_BINIT [5] (maybe <- 0x28000e5) (Int)
59073wr %g0, 0xe2, %asi
59074stwa %l4, [%i1 + 12] %asi
59075add %l4, 1, %l4
59076
59077P5561: !_MEMBAR (Int)
59078membar #StoreLoad
59079
59080P5562: !_BLD [2] (FP)
59081wr %g0, 0xf0, %asi
59082ldda [%i0 + 0] %asi, %f32
59083membar #Sync
59084! 3 addresses covered
59085fmovd %f32, %f18
59086fmovs %f18, %f7
59087fmovs %f19, %f8
59088fmovd %f34, %f18
59089fmovs %f19, %f9
59090
59091P5563: !_MEMBAR (FP)
59092
59093P5564: !_ST_BINIT [2] (maybe <- 0x28000e6) (Int)
59094wr %g0, 0xe2, %asi
59095stwa %l4, [%i0 + 12] %asi
59096add %l4, 1, %l4
59097
59098P5565: !_MEMBAR (Int)
59099membar #StoreLoad
59100
59101P5566: !_DWST_BINIT [16] (maybe <- 0x28000e7) (Int)
59102wr %g0, 0xe2, %asi
59103sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
59104sub %i0, %i3, %i3
59105sllx %l4, 32, %l3
59106add %l4, 1, %l4
59107or %l3, %l4, %l3
59108stxa %l3, [%i3 + 0] %asi
59109add %l4, 1, %l4
59110
59111P5567: !_MEMBAR (Int)
59112membar #StoreLoad
59113
59114P5568: !_LD [2] (FP)
59115ld [%i0 + 12], %f10
59116! 1 addresses covered
59117
59118P5569: !_ST_BINIT [22] (maybe <- 0x28000e9) (Int) (Branch target of P5295)
59119wr %g0, 0xe2, %asi
59120sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
59121add %i0, %i2, %i2
59122stwa %l4, [%i2 + 4] %asi
59123add %l4, 1, %l4
59124ba P5570
59125nop
59126
59127TARGET5295:
59128ba RET5295
59129nop
59130
59131
59132P5570: !_MEMBAR (Int)
59133membar #StoreLoad
59134
59135P5571: !_SWAP [13] (maybe <- 0x28000ea) (Int) (LE)
59136wr %g0, 0x88, %asi
59137sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
59138sub %i0, %i3, %i3
59139mov %l4, %l3
59140! Change single-word-level endianess (big endian <-> little endian)
59141sethi %hi(0xff00ff00), %l7
59142or %l7, %lo(0xff00ff00), %l7
59143and %l3, %l7, %o5
59144srl %o5, 8, %o5
59145sll %l3, 8, %l3
59146and %l3, %l7, %l3
59147or %l3, %o5, %l3
59148srl %l3, 16, %o5
59149sll %l3, 16, %l3
59150srl %l3, 0, %l3
59151or %l3, %o5, %l3
59152swapa [%i3 + 4] %asi, %l3
59153! move %l3(lower) -> %o3(lower)
59154srl %l3, 0, %l7
59155or %l7, %o3, %o3
59156add %l4, 1, %l4
59157
59158P5572: !_CAS [13] (maybe <- 0x28000eb) (Int) (LE)
59159! Change single-word-level endianess (big endian <-> little endian)
59160sethi %hi(0xff00ff00), %l7
59161or %l7, %lo(0xff00ff00), %l7
59162and %l4, %l7, %l6
59163srl %l6, 8, %l6
59164sll %l4, 8, %o5
59165and %o5, %l7, %o5
59166or %o5, %l6, %o5
59167srl %o5, 16, %l6
59168sll %o5, 16, %o5
59169srl %o5, 0, %o5
59170or %o5, %l6, %o5
59171wr %g0, 0x88, %asi
59172add %i3, 4, %l7
59173lduwa [%l7] %asi, %o4
59174mov %o4, %l6
59175! move %l6(lower) -> %o4(upper)
59176sllx %l6, 32, %o4
59177mov %o5, %l3
59178casa [%l7] %asi, %l6, %l3
59179! move %l3(lower) -> %o4(lower)
59180srl %l3, 0, %l6
59181or %l6, %o4, %o4
59182!---- flushing int results buffer----
59183mov %o0, %l5
59184mov %o1, %l5
59185mov %o2, %l5
59186mov %o3, %l5
59187mov %o4, %l5
59188add %l4, 1, %l4
59189
59190P5573: !_MEMBAR (FP)
59191
59192P5574: !_BST [5] (maybe <- 0x42000088) (FP)
59193wr %g0, 0xf0, %asi
59194! preparing store val #0, next val will be in f32
59195fmovs %f16, %f20
59196fadds %f16, %f17, %f16
59197! preparing store val #1, next val will be in f33
59198fmovs %f16, %f21
59199fadds %f16, %f17, %f16
59200! preparing store val #2, next val will be in f35
59201fmovd %f20, %f32
59202fmovs %f16, %f21
59203fadds %f16, %f17, %f16
59204fmovd %f20, %f34
59205membar #Sync
59206stda %f32, [%i1 + 0 ] %asi
59207
59208P5575: !_MEMBAR (FP)
59209membar #StoreLoad
59210
59211P5576: !_CAS [3] (maybe <- 0x28000ec) (Int) (CBR)
59212lduw [%i1], %o0
59213mov %o0, %l3
59214! move %l3(lower) -> %o0(upper)
59215sllx %l3, 32, %o0
59216mov %l4, %o5
59217cas [%i1], %l3, %o5
59218! move %o5(lower) -> %o0(lower)
59219srl %o5, 0, %l3
59220or %l3, %o0, %o0
59221add %l4, 1, %l4
59222
59223! cbranch
59224andcc %l0, 1, %g0
59225be,pn %xcc, TARGET5576
59226nop
59227RET5576:
59228
59229! lfsr step begin
59230srlx %l0, 1, %l3
59231xnor %l3, %l0, %l3
59232sllx %l3, 63, %l3
59233or %l3, %l0, %l0
59234srlx %l0, 1, %l0
59235
59236
59237P5577: !_MEMBAR (FP)
59238
59239P5578: !_BSTC [18] (maybe <- 0x4200008b) (FP)
59240wr %g0, 0xe0, %asi
59241sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
59242sub %i0, %i2, %i2
59243! preparing store val #0, next val will be in f32
59244fmovs %f16, %f20
59245fadds %f16, %f17, %f16
59246! preparing store val #1, next val will be in f33
59247fmovs %f16, %f21
59248fadds %f16, %f17, %f16
59249! preparing store val #2, next val will be in f35
59250fmovd %f20, %f32
59251fmovs %f16, %f21
59252fadds %f16, %f17, %f16
59253fmovd %f20, %f34
59254membar #Sync
59255stda %f32, [%i2 + 0 ] %asi
59256
59257P5579: !_MEMBAR (FP)
59258membar #StoreLoad
59259
59260P5580: !_DWST_BINIT [5] (maybe <- 0x28000ed) (Int)
59261wr %g0, 0xe2, %asi
59262mov %l4, %l3
59263stxa %l3, [%i1 + 8] %asi
59264add %l4, 1, %l4
59265
59266P5581: !_MEMBAR (Int)
59267membar #StoreLoad
59268
59269P5582: !_ST_BINIT [5] (maybe <- 0x28000ee) (Int)
59270wr %g0, 0xe2, %asi
59271stwa %l4, [%i1 + 12] %asi
59272add %l4, 1, %l4
59273
59274P5583: !_MEMBAR (Int)
59275membar #StoreLoad
59276
59277P5584: !_DWLD [13] (Int)
59278ldx [%i3 + 0], %o1
59279! move %o1(upper) -> %o1(upper)
59280! move %o1(lower) -> %o1(lower)
59281
59282P5585: !_MEMBAR (FP)
59283
59284P5586: !_BSTC [0] (maybe <- 0x4200008e) (FP)
59285wr %g0, 0xe0, %asi
59286! preparing store val #0, next val will be in f32
59287fmovs %f16, %f20
59288fadds %f16, %f17, %f16
59289! preparing store val #1, next val will be in f33
59290fmovs %f16, %f21
59291fadds %f16, %f17, %f16
59292! preparing store val #2, next val will be in f35
59293fmovd %f20, %f32
59294fmovs %f16, %f21
59295fadds %f16, %f17, %f16
59296fmovd %f20, %f34
59297membar #Sync
59298stda %f32, [%i0 + 0 ] %asi
59299
59300P5587: !_MEMBAR (FP)
59301membar #StoreLoad
59302
59303P5588: !_PREFETCH [13] (Int)
59304prefetch [%i3 + 4], 21
59305
59306P5589: !_MEMBAR (FP)
59307
59308P5590: !_BST [18] (maybe <- 0x42000091) (FP)
59309wr %g0, 0xf0, %asi
59310! preparing store val #0, next val will be in f32
59311fmovs %f16, %f20
59312fadds %f16, %f17, %f16
59313! preparing store val #1, next val will be in f33
59314fmovs %f16, %f21
59315fadds %f16, %f17, %f16
59316! preparing store val #2, next val will be in f35
59317fmovd %f20, %f32
59318fmovs %f16, %f21
59319fadds %f16, %f17, %f16
59320fmovd %f20, %f34
59321membar #Sync
59322stda %f32, [%i2 + 0 ] %asi
59323
59324P5591: !_MEMBAR (FP)
59325membar #StoreLoad
59326
59327P5592: !_LD [1] (Int) (CBR)
59328lduw [%i0 + 4], %o2
59329! move %o2(lower) -> %o2(upper)
59330sllx %o2, 32, %o2
59331
59332! cbranch
59333andcc %l0, 1, %g0
59334be,pt %xcc, TARGET5592
59335nop
59336RET5592:
59337
59338! lfsr step begin
59339srlx %l0, 1, %l6
59340xnor %l6, %l0, %l6
59341sllx %l6, 63, %l6
59342or %l6, %l0, %l0
59343srlx %l0, 1, %l0
59344
59345
59346P5593: !_ST_BINIT [3] (maybe <- 0x28000ef) (Int)
59347wr %g0, 0xe2, %asi
59348stwa %l4, [%i1 + 0] %asi
59349add %l4, 1, %l4
59350
59351P5594: !_MEMBAR (Int) (CBR)
59352membar #StoreLoad
59353
59354! cbranch
59355andcc %l0, 1, %g0
59356be,pn %xcc, TARGET5594
59357nop
59358RET5594:
59359
59360! lfsr step begin
59361srlx %l0, 1, %l6
59362xnor %l6, %l0, %l6
59363sllx %l6, 63, %l6
59364or %l6, %l0, %l0
59365srlx %l0, 1, %l0
59366
59367
59368P5595: !_LDD [10] (Int)
59369sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
59370add %i0, %i3, %i3
59371ldd [%i3 + 0], %l6
59372! move %l6(lower) -> %o2(lower)
59373or %l6, %o2, %o2
59374! move %l7(lower) -> %o3(upper)
59375sllx %l7, 32, %o3
59376
59377P5596: !_PREFETCH [22] (Int)
59378sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
59379add %i0, %i2, %i2
59380prefetch [%i2 + 4], 1
59381
59382P5597: !_ST [13] (maybe <- 0x42000094) (FP)
59383sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
59384sub %i0, %i3, %i3
59385! preparing store val #0, next val will be in f20
59386fmovs %f16, %f20
59387fadds %f16, %f17, %f16
59388st %f20, [%i3 + 4 ]
59389
59390P5598: !_MEMBAR (FP)
59391
59392P5599: !_BST [15] (maybe <- 0x42000095) (FP)
59393wr %g0, 0xf0, %asi
59394sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
59395sub %i0, %i2, %i2
59396! preparing store val #0, next val will be in f32
59397fmovs %f16, %f20
59398fadds %f16, %f17, %f16
59399! preparing store val #1, next val will be in f33
59400fmovs %f16, %f21
59401fadds %f16, %f17, %f16
59402! preparing store val #2, next val will be in f35
59403fmovd %f20, %f32
59404fmovs %f16, %f21
59405fadds %f16, %f17, %f16
59406fmovd %f20, %f34
59407membar #Sync
59408stda %f32, [%i2 + 0 ] %asi
59409
59410P5600: !_MEMBAR (FP)
59411membar #StoreLoad
59412
59413P5601: !_REPLACEMENT [8] (Int)
59414sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
59415sub %i0, %i3, %i3
59416sethi %hi(0x20000), %l7
59417ld [%i3+12], %l3
59418st %l3, [%i3+12]
59419add %i3, %l7, %o5
59420ld [%o5+12], %l3
59421st %l3, [%o5+12]
59422add %o5, %l7, %o5
59423ld [%o5+12], %l3
59424st %l3, [%o5+12]
59425add %o5, %l7, %o5
59426ld [%o5+12], %l3
59427st %l3, [%o5+12]
59428add %o5, %l7, %o5
59429ld [%o5+12], %l3
59430st %l3, [%o5+12]
59431add %o5, %l7, %o5
59432ld [%o5+12], %l3
59433st %l3, [%o5+12]
59434add %o5, %l7, %o5
59435ld [%o5+12], %l3
59436st %l3, [%o5+12]
59437add %o5, %l7, %o5
59438ld [%o5+12], %l3
59439st %l3, [%o5+12]
59440
59441P5602: !_PREFETCH [2] (Int)
59442prefetch [%i0 + 12], 22
59443
59444P5603: !_ST_BINIT [8] (maybe <- 0x28000f0) (Int)
59445wr %g0, 0xe2, %asi
59446sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
59447sub %i0, %i2, %i2
59448stwa %l4, [%i2 + 12] %asi
59449add %l4, 1, %l4
59450
59451P5604: !_MEMBAR (Int)
59452membar #StoreLoad
59453
59454P5605: !_CASX [0] (maybe <- 0x28000f1) (Int)
59455ldx [%i0], %o5
59456! move %o5(upper) -> %o3(lower)
59457srlx %o5, 32, %l3
59458or %l3, %o3, %o3
59459! move %o5(lower) -> %o4(upper)
59460sllx %o5, 32, %o4
59461mov %o5, %l3
59462sllx %l4, 32, %o5
59463add %l4, 1, %l4
59464or %l4, %o5, %o5
59465casx [%i0], %l3, %o5
59466! move %o5(upper) -> %o4(lower)
59467srlx %o5, 32, %l3
59468or %l3, %o4, %o4
59469!---- flushing int results buffer----
59470mov %o0, %l5
59471mov %o1, %l5
59472mov %o2, %l5
59473mov %o3, %l5
59474mov %o4, %l5
59475! move %o5(lower) -> %o0(upper)
59476sllx %o5, 32, %o0
59477add %l4, 1, %l4
59478
59479P5606: !_ST [23] (maybe <- 0x28000f3) (Int)
59480sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
59481add %i0, %i3, %i3
59482stw %l4, [%i3 + 12 ]
59483add %l4, 1, %l4
59484
59485P5607: !_LD [13] (Int)
59486sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
59487sub %i0, %i2, %i2
59488lduw [%i2 + 4], %l3
59489! move %l3(lower) -> %o0(lower)
59490or %l3, %o0, %o0
59491
59492P5608: !_LD [3] (Int)
59493lduw [%i1 + 0], %o1
59494! move %o1(lower) -> %o1(upper)
59495sllx %o1, 32, %o1
59496
59497P5609: !_MEMBAR (FP)
59498membar #StoreLoad
59499
59500P5610: !_BLD [3] (FP)
59501wr %g0, 0xf0, %asi
59502ldda [%i1 + 0] %asi, %f32
59503membar #Sync
59504! 3 addresses covered
59505fmovd %f32, %f18
59506fmovs %f18, %f11
59507fmovs %f19, %f12
59508fmovd %f34, %f18
59509fmovs %f19, %f13
59510
59511P5611: !_MEMBAR (FP)
59512
59513P5612: !_DWST [20] (maybe <- 0x28000f4) (Int) (CBR)
59514sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
59515sub %i0, %i3, %i3
59516mov %l4, %o5
59517stx %o5, [%i3 + 8]
59518add %l4, 1, %l4
59519
59520! cbranch
59521andcc %l0, 1, %g0
59522be,pn %xcc, TARGET5612
59523nop
59524RET5612:
59525
59526! lfsr step begin
59527srlx %l0, 1, %l7
59528xnor %l7, %l0, %l7
59529sllx %l7, 63, %l7
59530or %l7, %l0, %l0
59531srlx %l0, 1, %l0
59532
59533
59534P5613: !_DWST_BINIT [21] (maybe <- 0x28000f5) (Int) (CBR)
59535wr %g0, 0xe2, %asi
59536sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
59537add %i0, %i2, %i2
59538sllx %l4, 32, %o5
59539add %l4, 1, %l4
59540or %o5, %l4, %o5
59541stxa %o5, [%i2 + 0] %asi
59542add %l4, 1, %l4
59543
59544! cbranch
59545andcc %l0, 1, %g0
59546be,pn %xcc, TARGET5613
59547nop
59548RET5613:
59549
59550! lfsr step begin
59551srlx %l0, 1, %l7
59552xnor %l7, %l0, %l7
59553sllx %l7, 63, %l7
59554or %l7, %l0, %l0
59555srlx %l0, 1, %l0
59556
59557
59558P5614: !_MEMBAR (Int)
59559membar #StoreLoad
59560
59561P5615: !_DWLD [1] (Int)
59562ldx [%i0 + 0], %l3
59563! move %l3(upper) -> %o1(lower)
59564srlx %l3, 32, %o5
59565or %o5, %o1, %o1
59566! move %l3(lower) -> %o2(upper)
59567sllx %l3, 32, %o2
59568
59569P5616: !_PREFETCH [1] (Int)
59570prefetch [%i0 + 4], 18
59571
59572P5617: !_LDD [1] (Int)
59573ldd [%i0 + 0], %l6
59574! move %l6(lower) -> %o2(lower)
59575or %l6, %o2, %o2
59576! move %l7(lower) -> %o3(upper)
59577sllx %l7, 32, %o3
59578
59579P5618: !_MEMBAR (FP)
59580membar #StoreLoad
59581
59582P5619: !_BLD [6] (FP)
59583wr %g0, 0xf0, %asi
59584sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
59585sub %i0, %i3, %i3
59586ldda [%i3 + 0] %asi, %f32
59587membar #Sync
59588! 3 addresses covered
59589fmovd %f32, %f14
59590!---- flushing fp results buffer to %f30 ----
59591fmovd %f0, %f30
59592fmovd %f2, %f30
59593fmovd %f4, %f30
59594fmovd %f6, %f30
59595fmovd %f8, %f30
59596fmovd %f10, %f30
59597fmovd %f12, %f30
59598fmovd %f14, %f30
59599!--
59600fmovd %f34, %f18
59601fmovs %f19, %f0
59602
59603P5620: !_MEMBAR (FP)
59604
59605P5621: !_DWST_BINIT [4] (maybe <- 0x28000f7) (Int)
59606wr %g0, 0xe2, %asi
59607sllx %l4, 32, %l3
59608add %l4, 1, %l4
59609or %l3, %l4, %l3
59610stxa %l3, [%i1 + 0] %asi
59611add %l4, 1, %l4
59612
59613P5622: !_MEMBAR (Int)
59614
59615P5623: !_BST [15] (maybe <- 0x42000098) (FP)
59616wr %g0, 0xf0, %asi
59617sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
59618sub %i0, %i2, %i2
59619! preparing store val #0, next val will be in f32
59620fmovs %f16, %f20
59621fadds %f16, %f17, %f16
59622! preparing store val #1, next val will be in f33
59623fmovs %f16, %f21
59624fadds %f16, %f17, %f16
59625! preparing store val #2, next val will be in f35
59626fmovd %f20, %f32
59627fmovs %f16, %f21
59628fadds %f16, %f17, %f16
59629fmovd %f20, %f34
59630membar #Sync
59631stda %f32, [%i2 + 0 ] %asi
59632
59633P5624: !_MEMBAR (FP)
59634membar #StoreLoad
59635
59636P5625: !_CASX [4] (maybe <- 0x28000f9) (Int)
59637ldx [%i1], %l6
59638! move %l6(upper) -> %o3(lower)
59639srlx %l6, 32, %l7
59640or %l7, %o3, %o3
59641! move %l6(lower) -> %o4(upper)
59642sllx %l6, 32, %o4
59643mov %l6, %l7
59644sllx %l4, 32, %l6
59645add %l4, 1, %l4
59646or %l4, %l6, %l6
59647casx [%i1], %l7, %l6
59648! move %l6(upper) -> %o4(lower)
59649srlx %l6, 32, %l7
59650or %l7, %o4, %o4
59651!---- flushing int results buffer----
59652mov %o0, %l5
59653mov %o1, %l5
59654mov %o2, %l5
59655mov %o3, %l5
59656mov %o4, %l5
59657! move %l6(lower) -> %o0(upper)
59658sllx %l6, 32, %o0
59659add %l4, 1, %l4
59660
59661P5626: !_DWST_BINIT [3] (maybe <- 0x28000fb) (Int)
59662wr %g0, 0xe2, %asi
59663sllx %l4, 32, %l7
59664add %l4, 1, %l4
59665or %l7, %l4, %l7
59666stxa %l7, [%i1 + 0] %asi
59667add %l4, 1, %l4
59668
59669P5627: !_MEMBAR (Int)
59670membar #StoreLoad
59671
59672P5628: !_SWAP [0] (maybe <- 0x28000fd) (Int)
59673mov %l4, %o5
59674swap [%i0 + 0], %o5
59675! move %o5(lower) -> %o0(lower)
59676srl %o5, 0, %l6
59677or %l6, %o0, %o0
59678add %l4, 1, %l4
59679
59680P5629: !_PREFETCH [8] (Int)
59681prefetch [%i3 + 12], 0
59682
59683P5630: !_CASX [6] (maybe <- 0x28000fe) (Int)
59684ldx [%i3], %o1
59685! move %o1(upper) -> %o1(upper)
59686! move %o1(lower) -> %o1(lower)
59687mov %o1, %l3
59688sllx %l4, 32, %o2
59689add %l4, 1, %l4
59690or %l4, %o2, %o2
59691casx [%i3], %l3, %o2
59692! move %o2(upper) -> %o2(upper)
59693! move %o2(lower) -> %o2(lower)
59694add %l4, 1, %l4
59695
59696P5631: !_SWAP [22] (maybe <- 0x2800100) (Int) (Branch target of P5480)
59697sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
59698add %i0, %i3, %i3
59699mov %l4, %o3
59700swap [%i3 + 4], %o3
59701! move %o3(lower) -> %o3(upper)
59702sllx %o3, 32, %o3
59703add %l4, 1, %l4
59704ba P5632
59705nop
59706
59707TARGET5480:
59708ba RET5480
59709nop
59710
59711
59712P5632: !_PREFETCH [12] (Int)
59713sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
59714sub %i0, %i2, %i2
59715prefetch [%i2 + 0], 20
59716
59717P5633: !_LD [15] (Int)
59718sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
59719sub %i0, %i3, %i3
59720lduw [%i3 + 0], %l3
59721! move %l3(lower) -> %o3(lower)
59722or %l3, %o3, %o3
59723
59724P5634: !_MEMBAR (FP) (Branch target of P5445)
59725ba P5635
59726nop
59727
59728TARGET5445:
59729ba RET5445
59730nop
59731
59732
59733P5635: !_BSTC [0] (maybe <- 0x4200009b) (FP)
59734wr %g0, 0xe0, %asi
59735! preparing store val #0, next val will be in f32
59736fmovs %f16, %f20
59737fadds %f16, %f17, %f16
59738! preparing store val #1, next val will be in f33
59739fmovs %f16, %f21
59740fadds %f16, %f17, %f16
59741! preparing store val #2, next val will be in f35
59742fmovd %f20, %f32
59743fmovs %f16, %f21
59744fadds %f16, %f17, %f16
59745fmovd %f20, %f34
59746membar #Sync
59747stda %f32, [%i0 + 0 ] %asi
59748
59749P5636: !_MEMBAR (FP)
59750membar #StoreLoad
59751
59752P5637: !_LD [14] (Int)
59753lduw [%i2 + 12], %o4
59754! move %o4(lower) -> %o4(upper)
59755sllx %o4, 32, %o4
59756
59757P5638: !_DWLD [4] (Int) (LE)
59758wr %g0, 0x88, %asi
59759ldxa [%i1 + 0] %asi, %o5
59760! move %o5(lower) -> %o4(lower)
59761srl %o5, 0, %l7
59762or %l7, %o4, %o4
59763!---- flushing int results buffer----
59764mov %o0, %l5
59765mov %o1, %l5
59766mov %o2, %l5
59767mov %o3, %l5
59768mov %o4, %l5
59769! move %o5(upper) -> %o0(upper)
59770or %o5, %g0, %o0
59771
59772P5639: !_MEMBAR (FP)
59773membar #StoreLoad
59774
59775P5640: !_BLD [22] (FP)
59776wr %g0, 0xf0, %asi
59777sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
59778add %i0, %i2, %i2
59779ldda [%i2 + 0] %asi, %f32
59780membar #Sync
59781! 3 addresses covered
59782fmovd %f32, %f18
59783fmovs %f18, %f1
59784fmovs %f19, %f2
59785fmovd %f34, %f18
59786fmovs %f19, %f3
59787
59788P5641: !_MEMBAR (FP)
59789
59790P5642: !_ST [13] (maybe <- 0x4200009e) (FP)
59791sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
59792sub %i0, %i3, %i3
59793! preparing store val #0, next val will be in f20
59794fmovs %f16, %f20
59795fadds %f16, %f17, %f16
59796st %f20, [%i3 + 4 ]
59797
59798P5643: !_DWST [22] (maybe <- 0x4200009f) (FP)
59799! preparing store val #0, next val will be in f20
59800fmovs %f16, %f20
59801fadds %f16, %f17, %f16
59802! preparing store val #1, next val will be in f21
59803fmovs %f16, %f21
59804fadds %f16, %f17, %f16
59805std %f20, [%i2 + 0]
59806
59807P5644: !_DWST_BINIT [0] (maybe <- 0x2800101) (Int)
59808wr %g0, 0xe2, %asi
59809sllx %l4, 32, %l7
59810add %l4, 1, %l4
59811or %l7, %l4, %l7
59812stxa %l7, [%i0 + 0] %asi
59813add %l4, 1, %l4
59814
59815P5645: !_MEMBAR (Int)
59816membar #StoreLoad
59817
59818P5646: !_BLD [13] (FP)
59819wr %g0, 0xf0, %asi
59820ldda [%i3 + 0] %asi, %f32
59821membar #Sync
59822! 3 addresses covered
59823fmovd %f32, %f4
59824fmovd %f34, %f18
59825fmovs %f19, %f6
59826
59827P5647: !_MEMBAR (FP)
59828
59829P5648: !_DWST [20] (maybe <- 0x2800103) (Int)
59830sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
59831sub %i0, %i2, %i2
59832mov %l4, %l6
59833stx %l6, [%i2 + 8]
59834add %l4, 1, %l4
59835
59836P5649: !_CAS [11] (maybe <- 0x2800104) (Int)
59837sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
59838add %i0, %i3, %i3
59839add %i3, 12, %l6
59840lduw [%l6], %o5
59841mov %o5, %l3
59842! move %l3(lower) -> %o0(lower)
59843srlx %o0, 32, %o0
59844sllx %o0, 32, %o0
59845or %l3, %o0, %o0
59846mov %l4, %o1
59847cas [%l6], %l3, %o1
59848! move %o1(lower) -> %o1(upper)
59849sllx %o1, 32, %o1
59850add %l4, 1, %l4
59851
59852P5650: !_DWST_BINIT [17] (maybe <- 0x2800105) (Int)
59853wr %g0, 0xe2, %asi
59854sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
59855sub %i0, %i2, %i2
59856mov %l4, %l3
59857stxa %l3, [%i2 + 8] %asi
59858add %l4, 1, %l4
59859
59860P5651: !_MEMBAR (Int)
59861membar #StoreLoad
59862
59863P5652: !_ST [22] (maybe <- 0x2800106) (Int)
59864sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
59865add %i0, %i3, %i3
59866stw %l4, [%i3 + 4 ]
59867add %l4, 1, %l4
59868
59869P5653: !_ST_BINIT [18] (maybe <- 0x2800107) (Int)
59870wr %g0, 0xe2, %asi
59871sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
59872sub %i0, %i2, %i2
59873stwa %l4, [%i2 + 0] %asi
59874add %l4, 1, %l4
59875
59876P5654: !_MEMBAR (Int) (CBR)
59877membar #StoreLoad
59878
59879! cbranch
59880andcc %l0, 1, %g0
59881be,pt %xcc, TARGET5654
59882nop
59883RET5654:
59884
59885! lfsr step begin
59886srlx %l0, 1, %l7
59887xnor %l7, %l0, %l7
59888sllx %l7, 63, %l7
59889or %l7, %l0, %l0
59890srlx %l0, 1, %l0
59891
59892
59893P5655: !_REPLACEMENT [4] (Int) (CBR)
59894sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
59895sub %i0, %i3, %i3
59896sethi %hi(0x20000), %o5
59897ld [%i3+4], %l6
59898st %l6, [%i3+4]
59899add %i3, %o5, %l3
59900ld [%l3+4], %l6
59901st %l6, [%l3+4]
59902add %l3, %o5, %l3
59903ld [%l3+4], %l6
59904st %l6, [%l3+4]
59905add %l3, %o5, %l3
59906ld [%l3+4], %l6
59907st %l6, [%l3+4]
59908add %l3, %o5, %l3
59909ld [%l3+4], %l6
59910st %l6, [%l3+4]
59911add %l3, %o5, %l3
59912ld [%l3+4], %l6
59913st %l6, [%l3+4]
59914add %l3, %o5, %l3
59915ld [%l3+4], %l6
59916st %l6, [%l3+4]
59917add %l3, %o5, %l3
59918ld [%l3+4], %l6
59919st %l6, [%l3+4]
59920
59921! cbranch
59922andcc %l0, 1, %g0
59923be,pt %xcc, TARGET5655
59924nop
59925RET5655:
59926
59927! lfsr step begin
59928srlx %l0, 1, %l7
59929xnor %l7, %l0, %l7
59930sllx %l7, 63, %l7
59931or %l7, %l0, %l0
59932srlx %l0, 1, %l0
59933
59934
59935P5656: !_REPLACEMENT [18] (Int)
59936sethi %hi(0x20000), %o5
59937ld [%i3+0], %l6
59938st %l6, [%i3+0]
59939add %i3, %o5, %l3
59940ld [%l3+0], %l6
59941st %l6, [%l3+0]
59942add %l3, %o5, %l3
59943ld [%l3+0], %l6
59944st %l6, [%l3+0]
59945add %l3, %o5, %l3
59946ld [%l3+0], %l6
59947st %l6, [%l3+0]
59948add %l3, %o5, %l3
59949ld [%l3+0], %l6
59950st %l6, [%l3+0]
59951add %l3, %o5, %l3
59952ld [%l3+0], %l6
59953st %l6, [%l3+0]
59954add %l3, %o5, %l3
59955ld [%l3+0], %l6
59956st %l6, [%l3+0]
59957add %l3, %o5, %l3
59958ld [%l3+0], %l6
59959st %l6, [%l3+0]
59960
59961P5657: !_ST_BINIT [3] (maybe <- 0x2800108) (Int)
59962wr %g0, 0xe2, %asi
59963stwa %l4, [%i1 + 0] %asi
59964add %l4, 1, %l4
59965
59966P5658: !_MEMBAR (Int)
59967membar #StoreLoad
59968
59969P5659: !_BLD [5] (FP)
59970wr %g0, 0xf0, %asi
59971ldda [%i1 + 0] %asi, %f32
59972membar #Sync
59973! 3 addresses covered
59974fmovd %f32, %f18
59975fmovs %f18, %f7
59976fmovs %f19, %f8
59977fmovd %f34, %f18
59978fmovs %f19, %f9
59979
59980P5660: !_MEMBAR (FP) (CBR)
59981
59982! cbranch
59983andcc %l0, 1, %g0
59984be,pn %xcc, TARGET5660
59985nop
59986RET5660:
59987
59988! lfsr step begin
59989srlx %l0, 1, %l6
59990xnor %l6, %l0, %l6
59991sllx %l6, 63, %l6
59992or %l6, %l0, %l0
59993srlx %l0, 1, %l0
59994
59995
59996P5661: !_SWAP [11] (maybe <- 0x2800109) (Int)
59997sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
59998add %i0, %i2, %i2
59999mov %l4, %l3
60000swap [%i2 + 12], %l3
60001! move %l3(lower) -> %o1(lower)
60002srl %l3, 0, %l7
60003or %l7, %o1, %o1
60004add %l4, 1, %l4
60005
60006P5662: !_MEMBAR (FP)
60007membar #StoreLoad
60008
60009P5663: !_BLD [16] (FP)
60010wr %g0, 0xf0, %asi
60011sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
60012sub %i0, %i3, %i3
60013ldda [%i3 + 0] %asi, %f32
60014membar #Sync
60015! 3 addresses covered
60016fmovd %f32, %f10
60017fmovd %f34, %f18
60018fmovs %f19, %f12
60019
60020P5664: !_MEMBAR (FP)
60021
60022P5665: !_DWST [6] (maybe <- 0x280010a) (Int)
60023sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i2
60024sub %i0, %i2, %i2
60025sllx %l4, 32, %l6
60026add %l4, 1, %l4
60027or %l6, %l4, %l6
60028stx %l6, [%i2 + 0]
60029add %l4, 1, %l4
60030
60031P5666: !_LDD [0] (Int)
60032ldd [%i0 + 0], %l6
60033! move %l6(lower) -> %o2(upper)
60034sllx %l6, 32, %o2
60035! move %l7(lower) -> %o2(lower)
60036or %l7, %o2, %o2
60037
60038P5667: !_REPLACEMENT [9] (Int)
60039sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
60040sub %i0, %i3, %i3
60041sethi %hi(0x20000), %l3
60042ld [%i3+0], %l7
60043st %l7, [%i3+0]
60044add %i3, %l3, %l6
60045ld [%l6+0], %l7
60046st %l7, [%l6+0]
60047add %l6, %l3, %l6
60048ld [%l6+0], %l7
60049st %l7, [%l6+0]
60050add %l6, %l3, %l6
60051ld [%l6+0], %l7
60052st %l7, [%l6+0]
60053add %l6, %l3, %l6
60054ld [%l6+0], %l7
60055st %l7, [%l6+0]
60056add %l6, %l3, %l6
60057ld [%l6+0], %l7
60058st %l7, [%l6+0]
60059add %l6, %l3, %l6
60060ld [%l6+0], %l7
60061st %l7, [%l6+0]
60062add %l6, %l3, %l6
60063ld [%l6+0], %l7
60064st %l7, [%l6+0]
60065
60066P5668: !_LD [7] (FP)
60067ld [%i2 + 4], %f13
60068! 1 addresses covered
60069
60070P5669: !_MEMBAR (FP)
60071membar #StoreLoad
60072
60073P5670: !_BLD [9] (FP)
60074wr %g0, 0xf0, %asi
60075sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
60076add %i0, %i2, %i2
60077ldda [%i2 + 0] %asi, %f32
60078membar #Sync
60079! 3 addresses covered
60080fmovd %f32, %f14
60081!---- flushing fp results buffer to %f30 ----
60082fmovd %f0, %f30
60083fmovd %f2, %f30
60084fmovd %f4, %f30
60085fmovd %f6, %f30
60086fmovd %f8, %f30
60087fmovd %f10, %f30
60088fmovd %f12, %f30
60089fmovd %f14, %f30
60090!--
60091fmovd %f34, %f18
60092fmovs %f19, %f0
60093
60094P5671: !_MEMBAR (FP)
60095
60096P5672: !_DWST_BINIT [7] (maybe <- 0x280010c) (Int)
60097wr %g0, 0xe2, %asi
60098sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
60099sub %i0, %i3, %i3
60100sllx %l4, 32, %o5
60101add %l4, 1, %l4
60102or %o5, %l4, %o5
60103stxa %o5, [%i3 + 0] %asi
60104add %l4, 1, %l4
60105
60106P5673: !_MEMBAR (Int)
60107membar #StoreLoad
60108
60109P5674: !_DWST_BINIT [22] (maybe <- 0x280010e) (Int)
60110wr %g0, 0xe2, %asi
60111sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
60112add %i0, %i2, %i2
60113sllx %l4, 32, %l7
60114add %l4, 1, %l4
60115or %l7, %l4, %l7
60116stxa %l7, [%i2 + 0] %asi
60117add %l4, 1, %l4
60118
60119P5675: !_MEMBAR (Int)
60120membar #StoreLoad
60121
60122P5676: !_CASX [14] (maybe <- 0x2800110) (Int)
60123sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
60124sub %i0, %i3, %i3
60125add %i3, 8, %l7
60126ldx [%l7], %o3
60127! move %o3(upper) -> %o3(upper)
60128! move %o3(lower) -> %o3(lower)
60129mov %o3, %l6
60130mov %l4, %o4
60131casx [%l7], %l6, %o4
60132! move %o4(upper) -> %o4(upper)
60133! move %o4(lower) -> %o4(lower)
60134!---- flushing int results buffer----
60135mov %o0, %l5
60136mov %o1, %l5
60137mov %o2, %l5
60138mov %o3, %l5
60139mov %o4, %l5
60140add %l4, 1, %l4
60141
60142P5677: !_SWAP [21] (maybe <- 0x2800111) (Int)
60143mov %l4, %o0
60144swap [%i2 + 0], %o0
60145! move %o0(lower) -> %o0(upper)
60146sllx %o0, 32, %o0
60147add %l4, 1, %l4
60148
60149P5678: !_REPLACEMENT [19] (Int)
60150sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
60151sub %i0, %i2, %i2
60152sethi %hi(0x20000), %l3
60153ld [%i2+4], %l7
60154st %l7, [%i2+4]
60155add %i2, %l3, %l6
60156ld [%l6+4], %l7
60157st %l7, [%l6+4]
60158add %l6, %l3, %l6
60159ld [%l6+4], %l7
60160st %l7, [%l6+4]
60161add %l6, %l3, %l6
60162ld [%l6+4], %l7
60163st %l7, [%l6+4]
60164add %l6, %l3, %l6
60165ld [%l6+4], %l7
60166st %l7, [%l6+4]
60167add %l6, %l3, %l6
60168ld [%l6+4], %l7
60169st %l7, [%l6+4]
60170add %l6, %l3, %l6
60171ld [%l6+4], %l7
60172st %l7, [%l6+4]
60173add %l6, %l3, %l6
60174ld [%l6+4], %l7
60175st %l7, [%l6+4]
60176
60177P5679: !_LD [21] (Int) (LE)
60178wr %g0, 0x88, %asi
60179sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
60180add %i0, %i3, %i3
60181lduwa [%i3 + 0] %asi, %l3
60182! move %l3(lower) -> %o0(lower)
60183or %l3, %o0, %o0
60184
60185P5680: !_DWLD [19] (Int)
60186sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
60187sub %i0, %i2, %i2
60188ldx [%i2 + 0], %o1
60189! move %o1(upper) -> %o1(upper)
60190! move %o1(lower) -> %o1(lower)
60191
60192P5681: !_CASX [21] (maybe <- 0x2800112) (Int) (LE)
60193sllx %l4, 32, %l3
60194add %l4, 1, %l4
60195or %l4, %l3, %l3
60196! Change double-word-level endianess (big endian <-> little endian)
60197sethi %hi(0xff00ff00), %o5
60198or %o5, %lo(0xff00ff00), %o5
60199sllx %o5, 32, %l6
60200or %o5, %l6, %o5
60201and %l3, %o5, %l6
60202srlx %l6, 8, %l6
60203sllx %l3, 8, %l3
60204and %l3, %o5, %l3
60205or %l3, %l6, %l3
60206sethi %hi(0xffff0000), %o5
60207srlx %l3, 16, %l6
60208andn %l6, %o5, %l6
60209andn %l3, %o5, %l3
60210sllx %l3, 16, %l3
60211or %l3, %l6, %l3
60212srlx %l3, 32, %l6
60213sllx %l3, 32, %l3
60214or %l3, %l6, %l6
60215wr %g0, 0x88, %asi
60216ldxa [%i3] %asi, %l7
60217! move %l7(lower) -> %o2(upper)
60218sllx %l7, 32, %o2
60219! move %l7(upper) -> %o2(lower)
60220srlx %l7, 32, %o5
60221or %o5, %o2, %o2
60222mov %l7, %o5
60223mov %l6, %l7
60224casxa [%i3] %asi, %o5, %l7
60225! move %l7(lower) -> %o3(upper)
60226sllx %l7, 32, %o3
60227! move %l7(upper) -> %o3(lower)
60228srlx %l7, 32, %o5
60229or %o5, %o3, %o3
60230add %l4, 1, %l4
60231
60232P5682: !_CASX [3] (maybe <- 0x2800114) (Int)
60233ldx [%i1], %o4
60234! move %o4(upper) -> %o4(upper)
60235! move %o4(lower) -> %o4(lower)
60236!---- flushing int results buffer----
60237mov %o0, %l5
60238mov %o1, %l5
60239mov %o2, %l5
60240mov %o3, %l5
60241mov %o4, %l5
60242mov %o4, %o5
60243sllx %l4, 32, %o0
60244add %l4, 1, %l4
60245or %l4, %o0, %o0
60246casx [%i1], %o5, %o0
60247! move %o0(upper) -> %o0(upper)
60248! move %o0(lower) -> %o0(lower)
60249add %l4, 1, %l4
60250
60251P5683: !_ST_BINIT [21] (maybe <- 0x2800116) (Int)
60252wr %g0, 0xe2, %asi
60253stwa %l4, [%i3 + 0] %asi
60254add %l4, 1, %l4
60255
60256P5684: !_MEMBAR (Int)
60257membar #StoreLoad
60258
60259P5685: !_LD [12] (Int)
60260sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
60261sub %i0, %i3, %i3
60262lduw [%i3 + 0], %o1
60263! move %o1(lower) -> %o1(upper)
60264sllx %o1, 32, %o1
60265
60266P5686: !_MEMBAR (FP)
60267
60268P5687: !_BST [11] (maybe <- 0x420000a1) (FP)
60269wr %g0, 0xf0, %asi
60270sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
60271add %i0, %i2, %i2
60272! preparing store val #0, next val will be in f32
60273fmovs %f16, %f20
60274fadds %f16, %f17, %f16
60275! preparing store val #1, next val will be in f33
60276fmovs %f16, %f21
60277fadds %f16, %f17, %f16
60278! preparing store val #2, next val will be in f35
60279fmovd %f20, %f32
60280fmovs %f16, %f21
60281fadds %f16, %f17, %f16
60282fmovd %f20, %f34
60283membar #Sync
60284stda %f32, [%i2 + 0 ] %asi
60285
60286P5688: !_MEMBAR (FP)
60287membar #StoreLoad
60288
60289P5689: !_LD [13] (Int)
60290lduw [%i3 + 4], %l3
60291! move %l3(lower) -> %o1(lower)
60292or %l3, %o1, %o1
60293
60294P5690: !_DWST [15] (maybe <- 0x2800117) (Int)
60295sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
60296sub %i0, %i3, %i3
60297sllx %l4, 32, %l6
60298add %l4, 1, %l4
60299or %l6, %l4, %l6
60300stx %l6, [%i3 + 0]
60301add %l4, 1, %l4
60302
60303P5691: !_MEMBAR (FP)
60304membar #StoreLoad
60305
60306P5692: !_BLD [23] (FP)
60307wr %g0, 0xf0, %asi
60308sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
60309add %i0, %i2, %i2
60310ldda [%i2 + 0] %asi, %f32
60311membar #Sync
60312! 3 addresses covered
60313fmovd %f32, %f18
60314fmovs %f18, %f1
60315fmovs %f19, %f2
60316fmovd %f34, %f18
60317fmovs %f19, %f3
60318
60319P5693: !_MEMBAR (FP)
60320
60321P5694: !_BLD [17] (FP)
60322wr %g0, 0xf0, %asi
60323ldda [%i3 + 0] %asi, %f32
60324membar #Sync
60325! 3 addresses covered
60326fmovd %f32, %f4
60327fmovd %f34, %f18
60328fmovs %f19, %f6
60329
60330P5695: !_MEMBAR (FP)
60331
60332P5696: !_CAS [6] (maybe <- 0x2800119) (Int)
60333sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
60334sub %i0, %i3, %i3
60335lduw [%i3], %o2
60336mov %o2, %l3
60337! move %l3(lower) -> %o2(upper)
60338sllx %l3, 32, %o2
60339mov %l4, %o5
60340cas [%i3], %l3, %o5
60341! move %o5(lower) -> %o2(lower)
60342srl %o5, 0, %l3
60343or %l3, %o2, %o2
60344add %l4, 1, %l4
60345
60346P5697: !_CASX [5] (maybe <- 0x280011a) (Int)
60347add %i1, 8, %l6
60348ldx [%l6], %o3
60349! move %o3(upper) -> %o3(upper)
60350! move %o3(lower) -> %o3(lower)
60351mov %o3, %l3
60352mov %l4, %o4
60353casx [%l6], %l3, %o4
60354! move %o4(upper) -> %o4(upper)
60355! move %o4(lower) -> %o4(lower)
60356!---- flushing int results buffer----
60357mov %o0, %l5
60358mov %o1, %l5
60359mov %o2, %l5
60360mov %o3, %l5
60361mov %o4, %l5
60362add %l4, 1, %l4
60363
60364P5698: !_MEMBAR (FP)
60365
60366P5699: !_BSTC [18] (maybe <- 0x420000a4) (FP)
60367wr %g0, 0xe0, %asi
60368sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
60369sub %i0, %i2, %i2
60370! preparing store val #0, next val will be in f32
60371fmovs %f16, %f20
60372fadds %f16, %f17, %f16
60373! preparing store val #1, next val will be in f33
60374fmovs %f16, %f21
60375fadds %f16, %f17, %f16
60376! preparing store val #2, next val will be in f35
60377fmovd %f20, %f32
60378fmovs %f16, %f21
60379fadds %f16, %f17, %f16
60380fmovd %f20, %f34
60381membar #Sync
60382stda %f32, [%i2 + 0 ] %asi
60383
60384P5700: !_MEMBAR (FP)
60385membar #StoreLoad
60386
60387P5701: !_LDD [16] (Int) (Branch target of P5367)
60388sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
60389sub %i0, %i3, %i3
60390ldd [%i3 + 0], %l6
60391! move %l6(lower) -> %o0(upper)
60392sllx %l6, 32, %o0
60393! move %l7(lower) -> %o0(lower)
60394or %l7, %o0, %o0
60395ba P5702
60396nop
60397
60398TARGET5367:
60399ba RET5367
60400nop
60401
60402
60403P5702: !_MEMBAR (FP)
60404
60405P5703: !_BST [14] (maybe <- 0x420000a7) (FP)
60406wr %g0, 0xf0, %asi
60407sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
60408sub %i0, %i2, %i2
60409! preparing store val #0, next val will be in f32
60410fmovs %f16, %f20
60411fadds %f16, %f17, %f16
60412! preparing store val #1, next val will be in f33
60413fmovs %f16, %f21
60414fadds %f16, %f17, %f16
60415! preparing store val #2, next val will be in f35
60416fmovd %f20, %f32
60417fmovs %f16, %f21
60418fadds %f16, %f17, %f16
60419fmovd %f20, %f34
60420membar #Sync
60421stda %f32, [%i2 + 0 ] %asi
60422
60423P5704: !_MEMBAR (FP)
60424membar #StoreLoad
60425
60426P5705: !_DWST_BINIT [8] (maybe <- 0x280011b) (Int)
60427wr %g0, 0xe2, %asi
60428sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
60429sub %i0, %i3, %i3
60430mov %l4, %o5
60431stxa %o5, [%i3 + 8] %asi
60432add %l4, 1, %l4
60433
60434P5706: !_MEMBAR (Int) (Branch target of P5982)
60435membar #StoreLoad
60436ba P5707
60437nop
60438
60439TARGET5982:
60440ba RET5982
60441nop
60442
60443
60444P5707: !_CAS [23] (maybe <- 0x280011c) (Int)
60445sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
60446add %i0, %i2, %i2
60447add %i2, 12, %o5
60448lduw [%o5], %o1
60449mov %o1, %l7
60450! move %l7(lower) -> %o1(upper)
60451sllx %l7, 32, %o1
60452mov %l4, %l6
60453cas [%o5], %l7, %l6
60454! move %l6(lower) -> %o1(lower)
60455srl %l6, 0, %l7
60456or %l7, %o1, %o1
60457add %l4, 1, %l4
60458
60459P5708: !_MEMBAR (FP)
60460membar #StoreLoad
60461
60462P5709: !_BLD [1] (FP)
60463wr %g0, 0xf0, %asi
60464ldda [%i0 + 0] %asi, %f32
60465membar #Sync
60466! 3 addresses covered
60467fmovd %f32, %f18
60468fmovs %f18, %f7
60469fmovs %f19, %f8
60470fmovd %f34, %f18
60471fmovs %f19, %f9
60472
60473P5710: !_MEMBAR (FP)
60474
60475P5711: !_BST [2] (maybe <- 0x420000aa) (FP)
60476wr %g0, 0xf0, %asi
60477! preparing store val #0, next val will be in f32
60478fmovs %f16, %f20
60479fadds %f16, %f17, %f16
60480! preparing store val #1, next val will be in f33
60481fmovs %f16, %f21
60482fadds %f16, %f17, %f16
60483! preparing store val #2, next val will be in f35
60484fmovd %f20, %f32
60485fmovs %f16, %f21
60486fadds %f16, %f17, %f16
60487fmovd %f20, %f34
60488membar #Sync
60489stda %f32, [%i0 + 0 ] %asi
60490
60491P5712: !_MEMBAR (FP)
60492membar #StoreLoad
60493
60494P5713: !_CASX [16] (maybe <- 0x280011d) (Int)
60495sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
60496sub %i0, %i3, %i3
60497ldx [%i3], %o2
60498! move %o2(upper) -> %o2(upper)
60499! move %o2(lower) -> %o2(lower)
60500mov %o2, %l6
60501sllx %l4, 32, %o3
60502add %l4, 1, %l4
60503or %l4, %o3, %o3
60504casx [%i3], %l6, %o3
60505! move %o3(upper) -> %o3(upper)
60506! move %o3(lower) -> %o3(lower)
60507add %l4, 1, %l4
60508
60509P5714: !_CAS [20] (maybe <- 0x280011f) (Int) (Branch target of P5103)
60510sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
60511sub %i0, %i2, %i2
60512add %i2, 12, %l7
60513lduw [%l7], %o4
60514mov %o4, %l6
60515! move %l6(lower) -> %o4(upper)
60516sllx %l6, 32, %o4
60517mov %l4, %l3
60518cas [%l7], %l6, %l3
60519! move %l3(lower) -> %o4(lower)
60520srl %l3, 0, %l6
60521or %l6, %o4, %o4
60522!---- flushing int results buffer----
60523mov %o0, %l5
60524mov %o1, %l5
60525mov %o2, %l5
60526mov %o3, %l5
60527mov %o4, %l5
60528add %l4, 1, %l4
60529ba P5715
60530nop
60531
60532TARGET5103:
60533ba RET5103
60534nop
60535
60536
60537P5715: !_LD [4] (Int)
60538lduw [%i1 + 4], %o0
60539! move %o0(lower) -> %o0(upper)
60540sllx %o0, 32, %o0
60541
60542P5716: !_SWAP [7] (maybe <- 0x2800120) (Int)
60543sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS3_O), %i3
60544sub %i0, %i3, %i3
60545mov %l4, %l6
60546swap [%i3 + 4], %l6
60547! move %l6(lower) -> %o0(lower)
60548srl %l6, 0, %o5
60549or %o5, %o0, %o0
60550add %l4, 1, %l4
60551
60552P5717: !_PREFETCH [8] (Int)
60553sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
60554add %i0, %i2, %i2
60555prefetch [%i2 + 12], 3
60556
60557P5718: !_MEMBAR (FP)
60558
60559P5719: !_BST [11] (maybe <- 0x420000ad) (FP)
60560wr %g0, 0xf0, %asi
60561sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
60562add %i0, %i3, %i3
60563! preparing store val #0, next val will be in f32
60564fmovs %f16, %f20
60565fadds %f16, %f17, %f16
60566! preparing store val #1, next val will be in f33
60567fmovs %f16, %f21
60568fadds %f16, %f17, %f16
60569! preparing store val #2, next val will be in f35
60570fmovd %f20, %f32
60571fmovs %f16, %f21
60572fadds %f16, %f17, %f16
60573fmovd %f20, %f34
60574membar #Sync
60575stda %f32, [%i3 + 0 ] %asi
60576
60577P5720: !_MEMBAR (FP)
60578membar #StoreLoad
60579
60580P5721: !_LDD [2] (Int) (CBR)
60581ldd [%i0 + 8], %l6
60582! move %l7(lower) -> %o1(upper)
60583sllx %l7, 32, %o1
60584
60585! cbranch
60586andcc %l0, 1, %g0
60587be,pt %xcc, TARGET5721
60588nop
60589RET5721:
60590
60591! lfsr step begin
60592srlx %l0, 1, %l3
60593xnor %l3, %l0, %l3
60594sllx %l3, 63, %l3
60595or %l3, %l0, %l0
60596srlx %l0, 1, %l0
60597
60598
60599P5722: !_ST [9] (maybe <- 0x2800121) (Int)
60600stw %l4, [%i3 + 0 ]
60601add %l4, 1, %l4
60602
60603P5723: !_REPLACEMENT [2] (Int)
60604sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
60605sub %i0, %i2, %i2
60606sethi %hi(0x20000), %l3
60607ld [%i2+12], %l7
60608st %l7, [%i2+12]
60609add %i2, %l3, %l6
60610ld [%l6+12], %l7
60611st %l7, [%l6+12]
60612add %l6, %l3, %l6
60613ld [%l6+12], %l7
60614st %l7, [%l6+12]
60615add %l6, %l3, %l6
60616ld [%l6+12], %l7
60617st %l7, [%l6+12]
60618add %l6, %l3, %l6
60619ld [%l6+12], %l7
60620st %l7, [%l6+12]
60621add %l6, %l3, %l6
60622ld [%l6+12], %l7
60623st %l7, [%l6+12]
60624add %l6, %l3, %l6
60625ld [%l6+12], %l7
60626st %l7, [%l6+12]
60627add %l6, %l3, %l6
60628ld [%l6+12], %l7
60629st %l7, [%l6+12]
60630
60631P5724: !_DWST [16] (maybe <- 0x2800122) (Int)
60632sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
60633sub %i0, %i3, %i3
60634sllx %l4, 32, %o5
60635add %l4, 1, %l4
60636or %o5, %l4, %o5
60637stx %o5, [%i3 + 0]
60638add %l4, 1, %l4
60639
60640P5725: !_CASX [5] (maybe <- 0x2800124) (Int)
60641add %i1, 8, %o5
60642ldx [%o5], %l6
60643! move %l6(upper) -> %o1(lower)
60644srlx %l6, 32, %l7
60645or %l7, %o1, %o1
60646! move %l6(lower) -> %o2(upper)
60647sllx %l6, 32, %o2
60648mov %l6, %l7
60649mov %l4, %l6
60650casx [%o5], %l7, %l6
60651! move %l6(upper) -> %o2(lower)
60652srlx %l6, 32, %l7
60653or %l7, %o2, %o2
60654! move %l6(lower) -> %o3(upper)
60655sllx %l6, 32, %o3
60656add %l4, 1, %l4
60657
60658P5726: !_ST_BINIT [12] (maybe <- 0x2800125) (Int)
60659wr %g0, 0xe2, %asi
60660sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
60661sub %i0, %i2, %i2
60662stwa %l4, [%i2 + 0] %asi
60663add %l4, 1, %l4
60664
60665P5727: !_MEMBAR (Int)
60666membar #StoreLoad
60667
60668P5728: !_DWLD [7] (Int) (CBR)
60669sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
60670add %i0, %i3, %i3
60671ldx [%i3 + 0], %l7
60672! move %l7(upper) -> %o3(lower)
60673srlx %l7, 32, %l6
60674or %l6, %o3, %o3
60675! move %l7(lower) -> %o4(upper)
60676sllx %l7, 32, %o4
60677
60678! cbranch
60679andcc %l0, 1, %g0
60680be,pt %xcc, TARGET5728
60681nop
60682RET5728:
60683
60684! lfsr step begin
60685srlx %l0, 1, %o5
60686xnor %o5, %l0, %o5
60687sllx %o5, 63, %o5
60688or %o5, %l0, %l0
60689srlx %l0, 1, %l0
60690
60691
60692P5729: !_DWST_BINIT [5] (maybe <- 0x2800126) (Int) (CBR)
60693wr %g0, 0xe2, %asi
60694mov %l4, %l3
60695stxa %l3, [%i1 + 8] %asi
60696add %l4, 1, %l4
60697
60698! cbranch
60699andcc %l0, 1, %g0
60700be,pn %xcc, TARGET5729
60701nop
60702RET5729:
60703
60704! lfsr step begin
60705srlx %l0, 1, %o5
60706xnor %o5, %l0, %o5
60707sllx %o5, 63, %o5
60708or %o5, %l0, %l0
60709srlx %l0, 1, %l0
60710
60711
60712P5730: !_MEMBAR (Int)
60713membar #StoreLoad
60714
60715P5731: !_PREFETCH [1] (Int)
60716prefetch [%i0 + 4], 21
60717
60718P5732: !_REPLACEMENT [9] (Int)
60719sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
60720sub %i0, %i2, %i2
60721sethi %hi(0x20000), %l3
60722ld [%i2+0], %l7
60723st %l7, [%i2+0]
60724add %i2, %l3, %l6
60725ld [%l6+0], %l7
60726st %l7, [%l6+0]
60727add %l6, %l3, %l6
60728ld [%l6+0], %l7
60729st %l7, [%l6+0]
60730add %l6, %l3, %l6
60731ld [%l6+0], %l7
60732st %l7, [%l6+0]
60733add %l6, %l3, %l6
60734ld [%l6+0], %l7
60735st %l7, [%l6+0]
60736add %l6, %l3, %l6
60737ld [%l6+0], %l7
60738st %l7, [%l6+0]
60739add %l6, %l3, %l6
60740ld [%l6+0], %l7
60741st %l7, [%l6+0]
60742add %l6, %l3, %l6
60743ld [%l6+0], %l7
60744st %l7, [%l6+0]
60745
60746P5733: !_ST [15] (maybe <- 0x2800127) (Int)
60747sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
60748sub %i0, %i3, %i3
60749stw %l4, [%i3 + 0 ]
60750add %l4, 1, %l4
60751
60752P5734: !_MEMBAR (FP)
60753
60754P5735: !_BST [3] (maybe <- 0x420000b0) (FP)
60755wr %g0, 0xf0, %asi
60756! preparing store val #0, next val will be in f32
60757fmovs %f16, %f20
60758fadds %f16, %f17, %f16
60759! preparing store val #1, next val will be in f33
60760fmovs %f16, %f21
60761fadds %f16, %f17, %f16
60762! preparing store val #2, next val will be in f35
60763fmovd %f20, %f32
60764fmovs %f16, %f21
60765fadds %f16, %f17, %f16
60766fmovd %f20, %f34
60767membar #Sync
60768stda %f32, [%i1 + 0 ] %asi
60769
60770P5736: !_MEMBAR (FP)
60771membar #StoreLoad
60772
60773P5737: !_CAS [0] (maybe <- 0x2800128) (Int)
60774lduw [%i0], %l3
60775mov %l3, %l6
60776! move %l6(lower) -> %o4(lower)
60777or %l6, %o4, %o4
60778!---- flushing int results buffer----
60779mov %o0, %l5
60780mov %o1, %l5
60781mov %o2, %l5
60782mov %o3, %l5
60783mov %o4, %l5
60784mov %l4, %o0
60785cas [%i0], %l6, %o0
60786! move %o0(lower) -> %o0(upper)
60787sllx %o0, 32, %o0
60788add %l4, 1, %l4
60789
60790P5738: !_ST_BINIT [16] (maybe <- 0x2800129) (Int)
60791wr %g0, 0xe2, %asi
60792stwa %l4, [%i3 + 4] %asi
60793add %l4, 1, %l4
60794
60795P5739: !_MEMBAR (Int)
60796membar #StoreLoad
60797
60798P5740: !_BLD [16] (FP)
60799wr %g0, 0xf0, %asi
60800ldda [%i3 + 0] %asi, %f32
60801membar #Sync
60802! 3 addresses covered
60803fmovd %f32, %f10
60804fmovd %f34, %f18
60805fmovs %f19, %f12
60806
60807P5741: !_MEMBAR (FP)
60808
60809P5742: !_ST [9] (maybe <- 0x280012a) (Int)
60810sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
60811add %i0, %i2, %i2
60812stw %l4, [%i2 + 0 ]
60813add %l4, 1, %l4
60814
60815P5743: !_CAS [14] (maybe <- 0x280012b) (Int)
60816sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
60817sub %i0, %i3, %i3
60818add %i3, 12, %l3
60819lduw [%l3], %l7
60820mov %l7, %o5
60821! move %o5(lower) -> %o0(lower)
60822or %o5, %o0, %o0
60823mov %l4, %o1
60824cas [%l3], %o5, %o1
60825! move %o1(lower) -> %o1(upper)
60826sllx %o1, 32, %o1
60827add %l4, 1, %l4
60828
60829P5744: !_CAS [11] (maybe <- 0x280012c) (Int)
60830add %i2, 12, %l3
60831lduw [%l3], %l7
60832mov %l7, %o5
60833! move %o5(lower) -> %o1(lower)
60834or %o5, %o1, %o1
60835mov %l4, %o2
60836cas [%l3], %o5, %o2
60837! move %o2(lower) -> %o2(upper)
60838sllx %o2, 32, %o2
60839add %l4, 1, %l4
60840
60841P5745: !_CASX [2] (maybe <- 0x280012d) (Int)
60842add %i0, 8, %l3
60843ldx [%l3], %l7
60844! move %l7(upper) -> %o2(lower)
60845srlx %l7, 32, %o5
60846or %o5, %o2, %o2
60847! move %l7(lower) -> %o3(upper)
60848sllx %l7, 32, %o3
60849mov %l7, %o5
60850mov %l4, %l7
60851casx [%l3], %o5, %l7
60852! move %l7(upper) -> %o3(lower)
60853srlx %l7, 32, %o5
60854or %o5, %o3, %o3
60855! move %l7(lower) -> %o4(upper)
60856sllx %l7, 32, %o4
60857add %l4, 1, %l4
60858
60859P5746: !_ST [18] (maybe <- 0x280012e) (Int)
60860sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
60861sub %i0, %i2, %i2
60862stw %l4, [%i2 + 0 ]
60863add %l4, 1, %l4
60864
60865P5747: !_PREFETCH [1] (Int)
60866prefetch [%i0 + 4], 28
60867
60868P5748: !_MEMBAR (FP)
60869
60870P5749: !_BSTC [0] (maybe <- 0x420000b3) (FP)
60871wr %g0, 0xe0, %asi
60872! preparing store val #0, next val will be in f32
60873fmovs %f16, %f20
60874fadds %f16, %f17, %f16
60875! preparing store val #1, next val will be in f33
60876fmovs %f16, %f21
60877fadds %f16, %f17, %f16
60878! preparing store val #2, next val will be in f35
60879fmovd %f20, %f32
60880fmovs %f16, %f21
60881fadds %f16, %f17, %f16
60882fmovd %f20, %f34
60883membar #Sync
60884stda %f32, [%i0 + 0 ] %asi
60885
60886P5750: !_MEMBAR (FP)
60887membar #StoreLoad
60888
60889P5751: !_DWLD [2] (Int)
60890ldx [%i0 + 8], %l7
60891! move %l7(lower) -> %o4(lower)
60892srl %l7, 0, %l6
60893or %l6, %o4, %o4
60894!---- flushing int results buffer----
60895mov %o0, %l5
60896mov %o1, %l5
60897mov %o2, %l5
60898mov %o3, %l5
60899mov %o4, %l5
60900
60901P5752: !_MEMBAR (FP)
60902
60903P5753: !_BSTC [21] (maybe <- 0x420000b6) (FP)
60904wr %g0, 0xe0, %asi
60905sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
60906add %i0, %i3, %i3
60907! preparing store val #0, next val will be in f32
60908fmovs %f16, %f20
60909fadds %f16, %f17, %f16
60910! preparing store val #1, next val will be in f33
60911fmovs %f16, %f21
60912fadds %f16, %f17, %f16
60913! preparing store val #2, next val will be in f35
60914fmovd %f20, %f32
60915fmovs %f16, %f21
60916fadds %f16, %f17, %f16
60917fmovd %f20, %f34
60918membar #Sync
60919stda %f32, [%i3 + 0 ] %asi
60920
60921P5754: !_MEMBAR (FP)
60922membar #StoreLoad
60923
60924P5755: !_CASX [23] (maybe <- 0x280012f) (Int)
60925add %i3, 8, %o5
60926ldx [%o5], %o0
60927! move %o0(upper) -> %o0(upper)
60928! move %o0(lower) -> %o0(lower)
60929mov %o0, %l7
60930mov %l4, %o1
60931casx [%o5], %l7, %o1
60932! move %o1(upper) -> %o1(upper)
60933! move %o1(lower) -> %o1(lower)
60934add %l4, 1, %l4
60935
60936P5756: !_CASX [16] (maybe <- 0x2800130) (Int)
60937sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
60938sub %i0, %i2, %i2
60939ldx [%i2], %o2
60940! move %o2(upper) -> %o2(upper)
60941! move %o2(lower) -> %o2(lower)
60942mov %o2, %l7
60943sllx %l4, 32, %o3
60944add %l4, 1, %l4
60945or %l4, %o3, %o3
60946casx [%i2], %l7, %o3
60947! move %o3(upper) -> %o3(upper)
60948! move %o3(lower) -> %o3(lower)
60949add %l4, 1, %l4
60950
60951P5757: !_ST_BINIT [22] (maybe <- 0x2800132) (Int)
60952wr %g0, 0xe2, %asi
60953stwa %l4, [%i3 + 4] %asi
60954add %l4, 1, %l4
60955
60956P5758: !_MEMBAR (Int)
60957membar #StoreLoad
60958
60959P5759: !_CASX [7] (maybe <- 0x2800133) (Int)
60960sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
60961add %i0, %i3, %i3
60962ldx [%i3], %o4
60963! move %o4(upper) -> %o4(upper)
60964! move %o4(lower) -> %o4(lower)
60965!---- flushing int results buffer----
60966mov %o0, %l5
60967mov %o1, %l5
60968mov %o2, %l5
60969mov %o3, %l5
60970mov %o4, %l5
60971mov %o4, %l6
60972sllx %l4, 32, %o0
60973add %l4, 1, %l4
60974or %l4, %o0, %o0
60975casx [%i3], %l6, %o0
60976! move %o0(upper) -> %o0(upper)
60977! move %o0(lower) -> %o0(lower)
60978add %l4, 1, %l4
60979
60980P5760: !_DWLD [9] (Int)
60981sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
60982add %i0, %i2, %i2
60983ldx [%i2 + 0], %o1
60984! move %o1(upper) -> %o1(upper)
60985! move %o1(lower) -> %o1(lower)
60986
60987P5761: !_DWLD [1] (Int)
60988ldx [%i0 + 0], %o2
60989! move %o2(upper) -> %o2(upper)
60990! move %o2(lower) -> %o2(lower)
60991
60992P5762: !_LD [13] (Int)
60993sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
60994sub %i0, %i3, %i3
60995lduw [%i3 + 4], %o3
60996! move %o3(lower) -> %o3(upper)
60997sllx %o3, 32, %o3
60998
60999P5763: !_MEMBAR (FP) (Branch target of P5891)
61000ba P5764
61001nop
61002
61003TARGET5891:
61004ba RET5891
61005nop
61006
61007
61008P5764: !_BST [6] (maybe <- 0x420000b9) (FP)
61009wr %g0, 0xf0, %asi
61010sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
61011add %i0, %i2, %i2
61012! preparing store val #0, next val will be in f32
61013fmovs %f16, %f20
61014fadds %f16, %f17, %f16
61015! preparing store val #1, next val will be in f33
61016fmovs %f16, %f21
61017fadds %f16, %f17, %f16
61018! preparing store val #2, next val will be in f35
61019fmovd %f20, %f32
61020fmovs %f16, %f21
61021fadds %f16, %f17, %f16
61022fmovd %f20, %f34
61023membar #Sync
61024stda %f32, [%i2 + 0 ] %asi
61025
61026P5765: !_MEMBAR (FP)
61027membar #StoreLoad
61028
61029P5766: !_BLD [5] (FP)
61030wr %g0, 0xf0, %asi
61031ldda [%i1 + 0] %asi, %f32
61032membar #Sync
61033! 3 addresses covered
61034fmovd %f32, %f18
61035fmovs %f18, %f13
61036fmovs %f19, %f14
61037fmovd %f34, %f18
61038fmovs %f19, %f15
61039!---- flushing fp results buffer to %f30 ----
61040fmovd %f0, %f30
61041fmovd %f2, %f30
61042fmovd %f4, %f30
61043fmovd %f6, %f30
61044fmovd %f8, %f30
61045fmovd %f10, %f30
61046fmovd %f12, %f30
61047fmovd %f14, %f30
61048!--
61049
61050P5767: !_MEMBAR (FP)
61051
61052P5768: !_LD [20] (Int)
61053sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
61054sub %i0, %i3, %i3
61055lduw [%i3 + 12], %o5
61056! move %o5(lower) -> %o3(lower)
61057or %o5, %o3, %o3
61058
61059P5769: !_DWST_BINIT [19] (maybe <- 0x2800135) (Int)
61060wr %g0, 0xe2, %asi
61061sllx %l4, 32, %l3
61062add %l4, 1, %l4
61063or %l3, %l4, %l3
61064stxa %l3, [%i3 + 0] %asi
61065add %l4, 1, %l4
61066
61067P5770: !_MEMBAR (Int)
61068membar #StoreLoad
61069
61070P5771: !_SWAP [16] (maybe <- 0x2800137) (Int)
61071sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
61072sub %i0, %i2, %i2
61073mov %l4, %o4
61074swap [%i2 + 4], %o4
61075! move %o4(lower) -> %o4(upper)
61076sllx %o4, 32, %o4
61077add %l4, 1, %l4
61078
61079P5772: !_SWAP [22] (maybe <- 0x2800138) (Int)
61080sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
61081add %i0, %i3, %i3
61082mov %l4, %l3
61083swap [%i3 + 4], %l3
61084! move %l3(lower) -> %o4(lower)
61085srl %l3, 0, %l7
61086or %l7, %o4, %o4
61087!---- flushing int results buffer----
61088mov %o0, %l5
61089mov %o1, %l5
61090mov %o2, %l5
61091mov %o3, %l5
61092mov %o4, %l5
61093add %l4, 1, %l4
61094
61095P5773: !_ST [16] (maybe <- 0x2800139) (Int)
61096stw %l4, [%i2 + 4 ]
61097add %l4, 1, %l4
61098
61099P5774: !_DWST_BINIT [19] (maybe <- 0x280013a) (Int)
61100wr %g0, 0xe2, %asi
61101sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
61102sub %i0, %i2, %i2
61103sllx %l4, 32, %l3
61104add %l4, 1, %l4
61105or %l3, %l4, %l3
61106stxa %l3, [%i2 + 0] %asi
61107add %l4, 1, %l4
61108
61109P5775: !_MEMBAR (Int)
61110membar #StoreLoad
61111
61112P5776: !_LDD [16] (Int)
61113sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
61114sub %i0, %i3, %i3
61115ldd [%i3 + 0], %l6
61116! move %l6(lower) -> %o0(upper)
61117sllx %l6, 32, %o0
61118! move %l7(lower) -> %o0(lower)
61119or %l7, %o0, %o0
61120
61121P5777: !_DWST [2] (maybe <- 0x420000bc) (FP)
61122! preparing store val #0, next val will be in f21
61123fmovs %f16, %f21
61124fadds %f16, %f17, %f16
61125std %f20, [%i0 + 8]
61126
61127P5778: !_DWST_BINIT [4] (maybe <- 0x280013c) (Int)
61128wr %g0, 0xe2, %asi
61129sllx %l4, 32, %o5
61130add %l4, 1, %l4
61131or %o5, %l4, %o5
61132stxa %o5, [%i1 + 0] %asi
61133add %l4, 1, %l4
61134
61135P5779: !_MEMBAR (Int)
61136membar #StoreLoad
61137
61138P5780: !_LDD [6] (Int)
61139sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
61140add %i0, %i2, %i2
61141ldd [%i2 + 0], %l6
61142! move %l6(lower) -> %o1(upper)
61143sllx %l6, 32, %o1
61144! move %l7(lower) -> %o1(lower)
61145or %l7, %o1, %o1
61146
61147P5781: !_LD [2] (Int)
61148lduw [%i0 + 12], %o2
61149! move %o2(lower) -> %o2(upper)
61150sllx %o2, 32, %o2
61151
61152P5782: !_ST [0] (maybe <- 0x280013e) (Int) (LE)
61153wr %g0, 0x88, %asi
61154! Change single-word-level endianess (big endian <-> little endian)
61155sethi %hi(0xff00ff00), %l3
61156or %l3, %lo(0xff00ff00), %l3
61157and %l4, %l3, %l6
61158srl %l6, 8, %l6
61159sll %l4, 8, %o5
61160and %o5, %l3, %o5
61161or %o5, %l6, %o5
61162srl %o5, 16, %l6
61163sll %o5, 16, %o5
61164srl %o5, 0, %o5
61165or %o5, %l6, %o5
61166stwa %o5, [%i0 + 0] %asi
61167add %l4, 1, %l4
61168
61169P5783: !_MEMBAR (FP)
61170
61171P5784: !_BSTC [23] (maybe <- 0x420000bd) (FP)
61172wr %g0, 0xe0, %asi
61173sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
61174add %i0, %i3, %i3
61175! preparing store val #0, next val will be in f32
61176fmovs %f16, %f20
61177fadds %f16, %f17, %f16
61178! preparing store val #1, next val will be in f33
61179fmovs %f16, %f21
61180fadds %f16, %f17, %f16
61181! preparing store val #2, next val will be in f35
61182fmovd %f20, %f32
61183fmovs %f16, %f21
61184fadds %f16, %f17, %f16
61185fmovd %f20, %f34
61186membar #Sync
61187stda %f32, [%i3 + 0 ] %asi
61188
61189P5785: !_MEMBAR (FP)
61190membar #StoreLoad
61191
61192P5786: !_ST_BINIT [2] (maybe <- 0x280013f) (Int)
61193wr %g0, 0xe2, %asi
61194stwa %l4, [%i0 + 12] %asi
61195add %l4, 1, %l4
61196
61197P5787: !_MEMBAR (Int)
61198membar #StoreLoad
61199
61200P5788: !_CAS [14] (maybe <- 0x2800140) (Int)
61201sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
61202sub %i0, %i2, %i2
61203add %i2, 12, %l6
61204lduw [%l6], %o5
61205mov %o5, %l3
61206! move %l3(lower) -> %o2(lower)
61207or %l3, %o2, %o2
61208mov %l4, %o3
61209cas [%l6], %l3, %o3
61210! move %o3(lower) -> %o3(upper)
61211sllx %o3, 32, %o3
61212add %l4, 1, %l4
61213
61214P5789: !_MEMBAR (FP)
61215membar #StoreLoad
61216
61217P5790: !_BLD [15] (FP)
61218wr %g0, 0xf0, %asi
61219sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
61220sub %i0, %i3, %i3
61221ldda [%i3 + 0] %asi, %f0
61222membar #Sync
61223! 3 addresses covered
61224fmovs %f3, %f2
61225
61226P5791: !_MEMBAR (FP)
61227
61228P5792: !_DWST [3] (maybe <- 0x2800141) (Int)
61229sllx %l4, 32, %l3
61230add %l4, 1, %l4
61231or %l3, %l4, %l3
61232stx %l3, [%i1 + 0]
61233add %l4, 1, %l4
61234
61235P5793: !_MEMBAR (FP)
61236
61237P5794: !_BSTC [1] (maybe <- 0x420000c0) (FP)
61238wr %g0, 0xe0, %asi
61239! preparing store val #0, next val will be in f32
61240fmovs %f16, %f20
61241fadds %f16, %f17, %f16
61242! preparing store val #1, next val will be in f33
61243fmovs %f16, %f21
61244fadds %f16, %f17, %f16
61245! preparing store val #2, next val will be in f35
61246fmovd %f20, %f32
61247fmovs %f16, %f21
61248fadds %f16, %f17, %f16
61249fmovd %f20, %f34
61250membar #Sync
61251stda %f32, [%i0 + 0 ] %asi
61252
61253P5795: !_MEMBAR (FP) (CBR)
61254membar #StoreLoad
61255
61256! cbranch
61257andcc %l0, 1, %g0
61258be,pn %xcc, TARGET5795
61259nop
61260RET5795:
61261
61262! lfsr step begin
61263srlx %l0, 1, %l7
61264xnor %l7, %l0, %l7
61265sllx %l7, 63, %l7
61266or %l7, %l0, %l0
61267srlx %l0, 1, %l0
61268
61269
61270P5796: !_CASX [11] (maybe <- 0x2800143) (Int)
61271sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
61272add %i0, %i2, %i2
61273add %i2, 8, %l3
61274ldx [%l3], %l7
61275! move %l7(upper) -> %o3(lower)
61276srlx %l7, 32, %o5
61277or %o5, %o3, %o3
61278! move %l7(lower) -> %o4(upper)
61279sllx %l7, 32, %o4
61280mov %l7, %o5
61281mov %l4, %l7
61282casx [%l3], %o5, %l7
61283! move %l7(upper) -> %o4(lower)
61284srlx %l7, 32, %o5
61285or %o5, %o4, %o4
61286!---- flushing int results buffer----
61287mov %o0, %l5
61288mov %o1, %l5
61289mov %o2, %l5
61290mov %o3, %l5
61291mov %o4, %l5
61292! move %l7(lower) -> %o0(upper)
61293sllx %l7, 32, %o0
61294add %l4, 1, %l4
61295
61296P5797: !_SWAP [15] (maybe <- 0x2800144) (Int)
61297mov %l4, %l6
61298swap [%i3 + 0], %l6
61299! move %l6(lower) -> %o0(lower)
61300srl %l6, 0, %o5
61301or %o5, %o0, %o0
61302add %l4, 1, %l4
61303
61304P5798: !_ST_BINIT [22] (maybe <- 0x2800145) (Int)
61305wr %g0, 0xe2, %asi
61306sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
61307add %i0, %i3, %i3
61308stwa %l4, [%i3 + 4] %asi
61309add %l4, 1, %l4
61310
61311P5799: !_MEMBAR (Int)
61312membar #StoreLoad
61313
61314P5800: !_CAS [7] (maybe <- 0x2800146) (Int)
61315sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
61316add %i0, %i2, %i2
61317add %i2, 4, %l7
61318lduw [%l7], %o1
61319mov %o1, %l6
61320! move %l6(lower) -> %o1(upper)
61321sllx %l6, 32, %o1
61322mov %l4, %l3
61323cas [%l7], %l6, %l3
61324! move %l3(lower) -> %o1(lower)
61325srl %l3, 0, %l6
61326or %l6, %o1, %o1
61327add %l4, 1, %l4
61328
61329P5801: !_DWST_BINIT [1] (maybe <- 0x2800147) (Int)
61330wr %g0, 0xe2, %asi
61331sllx %l4, 32, %l6
61332add %l4, 1, %l4
61333or %l6, %l4, %l6
61334stxa %l6, [%i0 + 0] %asi
61335add %l4, 1, %l4
61336
61337P5802: !_MEMBAR (Int) (Branch target of P5721)
61338membar #StoreLoad
61339ba P5803
61340nop
61341
61342TARGET5721:
61343ba RET5721
61344nop
61345
61346
61347P5803: !_CAS [17] (maybe <- 0x2800149) (Int)
61348sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
61349sub %i0, %i3, %i3
61350add %i3, 12, %l6
61351lduw [%l6], %o2
61352mov %o2, %l3
61353! move %l3(lower) -> %o2(upper)
61354sllx %l3, 32, %o2
61355mov %l4, %o5
61356cas [%l6], %l3, %o5
61357! move %o5(lower) -> %o2(lower)
61358srl %o5, 0, %l3
61359or %l3, %o2, %o2
61360add %l4, 1, %l4
61361
61362P5804: !_MEMBAR (FP)
61363
61364P5805: !_BSTC [13] (maybe <- 0x420000c3) (FP)
61365wr %g0, 0xe0, %asi
61366sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
61367sub %i0, %i2, %i2
61368! preparing store val #0, next val will be in f32
61369fmovs %f16, %f20
61370fadds %f16, %f17, %f16
61371! preparing store val #1, next val will be in f33
61372fmovs %f16, %f21
61373fadds %f16, %f17, %f16
61374! preparing store val #2, next val will be in f35
61375fmovd %f20, %f32
61376fmovs %f16, %f21
61377fadds %f16, %f17, %f16
61378fmovd %f20, %f34
61379membar #Sync
61380stda %f32, [%i2 + 0 ] %asi
61381
61382P5806: !_MEMBAR (FP) (Branch target of P5819)
61383membar #StoreLoad
61384ba P5807
61385nop
61386
61387TARGET5819:
61388ba RET5819
61389nop
61390
61391
61392P5807: !_DWST_BINIT [5] (maybe <- 0x280014a) (Int)
61393wr %g0, 0xe2, %asi
61394mov %l4, %o5
61395stxa %o5, [%i1 + 8] %asi
61396add %l4, 1, %l4
61397
61398P5808: !_MEMBAR (Int) (Branch target of P5913)
61399membar #StoreLoad
61400ba P5809
61401nop
61402
61403TARGET5913:
61404ba RET5913
61405nop
61406
61407
61408P5809: !_ST_BINIT [21] (maybe <- 0x280014b) (Int)
61409wr %g0, 0xe2, %asi
61410sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
61411add %i0, %i3, %i3
61412stwa %l4, [%i3 + 0] %asi
61413add %l4, 1, %l4
61414
61415P5810: !_MEMBAR (Int)
61416membar #StoreLoad
61417
61418P5811: !_REPLACEMENT [2] (Int)
61419sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
61420sub %i0, %i2, %i2
61421sethi %hi(0x20000), %l6
61422ld [%i2+12], %o5
61423st %o5, [%i2+12]
61424add %i2, %l6, %l7
61425ld [%l7+12], %o5
61426st %o5, [%l7+12]
61427add %l7, %l6, %l7
61428ld [%l7+12], %o5
61429st %o5, [%l7+12]
61430add %l7, %l6, %l7
61431ld [%l7+12], %o5
61432st %o5, [%l7+12]
61433add %l7, %l6, %l7
61434ld [%l7+12], %o5
61435st %o5, [%l7+12]
61436add %l7, %l6, %l7
61437ld [%l7+12], %o5
61438st %o5, [%l7+12]
61439add %l7, %l6, %l7
61440ld [%l7+12], %o5
61441st %o5, [%l7+12]
61442add %l7, %l6, %l7
61443ld [%l7+12], %o5
61444st %o5, [%l7+12]
61445
61446P5812: !_CAS [8] (maybe <- 0x280014c) (Int)
61447sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
61448add %i0, %i3, %i3
61449add %i3, 12, %l6
61450lduw [%l6], %o3
61451mov %o3, %l3
61452! move %l3(lower) -> %o3(upper)
61453sllx %l3, 32, %o3
61454mov %l4, %o5
61455cas [%l6], %l3, %o5
61456! move %o5(lower) -> %o3(lower)
61457srl %o5, 0, %l3
61458or %l3, %o3, %o3
61459add %l4, 1, %l4
61460
61461P5813: !_LD [14] (Int) (Branch target of P5404)
61462sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
61463sub %i0, %i2, %i2
61464lduw [%i2 + 12], %o4
61465! move %o4(lower) -> %o4(upper)
61466sllx %o4, 32, %o4
61467ba P5814
61468nop
61469
61470TARGET5404:
61471ba RET5404
61472nop
61473
61474
61475P5814: !_ST [17] (maybe <- 0x280014d) (Int)
61476sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
61477sub %i0, %i3, %i3
61478stw %l4, [%i3 + 12 ]
61479add %l4, 1, %l4
61480
61481P5815: !_MEMBAR (FP)
61482
61483P5816: !_BST [6] (maybe <- 0x420000c6) (FP)
61484wr %g0, 0xf0, %asi
61485sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
61486add %i0, %i2, %i2
61487! preparing store val #0, next val will be in f32
61488fmovs %f16, %f20
61489fadds %f16, %f17, %f16
61490! preparing store val #1, next val will be in f33
61491fmovs %f16, %f21
61492fadds %f16, %f17, %f16
61493! preparing store val #2, next val will be in f35
61494fmovd %f20, %f32
61495fmovs %f16, %f21
61496fadds %f16, %f17, %f16
61497fmovd %f20, %f34
61498membar #Sync
61499stda %f32, [%i2 + 0 ] %asi
61500
61501P5817: !_MEMBAR (FP)
61502
61503P5818: !_BST [18] (maybe <- 0x420000c9) (FP)
61504wr %g0, 0xf0, %asi
61505sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
61506sub %i0, %i3, %i3
61507! preparing store val #0, next val will be in f32
61508fmovs %f16, %f20
61509fadds %f16, %f17, %f16
61510! preparing store val #1, next val will be in f33
61511fmovs %f16, %f21
61512fadds %f16, %f17, %f16
61513! preparing store val #2, next val will be in f35
61514fmovd %f20, %f32
61515fmovs %f16, %f21
61516fadds %f16, %f17, %f16
61517fmovd %f20, %f34
61518membar #Sync
61519stda %f32, [%i3 + 0 ] %asi
61520
61521P5819: !_MEMBAR (FP) (CBR)
61522membar #StoreLoad
61523
61524! cbranch
61525andcc %l0, 1, %g0
61526be,pt %xcc, TARGET5819
61527nop
61528RET5819:
61529
61530! lfsr step begin
61531srlx %l0, 1, %o5
61532xnor %o5, %l0, %o5
61533sllx %o5, 63, %o5
61534or %o5, %l0, %l0
61535srlx %l0, 1, %l0
61536
61537
61538P5820: !_SWAP [9] (maybe <- 0x280014e) (Int)
61539sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
61540add %i0, %i2, %i2
61541mov %l4, %l7
61542swap [%i2 + 0], %l7
61543! move %l7(lower) -> %o4(lower)
61544srl %l7, 0, %l3
61545or %l3, %o4, %o4
61546!---- flushing int results buffer----
61547mov %o0, %l5
61548mov %o1, %l5
61549mov %o2, %l5
61550mov %o3, %l5
61551mov %o4, %l5
61552add %l4, 1, %l4
61553
61554P5821: !_CASX [13] (maybe <- 0x280014f) (Int)
61555sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
61556sub %i0, %i3, %i3
61557ldx [%i3], %o0
61558! move %o0(upper) -> %o0(upper)
61559! move %o0(lower) -> %o0(lower)
61560mov %o0, %o5
61561sllx %l4, 32, %o1
61562add %l4, 1, %l4
61563or %l4, %o1, %o1
61564casx [%i3], %o5, %o1
61565! move %o1(upper) -> %o1(upper)
61566! move %o1(lower) -> %o1(lower)
61567add %l4, 1, %l4
61568
61569P5822: !_ST [7] (maybe <- 0x2800151) (Int)
61570sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
61571add %i0, %i2, %i2
61572stw %l4, [%i2 + 4 ]
61573add %l4, 1, %l4
61574
61575P5823: !_REPLACEMENT [3] (Int)
61576sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
61577add %i0, %i3, %i3
61578sethi %hi(0x20000), %l7
61579ld [%i3+0], %l3
61580st %l3, [%i3+0]
61581add %i3, %l7, %o5
61582ld [%o5+0], %l3
61583st %l3, [%o5+0]
61584add %o5, %l7, %o5
61585ld [%o5+0], %l3
61586st %l3, [%o5+0]
61587add %o5, %l7, %o5
61588ld [%o5+0], %l3
61589st %l3, [%o5+0]
61590add %o5, %l7, %o5
61591ld [%o5+0], %l3
61592st %l3, [%o5+0]
61593add %o5, %l7, %o5
61594ld [%o5+0], %l3
61595st %l3, [%o5+0]
61596add %o5, %l7, %o5
61597ld [%o5+0], %l3
61598st %l3, [%o5+0]
61599add %o5, %l7, %o5
61600ld [%o5+0], %l3
61601st %l3, [%o5+0]
61602
61603P5824: !_LDD [3] (Int)
61604ldd [%i1 + 0], %l6
61605! move %l6(lower) -> %o2(upper)
61606sllx %l6, 32, %o2
61607! move %l7(lower) -> %o2(lower)
61608or %l7, %o2, %o2
61609
61610P5825: !_MEMBAR (FP)
61611membar #StoreLoad
61612
61613P5826: !_BLD [13] (FP)
61614wr %g0, 0xf0, %asi
61615sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
61616sub %i0, %i2, %i2
61617ldda [%i2 + 0] %asi, %f32
61618membar #Sync
61619! 3 addresses covered
61620fmovd %f32, %f18
61621fmovs %f18, %f3
61622fmovs %f19, %f4
61623fmovd %f34, %f18
61624fmovs %f19, %f5
61625
61626P5827: !_MEMBAR (FP)
61627
61628P5828: !_ST_BINIT [8] (maybe <- 0x2800152) (Int)
61629wr %g0, 0xe2, %asi
61630sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
61631add %i0, %i3, %i3
61632stwa %l4, [%i3 + 12] %asi
61633add %l4, 1, %l4
61634
61635P5829: !_MEMBAR (Int)
61636membar #StoreLoad
61637
61638P5830: !_REPLACEMENT [9] (Int) (Branch target of P5594)
61639sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
61640sub %i0, %i2, %i2
61641sethi %hi(0x20000), %o5
61642ld [%i2+0], %l6
61643st %l6, [%i2+0]
61644add %i2, %o5, %l3
61645ld [%l3+0], %l6
61646st %l6, [%l3+0]
61647add %l3, %o5, %l3
61648ld [%l3+0], %l6
61649st %l6, [%l3+0]
61650add %l3, %o5, %l3
61651ld [%l3+0], %l6
61652st %l6, [%l3+0]
61653add %l3, %o5, %l3
61654ld [%l3+0], %l6
61655st %l6, [%l3+0]
61656add %l3, %o5, %l3
61657ld [%l3+0], %l6
61658st %l6, [%l3+0]
61659add %l3, %o5, %l3
61660ld [%l3+0], %l6
61661st %l6, [%l3+0]
61662add %l3, %o5, %l3
61663ld [%l3+0], %l6
61664st %l6, [%l3+0]
61665ba P5831
61666nop
61667
61668TARGET5594:
61669ba RET5594
61670nop
61671
61672
61673P5831: !_ST_BINIT [6] (maybe <- 0x2800153) (Int)
61674wr %g0, 0xe2, %asi
61675stwa %l4, [%i3 + 0] %asi
61676add %l4, 1, %l4
61677
61678P5832: !_MEMBAR (Int)
61679membar #StoreLoad
61680
61681P5833: !_REPLACEMENT [10] (Int)
61682sethi %hi(0x20000), %l6
61683ld [%i2+4], %o5
61684st %o5, [%i2+4]
61685add %i2, %l6, %l7
61686ld [%l7+4], %o5
61687st %o5, [%l7+4]
61688add %l7, %l6, %l7
61689ld [%l7+4], %o5
61690st %o5, [%l7+4]
61691add %l7, %l6, %l7
61692ld [%l7+4], %o5
61693st %o5, [%l7+4]
61694add %l7, %l6, %l7
61695ld [%l7+4], %o5
61696st %o5, [%l7+4]
61697add %l7, %l6, %l7
61698ld [%l7+4], %o5
61699st %o5, [%l7+4]
61700add %l7, %l6, %l7
61701ld [%l7+4], %o5
61702st %o5, [%l7+4]
61703add %l7, %l6, %l7
61704ld [%l7+4], %o5
61705st %o5, [%l7+4]
61706
61707P5834: !_SWAP [17] (maybe <- 0x2800154) (Int)
61708sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
61709sub %i0, %i3, %i3
61710mov %l4, %o3
61711swap [%i3 + 12], %o3
61712! move %o3(lower) -> %o3(upper)
61713sllx %o3, 32, %o3
61714add %l4, 1, %l4
61715
61716P5835: !_MEMBAR (FP)
61717
61718P5836: !_BST [0] (maybe <- 0x420000cc) (FP)
61719wr %g0, 0xf0, %asi
61720! preparing store val #0, next val will be in f32
61721fmovs %f16, %f20
61722fadds %f16, %f17, %f16
61723! preparing store val #1, next val will be in f33
61724fmovs %f16, %f21
61725fadds %f16, %f17, %f16
61726! preparing store val #2, next val will be in f35
61727fmovd %f20, %f32
61728fmovs %f16, %f21
61729fadds %f16, %f17, %f16
61730fmovd %f20, %f34
61731membar #Sync
61732stda %f32, [%i0 + 0 ] %asi
61733
61734P5837: !_MEMBAR (FP)
61735membar #StoreLoad
61736
61737P5838: !_DWLD [0] (Int) (LE)
61738wr %g0, 0x88, %asi
61739ldxa [%i0 + 0] %asi, %o5
61740! move %o5(lower) -> %o3(lower)
61741srl %o5, 0, %l7
61742or %l7, %o3, %o3
61743! move %o5(upper) -> %o4(upper)
61744or %o5, %g0, %o4
61745
61746P5839: !_ST [8] (maybe <- 0x2800155) (Int)
61747sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
61748add %i0, %i2, %i2
61749stw %l4, [%i2 + 12 ]
61750add %l4, 1, %l4
61751
61752P5840: !_ST [17] (maybe <- 0x2800156) (Int)
61753stw %l4, [%i3 + 12 ]
61754add %l4, 1, %l4
61755
61756P5841: !_CASX [3] (maybe <- 0x2800157) (Int)
61757ldx [%i1], %l6
61758! move %l6(upper) -> %o4(lower)
61759srlx %o4, 32, %o4
61760sllx %o4, 32, %o4
61761srlx %l6, 32, %l7
61762or %l7, %o4, %o4
61763!---- flushing int results buffer----
61764mov %o0, %l5
61765mov %o1, %l5
61766mov %o2, %l5
61767mov %o3, %l5
61768mov %o4, %l5
61769! move %l6(lower) -> %o0(upper)
61770sllx %l6, 32, %o0
61771mov %l6, %l7
61772sllx %l4, 32, %l6
61773add %l4, 1, %l4
61774or %l4, %l6, %l6
61775casx [%i1], %l7, %l6
61776! move %l6(upper) -> %o0(lower)
61777srlx %l6, 32, %l7
61778or %l7, %o0, %o0
61779! move %l6(lower) -> %o1(upper)
61780sllx %l6, 32, %o1
61781add %l4, 1, %l4
61782
61783P5842: !_CASX [17] (maybe <- 0x2800159) (Int) (LE)
61784! Change single-word-level endianess (big endian <-> little endian)
61785sethi %hi(0xff00ff00), %o5
61786or %o5, %lo(0xff00ff00), %o5
61787and %l4, %o5, %l7
61788srl %l7, 8, %l7
61789sll %l4, 8, %l3
61790and %l3, %o5, %l3
61791or %l3, %l7, %l3
61792srl %l3, 16, %l7
61793sll %l3, 16, %l3
61794srl %l3, 0, %l3
61795or %l3, %l7, %l3
61796sllx %l3, 32, %l3
61797wr %g0, 0x88, %asi
61798add %i3, 8, %o5
61799ldxa [%o5] %asi, %l6
61800! move %l6(lower) -> %o1(lower)
61801srl %l6, 0, %l7
61802or %l7, %o1, %o1
61803! move %l6(upper) -> %o2(upper)
61804or %l6, %g0, %o2
61805mov %l6, %l7
61806mov %l3, %l6
61807casxa [%o5] %asi, %l7, %l6
61808! move %l6(lower) -> %o2(lower)
61809srlx %o2, 32, %o2
61810sllx %o2, 32, %o2
61811srl %l6, 0, %l7
61812or %l7, %o2, %o2
61813! move %l6(upper) -> %o3(upper)
61814or %l6, %g0, %o3
61815add %l4, 1, %l4
61816
61817P5843: !_MEMBAR (FP)
61818
61819P5844: !_BST [19] (maybe <- 0x420000cf) (FP)
61820wr %g0, 0xf0, %asi
61821sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
61822sub %i0, %i3, %i3
61823! preparing store val #0, next val will be in f32
61824fmovs %f16, %f20
61825fadds %f16, %f17, %f16
61826! preparing store val #1, next val will be in f33
61827fmovs %f16, %f21
61828fadds %f16, %f17, %f16
61829! preparing store val #2, next val will be in f35
61830fmovd %f20, %f32
61831fmovs %f16, %f21
61832fadds %f16, %f17, %f16
61833fmovd %f20, %f34
61834membar #Sync
61835stda %f32, [%i3 + 0 ] %asi
61836
61837P5845: !_MEMBAR (FP)
61838membar #StoreLoad
61839
61840P5846: !_PREFETCH [11] (Int)
61841sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
61842add %i0, %i2, %i2
61843prefetch [%i2 + 12], 27
61844
61845P5847: !_MEMBAR (FP)
61846
61847P5848: !_BSTC [2] (maybe <- 0x420000d2) (FP)
61848wr %g0, 0xe0, %asi
61849! preparing store val #0, next val will be in f32
61850fmovs %f16, %f20
61851fadds %f16, %f17, %f16
61852! preparing store val #1, next val will be in f33
61853fmovs %f16, %f21
61854fadds %f16, %f17, %f16
61855! preparing store val #2, next val will be in f35
61856fmovd %f20, %f32
61857fmovs %f16, %f21
61858fadds %f16, %f17, %f16
61859fmovd %f20, %f34
61860membar #Sync
61861stda %f32, [%i0 + 0 ] %asi
61862
61863P5849: !_MEMBAR (FP)
61864membar #StoreLoad
61865
61866P5850: !_PREFETCH [18] (Int)
61867prefetch [%i3 + 0], 22
61868
61869P5851: !_CAS [21] (maybe <- 0x280015a) (Int)
61870sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
61871add %i0, %i3, %i3
61872lduw [%i3], %l3
61873mov %l3, %l6
61874! move %l6(lower) -> %o3(lower)
61875srlx %o3, 32, %o3
61876sllx %o3, 32, %o3
61877or %l6, %o3, %o3
61878mov %l4, %o4
61879cas [%i3], %l6, %o4
61880! move %o4(lower) -> %o4(upper)
61881sllx %o4, 32, %o4
61882add %l4, 1, %l4
61883
61884P5852: !_ST [7] (maybe <- 0x280015b) (Int)
61885sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
61886add %i0, %i2, %i2
61887stw %l4, [%i2 + 4 ]
61888add %l4, 1, %l4
61889
61890P5853: !_MEMBAR (FP)
61891
61892P5854: !_BSTC [1] (maybe <- 0x420000d5) (FP)
61893wr %g0, 0xe0, %asi
61894! preparing store val #0, next val will be in f32
61895fmovs %f16, %f20
61896fadds %f16, %f17, %f16
61897! preparing store val #1, next val will be in f33
61898fmovs %f16, %f21
61899fadds %f16, %f17, %f16
61900! preparing store val #2, next val will be in f35
61901fmovd %f20, %f32
61902fmovs %f16, %f21
61903fadds %f16, %f17, %f16
61904fmovd %f20, %f34
61905membar #Sync
61906stda %f32, [%i0 + 0 ] %asi
61907
61908P5855: !_MEMBAR (FP)
61909membar #StoreLoad
61910
61911P5856: !_BLD [20] (FP)
61912wr %g0, 0xf0, %asi
61913sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
61914sub %i0, %i3, %i3
61915ldda [%i3 + 0] %asi, %f32
61916membar #Sync
61917! 3 addresses covered
61918fmovd %f32, %f6
61919fmovd %f34, %f18
61920fmovs %f19, %f8
61921
61922P5857: !_MEMBAR (FP)
61923
61924P5858: !_CASX [7] (maybe <- 0x280015c) (Int)
61925ldx [%i2], %l7
61926! move %l7(upper) -> %o4(lower)
61927srlx %l7, 32, %o5
61928or %o5, %o4, %o4
61929!---- flushing int results buffer----
61930mov %o0, %l5
61931mov %o1, %l5
61932mov %o2, %l5
61933mov %o3, %l5
61934mov %o4, %l5
61935! move %l7(lower) -> %o0(upper)
61936sllx %l7, 32, %o0
61937mov %l7, %o5
61938sllx %l4, 32, %l7
61939add %l4, 1, %l4
61940or %l4, %l7, %l7
61941casx [%i2], %o5, %l7
61942! move %l7(upper) -> %o0(lower)
61943srlx %l7, 32, %o5
61944or %o5, %o0, %o0
61945! move %l7(lower) -> %o1(upper)
61946sllx %l7, 32, %o1
61947add %l4, 1, %l4
61948
61949P5859: !_LD [16] (Int)
61950sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
61951sub %i0, %i2, %i2
61952lduw [%i2 + 4], %l3
61953! move %l3(lower) -> %o1(lower)
61954or %l3, %o1, %o1
61955
61956P5860: !_LDD [9] (Int) (LE)
61957wr %g0, 0x88, %asi
61958sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
61959add %i0, %i3, %i3
61960ldda [%i3 + 0] %asi, %l6
61961! move %l6(lower) -> %o2(upper)
61962sllx %l6, 32, %o2
61963! move %l7(lower) -> %o2(lower)
61964or %l7, %o2, %o2
61965
61966P5861: !_REPLACEMENT [17] (Int)
61967sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
61968sub %i0, %i2, %i2
61969sethi %hi(0x20000), %l3
61970ld [%i2+12], %l7
61971st %l7, [%i2+12]
61972add %i2, %l3, %l6
61973ld [%l6+12], %l7
61974st %l7, [%l6+12]
61975add %l6, %l3, %l6
61976ld [%l6+12], %l7
61977st %l7, [%l6+12]
61978add %l6, %l3, %l6
61979ld [%l6+12], %l7
61980st %l7, [%l6+12]
61981add %l6, %l3, %l6
61982ld [%l6+12], %l7
61983st %l7, [%l6+12]
61984add %l6, %l3, %l6
61985ld [%l6+12], %l7
61986st %l7, [%l6+12]
61987add %l6, %l3, %l6
61988ld [%l6+12], %l7
61989st %l7, [%l6+12]
61990add %l6, %l3, %l6
61991ld [%l6+12], %l7
61992st %l7, [%l6+12]
61993
61994P5862: !_REPLACEMENT [16] (Int)
61995sethi %hi(0x20000), %o5
61996ld [%i2+4], %l6
61997st %l6, [%i2+4]
61998add %i2, %o5, %l3
61999ld [%l3+4], %l6
62000st %l6, [%l3+4]
62001add %l3, %o5, %l3
62002ld [%l3+4], %l6
62003st %l6, [%l3+4]
62004add %l3, %o5, %l3
62005ld [%l3+4], %l6
62006st %l6, [%l3+4]
62007add %l3, %o5, %l3
62008ld [%l3+4], %l6
62009st %l6, [%l3+4]
62010add %l3, %o5, %l3
62011ld [%l3+4], %l6
62012st %l6, [%l3+4]
62013add %l3, %o5, %l3
62014ld [%l3+4], %l6
62015st %l6, [%l3+4]
62016add %l3, %o5, %l3
62017ld [%l3+4], %l6
62018st %l6, [%l3+4]
62019
62020P5863: !_ST [17] (maybe <- 0x280015e) (Int)
62021sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
62022sub %i0, %i3, %i3
62023stw %l4, [%i3 + 12 ]
62024add %l4, 1, %l4
62025
62026P5864: !_PREFETCH [14] (Int)
62027sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
62028sub %i0, %i2, %i2
62029prefetch [%i2 + 12], 4
62030
62031P5865: !_SWAP [13] (maybe <- 0x280015f) (Int)
62032mov %l4, %o3
62033swap [%i2 + 4], %o3
62034! move %o3(lower) -> %o3(upper)
62035sllx %o3, 32, %o3
62036add %l4, 1, %l4
62037
62038P5866: !_PREFETCH [11] (Int)
62039sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
62040add %i0, %i3, %i3
62041prefetch [%i3 + 12], 0
62042
62043P5867: !_DWST [19] (maybe <- 0x2800160) (Int)
62044sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
62045sub %i0, %i2, %i2
62046sllx %l4, 32, %l3
62047add %l4, 1, %l4
62048or %l3, %l4, %l3
62049stx %l3, [%i2 + 0]
62050add %l4, 1, %l4
62051
62052P5868: !_PREFETCH [17] (Int)
62053sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
62054sub %i0, %i3, %i3
62055prefetch [%i3 + 12], 0
62056
62057P5869: !_ST_BINIT [0] (maybe <- 0x2800162) (Int)
62058wr %g0, 0xe2, %asi
62059stwa %l4, [%i0 + 0] %asi
62060add %l4, 1, %l4
62061
62062P5870: !_MEMBAR (Int)
62063
62064P5871: !_BSTC [15] (maybe <- 0x420000d8) (FP)
62065wr %g0, 0xe0, %asi
62066! preparing store val #0, next val will be in f32
62067fmovs %f16, %f20
62068fadds %f16, %f17, %f16
62069! preparing store val #1, next val will be in f33
62070fmovs %f16, %f21
62071fadds %f16, %f17, %f16
62072! preparing store val #2, next val will be in f35
62073fmovd %f20, %f32
62074fmovs %f16, %f21
62075fadds %f16, %f17, %f16
62076fmovd %f20, %f34
62077membar #Sync
62078stda %f32, [%i3 + 0 ] %asi
62079
62080P5872: !_MEMBAR (FP) (Branch target of P5729)
62081membar #StoreLoad
62082ba P5873
62083nop
62084
62085TARGET5729:
62086ba RET5729
62087nop
62088
62089
62090P5873: !_DWST [5] (maybe <- 0x2800163) (Int) (CBR)
62091mov %l4, %l6
62092stx %l6, [%i1 + 8]
62093add %l4, 1, %l4
62094
62095! cbranch
62096andcc %l0, 1, %g0
62097be,pt %xcc, TARGET5873
62098nop
62099RET5873:
62100
62101! lfsr step begin
62102srlx %l0, 1, %l3
62103xnor %l3, %l0, %l3
62104sllx %l3, 63, %l3
62105or %l3, %l0, %l0
62106srlx %l0, 1, %l0
62107
62108
62109P5874: !_SWAP [1] (maybe <- 0x2800164) (Int)
62110mov %l4, %o5
62111swap [%i0 + 4], %o5
62112! move %o5(lower) -> %o3(lower)
62113srl %o5, 0, %l6
62114or %l6, %o3, %o3
62115add %l4, 1, %l4
62116
62117P5875: !_ST_BINIT [22] (maybe <- 0x2800165) (Int)
62118wr %g0, 0xe2, %asi
62119sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
62120add %i0, %i2, %i2
62121stwa %l4, [%i2 + 4] %asi
62122add %l4, 1, %l4
62123
62124P5876: !_MEMBAR (Int)
62125membar #StoreLoad
62126
62127P5877: !_ST [5] (maybe <- 0x2800166) (Int)
62128stw %l4, [%i1 + 12 ]
62129add %l4, 1, %l4
62130
62131P5878: !_MEMBAR (FP)
62132membar #StoreLoad
62133
62134P5879: !_BLD [18] (FP)
62135wr %g0, 0xf0, %asi
62136sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
62137sub %i0, %i3, %i3
62138ldda [%i3 + 0] %asi, %f32
62139membar #Sync
62140! 3 addresses covered
62141fmovd %f32, %f18
62142fmovs %f18, %f9
62143fmovs %f19, %f10
62144fmovd %f34, %f18
62145fmovs %f19, %f11
62146
62147P5880: !_MEMBAR (FP)
62148
62149P5881: !_BSTC [3] (maybe <- 0x420000db) (FP)
62150wr %g0, 0xe0, %asi
62151! preparing store val #0, next val will be in f32
62152fmovs %f16, %f20
62153fadds %f16, %f17, %f16
62154! preparing store val #1, next val will be in f33
62155fmovs %f16, %f21
62156fadds %f16, %f17, %f16
62157! preparing store val #2, next val will be in f35
62158fmovd %f20, %f32
62159fmovs %f16, %f21
62160fadds %f16, %f17, %f16
62161fmovd %f20, %f34
62162membar #Sync
62163stda %f32, [%i1 + 0 ] %asi
62164
62165P5882: !_MEMBAR (FP)
62166membar #StoreLoad
62167
62168P5883: !_BLD [18] (FP)
62169wr %g0, 0xf0, %asi
62170ldda [%i3 + 0] %asi, %f32
62171membar #Sync
62172! 3 addresses covered
62173fmovd %f32, %f12
62174fmovd %f34, %f18
62175fmovs %f19, %f14
62176
62177P5884: !_MEMBAR (FP)
62178
62179P5885: !_CAS [13] (maybe <- 0x2800167) (Int) (Branch target of P5919)
62180sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
62181sub %i0, %i2, %i2
62182add %i2, 4, %l7
62183lduw [%l7], %o4
62184mov %o4, %l6
62185! move %l6(lower) -> %o4(upper)
62186sllx %l6, 32, %o4
62187mov %l4, %l3
62188cas [%l7], %l6, %l3
62189! move %l3(lower) -> %o4(lower)
62190srl %l3, 0, %l6
62191or %l6, %o4, %o4
62192!---- flushing int results buffer----
62193mov %o0, %l5
62194mov %o1, %l5
62195mov %o2, %l5
62196mov %o3, %l5
62197mov %o4, %l5
62198add %l4, 1, %l4
62199ba P5886
62200nop
62201
62202TARGET5919:
62203ba RET5919
62204nop
62205
62206
62207P5886: !_LDD [16] (Int)
62208sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
62209sub %i0, %i3, %i3
62210ldd [%i3 + 0], %l6
62211! move %l6(lower) -> %o0(upper)
62212sllx %l6, 32, %o0
62213! move %l7(lower) -> %o0(lower)
62214or %l7, %o0, %o0
62215
62216P5887: !_LDD [8] (Int)
62217sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
62218add %i0, %i2, %i2
62219ldd [%i2 + 8], %l6
62220! move %l7(lower) -> %o1(upper)
62221sllx %l7, 32, %o1
62222
62223P5888: !_MEMBAR (FP)
62224
62225P5889: !_BST [3] (maybe <- 0x420000de) (FP)
62226wr %g0, 0xf0, %asi
62227! preparing store val #0, next val will be in f32
62228fmovs %f16, %f20
62229fadds %f16, %f17, %f16
62230! preparing store val #1, next val will be in f33
62231fmovs %f16, %f21
62232fadds %f16, %f17, %f16
62233! preparing store val #2, next val will be in f35
62234fmovd %f20, %f32
62235fmovs %f16, %f21
62236fadds %f16, %f17, %f16
62237fmovd %f20, %f34
62238membar #Sync
62239stda %f32, [%i1 + 0 ] %asi
62240
62241P5890: !_MEMBAR (FP)
62242membar #StoreLoad
62243
62244P5891: !_DWST_BINIT [5] (maybe <- 0x2800168) (Int) (CBR)
62245wr %g0, 0xe2, %asi
62246mov %l4, %o5
62247stxa %o5, [%i1 + 8] %asi
62248add %l4, 1, %l4
62249
62250! cbranch
62251andcc %l0, 1, %g0
62252be,pn %xcc, TARGET5891
62253nop
62254RET5891:
62255
62256! lfsr step begin
62257srlx %l0, 1, %l7
62258xnor %l7, %l0, %l7
62259sllx %l7, 63, %l7
62260or %l7, %l0, %l0
62261srlx %l0, 1, %l0
62262
62263
62264P5892: !_MEMBAR (Int) (CBR)
62265membar #StoreLoad
62266
62267! cbranch
62268andcc %l0, 1, %g0
62269be,pn %xcc, TARGET5892
62270nop
62271RET5892:
62272
62273! lfsr step begin
62274srlx %l0, 1, %o5
62275xnor %o5, %l0, %o5
62276sllx %o5, 63, %o5
62277or %o5, %l0, %l0
62278srlx %l0, 1, %l0
62279
62280
62281P5893: !_PREFETCH [15] (Int)
62282prefetch [%i3 + 0], 27
62283
62284P5894: !_CAS [21] (maybe <- 0x2800169) (Int)
62285sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
62286add %i0, %i3, %i3
62287lduw [%i3], %o5
62288mov %o5, %l3
62289! move %l3(lower) -> %o1(lower)
62290or %l3, %o1, %o1
62291mov %l4, %o2
62292cas [%i3], %l3, %o2
62293! move %o2(lower) -> %o2(upper)
62294sllx %o2, 32, %o2
62295add %l4, 1, %l4
62296
62297P5895: !_ST [1] (maybe <- 0x280016a) (Int) (LE)
62298wr %g0, 0x88, %asi
62299! Change single-word-level endianess (big endian <-> little endian)
62300sethi %hi(0xff00ff00), %l6
62301or %l6, %lo(0xff00ff00), %l6
62302and %l4, %l6, %l7
62303srl %l7, 8, %l7
62304sll %l4, 8, %l3
62305and %l3, %l6, %l3
62306or %l3, %l7, %l3
62307srl %l3, 16, %l7
62308sll %l3, 16, %l3
62309srl %l3, 0, %l3
62310or %l3, %l7, %l3
62311stwa %l3, [%i0 + 4] %asi
62312add %l4, 1, %l4
62313
62314P5896: !_MEMBAR (FP)
62315
62316P5897: !_BST [2] (maybe <- 0x420000e1) (FP)
62317wr %g0, 0xf0, %asi
62318! preparing store val #0, next val will be in f32
62319fmovs %f16, %f20
62320fadds %f16, %f17, %f16
62321! preparing store val #1, next val will be in f33
62322fmovs %f16, %f21
62323fadds %f16, %f17, %f16
62324! preparing store val #2, next val will be in f35
62325fmovd %f20, %f32
62326fmovs %f16, %f21
62327fadds %f16, %f17, %f16
62328fmovd %f20, %f34
62329membar #Sync
62330stda %f32, [%i0 + 0 ] %asi
62331
62332P5898: !_MEMBAR (FP)
62333membar #StoreLoad
62334
62335P5899: !_ST [4] (maybe <- 0x280016b) (Int)
62336stw %l4, [%i1 + 4 ]
62337add %l4, 1, %l4
62338
62339P5900: !_CAS [17] (maybe <- 0x280016c) (Int)
62340sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
62341sub %i0, %i2, %i2
62342add %i2, 12, %l7
62343lduw [%l7], %l3
62344mov %l3, %l6
62345! move %l6(lower) -> %o2(lower)
62346or %l6, %o2, %o2
62347mov %l4, %o3
62348cas [%l7], %l6, %o3
62349! move %o3(lower) -> %o3(upper)
62350sllx %o3, 32, %o3
62351add %l4, 1, %l4
62352
62353P5901: !_DWST [17] (maybe <- 0x280016d) (Int)
62354mov %l4, %l6
62355stx %l6, [%i2 + 8]
62356add %l4, 1, %l4
62357
62358P5902: !_DWLD [14] (Int)
62359sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
62360sub %i0, %i3, %i3
62361ldx [%i3 + 8], %l6
62362! move %l6(lower) -> %o3(lower)
62363srl %l6, 0, %l3
62364or %l3, %o3, %o3
62365
62366P5903: !_LD [21] (Int)
62367sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
62368add %i0, %i2, %i2
62369lduw [%i2 + 0], %o4
62370! move %o4(lower) -> %o4(upper)
62371sllx %o4, 32, %o4
62372
62373P5904: !_SWAP [4] (maybe <- 0x280016e) (Int)
62374mov %l4, %l7
62375swap [%i1 + 4], %l7
62376! move %l7(lower) -> %o4(lower)
62377srl %l7, 0, %l3
62378or %l3, %o4, %o4
62379!---- flushing int results buffer----
62380mov %o0, %l5
62381mov %o1, %l5
62382mov %o2, %l5
62383mov %o3, %l5
62384mov %o4, %l5
62385add %l4, 1, %l4
62386
62387P5905: !_SWAP [4] (maybe <- 0x280016f) (Int)
62388mov %l4, %o0
62389swap [%i1 + 4], %o0
62390! move %o0(lower) -> %o0(upper)
62391sllx %o0, 32, %o0
62392add %l4, 1, %l4
62393
62394P5906: !_MEMBAR (FP)
62395membar #StoreLoad
62396
62397P5907: !_BLD [17] (FP)
62398wr %g0, 0xf0, %asi
62399sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
62400sub %i0, %i3, %i3
62401ldda [%i3 + 0] %asi, %f32
62402membar #Sync
62403! 3 addresses covered
62404fmovd %f32, %f18
62405fmovs %f18, %f15
62406!---- flushing fp results buffer to %f30 ----
62407fmovd %f0, %f30
62408fmovd %f2, %f30
62409fmovd %f4, %f30
62410fmovd %f6, %f30
62411fmovd %f8, %f30
62412fmovd %f10, %f30
62413fmovd %f12, %f30
62414fmovd %f14, %f30
62415!--
62416fmovs %f19, %f0
62417fmovd %f34, %f18
62418fmovs %f19, %f1
62419
62420P5908: !_MEMBAR (FP)
62421
62422P5909: !_BST [5] (maybe <- 0x420000e4) (FP)
62423!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #3
62424!Logical addr: 5
62425
62426sethi %hi(0x200000), %l7
62427sub %i1, %l7, %i1
62428wr %g0, 0xf0, %asi
62429! preparing store val #0, next val will be in f32
62430fmovs %f16, %f20
62431fadds %f16, %f17, %f16
62432! preparing store val #1, next val will be in f33
62433fmovs %f16, %f21
62434fadds %f16, %f17, %f16
62435! preparing store val #2, next val will be in f35
62436fmovd %f20, %f32
62437fmovs %f16, %f21
62438fadds %f16, %f17, %f16
62439fmovd %f20, %f34
62440membar #Sync
62441stda %f32, [%i1 + 0 ] %asi
62442
62443P5910: !_MEMBAR (FP)
62444membar #StoreLoad
62445
62446P5911: !_CASX [22] (maybe <- 0x2800170) (Int)
62447ldx [%i2], %l6
62448! move %l6(upper) -> %o0(lower)
62449srlx %l6, 32, %l7
62450or %l7, %o0, %o0
62451! move %l6(lower) -> %o1(upper)
62452sllx %l6, 32, %o1
62453mov %l6, %l7
62454sllx %l4, 32, %l6
62455add %l4, 1, %l4
62456or %l4, %l6, %l6
62457casx [%i2], %l7, %l6
62458! move %l6(upper) -> %o1(lower)
62459srlx %l6, 32, %l7
62460or %l7, %o1, %o1
62461! move %l6(lower) -> %o2(upper)
62462sllx %l6, 32, %o2
62463add %l4, 1, %l4
62464
62465P5912: !_ST [13] (maybe <- 0x2800172) (Int)
62466sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
62467sub %i0, %i2, %i2
62468stw %l4, [%i2 + 4 ]
62469add %l4, 1, %l4
62470
62471P5913: !_MEMBAR (FP) (CBR)
62472
62473! cbranch
62474andcc %l0, 1, %g0
62475be,pt %xcc, TARGET5913
62476nop
62477RET5913:
62478
62479! lfsr step begin
62480srlx %l0, 1, %l6
62481xnor %l6, %l0, %l6
62482sllx %l6, 63, %l6
62483or %l6, %l0, %l0
62484srlx %l0, 1, %l0
62485
62486
62487P5914: !_BSTC [3] (maybe <- 0x420000e7) (FP)
62488wr %g0, 0xe0, %asi
62489! preparing store val #0, next val will be in f32
62490fmovs %f16, %f20
62491fadds %f16, %f17, %f16
62492! preparing store val #1, next val will be in f33
62493fmovs %f16, %f21
62494fadds %f16, %f17, %f16
62495! preparing store val #2, next val will be in f35
62496fmovd %f20, %f32
62497fmovs %f16, %f21
62498fadds %f16, %f17, %f16
62499fmovd %f20, %f34
62500membar #Sync
62501stda %f32, [%i1 + 0 ] %asi
62502
62503P5915: !_MEMBAR (FP)
62504membar #StoreLoad
62505
62506P5916: !_LD [21] (Int)
62507sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
62508add %i0, %i3, %i3
62509lduw [%i3 + 0], %l7
62510! move %l7(lower) -> %o2(lower)
62511or %l7, %o2, %o2
62512
62513P5917: !_DWST_BINIT [14] (maybe <- 0x2800173) (Int) (Branch target of P5592)
62514wr %g0, 0xe2, %asi
62515mov %l4, %o5
62516stxa %o5, [%i2 + 8] %asi
62517add %l4, 1, %l4
62518ba P5918
62519nop
62520
62521TARGET5592:
62522ba RET5592
62523nop
62524
62525
62526P5918: !_MEMBAR (Int)
62527membar #StoreLoad
62528
62529P5919: !_ST [0] (maybe <- 0x2800174) (Int) (CBR) (Branch target of P5014)
62530stw %l4, [%i0 + 0 ]
62531add %l4, 1, %l4
62532
62533! cbranch
62534andcc %l0, 1, %g0
62535be,pt %xcc, TARGET5919
62536nop
62537RET5919:
62538
62539! lfsr step begin
62540srlx %l0, 1, %l6
62541xnor %l6, %l0, %l6
62542sllx %l6, 63, %l6
62543or %l6, %l0, %l0
62544srlx %l0, 1, %l0
62545
62546ba P5920
62547nop
62548
62549TARGET5014:
62550ba RET5014
62551nop
62552
62553
62554P5920: !_PREFETCH [4] (Int)
62555prefetch [%i1 + 4], 2
62556
62557P5921: !_PREFETCH [3] (Int)
62558prefetch [%i1 + 0], 4
62559
62560P5922: !_CAS [20] (maybe <- 0x2800175) (Int)
62561sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
62562sub %i0, %i2, %i2
62563add %i2, 12, %o5
62564lduw [%o5], %o3
62565mov %o3, %l7
62566! move %l7(lower) -> %o3(upper)
62567sllx %l7, 32, %o3
62568mov %l4, %l6
62569cas [%o5], %l7, %l6
62570! move %l6(lower) -> %o3(lower)
62571srl %l6, 0, %l7
62572or %l7, %o3, %o3
62573add %l4, 1, %l4
62574
62575P5923: !_SWAP [2] (maybe <- 0x2800176) (Int)
62576mov %l4, %o4
62577swap [%i0 + 12], %o4
62578! move %o4(lower) -> %o4(upper)
62579sllx %o4, 32, %o4
62580add %l4, 1, %l4
62581
62582P5924: !_SWAP [15] (maybe <- 0x2800177) (Int)
62583sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
62584sub %i0, %i3, %i3
62585mov %l4, %o5
62586swap [%i3 + 0], %o5
62587! move %o5(lower) -> %o4(lower)
62588srl %o5, 0, %l6
62589or %l6, %o4, %o4
62590!---- flushing int results buffer----
62591mov %o0, %l5
62592mov %o1, %l5
62593mov %o2, %l5
62594mov %o3, %l5
62595mov %o4, %l5
62596add %l4, 1, %l4
62597
62598P5925: !_DWST [17] (maybe <- 0x2800178) (Int)
62599mov %l4, %l3
62600stx %l3, [%i3 + 8]
62601add %l4, 1, %l4
62602
62603P5926: !_ST [17] (maybe <- 0x420000ea) (FP)
62604! preparing store val #0, next val will be in f20
62605fmovs %f16, %f20
62606fadds %f16, %f17, %f16
62607st %f20, [%i3 + 12 ]
62608
62609P5927: !_MEMBAR (FP)
62610membar #StoreLoad
62611
62612P5928: !_BLD [12] (FP)
62613wr %g0, 0xf0, %asi
62614sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
62615sub %i0, %i2, %i2
62616ldda [%i2 + 0] %asi, %f32
62617membar #Sync
62618! 3 addresses covered
62619fmovd %f32, %f2
62620fmovd %f34, %f18
62621fmovs %f19, %f4
62622
62623P5929: !_MEMBAR (FP)
62624
62625P5930: !_ST_BINIT [21] (maybe <- 0x2800179) (Int)
62626wr %g0, 0xe2, %asi
62627sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
62628add %i0, %i3, %i3
62629stwa %l4, [%i3 + 0] %asi
62630add %l4, 1, %l4
62631
62632P5931: !_MEMBAR (Int)
62633
62634P5932: !_BSTC [14] (maybe <- 0x420000eb) (FP)
62635wr %g0, 0xe0, %asi
62636! preparing store val #0, next val will be in f32
62637fmovs %f16, %f20
62638fadds %f16, %f17, %f16
62639! preparing store val #1, next val will be in f33
62640fmovs %f16, %f21
62641fadds %f16, %f17, %f16
62642! preparing store val #2, next val will be in f35
62643fmovd %f20, %f32
62644fmovs %f16, %f21
62645fadds %f16, %f17, %f16
62646fmovd %f20, %f34
62647membar #Sync
62648stda %f32, [%i2 + 0 ] %asi
62649
62650P5933: !_MEMBAR (FP)
62651membar #StoreLoad
62652
62653P5934: !_CASX [21] (maybe <- 0x280017a) (Int)
62654ldx [%i3], %o0
62655! move %o0(upper) -> %o0(upper)
62656! move %o0(lower) -> %o0(lower)
62657mov %o0, %l3
62658sllx %l4, 32, %o1
62659add %l4, 1, %l4
62660or %l4, %o1, %o1
62661casx [%i3], %l3, %o1
62662! move %o1(upper) -> %o1(upper)
62663! move %o1(lower) -> %o1(lower)
62664add %l4, 1, %l4
62665
62666P5935: !_PREFETCH [8] (Int) (Branch target of P5244)
62667sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
62668add %i0, %i2, %i2
62669prefetch [%i2 + 12], 18
62670ba P5936
62671nop
62672
62673TARGET5244:
62674ba RET5244
62675nop
62676
62677
62678P5936: !_ST_BINIT [10] (maybe <- 0x280017c) (Int)
62679wr %g0, 0xe2, %asi
62680sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
62681add %i0, %i3, %i3
62682stwa %l4, [%i3 + 4] %asi
62683add %l4, 1, %l4
62684
62685P5937: !_MEMBAR (Int)
62686membar #StoreLoad
62687
62688P5938: !_ST [20] (maybe <- 0x280017d) (Int)
62689sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
62690sub %i0, %i2, %i2
62691stw %l4, [%i2 + 12 ]
62692add %l4, 1, %l4
62693
62694P5939: !_DWLD [16] (FP) (Branch target of P5728)
62695sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
62696sub %i0, %i3, %i3
62697ldd [%i3 + 0], %f18
62698! 2 addresses covered
62699fmovs %f18, %f5
62700fmovs %f19, %f6
62701ba P5940
62702nop
62703
62704TARGET5728:
62705ba RET5728
62706nop
62707
62708
62709P5940: !_SWAP [13] (maybe <- 0x280017e) (Int)
62710sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
62711sub %i0, %i2, %i2
62712mov %l4, %o2
62713swap [%i2 + 4], %o2
62714! move %o2(lower) -> %o2(upper)
62715sllx %o2, 32, %o2
62716add %l4, 1, %l4
62717
62718P5941: !_ST [10] (maybe <- 0x280017f) (Int)
62719sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
62720add %i0, %i3, %i3
62721stw %l4, [%i3 + 4 ]
62722add %l4, 1, %l4
62723
62724P5942: !_MEMBAR (FP)
62725
62726P5943: !_BSTC [8] (maybe <- 0x420000ee) (FP)
62727wr %g0, 0xe0, %asi
62728sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
62729add %i0, %i2, %i2
62730! preparing store val #0, next val will be in f32
62731fmovs %f16, %f20
62732fadds %f16, %f17, %f16
62733! preparing store val #1, next val will be in f33
62734fmovs %f16, %f21
62735fadds %f16, %f17, %f16
62736! preparing store val #2, next val will be in f35
62737fmovd %f20, %f32
62738fmovs %f16, %f21
62739fadds %f16, %f17, %f16
62740fmovd %f20, %f34
62741membar #Sync
62742stda %f32, [%i2 + 0 ] %asi
62743
62744P5944: !_MEMBAR (FP)
62745membar #StoreLoad
62746
62747P5945: !_LDD [0] (Int)
62748ldd [%i0 + 0], %l6
62749! move %l6(lower) -> %o2(lower)
62750or %l6, %o2, %o2
62751! move %l7(lower) -> %o3(upper)
62752sllx %l7, 32, %o3
62753
62754P5946: !_ST_BINIT [17] (maybe <- 0x2800180) (Int)
62755wr %g0, 0xe2, %asi
62756sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
62757sub %i0, %i3, %i3
62758stwa %l4, [%i3 + 12] %asi
62759add %l4, 1, %l4
62760
62761P5947: !_MEMBAR (Int) (Branch target of P5576)
62762membar #StoreLoad
62763ba P5948
62764nop
62765
62766TARGET5576:
62767ba RET5576
62768nop
62769
62770
62771P5948: !_DWST [5] (maybe <- 0x2800181) (Int)
62772mov %l4, %o5
62773stx %o5, [%i1 + 8]
62774add %l4, 1, %l4
62775
62776P5949: !_DWST [4] (maybe <- 0x2800182) (Int) (LE)
62777wr %g0, 0x88, %asi
62778sllx %l4, 32, %l7
62779add %l4, 1, %l4
62780or %l7, %l4, %o5
62781! Change double-word-level endianess (big endian <-> little endian)
62782sethi %hi(0xff00ff00), %l3
62783or %l3, %lo(0xff00ff00), %l3
62784sllx %l3, 32, %l7
62785or %l3, %l7, %l3
62786and %o5, %l3, %l7
62787srlx %l7, 8, %l7
62788sllx %o5, 8, %o5
62789and %o5, %l3, %o5
62790or %o5, %l7, %o5
62791sethi %hi(0xffff0000), %l3
62792srlx %o5, 16, %l7
62793andn %l7, %l3, %l7
62794andn %o5, %l3, %o5
62795sllx %o5, 16, %o5
62796or %o5, %l7, %o5
62797srlx %o5, 32, %l7
62798sllx %o5, 32, %o5
62799or %o5, %l7, %l7
62800stxa %l7, [%i1 + 0 ] %asi
62801add %l4, 1, %l4
62802
62803P5950: !_SWAP [14] (maybe <- 0x2800184) (Int)
62804sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
62805sub %i0, %i2, %i2
62806mov %l4, %o5
62807swap [%i2 + 12], %o5
62808! move %o5(lower) -> %o3(lower)
62809srl %o5, 0, %l6
62810or %l6, %o3, %o3
62811add %l4, 1, %l4
62812
62813P5951: !_MEMBAR (FP)
62814
62815P5952: !_BST [21] (maybe <- 0x420000f1) (FP)
62816wr %g0, 0xf0, %asi
62817sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
62818add %i0, %i3, %i3
62819! preparing store val #0, next val will be in f32
62820fmovs %f16, %f20
62821fadds %f16, %f17, %f16
62822! preparing store val #1, next val will be in f33
62823fmovs %f16, %f21
62824fadds %f16, %f17, %f16
62825! preparing store val #2, next val will be in f35
62826fmovd %f20, %f32
62827fmovs %f16, %f21
62828fadds %f16, %f17, %f16
62829fmovd %f20, %f34
62830membar #Sync
62831stda %f32, [%i3 + 0 ] %asi
62832
62833P5953: !_MEMBAR (FP)
62834
62835P5954: !_BSTC [19] (maybe <- 0x420000f4) (FP)
62836wr %g0, 0xe0, %asi
62837sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
62838sub %i0, %i2, %i2
62839! preparing store val #0, next val will be in f32
62840fmovs %f16, %f20
62841fadds %f16, %f17, %f16
62842! preparing store val #1, next val will be in f33
62843fmovs %f16, %f21
62844fadds %f16, %f17, %f16
62845! preparing store val #2, next val will be in f35
62846fmovd %f20, %f32
62847fmovs %f16, %f21
62848fadds %f16, %f17, %f16
62849fmovd %f20, %f34
62850membar #Sync
62851stda %f32, [%i2 + 0 ] %asi
62852
62853P5955: !_MEMBAR (FP)
62854membar #StoreLoad
62855
62856P5956: !_PREFETCH [18] (Int)
62857prefetch [%i2 + 0], 0
62858
62859P5957: !_CASX [23] (maybe <- 0x2800185) (Int)
62860add %i3, 8, %o5
62861ldx [%o5], %o4
62862! move %o4(upper) -> %o4(upper)
62863! move %o4(lower) -> %o4(lower)
62864!---- flushing int results buffer----
62865mov %o0, %l5
62866mov %o1, %l5
62867mov %o2, %l5
62868mov %o3, %l5
62869mov %o4, %l5
62870mov %o4, %l7
62871mov %l4, %o0
62872casx [%o5], %l7, %o0
62873! move %o0(upper) -> %o0(upper)
62874! move %o0(lower) -> %o0(lower)
62875add %l4, 1, %l4
62876
62877P5958: !_REPLACEMENT [22] (Int)
62878sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
62879sub %i0, %i3, %i3
62880sethi %hi(0x20000), %l7
62881ld [%i3+4], %l3
62882st %l3, [%i3+4]
62883add %i3, %l7, %o5
62884ld [%o5+4], %l3
62885st %l3, [%o5+4]
62886add %o5, %l7, %o5
62887ld [%o5+4], %l3
62888st %l3, [%o5+4]
62889add %o5, %l7, %o5
62890ld [%o5+4], %l3
62891st %l3, [%o5+4]
62892add %o5, %l7, %o5
62893ld [%o5+4], %l3
62894st %l3, [%o5+4]
62895add %o5, %l7, %o5
62896ld [%o5+4], %l3
62897st %l3, [%o5+4]
62898add %o5, %l7, %o5
62899ld [%o5+4], %l3
62900st %l3, [%o5+4]
62901add %o5, %l7, %o5
62902ld [%o5+4], %l3
62903st %l3, [%o5+4]
62904
62905P5959: !_PREFETCH [17] (Int)
62906sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
62907sub %i0, %i2, %i2
62908prefetch [%i2 + 12], 4
62909
62910P5960: !_CASX [14] (maybe <- 0x2800186) (Int)
62911sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
62912sub %i0, %i3, %i3
62913add %i3, 8, %l7
62914ldx [%l7], %o1
62915! move %o1(upper) -> %o1(upper)
62916! move %o1(lower) -> %o1(lower)
62917mov %o1, %l6
62918mov %l4, %o2
62919casx [%l7], %l6, %o2
62920! move %o2(upper) -> %o2(upper)
62921! move %o2(lower) -> %o2(lower)
62922add %l4, 1, %l4
62923
62924P5961: !_LD [2] (Int)
62925lduw [%i0 + 12], %o3
62926! move %o3(lower) -> %o3(upper)
62927sllx %o3, 32, %o3
62928
62929P5962: !_CASX [8] (maybe <- 0x2800187) (Int)
62930sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
62931add %i0, %i2, %i2
62932add %i2, 8, %l3
62933ldx [%l3], %l7
62934! move %l7(upper) -> %o3(lower)
62935srlx %l7, 32, %o5
62936or %o5, %o3, %o3
62937! move %l7(lower) -> %o4(upper)
62938sllx %l7, 32, %o4
62939mov %l7, %o5
62940mov %l4, %l7
62941casx [%l3], %o5, %l7
62942! move %l7(upper) -> %o4(lower)
62943srlx %l7, 32, %o5
62944or %o5, %o4, %o4
62945!---- flushing int results buffer----
62946mov %o0, %l5
62947mov %o1, %l5
62948mov %o2, %l5
62949mov %o3, %l5
62950mov %o4, %l5
62951! move %l7(lower) -> %o0(upper)
62952sllx %l7, 32, %o0
62953add %l4, 1, %l4
62954
62955P5963: !_MEMBAR (FP) (Branch target of P5555)
62956ba P5964
62957nop
62958
62959TARGET5555:
62960ba RET5555
62961nop
62962
62963
62964P5964: !_BSTC [21] (maybe <- 0x420000f7) (FP)
62965wr %g0, 0xe0, %asi
62966sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
62967add %i0, %i3, %i3
62968! preparing store val #0, next val will be in f32
62969fmovs %f16, %f20
62970fadds %f16, %f17, %f16
62971! preparing store val #1, next val will be in f33
62972fmovs %f16, %f21
62973fadds %f16, %f17, %f16
62974! preparing store val #2, next val will be in f35
62975fmovd %f20, %f32
62976fmovs %f16, %f21
62977fadds %f16, %f17, %f16
62978fmovd %f20, %f34
62979membar #Sync
62980stda %f32, [%i3 + 0 ] %asi
62981
62982P5965: !_MEMBAR (FP)
62983membar #StoreLoad
62984
62985P5966: !_DWST_BINIT [13] (maybe <- 0x2800188) (Int)
62986wr %g0, 0xe2, %asi
62987sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
62988sub %i0, %i2, %i2
62989sllx %l4, 32, %l7
62990add %l4, 1, %l4
62991or %l7, %l4, %l7
62992stxa %l7, [%i2 + 0] %asi
62993add %l4, 1, %l4
62994
62995P5967: !_MEMBAR (Int)
62996membar #StoreLoad
62997
62998P5968: !_CAS [3] (maybe <- 0x280018a) (Int)
62999lduw [%i1], %l3
63000mov %l3, %l6
63001! move %l6(lower) -> %o0(lower)
63002or %l6, %o0, %o0
63003mov %l4, %o1
63004cas [%i1], %l6, %o1
63005! move %o1(lower) -> %o1(upper)
63006sllx %o1, 32, %o1
63007add %l4, 1, %l4
63008
63009P5969: !_MEMBAR (FP)
63010membar #StoreLoad
63011
63012P5970: !_BLD [8] (FP) (Branch target of P5366)
63013wr %g0, 0xf0, %asi
63014sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
63015add %i0, %i3, %i3
63016ldda [%i3 + 0] %asi, %f32
63017membar #Sync
63018! 3 addresses covered
63019fmovd %f32, %f18
63020fmovs %f18, %f7
63021fmovs %f19, %f8
63022fmovd %f34, %f18
63023fmovs %f19, %f9
63024ba P5971
63025nop
63026
63027TARGET5366:
63028ba RET5366
63029nop
63030
63031
63032P5971: !_MEMBAR (FP)
63033
63034P5972: !_DWLD [20] (Int)
63035sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
63036sub %i0, %i2, %i2
63037ldx [%i2 + 8], %l7
63038! move %l7(lower) -> %o1(lower)
63039srl %l7, 0, %l6
63040or %l6, %o1, %o1
63041
63042P5973: !_DWST_BINIT [0] (maybe <- 0x280018b) (Int)
63043wr %g0, 0xe2, %asi
63044sllx %l4, 32, %l3
63045add %l4, 1, %l4
63046or %l3, %l4, %l3
63047stxa %l3, [%i0 + 0] %asi
63048add %l4, 1, %l4
63049
63050P5974: !_MEMBAR (Int)
63051membar #StoreLoad
63052
63053P5975: !_DWLD [2] (Int)
63054ldx [%i0 + 8], %o2
63055! move %o2(lower) -> %o2(upper)
63056sllx %o2, 32, %o2
63057
63058P5976: !_REPLACEMENT [12] (Int)
63059sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
63060add %i0, %i3, %i3
63061sethi %hi(0x20000), %l6
63062ld [%i3+0], %o5
63063st %o5, [%i3+0]
63064add %i3, %l6, %l7
63065ld [%l7+0], %o5
63066st %o5, [%l7+0]
63067add %l7, %l6, %l7
63068ld [%l7+0], %o5
63069st %o5, [%l7+0]
63070add %l7, %l6, %l7
63071ld [%l7+0], %o5
63072st %o5, [%l7+0]
63073add %l7, %l6, %l7
63074ld [%l7+0], %o5
63075st %o5, [%l7+0]
63076add %l7, %l6, %l7
63077ld [%l7+0], %o5
63078st %o5, [%l7+0]
63079add %l7, %l6, %l7
63080ld [%l7+0], %o5
63081st %o5, [%l7+0]
63082add %l7, %l6, %l7
63083ld [%l7+0], %o5
63084st %o5, [%l7+0]
63085
63086P5977: !_LDD [19] (Int)
63087ldd [%i2 + 0], %l6
63088! move %l6(lower) -> %o2(lower)
63089or %l6, %o2, %o2
63090! move %l7(lower) -> %o3(upper)
63091sllx %l7, 32, %o3
63092
63093P5978: !_ST_BINIT [1] (maybe <- 0x280018d) (Int)
63094wr %g0, 0xe2, %asi
63095stwa %l4, [%i0 + 4] %asi
63096add %l4, 1, %l4
63097
63098P5979: !_MEMBAR (Int)
63099membar #StoreLoad
63100
63101P5980: !_LDD [14] (Int)
63102sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
63103sub %i0, %i2, %i2
63104ldd [%i2 + 8], %l6
63105! move %l7(lower) -> %o3(lower)
63106or %l7, %o3, %o3
63107
63108P5981: !_SWAP [12] (maybe <- 0x280018e) (Int)
63109mov %l4, %o4
63110swap [%i2 + 0], %o4
63111! move %o4(lower) -> %o4(upper)
63112sllx %o4, 32, %o4
63113add %l4, 1, %l4
63114
63115P5982: !_ST [23] (maybe <- 0x280018f) (Int) (CBR)
63116sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
63117add %i0, %i3, %i3
63118stw %l4, [%i3 + 12 ]
63119add %l4, 1, %l4
63120
63121! cbranch
63122andcc %l0, 1, %g0
63123be,pt %xcc, TARGET5982
63124nop
63125RET5982:
63126
63127! lfsr step begin
63128srlx %l0, 1, %l7
63129xnor %l7, %l0, %l7
63130sllx %l7, 63, %l7
63131or %l7, %l0, %l0
63132srlx %l0, 1, %l0
63133
63134
63135P5983: !_CASX [0] (maybe <- 0x2800190) (Int)
63136ldx [%i0], %l7
63137! move %l7(upper) -> %o4(lower)
63138srlx %l7, 32, %o5
63139or %o5, %o4, %o4
63140!---- flushing int results buffer----
63141mov %o0, %l5
63142mov %o1, %l5
63143mov %o2, %l5
63144mov %o3, %l5
63145mov %o4, %l5
63146! move %l7(lower) -> %o0(upper)
63147sllx %l7, 32, %o0
63148mov %l7, %o5
63149sllx %l4, 32, %l7
63150add %l4, 1, %l4
63151or %l4, %l7, %l7
63152casx [%i0], %o5, %l7
63153! move %l7(upper) -> %o0(lower)
63154srlx %l7, 32, %o5
63155or %o5, %o0, %o0
63156! move %l7(lower) -> %o1(upper)
63157sllx %l7, 32, %o1
63158add %l4, 1, %l4
63159
63160P5984: !_MEMBAR (FP)
63161membar #StoreLoad
63162
63163P5985: !_BLD [13] (FP)
63164wr %g0, 0xf0, %asi
63165ldda [%i2 + 0] %asi, %f32
63166membar #Sync
63167! 3 addresses covered
63168fmovd %f32, %f10
63169fmovd %f34, %f18
63170fmovs %f19, %f12
63171
63172P5986: !_MEMBAR (FP)
63173
63174P5987: !_DWLD [1] (Int) (LE)
63175wr %g0, 0x88, %asi
63176ldxa [%i0 + 0] %asi, %l3
63177! move %l3(lower) -> %o1(lower)
63178srl %l3, 0, %o5
63179or %o5, %o1, %o1
63180! move %l3(upper) -> %o2(upper)
63181or %l3, %g0, %o2
63182
63183P5988: !_ST_BINIT [7] (maybe <- 0x2800192) (Int) (LE)
63184wr %g0, 0xea, %asi
63185sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
63186add %i0, %i2, %i2
63187! Change single-word-level endianess (big endian <-> little endian)
63188sethi %hi(0xff00ff00), %l7
63189or %l7, %lo(0xff00ff00), %l7
63190and %l4, %l7, %o5
63191srl %o5, 8, %o5
63192sll %l4, 8, %l6
63193and %l6, %l7, %l6
63194or %l6, %o5, %l6
63195srl %l6, 16, %o5
63196sll %l6, 16, %l6
63197srl %l6, 0, %l6
63198or %l6, %o5, %l6
63199stwa %l6, [%i2 + 4] %asi
63200add %l4, 1, %l4
63201
63202P5989: !_MEMBAR (Int) (LE)
63203membar #StoreLoad
63204
63205P5990: !_DWST_BINIT [22] (maybe <- 0x2800193) (Int)
63206wr %g0, 0xe2, %asi
63207sllx %l4, 32, %l3
63208add %l4, 1, %l4
63209or %l3, %l4, %l3
63210stxa %l3, [%i3 + 0] %asi
63211add %l4, 1, %l4
63212
63213P5991: !_MEMBAR (Int)
63214membar #StoreLoad
63215
63216P5992: !_CAS [21] (maybe <- 0x2800195) (Int)
63217lduw [%i3], %l7
63218mov %l7, %o5
63219! move %o5(lower) -> %o2(lower)
63220srlx %o2, 32, %o2
63221sllx %o2, 32, %o2
63222or %o5, %o2, %o2
63223mov %l4, %o3
63224cas [%i3], %o5, %o3
63225! move %o3(lower) -> %o3(upper)
63226sllx %o3, 32, %o3
63227add %l4, 1, %l4
63228
63229P5993: !_MEMBAR (FP)
63230
63231P5994: !_BST [16] (maybe <- 0x420000fa) (FP)
63232wr %g0, 0xf0, %asi
63233sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
63234sub %i0, %i3, %i3
63235! preparing store val #0, next val will be in f32
63236fmovs %f16, %f20
63237fadds %f16, %f17, %f16
63238! preparing store val #1, next val will be in f33
63239fmovs %f16, %f21
63240fadds %f16, %f17, %f16
63241! preparing store val #2, next val will be in f35
63242fmovd %f20, %f32
63243fmovs %f16, %f21
63244fadds %f16, %f17, %f16
63245fmovd %f20, %f34
63246membar #Sync
63247stda %f32, [%i3 + 0 ] %asi
63248
63249P5995: !_MEMBAR (FP) (Branch target of P5654)
63250ba P5996
63251nop
63252
63253TARGET5654:
63254ba RET5654
63255nop
63256
63257
63258P5996: !_BST [3] (maybe <- 0x420000fd) (FP)
63259wr %g0, 0xf0, %asi
63260! preparing store val #0, next val will be in f32
63261fmovs %f16, %f20
63262fadds %f16, %f17, %f16
63263! preparing store val #1, next val will be in f33
63264fmovs %f16, %f21
63265fadds %f16, %f17, %f16
63266! preparing store val #2, next val will be in f35
63267fmovd %f20, %f32
63268fmovs %f16, %f21
63269fadds %f16, %f17, %f16
63270fmovd %f20, %f34
63271membar #Sync
63272stda %f32, [%i1 + 0 ] %asi
63273
63274P5997: !_MEMBAR (FP) (Branch target of P5613)
63275membar #StoreLoad
63276ba P5998
63277nop
63278
63279TARGET5613:
63280ba RET5613
63281nop
63282
63283
63284P5998: !_CAS [14] (maybe <- 0x2800196) (Int)
63285sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
63286sub %i0, %i2, %i2
63287add %i2, 12, %l7
63288lduw [%l7], %l3
63289mov %l3, %l6
63290! move %l6(lower) -> %o3(lower)
63291or %l6, %o3, %o3
63292mov %l4, %o4
63293cas [%l7], %l6, %o4
63294! move %o4(lower) -> %o4(upper)
63295sllx %o4, 32, %o4
63296add %l4, 1, %l4
63297
63298P5999: !_LD [22] (Int)
63299sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
63300add %i0, %i3, %i3
63301lduw [%i3 + 4], %l7
63302! move %l7(lower) -> %o4(lower)
63303or %l7, %o4, %o4
63304!---- flushing int results buffer----
63305mov %o0, %l5
63306mov %o1, %l5
63307mov %o2, %l5
63308mov %o3, %l5
63309mov %o4, %l5
63310
63311P6000: !_ST [19] (maybe <- 0x2800197) (Int) (Branch target of P5511)
63312sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
63313sub %i0, %i2, %i2
63314stw %l4, [%i2 + 4 ]
63315add %l4, 1, %l4
63316ba P6001
63317nop
63318
63319TARGET5511:
63320ba RET5511
63321nop
63322
63323
63324P6001: !_ST_BINIT [14] (maybe <- 0x2800198) (Int)
63325wr %g0, 0xe2, %asi
63326sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
63327sub %i0, %i3, %i3
63328stwa %l4, [%i3 + 12] %asi
63329add %l4, 1, %l4
63330
63331P6002: !_MEMBAR (Int)
63332membar #StoreLoad
63333
63334P6003: !_CASX [17] (maybe <- 0x2800199) (Int)
63335sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
63336sub %i0, %i2, %i2
63337add %i2, 8, %l7
63338ldx [%l7], %o0
63339! move %o0(upper) -> %o0(upper)
63340! move %o0(lower) -> %o0(lower)
63341mov %o0, %l6
63342mov %l4, %o1
63343casx [%l7], %l6, %o1
63344! move %o1(upper) -> %o1(upper)
63345! move %o1(lower) -> %o1(lower)
63346add %l4, 1, %l4
63347
63348P6004: !_DWST_BINIT [3] (maybe <- 0x280019a) (Int) (LE) (Branch target of P5227)
63349wr %g0, 0xea, %asi
63350sllx %l4, 32, %l6
63351add %l4, 1, %l4
63352or %l6, %l4, %l7
63353! Change double-word-level endianess (big endian <-> little endian)
63354sethi %hi(0xff00ff00), %o5
63355or %o5, %lo(0xff00ff00), %o5
63356sllx %o5, 32, %l6
63357or %o5, %l6, %o5
63358and %l7, %o5, %l6
63359srlx %l6, 8, %l6
63360sllx %l7, 8, %l7
63361and %l7, %o5, %l7
63362or %l7, %l6, %l7
63363sethi %hi(0xffff0000), %o5
63364srlx %l7, 16, %l6
63365andn %l6, %o5, %l6
63366andn %l7, %o5, %l7
63367sllx %l7, 16, %l7
63368or %l7, %l6, %l7
63369srlx %l7, 32, %l6
63370sllx %l7, 32, %l7
63371or %l7, %l6, %l6
63372stxa %l6, [%i1 + 0 ] %asi
63373add %l4, 1, %l4
63374ba P6005
63375nop
63376
63377TARGET5227:
63378ba RET5227
63379nop
63380
63381
63382P6005: !_MEMBAR (Int) (LE)
63383membar #StoreLoad
63384
63385P6006: !_LD [1] (FP)
63386ld [%i0 + 4], %f13
63387! 1 addresses covered
63388
63389P6007: !_PREFETCH [11] (Int)
63390sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
63391add %i0, %i3, %i3
63392prefetch [%i3 + 12], 0
63393
63394P6008: !_ST_BINIT [20] (maybe <- 0x280019c) (Int)
63395wr %g0, 0xe2, %asi
63396sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
63397sub %i0, %i2, %i2
63398stwa %l4, [%i2 + 12] %asi
63399add %l4, 1, %l4
63400
63401P6009: !_MEMBAR (Int)
63402membar #StoreLoad
63403
63404P6010: !_DWLD [3] (Int)
63405ldx [%i1 + 0], %o2
63406! move %o2(upper) -> %o2(upper)
63407! move %o2(lower) -> %o2(lower)
63408
63409P6011: !_MEMBAR (FP)
63410
63411P6012: !_BST [15] (maybe <- 0x42000100) (FP)
63412wr %g0, 0xf0, %asi
63413sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
63414sub %i0, %i3, %i3
63415! preparing store val #0, next val will be in f32
63416fmovs %f16, %f20
63417fadds %f16, %f17, %f16
63418! preparing store val #1, next val will be in f33
63419fmovs %f16, %f21
63420fadds %f16, %f17, %f16
63421! preparing store val #2, next val will be in f35
63422fmovd %f20, %f32
63423fmovs %f16, %f21
63424fadds %f16, %f17, %f16
63425fmovd %f20, %f34
63426membar #Sync
63427stda %f32, [%i3 + 0 ] %asi
63428
63429P6013: !_MEMBAR (FP) (Loop exit)
63430membar #StoreLoad
63431!---- flushing int results buffer----
63432mov %o0, %l5
63433mov %o1, %l5
63434mov %o2, %l5
63435!---- flushing fp results buffer to %f30 ----
63436fmovd %f0, %f30
63437fmovd %f2, %f30
63438fmovd %f4, %f30
63439fmovd %f6, %f30
63440fmovd %f8, %f30
63441fmovd %f10, %f30
63442fmovd %f12, %f30
63443!--
63444
63445sethi %hi(0x600000), %l3
63446add %i1, %l3, %i1
63447!-- End Aliased access: base register for region 1 (%i1) restored
63448loop_exit_5_0:
63449sub %l2, 1, %l2
63450cmp %l2, 0
63451bg loop_entry_5_0
63452nop
63453
63454P6014: !_MEMBAR (Int)
63455membar #StoreLoad
63456
63457END_NODES5: ! Test instruction sequence for CPU 5 ends
63458sethi %hi(0xdead0e0f), %l6
63459or %l6, %lo(0xdead0e0f), %l6
63460! move %l6(lower) -> %o0(upper)
63461sllx %l6, 32, %o0
63462sethi %hi(0xdead0e0f), %l6
63463or %l6, %lo(0xdead0e0f), %l6
63464stw %l6, [%i5]
63465ld [%i5], %f0
63466!---- flushing int results buffer----
63467mov %o0, %l5
63468!---- flushing fp results buffer to %f30 ----
63469fmovs %f0, %f30
63470!--
63471
63472restore
63473retl
63474nop
63475!-----------------
63476
63477! register usage:
63478! %i0 %i1 : base registers for first 2 regions
63479! %i2 %i3 : cache registers for 8 regions
63480! %i4 fixed pointer to per-cpu results area
63481! %l1 moving pointer to per-cpu FP results area
63482! %o7 moving pointer to per-cpu integer results area
63483! %i5 pointer to per-cpu private area
63484! %l0 holds lfsr, used as source of random bits
63485! %l2 loop count register
63486! %f16 running counter for unique fp store values
63487! %f17 holds increment value for fp counter
63488! %l4 running counter for unique integer store values (increment value is always 1)
63489! %l5 move-to register for load values (simulation only)
63490! %f30 move-to register for FP values (simulation only)
63491! %i4 holds the instructions count which is used for interrupt ordering
63492! %i4 holds the thread_id (OBP only)
63493! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage
63494! %l3 %l6 %l7 %o5 : 4 temporary registers
63495! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
63496! %f0-f15 FP results buffer registers
63497! %f32-f47 FP block load/store registers
63498
63499func6:
63500! instruction sequence begins
63501save %sp, -192, %sp
63502
63503! Force %i0-%i3 to be 64-byte aligned
63504add %i0, 63, %i0
63505andn %i0, 63, %i0
63506
63507add %i1, 63, %i1
63508andn %i1, 63, %i1
63509
63510add %i2, 63, %i2
63511andn %i2, 63, %i2
63512
63513add %i3, 63, %i3
63514andn %i3, 63, %i3
63515
63516add %i4, 63, %i4
63517andn %i4, 63, %i4
63518
63519add %i5, 63, %i5
63520andn %i5, 63, %i5
63521
63522
63523! Initialize pointer to FP load results area
63524mov %i4, %l1
63525
63526! Initialize pointer to integer load results area
63527sethi %hi(0x80000), %o7
63528or %o7, %lo(0x80000), %o7
63529add %o7, %l1, %o7
63530
63531! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info
63532mov 0x0, %i4
63533
63534! Initialize %f0-%f62 to 0xdeadbee0deadbee1
63535sethi %hi(0xdeadbee0), %l3
63536or %l3, %lo(0xdeadbee0), %l3
63537stw %l3, [%i5]
63538sethi %hi(0xdeadbee1), %l3
63539or %l3, %lo(0xdeadbee1), %l3
63540stw %l3, [%i5+4]
63541ldd [%i5], %f0
63542fmovd %f0, %f2
63543fmovd %f0, %f4
63544fmovd %f0, %f6
63545fmovd %f0, %f8
63546fmovd %f0, %f10
63547fmovd %f0, %f12
63548fmovd %f0, %f14
63549fmovd %f0, %f16
63550fmovd %f0, %f18
63551fmovd %f0, %f20
63552fmovd %f0, %f22
63553fmovd %f0, %f24
63554fmovd %f0, %f26
63555fmovd %f0, %f28
63556fmovd %f0, %f30
63557fmovd %f0, %f32
63558fmovd %f0, %f34
63559fmovd %f0, %f36
63560fmovd %f0, %f38
63561fmovd %f0, %f40
63562fmovd %f0, %f42
63563fmovd %f0, %f44
63564fmovd %f0, %f46
63565fmovd %f0, %f48
63566fmovd %f0, %f50
63567fmovd %f0, %f52
63568fmovd %f0, %f54
63569fmovd %f0, %f56
63570fmovd %f0, %f58
63571fmovd %f0, %f60
63572fmovd %f0, %f62
63573
63574! Signature for extract_loads script to start extracting load values for this stream
63575sethi %hi(0x06deade1), %l3
63576or %l3, %lo(0x06deade1), %l3
63577stw %l3, [%i5]
63578ld [%i5], %f16
63579
63580! Initialize running integer counter in register %l4
63581sethi %hi(0x3000001), %l4
63582or %l4, %lo(0x3000001), %l4
63583
63584! Initialize running FP counter in register %f16
63585sethi %hi(0x42800001), %l3
63586or %l3, %lo(0x42800001), %l3
63587stw %l3, [%i5]
63588ld [%i5], %f16
63589
63590! Initialize FP counter increment value in register %f17 (constant)
63591sethi %hi(0x37000000), %l3
63592or %l3, %lo(0x37000000), %l3
63593stw %l3, [%i5]
63594ld [%i5], %f17
63595
63596! Initialize LFSR to 0xb2^4
63597sethi %hi(0xb2), %l0
63598or %l0, %lo(0xb2), %l0
63599mulx %l0, %l0, %l0
63600mulx %l0, %l0, %l0
63601
63602BEGIN_NODES6: ! Test instruction sequence for ISTREAM 6 begins
63603
63604P6015: !_CAS [6] (maybe <- 0x3000001) (Int) (Loop entry) (Branch target of P6310)
63605sethi %hi(0x1), %l2
63606or %l2, %lo(0x1), %l2
63607loop_entry_6_0:
63608sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
63609add %i0, %i2, %i2
63610lduw [%i2], %o0
63611mov %o0, %l6
63612! move %l6(lower) -> %o0(upper)
63613sllx %l6, 32, %o0
63614mov %l4, %l3
63615cas [%i2], %l6, %l3
63616! move %l3(lower) -> %o0(lower)
63617srl %l3, 0, %l6
63618or %l6, %o0, %o0
63619add %l4, 1, %l4
63620ba P6016
63621nop
63622
63623TARGET6310:
63624ba RET6310
63625nop
63626
63627
63628P6016: !_LDD [4] (Int)
63629ldd [%i1 + 0], %l6
63630! move %l6(lower) -> %o1(upper)
63631sllx %l6, 32, %o1
63632! move %l7(lower) -> %o1(lower)
63633or %l7, %o1, %o1
63634
63635P6017: !_DWST [17] (maybe <- 0x3000002) (Int)
63636sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
63637sub %i0, %i3, %i3
63638mov %l4, %l3
63639stx %l3, [%i3 + 8]
63640add %l4, 1, %l4
63641
63642P6018: !_SWAP [10] (maybe <- 0x3000003) (Int) (LE)
63643wr %g0, 0x88, %asi
63644sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
63645add %i0, %i2, %i2
63646mov %l4, %o2
63647! Change single-word-level endianess (big endian <-> little endian)
63648sethi %hi(0xff00ff00), %o5
63649or %o5, %lo(0xff00ff00), %o5
63650and %o2, %o5, %l3
63651srl %l3, 8, %l3
63652sll %o2, 8, %o2
63653and %o2, %o5, %o2
63654or %o2, %l3, %o2
63655srl %o2, 16, %l3
63656sll %o2, 16, %o2
63657srl %o2, 0, %o2
63658or %o2, %l3, %o2
63659swapa [%i2 + 4] %asi, %o2
63660! move %o2(lower) -> %o2(upper)
63661sllx %o2, 32, %o2
63662add %l4, 1, %l4
63663
63664P6019: !_DWST [3] (maybe <- 0x3000004) (Int)
63665sllx %l4, 32, %l7
63666add %l4, 1, %l4
63667or %l7, %l4, %l7
63668stx %l7, [%i1 + 0]
63669add %l4, 1, %l4
63670
63671P6020: !_CASX [4] (maybe <- 0x3000006) (Int)
63672ldx [%i1], %l3
63673! move %l3(upper) -> %o2(lower)
63674srlx %l3, 32, %l6
63675or %l6, %o2, %o2
63676! move %l3(lower) -> %o3(upper)
63677sllx %l3, 32, %o3
63678mov %l3, %l6
63679sllx %l4, 32, %l3
63680add %l4, 1, %l4
63681or %l4, %l3, %l3
63682casx [%i1], %l6, %l3
63683! move %l3(upper) -> %o3(lower)
63684srlx %l3, 32, %l6
63685or %l6, %o3, %o3
63686! move %l3(lower) -> %o4(upper)
63687sllx %l3, 32, %o4
63688add %l4, 1, %l4
63689
63690P6021: !_LD [11] (FP)
63691ld [%i2 + 12], %f0
63692! 1 addresses covered
63693
63694P6022: !_PREFETCH [0] (Int)
63695prefetch [%i0 + 0], 20
63696
63697P6023: !_DWLD [15] (Int) (LE)
63698wr %g0, 0x88, %asi
63699ldxa [%i3 + 0] %asi, %l7
63700! move %l7(lower) -> %o4(lower)
63701srl %l7, 0, %l6
63702or %l6, %o4, %o4
63703!---- flushing int results buffer----
63704mov %o0, %l5
63705mov %o1, %l5
63706mov %o2, %l5
63707mov %o3, %l5
63708mov %o4, %l5
63709! move %l7(upper) -> %o0(upper)
63710or %l7, %g0, %o0
63711
63712P6024: !_LD [16] (Int)
63713lduw [%i3 + 4], %l3
63714! move %l3(lower) -> %o0(lower)
63715srlx %o0, 32, %o0
63716sllx %o0, 32, %o0
63717or %l3, %o0, %o0
63718
63719P6025: !_LDD [3] (Int)
63720ldd [%i1 + 0], %l6
63721! move %l6(lower) -> %o1(upper)
63722sllx %l6, 32, %o1
63723! move %l7(lower) -> %o1(lower)
63724or %l7, %o1, %o1
63725
63726P6026: !_REPLACEMENT [17] (Int)
63727sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
63728sub %i0, %i3, %i3
63729sethi %hi(0x20000), %l3
63730ld [%i3+12], %l7
63731st %l7, [%i3+12]
63732add %i3, %l3, %l6
63733ld [%l6+12], %l7
63734st %l7, [%l6+12]
63735add %l6, %l3, %l6
63736ld [%l6+12], %l7
63737st %l7, [%l6+12]
63738add %l6, %l3, %l6
63739ld [%l6+12], %l7
63740st %l7, [%l6+12]
63741add %l6, %l3, %l6
63742ld [%l6+12], %l7
63743st %l7, [%l6+12]
63744add %l6, %l3, %l6
63745ld [%l6+12], %l7
63746st %l7, [%l6+12]
63747add %l6, %l3, %l6
63748ld [%l6+12], %l7
63749st %l7, [%l6+12]
63750add %l6, %l3, %l6
63751ld [%l6+12], %l7
63752st %l7, [%l6+12]
63753
63754P6027: !_LDD [6] (Int)
63755sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
63756add %i0, %i2, %i2
63757ldd [%i2 + 0], %l6
63758! move %l6(lower) -> %o2(upper)
63759sllx %l6, 32, %o2
63760! move %l7(lower) -> %o2(lower)
63761or %l7, %o2, %o2
63762
63763P6028: !_MEMBAR (FP)
63764
63765P6029: !_BST [8] (maybe <- 0x42800001) (FP)
63766wr %g0, 0xf0, %asi
63767! preparing store val #0, next val will be in f32
63768fmovs %f16, %f20
63769fadds %f16, %f17, %f16
63770! preparing store val #1, next val will be in f33
63771fmovs %f16, %f21
63772fadds %f16, %f17, %f16
63773! preparing store val #2, next val will be in f35
63774fmovd %f20, %f32
63775fmovs %f16, %f21
63776fadds %f16, %f17, %f16
63777fmovd %f20, %f34
63778membar #Sync
63779stda %f32, [%i2 + 0 ] %asi
63780
63781P6030: !_MEMBAR (FP)
63782membar #StoreLoad
63783
63784P6031: !_ST_BINIT [17] (maybe <- 0x3000008) (Int)
63785wr %g0, 0xe2, %asi
63786sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
63787sub %i0, %i3, %i3
63788stwa %l4, [%i3 + 12] %asi
63789add %l4, 1, %l4
63790
63791P6032: !_MEMBAR (Int)
63792
63793P6033: !_BST [19] (maybe <- 0x42800004) (FP)
63794wr %g0, 0xf0, %asi
63795sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
63796sub %i0, %i2, %i2
63797! preparing store val #0, next val will be in f32
63798fmovs %f16, %f20
63799fadds %f16, %f17, %f16
63800! preparing store val #1, next val will be in f33
63801fmovs %f16, %f21
63802fadds %f16, %f17, %f16
63803! preparing store val #2, next val will be in f35
63804fmovd %f20, %f32
63805fmovs %f16, %f21
63806fadds %f16, %f17, %f16
63807fmovd %f20, %f34
63808membar #Sync
63809stda %f32, [%i2 + 0 ] %asi
63810
63811P6034: !_MEMBAR (FP)
63812membar #StoreLoad
63813
63814P6035: !_DWST_BINIT [6] (maybe <- 0x3000009) (Int) (CBR) (Branch target of P6762)
63815wr %g0, 0xe2, %asi
63816sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
63817add %i0, %i3, %i3
63818sllx %l4, 32, %l6
63819add %l4, 1, %l4
63820or %l6, %l4, %l6
63821stxa %l6, [%i3 + 0] %asi
63822add %l4, 1, %l4
63823
63824! cbranch
63825andcc %l0, 1, %g0
63826be,pt %xcc, TARGET6035
63827nop
63828RET6035:
63829
63830! lfsr step begin
63831srlx %l0, 1, %l3
63832xnor %l3, %l0, %l3
63833sllx %l3, 63, %l3
63834or %l3, %l0, %l0
63835srlx %l0, 1, %l0
63836
63837ba P6036
63838nop
63839
63840TARGET6762:
63841ba RET6762
63842nop
63843
63844
63845P6036: !_MEMBAR (Int)
63846membar #StoreLoad
63847
63848P6037: !_SWAP [8] (maybe <- 0x300000b) (Int)
63849mov %l4, %o3
63850swap [%i3 + 12], %o3
63851! move %o3(lower) -> %o3(upper)
63852sllx %o3, 32, %o3
63853add %l4, 1, %l4
63854
63855P6038: !_SWAP [0] (maybe <- 0x300000c) (Int)
63856mov %l4, %l7
63857swap [%i0 + 0], %l7
63858! move %l7(lower) -> %o3(lower)
63859srl %l7, 0, %l3
63860or %l3, %o3, %o3
63861add %l4, 1, %l4
63862
63863P6039: !_ST_BINIT [4] (maybe <- 0x300000d) (Int)
63864wr %g0, 0xe2, %asi
63865stwa %l4, [%i1 + 4] %asi
63866add %l4, 1, %l4
63867
63868P6040: !_MEMBAR (Int)
63869
63870P6041: !_BSTC [7] (maybe <- 0x42800007) (FP) (Branch target of P6421)
63871wr %g0, 0xe0, %asi
63872! preparing store val #0, next val will be in f32
63873fmovs %f16, %f20
63874fadds %f16, %f17, %f16
63875! preparing store val #1, next val will be in f33
63876fmovs %f16, %f21
63877fadds %f16, %f17, %f16
63878! preparing store val #2, next val will be in f35
63879fmovd %f20, %f32
63880fmovs %f16, %f21
63881fadds %f16, %f17, %f16
63882fmovd %f20, %f34
63883membar #Sync
63884stda %f32, [%i3 + 0 ] %asi
63885ba P6042
63886nop
63887
63888TARGET6421:
63889ba RET6421
63890nop
63891
63892
63893P6042: !_MEMBAR (FP)
63894membar #StoreLoad
63895
63896P6043: !_ST_BINIT [16] (maybe <- 0x300000e) (Int)
63897wr %g0, 0xe2, %asi
63898sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
63899sub %i0, %i2, %i2
63900stwa %l4, [%i2 + 4] %asi
63901add %l4, 1, %l4
63902
63903P6044: !_MEMBAR (Int)
63904membar #StoreLoad
63905
63906P6045: !_LD [2] (Int)
63907lduw [%i0 + 12], %o4
63908! move %o4(lower) -> %o4(upper)
63909sllx %o4, 32, %o4
63910
63911P6046: !_SWAP [3] (maybe <- 0x300000f) (Int) (CBR)
63912mov %l4, %l3
63913swap [%i1 + 0], %l3
63914! move %l3(lower) -> %o4(lower)
63915srl %l3, 0, %l7
63916or %l7, %o4, %o4
63917!---- flushing int results buffer----
63918mov %o0, %l5
63919mov %o1, %l5
63920mov %o2, %l5
63921mov %o3, %l5
63922mov %o4, %l5
63923add %l4, 1, %l4
63924
63925! cbranch
63926andcc %l0, 1, %g0
63927be,pn %xcc, TARGET6046
63928nop
63929RET6046:
63930
63931! lfsr step begin
63932srlx %l0, 1, %l6
63933xnor %l6, %l0, %l6
63934sllx %l6, 63, %l6
63935or %l6, %l0, %l0
63936srlx %l0, 1, %l0
63937
63938
63939P6047: !_LDD [8] (Int)
63940ldd [%i3 + 8], %l6
63941! move %l7(lower) -> %o0(upper)
63942sllx %l7, 32, %o0
63943
63944P6048: !_ST [13] (maybe <- 0x3000010) (Int)
63945sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
63946sub %i0, %i3, %i3
63947stw %l4, [%i3 + 4 ]
63948add %l4, 1, %l4
63949
63950P6049: !_DWST_BINIT [3] (maybe <- 0x3000011) (Int) (Branch target of P6172)
63951wr %g0, 0xe2, %asi
63952sllx %l4, 32, %o5
63953add %l4, 1, %l4
63954or %o5, %l4, %o5
63955stxa %o5, [%i1 + 0] %asi
63956add %l4, 1, %l4
63957ba P6050
63958nop
63959
63960TARGET6172:
63961ba RET6172
63962nop
63963
63964
63965P6050: !_MEMBAR (Int) (CBR)
63966membar #StoreLoad
63967
63968! cbranch
63969andcc %l0, 1, %g0
63970be,pt %xcc, TARGET6050
63971nop
63972RET6050:
63973
63974! lfsr step begin
63975srlx %l0, 1, %l7
63976xnor %l7, %l0, %l7
63977sllx %l7, 63, %l7
63978or %l7, %l0, %l0
63979srlx %l0, 1, %l0
63980
63981
63982P6051: !_SWAP [14] (maybe <- 0x3000013) (Int)
63983mov %l4, %l6
63984swap [%i3 + 12], %l6
63985! move %l6(lower) -> %o0(lower)
63986srl %l6, 0, %o5
63987or %o5, %o0, %o0
63988add %l4, 1, %l4
63989
63990P6052: !_MEMBAR (FP) (CBR)
63991membar #StoreLoad
63992
63993! cbranch
63994andcc %l0, 1, %g0
63995be,pn %xcc, TARGET6052
63996nop
63997RET6052:
63998
63999! lfsr step begin
64000srlx %l0, 1, %l7
64001xnor %l7, %l0, %l7
64002sllx %l7, 63, %l7
64003or %l7, %l0, %l0
64004srlx %l0, 1, %l0
64005
64006
64007P6053: !_BLD [2] (FP)
64008wr %g0, 0xf0, %asi
64009ldda [%i0 + 0] %asi, %f32
64010membar #Sync
64011! 3 addresses covered
64012fmovd %f32, %f18
64013fmovs %f18, %f1
64014fmovs %f19, %f2
64015fmovd %f34, %f18
64016fmovs %f19, %f3
64017
64018P6054: !_MEMBAR (FP)
64019
64020P6055: !_LDD [8] (Int) (LE)
64021wr %g0, 0x88, %asi
64022sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
64023add %i0, %i2, %i2
64024ldda [%i2 + 8] %asi, %l6
64025! move %l7(lower) -> %o1(upper)
64026sllx %l7, 32, %o1
64027
64028P6056: !_ST [18] (maybe <- 0x3000014) (Int) (LE)
64029wr %g0, 0x88, %asi
64030sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
64031sub %i0, %i3, %i3
64032! Change single-word-level endianess (big endian <-> little endian)
64033sethi %hi(0xff00ff00), %l6
64034or %l6, %lo(0xff00ff00), %l6
64035and %l4, %l6, %l7
64036srl %l7, 8, %l7
64037sll %l4, 8, %l3
64038and %l3, %l6, %l3
64039or %l3, %l7, %l3
64040srl %l3, 16, %l7
64041sll %l3, 16, %l3
64042srl %l3, 0, %l3
64043or %l3, %l7, %l3
64044stwa %l3, [%i3 + 0] %asi
64045add %l4, 1, %l4
64046
64047P6057: !_SWAP [12] (maybe <- 0x3000015) (Int)
64048sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
64049sub %i0, %i2, %i2
64050mov %l4, %l6
64051swap [%i2 + 0], %l6
64052! move %l6(lower) -> %o1(lower)
64053srl %l6, 0, %o5
64054or %o5, %o1, %o1
64055add %l4, 1, %l4
64056
64057P6058: !_SWAP [19] (maybe <- 0x3000016) (Int) (Branch target of P6183)
64058mov %l4, %o2
64059swap [%i3 + 4], %o2
64060! move %o2(lower) -> %o2(upper)
64061sllx %o2, 32, %o2
64062add %l4, 1, %l4
64063ba P6059
64064nop
64065
64066TARGET6183:
64067ba RET6183
64068nop
64069
64070
64071P6059: !_SWAP [3] (maybe <- 0x3000017) (Int)
64072mov %l4, %o5
64073swap [%i1 + 0], %o5
64074! move %o5(lower) -> %o2(lower)
64075srl %o5, 0, %l6
64076or %l6, %o2, %o2
64077add %l4, 1, %l4
64078
64079P6060: !_ST_BINIT [17] (maybe <- 0x3000018) (Int)
64080wr %g0, 0xe2, %asi
64081sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
64082sub %i0, %i3, %i3
64083stwa %l4, [%i3 + 12] %asi
64084add %l4, 1, %l4
64085
64086P6061: !_MEMBAR (Int)
64087membar #StoreLoad
64088
64089P6062: !_BLD [2] (FP) (CBR)
64090wr %g0, 0xf0, %asi
64091ldda [%i0 + 0] %asi, %f32
64092membar #Sync
64093! 3 addresses covered
64094fmovd %f32, %f4
64095fmovd %f34, %f18
64096fmovs %f19, %f6
64097
64098! cbranch
64099andcc %l0, 1, %g0
64100be,pn %xcc, TARGET6062
64101nop
64102RET6062:
64103
64104! lfsr step begin
64105srlx %l0, 1, %o5
64106xnor %o5, %l0, %o5
64107sllx %o5, 63, %o5
64108or %o5, %l0, %l0
64109srlx %l0, 1, %l0
64110
64111
64112P6063: !_MEMBAR (FP)
64113
64114P6064: !_LD [1] (Int) (CBR)
64115lduw [%i0 + 4], %o3
64116! move %o3(lower) -> %o3(upper)
64117sllx %o3, 32, %o3
64118
64119! cbranch
64120andcc %l0, 1, %g0
64121be,pt %xcc, TARGET6064
64122nop
64123RET6064:
64124
64125! lfsr step begin
64126srlx %l0, 1, %l7
64127xnor %l7, %l0, %l7
64128sllx %l7, 63, %l7
64129or %l7, %l0, %l0
64130srlx %l0, 1, %l0
64131
64132
64133P6065: !_LDD [14] (Int)
64134ldd [%i2 + 8], %l6
64135! move %l7(lower) -> %o3(lower)
64136or %l7, %o3, %o3
64137
64138P6066: !_DWLD [1] (Int)
64139ldx [%i0 + 0], %o4
64140! move %o4(upper) -> %o4(upper)
64141! move %o4(lower) -> %o4(lower)
64142!---- flushing int results buffer----
64143mov %o0, %l5
64144mov %o1, %l5
64145mov %o2, %l5
64146mov %o3, %l5
64147mov %o4, %l5
64148
64149P6067: !_DWST [2] (maybe <- 0x3000019) (Int) (LE)
64150wr %g0, 0x88, %asi
64151! Change single-word-level endianess (big endian <-> little endian)
64152sethi %hi(0xff00ff00), %l7
64153or %l7, %lo(0xff00ff00), %l7
64154and %l4, %l7, %l3
64155srl %l3, 8, %l3
64156sll %l4, 8, %o5
64157and %o5, %l7, %o5
64158or %o5, %l3, %o5
64159srl %o5, 16, %l3
64160sll %o5, 16, %o5
64161srl %o5, 0, %o5
64162or %o5, %l3, %o5
64163sllx %o5, 32, %o5
64164stxa %o5, [%i0 + 8 ] %asi
64165add %l4, 1, %l4
64166
64167P6068: !_MEMBAR (FP)
64168
64169P6069: !_BSTC [5] (maybe <- 0x4280000a) (FP) (CBR)
64170wr %g0, 0xe0, %asi
64171! preparing store val #0, next val will be in f32
64172fmovs %f16, %f20
64173fadds %f16, %f17, %f16
64174! preparing store val #1, next val will be in f33
64175fmovs %f16, %f21
64176fadds %f16, %f17, %f16
64177! preparing store val #2, next val will be in f35
64178fmovd %f20, %f32
64179fmovs %f16, %f21
64180fadds %f16, %f17, %f16
64181fmovd %f20, %f34
64182membar #Sync
64183stda %f32, [%i1 + 0 ] %asi
64184
64185! cbranch
64186andcc %l0, 1, %g0
64187be,pn %xcc, TARGET6069
64188nop
64189RET6069:
64190
64191! lfsr step begin
64192srlx %l0, 1, %l3
64193xnor %l3, %l0, %l3
64194sllx %l3, 63, %l3
64195or %l3, %l0, %l0
64196srlx %l0, 1, %l0
64197
64198
64199P6070: !_MEMBAR (FP)
64200membar #StoreLoad
64201
64202P6071: !_DWST [14] (maybe <- 0x300001a) (Int)
64203mov %l4, %l6
64204stx %l6, [%i2 + 8]
64205add %l4, 1, %l4
64206
64207P6072: !_DWST [2] (maybe <- 0x300001b) (Int)
64208mov %l4, %l3
64209stx %l3, [%i0 + 8]
64210add %l4, 1, %l4
64211
64212P6073: !_DWST_BINIT [21] (maybe <- 0x300001c) (Int)
64213wr %g0, 0xe2, %asi
64214sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
64215add %i0, %i2, %i2
64216sllx %l4, 32, %o5
64217add %l4, 1, %l4
64218or %o5, %l4, %o5
64219stxa %o5, [%i2 + 0] %asi
64220add %l4, 1, %l4
64221
64222P6074: !_MEMBAR (Int)
64223membar #StoreLoad
64224
64225P6075: !_ST_BINIT [22] (maybe <- 0x300001e) (Int) (CBR)
64226wr %g0, 0xe2, %asi
64227stwa %l4, [%i2 + 4] %asi
64228add %l4, 1, %l4
64229
64230! cbranch
64231andcc %l0, 1, %g0
64232be,pt %xcc, TARGET6075
64233nop
64234RET6075:
64235
64236! lfsr step begin
64237srlx %l0, 1, %l6
64238xnor %l6, %l0, %l6
64239sllx %l6, 63, %l6
64240or %l6, %l0, %l0
64241srlx %l0, 1, %l0
64242
64243
64244P6076: !_MEMBAR (Int) (CBR)
64245membar #StoreLoad
64246
64247! cbranch
64248andcc %l0, 1, %g0
64249be,pt %xcc, TARGET6076
64250nop
64251RET6076:
64252
64253! lfsr step begin
64254srlx %l0, 1, %l7
64255xnor %l7, %l0, %l7
64256sllx %l7, 63, %l7
64257or %l7, %l0, %l0
64258srlx %l0, 1, %l0
64259
64260
64261P6077: !_PREFETCH [5] (Int)
64262prefetch [%i1 + 12], 21
64263
64264P6078: !_MEMBAR (FP)
64265membar #StoreLoad
64266
64267P6079: !_BLD [13] (FP)
64268wr %g0, 0xf0, %asi
64269sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
64270sub %i0, %i3, %i3
64271ldda [%i3 + 0] %asi, %f32
64272membar #Sync
64273! 3 addresses covered
64274fmovd %f32, %f18
64275fmovs %f18, %f7
64276fmovs %f19, %f8
64277fmovd %f34, %f18
64278fmovs %f19, %f9
64279
64280P6080: !_MEMBAR (FP) (Branch target of P6466)
64281ba P6081
64282nop
64283
64284TARGET6466:
64285ba RET6466
64286nop
64287
64288
64289P6081: !_ST_BINIT [22] (maybe <- 0x300001f) (Int)
64290wr %g0, 0xe2, %asi
64291stwa %l4, [%i2 + 4] %asi
64292add %l4, 1, %l4
64293
64294P6082: !_MEMBAR (Int)
64295membar #StoreLoad
64296
64297P6083: !_DWLD [13] (Int)
64298ldx [%i3 + 0], %o0
64299! move %o0(upper) -> %o0(upper)
64300! move %o0(lower) -> %o0(lower)
64301
64302P6084: !_ST [21] (maybe <- 0x3000020) (Int) (LE)
64303wr %g0, 0x88, %asi
64304! Change single-word-level endianess (big endian <-> little endian)
64305sethi %hi(0xff00ff00), %l7
64306or %l7, %lo(0xff00ff00), %l7
64307and %l4, %l7, %o5
64308srl %o5, 8, %o5
64309sll %l4, 8, %l6
64310and %l6, %l7, %l6
64311or %l6, %o5, %l6
64312srl %l6, 16, %o5
64313sll %l6, 16, %l6
64314srl %l6, 0, %l6
64315or %l6, %o5, %l6
64316stwa %l6, [%i2 + 0] %asi
64317add %l4, 1, %l4
64318
64319P6085: !_MEMBAR (FP) (Branch target of P6222)
64320membar #StoreLoad
64321ba P6086
64322nop
64323
64324TARGET6222:
64325ba RET6222
64326nop
64327
64328
64329P6086: !_BLD [9] (FP)
64330wr %g0, 0xf0, %asi
64331sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
64332add %i0, %i2, %i2
64333ldda [%i2 + 0] %asi, %f32
64334membar #Sync
64335! 3 addresses covered
64336fmovd %f32, %f10
64337fmovd %f34, %f18
64338fmovs %f19, %f12
64339
64340P6087: !_MEMBAR (FP)
64341
64342P6088: !_DWST_BINIT [17] (maybe <- 0x3000021) (Int)
64343wr %g0, 0xe2, %asi
64344sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
64345sub %i0, %i3, %i3
64346mov %l4, %l3
64347stxa %l3, [%i3 + 8] %asi
64348add %l4, 1, %l4
64349
64350P6089: !_MEMBAR (Int)
64351membar #StoreLoad
64352
64353P6090: !_ST [23] (maybe <- 0x4280000d) (FP)
64354sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
64355add %i0, %i2, %i2
64356! preparing store val #0, next val will be in f20
64357fmovs %f16, %f20
64358fadds %f16, %f17, %f16
64359st %f20, [%i2 + 12 ]
64360
64361P6091: !_REPLACEMENT [9] (Int)
64362sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
64363sub %i0, %i3, %i3
64364sethi %hi(0x20000), %l7
64365ld [%i3+0], %l3
64366st %l3, [%i3+0]
64367add %i3, %l7, %o5
64368ld [%o5+0], %l3
64369st %l3, [%o5+0]
64370add %o5, %l7, %o5
64371ld [%o5+0], %l3
64372st %l3, [%o5+0]
64373add %o5, %l7, %o5
64374ld [%o5+0], %l3
64375st %l3, [%o5+0]
64376add %o5, %l7, %o5
64377ld [%o5+0], %l3
64378st %l3, [%o5+0]
64379add %o5, %l7, %o5
64380ld [%o5+0], %l3
64381st %l3, [%o5+0]
64382add %o5, %l7, %o5
64383ld [%o5+0], %l3
64384st %l3, [%o5+0]
64385add %o5, %l7, %o5
64386ld [%o5+0], %l3
64387st %l3, [%o5+0]
64388
64389P6092: !_MEMBAR (FP)
64390membar #StoreLoad
64391
64392P6093: !_BLD [17] (FP)
64393wr %g0, 0xf0, %asi
64394sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
64395sub %i0, %i2, %i2
64396ldda [%i2 + 0] %asi, %f32
64397membar #Sync
64398! 3 addresses covered
64399fmovd %f32, %f18
64400fmovs %f18, %f13
64401fmovs %f19, %f14
64402fmovd %f34, %f18
64403fmovs %f19, %f15
64404!---- flushing fp results buffer to %f30 ----
64405fmovd %f0, %f30
64406fmovd %f2, %f30
64407fmovd %f4, %f30
64408fmovd %f6, %f30
64409fmovd %f8, %f30
64410fmovd %f10, %f30
64411fmovd %f12, %f30
64412fmovd %f14, %f30
64413!--
64414
64415P6094: !_MEMBAR (FP)
64416
64417P6095: !_PREFETCH [21] (Int)
64418sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
64419add %i0, %i3, %i3
64420prefetch [%i3 + 0], 24
64421
64422P6096: !_SWAP [14] (maybe <- 0x3000022) (Int)
64423sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
64424sub %i0, %i2, %i2
64425mov %l4, %o1
64426swap [%i2 + 12], %o1
64427! move %o1(lower) -> %o1(upper)
64428sllx %o1, 32, %o1
64429add %l4, 1, %l4
64430
64431P6097: !_LD [9] (FP)
64432sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
64433add %i0, %i3, %i3
64434ld [%i3 + 0], %f0
64435! 1 addresses covered
64436
64437P6098: !_ST_BINIT [8] (maybe <- 0x3000023) (Int)
64438wr %g0, 0xe2, %asi
64439sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
64440add %i0, %i2, %i2
64441stwa %l4, [%i2 + 12] %asi
64442add %l4, 1, %l4
64443
64444P6099: !_MEMBAR (Int)
64445membar #StoreLoad
64446
64447P6100: !_DWST_BINIT [1] (maybe <- 0x3000024) (Int)
64448wr %g0, 0xe2, %asi
64449sllx %l4, 32, %o5
64450add %l4, 1, %l4
64451or %o5, %l4, %o5
64452stxa %o5, [%i0 + 0] %asi
64453add %l4, 1, %l4
64454
64455P6101: !_MEMBAR (Int)
64456membar #StoreLoad
64457
64458P6102: !_LD [11] (Int) (CBR)
64459lduw [%i3 + 12], %o5
64460! move %o5(lower) -> %o1(lower)
64461or %o5, %o1, %o1
64462
64463! cbranch
64464andcc %l0, 1, %g0
64465be,pt %xcc, TARGET6102
64466nop
64467RET6102:
64468
64469! lfsr step begin
64470srlx %l0, 1, %l3
64471xnor %l3, %l0, %l3
64472sllx %l3, 63, %l3
64473or %l3, %l0, %l0
64474srlx %l0, 1, %l0
64475
64476
64477P6103: !_LDD [22] (Int)
64478sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
64479add %i0, %i3, %i3
64480ldd [%i3 + 0], %l6
64481! move %l6(lower) -> %o2(upper)
64482sllx %l6, 32, %o2
64483! move %l7(lower) -> %o2(lower)
64484or %l7, %o2, %o2
64485
64486P6104: !_SWAP [12] (maybe <- 0x3000026) (Int)
64487sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
64488sub %i0, %i2, %i2
64489mov %l4, %o3
64490swap [%i2 + 0], %o3
64491! move %o3(lower) -> %o3(upper)
64492sllx %o3, 32, %o3
64493add %l4, 1, %l4
64494
64495P6105: !_DWST [2] (maybe <- 0x3000027) (Int)
64496mov %l4, %o5
64497stx %o5, [%i0 + 8]
64498add %l4, 1, %l4
64499
64500P6106: !_MEMBAR (FP)
64501
64502P6107: !_BST [7] (maybe <- 0x4280000e) (FP)
64503wr %g0, 0xf0, %asi
64504sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
64505add %i0, %i3, %i3
64506! preparing store val #0, next val will be in f32
64507fmovs %f16, %f20
64508fadds %f16, %f17, %f16
64509! preparing store val #1, next val will be in f33
64510fmovs %f16, %f21
64511fadds %f16, %f17, %f16
64512! preparing store val #2, next val will be in f35
64513fmovd %f20, %f32
64514fmovs %f16, %f21
64515fadds %f16, %f17, %f16
64516fmovd %f20, %f34
64517membar #Sync
64518stda %f32, [%i3 + 0 ] %asi
64519
64520P6108: !_MEMBAR (FP)
64521membar #StoreLoad
64522
64523P6109: !_BLD [13] (FP)
64524wr %g0, 0xf0, %asi
64525ldda [%i2 + 0] %asi, %f32
64526membar #Sync
64527! 3 addresses covered
64528fmovd %f32, %f18
64529fmovs %f18, %f1
64530fmovs %f19, %f2
64531fmovd %f34, %f18
64532fmovs %f19, %f3
64533
64534P6110: !_MEMBAR (FP)
64535
64536P6111: !_DWST [19] (maybe <- 0x3000028) (Int)
64537sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
64538sub %i0, %i2, %i2
64539sllx %l4, 32, %l6
64540add %l4, 1, %l4
64541or %l6, %l4, %l6
64542stx %l6, [%i2 + 0]
64543add %l4, 1, %l4
64544
64545P6112: !_DWST [3] (maybe <- 0x300002a) (Int) (Branch target of P6593)
64546sllx %l4, 32, %l3
64547add %l4, 1, %l4
64548or %l3, %l4, %l3
64549stx %l3, [%i1 + 0]
64550add %l4, 1, %l4
64551ba P6113
64552nop
64553
64554TARGET6593:
64555ba RET6593
64556nop
64557
64558
64559P6113: !_SWAP [8] (maybe <- 0x300002c) (Int)
64560mov %l4, %l6
64561swap [%i3 + 12], %l6
64562! move %l6(lower) -> %o3(lower)
64563srl %l6, 0, %o5
64564or %o5, %o3, %o3
64565add %l4, 1, %l4
64566
64567P6114: !_DWST_BINIT [14] (maybe <- 0x300002d) (Int)
64568wr %g0, 0xe2, %asi
64569sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
64570sub %i0, %i3, %i3
64571mov %l4, %l7
64572stxa %l7, [%i3 + 8] %asi
64573add %l4, 1, %l4
64574
64575P6115: !_MEMBAR (Int)
64576membar #StoreLoad
64577
64578P6116: !_DWST_BINIT [20] (maybe <- 0x300002e) (Int) (CBR)
64579wr %g0, 0xe2, %asi
64580mov %l4, %l6
64581stxa %l6, [%i2 + 8] %asi
64582add %l4, 1, %l4
64583
64584! cbranch
64585andcc %l0, 1, %g0
64586be,pt %xcc, TARGET6116
64587nop
64588RET6116:
64589
64590! lfsr step begin
64591srlx %l0, 1, %l3
64592xnor %l3, %l0, %l3
64593sllx %l3, 63, %l3
64594or %l3, %l0, %l0
64595srlx %l0, 1, %l0
64596
64597
64598P6117: !_MEMBAR (Int)
64599
64600P6118: !_BST [6] (maybe <- 0x42800011) (FP)
64601wr %g0, 0xf0, %asi
64602sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
64603add %i0, %i2, %i2
64604! preparing store val #0, next val will be in f32
64605fmovs %f16, %f20
64606fadds %f16, %f17, %f16
64607! preparing store val #1, next val will be in f33
64608fmovs %f16, %f21
64609fadds %f16, %f17, %f16
64610! preparing store val #2, next val will be in f35
64611fmovd %f20, %f32
64612fmovs %f16, %f21
64613fadds %f16, %f17, %f16
64614fmovd %f20, %f34
64615membar #Sync
64616stda %f32, [%i2 + 0 ] %asi
64617
64618P6119: !_MEMBAR (FP)
64619membar #StoreLoad
64620
64621P6120: !_DWLD [7] (Int)
64622ldx [%i2 + 0], %o4
64623! move %o4(upper) -> %o4(upper)
64624! move %o4(lower) -> %o4(lower)
64625!---- flushing int results buffer----
64626mov %o0, %l5
64627mov %o1, %l5
64628mov %o2, %l5
64629mov %o3, %l5
64630mov %o4, %l5
64631
64632P6121: !_DWST_BINIT [4] (maybe <- 0x300002f) (Int)
64633wr %g0, 0xe2, %asi
64634sllx %l4, 32, %l7
64635add %l4, 1, %l4
64636or %l7, %l4, %l7
64637stxa %l7, [%i1 + 0] %asi
64638add %l4, 1, %l4
64639
64640P6122: !_MEMBAR (Int)
64641membar #StoreLoad
64642
64643P6123: !_ST_BINIT [0] (maybe <- 0x3000031) (Int)
64644wr %g0, 0xe2, %asi
64645stwa %l4, [%i0 + 0] %asi
64646add %l4, 1, %l4
64647
64648P6124: !_MEMBAR (Int)
64649membar #StoreLoad
64650
64651P6125: !_LDD [6] (Int)
64652ldd [%i2 + 0], %l6
64653! move %l6(lower) -> %o0(upper)
64654sllx %l6, 32, %o0
64655! move %l7(lower) -> %o0(lower)
64656or %l7, %o0, %o0
64657
64658P6126: !_MEMBAR (FP)
64659
64660P6127: !_BSTC [11] (maybe <- 0x42800014) (FP)
64661wr %g0, 0xe0, %asi
64662sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
64663add %i0, %i3, %i3
64664! preparing store val #0, next val will be in f32
64665fmovs %f16, %f20
64666fadds %f16, %f17, %f16
64667! preparing store val #1, next val will be in f33
64668fmovs %f16, %f21
64669fadds %f16, %f17, %f16
64670! preparing store val #2, next val will be in f35
64671fmovd %f20, %f32
64672fmovs %f16, %f21
64673fadds %f16, %f17, %f16
64674fmovd %f20, %f34
64675membar #Sync
64676stda %f32, [%i3 + 0 ] %asi
64677
64678P6128: !_MEMBAR (FP)
64679membar #StoreLoad
64680
64681P6129: !_LDD [4] (Int) (CBR) (Branch target of P6116)
64682ldd [%i1 + 0], %l6
64683! move %l6(lower) -> %o1(upper)
64684sllx %l6, 32, %o1
64685! move %l7(lower) -> %o1(lower)
64686or %l7, %o1, %o1
64687
64688! cbranch
64689andcc %l0, 1, %g0
64690be,pn %xcc, TARGET6129
64691nop
64692RET6129:
64693
64694! lfsr step begin
64695srlx %l0, 1, %l3
64696xnor %l3, %l0, %l3
64697sllx %l3, 63, %l3
64698or %l3, %l0, %l0
64699srlx %l0, 1, %l0
64700
64701ba P6130
64702nop
64703
64704TARGET6116:
64705ba RET6116
64706nop
64707
64708
64709P6130: !_MEMBAR (FP)
64710
64711P6131: !_BST [22] (maybe <- 0x42800017) (FP)
64712wr %g0, 0xf0, %asi
64713sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
64714add %i0, %i2, %i2
64715! preparing store val #0, next val will be in f32
64716fmovs %f16, %f20
64717fadds %f16, %f17, %f16
64718! preparing store val #1, next val will be in f33
64719fmovs %f16, %f21
64720fadds %f16, %f17, %f16
64721! preparing store val #2, next val will be in f35
64722fmovd %f20, %f32
64723fmovs %f16, %f21
64724fadds %f16, %f17, %f16
64725fmovd %f20, %f34
64726membar #Sync
64727stda %f32, [%i2 + 0 ] %asi
64728
64729P6132: !_MEMBAR (FP)
64730membar #StoreLoad
64731
64732P6133: !_CAS [18] (maybe <- 0x3000032) (Int)
64733sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
64734sub %i0, %i3, %i3
64735lduw [%i3], %o2
64736mov %o2, %l3
64737! move %l3(lower) -> %o2(upper)
64738sllx %l3, 32, %o2
64739mov %l4, %o5
64740cas [%i3], %l3, %o5
64741! move %o5(lower) -> %o2(lower)
64742srl %o5, 0, %l3
64743or %l3, %o2, %o2
64744add %l4, 1, %l4
64745
64746P6134: !_ST_BINIT [2] (maybe <- 0x3000033) (Int)
64747wr %g0, 0xe2, %asi
64748stwa %l4, [%i0 + 12] %asi
64749add %l4, 1, %l4
64750
64751P6135: !_MEMBAR (Int)
64752membar #StoreLoad
64753
64754P6136: !_CAS [13] (maybe <- 0x3000034) (Int)
64755sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
64756sub %i0, %i2, %i2
64757add %i2, 4, %l3
64758lduw [%l3], %o3
64759mov %o3, %o5
64760! move %o5(lower) -> %o3(upper)
64761sllx %o5, 32, %o3
64762mov %l4, %l7
64763cas [%l3], %o5, %l7
64764! move %l7(lower) -> %o3(lower)
64765srl %l7, 0, %o5
64766or %o5, %o3, %o3
64767add %l4, 1, %l4
64768
64769P6137: !_LDD [0] (Int)
64770ldd [%i0 + 0], %l6
64771! move %l6(lower) -> %o4(upper)
64772sllx %l6, 32, %o4
64773! move %l7(lower) -> %o4(lower)
64774or %l7, %o4, %o4
64775!---- flushing int results buffer----
64776mov %o0, %l5
64777mov %o1, %l5
64778mov %o2, %l5
64779mov %o3, %l5
64780mov %o4, %l5
64781
64782P6138: !_DWST [23] (maybe <- 0x3000035) (Int) (LE)
64783wr %g0, 0x88, %asi
64784sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
64785add %i0, %i3, %i3
64786! Change single-word-level endianess (big endian <-> little endian)
64787sethi %hi(0xff00ff00), %l3
64788or %l3, %lo(0xff00ff00), %l3
64789and %l4, %l3, %l7
64790srl %l7, 8, %l7
64791sll %l4, 8, %l6
64792and %l6, %l3, %l6
64793or %l6, %l7, %l6
64794srl %l6, 16, %l7
64795sll %l6, 16, %l6
64796srl %l6, 0, %l6
64797or %l6, %l7, %l6
64798sllx %l6, 32, %l6
64799stxa %l6, [%i3 + 8 ] %asi
64800add %l4, 1, %l4
64801
64802P6139: !_DWST [1] (maybe <- 0x3000036) (Int)
64803sllx %l4, 32, %o5
64804add %l4, 1, %l4
64805or %o5, %l4, %o5
64806stx %o5, [%i0 + 0]
64807add %l4, 1, %l4
64808
64809P6140: !_DWST_BINIT [1] (maybe <- 0x3000038) (Int)
64810wr %g0, 0xe2, %asi
64811sllx %l4, 32, %l7
64812add %l4, 1, %l4
64813or %l7, %l4, %l7
64814stxa %l7, [%i0 + 0] %asi
64815add %l4, 1, %l4
64816
64817P6141: !_MEMBAR (Int)
64818membar #StoreLoad
64819
64820P6142: !_BLD [3] (FP)
64821!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
64822!Logical addr: 3
64823
64824sethi %hi(0x200000), %l6
64825sub %i1, %l6, %i1
64826wr %g0, 0xf0, %asi
64827ldda [%i1 + 0] %asi, %f32
64828membar #Sync
64829! 3 addresses covered
64830fmovd %f32, %f4
64831fmovd %f34, %f18
64832fmovs %f19, %f6
64833
64834P6143: !_MEMBAR (FP)
64835
64836P6144: !_DWST_BINIT [15] (maybe <- 0x300003a) (Int)
64837wr %g0, 0xe2, %asi
64838sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
64839sub %i0, %i2, %i2
64840sllx %l4, 32, %l7
64841add %l4, 1, %l4
64842or %l7, %l4, %l7
64843stxa %l7, [%i2 + 0] %asi
64844add %l4, 1, %l4
64845
64846P6145: !_MEMBAR (Int)
64847membar #StoreLoad
64848
64849P6146: !_PREFETCH [16] (Int)
64850prefetch [%i2 + 4], 4
64851
64852P6147: !_MEMBAR (FP)
64853
64854P6148: !_BSTC [14] (maybe <- 0x4280001a) (FP) (Branch target of P6460)
64855wr %g0, 0xe0, %asi
64856sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
64857sub %i0, %i3, %i3
64858! preparing store val #0, next val will be in f32
64859fmovs %f16, %f20
64860fadds %f16, %f17, %f16
64861! preparing store val #1, next val will be in f33
64862fmovs %f16, %f21
64863fadds %f16, %f17, %f16
64864! preparing store val #2, next val will be in f35
64865fmovd %f20, %f32
64866fmovs %f16, %f21
64867fadds %f16, %f17, %f16
64868fmovd %f20, %f34
64869membar #Sync
64870stda %f32, [%i3 + 0 ] %asi
64871ba P6149
64872nop
64873
64874TARGET6460:
64875ba RET6460
64876nop
64877
64878
64879P6149: !_MEMBAR (FP) (Branch target of P6721)
64880membar #StoreLoad
64881ba P6150
64882nop
64883
64884TARGET6721:
64885ba RET6721
64886nop
64887
64888
64889P6150: !_CASX [11] (maybe <- 0x300003c) (Int)
64890sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
64891add %i0, %i2, %i2
64892add %i2, 8, %l6
64893ldx [%l6], %o0
64894! move %o0(upper) -> %o0(upper)
64895! move %o0(lower) -> %o0(lower)
64896mov %o0, %l3
64897mov %l4, %o1
64898casx [%l6], %l3, %o1
64899! move %o1(upper) -> %o1(upper)
64900! move %o1(lower) -> %o1(lower)
64901add %l4, 1, %l4
64902
64903P6151: !_CAS [16] (maybe <- 0x300003d) (Int)
64904sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
64905sub %i0, %i3, %i3
64906add %i3, 4, %l6
64907lduw [%l6], %o2
64908mov %o2, %l3
64909! move %l3(lower) -> %o2(upper)
64910sllx %l3, 32, %o2
64911mov %l4, %o5
64912cas [%l6], %l3, %o5
64913! move %o5(lower) -> %o2(lower)
64914srl %o5, 0, %l3
64915or %l3, %o2, %o2
64916add %l4, 1, %l4
64917
64918P6152: !_ST_BINIT [7] (maybe <- 0x300003e) (Int)
64919wr %g0, 0xe2, %asi
64920sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
64921add %i0, %i2, %i2
64922stwa %l4, [%i2 + 4] %asi
64923add %l4, 1, %l4
64924
64925P6153: !_MEMBAR (Int)
64926membar #StoreLoad
64927
64928P6154: !_LD [14] (Int)
64929sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
64930sub %i0, %i3, %i3
64931lduw [%i3 + 12], %o3
64932! move %o3(lower) -> %o3(upper)
64933sllx %o3, 32, %o3
64934
64935P6155: !_DWST [13] (maybe <- 0x300003f) (Int)
64936sllx %l4, 32, %l6
64937add %l4, 1, %l4
64938or %l6, %l4, %l6
64939stx %l6, [%i3 + 0]
64940add %l4, 1, %l4
64941
64942P6156: !_MEMBAR (FP)
64943
64944P6157: !_BSTC [7] (maybe <- 0x4280001d) (FP)
64945wr %g0, 0xe0, %asi
64946! preparing store val #0, next val will be in f32
64947fmovs %f16, %f20
64948fadds %f16, %f17, %f16
64949! preparing store val #1, next val will be in f33
64950fmovs %f16, %f21
64951fadds %f16, %f17, %f16
64952! preparing store val #2, next val will be in f35
64953fmovd %f20, %f32
64954fmovs %f16, %f21
64955fadds %f16, %f17, %f16
64956fmovd %f20, %f34
64957membar #Sync
64958stda %f32, [%i2 + 0 ] %asi
64959
64960P6158: !_MEMBAR (FP) (CBR)
64961membar #StoreLoad
64962
64963! cbranch
64964andcc %l0, 1, %g0
64965be,pn %xcc, TARGET6158
64966nop
64967RET6158:
64968
64969! lfsr step begin
64970srlx %l0, 1, %o5
64971xnor %o5, %l0, %o5
64972sllx %o5, 63, %o5
64973or %o5, %l0, %l0
64974srlx %l0, 1, %l0
64975
64976
64977P6159: !_LDD [4] (Int)
64978ldd [%i1 + 0], %l6
64979! move %l6(lower) -> %o3(lower)
64980or %l6, %o3, %o3
64981! move %l7(lower) -> %o4(upper)
64982sllx %l7, 32, %o4
64983
64984P6160: !_MEMBAR (FP)
64985
64986P6161: !_BST [19] (maybe <- 0x42800020) (FP)
64987wr %g0, 0xf0, %asi
64988sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
64989sub %i0, %i2, %i2
64990! preparing store val #0, next val will be in f32
64991fmovs %f16, %f20
64992fadds %f16, %f17, %f16
64993! preparing store val #1, next val will be in f33
64994fmovs %f16, %f21
64995fadds %f16, %f17, %f16
64996! preparing store val #2, next val will be in f35
64997fmovd %f20, %f32
64998fmovs %f16, %f21
64999fadds %f16, %f17, %f16
65000fmovd %f20, %f34
65001membar #Sync
65002stda %f32, [%i2 + 0 ] %asi
65003
65004P6162: !_MEMBAR (FP)
65005membar #StoreLoad
65006
65007P6163: !_CASX [1] (maybe <- 0x3000041) (Int)
65008ldx [%i0], %l7
65009! move %l7(upper) -> %o4(lower)
65010srlx %l7, 32, %o5
65011or %o5, %o4, %o4
65012!---- flushing int results buffer----
65013mov %o0, %l5
65014mov %o1, %l5
65015mov %o2, %l5
65016mov %o3, %l5
65017mov %o4, %l5
65018! move %l7(lower) -> %o0(upper)
65019sllx %l7, 32, %o0
65020mov %l7, %o5
65021sllx %l4, 32, %l7
65022add %l4, 1, %l4
65023or %l4, %l7, %l7
65024casx [%i0], %o5, %l7
65025! move %l7(upper) -> %o0(lower)
65026srlx %l7, 32, %o5
65027or %o5, %o0, %o0
65028! move %l7(lower) -> %o1(upper)
65029sllx %l7, 32, %o1
65030add %l4, 1, %l4
65031
65032P6164: !_DWST_BINIT [10] (maybe <- 0x3000043) (Int)
65033wr %g0, 0xe2, %asi
65034sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
65035add %i0, %i3, %i3
65036sllx %l4, 32, %o5
65037add %l4, 1, %l4
65038or %o5, %l4, %o5
65039stxa %o5, [%i3 + 0] %asi
65040add %l4, 1, %l4
65041
65042P6165: !_MEMBAR (Int)
65043membar #StoreLoad
65044
65045P6166: !_PREFETCH [22] (Int)
65046sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
65047add %i0, %i2, %i2
65048prefetch [%i2 + 4], 23
65049
65050P6167: !_MEMBAR (FP)
65051
65052P6168: !_BST [13] (maybe <- 0x42800023) (FP)
65053wr %g0, 0xf0, %asi
65054sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
65055sub %i0, %i3, %i3
65056! preparing store val #0, next val will be in f32
65057fmovs %f16, %f20
65058fadds %f16, %f17, %f16
65059! preparing store val #1, next val will be in f33
65060fmovs %f16, %f21
65061fadds %f16, %f17, %f16
65062! preparing store val #2, next val will be in f35
65063fmovd %f20, %f32
65064fmovs %f16, %f21
65065fadds %f16, %f17, %f16
65066fmovd %f20, %f34
65067membar #Sync
65068stda %f32, [%i3 + 0 ] %asi
65069
65070P6169: !_MEMBAR (FP)
65071membar #StoreLoad
65072
65073P6170: !_ST [0] (maybe <- 0x3000045) (Int)
65074stw %l4, [%i0 + 0 ]
65075add %l4, 1, %l4
65076
65077P6171: !_MEMBAR (FP)
65078membar #StoreLoad
65079
65080P6172: !_BLD [4] (FP) (CBR)
65081wr %g0, 0xf0, %asi
65082ldda [%i1 + 0] %asi, %f32
65083membar #Sync
65084! 3 addresses covered
65085fmovd %f32, %f18
65086fmovs %f18, %f7
65087fmovs %f19, %f8
65088fmovd %f34, %f18
65089fmovs %f19, %f9
65090
65091! cbranch
65092andcc %l0, 1, %g0
65093be,pn %xcc, TARGET6172
65094nop
65095RET6172:
65096
65097! lfsr step begin
65098srlx %l0, 1, %l3
65099xnor %l3, %l0, %l3
65100sllx %l3, 63, %l3
65101or %l3, %l0, %l0
65102srlx %l0, 1, %l0
65103
65104
65105P6173: !_MEMBAR (FP)
65106
65107P6174: !_CAS [16] (maybe <- 0x3000046) (Int)
65108sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
65109sub %i0, %i2, %i2
65110add %i2, 4, %l7
65111lduw [%l7], %l3
65112mov %l3, %l6
65113! move %l6(lower) -> %o1(lower)
65114or %l6, %o1, %o1
65115mov %l4, %o2
65116cas [%l7], %l6, %o2
65117! move %o2(lower) -> %o2(upper)
65118sllx %o2, 32, %o2
65119add %l4, 1, %l4
65120
65121P6175: !_CASX [8] (maybe <- 0x3000047) (Int)
65122sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
65123add %i0, %i3, %i3
65124add %i3, 8, %l7
65125ldx [%l7], %l3
65126! move %l3(upper) -> %o2(lower)
65127srlx %l3, 32, %l6
65128or %l6, %o2, %o2
65129! move %l3(lower) -> %o3(upper)
65130sllx %l3, 32, %o3
65131mov %l3, %l6
65132mov %l4, %l3
65133casx [%l7], %l6, %l3
65134! move %l3(upper) -> %o3(lower)
65135srlx %l3, 32, %l6
65136or %l6, %o3, %o3
65137! move %l3(lower) -> %o4(upper)
65138sllx %l3, 32, %o4
65139add %l4, 1, %l4
65140
65141P6176: !_REPLACEMENT [6] (Int) (Branch target of P6722)
65142sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
65143sub %i0, %i2, %i2
65144sethi %hi(0x20000), %l6
65145ld [%i2+0], %o5
65146st %o5, [%i2+0]
65147add %i2, %l6, %l7
65148ld [%l7+0], %o5
65149st %o5, [%l7+0]
65150add %l7, %l6, %l7
65151ld [%l7+0], %o5
65152st %o5, [%l7+0]
65153add %l7, %l6, %l7
65154ld [%l7+0], %o5
65155st %o5, [%l7+0]
65156add %l7, %l6, %l7
65157ld [%l7+0], %o5
65158st %o5, [%l7+0]
65159add %l7, %l6, %l7
65160ld [%l7+0], %o5
65161st %o5, [%l7+0]
65162add %l7, %l6, %l7
65163ld [%l7+0], %o5
65164st %o5, [%l7+0]
65165add %l7, %l6, %l7
65166ld [%l7+0], %o5
65167st %o5, [%l7+0]
65168ba P6177
65169nop
65170
65171TARGET6722:
65172ba RET6722
65173nop
65174
65175
65176P6177: !_MEMBAR (FP)
65177
65178P6178: !_BSTC [13] (maybe <- 0x42800026) (FP)
65179wr %g0, 0xe0, %asi
65180sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
65181sub %i0, %i3, %i3
65182! preparing store val #0, next val will be in f32
65183fmovs %f16, %f20
65184fadds %f16, %f17, %f16
65185! preparing store val #1, next val will be in f33
65186fmovs %f16, %f21
65187fadds %f16, %f17, %f16
65188! preparing store val #2, next val will be in f35
65189fmovd %f20, %f32
65190fmovs %f16, %f21
65191fadds %f16, %f17, %f16
65192fmovd %f20, %f34
65193membar #Sync
65194stda %f32, [%i3 + 0 ] %asi
65195
65196P6179: !_MEMBAR (FP)
65197membar #StoreLoad
65198
65199P6180: !_BLD [7] (FP)
65200wr %g0, 0xf0, %asi
65201sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
65202add %i0, %i2, %i2
65203ldda [%i2 + 0] %asi, %f32
65204membar #Sync
65205! 3 addresses covered
65206fmovd %f32, %f10
65207fmovd %f34, %f18
65208fmovs %f19, %f12
65209
65210P6181: !_MEMBAR (FP)
65211
65212P6182: !_DWST_BINIT [15] (maybe <- 0x3000048) (Int)
65213wr %g0, 0xe2, %asi
65214sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
65215sub %i0, %i3, %i3
65216sllx %l4, 32, %o5
65217add %l4, 1, %l4
65218or %o5, %l4, %o5
65219stxa %o5, [%i3 + 0] %asi
65220add %l4, 1, %l4
65221
65222P6183: !_MEMBAR (Int) (CBR)
65223membar #StoreLoad
65224
65225! cbranch
65226andcc %l0, 1, %g0
65227be,pt %xcc, TARGET6183
65228nop
65229RET6183:
65230
65231! lfsr step begin
65232srlx %l0, 1, %l7
65233xnor %l7, %l0, %l7
65234sllx %l7, 63, %l7
65235or %l7, %l0, %l0
65236srlx %l0, 1, %l0
65237
65238
65239P6184: !_DWLD [3] (Int)
65240ldx [%i1 + 0], %l3
65241! move %l3(upper) -> %o4(lower)
65242srlx %l3, 32, %o5
65243or %o5, %o4, %o4
65244!---- flushing int results buffer----
65245mov %o0, %l5
65246mov %o1, %l5
65247mov %o2, %l5
65248mov %o3, %l5
65249mov %o4, %l5
65250! move %l3(lower) -> %o0(upper)
65251sllx %l3, 32, %o0
65252
65253P6185: !_PREFETCH [9] (Int)
65254sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
65255add %i0, %i2, %i2
65256prefetch [%i2 + 0], 24
65257
65258P6186: !_PREFETCH [10] (Int)
65259prefetch [%i2 + 4], 21
65260
65261P6187: !_ST [17] (maybe <- 0x300004a) (Int)
65262stw %l4, [%i3 + 12 ]
65263add %l4, 1, %l4
65264
65265P6188: !_MEMBAR (FP)
65266
65267P6189: !_BST [12] (maybe <- 0x42800029) (FP) (CBR)
65268wr %g0, 0xf0, %asi
65269sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
65270sub %i0, %i3, %i3
65271! preparing store val #0, next val will be in f32
65272fmovs %f16, %f20
65273fadds %f16, %f17, %f16
65274! preparing store val #1, next val will be in f33
65275fmovs %f16, %f21
65276fadds %f16, %f17, %f16
65277! preparing store val #2, next val will be in f35
65278fmovd %f20, %f32
65279fmovs %f16, %f21
65280fadds %f16, %f17, %f16
65281fmovd %f20, %f34
65282membar #Sync
65283stda %f32, [%i3 + 0 ] %asi
65284
65285! cbranch
65286andcc %l0, 1, %g0
65287be,pt %xcc, TARGET6189
65288nop
65289RET6189:
65290
65291! lfsr step begin
65292srlx %l0, 1, %o5
65293xnor %o5, %l0, %o5
65294sllx %o5, 63, %o5
65295or %o5, %l0, %l0
65296srlx %l0, 1, %l0
65297
65298
65299P6190: !_MEMBAR (FP)
65300membar #StoreLoad
65301
65302P6191: !_SWAP [6] (maybe <- 0x300004b) (Int)
65303sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
65304add %i0, %i2, %i2
65305mov %l4, %l7
65306swap [%i2 + 0], %l7
65307! move %l7(lower) -> %o0(lower)
65308srl %l7, 0, %l3
65309or %l3, %o0, %o0
65310add %l4, 1, %l4
65311
65312P6192: !_SWAP [3] (maybe <- 0x300004c) (Int)
65313mov %l4, %o1
65314swap [%i1 + 0], %o1
65315! move %o1(lower) -> %o1(upper)
65316sllx %o1, 32, %o1
65317add %l4, 1, %l4
65318
65319P6193: !_CAS [11] (maybe <- 0x300004d) (Int)
65320sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
65321add %i0, %i3, %i3
65322add %i3, 12, %o5
65323lduw [%o5], %l6
65324mov %l6, %l7
65325! move %l7(lower) -> %o1(lower)
65326or %l7, %o1, %o1
65327mov %l4, %o2
65328cas [%o5], %l7, %o2
65329! move %o2(lower) -> %o2(upper)
65330sllx %o2, 32, %o2
65331add %l4, 1, %l4
65332
65333P6194: !_ST_BINIT [7] (maybe <- 0x300004e) (Int)
65334wr %g0, 0xe2, %asi
65335stwa %l4, [%i2 + 4] %asi
65336add %l4, 1, %l4
65337
65338P6195: !_MEMBAR (Int)
65339
65340P6196: !_BSTC [15] (maybe <- 0x4280002c) (FP)
65341wr %g0, 0xe0, %asi
65342sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
65343sub %i0, %i2, %i2
65344! preparing store val #0, next val will be in f32
65345fmovs %f16, %f20
65346fadds %f16, %f17, %f16
65347! preparing store val #1, next val will be in f33
65348fmovs %f16, %f21
65349fadds %f16, %f17, %f16
65350! preparing store val #2, next val will be in f35
65351fmovd %f20, %f32
65352fmovs %f16, %f21
65353fadds %f16, %f17, %f16
65354fmovd %f20, %f34
65355membar #Sync
65356stda %f32, [%i2 + 0 ] %asi
65357
65358P6197: !_MEMBAR (FP)
65359membar #StoreLoad
65360
65361P6198: !_LDD [12] (Int)
65362sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
65363sub %i0, %i3, %i3
65364ldd [%i3 + 0], %l6
65365! move %l6(lower) -> %o2(lower)
65366or %l6, %o2, %o2
65367! move %l7(lower) -> %o3(upper)
65368sllx %l7, 32, %o3
65369
65370P6199: !_CASX [13] (maybe <- 0x300004f) (Int)
65371ldx [%i3], %o5
65372! move %o5(upper) -> %o3(lower)
65373srlx %o5, 32, %l3
65374or %l3, %o3, %o3
65375! move %o5(lower) -> %o4(upper)
65376sllx %o5, 32, %o4
65377mov %o5, %l3
65378sllx %l4, 32, %o5
65379add %l4, 1, %l4
65380or %l4, %o5, %o5
65381casx [%i3], %l3, %o5
65382! move %o5(upper) -> %o4(lower)
65383srlx %o5, 32, %l3
65384or %l3, %o4, %o4
65385!---- flushing int results buffer----
65386mov %o0, %l5
65387mov %o1, %l5
65388mov %o2, %l5
65389mov %o3, %l5
65390mov %o4, %l5
65391! move %o5(lower) -> %o0(upper)
65392sllx %o5, 32, %o0
65393add %l4, 1, %l4
65394
65395P6200: !_REPLACEMENT [23] (Int)
65396sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
65397sub %i0, %i2, %i2
65398sethi %hi(0x20000), %l3
65399ld [%i2+12], %l7
65400st %l7, [%i2+12]
65401add %i2, %l3, %l6
65402ld [%l6+12], %l7
65403st %l7, [%l6+12]
65404add %l6, %l3, %l6
65405ld [%l6+12], %l7
65406st %l7, [%l6+12]
65407add %l6, %l3, %l6
65408ld [%l6+12], %l7
65409st %l7, [%l6+12]
65410add %l6, %l3, %l6
65411ld [%l6+12], %l7
65412st %l7, [%l6+12]
65413add %l6, %l3, %l6
65414ld [%l6+12], %l7
65415st %l7, [%l6+12]
65416add %l6, %l3, %l6
65417ld [%l6+12], %l7
65418st %l7, [%l6+12]
65419add %l6, %l3, %l6
65420ld [%l6+12], %l7
65421st %l7, [%l6+12]
65422
65423P6201: !_ST [7] (maybe <- 0x3000051) (Int)
65424sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
65425add %i0, %i3, %i3
65426stw %l4, [%i3 + 4 ]
65427add %l4, 1, %l4
65428
65429P6202: !_ST [9] (maybe <- 0x3000052) (Int)
65430sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
65431add %i0, %i2, %i2
65432stw %l4, [%i2 + 0 ]
65433add %l4, 1, %l4
65434
65435P6203: !_PREFETCH [16] (Int)
65436sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
65437sub %i0, %i3, %i3
65438prefetch [%i3 + 4], 21
65439
65440P6204: !_CAS [1] (maybe <- 0x3000053) (Int)
65441add %i0, 4, %l7
65442lduw [%l7], %l3
65443mov %l3, %l6
65444! move %l6(lower) -> %o0(lower)
65445or %l6, %o0, %o0
65446mov %l4, %o1
65447cas [%l7], %l6, %o1
65448! move %o1(lower) -> %o1(upper)
65449sllx %o1, 32, %o1
65450add %l4, 1, %l4
65451
65452P6205: !_ST_BINIT [2] (maybe <- 0x3000054) (Int)
65453wr %g0, 0xe2, %asi
65454stwa %l4, [%i0 + 12] %asi
65455add %l4, 1, %l4
65456
65457P6206: !_MEMBAR (Int)
65458membar #StoreLoad
65459
65460P6207: !_ST [4] (maybe <- 0x3000055) (Int)
65461stw %l4, [%i1 + 4 ]
65462add %l4, 1, %l4
65463
65464P6208: !_MEMBAR (FP)
65465
65466P6209: !_BSTC [0] (maybe <- 0x4280002f) (FP) (CBR)
65467wr %g0, 0xe0, %asi
65468! preparing store val #0, next val will be in f32
65469fmovs %f16, %f20
65470fadds %f16, %f17, %f16
65471! preparing store val #1, next val will be in f33
65472fmovs %f16, %f21
65473fadds %f16, %f17, %f16
65474! preparing store val #2, next val will be in f35
65475fmovd %f20, %f32
65476fmovs %f16, %f21
65477fadds %f16, %f17, %f16
65478fmovd %f20, %f34
65479membar #Sync
65480stda %f32, [%i0 + 0 ] %asi
65481
65482! cbranch
65483andcc %l0, 1, %g0
65484be,pn %xcc, TARGET6209
65485nop
65486RET6209:
65487
65488! lfsr step begin
65489srlx %l0, 1, %o5
65490xnor %o5, %l0, %o5
65491sllx %o5, 63, %o5
65492or %o5, %l0, %l0
65493srlx %l0, 1, %l0
65494
65495
65496P6210: !_MEMBAR (FP)
65497membar #StoreLoad
65498
65499P6211: !_SWAP [22] (maybe <- 0x3000056) (Int)
65500sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
65501add %i0, %i2, %i2
65502mov %l4, %l7
65503swap [%i2 + 4], %l7
65504! move %l7(lower) -> %o1(lower)
65505srl %l7, 0, %l3
65506or %l3, %o1, %o1
65507add %l4, 1, %l4
65508
65509P6212: !_MEMBAR (FP)
65510
65511P6213: !_BSTC [17] (maybe <- 0x42800032) (FP)
65512wr %g0, 0xe0, %asi
65513! preparing store val #0, next val will be in f32
65514fmovs %f16, %f20
65515fadds %f16, %f17, %f16
65516! preparing store val #1, next val will be in f33
65517fmovs %f16, %f21
65518fadds %f16, %f17, %f16
65519! preparing store val #2, next val will be in f35
65520fmovd %f20, %f32
65521fmovs %f16, %f21
65522fadds %f16, %f17, %f16
65523fmovd %f20, %f34
65524membar #Sync
65525stda %f32, [%i3 + 0 ] %asi
65526
65527P6214: !_MEMBAR (FP)
65528membar #StoreLoad
65529
65530P6215: !_DWST [13] (maybe <- 0x3000057) (Int)
65531sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
65532sub %i0, %i3, %i3
65533sllx %l4, 32, %l7
65534add %l4, 1, %l4
65535or %l7, %l4, %l7
65536stx %l7, [%i3 + 0]
65537add %l4, 1, %l4
65538
65539P6216: !_MEMBAR (FP)
65540
65541P6217: !_BST [21] (maybe <- 0x42800035) (FP)
65542wr %g0, 0xf0, %asi
65543! preparing store val #0, next val will be in f32
65544fmovs %f16, %f20
65545fadds %f16, %f17, %f16
65546! preparing store val #1, next val will be in f33
65547fmovs %f16, %f21
65548fadds %f16, %f17, %f16
65549! preparing store val #2, next val will be in f35
65550fmovd %f20, %f32
65551fmovs %f16, %f21
65552fadds %f16, %f17, %f16
65553fmovd %f20, %f34
65554membar #Sync
65555stda %f32, [%i2 + 0 ] %asi
65556
65557P6218: !_MEMBAR (FP)
65558membar #StoreLoad
65559
65560P6219: !_PREFETCH [17] (Int)
65561sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
65562sub %i0, %i2, %i2
65563prefetch [%i2 + 12], 30
65564
65565P6220: !_MEMBAR (FP)
65566
65567P6221: !_BST [3] (maybe <- 0x42800038) (FP)
65568wr %g0, 0xf0, %asi
65569! preparing store val #0, next val will be in f32
65570fmovs %f16, %f20
65571fadds %f16, %f17, %f16
65572! preparing store val #1, next val will be in f33
65573fmovs %f16, %f21
65574fadds %f16, %f17, %f16
65575! preparing store val #2, next val will be in f35
65576fmovd %f20, %f32
65577fmovs %f16, %f21
65578fadds %f16, %f17, %f16
65579fmovd %f20, %f34
65580membar #Sync
65581stda %f32, [%i1 + 0 ] %asi
65582
65583P6222: !_MEMBAR (FP) (CBR)
65584membar #StoreLoad
65585
65586! cbranch
65587andcc %l0, 1, %g0
65588be,pn %xcc, TARGET6222
65589nop
65590RET6222:
65591
65592! lfsr step begin
65593srlx %l0, 1, %o5
65594xnor %o5, %l0, %o5
65595sllx %o5, 63, %o5
65596or %o5, %l0, %l0
65597srlx %l0, 1, %l0
65598
65599
65600P6223: !_REPLACEMENT [14] (Int)
65601sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
65602add %i0, %i3, %i3
65603sethi %hi(0x20000), %l3
65604ld [%i3+12], %l7
65605st %l7, [%i3+12]
65606add %i3, %l3, %l6
65607ld [%l6+12], %l7
65608st %l7, [%l6+12]
65609add %l6, %l3, %l6
65610ld [%l6+12], %l7
65611st %l7, [%l6+12]
65612add %l6, %l3, %l6
65613ld [%l6+12], %l7
65614st %l7, [%l6+12]
65615add %l6, %l3, %l6
65616ld [%l6+12], %l7
65617st %l7, [%l6+12]
65618add %l6, %l3, %l6
65619ld [%l6+12], %l7
65620st %l7, [%l6+12]
65621add %l6, %l3, %l6
65622ld [%l6+12], %l7
65623st %l7, [%l6+12]
65624add %l6, %l3, %l6
65625ld [%l6+12], %l7
65626st %l7, [%l6+12]
65627
65628P6224: !_DWST_BINIT [0] (maybe <- 0x3000059) (Int)
65629wr %g0, 0xe2, %asi
65630sllx %l4, 32, %o5
65631add %l4, 1, %l4
65632or %o5, %l4, %o5
65633stxa %o5, [%i0 + 0] %asi
65634add %l4, 1, %l4
65635
65636P6225: !_MEMBAR (Int)
65637membar #StoreLoad
65638
65639P6226: !_BLD [14] (FP) (Branch target of P6327)
65640wr %g0, 0xf0, %asi
65641sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
65642sub %i0, %i2, %i2
65643ldda [%i2 + 0] %asi, %f32
65644membar #Sync
65645! 3 addresses covered
65646fmovd %f32, %f18
65647fmovs %f18, %f13
65648fmovs %f19, %f14
65649fmovd %f34, %f18
65650fmovs %f19, %f15
65651!---- flushing fp results buffer to %f30 ----
65652fmovd %f0, %f30
65653fmovd %f2, %f30
65654fmovd %f4, %f30
65655fmovd %f6, %f30
65656fmovd %f8, %f30
65657fmovd %f10, %f30
65658fmovd %f12, %f30
65659fmovd %f14, %f30
65660!--
65661ba P6227
65662nop
65663
65664TARGET6327:
65665ba RET6327
65666nop
65667
65668
65669P6227: !_MEMBAR (FP)
65670
65671P6228: !_CAS [22] (maybe <- 0x300005b) (Int) (CBR)
65672sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
65673add %i0, %i3, %i3
65674add %i3, 4, %o5
65675lduw [%o5], %o2
65676mov %o2, %l7
65677! move %l7(lower) -> %o2(upper)
65678sllx %l7, 32, %o2
65679mov %l4, %l6
65680cas [%o5], %l7, %l6
65681! move %l6(lower) -> %o2(lower)
65682srl %l6, 0, %l7
65683or %l7, %o2, %o2
65684add %l4, 1, %l4
65685
65686! cbranch
65687andcc %l0, 1, %g0
65688be,pt %xcc, TARGET6228
65689nop
65690RET6228:
65691
65692! lfsr step begin
65693srlx %l0, 1, %l7
65694xnor %l7, %l0, %l7
65695sllx %l7, 63, %l7
65696or %l7, %l0, %l0
65697srlx %l0, 1, %l0
65698
65699
65700P6229: !_PREFETCH [5] (Int)
65701prefetch [%i1 + 12], 20
65702
65703P6230: !_MEMBAR (FP)
65704
65705P6231: !_BSTC [0] (maybe <- 0x4280003b) (FP)
65706wr %g0, 0xe0, %asi
65707! preparing store val #0, next val will be in f32
65708fmovs %f16, %f20
65709fadds %f16, %f17, %f16
65710! preparing store val #1, next val will be in f33
65711fmovs %f16, %f21
65712fadds %f16, %f17, %f16
65713! preparing store val #2, next val will be in f35
65714fmovd %f20, %f32
65715fmovs %f16, %f21
65716fadds %f16, %f17, %f16
65717fmovd %f20, %f34
65718membar #Sync
65719stda %f32, [%i0 + 0 ] %asi
65720
65721P6232: !_MEMBAR (FP)
65722membar #StoreLoad
65723
65724P6233: !_LD [1] (Int)
65725lduw [%i0 + 4], %o3
65726! move %o3(lower) -> %o3(upper)
65727sllx %o3, 32, %o3
65728
65729P6234: !_LDD [16] (Int)
65730sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
65731sub %i0, %i2, %i2
65732ldd [%i2 + 0], %l6
65733! move %l6(lower) -> %o3(lower)
65734or %l6, %o3, %o3
65735! move %l7(lower) -> %o4(upper)
65736sllx %l7, 32, %o4
65737
65738P6235: !_LD [12] (Int)
65739sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
65740sub %i0, %i3, %i3
65741lduw [%i3 + 0], %l6
65742! move %l6(lower) -> %o4(lower)
65743or %l6, %o4, %o4
65744!---- flushing int results buffer----
65745mov %o0, %l5
65746mov %o1, %l5
65747mov %o2, %l5
65748mov %o3, %l5
65749mov %o4, %l5
65750
65751P6236: !_DWLD [16] (Int)
65752ldx [%i2 + 0], %o0
65753! move %o0(upper) -> %o0(upper)
65754! move %o0(lower) -> %o0(lower)
65755
65756P6237: !_LD [9] (FP) (Branch target of P6791)
65757sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
65758add %i0, %i2, %i2
65759ld [%i2 + 0], %f0
65760! 1 addresses covered
65761ba P6238
65762nop
65763
65764TARGET6791:
65765ba RET6791
65766nop
65767
65768
65769P6238: !_DWLD [5] (Int)
65770ldx [%i1 + 8], %o1
65771! move %o1(lower) -> %o1(upper)
65772sllx %o1, 32, %o1
65773
65774P6239: !_ST_BINIT [13] (maybe <- 0x300005c) (Int)
65775wr %g0, 0xe2, %asi
65776stwa %l4, [%i3 + 4] %asi
65777add %l4, 1, %l4
65778
65779P6240: !_MEMBAR (Int)
65780membar #StoreLoad
65781
65782P6241: !_BLD [12] (FP)
65783wr %g0, 0xf0, %asi
65784ldda [%i3 + 0] %asi, %f32
65785membar #Sync
65786! 3 addresses covered
65787fmovd %f32, %f18
65788fmovs %f18, %f1
65789fmovs %f19, %f2
65790fmovd %f34, %f18
65791fmovs %f19, %f3
65792
65793P6242: !_MEMBAR (FP)
65794
65795P6243: !_DWST_BINIT [19] (maybe <- 0x300005d) (Int)
65796wr %g0, 0xe2, %asi
65797sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
65798sub %i0, %i3, %i3
65799sllx %l4, 32, %l6
65800add %l4, 1, %l4
65801or %l6, %l4, %l6
65802stxa %l6, [%i3 + 0] %asi
65803add %l4, 1, %l4
65804
65805P6244: !_MEMBAR (Int)
65806membar #StoreLoad
65807
65808P6245: !_DWST_BINIT [17] (maybe <- 0x300005f) (Int)
65809wr %g0, 0xe2, %asi
65810sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i2
65811sub %i0, %i2, %i2
65812mov %l4, %l3
65813stxa %l3, [%i2 + 8] %asi
65814add %l4, 1, %l4
65815
65816P6246: !_MEMBAR (Int)
65817membar #StoreLoad
65818
65819P6247: !_CAS [0] (maybe <- 0x3000060) (Int)
65820lduw [%i0], %l7
65821mov %l7, %o5
65822! move %o5(lower) -> %o1(lower)
65823or %o5, %o1, %o1
65824mov %l4, %o2
65825cas [%i0], %o5, %o2
65826! move %o2(lower) -> %o2(upper)
65827sllx %o2, 32, %o2
65828add %l4, 1, %l4
65829
65830P6248: !_LD [2] (Int) (Branch target of P6909)
65831lduw [%i0 + 12], %l3
65832! move %l3(lower) -> %o2(lower)
65833or %l3, %o2, %o2
65834ba P6249
65835nop
65836
65837TARGET6909:
65838ba RET6909
65839nop
65840
65841
65842P6249: !_CAS [18] (maybe <- 0x3000061) (Int) (LE)
65843! Change single-word-level endianess (big endian <-> little endian)
65844sethi %hi(0xff00ff00), %l7
65845or %l7, %lo(0xff00ff00), %l7
65846and %l4, %l7, %l6
65847srl %l6, 8, %l6
65848sll %l4, 8, %o5
65849and %o5, %l7, %o5
65850or %o5, %l6, %o5
65851srl %o5, 16, %l6
65852sll %o5, 16, %o5
65853srl %o5, 0, %o5
65854or %o5, %l6, %o5
65855wr %g0, 0x88, %asi
65856lduwa [%i3] %asi, %o3
65857mov %o3, %l6
65858! move %l6(lower) -> %o3(upper)
65859sllx %l6, 32, %o3
65860mov %o5, %l3
65861casa [%i3] %asi, %l6, %l3
65862! move %l3(lower) -> %o3(lower)
65863srl %l3, 0, %l6
65864or %l6, %o3, %o3
65865add %l4, 1, %l4
65866
65867P6250: !_ST [1] (maybe <- 0x4280003e) (FP)
65868! preparing store val #0, next val will be in f20
65869fmovs %f16, %f20
65870fadds %f16, %f17, %f16
65871st %f20, [%i0 + 4 ]
65872
65873P6251: !_MEMBAR (FP)
65874membar #StoreLoad
65875
65876P6252: !_BLD [12] (FP)
65877wr %g0, 0xf0, %asi
65878sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
65879sub %i0, %i3, %i3
65880ldda [%i3 + 0] %asi, %f32
65881membar #Sync
65882! 3 addresses covered
65883fmovd %f32, %f4
65884fmovd %f34, %f18
65885fmovs %f19, %f6
65886
65887P6253: !_MEMBAR (FP)
65888
65889P6254: !_DWST_BINIT [8] (maybe <- 0x3000062) (Int) (Branch target of P6888)
65890wr %g0, 0xe2, %asi
65891sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
65892add %i0, %i2, %i2
65893mov %l4, %l3
65894stxa %l3, [%i2 + 8] %asi
65895add %l4, 1, %l4
65896ba P6255
65897nop
65898
65899TARGET6888:
65900ba RET6888
65901nop
65902
65903
65904P6255: !_MEMBAR (Int)
65905membar #StoreLoad
65906
65907P6256: !_SWAP [6] (maybe <- 0x3000063) (Int)
65908mov %l4, %o4
65909swap [%i2 + 0], %o4
65910! move %o4(lower) -> %o4(upper)
65911sllx %o4, 32, %o4
65912add %l4, 1, %l4
65913
65914P6257: !_MEMBAR (FP)
65915
65916P6258: !_BSTC [7] (maybe <- 0x4280003f) (FP)
65917wr %g0, 0xe0, %asi
65918! preparing store val #0, next val will be in f32
65919fmovs %f16, %f20
65920fadds %f16, %f17, %f16
65921! preparing store val #1, next val will be in f33
65922fmovs %f16, %f21
65923fadds %f16, %f17, %f16
65924! preparing store val #2, next val will be in f35
65925fmovd %f20, %f32
65926fmovs %f16, %f21
65927fadds %f16, %f17, %f16
65928fmovd %f20, %f34
65929membar #Sync
65930stda %f32, [%i2 + 0 ] %asi
65931
65932P6259: !_MEMBAR (FP)
65933membar #StoreLoad
65934
65935P6260: !_BLD [3] (FP)
65936wr %g0, 0xf0, %asi
65937ldda [%i1 + 0] %asi, %f32
65938membar #Sync
65939! 3 addresses covered
65940fmovd %f32, %f18
65941fmovs %f18, %f7
65942fmovs %f19, %f8
65943fmovd %f34, %f18
65944fmovs %f19, %f9
65945
65946P6261: !_MEMBAR (FP)
65947
65948P6262: !_BLD [15] (FP)
65949wr %g0, 0xf0, %asi
65950sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS2_O), %i3
65951sub %i0, %i3, %i3
65952ldda [%i3 + 0] %asi, %f32
65953membar #Sync
65954! 3 addresses covered
65955fmovd %f32, %f10
65956fmovd %f34, %f18
65957fmovs %f19, %f12
65958
65959P6263: !_MEMBAR (FP)
65960
65961P6264: !_ST_BINIT [20] (maybe <- 0x3000064) (Int)
65962wr %g0, 0xe2, %asi
65963sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
65964sub %i0, %i2, %i2
65965stwa %l4, [%i2 + 12] %asi
65966add %l4, 1, %l4
65967
65968P6265: !_MEMBAR (Int)
65969membar #StoreLoad
65970
65971P6266: !_ST_BINIT [0] (maybe <- 0x3000065) (Int)
65972wr %g0, 0xe2, %asi
65973stwa %l4, [%i0 + 0] %asi
65974add %l4, 1, %l4
65975
65976P6267: !_MEMBAR (Int)
65977membar #StoreLoad
65978
65979P6268: !_ST_BINIT [10] (maybe <- 0x3000066) (Int)
65980wr %g0, 0xe2, %asi
65981sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
65982add %i0, %i3, %i3
65983stwa %l4, [%i3 + 4] %asi
65984add %l4, 1, %l4
65985
65986P6269: !_MEMBAR (Int)
65987membar #StoreLoad
65988
65989P6270: !_DWLD [17] (Int)
65990sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
65991sub %i0, %i2, %i2
65992ldx [%i2 + 8], %l3
65993! move %l3(lower) -> %o4(lower)
65994srl %l3, 0, %o5
65995or %o5, %o4, %o4
65996!---- flushing int results buffer----
65997mov %o0, %l5
65998mov %o1, %l5
65999mov %o2, %l5
66000mov %o3, %l5
66001mov %o4, %l5
66002
66003P6271: !_PREFETCH [11] (Int)
66004prefetch [%i3 + 12], 0
66005
66006P6272: !_CAS [7] (maybe <- 0x3000067) (Int)
66007sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
66008add %i0, %i3, %i3
66009add %i3, 4, %l7
66010lduw [%l7], %o0
66011mov %o0, %l6
66012! move %l6(lower) -> %o0(upper)
66013sllx %l6, 32, %o0
66014mov %l4, %l3
66015cas [%l7], %l6, %l3
66016! move %l3(lower) -> %o0(lower)
66017srl %l3, 0, %l6
66018or %l6, %o0, %o0
66019add %l4, 1, %l4
66020
66021P6273: !_MEMBAR (FP)
66022
66023P6274: !_BSTC [13] (maybe <- 0x42800042) (FP)
66024wr %g0, 0xe0, %asi
66025sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
66026sub %i0, %i2, %i2
66027! preparing store val #0, next val will be in f32
66028fmovs %f16, %f20
66029fadds %f16, %f17, %f16
66030! preparing store val #1, next val will be in f33
66031fmovs %f16, %f21
66032fadds %f16, %f17, %f16
66033! preparing store val #2, next val will be in f35
66034fmovd %f20, %f32
66035fmovs %f16, %f21
66036fadds %f16, %f17, %f16
66037fmovd %f20, %f34
66038membar #Sync
66039stda %f32, [%i2 + 0 ] %asi
66040
66041P6275: !_MEMBAR (FP)
66042membar #StoreLoad
66043
66044P6276: !_CAS [4] (maybe <- 0x3000068) (Int)
66045add %i1, 4, %l6
66046lduw [%l6], %o1
66047mov %o1, %l3
66048! move %l3(lower) -> %o1(upper)
66049sllx %l3, 32, %o1
66050mov %l4, %o5
66051cas [%l6], %l3, %o5
66052! move %o5(lower) -> %o1(lower)
66053srl %o5, 0, %l3
66054or %l3, %o1, %o1
66055add %l4, 1, %l4
66056
66057P6277: !_MEMBAR (FP)
66058
66059P6278: !_BSTC [12] (maybe <- 0x42800045) (FP)
66060wr %g0, 0xe0, %asi
66061! preparing store val #0, next val will be in f32
66062fmovs %f16, %f20
66063fadds %f16, %f17, %f16
66064! preparing store val #1, next val will be in f33
66065fmovs %f16, %f21
66066fadds %f16, %f17, %f16
66067! preparing store val #2, next val will be in f35
66068fmovd %f20, %f32
66069fmovs %f16, %f21
66070fadds %f16, %f17, %f16
66071fmovd %f20, %f34
66072membar #Sync
66073stda %f32, [%i2 + 0 ] %asi
66074
66075P6279: !_MEMBAR (FP)
66076
66077P6280: !_BST [5] (maybe <- 0x42800048) (FP) (CBR)
66078wr %g0, 0xf0, %asi
66079! preparing store val #0, next val will be in f32
66080fmovs %f16, %f20
66081fadds %f16, %f17, %f16
66082! preparing store val #1, next val will be in f33
66083fmovs %f16, %f21
66084fadds %f16, %f17, %f16
66085! preparing store val #2, next val will be in f35
66086fmovd %f20, %f32
66087fmovs %f16, %f21
66088fadds %f16, %f17, %f16
66089fmovd %f20, %f34
66090membar #Sync
66091stda %f32, [%i1 + 0 ] %asi
66092
66093! cbranch
66094andcc %l0, 1, %g0
66095be,pt %xcc, TARGET6280
66096nop
66097RET6280:
66098
66099! lfsr step begin
66100srlx %l0, 1, %l7
66101xnor %l7, %l0, %l7
66102sllx %l7, 63, %l7
66103or %l7, %l0, %l0
66104srlx %l0, 1, %l0
66105
66106
66107P6281: !_MEMBAR (FP)
66108membar #StoreLoad
66109
66110P6282: !_LDD [13] (Int)
66111ldd [%i2 + 0], %l6
66112! move %l6(lower) -> %o2(upper)
66113sllx %l6, 32, %o2
66114! move %l7(lower) -> %o2(lower)
66115or %l7, %o2, %o2
66116
66117P6283: !_MEMBAR (FP)
66118
66119P6284: !_BSTC [7] (maybe <- 0x4280004b) (FP)
66120wr %g0, 0xe0, %asi
66121! preparing store val #0, next val will be in f32
66122fmovs %f16, %f20
66123fadds %f16, %f17, %f16
66124! preparing store val #1, next val will be in f33
66125fmovs %f16, %f21
66126fadds %f16, %f17, %f16
66127! preparing store val #2, next val will be in f35
66128fmovd %f20, %f32
66129fmovs %f16, %f21
66130fadds %f16, %f17, %f16
66131fmovd %f20, %f34
66132membar #Sync
66133stda %f32, [%i3 + 0 ] %asi
66134
66135P6285: !_MEMBAR (FP)
66136membar #StoreLoad
66137
66138P6286: !_DWLD [7] (Int) (Branch target of P6069)
66139ldx [%i3 + 0], %o3
66140! move %o3(upper) -> %o3(upper)
66141! move %o3(lower) -> %o3(lower)
66142ba P6287
66143nop
66144
66145TARGET6069:
66146ba RET6069
66147nop
66148
66149
66150P6287: !_DWLD [9] (FP)
66151sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
66152add %i0, %i3, %i3
66153ldd [%i3 + 0], %f18
66154! 2 addresses covered
66155fmovs %f18, %f13
66156fmovs %f19, %f14
66157
66158P6288: !_SWAP [7] (maybe <- 0x3000069) (Int)
66159sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
66160add %i0, %i2, %i2
66161mov %l4, %o4
66162swap [%i2 + 4], %o4
66163! move %o4(lower) -> %o4(upper)
66164sllx %o4, 32, %o4
66165add %l4, 1, %l4
66166
66167P6289: !_CAS [18] (maybe <- 0x300006a) (Int) (LE)
66168! Change single-word-level endianess (big endian <-> little endian)
66169sethi %hi(0xff00ff00), %l6
66170or %l6, %lo(0xff00ff00), %l6
66171and %l4, %l6, %l3
66172srl %l3, 8, %l3
66173sll %l4, 8, %l7
66174and %l7, %l6, %l7
66175or %l7, %l3, %l7
66176srl %l7, 16, %l3
66177sll %l7, 16, %l7
66178srl %l7, 0, %l7
66179or %l7, %l3, %l7
66180wr %g0, 0x88, %asi
66181sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
66182sub %i0, %i3, %i3
66183lduwa [%i3] %asi, %o5
66184mov %o5, %l3
66185! move %l3(lower) -> %o4(lower)
66186or %l3, %o4, %o4
66187!---- flushing int results buffer----
66188mov %o0, %l5
66189mov %o1, %l5
66190mov %o2, %l5
66191mov %o3, %l5
66192mov %o4, %l5
66193mov %l7, %o0
66194casa [%i3] %asi, %l3, %o0
66195! move %o0(lower) -> %o0(upper)
66196sllx %o0, 32, %o0
66197add %l4, 1, %l4
66198
66199P6290: !_DWLD [8] (FP)
66200ldd [%i2 + 8], %f18
66201! 1 addresses covered
66202fmovs %f19, %f15
66203!---- flushing fp results buffer to %f30 ----
66204fmovd %f0, %f30
66205fmovd %f2, %f30
66206fmovd %f4, %f30
66207fmovd %f6, %f30
66208fmovd %f8, %f30
66209fmovd %f10, %f30
66210fmovd %f12, %f30
66211fmovd %f14, %f30
66212!--
66213
66214P6291: !_PREFETCH [13] (Int)
66215sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
66216sub %i0, %i2, %i2
66217prefetch [%i2 + 4], 21
66218
66219P6292: !_MEMBAR (FP)
66220
66221P6293: !_BSTC [13] (maybe <- 0x4280004e) (FP) (Branch target of P6052)
66222wr %g0, 0xe0, %asi
66223! preparing store val #0, next val will be in f32
66224fmovs %f16, %f20
66225fadds %f16, %f17, %f16
66226! preparing store val #1, next val will be in f33
66227fmovs %f16, %f21
66228fadds %f16, %f17, %f16
66229! preparing store val #2, next val will be in f35
66230fmovd %f20, %f32
66231fmovs %f16, %f21
66232fadds %f16, %f17, %f16
66233fmovd %f20, %f34
66234membar #Sync
66235stda %f32, [%i2 + 0 ] %asi
66236ba P6294
66237nop
66238
66239TARGET6052:
66240ba RET6052
66241nop
66242
66243
66244P6294: !_MEMBAR (FP)
66245membar #StoreLoad
66246
66247P6295: !_ST [7] (maybe <- 0x300006b) (Int)
66248sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
66249add %i0, %i3, %i3
66250stw %l4, [%i3 + 4 ]
66251add %l4, 1, %l4
66252
66253P6296: !_LDD [8] (Int)
66254ldd [%i3 + 8], %l6
66255! move %l7(lower) -> %o0(lower)
66256or %l7, %o0, %o0
66257
66258P6297: !_MEMBAR (FP)
66259
66260P6298: !_BSTC [5] (maybe <- 0x42800051) (FP)
66261wr %g0, 0xe0, %asi
66262! preparing store val #0, next val will be in f32
66263fmovs %f16, %f20
66264fadds %f16, %f17, %f16
66265! preparing store val #1, next val will be in f33
66266fmovs %f16, %f21
66267fadds %f16, %f17, %f16
66268! preparing store val #2, next val will be in f35
66269fmovd %f20, %f32
66270fmovs %f16, %f21
66271fadds %f16, %f17, %f16
66272fmovd %f20, %f34
66273membar #Sync
66274stda %f32, [%i1 + 0 ] %asi
66275
66276P6299: !_MEMBAR (FP)
66277
66278P6300: !_BSTC [9] (maybe <- 0x42800054) (FP)
66279wr %g0, 0xe0, %asi
66280sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
66281add %i0, %i2, %i2
66282! preparing store val #0, next val will be in f32
66283fmovs %f16, %f20
66284fadds %f16, %f17, %f16
66285! preparing store val #1, next val will be in f33
66286fmovs %f16, %f21
66287fadds %f16, %f17, %f16
66288! preparing store val #2, next val will be in f35
66289fmovd %f20, %f32
66290fmovs %f16, %f21
66291fadds %f16, %f17, %f16
66292fmovd %f20, %f34
66293membar #Sync
66294stda %f32, [%i2 + 0 ] %asi
66295
66296P6301: !_MEMBAR (FP) (Branch target of P6046)
66297membar #StoreLoad
66298ba P6302
66299nop
66300
66301TARGET6046:
66302ba RET6046
66303nop
66304
66305
66306P6302: !_DWST [16] (maybe <- 0x300006c) (Int)
66307sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
66308sub %i0, %i3, %i3
66309sllx %l4, 32, %l7
66310add %l4, 1, %l4
66311or %l7, %l4, %l7
66312stx %l7, [%i3 + 0]
66313add %l4, 1, %l4
66314
66315P6303: !_DWST_BINIT [15] (maybe <- 0x300006e) (Int)
66316wr %g0, 0xe2, %asi
66317sllx %l4, 32, %l6
66318add %l4, 1, %l4
66319or %l6, %l4, %l6
66320stxa %l6, [%i3 + 0] %asi
66321add %l4, 1, %l4
66322
66323P6304: !_MEMBAR (Int) (CBR)
66324membar #StoreLoad
66325
66326! cbranch
66327andcc %l0, 1, %g0
66328be,pt %xcc, TARGET6304
66329nop
66330RET6304:
66331
66332! lfsr step begin
66333srlx %l0, 1, %l3
66334xnor %l3, %l0, %l3
66335sllx %l3, 63, %l3
66336or %l3, %l0, %l0
66337srlx %l0, 1, %l0
66338
66339
66340P6305: !_DWST [10] (maybe <- 0x3000070) (Int)
66341sllx %l4, 32, %l6
66342add %l4, 1, %l4
66343or %l6, %l4, %l6
66344stx %l6, [%i2 + 0]
66345add %l4, 1, %l4
66346
66347P6306: !_SWAP [6] (maybe <- 0x3000072) (Int)
66348sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
66349add %i0, %i2, %i2
66350mov %l4, %o1
66351swap [%i2 + 0], %o1
66352! move %o1(lower) -> %o1(upper)
66353sllx %o1, 32, %o1
66354add %l4, 1, %l4
66355
66356P6307: !_DWST_BINIT [2] (maybe <- 0x3000073) (Int) (LE)
66357wr %g0, 0xea, %asi
66358! Change single-word-level endianess (big endian <-> little endian)
66359sethi %hi(0xff00ff00), %o5
66360or %o5, %lo(0xff00ff00), %o5
66361and %l4, %o5, %l6
66362srl %l6, 8, %l6
66363sll %l4, 8, %l3
66364and %l3, %o5, %l3
66365or %l3, %l6, %l3
66366srl %l3, 16, %l6
66367sll %l3, 16, %l3
66368srl %l3, 0, %l3
66369or %l3, %l6, %l3
66370sllx %l3, 32, %l3
66371stxa %l3, [%i0 + 8 ] %asi
66372add %l4, 1, %l4
66373
66374P6308: !_MEMBAR (Int) (LE)
66375membar #StoreLoad
66376
66377P6309: !_SWAP [3] (maybe <- 0x3000074) (Int)
66378mov %l4, %l3
66379swap [%i1 + 0], %l3
66380! move %l3(lower) -> %o1(lower)
66381srl %l3, 0, %l7
66382or %l7, %o1, %o1
66383add %l4, 1, %l4
66384
66385P6310: !_MEMBAR (FP) (CBR)
66386
66387! cbranch
66388andcc %l0, 1, %g0
66389be,pn %xcc, TARGET6310
66390nop
66391RET6310:
66392
66393! lfsr step begin
66394srlx %l0, 1, %l6
66395xnor %l6, %l0, %l6
66396sllx %l6, 63, %l6
66397or %l6, %l0, %l0
66398srlx %l0, 1, %l0
66399
66400
66401P6311: !_BSTC [3] (maybe <- 0x42800057) (FP)
66402wr %g0, 0xe0, %asi
66403! preparing store val #0, next val will be in f32
66404fmovs %f16, %f20
66405fadds %f16, %f17, %f16
66406! preparing store val #1, next val will be in f33
66407fmovs %f16, %f21
66408fadds %f16, %f17, %f16
66409! preparing store val #2, next val will be in f35
66410fmovd %f20, %f32
66411fmovs %f16, %f21
66412fadds %f16, %f17, %f16
66413fmovd %f20, %f34
66414membar #Sync
66415stda %f32, [%i1 + 0 ] %asi
66416
66417P6312: !_MEMBAR (FP)
66418membar #StoreLoad
66419
66420P6313: !_LD [12] (Int)
66421sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
66422sub %i0, %i3, %i3
66423lduw [%i3 + 0], %o2
66424! move %o2(lower) -> %o2(upper)
66425sllx %o2, 32, %o2
66426
66427P6314: !_DWLD [14] (FP)
66428ldd [%i3 + 8], %f0
66429! 1 addresses covered
66430fmovs %f1, %f0
66431
66432P6315: !_DWLD [13] (Int)
66433ldx [%i3 + 0], %l3
66434! move %l3(upper) -> %o2(lower)
66435srlx %l3, 32, %o5
66436or %o5, %o2, %o2
66437! move %l3(lower) -> %o3(upper)
66438sllx %l3, 32, %o3
66439
66440P6316: !_ST [1] (maybe <- 0x3000075) (Int) (LE)
66441wr %g0, 0x88, %asi
66442! Change single-word-level endianess (big endian <-> little endian)
66443sethi %hi(0xff00ff00), %l7
66444or %l7, %lo(0xff00ff00), %l7
66445and %l4, %l7, %o5
66446srl %o5, 8, %o5
66447sll %l4, 8, %l6
66448and %l6, %l7, %l6
66449or %l6, %o5, %l6
66450srl %l6, 16, %o5
66451sll %l6, 16, %l6
66452srl %l6, 0, %l6
66453or %l6, %o5, %l6
66454stwa %l6, [%i0 + 4] %asi
66455add %l4, 1, %l4
66456
66457P6317: !_ST [9] (maybe <- 0x3000076) (Int)
66458sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
66459add %i0, %i2, %i2
66460stw %l4, [%i2 + 0 ]
66461add %l4, 1, %l4
66462
66463P6318: !_PREFETCH [9] (Int)
66464prefetch [%i2 + 0], 4
66465
66466P6319: !_MEMBAR (FP)
66467
66468P6320: !_BST [14] (maybe <- 0x4280005a) (FP)
66469wr %g0, 0xf0, %asi
66470! preparing store val #0, next val will be in f32
66471fmovs %f16, %f20
66472fadds %f16, %f17, %f16
66473! preparing store val #1, next val will be in f33
66474fmovs %f16, %f21
66475fadds %f16, %f17, %f16
66476! preparing store val #2, next val will be in f35
66477fmovd %f20, %f32
66478fmovs %f16, %f21
66479fadds %f16, %f17, %f16
66480fmovd %f20, %f34
66481membar #Sync
66482stda %f32, [%i3 + 0 ] %asi
66483
66484P6321: !_MEMBAR (FP)
66485membar #StoreLoad
66486
66487P6322: !_BLD [22] (FP)
66488wr %g0, 0xf0, %asi
66489sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
66490add %i0, %i3, %i3
66491ldda [%i3 + 0] %asi, %f32
66492membar #Sync
66493! 3 addresses covered
66494fmovd %f32, %f18
66495fmovs %f18, %f1
66496fmovs %f19, %f2
66497fmovd %f34, %f18
66498fmovs %f19, %f3
66499
66500P6323: !_MEMBAR (FP)
66501
66502P6324: !_BST [23] (maybe <- 0x4280005d) (FP)
66503wr %g0, 0xf0, %asi
66504! preparing store val #0, next val will be in f32
66505fmovs %f16, %f20
66506fadds %f16, %f17, %f16
66507! preparing store val #1, next val will be in f33
66508fmovs %f16, %f21
66509fadds %f16, %f17, %f16
66510! preparing store val #2, next val will be in f35
66511fmovd %f20, %f32
66512fmovs %f16, %f21
66513fadds %f16, %f17, %f16
66514fmovd %f20, %f34
66515membar #Sync
66516stda %f32, [%i3 + 0 ] %asi
66517
66518P6325: !_MEMBAR (FP)
66519membar #StoreLoad
66520
66521P6326: !_CAS [0] (maybe <- 0x3000077) (Int)
66522lduw [%i0], %l3
66523mov %l3, %l6
66524! move %l6(lower) -> %o3(lower)
66525or %l6, %o3, %o3
66526mov %l4, %o4
66527cas [%i0], %l6, %o4
66528! move %o4(lower) -> %o4(upper)
66529sllx %o4, 32, %o4
66530add %l4, 1, %l4
66531
66532P6327: !_CASX [8] (maybe <- 0x3000078) (Int) (CBR)
66533sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2
66534add %i0, %i2, %i2
66535add %i2, 8, %l7
66536ldx [%l7], %l3
66537! move %l3(upper) -> %o4(lower)
66538srlx %l3, 32, %l6
66539or %l6, %o4, %o4
66540!---- flushing int results buffer----
66541mov %o0, %l5
66542mov %o1, %l5
66543mov %o2, %l5
66544mov %o3, %l5
66545mov %o4, %l5
66546! move %l3(lower) -> %o0(upper)
66547sllx %l3, 32, %o0
66548mov %l3, %l6
66549mov %l4, %l3
66550casx [%l7], %l6, %l3
66551! move %l3(upper) -> %o0(lower)
66552srlx %l3, 32, %l6
66553or %l6, %o0, %o0
66554! move %l3(lower) -> %o1(upper)
66555sllx %l3, 32, %o1
66556add %l4, 1, %l4
66557
66558! cbranch
66559andcc %l0, 1, %g0
66560be,pn %xcc, TARGET6327
66561nop
66562RET6327:
66563
66564! lfsr step begin
66565srlx %l0, 1, %l6
66566xnor %l6, %l0, %l6
66567sllx %l6, 63, %l6
66568or %l6, %l0, %l0
66569srlx %l0, 1, %l0
66570
66571
66572P6328: !_MEMBAR (FP)
66573
66574P6329: !_BST [11] (maybe <- 0x42800060) (FP)
66575wr %g0, 0xf0, %asi
66576sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
66577add %i0, %i3, %i3
66578! preparing store val #0, next val will be in f32
66579fmovs %f16, %f20
66580fadds %f16, %f17, %f16
66581! preparing store val #1, next val will be in f33
66582fmovs %f16, %f21
66583fadds %f16, %f17, %f16
66584! preparing store val #2, next val will be in f35
66585fmovd %f20, %f32
66586fmovs %f16, %f21
66587fadds %f16, %f17, %f16
66588fmovd %f20, %f34
66589membar #Sync
66590stda %f32, [%i3 + 0 ] %asi
66591
66592P6330: !_MEMBAR (FP)
66593membar #StoreLoad
66594
66595P6331: !_DWST_BINIT [13] (maybe <- 0x3000079) (Int)
66596wr %g0, 0xe2, %asi
66597sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
66598sub %i0, %i2, %i2
66599sllx %l4, 32, %l6
66600add %l4, 1, %l4
66601or %l6, %l4, %l6
66602stxa %l6, [%i2 + 0] %asi
66603add %l4, 1, %l4
66604
66605P6332: !_MEMBAR (Int)
66606membar #StoreLoad
66607
66608P6333: !_LDD [7] (Int)
66609sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3
66610add %i0, %i3, %i3
66611ldd [%i3 + 0], %l6
66612! move %l6(lower) -> %o1(lower)
66613or %l6, %o1, %o1
66614! move %l7(lower) -> %o2(upper)
66615sllx %l7, 32, %o2
66616
66617P6334: !_DWLD [6] (Int)
66618sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
66619sub %i0, %i2, %i2
66620ldx [%i2 + 0], %l7
66621! move %l7(upper) -> %o2(lower)
66622srlx %l7, 32, %l6
66623or %l6, %o2, %o2
66624! move %l7(lower) -> %o3(upper)
66625sllx %l7, 32, %o3
66626
66627P6335: !_LDD [16] (Int) (Branch target of P6448)
66628sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
66629sub %i0, %i3, %i3
66630ldd [%i3 + 0], %l6
66631! move %l6(lower) -> %o3(lower)
66632or %l6, %o3, %o3
66633! move %l7(lower) -> %o4(upper)
66634sllx %l7, 32, %o4
66635ba P6336
66636nop
66637
66638TARGET6448:
66639ba RET6448
66640nop
66641
66642
66643P6336: !_MEMBAR (FP)
66644
66645P6337: !_BSTC [18] (maybe <- 0x42800063) (FP)
66646wr %g0, 0xe0, %asi
66647sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
66648sub %i0, %i2, %i2
66649! preparing store val #0, next val will be in f32
66650fmovs %f16, %f20
66651fadds %f16, %f17, %f16
66652! preparing store val #1, next val will be in f33
66653fmovs %f16, %f21
66654fadds %f16, %f17, %f16
66655! preparing store val #2, next val will be in f35
66656fmovd %f20, %f32
66657fmovs %f16, %f21
66658fadds %f16, %f17, %f16
66659fmovd %f20, %f34
66660membar #Sync
66661stda %f32, [%i2 + 0 ] %asi
66662
66663P6338: !_MEMBAR (FP)
66664membar #StoreLoad
66665
66666P6339: !_DWST [13] (maybe <- 0x300007b) (Int)
66667sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
66668sub %i0, %i3, %i3
66669sllx %l4, 32, %o5
66670add %l4, 1, %l4
66671or %o5, %l4, %o5
66672stx %o5, [%i3 + 0]
66673add %l4, 1, %l4
66674
66675P6340: !_LD [22] (Int)
66676sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
66677add %i0, %i2, %i2
66678lduw [%i2 + 4], %o5
66679! move %o5(lower) -> %o4(lower)
66680or %o5, %o4, %o4
66681!---- flushing int results buffer----
66682mov %o0, %l5
66683mov %o1, %l5
66684mov %o2, %l5
66685mov %o3, %l5
66686mov %o4, %l5
66687
66688P6341: !_CAS [14] (maybe <- 0x300007d) (Int)
66689add %i3, 12, %l6
66690lduw [%l6], %o0
66691mov %o0, %l3
66692! move %l3(lower) -> %o0(upper)
66693sllx %l3, 32, %o0
66694mov %l4, %o5
66695cas [%l6], %l3, %o5
66696! move %o5(lower) -> %o0(lower)
66697srl %o5, 0, %l3
66698or %l3, %o0, %o0
66699add %l4, 1, %l4
66700
66701P6342: !_REPLACEMENT [3] (Int)
66702sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
66703sub %i0, %i3, %i3
66704sethi %hi(0x20000), %l3
66705ld [%i3+0], %l7
66706st %l7, [%i3+0]
66707add %i3, %l3, %l6
66708ld [%l6+0], %l7
66709st %l7, [%l6+0]
66710add %l6, %l3, %l6
66711ld [%l6+0], %l7
66712st %l7, [%l6+0]
66713add %l6, %l3, %l6
66714ld [%l6+0], %l7
66715st %l7, [%l6+0]
66716add %l6, %l3, %l6
66717ld [%l6+0], %l7
66718st %l7, [%l6+0]
66719add %l6, %l3, %l6
66720ld [%l6+0], %l7
66721st %l7, [%l6+0]
66722add %l6, %l3, %l6
66723ld [%l6+0], %l7
66724st %l7, [%l6+0]
66725add %l6, %l3, %l6
66726ld [%l6+0], %l7
66727st %l7, [%l6+0]
66728
66729P6343: !_CAS [19] (maybe <- 0x300007e) (Int)
66730sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i2
66731sub %i0, %i2, %i2
66732add %i2, 4, %l3
66733lduw [%l3], %o1
66734mov %o1, %o5
66735! move %o5(lower) -> %o1(upper)
66736sllx %o5, 32, %o1
66737mov %l4, %l7
66738cas [%l3], %o5, %l7
66739! move %l7(lower) -> %o1(lower)
66740srl %l7, 0, %o5
66741or %o5, %o1, %o1
66742add %l4, 1, %l4
66743
66744P6344: !_MEMBAR (FP)
66745
66746P6345: !_BSTC [10] (maybe <- 0x42800066) (FP)
66747wr %g0, 0xe0, %asi
66748sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
66749add %i0, %i3, %i3
66750! preparing store val #0, next val will be in f32
66751fmovs %f16, %f20
66752fadds %f16, %f17, %f16
66753! preparing store val #1, next val will be in f33
66754fmovs %f16, %f21
66755fadds %f16, %f17, %f16
66756! preparing store val #2, next val will be in f35
66757fmovd %f20, %f32
66758fmovs %f16, %f21
66759fadds %f16, %f17, %f16
66760fmovd %f20, %f34
66761membar #Sync
66762stda %f32, [%i3 + 0 ] %asi
66763
66764P6346: !_MEMBAR (FP)
66765membar #StoreLoad
66766
66767P6347: !_ST_BINIT [11] (maybe <- 0x300007f) (Int) (LE)
66768wr %g0, 0xea, %asi
66769! Change single-word-level endianess (big endian <-> little endian)
66770sethi %hi(0xff00ff00), %o5
66771or %o5, %lo(0xff00ff00), %o5
66772and %l4, %o5, %l3
66773srl %l3, 8, %l3
66774sll %l4, 8, %l7
66775and %l7, %o5, %l7
66776or %l7, %l3, %l7
66777srl %l7, 16, %l3
66778sll %l7, 16, %l7
66779srl %l7, 0, %l7
66780or %l7, %l3, %l7
66781stwa %l7, [%i3 + 12] %asi
66782add %l4, 1, %l4
66783
66784P6348: !_MEMBAR (Int) (LE)
66785membar #StoreLoad
66786
66787P6349: !_DWST_BINIT [1] (maybe <- 0x3000080) (Int)
66788wr %g0, 0xe2, %asi
66789sllx %l4, 32, %l6
66790add %l4, 1, %l4
66791or %l6, %l4, %l6
66792stxa %l6, [%i0 + 0] %asi
66793add %l4, 1, %l4
66794
66795P6350: !_MEMBAR (Int)
66796membar #StoreLoad
66797
66798P6351: !_CAS [16] (maybe <- 0x3000082) (Int)
66799sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
66800sub %i0, %i2, %i2
66801add %i2, 4, %l6
66802lduw [%l6], %o2
66803mov %o2, %l3
66804! move %l3(lower) -> %o2(upper)
66805sllx %l3, 32, %o2
66806mov %l4, %o5
66807cas [%l6], %l3, %o5
66808! move %o5(lower) -> %o2(lower)
66809srl %o5, 0, %l3
66810or %l3, %o2, %o2
66811add %l4, 1, %l4
66812
66813P6352: !_DWST_BINIT [7] (maybe <- 0x3000083) (Int)
66814wr %g0, 0xe2, %asi
66815sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
66816sub %i0, %i3, %i3
66817sllx %l4, 32, %l3
66818add %l4, 1, %l4
66819or %l3, %l4, %l3
66820stxa %l3, [%i3 + 0] %asi
66821add %l4, 1, %l4
66822
66823P6353: !_MEMBAR (Int)
66824membar #StoreLoad
66825
66826P6354: !_DWST [1] (maybe <- 0x3000085) (Int)
66827sllx %l4, 32, %o5
66828add %l4, 1, %l4
66829or %o5, %l4, %o5
66830stx %o5, [%i0 + 0]
66831add %l4, 1, %l4
66832
66833P6355: !_MEMBAR (FP)
66834membar #StoreLoad
66835
66836P6356: !_BLD [22] (FP)
66837wr %g0, 0xf0, %asi
66838sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
66839add %i0, %i2, %i2
66840ldda [%i2 + 0] %asi, %f32
66841membar #Sync
66842! 3 addresses covered
66843fmovd %f32, %f4
66844fmovd %f34, %f18
66845fmovs %f19, %f6
66846
66847P6357: !_MEMBAR (FP)
66848
66849P6358: !_REPLACEMENT [3] (Int) (CBR)
66850sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
66851sub %i0, %i3, %i3
66852sethi %hi(0x20000), %l7
66853ld [%i3+0], %l3
66854st %l3, [%i3+0]
66855add %i3, %l7, %o5
66856ld [%o5+0], %l3
66857st %l3, [%o5+0]
66858add %o5, %l7, %o5
66859ld [%o5+0], %l3
66860st %l3, [%o5+0]
66861add %o5, %l7, %o5
66862ld [%o5+0], %l3
66863st %l3, [%o5+0]
66864add %o5, %l7, %o5
66865ld [%o5+0], %l3
66866st %l3, [%o5+0]
66867add %o5, %l7, %o5
66868ld [%o5+0], %l3
66869st %l3, [%o5+0]
66870add %o5, %l7, %o5
66871ld [%o5+0], %l3
66872st %l3, [%o5+0]
66873add %o5, %l7, %o5
66874ld [%o5+0], %l3
66875st %l3, [%o5+0]
66876
66877! cbranch
66878andcc %l0, 1, %g0
66879be,pt %xcc, TARGET6358
66880nop
66881RET6358:
66882
66883! lfsr step begin
66884srlx %l0, 1, %l6
66885xnor %l6, %l0, %l6
66886sllx %l6, 63, %l6
66887or %l6, %l0, %l0
66888srlx %l0, 1, %l0
66889
66890
66891P6359: !_ST [5] (maybe <- 0x3000087) (Int)
66892stw %l4, [%i1 + 12 ]
66893add %l4, 1, %l4
66894
66895P6360: !_DWLD [23] (Int)
66896ldx [%i2 + 8], %o3
66897! move %o3(lower) -> %o3(upper)
66898sllx %o3, 32, %o3
66899
66900P6361: !_MEMBAR (FP)
66901membar #StoreLoad
66902
66903P6362: !_BLD [6] (FP)
66904wr %g0, 0xf0, %asi
66905sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
66906sub %i0, %i2, %i2
66907ldda [%i2 + 0] %asi, %f32
66908membar #Sync
66909! 3 addresses covered
66910fmovd %f32, %f18
66911fmovs %f18, %f7
66912fmovs %f19, %f8
66913fmovd %f34, %f18
66914fmovs %f19, %f9
66915
66916P6363: !_MEMBAR (FP)
66917
66918P6364: !_DWST_BINIT [17] (maybe <- 0x3000088) (Int)
66919wr %g0, 0xe2, %asi
66920sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
66921sub %i0, %i3, %i3
66922mov %l4, %o5
66923stxa %o5, [%i3 + 8] %asi
66924add %l4, 1, %l4
66925
66926P6365: !_MEMBAR (Int)
66927membar #StoreLoad
66928
66929P6366: !_LD [13] (Int)
66930sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
66931sub %i0, %i2, %i2
66932lduw [%i2 + 4], %o5
66933! move %o5(lower) -> %o3(lower)
66934or %o5, %o3, %o3
66935
66936P6367: !_LD [15] (Int)
66937lduw [%i3 + 0], %o4
66938! move %o4(lower) -> %o4(upper)
66939sllx %o4, 32, %o4
66940
66941P6368: !_CAS [17] (maybe <- 0x3000089) (Int)
66942add %i3, 12, %o5
66943lduw [%o5], %l6
66944mov %l6, %l7
66945! move %l7(lower) -> %o4(lower)
66946or %l7, %o4, %o4
66947!---- flushing int results buffer----
66948mov %o0, %l5
66949mov %o1, %l5
66950mov %o2, %l5
66951mov %o3, %l5
66952mov %o4, %l5
66953mov %l4, %o0
66954cas [%o5], %l7, %o0
66955! move %o0(lower) -> %o0(upper)
66956sllx %o0, 32, %o0
66957add %l4, 1, %l4
66958
66959P6369: !_PREFETCH [20] (Int)
66960sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
66961sub %i0, %i3, %i3
66962prefetch [%i3 + 12], 20
66963
66964P6370: !_MEMBAR (FP)
66965
66966P6371: !_BSTC [11] (maybe <- 0x42800069) (FP)
66967wr %g0, 0xe0, %asi
66968sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
66969add %i0, %i2, %i2
66970! preparing store val #0, next val will be in f32
66971fmovs %f16, %f20
66972fadds %f16, %f17, %f16
66973! preparing store val #1, next val will be in f33
66974fmovs %f16, %f21
66975fadds %f16, %f17, %f16
66976! preparing store val #2, next val will be in f35
66977fmovd %f20, %f32
66978fmovs %f16, %f21
66979fadds %f16, %f17, %f16
66980fmovd %f20, %f34
66981membar #Sync
66982stda %f32, [%i2 + 0 ] %asi
66983
66984P6372: !_MEMBAR (FP)
66985membar #StoreLoad
66986
66987P6373: !_PREFETCH [8] (Int) (Branch target of P6500)
66988sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
66989sub %i0, %i3, %i3
66990prefetch [%i3 + 12], 23
66991ba P6374
66992nop
66993
66994TARGET6500:
66995ba RET6500
66996nop
66997
66998
66999P6374: !_SWAP [23] (maybe <- 0x300008a) (Int)
67000sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
67001add %i0, %i2, %i2
67002mov %l4, %o5
67003swap [%i2 + 12], %o5
67004! move %o5(lower) -> %o0(lower)
67005srl %o5, 0, %l6
67006or %l6, %o0, %o0
67007add %l4, 1, %l4
67008
67009P6375: !_PREFETCH [22] (Int)
67010prefetch [%i2 + 4], 0
67011
67012P6376: !_MEMBAR (FP)
67013membar #StoreLoad
67014
67015P6377: !_BLD [11] (FP) (Branch target of P6076)
67016wr %g0, 0xf0, %asi
67017sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
67018add %i0, %i3, %i3
67019ldda [%i3 + 0] %asi, %f32
67020membar #Sync
67021! 3 addresses covered
67022fmovd %f32, %f10
67023fmovd %f34, %f18
67024fmovs %f19, %f12
67025ba P6378
67026nop
67027
67028TARGET6076:
67029ba RET6076
67030nop
67031
67032
67033P6378: !_MEMBAR (FP)
67034
67035P6379: !_BSTC [23] (maybe <- 0x4280006c) (FP)
67036wr %g0, 0xe0, %asi
67037! preparing store val #0, next val will be in f32
67038fmovs %f16, %f20
67039fadds %f16, %f17, %f16
67040! preparing store val #1, next val will be in f33
67041fmovs %f16, %f21
67042fadds %f16, %f17, %f16
67043! preparing store val #2, next val will be in f35
67044fmovd %f20, %f32
67045fmovs %f16, %f21
67046fadds %f16, %f17, %f16
67047fmovd %f20, %f34
67048membar #Sync
67049stda %f32, [%i2 + 0 ] %asi
67050
67051P6380: !_MEMBAR (FP)
67052
67053P6381: !_BST [23] (maybe <- 0x4280006f) (FP)
67054wr %g0, 0xf0, %asi
67055! preparing store val #0, next val will be in f32
67056fmovs %f16, %f20
67057fadds %f16, %f17, %f16
67058! preparing store val #1, next val will be in f33
67059fmovs %f16, %f21
67060fadds %f16, %f17, %f16
67061! preparing store val #2, next val will be in f35
67062fmovd %f20, %f32
67063fmovs %f16, %f21
67064fadds %f16, %f17, %f16
67065fmovd %f20, %f34
67066membar #Sync
67067stda %f32, [%i2 + 0 ] %asi
67068
67069P6382: !_MEMBAR (FP)
67070membar #StoreLoad
67071
67072P6383: !_DWST_BINIT [7] (maybe <- 0x300008b) (Int)
67073wr %g0, 0xe2, %asi
67074sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
67075sub %i0, %i2, %i2
67076sllx %l4, 32, %l7
67077add %l4, 1, %l4
67078or %l7, %l4, %l7
67079stxa %l7, [%i2 + 0] %asi
67080add %l4, 1, %l4
67081
67082P6384: !_MEMBAR (Int)
67083membar #StoreLoad
67084
67085P6385: !_CAS [1] (maybe <- 0x300008d) (Int)
67086add %i0, 4, %l7
67087lduw [%l7], %o1
67088mov %o1, %l6
67089! move %l6(lower) -> %o1(upper)
67090sllx %l6, 32, %o1
67091mov %l4, %l3
67092cas [%l7], %l6, %l3
67093! move %l3(lower) -> %o1(lower)
67094srl %l3, 0, %l6
67095or %l6, %o1, %o1
67096add %l4, 1, %l4
67097
67098P6386: !_PREFETCH [18] (Int)
67099sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS3_O), %i3
67100sub %i0, %i3, %i3
67101prefetch [%i3 + 0], 0
67102
67103P6387: !_CAS [11] (maybe <- 0x300008e) (Int) (Branch target of P6209)
67104sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2
67105add %i0, %i2, %i2
67106add %i2, 12, %l7
67107lduw [%l7], %o2
67108mov %o2, %l6
67109! move %l6(lower) -> %o2(upper)
67110sllx %l6, 32, %o2
67111mov %l4, %l3
67112cas [%l7], %l6, %l3
67113! move %l3(lower) -> %o2(lower)
67114srl %l3, 0, %l6
67115or %l6, %o2, %o2
67116add %l4, 1, %l4
67117ba P6388
67118nop
67119
67120TARGET6209:
67121ba RET6209
67122nop
67123
67124
67125P6388: !_DWLD [3] (Int)
67126ldx [%i1 + 0], %o3
67127! move %o3(upper) -> %o3(upper)
67128! move %o3(lower) -> %o3(lower)
67129
67130P6389: !_PREFETCH [4] (Int)
67131prefetch [%i1 + 4], 20
67132
67133P6390: !_DWLD [9] (Int)
67134ldx [%i2 + 0], %o4
67135! move %o4(upper) -> %o4(upper)
67136! move %o4(lower) -> %o4(lower)
67137!---- flushing int results buffer----
67138mov %o0, %l5
67139mov %o1, %l5
67140mov %o2, %l5
67141mov %o3, %l5
67142mov %o4, %l5
67143
67144P6391: !_DWLD [19] (Int)
67145ldx [%i3 + 0], %o0
67146! move %o0(upper) -> %o0(upper)
67147! move %o0(lower) -> %o0(lower)
67148
67149P6392: !_MEMBAR (FP)
67150
67151P6393: !_BST [0] (maybe <- 0x42800072) (FP)
67152wr %g0, 0xf0, %asi
67153! preparing store val #0, next val will be in f32
67154fmovs %f16, %f20
67155fadds %f16, %f17, %f16
67156! preparing store val #1, next val will be in f33
67157fmovs %f16, %f21
67158fadds %f16, %f17, %f16
67159! preparing store val #2, next val will be in f35
67160fmovd %f20, %f32
67161fmovs %f16, %f21
67162fadds %f16, %f17, %f16
67163fmovd %f20, %f34
67164membar #Sync
67165stda %f32, [%i0 + 0 ] %asi
67166
67167P6394: !_MEMBAR (FP)
67168membar #StoreLoad
67169
67170P6395: !_PREFETCH [15] (Int)
67171sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
67172sub %i0, %i3, %i3
67173prefetch [%i3 + 0], 0
67174
67175P6396: !_CAS [5] (maybe <- 0x300008f) (Int) (CBR)
67176add %i1, 12, %o5
67177lduw [%o5], %o1
67178mov %o1, %l7
67179! move %l7(lower) -> %o1(upper)
67180sllx %l7, 32, %o1
67181mov %l4, %l6
67182cas [%o5], %l7, %l6
67183! move %l6(lower) -> %o1(lower)
67184srl %l6, 0, %l7
67185or %l7, %o1, %o1
67186add %l4, 1, %l4
67187
67188! cbranch
67189andcc %l0, 1, %g0
67190be,pn %xcc, TARGET6396
67191nop
67192RET6396:
67193
67194! lfsr step begin
67195srlx %l0, 1, %l7
67196xnor %l7, %l0, %l7
67197sllx %l7, 63, %l7
67198or %l7, %l0, %l0
67199srlx %l0, 1, %l0
67200
67201
67202P6397: !_MEMBAR (FP)
67203membar #StoreLoad
67204
67205P6398: !_BLD [18] (FP)
67206wr %g0, 0xf0, %asi
67207sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
67208add %i0, %i2, %i2
67209ldda [%i2 + 0] %asi, %f32
67210membar #Sync
67211! 3 addresses covered
67212fmovd %f32, %f18
67213fmovs %f18, %f13
67214fmovs %f19, %f14
67215fmovd %f34, %f18
67216fmovs %f19, %f15
67217!---- flushing fp results buffer to %f30 ----
67218fmovd %f0, %f30
67219fmovd %f2, %f30
67220fmovd %f4, %f30
67221fmovd %f6, %f30
67222fmovd %f8, %f30
67223fmovd %f10, %f30
67224fmovd %f12, %f30
67225fmovd %f14, %f30
67226!--
67227
67228P6399: !_MEMBAR (FP)
67229
67230P6400: !_SWAP [11] (maybe <- 0x3000090) (Int)
67231sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
67232add %i0, %i3, %i3
67233mov %l4, %o2
67234swap [%i3 + 12], %o2
67235! move %o2(lower) -> %o2(upper)
67236sllx %o2, 32, %o2
67237add %l4, 1, %l4
67238
67239P6401: !_MEMBAR (FP)
67240
67241P6402: !_BST [4] (maybe <- 0x42800075) (FP)
67242wr %g0, 0xf0, %asi
67243! preparing store val #0, next val will be in f32
67244fmovs %f16, %f20
67245fadds %f16, %f17, %f16
67246! preparing store val #1, next val will be in f33
67247fmovs %f16, %f21
67248fadds %f16, %f17, %f16
67249! preparing store val #2, next val will be in f35
67250fmovd %f20, %f32
67251fmovs %f16, %f21
67252fadds %f16, %f17, %f16
67253fmovd %f20, %f34
67254membar #Sync
67255stda %f32, [%i1 + 0 ] %asi
67256
67257P6403: !_MEMBAR (FP)
67258membar #StoreLoad
67259
67260P6404: !_BLD [16] (FP)
67261wr %g0, 0xf0, %asi
67262sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
67263sub %i0, %i2, %i2
67264ldda [%i2 + 0] %asi, %f0
67265membar #Sync
67266! 3 addresses covered
67267fmovs %f3, %f2
67268
67269P6405: !_MEMBAR (FP)
67270
67271P6406: !_DWST [5] (maybe <- 0x3000091) (Int)
67272mov %l4, %l7
67273stx %l7, [%i1 + 8]
67274add %l4, 1, %l4
67275
67276P6407: !_LDD [15] (Int)
67277ldd [%i2 + 0], %l6
67278! move %l6(lower) -> %o2(lower)
67279or %l6, %o2, %o2
67280! move %l7(lower) -> %o3(upper)
67281sllx %l7, 32, %o3
67282
67283P6408: !_LD [23] (Int)
67284sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
67285add %i0, %i3, %i3
67286lduw [%i3 + 12], %l6
67287! move %l6(lower) -> %o3(lower)
67288or %l6, %o3, %o3
67289
67290P6409: !_MEMBAR (FP)
67291
67292P6410: !_BST [2] (maybe <- 0x42800078) (FP)
67293wr %g0, 0xf0, %asi
67294! preparing store val #0, next val will be in f32
67295fmovs %f16, %f20
67296fadds %f16, %f17, %f16
67297! preparing store val #1, next val will be in f33
67298fmovs %f16, %f21
67299fadds %f16, %f17, %f16
67300! preparing store val #2, next val will be in f35
67301fmovd %f20, %f32
67302fmovs %f16, %f21
67303fadds %f16, %f17, %f16
67304fmovd %f20, %f34
67305membar #Sync
67306stda %f32, [%i0 + 0 ] %asi
67307
67308P6411: !_MEMBAR (FP)
67309membar #StoreLoad
67310
67311P6412: !_CAS [0] (maybe <- 0x3000092) (Int)
67312lduw [%i0], %o4
67313mov %o4, %l6
67314! move %l6(lower) -> %o4(upper)
67315sllx %l6, 32, %o4
67316mov %l4, %l3
67317cas [%i0], %l6, %l3
67318! move %l3(lower) -> %o4(lower)
67319srl %l3, 0, %l6
67320or %l6, %o4, %o4
67321!---- flushing int results buffer----
67322mov %o0, %l5
67323mov %o1, %l5
67324mov %o2, %l5
67325mov %o3, %l5
67326mov %o4, %l5
67327add %l4, 1, %l4
67328
67329P6413: !_LD [5] (Int)
67330lduw [%i1 + 12], %o0
67331! move %o0(lower) -> %o0(upper)
67332sllx %o0, 32, %o0
67333
67334P6414: !_ST_BINIT [15] (maybe <- 0x3000093) (Int)
67335wr %g0, 0xe2, %asi
67336stwa %l4, [%i2 + 0] %asi
67337add %l4, 1, %l4
67338
67339P6415: !_MEMBAR (Int)
67340membar #StoreLoad
67341
67342P6416: !_DWST [2] (maybe <- 0x4280007b) (FP) (Branch target of P6490)
67343! preparing store val #0, next val will be in f21
67344fmovs %f16, %f21
67345fadds %f16, %f17, %f16
67346std %f20, [%i0 + 8]
67347ba P6417
67348nop
67349
67350TARGET6490:
67351ba RET6490
67352nop
67353
67354
67355P6417: !_DWLD [8] (Int) (Branch target of P6062)
67356sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
67357sub %i0, %i2, %i2
67358ldx [%i2 + 8], %l7
67359! move %l7(lower) -> %o0(lower)
67360srl %l7, 0, %l6
67361or %l6, %o0, %o0
67362ba P6418
67363nop
67364
67365TARGET6062:
67366ba RET6062
67367nop
67368
67369
67370P6418: !_MEMBAR (FP)
67371
67372P6419: !_BSTC [17] (maybe <- 0x4280007c) (FP)
67373wr %g0, 0xe0, %asi
67374sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
67375sub %i0, %i3, %i3
67376! preparing store val #0, next val will be in f32
67377fmovs %f16, %f20
67378fadds %f16, %f17, %f16
67379! preparing store val #1, next val will be in f33
67380fmovs %f16, %f21
67381fadds %f16, %f17, %f16
67382! preparing store val #2, next val will be in f35
67383fmovd %f20, %f32
67384fmovs %f16, %f21
67385fadds %f16, %f17, %f16
67386fmovd %f20, %f34
67387membar #Sync
67388stda %f32, [%i3 + 0 ] %asi
67389
67390P6420: !_MEMBAR (FP)
67391membar #StoreLoad
67392
67393P6421: !_REPLACEMENT [15] (Int) (CBR)
67394sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
67395add %i0, %i2, %i2
67396sethi %hi(0x20000), %l7
67397ld [%i2+0], %l3
67398st %l3, [%i2+0]
67399add %i2, %l7, %o5
67400ld [%o5+0], %l3
67401st %l3, [%o5+0]
67402add %o5, %l7, %o5
67403ld [%o5+0], %l3
67404st %l3, [%o5+0]
67405add %o5, %l7, %o5
67406ld [%o5+0], %l3
67407st %l3, [%o5+0]
67408add %o5, %l7, %o5
67409ld [%o5+0], %l3
67410st %l3, [%o5+0]
67411add %o5, %l7, %o5
67412ld [%o5+0], %l3
67413st %l3, [%o5+0]
67414add %o5, %l7, %o5
67415ld [%o5+0], %l3
67416st %l3, [%o5+0]
67417add %o5, %l7, %o5
67418ld [%o5+0], %l3
67419st %l3, [%o5+0]
67420
67421! cbranch
67422andcc %l0, 1, %g0
67423be,pn %xcc, TARGET6421
67424nop
67425RET6421:
67426
67427! lfsr step begin
67428srlx %l0, 1, %l6
67429xnor %l6, %l0, %l6
67430sllx %l6, 63, %l6
67431or %l6, %l0, %l0
67432srlx %l0, 1, %l0
67433
67434
67435P6422: !_DWST_BINIT [12] (maybe <- 0x3000094) (Int)
67436wr %g0, 0xe2, %asi
67437sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
67438sub %i0, %i3, %i3
67439sllx %l4, 32, %l7
67440add %l4, 1, %l4
67441or %l7, %l4, %l7
67442stxa %l7, [%i3 + 0] %asi
67443add %l4, 1, %l4
67444
67445P6423: !_MEMBAR (Int)
67446membar #StoreLoad
67447
67448P6424: !_ST [18] (maybe <- 0x3000096) (Int)
67449sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
67450add %i0, %i2, %i2
67451stw %l4, [%i2 + 0 ]
67452add %l4, 1, %l4
67453
67454P6425: !_SWAP [23] (maybe <- 0x3000097) (Int)
67455sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
67456add %i0, %i3, %i3
67457mov %l4, %o1
67458swap [%i3 + 12], %o1
67459! move %o1(lower) -> %o1(upper)
67460sllx %o1, 32, %o1
67461add %l4, 1, %l4
67462
67463P6426: !_LD [13] (Int)
67464sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
67465sub %i0, %i2, %i2
67466lduw [%i2 + 4], %l3
67467! move %l3(lower) -> %o1(lower)
67468or %l3, %o1, %o1
67469
67470P6427: !_LD [23] (Int)
67471lduw [%i3 + 12], %o2
67472! move %o2(lower) -> %o2(upper)
67473sllx %o2, 32, %o2
67474
67475P6428: !_CAS [8] (maybe <- 0x3000098) (Int)
67476sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
67477sub %i0, %i3, %i3
67478add %i3, 12, %l3
67479lduw [%l3], %l7
67480mov %l7, %o5
67481! move %o5(lower) -> %o2(lower)
67482or %o5, %o2, %o2
67483mov %l4, %o3
67484cas [%l3], %o5, %o3
67485! move %o3(lower) -> %o3(upper)
67486sllx %o3, 32, %o3
67487add %l4, 1, %l4
67488
67489P6429: !_DWST [19] (maybe <- 0x4280007f) (FP)
67490sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
67491add %i0, %i2, %i2
67492! preparing store val #0, next val will be in f20
67493fmovs %f16, %f20
67494fadds %f16, %f17, %f16
67495! preparing store val #1, next val will be in f21
67496fmovs %f16, %f21
67497fadds %f16, %f17, %f16
67498std %f20, [%i2 + 0]
67499
67500P6430: !_CASX [16] (maybe <- 0x3000099) (Int) (Branch target of P6867)
67501sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
67502sub %i0, %i3, %i3
67503ldx [%i3], %l6
67504! move %l6(upper) -> %o3(lower)
67505srlx %l6, 32, %l7
67506or %l7, %o3, %o3
67507! move %l6(lower) -> %o4(upper)
67508sllx %l6, 32, %o4
67509mov %l6, %l7
67510sllx %l4, 32, %l6
67511add %l4, 1, %l4
67512or %l4, %l6, %l6
67513casx [%i3], %l7, %l6
67514! move %l6(upper) -> %o4(lower)
67515srlx %l6, 32, %l7
67516or %l7, %o4, %o4
67517!---- flushing int results buffer----
67518mov %o0, %l5
67519mov %o1, %l5
67520mov %o2, %l5
67521mov %o3, %l5
67522mov %o4, %l5
67523! move %l6(lower) -> %o0(upper)
67524sllx %l6, 32, %o0
67525add %l4, 1, %l4
67526ba P6431
67527nop
67528
67529TARGET6867:
67530ba RET6867
67531nop
67532
67533
67534P6431: !_ST [2] (maybe <- 0x300009b) (Int)
67535stw %l4, [%i0 + 12 ]
67536add %l4, 1, %l4
67537
67538P6432: !_LD [5] (Int)
67539lduw [%i1 + 12], %l7
67540! move %l7(lower) -> %o0(lower)
67541or %l7, %o0, %o0
67542
67543P6433: !_LDD [4] (Int)
67544ldd [%i1 + 0], %l6
67545! move %l6(lower) -> %o1(upper)
67546sllx %l6, 32, %o1
67547! move %l7(lower) -> %o1(lower)
67548or %l7, %o1, %o1
67549
67550P6434: !_ST_BINIT [22] (maybe <- 0x300009c) (Int)
67551wr %g0, 0xe2, %asi
67552sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
67553add %i0, %i2, %i2
67554stwa %l4, [%i2 + 4] %asi
67555add %l4, 1, %l4
67556
67557P6435: !_MEMBAR (Int)
67558membar #StoreLoad
67559
67560P6436: !_CAS [8] (maybe <- 0x300009d) (Int)
67561sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
67562sub %i0, %i3, %i3
67563add %i3, 12, %l3
67564lduw [%l3], %o2
67565mov %o2, %o5
67566! move %o5(lower) -> %o2(upper)
67567sllx %o5, 32, %o2
67568mov %l4, %l7
67569cas [%l3], %o5, %l7
67570! move %l7(lower) -> %o2(lower)
67571srl %l7, 0, %o5
67572or %o5, %o2, %o2
67573add %l4, 1, %l4
67574
67575P6437: !_DWLD [22] (FP)
67576ldd [%i2 + 0], %f18
67577! 2 addresses covered
67578fmovs %f18, %f3
67579fmovs %f19, %f4
67580
67581P6438: !_SWAP [16] (maybe <- 0x300009e) (Int)
67582sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
67583sub %i0, %i2, %i2
67584mov %l4, %o3
67585swap [%i2 + 4], %o3
67586! move %o3(lower) -> %o3(upper)
67587sllx %o3, 32, %o3
67588add %l4, 1, %l4
67589
67590P6439: !_LD [5] (Int) (CBR) (Branch target of P6396)
67591lduw [%i1 + 12], %o5
67592! move %o5(lower) -> %o3(lower)
67593or %o5, %o3, %o3
67594
67595! cbranch
67596andcc %l0, 1, %g0
67597be,pn %xcc, TARGET6439
67598nop
67599RET6439:
67600
67601! lfsr step begin
67602srlx %l0, 1, %l3
67603xnor %l3, %l0, %l3
67604sllx %l3, 63, %l3
67605or %l3, %l0, %l0
67606srlx %l0, 1, %l0
67607
67608ba P6440
67609nop
67610
67611TARGET6396:
67612ba RET6396
67613nop
67614
67615
67616P6440: !_LD [6] (Int)
67617lduw [%i3 + 0], %o4
67618! move %o4(lower) -> %o4(upper)
67619sllx %o4, 32, %o4
67620
67621P6441: !_LDD [21] (Int) (Branch target of P6129)
67622sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
67623add %i0, %i3, %i3
67624ldd [%i3 + 0], %l6
67625! move %l6(lower) -> %o4(lower)
67626or %l6, %o4, %o4
67627!---- flushing int results buffer----
67628mov %o0, %l5
67629mov %o1, %l5
67630mov %o2, %l5
67631mov %o3, %l5
67632mov %o4, %l5
67633! move %l7(lower) -> %o0(upper)
67634sllx %l7, 32, %o0
67635ba P6442
67636nop
67637
67638TARGET6129:
67639ba RET6129
67640nop
67641
67642
67643P6442: !_LDD [0] (Int)
67644ldd [%i0 + 0], %l6
67645! move %l6(lower) -> %o0(lower)
67646or %l6, %o0, %o0
67647! move %l7(lower) -> %o1(upper)
67648sllx %l7, 32, %o1
67649
67650P6443: !_DWST [18] (maybe <- 0x300009f) (Int)
67651sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
67652add %i0, %i2, %i2
67653sllx %l4, 32, %l3
67654add %l4, 1, %l4
67655or %l3, %l4, %l3
67656stx %l3, [%i2 + 0]
67657add %l4, 1, %l4
67658
67659P6444: !_DWLD [21] (Int)
67660ldx [%i3 + 0], %l3
67661! move %l3(upper) -> %o1(lower)
67662srlx %l3, 32, %o5
67663or %o5, %o1, %o1
67664! move %l3(lower) -> %o2(upper)
67665sllx %l3, 32, %o2
67666
67667P6445: !_MEMBAR (FP)
67668
67669P6446: !_BST [11] (maybe <- 0x42800081) (FP)
67670wr %g0, 0xf0, %asi
67671sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
67672add %i0, %i3, %i3
67673! preparing store val #0, next val will be in f32
67674fmovs %f16, %f20
67675fadds %f16, %f17, %f16
67676! preparing store val #1, next val will be in f33
67677fmovs %f16, %f21
67678fadds %f16, %f17, %f16
67679! preparing store val #2, next val will be in f35
67680fmovd %f20, %f32
67681fmovs %f16, %f21
67682fadds %f16, %f17, %f16
67683fmovd %f20, %f34
67684membar #Sync
67685stda %f32, [%i3 + 0 ] %asi
67686
67687P6447: !_MEMBAR (FP)
67688membar #StoreLoad
67689
67690P6448: !_BLD [23] (FP) (CBR) (Branch target of P6812)
67691wr %g0, 0xf0, %asi
67692sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
67693add %i0, %i2, %i2
67694ldda [%i2 + 0] %asi, %f32
67695membar #Sync
67696! 3 addresses covered
67697fmovd %f32, %f18
67698fmovs %f18, %f5
67699fmovs %f19, %f6
67700fmovd %f34, %f18
67701fmovs %f19, %f7
67702
67703! cbranch
67704andcc %l0, 1, %g0
67705be,pn %xcc, TARGET6448
67706nop
67707RET6448:
67708
67709! lfsr step begin
67710srlx %l0, 1, %l3
67711xnor %l3, %l0, %l3
67712sllx %l3, 63, %l3
67713or %l3, %l0, %l0
67714srlx %l0, 1, %l0
67715
67716ba P6449
67717nop
67718
67719TARGET6812:
67720ba RET6812
67721nop
67722
67723
67724P6449: !_MEMBAR (FP)
67725
67726P6450: !_BLD [19] (FP)
67727wr %g0, 0xf0, %asi
67728sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
67729add %i0, %i3, %i3
67730ldda [%i3 + 0] %asi, %f32
67731membar #Sync
67732! 3 addresses covered
67733fmovd %f32, %f8
67734fmovd %f34, %f18
67735fmovs %f19, %f10
67736
67737P6451: !_MEMBAR (FP)
67738
67739P6452: !_LDD [18] (Int) (Branch target of P6543)
67740ldd [%i3 + 0], %l6
67741! move %l6(lower) -> %o2(lower)
67742or %l6, %o2, %o2
67743! move %l7(lower) -> %o3(upper)
67744sllx %l7, 32, %o3
67745ba P6453
67746nop
67747
67748TARGET6543:
67749ba RET6543
67750nop
67751
67752
67753P6453: !_MEMBAR (FP)
67754membar #StoreLoad
67755
67756P6454: !_BLD [14] (FP)
67757wr %g0, 0xf0, %asi
67758sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
67759sub %i0, %i2, %i2
67760ldda [%i2 + 0] %asi, %f32
67761membar #Sync
67762! 3 addresses covered
67763fmovd %f32, %f18
67764fmovs %f18, %f11
67765fmovs %f19, %f12
67766fmovd %f34, %f18
67767fmovs %f19, %f13
67768
67769P6455: !_MEMBAR (FP)
67770
67771P6456: !_BSTC [0] (maybe <- 0x42800084) (FP)
67772wr %g0, 0xe0, %asi
67773! preparing store val #0, next val will be in f32
67774fmovs %f16, %f20
67775fadds %f16, %f17, %f16
67776! preparing store val #1, next val will be in f33
67777fmovs %f16, %f21
67778fadds %f16, %f17, %f16
67779! preparing store val #2, next val will be in f35
67780fmovd %f20, %f32
67781fmovs %f16, %f21
67782fadds %f16, %f17, %f16
67783fmovd %f20, %f34
67784membar #Sync
67785stda %f32, [%i0 + 0 ] %asi
67786
67787P6457: !_MEMBAR (FP)
67788
67789P6458: !_BST [11] (maybe <- 0x42800087) (FP)
67790wr %g0, 0xf0, %asi
67791sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3
67792add %i0, %i3, %i3
67793! preparing store val #0, next val will be in f32
67794fmovs %f16, %f20
67795fadds %f16, %f17, %f16
67796! preparing store val #1, next val will be in f33
67797fmovs %f16, %f21
67798fadds %f16, %f17, %f16
67799! preparing store val #2, next val will be in f35
67800fmovd %f20, %f32
67801fmovs %f16, %f21
67802fadds %f16, %f17, %f16
67803fmovd %f20, %f34
67804membar #Sync
67805stda %f32, [%i3 + 0 ] %asi
67806
67807P6459: !_MEMBAR (FP)
67808membar #StoreLoad
67809
67810P6460: !_ST [6] (maybe <- 0x30000a1) (Int) (CBR)
67811sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
67812sub %i0, %i2, %i2
67813stw %l4, [%i2 + 0 ]
67814add %l4, 1, %l4
67815
67816! cbranch
67817andcc %l0, 1, %g0
67818be,pt %xcc, TARGET6460
67819nop
67820RET6460:
67821
67822! lfsr step begin
67823srlx %l0, 1, %l6
67824xnor %l6, %l0, %l6
67825sllx %l6, 63, %l6
67826or %l6, %l0, %l0
67827srlx %l0, 1, %l0
67828
67829
67830P6461: !_CASX [7] (maybe <- 0x30000a2) (Int)
67831ldx [%i2], %l6
67832! move %l6(upper) -> %o3(lower)
67833srlx %l6, 32, %l7
67834or %l7, %o3, %o3
67835! move %l6(lower) -> %o4(upper)
67836sllx %l6, 32, %o4
67837mov %l6, %l7
67838sllx %l4, 32, %l6
67839add %l4, 1, %l4
67840or %l4, %l6, %l6
67841casx [%i2], %l7, %l6
67842! move %l6(upper) -> %o4(lower)
67843srlx %l6, 32, %l7
67844or %l7, %o4, %o4
67845!---- flushing int results buffer----
67846mov %o0, %l5
67847mov %o1, %l5
67848mov %o2, %l5
67849mov %o3, %l5
67850mov %o4, %l5
67851! move %l6(lower) -> %o0(upper)
67852sllx %l6, 32, %o0
67853add %l4, 1, %l4
67854
67855P6462: !_LDD [10] (Int)
67856sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
67857sub %i0, %i3, %i3
67858ldd [%i3 + 0], %l6
67859! move %l6(lower) -> %o0(lower)
67860or %l6, %o0, %o0
67861! move %l7(lower) -> %o1(upper)
67862sllx %l7, 32, %o1
67863
67864P6463: !_SWAP [19] (maybe <- 0x30000a4) (Int)
67865sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
67866add %i0, %i2, %i2
67867mov %l4, %l7
67868swap [%i2 + 4], %l7
67869! move %l7(lower) -> %o1(lower)
67870srl %l7, 0, %l3
67871or %l3, %o1, %o1
67872add %l4, 1, %l4
67873
67874P6464: !_REPLACEMENT [23] (Int)
67875sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
67876add %i0, %i3, %i3
67877sethi %hi(0x20000), %o5
67878ld [%i3+12], %l6
67879st %l6, [%i3+12]
67880add %i3, %o5, %l3
67881ld [%l3+12], %l6
67882st %l6, [%l3+12]
67883add %l3, %o5, %l3
67884ld [%l3+12], %l6
67885st %l6, [%l3+12]
67886add %l3, %o5, %l3
67887ld [%l3+12], %l6
67888st %l6, [%l3+12]
67889add %l3, %o5, %l3
67890ld [%l3+12], %l6
67891st %l6, [%l3+12]
67892add %l3, %o5, %l3
67893ld [%l3+12], %l6
67894st %l6, [%l3+12]
67895add %l3, %o5, %l3
67896ld [%l3+12], %l6
67897st %l6, [%l3+12]
67898add %l3, %o5, %l3
67899ld [%l3+12], %l6
67900st %l6, [%l3+12]
67901
67902P6465: !_PREFETCH [19] (Int)
67903prefetch [%i2 + 4], 2
67904
67905P6466: !_ST_BINIT [16] (maybe <- 0x30000a5) (Int) (CBR)
67906wr %g0, 0xe2, %asi
67907sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
67908sub %i0, %i2, %i2
67909stwa %l4, [%i2 + 4] %asi
67910add %l4, 1, %l4
67911
67912! cbranch
67913andcc %l0, 1, %g0
67914be,pn %xcc, TARGET6466
67915nop
67916RET6466:
67917
67918! lfsr step begin
67919srlx %l0, 1, %l6
67920xnor %l6, %l0, %l6
67921sllx %l6, 63, %l6
67922or %l6, %l0, %l0
67923srlx %l0, 1, %l0
67924
67925
67926P6467: !_MEMBAR (Int)
67927membar #StoreLoad
67928
67929P6468: !_CAS [10] (maybe <- 0x30000a6) (Int)
67930sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
67931sub %i0, %i3, %i3
67932add %i3, 4, %o5
67933lduw [%o5], %o2
67934mov %o2, %l7
67935! move %l7(lower) -> %o2(upper)
67936sllx %l7, 32, %o2
67937mov %l4, %l6
67938cas [%o5], %l7, %l6
67939! move %l6(lower) -> %o2(lower)
67940srl %l6, 0, %l7
67941or %l7, %o2, %o2
67942add %l4, 1, %l4
67943
67944P6469: !_DWST_BINIT [10] (maybe <- 0x30000a7) (Int)
67945wr %g0, 0xe2, %asi
67946sllx %l4, 32, %l7
67947add %l4, 1, %l4
67948or %l7, %l4, %l7
67949stxa %l7, [%i3 + 0] %asi
67950add %l4, 1, %l4
67951
67952P6470: !_MEMBAR (Int)
67953membar #StoreLoad
67954
67955P6471: !_DWST [3] (maybe <- 0x30000a9) (Int)
67956sllx %l4, 32, %l6
67957add %l4, 1, %l4
67958or %l6, %l4, %l6
67959stx %l6, [%i1 + 0]
67960add %l4, 1, %l4
67961
67962P6472: !_PREFETCH [18] (Int)
67963sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
67964add %i0, %i2, %i2
67965prefetch [%i2 + 0], 23
67966
67967P6473: !_DWST [15] (maybe <- 0x30000ab) (Int)
67968sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
67969sub %i0, %i3, %i3
67970sllx %l4, 32, %l3
67971add %l4, 1, %l4
67972or %l3, %l4, %l3
67973stx %l3, [%i3 + 0]
67974add %l4, 1, %l4
67975
67976P6474: !_DWST_BINIT [0] (maybe <- 0x30000ad) (Int) (LE) (Branch target of P6439)
67977wr %g0, 0xea, %asi
67978sllx %l4, 32, %o5
67979add %l4, 1, %l4
67980or %o5, %l4, %l3
67981! Change double-word-level endianess (big endian <-> little endian)
67982sethi %hi(0xff00ff00), %l6
67983or %l6, %lo(0xff00ff00), %l6
67984sllx %l6, 32, %o5
67985or %l6, %o5, %l6
67986and %l3, %l6, %o5
67987srlx %o5, 8, %o5
67988sllx %l3, 8, %l3
67989and %l3, %l6, %l3
67990or %l3, %o5, %l3
67991sethi %hi(0xffff0000), %l6
67992srlx %l3, 16, %o5
67993andn %o5, %l6, %o5
67994andn %l3, %l6, %l3
67995sllx %l3, 16, %l3
67996or %l3, %o5, %l3
67997srlx %l3, 32, %o5
67998sllx %l3, 32, %l3
67999or %l3, %o5, %o5
68000stxa %o5, [%i0 + 0 ] %asi
68001add %l4, 1, %l4
68002ba P6475
68003nop
68004
68005TARGET6439:
68006ba RET6439
68007nop
68008
68009
68010P6475: !_MEMBAR (Int) (LE)
68011membar #StoreLoad
68012
68013P6476: !_CASX [2] (maybe <- 0x30000af) (Int)
68014add %i0, 8, %o5
68015ldx [%o5], %o3
68016! move %o3(upper) -> %o3(upper)
68017! move %o3(lower) -> %o3(lower)
68018mov %o3, %l7
68019mov %l4, %o4
68020casx [%o5], %l7, %o4
68021! move %o4(upper) -> %o4(upper)
68022! move %o4(lower) -> %o4(lower)
68023!---- flushing int results buffer----
68024mov %o0, %l5
68025mov %o1, %l5
68026mov %o2, %l5
68027mov %o3, %l5
68028mov %o4, %l5
68029add %l4, 1, %l4
68030
68031P6477: !_DWST [5] (maybe <- 0x4280008a) (FP)
68032! preparing store val #0, next val will be in f21
68033fmovs %f16, %f21
68034fadds %f16, %f17, %f16
68035std %f20, [%i1 + 8]
68036
68037P6478: !_CASX [0] (maybe <- 0x30000b0) (Int)
68038ldx [%i0], %o0
68039! move %o0(upper) -> %o0(upper)
68040! move %o0(lower) -> %o0(lower)
68041mov %o0, %l6
68042sllx %l4, 32, %o1
68043add %l4, 1, %l4
68044or %l4, %o1, %o1
68045casx [%i0], %l6, %o1
68046! move %o1(upper) -> %o1(upper)
68047! move %o1(lower) -> %o1(lower)
68048add %l4, 1, %l4
68049
68050P6479: !_CASX [3] (maybe <- 0x30000b2) (Int)
68051ldx [%i1], %o2
68052! move %o2(upper) -> %o2(upper)
68053! move %o2(lower) -> %o2(lower)
68054mov %o2, %l6
68055sllx %l4, 32, %o3
68056add %l4, 1, %l4
68057or %l4, %o3, %o3
68058casx [%i1], %l6, %o3
68059! move %o3(upper) -> %o3(upper)
68060! move %o3(lower) -> %o3(lower)
68061add %l4, 1, %l4
68062
68063P6480: !_MEMBAR (FP)
68064
68065P6481: !_BSTC [14] (maybe <- 0x4280008b) (FP) (Branch target of P6280)
68066wr %g0, 0xe0, %asi
68067sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
68068sub %i0, %i2, %i2
68069! preparing store val #0, next val will be in f32
68070fmovs %f16, %f20
68071fadds %f16, %f17, %f16
68072! preparing store val #1, next val will be in f33
68073fmovs %f16, %f21
68074fadds %f16, %f17, %f16
68075! preparing store val #2, next val will be in f35
68076fmovd %f20, %f32
68077fmovs %f16, %f21
68078fadds %f16, %f17, %f16
68079fmovd %f20, %f34
68080membar #Sync
68081stda %f32, [%i2 + 0 ] %asi
68082ba P6482
68083nop
68084
68085TARGET6280:
68086ba RET6280
68087nop
68088
68089
68090P6482: !_MEMBAR (FP)
68091membar #StoreLoad
68092
68093P6483: !_ST_BINIT [17] (maybe <- 0x30000b4) (Int)
68094wr %g0, 0xe2, %asi
68095stwa %l4, [%i3 + 12] %asi
68096add %l4, 1, %l4
68097
68098P6484: !_MEMBAR (Int)
68099membar #StoreLoad
68100
68101P6485: !_LD [9] (Int)
68102sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
68103sub %i0, %i3, %i3
68104lduw [%i3 + 0], %o4
68105! move %o4(lower) -> %o4(upper)
68106sllx %o4, 32, %o4
68107
68108P6486: !_MEMBAR (FP) (Branch target of P6595)
68109ba P6487
68110nop
68111
68112TARGET6595:
68113ba RET6595
68114nop
68115
68116
68117P6487: !_BSTC [0] (maybe <- 0x4280008e) (FP)
68118wr %g0, 0xe0, %asi
68119! preparing store val #0, next val will be in f32
68120fmovs %f16, %f20
68121fadds %f16, %f17, %f16
68122! preparing store val #1, next val will be in f33
68123fmovs %f16, %f21
68124fadds %f16, %f17, %f16
68125! preparing store val #2, next val will be in f35
68126fmovd %f20, %f32
68127fmovs %f16, %f21
68128fadds %f16, %f17, %f16
68129fmovd %f20, %f34
68130membar #Sync
68131stda %f32, [%i0 + 0 ] %asi
68132
68133P6488: !_MEMBAR (FP)
68134membar #StoreLoad
68135
68136P6489: !_LD [6] (Int)
68137sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
68138sub %i0, %i2, %i2
68139lduw [%i2 + 0], %l6
68140! move %l6(lower) -> %o4(lower)
68141or %l6, %o4, %o4
68142!---- flushing int results buffer----
68143mov %o0, %l5
68144mov %o1, %l5
68145mov %o2, %l5
68146mov %o3, %l5
68147mov %o4, %l5
68148
68149P6490: !_ST_BINIT [9] (maybe <- 0x30000b5) (Int) (CBR)
68150wr %g0, 0xe2, %asi
68151stwa %l4, [%i3 + 0] %asi
68152add %l4, 1, %l4
68153
68154! cbranch
68155andcc %l0, 1, %g0
68156be,pn %xcc, TARGET6490
68157nop
68158RET6490:
68159
68160! lfsr step begin
68161srlx %l0, 1, %l6
68162xnor %l6, %l0, %l6
68163sllx %l6, 63, %l6
68164or %l6, %l0, %l0
68165srlx %l0, 1, %l0
68166
68167
68168P6491: !_MEMBAR (Int)
68169membar #StoreLoad
68170
68171P6492: !_ST [13] (maybe <- 0x30000b6) (Int)
68172sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
68173sub %i0, %i3, %i3
68174stw %l4, [%i3 + 4 ]
68175add %l4, 1, %l4
68176
68177P6493: !_DWLD [17] (Int) (Branch target of P6495)
68178sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i2
68179sub %i0, %i2, %i2
68180ldx [%i2 + 8], %o0
68181! move %o0(lower) -> %o0(upper)
68182sllx %o0, 32, %o0
68183ba P6494
68184nop
68185
68186TARGET6495:
68187ba RET6495
68188nop
68189
68190
68191P6494: !_ST_BINIT [17] (maybe <- 0x30000b7) (Int)
68192wr %g0, 0xe2, %asi
68193stwa %l4, [%i2 + 12] %asi
68194add %l4, 1, %l4
68195
68196P6495: !_MEMBAR (Int) (CBR)
68197
68198! cbranch
68199andcc %l0, 1, %g0
68200be,pn %xcc, TARGET6495
68201nop
68202RET6495:
68203
68204! lfsr step begin
68205srlx %l0, 1, %l7
68206xnor %l7, %l0, %l7
68207sllx %l7, 63, %l7
68208or %l7, %l0, %l0
68209srlx %l0, 1, %l0
68210
68211
68212P6496: !_BSTC [3] (maybe <- 0x42800091) (FP)
68213wr %g0, 0xe0, %asi
68214! preparing store val #0, next val will be in f32
68215fmovs %f16, %f20
68216fadds %f16, %f17, %f16
68217! preparing store val #1, next val will be in f33
68218fmovs %f16, %f21
68219fadds %f16, %f17, %f16
68220! preparing store val #2, next val will be in f35
68221fmovd %f20, %f32
68222fmovs %f16, %f21
68223fadds %f16, %f17, %f16
68224fmovd %f20, %f34
68225membar #Sync
68226stda %f32, [%i1 + 0 ] %asi
68227
68228P6497: !_MEMBAR (FP)
68229membar #StoreLoad
68230
68231P6498: !_DWST [13] (maybe <- 0x30000b8) (Int)
68232sllx %l4, 32, %l7
68233add %l4, 1, %l4
68234or %l7, %l4, %l7
68235stx %l7, [%i3 + 0]
68236add %l4, 1, %l4
68237
68238P6499: !_CAS [20] (maybe <- 0x30000ba) (Int)
68239sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
68240add %i0, %i3, %i3
68241add %i3, 12, %l7
68242lduw [%l7], %l3
68243mov %l3, %l6
68244! move %l6(lower) -> %o0(lower)
68245or %l6, %o0, %o0
68246mov %l4, %o1
68247cas [%l7], %l6, %o1
68248! move %o1(lower) -> %o1(upper)
68249sllx %o1, 32, %o1
68250add %l4, 1, %l4
68251
68252P6500: !_ST_BINIT [5] (maybe <- 0x30000bb) (Int) (CBR)
68253wr %g0, 0xe2, %asi
68254stwa %l4, [%i1 + 12] %asi
68255add %l4, 1, %l4
68256
68257! cbranch
68258andcc %l0, 1, %g0
68259be,pt %xcc, TARGET6500
68260nop
68261RET6500:
68262
68263! lfsr step begin
68264srlx %l0, 1, %l3
68265xnor %l3, %l0, %l3
68266sllx %l3, 63, %l3
68267or %l3, %l0, %l0
68268srlx %l0, 1, %l0
68269
68270
68271P6501: !_MEMBAR (Int)
68272
68273P6502: !_BST [1] (maybe <- 0x42800094) (FP)
68274wr %g0, 0xf0, %asi
68275! preparing store val #0, next val will be in f32
68276fmovs %f16, %f20
68277fadds %f16, %f17, %f16
68278! preparing store val #1, next val will be in f33
68279fmovs %f16, %f21
68280fadds %f16, %f17, %f16
68281! preparing store val #2, next val will be in f35
68282fmovd %f20, %f32
68283fmovs %f16, %f21
68284fadds %f16, %f17, %f16
68285fmovd %f20, %f34
68286membar #Sync
68287stda %f32, [%i0 + 0 ] %asi
68288
68289P6503: !_MEMBAR (FP)
68290membar #StoreLoad
68291
68292P6504: !_LD [23] (Int) (LE)
68293wr %g0, 0x88, %asi
68294sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
68295add %i0, %i2, %i2
68296lduwa [%i2 + 12] %asi, %l6
68297! move %l6(lower) -> %o1(lower)
68298or %l6, %o1, %o1
68299
68300P6505: !_ST_BINIT [17] (maybe <- 0x30000bc) (Int)
68301wr %g0, 0xe2, %asi
68302sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS3_O), %i3
68303sub %i0, %i3, %i3
68304stwa %l4, [%i3 + 12] %asi
68305add %l4, 1, %l4
68306
68307P6506: !_MEMBAR (Int)
68308
68309P6507: !_BST [8] (maybe <- 0x42800097) (FP)
68310wr %g0, 0xf0, %asi
68311sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
68312sub %i0, %i2, %i2
68313! preparing store val #0, next val will be in f32
68314fmovs %f16, %f20
68315fadds %f16, %f17, %f16
68316! preparing store val #1, next val will be in f33
68317fmovs %f16, %f21
68318fadds %f16, %f17, %f16
68319! preparing store val #2, next val will be in f35
68320fmovd %f20, %f32
68321fmovs %f16, %f21
68322fadds %f16, %f17, %f16
68323fmovd %f20, %f34
68324membar #Sync
68325stda %f32, [%i2 + 0 ] %asi
68326
68327P6508: !_MEMBAR (FP)
68328membar #StoreLoad
68329
68330P6509: !_ST [19] (maybe <- 0x30000bd) (Int)
68331sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
68332add %i0, %i3, %i3
68333stw %l4, [%i3 + 4 ]
68334add %l4, 1, %l4
68335
68336P6510: !_MEMBAR (FP)
68337
68338P6511: !_BST [9] (maybe <- 0x4280009a) (FP)
68339wr %g0, 0xf0, %asi
68340sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
68341sub %i0, %i2, %i2
68342! preparing store val #0, next val will be in f32
68343fmovs %f16, %f20
68344fadds %f16, %f17, %f16
68345! preparing store val #1, next val will be in f33
68346fmovs %f16, %f21
68347fadds %f16, %f17, %f16
68348! preparing store val #2, next val will be in f35
68349fmovd %f20, %f32
68350fmovs %f16, %f21
68351fadds %f16, %f17, %f16
68352fmovd %f20, %f34
68353membar #Sync
68354stda %f32, [%i2 + 0 ] %asi
68355
68356P6512: !_MEMBAR (FP)
68357membar #StoreLoad
68358
68359P6513: !_LD [1] (Int)
68360lduw [%i0 + 4], %o2
68361! move %o2(lower) -> %o2(upper)
68362sllx %o2, 32, %o2
68363
68364P6514: !_LD [3] (Int)
68365lduw [%i1 + 0], %l6
68366! move %l6(lower) -> %o2(lower)
68367or %l6, %o2, %o2
68368
68369P6515: !_DWST_BINIT [13] (maybe <- 0x30000be) (Int)
68370wr %g0, 0xe2, %asi
68371sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
68372sub %i0, %i3, %i3
68373sllx %l4, 32, %l7
68374add %l4, 1, %l4
68375or %l7, %l4, %l7
68376stxa %l7, [%i3 + 0] %asi
68377add %l4, 1, %l4
68378
68379P6516: !_MEMBAR (Int)
68380membar #StoreLoad
68381
68382P6517: !_LDD [11] (Int)
68383ldd [%i2 + 8], %l6
68384! move %l7(lower) -> %o3(upper)
68385sllx %l7, 32, %o3
68386
68387P6518: !_CASX [21] (maybe <- 0x30000c0) (Int)
68388sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
68389add %i0, %i2, %i2
68390ldx [%i2], %o5
68391! move %o5(upper) -> %o3(lower)
68392srlx %o5, 32, %l3
68393or %l3, %o3, %o3
68394! move %o5(lower) -> %o4(upper)
68395sllx %o5, 32, %o4
68396mov %o5, %l3
68397sllx %l4, 32, %o5
68398add %l4, 1, %l4
68399or %l4, %o5, %o5
68400casx [%i2], %l3, %o5
68401! move %o5(upper) -> %o4(lower)
68402srlx %o5, 32, %l3
68403or %l3, %o4, %o4
68404!---- flushing int results buffer----
68405mov %o0, %l5
68406mov %o1, %l5
68407mov %o2, %l5
68408mov %o3, %l5
68409mov %o4, %l5
68410! move %o5(lower) -> %o0(upper)
68411sllx %o5, 32, %o0
68412add %l4, 1, %l4
68413
68414P6519: !_PREFETCH [3] (Int)
68415prefetch [%i1 + 0], 23
68416
68417P6520: !_LD [10] (Int)
68418sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
68419sub %i0, %i3, %i3
68420lduw [%i3 + 4], %l6
68421! move %l6(lower) -> %o0(lower)
68422or %l6, %o0, %o0
68423
68424P6521: !_DWST [12] (maybe <- 0x30000c2) (Int)
68425sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
68426sub %i0, %i2, %i2
68427sllx %l4, 32, %l7
68428add %l4, 1, %l4
68429or %l7, %l4, %l7
68430stx %l7, [%i2 + 0]
68431add %l4, 1, %l4
68432
68433P6522: !_DWST [0] (maybe <- 0x30000c4) (Int)
68434sllx %l4, 32, %l6
68435add %l4, 1, %l4
68436or %l6, %l4, %l6
68437stx %l6, [%i0 + 0]
68438add %l4, 1, %l4
68439
68440P6523: !_CAS [0] (maybe <- 0x30000c6) (Int)
68441lduw [%i0], %o1
68442mov %o1, %l3
68443! move %l3(lower) -> %o1(upper)
68444sllx %l3, 32, %o1
68445mov %l4, %o5
68446cas [%i0], %l3, %o5
68447! move %o5(lower) -> %o1(lower)
68448srl %o5, 0, %l3
68449or %l3, %o1, %o1
68450add %l4, 1, %l4
68451
68452P6524: !_DWST_BINIT [14] (maybe <- 0x30000c7) (Int)
68453wr %g0, 0xe2, %asi
68454mov %l4, %l3
68455stxa %l3, [%i2 + 8] %asi
68456add %l4, 1, %l4
68457
68458P6525: !_MEMBAR (Int)
68459membar #StoreLoad
68460
68461P6526: !_SWAP [16] (maybe <- 0x30000c8) (Int)
68462sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
68463add %i0, %i3, %i3
68464mov %l4, %o2
68465swap [%i3 + 4], %o2
68466! move %o2(lower) -> %o2(upper)
68467sllx %o2, 32, %o2
68468add %l4, 1, %l4
68469
68470P6527: !_PREFETCH [11] (Int) (LE) (Branch target of P6962)
68471wr %g0, 0x88, %asi
68472sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
68473sub %i0, %i2, %i2
68474prefetcha [%i2 + 12] %asi, 4
68475ba P6528
68476nop
68477
68478TARGET6962:
68479ba RET6962
68480nop
68481
68482
68483P6528: !_CAS [5] (maybe <- 0x30000c9) (Int)
68484add %i1, 12, %l3
68485lduw [%l3], %l7
68486mov %l7, %o5
68487! move %o5(lower) -> %o2(lower)
68488or %o5, %o2, %o2
68489mov %l4, %o3
68490cas [%l3], %o5, %o3
68491! move %o3(lower) -> %o3(upper)
68492sllx %o3, 32, %o3
68493add %l4, 1, %l4
68494
68495P6529: !_CASX [12] (maybe <- 0x30000ca) (Int)
68496sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
68497sub %i0, %i3, %i3
68498ldx [%i3], %l7
68499! move %l7(upper) -> %o3(lower)
68500srlx %l7, 32, %o5
68501or %o5, %o3, %o3
68502! move %l7(lower) -> %o4(upper)
68503sllx %l7, 32, %o4
68504mov %l7, %o5
68505sllx %l4, 32, %l7
68506add %l4, 1, %l4
68507or %l4, %l7, %l7
68508casx [%i3], %o5, %l7
68509! move %l7(upper) -> %o4(lower)
68510srlx %l7, 32, %o5
68511or %o5, %o4, %o4
68512!---- flushing int results buffer----
68513mov %o0, %l5
68514mov %o1, %l5
68515mov %o2, %l5
68516mov %o3, %l5
68517mov %o4, %l5
68518! move %l7(lower) -> %o0(upper)
68519sllx %l7, 32, %o0
68520add %l4, 1, %l4
68521
68522P6530: !_PREFETCH [0] (Int)
68523prefetch [%i0 + 0], 1
68524
68525P6531: !_MEMBAR (FP)
68526membar #StoreLoad
68527
68528P6532: !_BLD [19] (FP)
68529wr %g0, 0xf0, %asi
68530sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
68531add %i0, %i2, %i2
68532ldda [%i2 + 0] %asi, %f32
68533membar #Sync
68534! 3 addresses covered
68535fmovd %f32, %f14
68536!---- flushing fp results buffer to %f30 ----
68537fmovd %f0, %f30
68538fmovd %f2, %f30
68539fmovd %f4, %f30
68540fmovd %f6, %f30
68541fmovd %f8, %f30
68542fmovd %f10, %f30
68543fmovd %f12, %f30
68544fmovd %f14, %f30
68545!--
68546fmovd %f34, %f18
68547fmovs %f19, %f0
68548
68549P6533: !_MEMBAR (FP)
68550
68551P6534: !_LDD [11] (Int)
68552sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
68553sub %i0, %i3, %i3
68554ldd [%i3 + 8], %l6
68555! move %l7(lower) -> %o0(lower)
68556or %l7, %o0, %o0
68557
68558P6535: !_MEMBAR (FP)
68559membar #StoreLoad
68560
68561P6536: !_BLD [5] (FP)
68562wr %g0, 0xf0, %asi
68563ldda [%i1 + 0] %asi, %f32
68564membar #Sync
68565! 3 addresses covered
68566fmovd %f32, %f18
68567fmovs %f18, %f1
68568fmovs %f19, %f2
68569fmovd %f34, %f18
68570fmovs %f19, %f3
68571
68572P6537: !_MEMBAR (FP) (Branch target of P6684)
68573ba P6538
68574nop
68575
68576TARGET6684:
68577ba RET6684
68578nop
68579
68580
68581P6538: !_DWST_BINIT [9] (maybe <- 0x30000cc) (Int)
68582wr %g0, 0xe2, %asi
68583sllx %l4, 32, %l3
68584add %l4, 1, %l4
68585or %l3, %l4, %l3
68586stxa %l3, [%i3 + 0] %asi
68587add %l4, 1, %l4
68588
68589P6539: !_MEMBAR (Int)
68590membar #StoreLoad
68591
68592P6540: !_ST [19] (maybe <- 0x30000ce) (Int)
68593stw %l4, [%i2 + 4 ]
68594add %l4, 1, %l4
68595
68596P6541: !_ST [0] (maybe <- 0x30000cf) (Int)
68597stw %l4, [%i0 + 0 ]
68598add %l4, 1, %l4
68599
68600P6542: !_PREFETCH [7] (Int)
68601sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
68602sub %i0, %i2, %i2
68603prefetch [%i2 + 4], 0
68604
68605P6543: !_PREFETCH [23] (Int) (CBR)
68606sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
68607add %i0, %i3, %i3
68608prefetch [%i3 + 12], 20
68609
68610! cbranch
68611andcc %l0, 1, %g0
68612be,pt %xcc, TARGET6543
68613nop
68614RET6543:
68615
68616! lfsr step begin
68617srlx %l0, 1, %l6
68618xnor %l6, %l0, %l6
68619sllx %l6, 63, %l6
68620or %l6, %l0, %l0
68621srlx %l0, 1, %l0
68622
68623
68624P6544: !_DWST [23] (maybe <- 0x30000d0) (Int)
68625mov %l4, %l7
68626stx %l7, [%i3 + 8]
68627add %l4, 1, %l4
68628
68629P6545: !_MEMBAR (FP)
68630membar #StoreLoad
68631
68632P6546: !_BLD [11] (FP)
68633wr %g0, 0xf0, %asi
68634sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
68635sub %i0, %i2, %i2
68636ldda [%i2 + 0] %asi, %f32
68637membar #Sync
68638! 3 addresses covered
68639fmovd %f32, %f4
68640fmovd %f34, %f18
68641fmovs %f19, %f6
68642
68643P6547: !_MEMBAR (FP)
68644
68645P6548: !_BLD [15] (FP)
68646wr %g0, 0xf0, %asi
68647sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
68648add %i0, %i3, %i3
68649ldda [%i3 + 0] %asi, %f32
68650membar #Sync
68651! 3 addresses covered
68652fmovd %f32, %f18
68653fmovs %f18, %f7
68654fmovs %f19, %f8
68655fmovd %f34, %f18
68656fmovs %f19, %f9
68657
68658P6549: !_MEMBAR (FP)
68659
68660P6550: !_DWST_BINIT [7] (maybe <- 0x30000d1) (Int)
68661wr %g0, 0xe2, %asi
68662sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
68663sub %i0, %i2, %i2
68664sllx %l4, 32, %l6
68665add %l4, 1, %l4
68666or %l6, %l4, %l6
68667stxa %l6, [%i2 + 0] %asi
68668add %l4, 1, %l4
68669
68670P6551: !_MEMBAR (Int)
68671membar #StoreLoad
68672
68673P6552: !_PREFETCH [8] (Int)
68674prefetch [%i2 + 12], 20
68675
68676P6553: !_PREFETCH [8] (Int)
68677prefetch [%i2 + 12], 1
68678
68679P6554: !_REPLACEMENT [4] (Int)
68680sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
68681sub %i0, %i3, %i3
68682sethi %hi(0x20000), %l3
68683ld [%i3+4], %l7
68684st %l7, [%i3+4]
68685add %i3, %l3, %l6
68686ld [%l6+4], %l7
68687st %l7, [%l6+4]
68688add %l6, %l3, %l6
68689ld [%l6+4], %l7
68690st %l7, [%l6+4]
68691add %l6, %l3, %l6
68692ld [%l6+4], %l7
68693st %l7, [%l6+4]
68694add %l6, %l3, %l6
68695ld [%l6+4], %l7
68696st %l7, [%l6+4]
68697add %l6, %l3, %l6
68698ld [%l6+4], %l7
68699st %l7, [%l6+4]
68700add %l6, %l3, %l6
68701ld [%l6+4], %l7
68702st %l7, [%l6+4]
68703add %l6, %l3, %l6
68704ld [%l6+4], %l7
68705st %l7, [%l6+4]
68706
68707P6555: !_LDD [18] (Int)
68708sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
68709add %i0, %i2, %i2
68710ldd [%i2 + 0], %l6
68711! move %l6(lower) -> %o1(upper)
68712sllx %l6, 32, %o1
68713! move %l7(lower) -> %o1(lower)
68714or %l7, %o1, %o1
68715
68716P6556: !_ST_BINIT [2] (maybe <- 0x30000d3) (Int)
68717wr %g0, 0xe2, %asi
68718stwa %l4, [%i0 + 12] %asi
68719add %l4, 1, %l4
68720
68721P6557: !_MEMBAR (Int)
68722
68723P6558: !_BSTC [11] (maybe <- 0x4280009d) (FP)
68724wr %g0, 0xe0, %asi
68725sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
68726sub %i0, %i3, %i3
68727! preparing store val #0, next val will be in f32
68728fmovs %f16, %f20
68729fadds %f16, %f17, %f16
68730! preparing store val #1, next val will be in f33
68731fmovs %f16, %f21
68732fadds %f16, %f17, %f16
68733! preparing store val #2, next val will be in f35
68734fmovd %f20, %f32
68735fmovs %f16, %f21
68736fadds %f16, %f17, %f16
68737fmovd %f20, %f34
68738membar #Sync
68739stda %f32, [%i3 + 0 ] %asi
68740
68741P6559: !_MEMBAR (FP)
68742membar #StoreLoad
68743
68744P6560: !_LDD [15] (Int)
68745sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
68746add %i0, %i2, %i2
68747ldd [%i2 + 0], %l6
68748! move %l6(lower) -> %o2(upper)
68749sllx %l6, 32, %o2
68750! move %l7(lower) -> %o2(lower)
68751or %l7, %o2, %o2
68752
68753P6561: !_LD [11] (Int)
68754lduw [%i3 + 12], %o3
68755! move %o3(lower) -> %o3(upper)
68756sllx %o3, 32, %o3
68757
68758P6562: !_DWST_BINIT [10] (maybe <- 0x30000d4) (Int)
68759wr %g0, 0xe2, %asi
68760sllx %l4, 32, %l7
68761add %l4, 1, %l4
68762or %l7, %l4, %l7
68763stxa %l7, [%i3 + 0] %asi
68764add %l4, 1, %l4
68765
68766P6563: !_MEMBAR (Int)
68767
68768P6564: !_BSTC [20] (maybe <- 0x428000a0) (FP) (Branch target of P6158)
68769wr %g0, 0xe0, %asi
68770sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
68771add %i0, %i3, %i3
68772! preparing store val #0, next val will be in f32
68773fmovs %f16, %f20
68774fadds %f16, %f17, %f16
68775! preparing store val #1, next val will be in f33
68776fmovs %f16, %f21
68777fadds %f16, %f17, %f16
68778! preparing store val #2, next val will be in f35
68779fmovd %f20, %f32
68780fmovs %f16, %f21
68781fadds %f16, %f17, %f16
68782fmovd %f20, %f34
68783membar #Sync
68784stda %f32, [%i3 + 0 ] %asi
68785ba P6565
68786nop
68787
68788TARGET6158:
68789ba RET6158
68790nop
68791
68792
68793P6565: !_MEMBAR (FP)
68794membar #StoreLoad
68795
68796P6566: !_ST [15] (maybe <- 0x30000d6) (Int)
68797stw %l4, [%i2 + 0 ]
68798add %l4, 1, %l4
68799
68800P6567: !_MEMBAR (FP)
68801
68802P6568: !_BSTC [12] (maybe <- 0x428000a3) (FP)
68803wr %g0, 0xe0, %asi
68804sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
68805sub %i0, %i2, %i2
68806! preparing store val #0, next val will be in f32
68807fmovs %f16, %f20
68808fadds %f16, %f17, %f16
68809! preparing store val #1, next val will be in f33
68810fmovs %f16, %f21
68811fadds %f16, %f17, %f16
68812! preparing store val #2, next val will be in f35
68813fmovd %f20, %f32
68814fmovs %f16, %f21
68815fadds %f16, %f17, %f16
68816fmovd %f20, %f34
68817membar #Sync
68818stda %f32, [%i2 + 0 ] %asi
68819
68820P6569: !_MEMBAR (FP)
68821membar #StoreLoad
68822
68823P6570: !_PREFETCH [8] (Int)
68824sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
68825sub %i0, %i3, %i3
68826prefetch [%i3 + 12], 2
68827
68828P6571: !_PREFETCH [10] (Int)
68829sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
68830sub %i0, %i2, %i2
68831prefetch [%i2 + 4], 20
68832
68833P6572: !_CAS [23] (maybe <- 0x30000d7) (Int)
68834sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
68835add %i0, %i3, %i3
68836add %i3, 12, %o5
68837lduw [%o5], %l6
68838mov %l6, %l7
68839! move %l7(lower) -> %o3(lower)
68840or %l7, %o3, %o3
68841mov %l4, %o4
68842cas [%o5], %l7, %o4
68843! move %o4(lower) -> %o4(upper)
68844sllx %o4, 32, %o4
68845add %l4, 1, %l4
68846
68847P6573: !_ST [18] (maybe <- 0x30000d8) (Int)
68848sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
68849add %i0, %i2, %i2
68850stw %l4, [%i2 + 0 ]
68851add %l4, 1, %l4
68852
68853P6574: !_ST_BINIT [15] (maybe <- 0x30000d9) (Int)
68854wr %g0, 0xe2, %asi
68855sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
68856add %i0, %i3, %i3
68857stwa %l4, [%i3 + 0] %asi
68858add %l4, 1, %l4
68859
68860P6575: !_MEMBAR (Int)
68861membar #StoreLoad
68862
68863P6576: !_BLD [15] (FP)
68864wr %g0, 0xf0, %asi
68865ldda [%i3 + 0] %asi, %f32
68866membar #Sync
68867! 3 addresses covered
68868fmovd %f32, %f10
68869fmovd %f34, %f18
68870fmovs %f19, %f12
68871
68872P6577: !_MEMBAR (FP) (Branch target of P6858)
68873ba P6578
68874nop
68875
68876TARGET6858:
68877ba RET6858
68878nop
68879
68880
68881P6578: !_DWST [22] (maybe <- 0x30000da) (Int)
68882sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i2
68883add %i0, %i2, %i2
68884sllx %l4, 32, %l3
68885add %l4, 1, %l4
68886or %l3, %l4, %l3
68887stx %l3, [%i2 + 0]
68888add %l4, 1, %l4
68889
68890P6579: !_ST_BINIT [3] (maybe <- 0x30000dc) (Int)
68891wr %g0, 0xe2, %asi
68892stwa %l4, [%i1 + 0] %asi
68893add %l4, 1, %l4
68894
68895P6580: !_MEMBAR (Int)
68896membar #StoreLoad
68897
68898P6581: !_CASX [19] (maybe <- 0x30000dd) (Int)
68899sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
68900add %i0, %i3, %i3
68901ldx [%i3], %l6
68902! move %l6(upper) -> %o4(lower)
68903srlx %l6, 32, %l7
68904or %l7, %o4, %o4
68905!---- flushing int results buffer----
68906mov %o0, %l5
68907mov %o1, %l5
68908mov %o2, %l5
68909mov %o3, %l5
68910mov %o4, %l5
68911! move %l6(lower) -> %o0(upper)
68912sllx %l6, 32, %o0
68913mov %l6, %l7
68914sllx %l4, 32, %l6
68915add %l4, 1, %l4
68916or %l4, %l6, %l6
68917casx [%i3], %l7, %l6
68918! move %l6(upper) -> %o0(lower)
68919srlx %l6, 32, %l7
68920or %l7, %o0, %o0
68921! move %l6(lower) -> %o1(upper)
68922sllx %l6, 32, %o1
68923add %l4, 1, %l4
68924
68925P6582: !_MEMBAR (FP) (Branch target of P6618)
68926ba P6583
68927nop
68928
68929TARGET6618:
68930ba RET6618
68931nop
68932
68933
68934P6583: !_BSTC [12] (maybe <- 0x428000a6) (FP)
68935wr %g0, 0xe0, %asi
68936sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
68937sub %i0, %i2, %i2
68938! preparing store val #0, next val will be in f32
68939fmovs %f16, %f20
68940fadds %f16, %f17, %f16
68941! preparing store val #1, next val will be in f33
68942fmovs %f16, %f21
68943fadds %f16, %f17, %f16
68944! preparing store val #2, next val will be in f35
68945fmovd %f20, %f32
68946fmovs %f16, %f21
68947fadds %f16, %f17, %f16
68948fmovd %f20, %f34
68949membar #Sync
68950stda %f32, [%i2 + 0 ] %asi
68951
68952P6584: !_MEMBAR (FP)
68953membar #StoreLoad
68954
68955P6585: !_PREFETCH [23] (Int)
68956sethi %hi(REGION7_ALIAS0_O-REGION0_ALIAS0_O), %i3
68957add %i0, %i3, %i3
68958prefetch [%i3 + 12], 22
68959
68960P6586: !_DWST_BINIT [23] (maybe <- 0x30000df) (Int)
68961wr %g0, 0xe2, %asi
68962mov %l4, %l6
68963stxa %l6, [%i3 + 8] %asi
68964add %l4, 1, %l4
68965
68966P6587: !_MEMBAR (Int)
68967membar #StoreLoad
68968
68969P6588: !_REPLACEMENT [22] (Int)
68970sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
68971add %i0, %i2, %i2
68972sethi %hi(0x20000), %l3
68973ld [%i2+4], %l7
68974st %l7, [%i2+4]
68975add %i2, %l3, %l6
68976ld [%l6+4], %l7
68977st %l7, [%l6+4]
68978add %l6, %l3, %l6
68979ld [%l6+4], %l7
68980st %l7, [%l6+4]
68981add %l6, %l3, %l6
68982ld [%l6+4], %l7
68983st %l7, [%l6+4]
68984add %l6, %l3, %l6
68985ld [%l6+4], %l7
68986st %l7, [%l6+4]
68987add %l6, %l3, %l6
68988ld [%l6+4], %l7
68989st %l7, [%l6+4]
68990add %l6, %l3, %l6
68991ld [%l6+4], %l7
68992st %l7, [%l6+4]
68993add %l6, %l3, %l6
68994ld [%l6+4], %l7
68995st %l7, [%l6+4]
68996
68997P6589: !_CASX [15] (maybe <- 0x30000e0) (Int)
68998sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
68999add %i0, %i3, %i3
69000ldx [%i3], %l7
69001! move %l7(upper) -> %o1(lower)
69002srlx %l7, 32, %o5
69003or %o5, %o1, %o1
69004! move %l7(lower) -> %o2(upper)
69005sllx %l7, 32, %o2
69006mov %l7, %o5
69007sllx %l4, 32, %l7
69008add %l4, 1, %l4
69009or %l4, %l7, %l7
69010casx [%i3], %o5, %l7
69011! move %l7(upper) -> %o2(lower)
69012srlx %l7, 32, %o5
69013or %o5, %o2, %o2
69014! move %l7(lower) -> %o3(upper)
69015sllx %l7, 32, %o3
69016add %l4, 1, %l4
69017
69018P6590: !_LDD [22] (Int)
69019sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
69020sub %i0, %i2, %i2
69021ldd [%i2 + 0], %l6
69022! move %l6(lower) -> %o3(lower)
69023or %l6, %o3, %o3
69024! move %l7(lower) -> %o4(upper)
69025sllx %l7, 32, %o4
69026
69027P6591: !_ST [16] (maybe <- 0x30000e2) (Int)
69028stw %l4, [%i3 + 4 ]
69029add %l4, 1, %l4
69030
69031P6592: !_LDD [20] (Int)
69032sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
69033add %i0, %i3, %i3
69034ldd [%i3 + 8], %l6
69035! move %l7(lower) -> %o4(lower)
69036or %l7, %o4, %o4
69037!---- flushing int results buffer----
69038mov %o0, %l5
69039mov %o1, %l5
69040mov %o2, %l5
69041mov %o3, %l5
69042mov %o4, %l5
69043
69044P6593: !_LD [12] (Int) (CBR)
69045sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
69046sub %i0, %i2, %i2
69047lduw [%i2 + 0], %o0
69048! move %o0(lower) -> %o0(upper)
69049sllx %o0, 32, %o0
69050
69051! cbranch
69052andcc %l0, 1, %g0
69053be,pt %xcc, TARGET6593
69054nop
69055RET6593:
69056
69057! lfsr step begin
69058srlx %l0, 1, %l7
69059xnor %l7, %l0, %l7
69060sllx %l7, 63, %l7
69061or %l7, %l0, %l0
69062srlx %l0, 1, %l0
69063
69064
69065P6594: !_SWAP [11] (maybe <- 0x30000e3) (Int)
69066sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
69067sub %i0, %i3, %i3
69068mov %l4, %l6
69069swap [%i3 + 12], %l6
69070! move %l6(lower) -> %o0(lower)
69071srl %l6, 0, %o5
69072or %o5, %o0, %o0
69073add %l4, 1, %l4
69074
69075P6595: !_MEMBAR (FP) (CBR)
69076
69077! cbranch
69078andcc %l0, 1, %g0
69079be,pn %xcc, TARGET6595
69080nop
69081RET6595:
69082
69083! lfsr step begin
69084srlx %l0, 1, %l7
69085xnor %l7, %l0, %l7
69086sllx %l7, 63, %l7
69087or %l7, %l0, %l0
69088srlx %l0, 1, %l0
69089
69090
69091P6596: !_BSTC [5] (maybe <- 0x428000a9) (FP) (CBR)
69092wr %g0, 0xe0, %asi
69093! preparing store val #0, next val will be in f32
69094fmovs %f16, %f20
69095fadds %f16, %f17, %f16
69096! preparing store val #1, next val will be in f33
69097fmovs %f16, %f21
69098fadds %f16, %f17, %f16
69099! preparing store val #2, next val will be in f35
69100fmovd %f20, %f32
69101fmovs %f16, %f21
69102fadds %f16, %f17, %f16
69103fmovd %f20, %f34
69104membar #Sync
69105stda %f32, [%i1 + 0 ] %asi
69106
69107! cbranch
69108andcc %l0, 1, %g0
69109be,pn %xcc, TARGET6596
69110nop
69111RET6596:
69112
69113! lfsr step begin
69114srlx %l0, 1, %l7
69115xnor %l7, %l0, %l7
69116sllx %l7, 63, %l7
69117or %l7, %l0, %l0
69118srlx %l0, 1, %l0
69119
69120
69121P6597: !_MEMBAR (FP)
69122membar #StoreLoad
69123
69124P6598: !_PREFETCH [8] (Int)
69125sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
69126sub %i0, %i2, %i2
69127prefetch [%i2 + 12], 1
69128
69129P6599: !_LDD [8] (Int)
69130ldd [%i2 + 8], %l6
69131! move %l7(lower) -> %o1(upper)
69132sllx %l7, 32, %o1
69133
69134P6600: !_DWLD [16] (Int)
69135sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
69136add %i0, %i3, %i3
69137ldx [%i3 + 0], %l6
69138! move %l6(upper) -> %o1(lower)
69139srlx %l6, 32, %l3
69140or %l3, %o1, %o1
69141! move %l6(lower) -> %o2(upper)
69142sllx %l6, 32, %o2
69143
69144P6601: !_CASX [20] (maybe <- 0x30000e4) (Int)
69145sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
69146add %i0, %i2, %i2
69147add %i2, 8, %o5
69148ldx [%o5], %l6
69149! move %l6(upper) -> %o2(lower)
69150srlx %l6, 32, %l7
69151or %l7, %o2, %o2
69152! move %l6(lower) -> %o3(upper)
69153sllx %l6, 32, %o3
69154mov %l6, %l7
69155mov %l4, %l6
69156casx [%o5], %l7, %l6
69157! move %l6(upper) -> %o3(lower)
69158srlx %l6, 32, %l7
69159or %l7, %o3, %o3
69160! move %l6(lower) -> %o4(upper)
69161sllx %l6, 32, %o4
69162add %l4, 1, %l4
69163
69164P6602: !_ST [11] (maybe <- 0x30000e5) (Int)
69165sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
69166sub %i0, %i3, %i3
69167stw %l4, [%i3 + 12 ]
69168add %l4, 1, %l4
69169
69170P6603: !_DWST_BINIT [0] (maybe <- 0x30000e6) (Int)
69171wr %g0, 0xe2, %asi
69172sllx %l4, 32, %l6
69173add %l4, 1, %l4
69174or %l6, %l4, %l6
69175stxa %l6, [%i0 + 0] %asi
69176add %l4, 1, %l4
69177
69178P6604: !_MEMBAR (Int)
69179membar #StoreLoad
69180
69181P6605: !_CAS [4] (maybe <- 0x30000e8) (Int)
69182add %i1, 4, %l6
69183lduw [%l6], %o5
69184mov %o5, %l3
69185! move %l3(lower) -> %o4(lower)
69186or %l3, %o4, %o4
69187!---- flushing int results buffer----
69188mov %o0, %l5
69189mov %o1, %l5
69190mov %o2, %l5
69191mov %o3, %l5
69192mov %o4, %l5
69193mov %l4, %o0
69194cas [%l6], %l3, %o0
69195! move %o0(lower) -> %o0(upper)
69196sllx %o0, 32, %o0
69197add %l4, 1, %l4
69198
69199P6606: !_CASX [7] (maybe <- 0x30000e9) (Int)
69200sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
69201sub %i0, %i2, %i2
69202ldx [%i2], %o5
69203! move %o5(upper) -> %o0(lower)
69204srlx %o5, 32, %l3
69205or %l3, %o0, %o0
69206! move %o5(lower) -> %o1(upper)
69207sllx %o5, 32, %o1
69208mov %o5, %l3
69209sllx %l4, 32, %o5
69210add %l4, 1, %l4
69211or %l4, %o5, %o5
69212casx [%i2], %l3, %o5
69213! move %o5(upper) -> %o1(lower)
69214srlx %o5, 32, %l3
69215or %l3, %o1, %o1
69216! move %o5(lower) -> %o2(upper)
69217sllx %o5, 32, %o2
69218add %l4, 1, %l4
69219
69220P6607: !_REPLACEMENT [11] (Int)
69221sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
69222add %i0, %i3, %i3
69223sethi %hi(0x20000), %l3
69224ld [%i3+12], %l7
69225st %l7, [%i3+12]
69226add %i3, %l3, %l6
69227ld [%l6+12], %l7
69228st %l7, [%l6+12]
69229add %l6, %l3, %l6
69230ld [%l6+12], %l7
69231st %l7, [%l6+12]
69232add %l6, %l3, %l6
69233ld [%l6+12], %l7
69234st %l7, [%l6+12]
69235add %l6, %l3, %l6
69236ld [%l6+12], %l7
69237st %l7, [%l6+12]
69238add %l6, %l3, %l6
69239ld [%l6+12], %l7
69240st %l7, [%l6+12]
69241add %l6, %l3, %l6
69242ld [%l6+12], %l7
69243st %l7, [%l6+12]
69244add %l6, %l3, %l6
69245ld [%l6+12], %l7
69246st %l7, [%l6+12]
69247
69248P6608: !_CASX [1] (maybe <- 0x30000eb) (Int)
69249ldx [%i0], %l7
69250! move %l7(upper) -> %o2(lower)
69251srlx %l7, 32, %o5
69252or %o5, %o2, %o2
69253! move %l7(lower) -> %o3(upper)
69254sllx %l7, 32, %o3
69255mov %l7, %o5
69256sllx %l4, 32, %l7
69257add %l4, 1, %l4
69258or %l4, %l7, %l7
69259casx [%i0], %o5, %l7
69260! move %l7(upper) -> %o3(lower)
69261srlx %l7, 32, %o5
69262or %o5, %o3, %o3
69263! move %l7(lower) -> %o4(upper)
69264sllx %l7, 32, %o4
69265add %l4, 1, %l4
69266
69267P6609: !_DWLD [2] (Int)
69268ldx [%i0 + 8], %l3
69269! move %l3(lower) -> %o4(lower)
69270srl %l3, 0, %o5
69271or %o5, %o4, %o4
69272!---- flushing int results buffer----
69273mov %o0, %l5
69274mov %o1, %l5
69275mov %o2, %l5
69276mov %o3, %l5
69277mov %o4, %l5
69278
69279P6610: !_CAS [2] (maybe <- 0x30000ed) (Int)
69280add %i0, 12, %l7
69281lduw [%l7], %o0
69282mov %o0, %l6
69283! move %l6(lower) -> %o0(upper)
69284sllx %l6, 32, %o0
69285mov %l4, %l3
69286cas [%l7], %l6, %l3
69287! move %l3(lower) -> %o0(lower)
69288srl %l3, 0, %l6
69289or %l6, %o0, %o0
69290add %l4, 1, %l4
69291
69292P6611: !_DWST_BINIT [22] (maybe <- 0x30000ee) (Int)
69293wr %g0, 0xe2, %asi
69294sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
69295sub %i0, %i2, %i2
69296sllx %l4, 32, %l6
69297add %l4, 1, %l4
69298or %l6, %l4, %l6
69299stxa %l6, [%i2 + 0] %asi
69300add %l4, 1, %l4
69301
69302P6612: !_MEMBAR (Int)
69303membar #StoreLoad
69304
69305P6613: !_BLD [17] (FP)
69306wr %g0, 0xf0, %asi
69307sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
69308add %i0, %i3, %i3
69309ldda [%i3 + 0] %asi, %f32
69310membar #Sync
69311! 3 addresses covered
69312fmovd %f32, %f18
69313fmovs %f18, %f13
69314fmovs %f19, %f14
69315fmovd %f34, %f18
69316fmovs %f19, %f15
69317!---- flushing fp results buffer to %f30 ----
69318fmovd %f0, %f30
69319fmovd %f2, %f30
69320fmovd %f4, %f30
69321fmovd %f6, %f30
69322fmovd %f8, %f30
69323fmovd %f10, %f30
69324fmovd %f12, %f30
69325fmovd %f14, %f30
69326!--
69327
69328P6614: !_MEMBAR (FP)
69329
69330P6615: !_LDD [10] (Int)
69331sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
69332sub %i0, %i2, %i2
69333ldd [%i2 + 0], %l6
69334! move %l6(lower) -> %o1(upper)
69335sllx %l6, 32, %o1
69336! move %l7(lower) -> %o1(lower)
69337or %l7, %o1, %o1
69338
69339P6616: !_DWLD [3] (Int)
69340ldx [%i1 + 0], %o2
69341! move %o2(upper) -> %o2(upper)
69342! move %o2(lower) -> %o2(lower)
69343
69344P6617: !_DWLD [11] (Int)
69345ldx [%i2 + 8], %o3
69346! move %o3(lower) -> %o3(upper)
69347sllx %o3, 32, %o3
69348
69349P6618: !_MEMBAR (FP) (CBR)
69350membar #StoreLoad
69351
69352! cbranch
69353andcc %l0, 1, %g0
69354be,pt %xcc, TARGET6618
69355nop
69356RET6618:
69357
69358! lfsr step begin
69359srlx %l0, 1, %l3
69360xnor %l3, %l0, %l3
69361sllx %l3, 63, %l3
69362or %l3, %l0, %l0
69363srlx %l0, 1, %l0
69364
69365
69366P6619: !_BLD [19] (FP)
69367wr %g0, 0xf0, %asi
69368sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
69369add %i0, %i3, %i3
69370ldda [%i3 + 0] %asi, %f0
69371membar #Sync
69372! 3 addresses covered
69373fmovs %f3, %f2
69374
69375P6620: !_MEMBAR (FP) (Branch target of P6358)
69376ba P6621
69377nop
69378
69379TARGET6358:
69380ba RET6358
69381nop
69382
69383
69384P6621: !_ST [8] (maybe <- 0x30000f0) (Int)
69385sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
69386sub %i0, %i2, %i2
69387stw %l4, [%i2 + 12 ]
69388add %l4, 1, %l4
69389
69390P6622: !_DWST_BINIT [5] (maybe <- 0x30000f1) (Int)
69391wr %g0, 0xe2, %asi
69392mov %l4, %l3
69393stxa %l3, [%i1 + 8] %asi
69394add %l4, 1, %l4
69395
69396P6623: !_MEMBAR (Int) (Branch target of P6649)
69397membar #StoreLoad
69398ba P6624
69399nop
69400
69401TARGET6649:
69402ba RET6649
69403nop
69404
69405
69406P6624: !_CAS [14] (maybe <- 0x30000f2) (Int)
69407sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
69408sub %i0, %i3, %i3
69409add %i3, 12, %l3
69410lduw [%l3], %l7
69411mov %l7, %o5
69412! move %o5(lower) -> %o3(lower)
69413or %o5, %o3, %o3
69414mov %l4, %o4
69415cas [%l3], %o5, %o4
69416! move %o4(lower) -> %o4(upper)
69417sllx %o4, 32, %o4
69418add %l4, 1, %l4
69419
69420P6625: !_SWAP [12] (maybe <- 0x30000f3) (Int) (LE)
69421wr %g0, 0x88, %asi
69422mov %l4, %l6
69423! Change single-word-level endianess (big endian <-> little endian)
69424sethi %hi(0xff00ff00), %o5
69425or %o5, %lo(0xff00ff00), %o5
69426and %l6, %o5, %l3
69427srl %l3, 8, %l3
69428sll %l6, 8, %l6
69429and %l6, %o5, %l6
69430or %l6, %l3, %l6
69431srl %l6, 16, %l3
69432sll %l6, 16, %l6
69433srl %l6, 0, %l6
69434or %l6, %l3, %l6
69435swapa [%i3 + 0] %asi, %l6
69436! move %l6(lower) -> %o4(lower)
69437srl %l6, 0, %o5
69438or %o5, %o4, %o4
69439!---- flushing int results buffer----
69440mov %o0, %l5
69441mov %o1, %l5
69442mov %o2, %l5
69443mov %o3, %l5
69444mov %o4, %l5
69445add %l4, 1, %l4
69446
69447P6626: !_ST [22] (maybe <- 0x30000f4) (Int) (Branch target of P6680)
69448sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
69449sub %i0, %i2, %i2
69450stw %l4, [%i2 + 4 ]
69451add %l4, 1, %l4
69452ba P6627
69453nop
69454
69455TARGET6680:
69456ba RET6680
69457nop
69458
69459
69460P6627: !_LDD [8] (Int)
69461sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
69462sub %i0, %i3, %i3
69463ldd [%i3 + 8], %l6
69464! move %l7(lower) -> %o0(upper)
69465sllx %l7, 32, %o0
69466
69467P6628: !_LDD [0] (Int) (LE)
69468wr %g0, 0x88, %asi
69469ldda [%i0 + 0] %asi, %l6
69470! move %l6(lower) -> %o0(lower)
69471or %l6, %o0, %o0
69472! move %l7(lower) -> %o1(upper)
69473sllx %l7, 32, %o1
69474
69475P6629: !_MEMBAR (FP)
69476
69477P6630: !_BSTC [19] (maybe <- 0x428000ac) (FP)
69478wr %g0, 0xe0, %asi
69479sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
69480add %i0, %i2, %i2
69481! preparing store val #0, next val will be in f32
69482fmovs %f16, %f20
69483fadds %f16, %f17, %f16
69484! preparing store val #1, next val will be in f33
69485fmovs %f16, %f21
69486fadds %f16, %f17, %f16
69487! preparing store val #2, next val will be in f35
69488fmovd %f20, %f32
69489fmovs %f16, %f21
69490fadds %f16, %f17, %f16
69491fmovd %f20, %f34
69492membar #Sync
69493stda %f32, [%i2 + 0 ] %asi
69494
69495P6631: !_MEMBAR (FP)
69496
69497P6632: !_BSTC [21] (maybe <- 0x428000af) (FP)
69498wr %g0, 0xe0, %asi
69499sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
69500sub %i0, %i3, %i3
69501! preparing store val #0, next val will be in f32
69502fmovs %f16, %f20
69503fadds %f16, %f17, %f16
69504! preparing store val #1, next val will be in f33
69505fmovs %f16, %f21
69506fadds %f16, %f17, %f16
69507! preparing store val #2, next val will be in f35
69508fmovd %f20, %f32
69509fmovs %f16, %f21
69510fadds %f16, %f17, %f16
69511fmovd %f20, %f34
69512membar #Sync
69513stda %f32, [%i3 + 0 ] %asi
69514
69515P6633: !_MEMBAR (FP)
69516membar #StoreLoad
69517
69518P6634: !_PREFETCH [18] (Int)
69519prefetch [%i2 + 0], 3
69520
69521P6635: !_ST [9] (maybe <- 0x30000f5) (Int)
69522sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
69523sub %i0, %i2, %i2
69524stw %l4, [%i2 + 0 ]
69525add %l4, 1, %l4
69526
69527P6636: !_SWAP [10] (maybe <- 0x30000f6) (Int)
69528mov %l4, %o5
69529swap [%i2 + 4], %o5
69530! move %o5(lower) -> %o1(lower)
69531srl %o5, 0, %l6
69532or %l6, %o1, %o1
69533add %l4, 1, %l4
69534
69535P6637: !_MEMBAR (FP)
69536
69537P6638: !_BSTC [0] (maybe <- 0x428000b2) (FP)
69538wr %g0, 0xe0, %asi
69539! preparing store val #0, next val will be in f32
69540fmovs %f16, %f20
69541fadds %f16, %f17, %f16
69542! preparing store val #1, next val will be in f33
69543fmovs %f16, %f21
69544fadds %f16, %f17, %f16
69545! preparing store val #2, next val will be in f35
69546fmovd %f20, %f32
69547fmovs %f16, %f21
69548fadds %f16, %f17, %f16
69549fmovd %f20, %f34
69550membar #Sync
69551stda %f32, [%i0 + 0 ] %asi
69552
69553P6639: !_MEMBAR (FP)
69554membar #StoreLoad
69555
69556P6640: !_ST_BINIT [6] (maybe <- 0x30000f7) (Int)
69557wr %g0, 0xe2, %asi
69558sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
69559sub %i0, %i3, %i3
69560stwa %l4, [%i3 + 0] %asi
69561add %l4, 1, %l4
69562
69563P6641: !_MEMBAR (Int) (CBR)
69564membar #StoreLoad
69565
69566! cbranch
69567andcc %l0, 1, %g0
69568be,pn %xcc, TARGET6641
69569nop
69570RET6641:
69571
69572! lfsr step begin
69573srlx %l0, 1, %l7
69574xnor %l7, %l0, %l7
69575sllx %l7, 63, %l7
69576or %l7, %l0, %l0
69577srlx %l0, 1, %l0
69578
69579
69580P6642: !_LD [21] (Int)
69581sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
69582sub %i0, %i2, %i2
69583lduw [%i2 + 0], %o2
69584! move %o2(lower) -> %o2(upper)
69585sllx %o2, 32, %o2
69586
69587P6643: !_DWLD [17] (Int)
69588sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
69589add %i0, %i3, %i3
69590ldx [%i3 + 8], %l7
69591! move %l7(lower) -> %o2(lower)
69592srl %l7, 0, %l6
69593or %l6, %o2, %o2
69594
69595P6644: !_PREFETCH [9] (Int)
69596sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
69597sub %i0, %i2, %i2
69598prefetch [%i2 + 0], 23
69599
69600P6645: !_CASX [23] (maybe <- 0x30000f8) (Int) (LE)
69601! Change single-word-level endianess (big endian <-> little endian)
69602sethi %hi(0xff00ff00), %l3
69603or %l3, %lo(0xff00ff00), %l3
69604and %l4, %l3, %o5
69605srl %o5, 8, %o5
69606sll %l4, 8, %l6
69607and %l6, %l3, %l6
69608or %l6, %o5, %l6
69609srl %l6, 16, %o5
69610sll %l6, 16, %l6
69611srl %l6, 0, %l6
69612or %l6, %o5, %l6
69613sllx %l6, 32, %l6
69614wr %g0, 0x88, %asi
69615sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
69616sub %i0, %i3, %i3
69617add %i3, 8, %l3
69618ldxa [%l3] %asi, %l7
69619! move %l7(lower) -> %o3(upper)
69620sllx %l7, 32, %o3
69621! move %l7(upper) -> %o3(lower)
69622srlx %l7, 32, %o5
69623or %o5, %o3, %o3
69624mov %l7, %o5
69625mov %l6, %l7
69626casxa [%l3] %asi, %o5, %l7
69627! move %l7(lower) -> %o4(upper)
69628sllx %l7, 32, %o4
69629! move %l7(upper) -> %o4(lower)
69630srlx %l7, 32, %o5
69631or %o5, %o4, %o4
69632!---- flushing int results buffer----
69633mov %o0, %l5
69634mov %o1, %l5
69635mov %o2, %l5
69636mov %o3, %l5
69637mov %o4, %l5
69638add %l4, 1, %l4
69639
69640P6646: !_CAS [23] (maybe <- 0x30000f9) (Int)
69641add %i3, 12, %l3
69642lduw [%l3], %o0
69643mov %o0, %o5
69644! move %o5(lower) -> %o0(upper)
69645sllx %o5, 32, %o0
69646mov %l4, %l7
69647cas [%l3], %o5, %l7
69648! move %l7(lower) -> %o0(lower)
69649srl %l7, 0, %o5
69650or %o5, %o0, %o0
69651add %l4, 1, %l4
69652
69653P6647: !_PREFETCH [20] (Int)
69654sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
69655add %i0, %i2, %i2
69656prefetch [%i2 + 12], 4
69657
69658P6648: !_MEMBAR (FP)
69659
69660P6649: !_BSTC [16] (maybe <- 0x428000b5) (FP) (CBR)
69661wr %g0, 0xe0, %asi
69662sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
69663add %i0, %i3, %i3
69664! preparing store val #0, next val will be in f32
69665fmovs %f16, %f20
69666fadds %f16, %f17, %f16
69667! preparing store val #1, next val will be in f33
69668fmovs %f16, %f21
69669fadds %f16, %f17, %f16
69670! preparing store val #2, next val will be in f35
69671fmovd %f20, %f32
69672fmovs %f16, %f21
69673fadds %f16, %f17, %f16
69674fmovd %f20, %f34
69675membar #Sync
69676stda %f32, [%i3 + 0 ] %asi
69677
69678! cbranch
69679andcc %l0, 1, %g0
69680be,pn %xcc, TARGET6649
69681nop
69682RET6649:
69683
69684! lfsr step begin
69685srlx %l0, 1, %l7
69686xnor %l7, %l0, %l7
69687sllx %l7, 63, %l7
69688or %l7, %l0, %l0
69689srlx %l0, 1, %l0
69690
69691
69692P6650: !_MEMBAR (FP)
69693membar #StoreLoad
69694
69695P6651: !_BLD [13] (FP)
69696wr %g0, 0xf0, %asi
69697sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
69698sub %i0, %i2, %i2
69699ldda [%i2 + 0] %asi, %f32
69700membar #Sync
69701! 3 addresses covered
69702fmovd %f32, %f18
69703fmovs %f18, %f3
69704fmovs %f19, %f4
69705fmovd %f34, %f18
69706fmovs %f19, %f5
69707
69708P6652: !_MEMBAR (FP)
69709
69710P6653: !_BSTC [17] (maybe <- 0x428000b8) (FP)
69711wr %g0, 0xe0, %asi
69712! preparing store val #0, next val will be in f32
69713fmovs %f16, %f20
69714fadds %f16, %f17, %f16
69715! preparing store val #1, next val will be in f33
69716fmovs %f16, %f21
69717fadds %f16, %f17, %f16
69718! preparing store val #2, next val will be in f35
69719fmovd %f20, %f32
69720fmovs %f16, %f21
69721fadds %f16, %f17, %f16
69722fmovd %f20, %f34
69723membar #Sync
69724stda %f32, [%i3 + 0 ] %asi
69725
69726P6654: !_MEMBAR (FP)
69727membar #StoreLoad
69728
69729P6655: !_ST_BINIT [9] (maybe <- 0x30000fa) (Int)
69730wr %g0, 0xe2, %asi
69731sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
69732sub %i0, %i3, %i3
69733stwa %l4, [%i3 + 0] %asi
69734add %l4, 1, %l4
69735
69736P6656: !_MEMBAR (Int)
69737membar #StoreLoad
69738
69739P6657: !_CASX [14] (maybe <- 0x30000fb) (Int) (LE)
69740! Change single-word-level endianess (big endian <-> little endian)
69741sethi %hi(0xff00ff00), %o5
69742or %o5, %lo(0xff00ff00), %o5
69743and %l4, %o5, %l7
69744srl %l7, 8, %l7
69745sll %l4, 8, %l3
69746and %l3, %o5, %l3
69747or %l3, %l7, %l3
69748srl %l3, 16, %l7
69749sll %l3, 16, %l3
69750srl %l3, 0, %l3
69751or %l3, %l7, %l3
69752sllx %l3, 32, %l3
69753wr %g0, 0x88, %asi
69754add %i2, 8, %o5
69755ldxa [%o5] %asi, %l6
69756! move %l6(lower) -> %o1(upper)
69757sllx %l6, 32, %o1
69758! move %l6(upper) -> %o1(lower)
69759srlx %l6, 32, %l7
69760or %l7, %o1, %o1
69761mov %l6, %l7
69762mov %l3, %l6
69763casxa [%o5] %asi, %l7, %l6
69764! move %l6(lower) -> %o2(upper)
69765sllx %l6, 32, %o2
69766! move %l6(upper) -> %o2(lower)
69767srlx %l6, 32, %l7
69768or %l7, %o2, %o2
69769add %l4, 1, %l4
69770
69771P6658: !_PREFETCH [18] (Int)
69772sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i2
69773add %i0, %i2, %i2
69774prefetch [%i2 + 0], 0
69775
69776P6659: !_DWST [10] (maybe <- 0x30000fc) (Int) (Branch target of P6064)
69777sllx %l4, 32, %l7
69778add %l4, 1, %l4
69779or %l7, %l4, %l7
69780stx %l7, [%i3 + 0]
69781add %l4, 1, %l4
69782ba P6660
69783nop
69784
69785TARGET6064:
69786ba RET6064
69787nop
69788
69789
69790P6660: !_MEMBAR (FP)
69791
69792P6661: !_BSTC [20] (maybe <- 0x428000bb) (FP)
69793wr %g0, 0xe0, %asi
69794! preparing store val #0, next val will be in f32
69795fmovs %f16, %f20
69796fadds %f16, %f17, %f16
69797! preparing store val #1, next val will be in f33
69798fmovs %f16, %f21
69799fadds %f16, %f17, %f16
69800! preparing store val #2, next val will be in f35
69801fmovd %f20, %f32
69802fmovs %f16, %f21
69803fadds %f16, %f17, %f16
69804fmovd %f20, %f34
69805membar #Sync
69806stda %f32, [%i2 + 0 ] %asi
69807
69808P6662: !_MEMBAR (FP)
69809membar #StoreLoad
69810
69811P6663: !_LDD [3] (Int)
69812ldd [%i1 + 0], %l6
69813! move %l6(lower) -> %o3(upper)
69814sllx %l6, 32, %o3
69815! move %l7(lower) -> %o3(lower)
69816or %l7, %o3, %o3
69817
69818P6664: !_MEMBAR (FP) (CBR)
69819
69820! cbranch
69821andcc %l0, 1, %g0
69822be,pt %xcc, TARGET6664
69823nop
69824RET6664:
69825
69826! lfsr step begin
69827srlx %l0, 1, %l3
69828xnor %l3, %l0, %l3
69829sllx %l3, 63, %l3
69830or %l3, %l0, %l0
69831srlx %l0, 1, %l0
69832
69833
69834P6665: !_BST [1] (maybe <- 0x428000be) (FP)
69835wr %g0, 0xf0, %asi
69836! preparing store val #0, next val will be in f32
69837fmovs %f16, %f20
69838fadds %f16, %f17, %f16
69839! preparing store val #1, next val will be in f33
69840fmovs %f16, %f21
69841fadds %f16, %f17, %f16
69842! preparing store val #2, next val will be in f35
69843fmovd %f20, %f32
69844fmovs %f16, %f21
69845fadds %f16, %f17, %f16
69846fmovd %f20, %f34
69847membar #Sync
69848stda %f32, [%i0 + 0 ] %asi
69849
69850P6666: !_MEMBAR (FP)
69851membar #StoreLoad
69852
69853P6667: !_SWAP [19] (maybe <- 0x30000fe) (Int)
69854mov %l4, %o4
69855swap [%i2 + 4], %o4
69856! move %o4(lower) -> %o4(upper)
69857sllx %o4, 32, %o4
69858add %l4, 1, %l4
69859
69860P6668: !_LDD [4] (Int)
69861ldd [%i1 + 0], %l6
69862! move %l6(lower) -> %o4(lower)
69863or %l6, %o4, %o4
69864!---- flushing int results buffer----
69865mov %o0, %l5
69866mov %o1, %l5
69867mov %o2, %l5
69868mov %o3, %l5
69869mov %o4, %l5
69870! move %l7(lower) -> %o0(upper)
69871sllx %l7, 32, %o0
69872
69873P6669: !_DWST_BINIT [10] (maybe <- 0x30000ff) (Int)
69874wr %g0, 0xe2, %asi
69875sllx %l4, 32, %l3
69876add %l4, 1, %l4
69877or %l3, %l4, %l3
69878stxa %l3, [%i3 + 0] %asi
69879add %l4, 1, %l4
69880
69881P6670: !_MEMBAR (Int)
69882membar #StoreLoad
69883
69884P6671: !_DWLD [23] (Int)
69885sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
69886sub %i0, %i3, %i3
69887ldx [%i3 + 8], %l3
69888! move %l3(lower) -> %o0(lower)
69889srl %l3, 0, %o5
69890or %o5, %o0, %o0
69891
69892P6672: !_DWLD [21] (Int)
69893ldx [%i3 + 0], %o1
69894! move %o1(upper) -> %o1(upper)
69895! move %o1(lower) -> %o1(lower)
69896
69897P6673: !_PREFETCH [20] (Int)
69898prefetch [%i2 + 12], 23
69899
69900P6674: !_LD [7] (Int)
69901sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
69902sub %i0, %i2, %i2
69903lduw [%i2 + 4], %o2
69904! move %o2(lower) -> %o2(upper)
69905sllx %o2, 32, %o2
69906
69907P6675: !_DWST_BINIT [19] (maybe <- 0x3000101) (Int)
69908wr %g0, 0xe2, %asi
69909sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
69910add %i0, %i3, %i3
69911sllx %l4, 32, %l6
69912add %l4, 1, %l4
69913or %l6, %l4, %l6
69914stxa %l6, [%i3 + 0] %asi
69915add %l4, 1, %l4
69916
69917P6676: !_MEMBAR (Int)
69918membar #StoreLoad
69919
69920P6677: !_SWAP [12] (maybe <- 0x3000103) (Int)
69921sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
69922sub %i0, %i2, %i2
69923mov %l4, %l7
69924swap [%i2 + 0], %l7
69925! move %l7(lower) -> %o2(lower)
69926srl %l7, 0, %l3
69927or %l3, %o2, %o2
69928add %l4, 1, %l4
69929
69930P6678: !_SWAP [19] (maybe <- 0x3000104) (Int)
69931mov %l4, %o3
69932swap [%i3 + 4], %o3
69933! move %o3(lower) -> %o3(upper)
69934sllx %o3, 32, %o3
69935add %l4, 1, %l4
69936
69937P6679: !_DWLD [7] (Int)
69938sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
69939sub %i0, %i3, %i3
69940ldx [%i3 + 0], %o5
69941! move %o5(upper) -> %o3(lower)
69942srlx %o5, 32, %l7
69943or %l7, %o3, %o3
69944! move %o5(lower) -> %o4(upper)
69945sllx %o5, 32, %o4
69946
69947P6680: !_DWST_BINIT [8] (maybe <- 0x3000105) (Int) (CBR)
69948wr %g0, 0xe2, %asi
69949mov %l4, %l3
69950stxa %l3, [%i3 + 8] %asi
69951add %l4, 1, %l4
69952
69953! cbranch
69954andcc %l0, 1, %g0
69955be,pn %xcc, TARGET6680
69956nop
69957RET6680:
69958
69959! lfsr step begin
69960srlx %l0, 1, %o5
69961xnor %o5, %l0, %o5
69962sllx %o5, 63, %o5
69963or %o5, %l0, %l0
69964srlx %l0, 1, %l0
69965
69966
69967P6681: !_MEMBAR (Int)
69968membar #StoreLoad
69969
69970P6682: !_CASX [12] (maybe <- 0x3000106) (Int) (LE)
69971sllx %l4, 32, %l6
69972add %l4, 1, %l4
69973or %l4, %l6, %l6
69974! Change double-word-level endianess (big endian <-> little endian)
69975sethi %hi(0xff00ff00), %l3
69976or %l3, %lo(0xff00ff00), %l3
69977sllx %l3, 32, %l7
69978or %l3, %l7, %l3
69979and %l6, %l3, %l7
69980srlx %l7, 8, %l7
69981sllx %l6, 8, %l6
69982and %l6, %l3, %l6
69983or %l6, %l7, %l6
69984sethi %hi(0xffff0000), %l3
69985srlx %l6, 16, %l7
69986andn %l7, %l3, %l7
69987andn %l6, %l3, %l6
69988sllx %l6, 16, %l6
69989or %l6, %l7, %l6
69990srlx %l6, 32, %l7
69991sllx %l6, 32, %l6
69992or %l6, %l7, %l7
69993wr %g0, 0x88, %asi
69994ldxa [%i2] %asi, %o5
69995! move %o5(lower) -> %o4(lower)
69996srl %o5, 0, %l3
69997or %l3, %o4, %o4
69998!---- flushing int results buffer----
69999mov %o0, %l5
70000mov %o1, %l5
70001mov %o2, %l5
70002mov %o3, %l5
70003mov %o4, %l5
70004! move %o5(upper) -> %o0(upper)
70005or %o5, %g0, %o0
70006mov %o5, %l3
70007mov %l7, %o5
70008casxa [%i2] %asi, %l3, %o5
70009! move %o5(lower) -> %o0(lower)
70010srlx %o0, 32, %o0
70011sllx %o0, 32, %o0
70012srl %o5, 0, %l3
70013or %l3, %o0, %o0
70014! move %o5(upper) -> %o1(upper)
70015or %o5, %g0, %o1
70016add %l4, 1, %l4
70017
70018P6683: !_ST [13] (maybe <- 0x3000108) (Int)
70019stw %l4, [%i2 + 4 ]
70020add %l4, 1, %l4
70021
70022P6684: !_ST_BINIT [6] (maybe <- 0x3000109) (Int) (CBR)
70023wr %g0, 0xe2, %asi
70024stwa %l4, [%i3 + 0] %asi
70025add %l4, 1, %l4
70026
70027! cbranch
70028andcc %l0, 1, %g0
70029be,pt %xcc, TARGET6684
70030nop
70031RET6684:
70032
70033! lfsr step begin
70034srlx %l0, 1, %l7
70035xnor %l7, %l0, %l7
70036sllx %l7, 63, %l7
70037or %l7, %l0, %l0
70038srlx %l0, 1, %l0
70039
70040
70041P6685: !_MEMBAR (Int)
70042membar #StoreLoad
70043
70044P6686: !_ST_BINIT [3] (maybe <- 0x300010a) (Int)
70045wr %g0, 0xe2, %asi
70046stwa %l4, [%i1 + 0] %asi
70047add %l4, 1, %l4
70048
70049P6687: !_MEMBAR (Int)
70050membar #StoreLoad
70051
70052P6688: !_CASX [15] (maybe <- 0x300010b) (Int)
70053sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
70054add %i0, %i2, %i2
70055ldx [%i2], %l6
70056! move %l6(upper) -> %o1(lower)
70057srlx %o1, 32, %o1
70058sllx %o1, 32, %o1
70059srlx %l6, 32, %l7
70060or %l7, %o1, %o1
70061! move %l6(lower) -> %o2(upper)
70062sllx %l6, 32, %o2
70063mov %l6, %l7
70064sllx %l4, 32, %l6
70065add %l4, 1, %l4
70066or %l4, %l6, %l6
70067casx [%i2], %l7, %l6
70068! move %l6(upper) -> %o2(lower)
70069srlx %l6, 32, %l7
70070or %l7, %o2, %o2
70071! move %l6(lower) -> %o3(upper)
70072sllx %l6, 32, %o3
70073add %l4, 1, %l4
70074
70075P6689: !_LDD [23] (Int)
70076sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
70077sub %i0, %i3, %i3
70078ldd [%i3 + 8], %l6
70079! move %l7(lower) -> %o3(lower)
70080or %l7, %o3, %o3
70081
70082P6690: !_ST_BINIT [4] (maybe <- 0x300010d) (Int)
70083wr %g0, 0xe2, %asi
70084stwa %l4, [%i1 + 4] %asi
70085add %l4, 1, %l4
70086
70087P6691: !_MEMBAR (Int)
70088membar #StoreLoad
70089
70090P6692: !_SWAP [6] (maybe <- 0x300010e) (Int)
70091sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
70092sub %i0, %i2, %i2
70093mov %l4, %o4
70094swap [%i2 + 0], %o4
70095! move %o4(lower) -> %o4(upper)
70096sllx %o4, 32, %o4
70097add %l4, 1, %l4
70098
70099P6693: !_DWST_BINIT [23] (maybe <- 0x300010f) (Int)
70100wr %g0, 0xe2, %asi
70101mov %l4, %l7
70102stxa %l7, [%i3 + 8] %asi
70103add %l4, 1, %l4
70104
70105P6694: !_MEMBAR (Int)
70106membar #StoreLoad
70107
70108P6695: !_PREFETCH [7] (Int)
70109prefetch [%i2 + 4], 17
70110
70111P6696: !_LDD [7] (Int)
70112ldd [%i2 + 0], %l6
70113! move %l6(lower) -> %o4(lower)
70114or %l6, %o4, %o4
70115!---- flushing int results buffer----
70116mov %o0, %l5
70117mov %o1, %l5
70118mov %o2, %l5
70119mov %o3, %l5
70120mov %o4, %l5
70121! move %l7(lower) -> %o0(upper)
70122sllx %l7, 32, %o0
70123
70124P6697: !_LDD [4] (Int)
70125ldd [%i1 + 0], %l6
70126! move %l6(lower) -> %o0(lower)
70127or %l6, %o0, %o0
70128! move %l7(lower) -> %o1(upper)
70129sllx %l7, 32, %o1
70130
70131P6698: !_CAS [16] (maybe <- 0x3000110) (Int)
70132sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
70133add %i0, %i3, %i3
70134add %i3, 4, %l6
70135lduw [%l6], %o5
70136mov %o5, %l3
70137! move %l3(lower) -> %o1(lower)
70138or %l3, %o1, %o1
70139mov %l4, %o2
70140cas [%l6], %l3, %o2
70141! move %o2(lower) -> %o2(upper)
70142sllx %o2, 32, %o2
70143add %l4, 1, %l4
70144
70145P6699: !_CAS [8] (maybe <- 0x3000111) (Int)
70146add %i2, 12, %l6
70147lduw [%l6], %o5
70148mov %o5, %l3
70149! move %l3(lower) -> %o2(lower)
70150or %l3, %o2, %o2
70151mov %l4, %o3
70152cas [%l6], %l3, %o3
70153! move %o3(lower) -> %o3(upper)
70154sllx %o3, 32, %o3
70155add %l4, 1, %l4
70156
70157P6700: !_REPLACEMENT [10] (Int)
70158sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
70159sub %i0, %i2, %i2
70160sethi %hi(0x20000), %l3
70161ld [%i2+4], %l7
70162st %l7, [%i2+4]
70163add %i2, %l3, %l6
70164ld [%l6+4], %l7
70165st %l7, [%l6+4]
70166add %l6, %l3, %l6
70167ld [%l6+4], %l7
70168st %l7, [%l6+4]
70169add %l6, %l3, %l6
70170ld [%l6+4], %l7
70171st %l7, [%l6+4]
70172add %l6, %l3, %l6
70173ld [%l6+4], %l7
70174st %l7, [%l6+4]
70175add %l6, %l3, %l6
70176ld [%l6+4], %l7
70177st %l7, [%l6+4]
70178add %l6, %l3, %l6
70179ld [%l6+4], %l7
70180st %l7, [%l6+4]
70181add %l6, %l3, %l6
70182ld [%l6+4], %l7
70183st %l7, [%l6+4]
70184
70185P6701: !_MEMBAR (FP) (CBR)
70186
70187! cbranch
70188andcc %l0, 1, %g0
70189be,pn %xcc, TARGET6701
70190nop
70191RET6701:
70192
70193! lfsr step begin
70194srlx %l0, 1, %o5
70195xnor %o5, %l0, %o5
70196sllx %o5, 63, %o5
70197or %o5, %l0, %l0
70198srlx %l0, 1, %l0
70199
70200
70201P6702: !_BST [8] (maybe <- 0x428000c1) (FP)
70202wr %g0, 0xf0, %asi
70203sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
70204sub %i0, %i3, %i3
70205! preparing store val #0, next val will be in f32
70206fmovs %f16, %f20
70207fadds %f16, %f17, %f16
70208! preparing store val #1, next val will be in f33
70209fmovs %f16, %f21
70210fadds %f16, %f17, %f16
70211! preparing store val #2, next val will be in f35
70212fmovd %f20, %f32
70213fmovs %f16, %f21
70214fadds %f16, %f17, %f16
70215fmovd %f20, %f34
70216membar #Sync
70217stda %f32, [%i3 + 0 ] %asi
70218
70219P6703: !_MEMBAR (FP)
70220membar #StoreLoad
70221
70222P6704: !_BLD [10] (FP)
70223wr %g0, 0xf0, %asi
70224sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
70225sub %i0, %i2, %i2
70226ldda [%i2 + 0] %asi, %f32
70227membar #Sync
70228! 3 addresses covered
70229fmovd %f32, %f6
70230fmovd %f34, %f18
70231fmovs %f19, %f8
70232
70233P6705: !_MEMBAR (FP)
70234
70235P6706: !_LD [4] (Int)
70236lduw [%i1 + 4], %l3
70237! move %l3(lower) -> %o3(lower)
70238or %l3, %o3, %o3
70239
70240P6707: !_MEMBAR (FP)
70241
70242P6708: !_BST [9] (maybe <- 0x428000c4) (FP)
70243wr %g0, 0xf0, %asi
70244! preparing store val #0, next val will be in f32
70245fmovs %f16, %f20
70246fadds %f16, %f17, %f16
70247! preparing store val #1, next val will be in f33
70248fmovs %f16, %f21
70249fadds %f16, %f17, %f16
70250! preparing store val #2, next val will be in f35
70251fmovd %f20, %f32
70252fmovs %f16, %f21
70253fadds %f16, %f17, %f16
70254fmovd %f20, %f34
70255membar #Sync
70256stda %f32, [%i2 + 0 ] %asi
70257
70258P6709: !_MEMBAR (FP)
70259membar #StoreLoad
70260
70261P6710: !_CAS [4] (maybe <- 0x3000112) (Int)
70262add %i1, 4, %l6
70263lduw [%l6], %o4
70264mov %o4, %l3
70265! move %l3(lower) -> %o4(upper)
70266sllx %l3, 32, %o4
70267mov %l4, %o5
70268cas [%l6], %l3, %o5
70269! move %o5(lower) -> %o4(lower)
70270srl %o5, 0, %l3
70271or %l3, %o4, %o4
70272!---- flushing int results buffer----
70273mov %o0, %l5
70274mov %o1, %l5
70275mov %o2, %l5
70276mov %o3, %l5
70277mov %o4, %l5
70278add %l4, 1, %l4
70279
70280P6711: !_LD [18] (Int) (CBR)
70281sethi %hi(REGION6_ALIAS0_O-REGION0_ALIAS0_O), %i3
70282add %i0, %i3, %i3
70283lduw [%i3 + 0], %o0
70284! move %o0(lower) -> %o0(upper)
70285sllx %o0, 32, %o0
70286
70287! cbranch
70288andcc %l0, 1, %g0
70289be,pt %xcc, TARGET6711
70290nop
70291RET6711:
70292
70293! lfsr step begin
70294srlx %l0, 1, %l7
70295xnor %l7, %l0, %l7
70296sllx %l7, 63, %l7
70297or %l7, %l0, %l0
70298srlx %l0, 1, %l0
70299
70300
70301P6712: !_SWAP [13] (maybe <- 0x3000113) (Int)
70302sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
70303sub %i0, %i2, %i2
70304mov %l4, %l6
70305swap [%i2 + 4], %l6
70306! move %l6(lower) -> %o0(lower)
70307srl %l6, 0, %o5
70308or %o5, %o0, %o0
70309add %l4, 1, %l4
70310
70311P6713: !_DWLD [17] (Int)
70312sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
70313add %i0, %i3, %i3
70314ldx [%i3 + 8], %o1
70315! move %o1(lower) -> %o1(upper)
70316sllx %o1, 32, %o1
70317
70318P6714: !_ST [22] (maybe <- 0x3000114) (Int)
70319sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
70320sub %i0, %i2, %i2
70321stw %l4, [%i2 + 4 ]
70322add %l4, 1, %l4
70323
70324P6715: !_MEMBAR (FP)
70325
70326P6716: !_BST [0] (maybe <- 0x428000c7) (FP)
70327wr %g0, 0xf0, %asi
70328! preparing store val #0, next val will be in f32
70329fmovs %f16, %f20
70330fadds %f16, %f17, %f16
70331! preparing store val #1, next val will be in f33
70332fmovs %f16, %f21
70333fadds %f16, %f17, %f16
70334! preparing store val #2, next val will be in f35
70335fmovd %f20, %f32
70336fmovs %f16, %f21
70337fadds %f16, %f17, %f16
70338fmovd %f20, %f34
70339membar #Sync
70340stda %f32, [%i0 + 0 ] %asi
70341
70342P6717: !_MEMBAR (FP) (Branch target of P6304)
70343ba P6718
70344nop
70345
70346TARGET6304:
70347ba RET6304
70348nop
70349
70350
70351P6718: !_BST [19] (maybe <- 0x428000ca) (FP)
70352wr %g0, 0xf0, %asi
70353sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
70354sub %i0, %i3, %i3
70355! preparing store val #0, next val will be in f32
70356fmovs %f16, %f20
70357fadds %f16, %f17, %f16
70358! preparing store val #1, next val will be in f33
70359fmovs %f16, %f21
70360fadds %f16, %f17, %f16
70361! preparing store val #2, next val will be in f35
70362fmovd %f20, %f32
70363fmovs %f16, %f21
70364fadds %f16, %f17, %f16
70365fmovd %f20, %f34
70366membar #Sync
70367stda %f32, [%i3 + 0 ] %asi
70368
70369P6719: !_MEMBAR (FP)
70370
70371P6720: !_BST [2] (maybe <- 0x428000cd) (FP)
70372wr %g0, 0xf0, %asi
70373! preparing store val #0, next val will be in f32
70374fmovs %f16, %f20
70375fadds %f16, %f17, %f16
70376! preparing store val #1, next val will be in f33
70377fmovs %f16, %f21
70378fadds %f16, %f17, %f16
70379! preparing store val #2, next val will be in f35
70380fmovd %f20, %f32
70381fmovs %f16, %f21
70382fadds %f16, %f17, %f16
70383fmovd %f20, %f34
70384membar #Sync
70385stda %f32, [%i0 + 0 ] %asi
70386
70387P6721: !_MEMBAR (FP) (CBR)
70388membar #StoreLoad
70389
70390! cbranch
70391andcc %l0, 1, %g0
70392be,pn %xcc, TARGET6721
70393nop
70394RET6721:
70395
70396! lfsr step begin
70397srlx %l0, 1, %l6
70398xnor %l6, %l0, %l6
70399sllx %l6, 63, %l6
70400or %l6, %l0, %l0
70401srlx %l0, 1, %l0
70402
70403
70404P6722: !_DWST_BINIT [3] (maybe <- 0x3000115) (Int) (CBR)
70405wr %g0, 0xe2, %asi
70406sllx %l4, 32, %l7
70407add %l4, 1, %l4
70408or %l7, %l4, %l7
70409stxa %l7, [%i1 + 0] %asi
70410add %l4, 1, %l4
70411
70412! cbranch
70413andcc %l0, 1, %g0
70414be,pn %xcc, TARGET6722
70415nop
70416RET6722:
70417
70418! lfsr step begin
70419srlx %l0, 1, %l6
70420xnor %l6, %l0, %l6
70421sllx %l6, 63, %l6
70422or %l6, %l0, %l0
70423srlx %l0, 1, %l0
70424
70425
70426P6723: !_MEMBAR (Int)
70427membar #StoreLoad
70428
70429P6724: !_CAS [15] (maybe <- 0x3000117) (Int)
70430sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
70431add %i0, %i2, %i2
70432lduw [%i2], %l6
70433mov %l6, %l7
70434! move %l7(lower) -> %o1(lower)
70435or %l7, %o1, %o1
70436mov %l4, %o2
70437cas [%i2], %l7, %o2
70438! move %o2(lower) -> %o2(upper)
70439sllx %o2, 32, %o2
70440add %l4, 1, %l4
70441
70442P6725: !_ST_BINIT [21] (maybe <- 0x3000118) (Int)
70443wr %g0, 0xe2, %asi
70444sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
70445sub %i0, %i3, %i3
70446stwa %l4, [%i3 + 0] %asi
70447add %l4, 1, %l4
70448
70449P6726: !_MEMBAR (Int)
70450membar #StoreLoad
70451
70452P6727: !_REPLACEMENT [11] (Int)
70453sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
70454sub %i0, %i2, %i2
70455sethi %hi(0x20000), %l6
70456ld [%i2+12], %o5
70457st %o5, [%i2+12]
70458add %i2, %l6, %l7
70459ld [%l7+12], %o5
70460st %o5, [%l7+12]
70461add %l7, %l6, %l7
70462ld [%l7+12], %o5
70463st %o5, [%l7+12]
70464add %l7, %l6, %l7
70465ld [%l7+12], %o5
70466st %o5, [%l7+12]
70467add %l7, %l6, %l7
70468ld [%l7+12], %o5
70469st %o5, [%l7+12]
70470add %l7, %l6, %l7
70471ld [%l7+12], %o5
70472st %o5, [%l7+12]
70473add %l7, %l6, %l7
70474ld [%l7+12], %o5
70475st %o5, [%l7+12]
70476add %l7, %l6, %l7
70477ld [%l7+12], %o5
70478st %o5, [%l7+12]
70479
70480P6728: !_LDD [22] (Int)
70481ldd [%i3 + 0], %l6
70482! move %l6(lower) -> %o2(lower)
70483or %l6, %o2, %o2
70484! move %l7(lower) -> %o3(upper)
70485sllx %l7, 32, %o3
70486
70487P6729: !_ST [18] (maybe <- 0x3000119) (Int) (CBR)
70488sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
70489sub %i0, %i3, %i3
70490stw %l4, [%i3 + 0 ]
70491add %l4, 1, %l4
70492
70493! cbranch
70494andcc %l0, 1, %g0
70495be,pn %xcc, TARGET6729
70496nop
70497RET6729:
70498
70499! lfsr step begin
70500srlx %l0, 1, %o5
70501xnor %o5, %l0, %o5
70502sllx %o5, 63, %o5
70503or %o5, %l0, %l0
70504srlx %l0, 1, %l0
70505
70506
70507P6730: !_LD [22] (Int)
70508sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
70509sub %i0, %i2, %i2
70510lduw [%i2 + 4], %l6
70511! move %l6(lower) -> %o3(lower)
70512or %l6, %o3, %o3
70513
70514P6731: !_PREFETCH [1] (Int)
70515prefetch [%i0 + 4], 23
70516
70517P6732: !_LD [4] (Int)
70518lduw [%i1 + 4], %o4
70519! move %o4(lower) -> %o4(upper)
70520sllx %o4, 32, %o4
70521
70522P6733: !_LDD [12] (Int)
70523sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
70524sub %i0, %i3, %i3
70525ldd [%i3 + 0], %l6
70526! move %l6(lower) -> %o4(lower)
70527or %l6, %o4, %o4
70528!---- flushing int results buffer----
70529mov %o0, %l5
70530mov %o1, %l5
70531mov %o2, %l5
70532mov %o3, %l5
70533mov %o4, %l5
70534! move %l7(lower) -> %o0(upper)
70535sllx %l7, 32, %o0
70536
70537P6734: !_MEMBAR (FP)
70538
70539P6735: !_BSTC [8] (maybe <- 0x428000d0) (FP)
70540wr %g0, 0xe0, %asi
70541sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
70542sub %i0, %i2, %i2
70543! preparing store val #0, next val will be in f32
70544fmovs %f16, %f20
70545fadds %f16, %f17, %f16
70546! preparing store val #1, next val will be in f33
70547fmovs %f16, %f21
70548fadds %f16, %f17, %f16
70549! preparing store val #2, next val will be in f35
70550fmovd %f20, %f32
70551fmovs %f16, %f21
70552fadds %f16, %f17, %f16
70553fmovd %f20, %f34
70554membar #Sync
70555stda %f32, [%i2 + 0 ] %asi
70556
70557P6736: !_MEMBAR (FP)
70558membar #StoreLoad
70559
70560P6737: !_SWAP [10] (maybe <- 0x300011a) (Int) (CBR)
70561sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
70562sub %i0, %i3, %i3
70563mov %l4, %l6
70564swap [%i3 + 4], %l6
70565! move %l6(lower) -> %o0(lower)
70566srl %l6, 0, %o5
70567or %o5, %o0, %o0
70568add %l4, 1, %l4
70569
70570! cbranch
70571andcc %l0, 1, %g0
70572be,pn %xcc, TARGET6737
70573nop
70574RET6737:
70575
70576! lfsr step begin
70577srlx %l0, 1, %l7
70578xnor %l7, %l0, %l7
70579sllx %l7, 63, %l7
70580or %l7, %l0, %l0
70581srlx %l0, 1, %l0
70582
70583
70584P6738: !_CAS [23] (maybe <- 0x300011b) (Int) (LE)
70585! Change single-word-level endianess (big endian <-> little endian)
70586sethi %hi(0xff00ff00), %l3
70587or %l3, %lo(0xff00ff00), %l3
70588and %l4, %l3, %o5
70589srl %o5, 8, %o5
70590sll %l4, 8, %l6
70591and %l6, %l3, %l6
70592or %l6, %o5, %l6
70593srl %l6, 16, %o5
70594sll %l6, 16, %l6
70595srl %l6, 0, %l6
70596or %l6, %o5, %l6
70597wr %g0, 0x88, %asi
70598sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
70599sub %i0, %i2, %i2
70600add %i2, 12, %l3
70601lduwa [%l3] %asi, %o1
70602mov %o1, %o5
70603! move %o5(lower) -> %o1(upper)
70604sllx %o5, 32, %o1
70605mov %l6, %l7
70606casa [%l3] %asi, %o5, %l7
70607! move %l7(lower) -> %o1(lower)
70608srl %l7, 0, %o5
70609or %o5, %o1, %o1
70610add %l4, 1, %l4
70611
70612P6739: !_LDD [18] (Int)
70613sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
70614sub %i0, %i3, %i3
70615ldd [%i3 + 0], %l6
70616! move %l6(lower) -> %o2(upper)
70617sllx %l6, 32, %o2
70618! move %l7(lower) -> %o2(lower)
70619or %l7, %o2, %o2
70620
70621P6740: !_SWAP [15] (maybe <- 0x300011c) (Int)
70622sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
70623add %i0, %i2, %i2
70624mov %l4, %o3
70625swap [%i2 + 0], %o3
70626! move %o3(lower) -> %o3(upper)
70627sllx %o3, 32, %o3
70628add %l4, 1, %l4
70629
70630P6741: !_LDD [7] (Int)
70631sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
70632sub %i0, %i3, %i3
70633ldd [%i3 + 0], %l6
70634! move %l6(lower) -> %o3(lower)
70635or %l6, %o3, %o3
70636! move %l7(lower) -> %o4(upper)
70637sllx %l7, 32, %o4
70638
70639P6742: !_DWST [10] (maybe <- 0x300011d) (Int)
70640sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
70641sub %i0, %i2, %i2
70642sllx %l4, 32, %l3
70643add %l4, 1, %l4
70644or %l3, %l4, %l3
70645stx %l3, [%i2 + 0]
70646add %l4, 1, %l4
70647
70648P6743: !_MEMBAR (FP)
70649
70650P6744: !_BST [1] (maybe <- 0x428000d3) (FP)
70651wr %g0, 0xf0, %asi
70652! preparing store val #0, next val will be in f32
70653fmovs %f16, %f20
70654fadds %f16, %f17, %f16
70655! preparing store val #1, next val will be in f33
70656fmovs %f16, %f21
70657fadds %f16, %f17, %f16
70658! preparing store val #2, next val will be in f35
70659fmovd %f20, %f32
70660fmovs %f16, %f21
70661fadds %f16, %f17, %f16
70662fmovd %f20, %f34
70663membar #Sync
70664stda %f32, [%i0 + 0 ] %asi
70665
70666P6745: !_MEMBAR (FP)
70667membar #StoreLoad
70668
70669P6746: !_LDD [3] (Int)
70670ldd [%i1 + 0], %l6
70671! move %l6(lower) -> %o4(lower)
70672or %l6, %o4, %o4
70673!---- flushing int results buffer----
70674mov %o0, %l5
70675mov %o1, %l5
70676mov %o2, %l5
70677mov %o3, %l5
70678mov %o4, %l5
70679! move %l7(lower) -> %o0(upper)
70680sllx %l7, 32, %o0
70681
70682P6747: !_LDD [2] (Int)
70683ldd [%i0 + 8], %l6
70684! move %l7(lower) -> %o0(lower)
70685or %l7, %o0, %o0
70686
70687P6748: !_PREFETCH [21] (Int)
70688sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
70689sub %i0, %i3, %i3
70690prefetch [%i3 + 0], 27
70691
70692P6749: !_DWLD [18] (Int)
70693sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
70694sub %i0, %i2, %i2
70695ldx [%i2 + 0], %o1
70696! move %o1(upper) -> %o1(upper)
70697! move %o1(lower) -> %o1(lower)
70698
70699P6750: !_PREFETCH [5] (Int) (Branch target of P6729)
70700prefetch [%i1 + 12], 27
70701ba P6751
70702nop
70703
70704TARGET6729:
70705ba RET6729
70706nop
70707
70708
70709P6751: !_DWST_BINIT [20] (maybe <- 0x300011f) (Int)
70710wr %g0, 0xe2, %asi
70711mov %l4, %l7
70712stxa %l7, [%i2 + 8] %asi
70713add %l4, 1, %l4
70714
70715P6752: !_MEMBAR (Int)
70716membar #StoreLoad
70717
70718P6753: !_PREFETCH [19] (Int)
70719prefetch [%i2 + 4], 1
70720
70721P6754: !_SWAP [15] (maybe <- 0x3000120) (Int)
70722sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
70723add %i0, %i3, %i3
70724mov %l4, %o2
70725swap [%i3 + 0], %o2
70726! move %o2(lower) -> %o2(upper)
70727sllx %o2, 32, %o2
70728add %l4, 1, %l4
70729
70730P6755: !_MEMBAR (FP)
70731
70732P6756: !_BST [21] (maybe <- 0x428000d6) (FP)
70733wr %g0, 0xf0, %asi
70734sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
70735sub %i0, %i2, %i2
70736! preparing store val #0, next val will be in f32
70737fmovs %f16, %f20
70738fadds %f16, %f17, %f16
70739! preparing store val #1, next val will be in f33
70740fmovs %f16, %f21
70741fadds %f16, %f17, %f16
70742! preparing store val #2, next val will be in f35
70743fmovd %f20, %f32
70744fmovs %f16, %f21
70745fadds %f16, %f17, %f16
70746fmovd %f20, %f34
70747membar #Sync
70748stda %f32, [%i2 + 0 ] %asi
70749
70750P6757: !_MEMBAR (FP)
70751membar #StoreLoad
70752
70753P6758: !_CAS [0] (maybe <- 0x3000121) (Int)
70754lduw [%i0], %l7
70755mov %l7, %o5
70756! move %o5(lower) -> %o2(lower)
70757or %o5, %o2, %o2
70758mov %l4, %o3
70759cas [%i0], %o5, %o3
70760! move %o3(lower) -> %o3(upper)
70761sllx %o3, 32, %o3
70762add %l4, 1, %l4
70763
70764P6759: !_LD [0] (Int)
70765lduw [%i0 + 0], %l3
70766! move %l3(lower) -> %o3(lower)
70767or %l3, %o3, %o3
70768
70769P6760: !_PREFETCH [15] (Int)
70770prefetch [%i3 + 0], 21
70771
70772P6761: !_MEMBAR (FP)
70773membar #StoreLoad
70774
70775P6762: !_BLD [11] (FP) (CBR)
70776wr %g0, 0xf0, %asi
70777sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
70778sub %i0, %i3, %i3
70779ldda [%i3 + 0] %asi, %f32
70780membar #Sync
70781! 3 addresses covered
70782fmovd %f32, %f18
70783fmovs %f18, %f9
70784fmovs %f19, %f10
70785fmovd %f34, %f18
70786fmovs %f19, %f11
70787
70788! cbranch
70789andcc %l0, 1, %g0
70790be,pt %xcc, TARGET6762
70791nop
70792RET6762:
70793
70794! lfsr step begin
70795srlx %l0, 1, %l6
70796xnor %l6, %l0, %l6
70797sllx %l6, 63, %l6
70798or %l6, %l0, %l0
70799srlx %l0, 1, %l0
70800
70801
70802P6763: !_MEMBAR (FP)
70803
70804P6764: !_BSTC [6] (maybe <- 0x428000d9) (FP)
70805wr %g0, 0xe0, %asi
70806sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
70807sub %i0, %i2, %i2
70808! preparing store val #0, next val will be in f32
70809fmovs %f16, %f20
70810fadds %f16, %f17, %f16
70811! preparing store val #1, next val will be in f33
70812fmovs %f16, %f21
70813fadds %f16, %f17, %f16
70814! preparing store val #2, next val will be in f35
70815fmovd %f20, %f32
70816fmovs %f16, %f21
70817fadds %f16, %f17, %f16
70818fmovd %f20, %f34
70819membar #Sync
70820stda %f32, [%i2 + 0 ] %asi
70821
70822P6765: !_MEMBAR (FP)
70823membar #StoreLoad
70824
70825P6766: !_ST_BINIT [5] (maybe <- 0x3000122) (Int)
70826wr %g0, 0xe2, %asi
70827stwa %l4, [%i1 + 12] %asi
70828add %l4, 1, %l4
70829
70830P6767: !_MEMBAR (Int) (Branch target of P6737)
70831membar #StoreLoad
70832ba P6768
70833nop
70834
70835TARGET6737:
70836ba RET6737
70837nop
70838
70839
70840P6768: !_REPLACEMENT [6] (Int)
70841sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
70842sub %i0, %i3, %i3
70843sethi %hi(0x20000), %l3
70844ld [%i3+0], %l7
70845st %l7, [%i3+0]
70846add %i3, %l3, %l6
70847ld [%l6+0], %l7
70848st %l7, [%l6+0]
70849add %l6, %l3, %l6
70850ld [%l6+0], %l7
70851st %l7, [%l6+0]
70852add %l6, %l3, %l6
70853ld [%l6+0], %l7
70854st %l7, [%l6+0]
70855add %l6, %l3, %l6
70856ld [%l6+0], %l7
70857st %l7, [%l6+0]
70858add %l6, %l3, %l6
70859ld [%l6+0], %l7
70860st %l7, [%l6+0]
70861add %l6, %l3, %l6
70862ld [%l6+0], %l7
70863st %l7, [%l6+0]
70864add %l6, %l3, %l6
70865ld [%l6+0], %l7
70866st %l7, [%l6+0]
70867
70868P6769: !_ST_BINIT [19] (maybe <- 0x3000123) (Int)
70869wr %g0, 0xe2, %asi
70870sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
70871sub %i0, %i2, %i2
70872stwa %l4, [%i2 + 4] %asi
70873add %l4, 1, %l4
70874
70875P6770: !_MEMBAR (Int)
70876membar #StoreLoad
70877
70878P6771: !_LDD [11] (Int)
70879sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
70880sub %i0, %i3, %i3
70881ldd [%i3 + 8], %l6
70882! move %l7(lower) -> %o4(upper)
70883sllx %l7, 32, %o4
70884
70885P6772: !_MEMBAR (FP)
70886membar #StoreLoad
70887
70888P6773: !_BLD [5] (FP)
70889wr %g0, 0xf0, %asi
70890ldda [%i1 + 0] %asi, %f32
70891membar #Sync
70892! 3 addresses covered
70893fmovd %f32, %f12
70894fmovd %f34, %f18
70895fmovs %f19, %f14
70896
70897P6774: !_MEMBAR (FP)
70898
70899P6775: !_CAS [6] (maybe <- 0x3000124) (Int)
70900sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
70901sub %i0, %i2, %i2
70902lduw [%i2], %o5
70903mov %o5, %l3
70904! move %l3(lower) -> %o4(lower)
70905or %l3, %o4, %o4
70906!---- flushing int results buffer----
70907mov %o0, %l5
70908mov %o1, %l5
70909mov %o2, %l5
70910mov %o3, %l5
70911mov %o4, %l5
70912mov %l4, %o0
70913cas [%i2], %l3, %o0
70914! move %o0(lower) -> %o0(upper)
70915sllx %o0, 32, %o0
70916add %l4, 1, %l4
70917
70918P6776: !_DWLD [8] (Int)
70919ldx [%i2 + 8], %l6
70920! move %l6(lower) -> %o0(lower)
70921srl %l6, 0, %l3
70922or %l3, %o0, %o0
70923
70924P6777: !_ST [6] (maybe <- 0x3000125) (Int)
70925stw %l4, [%i2 + 0 ]
70926add %l4, 1, %l4
70927
70928P6778: !_MEMBAR (FP)
70929membar #StoreLoad
70930
70931P6779: !_BLD [9] (FP)
70932wr %g0, 0xf0, %asi
70933ldda [%i3 + 0] %asi, %f32
70934membar #Sync
70935! 3 addresses covered
70936fmovd %f32, %f18
70937fmovs %f18, %f15
70938!---- flushing fp results buffer to %f30 ----
70939fmovd %f0, %f30
70940fmovd %f2, %f30
70941fmovd %f4, %f30
70942fmovd %f6, %f30
70943fmovd %f8, %f30
70944fmovd %f10, %f30
70945fmovd %f12, %f30
70946fmovd %f14, %f30
70947!--
70948fmovs %f19, %f0
70949fmovd %f34, %f18
70950fmovs %f19, %f1
70951
70952P6780: !_MEMBAR (FP)
70953
70954P6781: !_LDD [2] (Int)
70955ldd [%i0 + 8], %l6
70956! move %l7(lower) -> %o1(upper)
70957sllx %l7, 32, %o1
70958
70959P6782: !_MEMBAR (FP)
70960
70961P6783: !_BSTC [8] (maybe <- 0x428000dc) (FP)
70962wr %g0, 0xe0, %asi
70963! preparing store val #0, next val will be in f32
70964fmovs %f16, %f20
70965fadds %f16, %f17, %f16
70966! preparing store val #1, next val will be in f33
70967fmovs %f16, %f21
70968fadds %f16, %f17, %f16
70969! preparing store val #2, next val will be in f35
70970fmovd %f20, %f32
70971fmovs %f16, %f21
70972fadds %f16, %f17, %f16
70973fmovd %f20, %f34
70974membar #Sync
70975stda %f32, [%i2 + 0 ] %asi
70976
70977P6784: !_MEMBAR (FP) (Branch target of P6228)
70978membar #StoreLoad
70979ba P6785
70980nop
70981
70982TARGET6228:
70983ba RET6228
70984nop
70985
70986
70987P6785: !_REPLACEMENT [20] (Int)
70988sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
70989sub %i0, %i3, %i3
70990sethi %hi(0x20000), %l3
70991ld [%i3+12], %l7
70992st %l7, [%i3+12]
70993add %i3, %l3, %l6
70994ld [%l6+12], %l7
70995st %l7, [%l6+12]
70996add %l6, %l3, %l6
70997ld [%l6+12], %l7
70998st %l7, [%l6+12]
70999add %l6, %l3, %l6
71000ld [%l6+12], %l7
71001st %l7, [%l6+12]
71002add %l6, %l3, %l6
71003ld [%l6+12], %l7
71004st %l7, [%l6+12]
71005add %l6, %l3, %l6
71006ld [%l6+12], %l7
71007st %l7, [%l6+12]
71008add %l6, %l3, %l6
71009ld [%l6+12], %l7
71010st %l7, [%l6+12]
71011add %l6, %l3, %l6
71012ld [%l6+12], %l7
71013st %l7, [%l6+12]
71014
71015P6786: !_SWAP [17] (maybe <- 0x3000126) (Int)
71016sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
71017add %i0, %i2, %i2
71018mov %l4, %l6
71019swap [%i2 + 12], %l6
71020! move %l6(lower) -> %o1(lower)
71021srl %l6, 0, %o5
71022or %o5, %o1, %o1
71023add %l4, 1, %l4
71024
71025P6787: !_LD [3] (Int) (LE)
71026wr %g0, 0x88, %asi
71027lduwa [%i1 + 0] %asi, %o2
71028! move %o2(lower) -> %o2(upper)
71029sllx %o2, 32, %o2
71030
71031P6788: !_CAS [17] (maybe <- 0x3000127) (Int)
71032add %i2, 12, %l6
71033lduw [%l6], %o5
71034mov %o5, %l3
71035! move %l3(lower) -> %o2(lower)
71036or %l3, %o2, %o2
71037mov %l4, %o3
71038cas [%l6], %l3, %o3
71039! move %o3(lower) -> %o3(upper)
71040sllx %o3, 32, %o3
71041add %l4, 1, %l4
71042
71043P6789: !_MEMBAR (FP)
71044membar #StoreLoad
71045
71046P6790: !_BLD [20] (FP)
71047wr %g0, 0xf0, %asi
71048sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
71049sub %i0, %i3, %i3
71050ldda [%i3 + 0] %asi, %f32
71051membar #Sync
71052! 3 addresses covered
71053fmovd %f32, %f2
71054fmovd %f34, %f18
71055fmovs %f19, %f4
71056
71057P6791: !_MEMBAR (FP) (CBR)
71058
71059! cbranch
71060andcc %l0, 1, %g0
71061be,pt %xcc, TARGET6791
71062nop
71063RET6791:
71064
71065! lfsr step begin
71066srlx %l0, 1, %l3
71067xnor %l3, %l0, %l3
71068sllx %l3, 63, %l3
71069or %l3, %l0, %l0
71070srlx %l0, 1, %l0
71071
71072
71073P6792: !_BLD [8] (FP)
71074wr %g0, 0xf0, %asi
71075sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
71076sub %i0, %i2, %i2
71077ldda [%i2 + 0] %asi, %f32
71078membar #Sync
71079! 3 addresses covered
71080fmovd %f32, %f18
71081fmovs %f18, %f5
71082fmovs %f19, %f6
71083fmovd %f34, %f18
71084fmovs %f19, %f7
71085
71086P6793: !_MEMBAR (FP)
71087
71088P6794: !_BST [7] (maybe <- 0x428000df) (FP)
71089wr %g0, 0xf0, %asi
71090! preparing store val #0, next val will be in f32
71091fmovs %f16, %f20
71092fadds %f16, %f17, %f16
71093! preparing store val #1, next val will be in f33
71094fmovs %f16, %f21
71095fadds %f16, %f17, %f16
71096! preparing store val #2, next val will be in f35
71097fmovd %f20, %f32
71098fmovs %f16, %f21
71099fadds %f16, %f17, %f16
71100fmovd %f20, %f34
71101membar #Sync
71102stda %f32, [%i2 + 0 ] %asi
71103
71104P6795: !_MEMBAR (FP)
71105membar #StoreLoad
71106
71107P6796: !_LD [8] (Int)
71108lduw [%i2 + 12], %l6
71109! move %l6(lower) -> %o3(lower)
71110or %l6, %o3, %o3
71111
71112P6797: !_MEMBAR (FP)
71113
71114P6798: !_BSTC [18] (maybe <- 0x428000e2) (FP)
71115wr %g0, 0xe0, %asi
71116! preparing store val #0, next val will be in f32
71117fmovs %f16, %f20
71118fadds %f16, %f17, %f16
71119! preparing store val #1, next val will be in f33
71120fmovs %f16, %f21
71121fadds %f16, %f17, %f16
71122! preparing store val #2, next val will be in f35
71123fmovd %f20, %f32
71124fmovs %f16, %f21
71125fadds %f16, %f17, %f16
71126fmovd %f20, %f34
71127membar #Sync
71128stda %f32, [%i3 + 0 ] %asi
71129
71130P6799: !_MEMBAR (FP)
71131membar #StoreLoad
71132
71133P6800: !_DWLD [17] (Int)
71134sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
71135add %i0, %i3, %i3
71136ldx [%i3 + 8], %o4
71137! move %o4(lower) -> %o4(upper)
71138sllx %o4, 32, %o4
71139
71140P6801: !_DWLD [13] (FP)
71141sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
71142sub %i0, %i2, %i2
71143ldd [%i2 + 0], %f8
71144! 2 addresses covered
71145
71146P6802: !_PREFETCH [11] (Int)
71147sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
71148sub %i0, %i3, %i3
71149prefetch [%i3 + 12], 23
71150
71151P6803: !_PREFETCH [6] (Int)
71152sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
71153sub %i0, %i2, %i2
71154prefetch [%i2 + 0], 21
71155
71156P6804: !_DWST_BINIT [18] (maybe <- 0x3000128) (Int)
71157wr %g0, 0xe2, %asi
71158sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
71159sub %i0, %i3, %i3
71160sllx %l4, 32, %o5
71161add %l4, 1, %l4
71162or %o5, %l4, %o5
71163stxa %o5, [%i3 + 0] %asi
71164add %l4, 1, %l4
71165
71166P6805: !_MEMBAR (Int)
71167membar #StoreLoad
71168
71169P6806: !_ST_BINIT [17] (maybe <- 0x300012a) (Int)
71170wr %g0, 0xe2, %asi
71171sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
71172add %i0, %i2, %i2
71173stwa %l4, [%i2 + 12] %asi
71174add %l4, 1, %l4
71175
71176P6807: !_MEMBAR (Int)
71177membar #StoreLoad
71178
71179P6808: !_DWST [17] (maybe <- 0x300012b) (Int) (Branch target of P6664)
71180mov %l4, %l6
71181stx %l6, [%i2 + 8]
71182add %l4, 1, %l4
71183ba P6809
71184nop
71185
71186TARGET6664:
71187ba RET6664
71188nop
71189
71190
71191P6809: !_LD [17] (Int)
71192lduw [%i2 + 12], %l6
71193! move %l6(lower) -> %o4(lower)
71194or %l6, %o4, %o4
71195!---- flushing int results buffer----
71196mov %o0, %l5
71197mov %o1, %l5
71198mov %o2, %l5
71199mov %o3, %l5
71200mov %o4, %l5
71201
71202P6810: !_DWST_BINIT [5] (maybe <- 0x300012c) (Int)
71203wr %g0, 0xe2, %asi
71204mov %l4, %l7
71205stxa %l7, [%i1 + 8] %asi
71206add %l4, 1, %l4
71207
71208P6811: !_MEMBAR (Int)
71209membar #StoreLoad
71210
71211P6812: !_CAS [17] (maybe <- 0x300012d) (Int) (CBR)
71212add %i2, 12, %l7
71213lduw [%l7], %o0
71214mov %o0, %l6
71215! move %l6(lower) -> %o0(upper)
71216sllx %l6, 32, %o0
71217mov %l4, %l3
71218cas [%l7], %l6, %l3
71219! move %l3(lower) -> %o0(lower)
71220srl %l3, 0, %l6
71221or %l6, %o0, %o0
71222add %l4, 1, %l4
71223
71224! cbranch
71225andcc %l0, 1, %g0
71226be,pn %xcc, TARGET6812
71227nop
71228RET6812:
71229
71230! lfsr step begin
71231srlx %l0, 1, %l6
71232xnor %l6, %l0, %l6
71233sllx %l6, 63, %l6
71234or %l6, %l0, %l0
71235srlx %l0, 1, %l0
71236
71237
71238P6813: !_DWST_BINIT [1] (maybe <- 0x300012e) (Int)
71239wr %g0, 0xe2, %asi
71240sllx %l4, 32, %l7
71241add %l4, 1, %l4
71242or %l7, %l4, %l7
71243stxa %l7, [%i0 + 0] %asi
71244add %l4, 1, %l4
71245
71246P6814: !_MEMBAR (Int)
71247membar #StoreLoad
71248
71249P6815: !_BLD [13] (FP)
71250wr %g0, 0xf0, %asi
71251sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
71252sub %i0, %i3, %i3
71253ldda [%i3 + 0] %asi, %f32
71254membar #Sync
71255! 3 addresses covered
71256fmovd %f32, %f10
71257fmovd %f34, %f18
71258fmovs %f19, %f12
71259
71260P6816: !_MEMBAR (FP) (Branch target of P6641)
71261ba P6817
71262nop
71263
71264TARGET6641:
71265ba RET6641
71266nop
71267
71268
71269P6817: !_DWLD [17] (Int)
71270ldx [%i2 + 8], %o1
71271! move %o1(lower) -> %o1(upper)
71272sllx %o1, 32, %o1
71273
71274P6818: !_DWST [11] (maybe <- 0x3000130) (Int)
71275sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
71276sub %i0, %i2, %i2
71277mov %l4, %o5
71278stx %o5, [%i2 + 8]
71279add %l4, 1, %l4
71280
71281P6819: !_SWAP [21] (maybe <- 0x3000131) (Int)
71282sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
71283sub %i0, %i3, %i3
71284mov %l4, %l3
71285swap [%i3 + 0], %l3
71286! move %l3(lower) -> %o1(lower)
71287srl %l3, 0, %l7
71288or %l7, %o1, %o1
71289add %l4, 1, %l4
71290
71291P6820: !_DWST [9] (maybe <- 0x3000132) (Int)
71292sllx %l4, 32, %l6
71293add %l4, 1, %l4
71294or %l6, %l4, %l6
71295stx %l6, [%i2 + 0]
71296add %l4, 1, %l4
71297
71298P6821: !_LDD [11] (Int)
71299ldd [%i2 + 8], %l6
71300! move %l7(lower) -> %o2(upper)
71301sllx %l7, 32, %o2
71302
71303P6822: !_CAS [1] (maybe <- 0x3000134) (Int) (Branch target of P6881)
71304add %i0, 4, %l6
71305lduw [%l6], %o5
71306mov %o5, %l3
71307! move %l3(lower) -> %o2(lower)
71308or %l3, %o2, %o2
71309mov %l4, %o3
71310cas [%l6], %l3, %o3
71311! move %o3(lower) -> %o3(upper)
71312sllx %o3, 32, %o3
71313add %l4, 1, %l4
71314ba P6823
71315nop
71316
71317TARGET6881:
71318ba RET6881
71319nop
71320
71321
71322P6823: !_SWAP [4] (maybe <- 0x3000135) (Int)
71323mov %l4, %l7
71324swap [%i1 + 4], %l7
71325! move %l7(lower) -> %o3(lower)
71326srl %l7, 0, %l3
71327or %l3, %o3, %o3
71328add %l4, 1, %l4
71329
71330P6824: !_LD [22] (Int)
71331lduw [%i3 + 4], %o4
71332! move %o4(lower) -> %o4(upper)
71333sllx %o4, 32, %o4
71334
71335P6825: !_CASX [1] (maybe <- 0x3000136) (Int)
71336ldx [%i0], %l3
71337! move %l3(upper) -> %o4(lower)
71338srlx %l3, 32, %l6
71339or %l6, %o4, %o4
71340!---- flushing int results buffer----
71341mov %o0, %l5
71342mov %o1, %l5
71343mov %o2, %l5
71344mov %o3, %l5
71345mov %o4, %l5
71346! move %l3(lower) -> %o0(upper)
71347sllx %l3, 32, %o0
71348mov %l3, %l6
71349sllx %l4, 32, %l3
71350add %l4, 1, %l4
71351or %l4, %l3, %l3
71352casx [%i0], %l6, %l3
71353! move %l3(upper) -> %o0(lower)
71354srlx %l3, 32, %l6
71355or %l6, %o0, %o0
71356! move %l3(lower) -> %o1(upper)
71357sllx %l3, 32, %o1
71358add %l4, 1, %l4
71359
71360P6826: !_DWLD [8] (Int)
71361sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
71362sub %i0, %i2, %i2
71363ldx [%i2 + 8], %l7
71364! move %l7(lower) -> %o1(lower)
71365srl %l7, 0, %l6
71366or %l6, %o1, %o1
71367
71368P6827: !_CASX [0] (maybe <- 0x3000138) (Int) (LE)
71369sllx %l4, 32, %l3
71370add %l4, 1, %l4
71371or %l4, %l3, %l3
71372! Change double-word-level endianess (big endian <-> little endian)
71373sethi %hi(0xff00ff00), %o5
71374or %o5, %lo(0xff00ff00), %o5
71375sllx %o5, 32, %l6
71376or %o5, %l6, %o5
71377and %l3, %o5, %l6
71378srlx %l6, 8, %l6
71379sllx %l3, 8, %l3
71380and %l3, %o5, %l3
71381or %l3, %l6, %l3
71382sethi %hi(0xffff0000), %o5
71383srlx %l3, 16, %l6
71384andn %l6, %o5, %l6
71385andn %l3, %o5, %l3
71386sllx %l3, 16, %l3
71387or %l3, %l6, %l3
71388srlx %l3, 32, %l6
71389sllx %l3, 32, %l3
71390or %l3, %l6, %l6
71391wr %g0, 0x88, %asi
71392ldxa [%i0] %asi, %l7
71393! move %l7(lower) -> %o2(upper)
71394sllx %l7, 32, %o2
71395! move %l7(upper) -> %o2(lower)
71396srlx %l7, 32, %o5
71397or %o5, %o2, %o2
71398mov %l7, %o5
71399mov %l6, %l7
71400casxa [%i0] %asi, %o5, %l7
71401! move %l7(lower) -> %o3(upper)
71402sllx %l7, 32, %o3
71403! move %l7(upper) -> %o3(lower)
71404srlx %l7, 32, %o5
71405or %o5, %o3, %o3
71406add %l4, 1, %l4
71407
71408P6828: !_SWAP [0] (maybe <- 0x300013a) (Int) (Branch target of P6985)
71409mov %l4, %o4
71410swap [%i0 + 0], %o4
71411! move %o4(lower) -> %o4(upper)
71412sllx %o4, 32, %o4
71413add %l4, 1, %l4
71414ba P6829
71415nop
71416
71417TARGET6985:
71418ba RET6985
71419nop
71420
71421
71422P6829: !_LDD [15] (Int) (LE)
71423wr %g0, 0x88, %asi
71424sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
71425add %i0, %i3, %i3
71426ldda [%i3 + 0] %asi, %l6
71427! move %l6(lower) -> %o4(lower)
71428or %l6, %o4, %o4
71429!---- flushing int results buffer----
71430mov %o0, %l5
71431mov %o1, %l5
71432mov %o2, %l5
71433mov %o3, %l5
71434mov %o4, %l5
71435! move %l7(lower) -> %o0(upper)
71436sllx %l7, 32, %o0
71437
71438P6830: !_LD [0] (Int)
71439lduw [%i0 + 0], %l6
71440! move %l6(lower) -> %o0(lower)
71441or %l6, %o0, %o0
71442
71443P6831: !_ST [17] (maybe <- 0x300013b) (Int)
71444stw %l4, [%i3 + 12 ]
71445add %l4, 1, %l4
71446
71447P6832: !_ST [1] (maybe <- 0x300013c) (Int)
71448stw %l4, [%i0 + 4 ]
71449add %l4, 1, %l4
71450
71451P6833: !_DWLD [1] (FP)
71452ldd [%i0 + 0], %f18
71453! 2 addresses covered
71454fmovs %f18, %f13
71455fmovs %f19, %f14
71456
71457P6834: !_ST_BINIT [15] (maybe <- 0x300013d) (Int) (LE)
71458wr %g0, 0xea, %asi
71459! Change single-word-level endianess (big endian <-> little endian)
71460sethi %hi(0xff00ff00), %l6
71461or %l6, %lo(0xff00ff00), %l6
71462and %l4, %l6, %l7
71463srl %l7, 8, %l7
71464sll %l4, 8, %l3
71465and %l3, %l6, %l3
71466or %l3, %l7, %l3
71467srl %l3, 16, %l7
71468sll %l3, 16, %l3
71469srl %l3, 0, %l3
71470or %l3, %l7, %l3
71471stwa %l3, [%i3 + 0] %asi
71472add %l4, 1, %l4
71473
71474P6835: !_MEMBAR (Int) (LE) (Branch target of P6596)
71475membar #StoreLoad
71476ba P6836
71477nop
71478
71479TARGET6596:
71480ba RET6596
71481nop
71482
71483
71484P6836: !_CASX [10] (maybe <- 0x300013e) (Int)
71485sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
71486sub %i0, %i2, %i2
71487ldx [%i2], %o1
71488! move %o1(upper) -> %o1(upper)
71489! move %o1(lower) -> %o1(lower)
71490mov %o1, %o5
71491sllx %l4, 32, %o2
71492add %l4, 1, %l4
71493or %l4, %o2, %o2
71494casx [%i2], %o5, %o2
71495! move %o2(upper) -> %o2(upper)
71496! move %o2(lower) -> %o2(lower)
71497add %l4, 1, %l4
71498
71499P6837: !_MEMBAR (FP)
71500
71501P6838: !_BSTC [5] (maybe <- 0x428000e5) (FP) (CBR)
71502wr %g0, 0xe0, %asi
71503! preparing store val #0, next val will be in f32
71504fmovs %f16, %f20
71505fadds %f16, %f17, %f16
71506! preparing store val #1, next val will be in f33
71507fmovs %f16, %f21
71508fadds %f16, %f17, %f16
71509! preparing store val #2, next val will be in f35
71510fmovd %f20, %f32
71511fmovs %f16, %f21
71512fadds %f16, %f17, %f16
71513fmovd %f20, %f34
71514membar #Sync
71515stda %f32, [%i1 + 0 ] %asi
71516
71517! cbranch
71518andcc %l0, 1, %g0
71519be,pt %xcc, TARGET6838
71520nop
71521RET6838:
71522
71523! lfsr step begin
71524srlx %l0, 1, %l7
71525xnor %l7, %l0, %l7
71526sllx %l7, 63, %l7
71527or %l7, %l0, %l0
71528srlx %l0, 1, %l0
71529
71530
71531P6839: !_MEMBAR (FP) (Branch target of P6050)
71532membar #StoreLoad
71533ba P6840
71534nop
71535
71536TARGET6050:
71537ba RET6050
71538nop
71539
71540
71541P6840: !_LD [8] (Int) (LE) (Branch target of P6960)
71542wr %g0, 0x88, %asi
71543sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i3
71544sub %i0, %i3, %i3
71545lduwa [%i3 + 12] %asi, %o3
71546! move %o3(lower) -> %o3(upper)
71547sllx %o3, 32, %o3
71548ba P6841
71549nop
71550
71551TARGET6960:
71552ba RET6960
71553nop
71554
71555
71556P6841: !_MEMBAR (FP)
71557
71558P6842: !_BSTC [22] (maybe <- 0x428000e8) (FP)
71559wr %g0, 0xe0, %asi
71560sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
71561sub %i0, %i2, %i2
71562! preparing store val #0, next val will be in f32
71563fmovs %f16, %f20
71564fadds %f16, %f17, %f16
71565! preparing store val #1, next val will be in f33
71566fmovs %f16, %f21
71567fadds %f16, %f17, %f16
71568! preparing store val #2, next val will be in f35
71569fmovd %f20, %f32
71570fmovs %f16, %f21
71571fadds %f16, %f17, %f16
71572fmovd %f20, %f34
71573membar #Sync
71574stda %f32, [%i2 + 0 ] %asi
71575
71576P6843: !_MEMBAR (FP)
71577membar #StoreLoad
71578
71579P6844: !_PREFETCH [9] (Int)
71580sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
71581sub %i0, %i3, %i3
71582prefetch [%i3 + 0], 0
71583
71584P6845: !_DWLD [8] (Int)
71585sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS1_O), %i2
71586sub %i0, %i2, %i2
71587ldx [%i2 + 8], %l6
71588! move %l6(lower) -> %o3(lower)
71589srl %l6, 0, %l3
71590or %l3, %o3, %o3
71591
71592P6846: !_ST [8] (maybe <- 0x3000140) (Int)
71593sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
71594sub %i0, %i3, %i3
71595stw %l4, [%i3 + 12 ]
71596add %l4, 1, %l4
71597
71598P6847: !_MEMBAR (FP)
71599
71600P6848: !_BSTC [2] (maybe <- 0x428000eb) (FP) (CBR)
71601wr %g0, 0xe0, %asi
71602! preparing store val #0, next val will be in f32
71603fmovs %f16, %f20
71604fadds %f16, %f17, %f16
71605! preparing store val #1, next val will be in f33
71606fmovs %f16, %f21
71607fadds %f16, %f17, %f16
71608! preparing store val #2, next val will be in f35
71609fmovd %f20, %f32
71610fmovs %f16, %f21
71611fadds %f16, %f17, %f16
71612fmovd %f20, %f34
71613membar #Sync
71614stda %f32, [%i0 + 0 ] %asi
71615
71616! cbranch
71617andcc %l0, 1, %g0
71618be,pn %xcc, TARGET6848
71619nop
71620RET6848:
71621
71622! lfsr step begin
71623srlx %l0, 1, %l6
71624xnor %l6, %l0, %l6
71625sllx %l6, 63, %l6
71626or %l6, %l0, %l0
71627srlx %l0, 1, %l0
71628
71629
71630P6849: !_MEMBAR (FP)
71631membar #StoreLoad
71632
71633P6850: !_CAS [19] (maybe <- 0x3000141) (Int)
71634sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
71635sub %i0, %i2, %i2
71636add %i2, 4, %o5
71637lduw [%o5], %o4
71638mov %o4, %l7
71639! move %l7(lower) -> %o4(upper)
71640sllx %l7, 32, %o4
71641mov %l4, %l6
71642cas [%o5], %l7, %l6
71643! move %l6(lower) -> %o4(lower)
71644srl %l6, 0, %l7
71645or %l7, %o4, %o4
71646!---- flushing int results buffer----
71647mov %o0, %l5
71648mov %o1, %l5
71649mov %o2, %l5
71650mov %o3, %l5
71651mov %o4, %l5
71652add %l4, 1, %l4
71653
71654P6851: !_DWST_BINIT [1] (maybe <- 0x3000142) (Int)
71655wr %g0, 0xe2, %asi
71656sllx %l4, 32, %l7
71657add %l4, 1, %l4
71658or %l7, %l4, %l7
71659stxa %l7, [%i0 + 0] %asi
71660add %l4, 1, %l4
71661
71662P6852: !_MEMBAR (Int)
71663membar #StoreLoad
71664
71665P6853: !_PREFETCH [14] (Int)
71666sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
71667sub %i0, %i3, %i3
71668prefetch [%i3 + 12], 17
71669
71670P6854: !_PREFETCH [22] (Int)
71671sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
71672sub %i0, %i2, %i2
71673prefetch [%i2 + 4], 0
71674
71675P6855: !_MEMBAR (FP)
71676
71677P6856: !_BSTC [14] (maybe <- 0x428000ee) (FP)
71678wr %g0, 0xe0, %asi
71679! preparing store val #0, next val will be in f32
71680fmovs %f16, %f20
71681fadds %f16, %f17, %f16
71682! preparing store val #1, next val will be in f33
71683fmovs %f16, %f21
71684fadds %f16, %f17, %f16
71685! preparing store val #2, next val will be in f35
71686fmovd %f20, %f32
71687fmovs %f16, %f21
71688fadds %f16, %f17, %f16
71689fmovd %f20, %f34
71690membar #Sync
71691stda %f32, [%i3 + 0 ] %asi
71692
71693P6857: !_MEMBAR (FP)
71694membar #StoreLoad
71695
71696P6858: !_DWST [2] (maybe <- 0x3000144) (Int) (CBR)
71697mov %l4, %l3
71698stx %l3, [%i0 + 8]
71699add %l4, 1, %l4
71700
71701! cbranch
71702andcc %l0, 1, %g0
71703be,pn %xcc, TARGET6858
71704nop
71705RET6858:
71706
71707! lfsr step begin
71708srlx %l0, 1, %o5
71709xnor %o5, %l0, %o5
71710sllx %o5, 63, %o5
71711or %o5, %l0, %l0
71712srlx %l0, 1, %l0
71713
71714
71715P6859: !_ST [18] (maybe <- 0x3000145) (Int)
71716sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
71717sub %i0, %i3, %i3
71718stw %l4, [%i3 + 0 ]
71719add %l4, 1, %l4
71720
71721P6860: !_ST_BINIT [9] (maybe <- 0x3000146) (Int)
71722wr %g0, 0xe2, %asi
71723sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
71724sub %i0, %i2, %i2
71725stwa %l4, [%i2 + 0] %asi
71726add %l4, 1, %l4
71727
71728P6861: !_MEMBAR (Int)
71729membar #StoreLoad
71730
71731P6862: !_DWST [21] (maybe <- 0x3000147) (Int)
71732sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
71733sub %i0, %i3, %i3
71734sllx %l4, 32, %l7
71735add %l4, 1, %l4
71736or %l7, %l4, %l7
71737stx %l7, [%i3 + 0]
71738add %l4, 1, %l4
71739
71740P6863: !_DWST [8] (maybe <- 0x3000149) (Int)
71741sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
71742sub %i0, %i2, %i2
71743mov %l4, %l6
71744stx %l6, [%i2 + 8]
71745add %l4, 1, %l4
71746
71747P6864: !_CASX [10] (maybe <- 0x300014a) (Int)
71748sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
71749sub %i0, %i3, %i3
71750ldx [%i3], %o0
71751! move %o0(upper) -> %o0(upper)
71752! move %o0(lower) -> %o0(lower)
71753mov %o0, %l3
71754sllx %l4, 32, %o1
71755add %l4, 1, %l4
71756or %l4, %o1, %o1
71757casx [%i3], %l3, %o1
71758! move %o1(upper) -> %o1(upper)
71759! move %o1(lower) -> %o1(lower)
71760add %l4, 1, %l4
71761
71762P6865: !_CASX [11] (maybe <- 0x300014c) (Int)
71763add %i3, 8, %l6
71764ldx [%l6], %o2
71765! move %o2(upper) -> %o2(upper)
71766! move %o2(lower) -> %o2(lower)
71767mov %o2, %l3
71768mov %l4, %o3
71769casx [%l6], %l3, %o3
71770! move %o3(upper) -> %o3(upper)
71771! move %o3(lower) -> %o3(lower)
71772add %l4, 1, %l4
71773
71774P6866: !_SWAP [2] (maybe <- 0x300014d) (Int)
71775mov %l4, %o4
71776swap [%i0 + 12], %o4
71777! move %o4(lower) -> %o4(upper)
71778sllx %o4, 32, %o4
71779add %l4, 1, %l4
71780
71781P6867: !_CASX [23] (maybe <- 0x300014e) (Int) (CBR)
71782sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
71783sub %i0, %i2, %i2
71784add %i2, 8, %l3
71785ldx [%l3], %l7
71786! move %l7(upper) -> %o4(lower)
71787srlx %l7, 32, %o5
71788or %o5, %o4, %o4
71789!---- flushing int results buffer----
71790mov %o0, %l5
71791mov %o1, %l5
71792mov %o2, %l5
71793mov %o3, %l5
71794mov %o4, %l5
71795! move %l7(lower) -> %o0(upper)
71796sllx %l7, 32, %o0
71797mov %l7, %o5
71798mov %l4, %l7
71799casx [%l3], %o5, %l7
71800! move %l7(upper) -> %o0(lower)
71801srlx %l7, 32, %o5
71802or %o5, %o0, %o0
71803! move %l7(lower) -> %o1(upper)
71804sllx %l7, 32, %o1
71805add %l4, 1, %l4
71806
71807! cbranch
71808andcc %l0, 1, %g0
71809be,pt %xcc, TARGET6867
71810nop
71811RET6867:
71812
71813! lfsr step begin
71814srlx %l0, 1, %o5
71815xnor %o5, %l0, %o5
71816sllx %o5, 63, %o5
71817or %o5, %l0, %l0
71818srlx %l0, 1, %l0
71819
71820
71821P6868: !_SWAP [7] (maybe <- 0x300014f) (Int)
71822sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
71823sub %i0, %i3, %i3
71824mov %l4, %l7
71825swap [%i3 + 4], %l7
71826! move %l7(lower) -> %o1(lower)
71827srl %l7, 0, %l3
71828or %l3, %o1, %o1
71829add %l4, 1, %l4
71830
71831P6869: !_ST [15] (maybe <- 0x3000150) (Int)
71832sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
71833add %i0, %i2, %i2
71834stw %l4, [%i2 + 0 ]
71835add %l4, 1, %l4
71836
71837P6870: !_ST [13] (maybe <- 0x428000f1) (FP)
71838sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
71839sub %i0, %i3, %i3
71840! preparing store val #0, next val will be in f20
71841fmovs %f16, %f20
71842fadds %f16, %f17, %f16
71843st %f20, [%i3 + 4 ]
71844
71845P6871: !_DWST_BINIT [15] (maybe <- 0x3000151) (Int)
71846wr %g0, 0xe2, %asi
71847sllx %l4, 32, %l6
71848add %l4, 1, %l4
71849or %l6, %l4, %l6
71850stxa %l6, [%i2 + 0] %asi
71851add %l4, 1, %l4
71852
71853P6872: !_MEMBAR (Int)
71854membar #StoreLoad
71855
71856P6873: !_DWLD [12] (Int)
71857ldx [%i3 + 0], %o2
71858! move %o2(upper) -> %o2(upper)
71859! move %o2(lower) -> %o2(lower)
71860
71861P6874: !_SWAP [4] (maybe <- 0x3000153) (Int)
71862mov %l4, %o3
71863swap [%i1 + 4], %o3
71864! move %o3(lower) -> %o3(upper)
71865sllx %o3, 32, %o3
71866add %l4, 1, %l4
71867
71868P6875: !_CASX [17] (maybe <- 0x3000154) (Int)
71869add %i2, 8, %l7
71870ldx [%l7], %l3
71871! move %l3(upper) -> %o3(lower)
71872srlx %l3, 32, %l6
71873or %l6, %o3, %o3
71874! move %l3(lower) -> %o4(upper)
71875sllx %l3, 32, %o4
71876mov %l3, %l6
71877mov %l4, %l3
71878casx [%l7], %l6, %l3
71879! move %l3(upper) -> %o4(lower)
71880srlx %l3, 32, %l6
71881or %l6, %o4, %o4
71882!---- flushing int results buffer----
71883mov %o0, %l5
71884mov %o1, %l5
71885mov %o2, %l5
71886mov %o3, %l5
71887mov %o4, %l5
71888! move %l3(lower) -> %o0(upper)
71889sllx %l3, 32, %o0
71890add %l4, 1, %l4
71891
71892P6876: !_REPLACEMENT [18] (Int)
71893sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
71894add %i0, %i2, %i2
71895sethi %hi(0x20000), %l6
71896ld [%i2+0], %o5
71897st %o5, [%i2+0]
71898add %i2, %l6, %l7
71899ld [%l7+0], %o5
71900st %o5, [%l7+0]
71901add %l7, %l6, %l7
71902ld [%l7+0], %o5
71903st %o5, [%l7+0]
71904add %l7, %l6, %l7
71905ld [%l7+0], %o5
71906st %o5, [%l7+0]
71907add %l7, %l6, %l7
71908ld [%l7+0], %o5
71909st %o5, [%l7+0]
71910add %l7, %l6, %l7
71911ld [%l7+0], %o5
71912st %o5, [%l7+0]
71913add %l7, %l6, %l7
71914ld [%l7+0], %o5
71915st %o5, [%l7+0]
71916add %l7, %l6, %l7
71917ld [%l7+0], %o5
71918st %o5, [%l7+0]
71919
71920P6877: !_MEMBAR (FP)
71921
71922P6878: !_BST [19] (maybe <- 0x428000f2) (FP)
71923wr %g0, 0xf0, %asi
71924sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
71925sub %i0, %i3, %i3
71926! preparing store val #0, next val will be in f32
71927fmovs %f16, %f20
71928fadds %f16, %f17, %f16
71929! preparing store val #1, next val will be in f33
71930fmovs %f16, %f21
71931fadds %f16, %f17, %f16
71932! preparing store val #2, next val will be in f35
71933fmovd %f20, %f32
71934fmovs %f16, %f21
71935fadds %f16, %f17, %f16
71936fmovd %f20, %f34
71937membar #Sync
71938stda %f32, [%i3 + 0 ] %asi
71939
71940P6879: !_MEMBAR (FP)
71941
71942P6880: !_BSTC [22] (maybe <- 0x428000f5) (FP)
71943wr %g0, 0xe0, %asi
71944sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
71945sub %i0, %i2, %i2
71946! preparing store val #0, next val will be in f32
71947fmovs %f16, %f20
71948fadds %f16, %f17, %f16
71949! preparing store val #1, next val will be in f33
71950fmovs %f16, %f21
71951fadds %f16, %f17, %f16
71952! preparing store val #2, next val will be in f35
71953fmovd %f20, %f32
71954fmovs %f16, %f21
71955fadds %f16, %f17, %f16
71956fmovd %f20, %f34
71957membar #Sync
71958stda %f32, [%i2 + 0 ] %asi
71959
71960P6881: !_MEMBAR (FP) (CBR)
71961membar #StoreLoad
71962
71963! cbranch
71964andcc %l0, 1, %g0
71965be,pt %xcc, TARGET6881
71966nop
71967RET6881:
71968
71969! lfsr step begin
71970srlx %l0, 1, %l7
71971xnor %l7, %l0, %l7
71972sllx %l7, 63, %l7
71973or %l7, %l0, %l0
71974srlx %l0, 1, %l0
71975
71976
71977P6882: !_PREFETCH [0] (Int)
71978prefetch [%i0 + 0], 31
71979
71980P6883: !_DWST [16] (maybe <- 0x3000155) (Int)
71981sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
71982add %i0, %i3, %i3
71983sllx %l4, 32, %o5
71984add %l4, 1, %l4
71985or %o5, %l4, %o5
71986stx %o5, [%i3 + 0]
71987add %l4, 1, %l4
71988
71989P6884: !_ST [12] (maybe <- 0x3000157) (Int)
71990sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
71991sub %i0, %i2, %i2
71992stw %l4, [%i2 + 0 ]
71993add %l4, 1, %l4
71994
71995P6885: !_REPLACEMENT [10] (Int) (Branch target of P6925)
71996sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
71997add %i0, %i3, %i3
71998sethi %hi(0x20000), %l6
71999ld [%i3+4], %o5
72000st %o5, [%i3+4]
72001add %i3, %l6, %l7
72002ld [%l7+4], %o5
72003st %o5, [%l7+4]
72004add %l7, %l6, %l7
72005ld [%l7+4], %o5
72006st %o5, [%l7+4]
72007add %l7, %l6, %l7
72008ld [%l7+4], %o5
72009st %o5, [%l7+4]
72010add %l7, %l6, %l7
72011ld [%l7+4], %o5
72012st %o5, [%l7+4]
72013add %l7, %l6, %l7
72014ld [%l7+4], %o5
72015st %o5, [%l7+4]
72016add %l7, %l6, %l7
72017ld [%l7+4], %o5
72018st %o5, [%l7+4]
72019add %l7, %l6, %l7
72020ld [%l7+4], %o5
72021st %o5, [%l7+4]
72022ba P6886
72023nop
72024
72025TARGET6925:
72026ba RET6925
72027nop
72028
72029
72030P6886: !_MEMBAR (FP)
72031membar #StoreLoad
72032
72033P6887: !_BLD [23] (FP)
72034wr %g0, 0xf0, %asi
72035sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
72036sub %i0, %i2, %i2
72037ldda [%i2 + 0] %asi, %f32
72038membar #Sync
72039! 3 addresses covered
72040fmovd %f32, %f18
72041fmovs %f18, %f15
72042!---- flushing fp results buffer to %f30 ----
72043fmovd %f0, %f30
72044fmovd %f2, %f30
72045fmovd %f4, %f30
72046fmovd %f6, %f30
72047fmovd %f8, %f30
72048fmovd %f10, %f30
72049fmovd %f12, %f30
72050fmovd %f14, %f30
72051!--
72052fmovs %f19, %f0
72053fmovd %f34, %f18
72054fmovs %f19, %f1
72055
72056P6888: !_MEMBAR (FP) (CBR) (Branch target of P6701)
72057
72058! cbranch
72059andcc %l0, 1, %g0
72060be,pn %xcc, TARGET6888
72061nop
72062RET6888:
72063
72064! lfsr step begin
72065srlx %l0, 1, %l3
72066xnor %l3, %l0, %l3
72067sllx %l3, 63, %l3
72068or %l3, %l0, %l0
72069srlx %l0, 1, %l0
72070
72071ba P6889
72072nop
72073
72074TARGET6701:
72075ba RET6701
72076nop
72077
72078
72079P6889: !_DWST [21] (maybe <- 0x3000158) (Int)
72080sllx %l4, 32, %l6
72081add %l4, 1, %l4
72082or %l6, %l4, %l6
72083stx %l6, [%i2 + 0]
72084add %l4, 1, %l4
72085
72086P6890: !_DWLD [1] (Int)
72087ldx [%i0 + 0], %l6
72088! move %l6(upper) -> %o0(lower)
72089srlx %l6, 32, %l3
72090or %l3, %o0, %o0
72091! move %l6(lower) -> %o1(upper)
72092sllx %l6, 32, %o1
72093
72094P6891: !_ST [23] (maybe <- 0x300015a) (Int)
72095stw %l4, [%i2 + 12 ]
72096add %l4, 1, %l4
72097
72098P6892: !_MEMBAR (FP)
72099
72100P6893: !_BST [5] (maybe <- 0x428000f8) (FP)
72101wr %g0, 0xf0, %asi
72102! preparing store val #0, next val will be in f32
72103fmovs %f16, %f20
72104fadds %f16, %f17, %f16
72105! preparing store val #1, next val will be in f33
72106fmovs %f16, %f21
72107fadds %f16, %f17, %f16
72108! preparing store val #2, next val will be in f35
72109fmovd %f20, %f32
72110fmovs %f16, %f21
72111fadds %f16, %f17, %f16
72112fmovd %f20, %f34
72113membar #Sync
72114stda %f32, [%i1 + 0 ] %asi
72115
72116P6894: !_MEMBAR (FP) (Branch target of P6711)
72117membar #StoreLoad
72118ba P6895
72119nop
72120
72121TARGET6711:
72122ba RET6711
72123nop
72124
72125
72126P6895: !_CAS [8] (maybe <- 0x300015b) (Int) (Branch target of P6035)
72127sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
72128sub %i0, %i3, %i3
72129add %i3, 12, %l6
72130lduw [%l6], %o5
72131mov %o5, %l3
72132! move %l3(lower) -> %o1(lower)
72133or %l3, %o1, %o1
72134mov %l4, %o2
72135cas [%l6], %l3, %o2
72136! move %o2(lower) -> %o2(upper)
72137sllx %o2, 32, %o2
72138add %l4, 1, %l4
72139ba P6896
72140nop
72141
72142TARGET6035:
72143ba RET6035
72144nop
72145
72146
72147P6896: !_DWST_BINIT [6] (maybe <- 0x300015c) (Int)
72148wr %g0, 0xe2, %asi
72149sllx %l4, 32, %l3
72150add %l4, 1, %l4
72151or %l3, %l4, %l3
72152stxa %l3, [%i3 + 0] %asi
72153add %l4, 1, %l4
72154
72155P6897: !_MEMBAR (Int) (Branch target of P6189)
72156membar #StoreLoad
72157ba P6898
72158nop
72159
72160TARGET6189:
72161ba RET6189
72162nop
72163
72164
72165P6898: !_DWST_BINIT [13] (maybe <- 0x300015e) (Int)
72166wr %g0, 0xe2, %asi
72167sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
72168sub %i0, %i2, %i2
72169sllx %l4, 32, %o5
72170add %l4, 1, %l4
72171or %o5, %l4, %o5
72172stxa %o5, [%i2 + 0] %asi
72173add %l4, 1, %l4
72174
72175P6899: !_MEMBAR (Int)
72176membar #StoreLoad
72177
72178P6900: !_CAS [18] (maybe <- 0x3000160) (Int)
72179sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
72180sub %i0, %i3, %i3
72181lduw [%i3], %l6
72182mov %l6, %l7
72183! move %l7(lower) -> %o2(lower)
72184or %l7, %o2, %o2
72185mov %l4, %o3
72186cas [%i3], %l7, %o3
72187! move %o3(lower) -> %o3(upper)
72188sllx %o3, 32, %o3
72189add %l4, 1, %l4
72190
72191P6901: !_PREFETCH [7] (Int)
72192sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
72193sub %i0, %i2, %i2
72194prefetch [%i2 + 4], 21
72195
72196P6902: !_CAS [13] (maybe <- 0x3000161) (Int)
72197sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
72198sub %i0, %i3, %i3
72199add %i3, 4, %o5
72200lduw [%o5], %l6
72201mov %l6, %l7
72202! move %l7(lower) -> %o3(lower)
72203or %l7, %o3, %o3
72204mov %l4, %o4
72205cas [%o5], %l7, %o4
72206! move %o4(lower) -> %o4(upper)
72207sllx %o4, 32, %o4
72208add %l4, 1, %l4
72209
72210P6903: !_REPLACEMENT [0] (Int)
72211sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
72212add %i0, %i2, %i2
72213sethi %hi(0x20000), %l7
72214ld [%i2+0], %l3
72215st %l3, [%i2+0]
72216add %i2, %l7, %o5
72217ld [%o5+0], %l3
72218st %l3, [%o5+0]
72219add %o5, %l7, %o5
72220ld [%o5+0], %l3
72221st %l3, [%o5+0]
72222add %o5, %l7, %o5
72223ld [%o5+0], %l3
72224st %l3, [%o5+0]
72225add %o5, %l7, %o5
72226ld [%o5+0], %l3
72227st %l3, [%o5+0]
72228add %o5, %l7, %o5
72229ld [%o5+0], %l3
72230st %l3, [%o5+0]
72231add %o5, %l7, %o5
72232ld [%o5+0], %l3
72233st %l3, [%o5+0]
72234add %o5, %l7, %o5
72235ld [%o5+0], %l3
72236st %l3, [%o5+0]
72237
72238P6904: !_ST_BINIT [12] (maybe <- 0x3000162) (Int)
72239wr %g0, 0xe2, %asi
72240stwa %l4, [%i3 + 0] %asi
72241add %l4, 1, %l4
72242
72243P6905: !_MEMBAR (Int)
72244membar #StoreLoad
72245
72246P6906: !_LD [22] (FP)
72247sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
72248sub %i0, %i3, %i3
72249ld [%i3 + 4], %f2
72250! 1 addresses covered
72251
72252P6907: !_CASX [15] (maybe <- 0x3000163) (Int)
72253sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
72254add %i0, %i2, %i2
72255ldx [%i2], %o5
72256! move %o5(upper) -> %o4(lower)
72257srlx %o5, 32, %l3
72258or %l3, %o4, %o4
72259!---- flushing int results buffer----
72260mov %o0, %l5
72261mov %o1, %l5
72262mov %o2, %l5
72263mov %o3, %l5
72264mov %o4, %l5
72265! move %o5(lower) -> %o0(upper)
72266sllx %o5, 32, %o0
72267mov %o5, %l3
72268sllx %l4, 32, %o5
72269add %l4, 1, %l4
72270or %l4, %o5, %o5
72271casx [%i2], %l3, %o5
72272! move %o5(upper) -> %o0(lower)
72273srlx %o5, 32, %l3
72274or %l3, %o0, %o0
72275! move %o5(lower) -> %o1(upper)
72276sllx %o5, 32, %o1
72277add %l4, 1, %l4
72278
72279P6908: !_MEMBAR (FP)
72280
72281P6909: !_BST [16] (maybe <- 0x428000fb) (FP) (CBR)
72282wr %g0, 0xf0, %asi
72283! preparing store val #0, next val will be in f32
72284fmovs %f16, %f20
72285fadds %f16, %f17, %f16
72286! preparing store val #1, next val will be in f33
72287fmovs %f16, %f21
72288fadds %f16, %f17, %f16
72289! preparing store val #2, next val will be in f35
72290fmovd %f20, %f32
72291fmovs %f16, %f21
72292fadds %f16, %f17, %f16
72293fmovd %f20, %f34
72294membar #Sync
72295stda %f32, [%i2 + 0 ] %asi
72296
72297! cbranch
72298andcc %l0, 1, %g0
72299be,pt %xcc, TARGET6909
72300nop
72301RET6909:
72302
72303! lfsr step begin
72304srlx %l0, 1, %o5
72305xnor %o5, %l0, %o5
72306sllx %o5, 63, %o5
72307or %o5, %l0, %l0
72308srlx %l0, 1, %l0
72309
72310
72311P6910: !_MEMBAR (FP)
72312membar #StoreLoad
72313
72314P6911: !_ST [10] (maybe <- 0x3000165) (Int)
72315sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
72316sub %i0, %i3, %i3
72317stw %l4, [%i3 + 4 ]
72318add %l4, 1, %l4
72319
72320P6912: !_DWST_BINIT [21] (maybe <- 0x3000166) (Int)
72321wr %g0, 0xe2, %asi
72322sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
72323sub %i0, %i2, %i2
72324sllx %l4, 32, %l3
72325add %l4, 1, %l4
72326or %l3, %l4, %l3
72327stxa %l3, [%i2 + 0] %asi
72328add %l4, 1, %l4
72329
72330P6913: !_MEMBAR (Int) (CBR)
72331membar #StoreLoad
72332
72333! cbranch
72334andcc %l0, 1, %g0
72335be,pt %xcc, TARGET6913
72336nop
72337RET6913:
72338
72339! lfsr step begin
72340srlx %l0, 1, %o5
72341xnor %o5, %l0, %o5
72342sllx %o5, 63, %o5
72343or %o5, %l0, %l0
72344srlx %l0, 1, %l0
72345
72346
72347P6914: !_DWST_BINIT [9] (maybe <- 0x3000168) (Int)
72348wr %g0, 0xe2, %asi
72349sllx %l4, 32, %l3
72350add %l4, 1, %l4
72351or %l3, %l4, %l3
72352stxa %l3, [%i3 + 0] %asi
72353add %l4, 1, %l4
72354
72355P6915: !_MEMBAR (Int)
72356
72357P6916: !_BST [11] (maybe <- 0x428000fe) (FP)
72358wr %g0, 0xf0, %asi
72359! preparing store val #0, next val will be in f32
72360fmovs %f16, %f20
72361fadds %f16, %f17, %f16
72362! preparing store val #1, next val will be in f33
72363fmovs %f16, %f21
72364fadds %f16, %f17, %f16
72365! preparing store val #2, next val will be in f35
72366fmovd %f20, %f32
72367fmovs %f16, %f21
72368fadds %f16, %f17, %f16
72369fmovd %f20, %f34
72370membar #Sync
72371stda %f32, [%i3 + 0 ] %asi
72372
72373P6917: !_MEMBAR (FP)
72374membar #StoreLoad
72375
72376P6918: !_CASX [9] (maybe <- 0x300016a) (Int)
72377ldx [%i3], %l6
72378! move %l6(upper) -> %o1(lower)
72379srlx %l6, 32, %l7
72380or %l7, %o1, %o1
72381! move %l6(lower) -> %o2(upper)
72382sllx %l6, 32, %o2
72383mov %l6, %l7
72384sllx %l4, 32, %l6
72385add %l4, 1, %l4
72386or %l4, %l6, %l6
72387casx [%i3], %l7, %l6
72388! move %l6(upper) -> %o2(lower)
72389srlx %l6, 32, %l7
72390or %l7, %o2, %o2
72391! move %l6(lower) -> %o3(upper)
72392sllx %l6, 32, %o3
72393add %l4, 1, %l4
72394
72395P6919: !_MEMBAR (FP)
72396
72397P6920: !_BSTC [8] (maybe <- 0x42800101) (FP)
72398wr %g0, 0xe0, %asi
72399sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
72400sub %i0, %i3, %i3
72401! preparing store val #0, next val will be in f32
72402fmovs %f16, %f20
72403fadds %f16, %f17, %f16
72404! preparing store val #1, next val will be in f33
72405fmovs %f16, %f21
72406fadds %f16, %f17, %f16
72407! preparing store val #2, next val will be in f35
72408fmovd %f20, %f32
72409fmovs %f16, %f21
72410fadds %f16, %f17, %f16
72411fmovd %f20, %f34
72412membar #Sync
72413stda %f32, [%i3 + 0 ] %asi
72414
72415P6921: !_MEMBAR (FP)
72416membar #StoreLoad
72417
72418P6922: !_LDD [0] (Int)
72419ldd [%i0 + 0], %l6
72420! move %l6(lower) -> %o3(lower)
72421or %l6, %o3, %o3
72422! move %l7(lower) -> %o4(upper)
72423sllx %l7, 32, %o4
72424
72425P6923: !_MEMBAR (FP)
72426
72427P6924: !_BST [19] (maybe <- 0x42800104) (FP)
72428wr %g0, 0xf0, %asi
72429sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
72430sub %i0, %i2, %i2
72431! preparing store val #0, next val will be in f32
72432fmovs %f16, %f20
72433fadds %f16, %f17, %f16
72434! preparing store val #1, next val will be in f33
72435fmovs %f16, %f21
72436fadds %f16, %f17, %f16
72437! preparing store val #2, next val will be in f35
72438fmovd %f20, %f32
72439fmovs %f16, %f21
72440fadds %f16, %f17, %f16
72441fmovd %f20, %f34
72442membar #Sync
72443stda %f32, [%i2 + 0 ] %asi
72444
72445P6925: !_MEMBAR (FP) (CBR)
72446membar #StoreLoad
72447
72448! cbranch
72449andcc %l0, 1, %g0
72450be,pt %xcc, TARGET6925
72451nop
72452RET6925:
72453
72454! lfsr step begin
72455srlx %l0, 1, %o5
72456xnor %o5, %l0, %o5
72457sllx %o5, 63, %o5
72458or %o5, %l0, %l0
72459srlx %l0, 1, %l0
72460
72461
72462P6926: !_LDD [23] (Int)
72463sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
72464sub %i0, %i3, %i3
72465ldd [%i3 + 8], %l6
72466! move %l7(lower) -> %o4(lower)
72467or %l7, %o4, %o4
72468!---- flushing int results buffer----
72469mov %o0, %l5
72470mov %o1, %l5
72471mov %o2, %l5
72472mov %o3, %l5
72473mov %o4, %l5
72474
72475P6927: !_LDD [9] (Int)
72476sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
72477sub %i0, %i2, %i2
72478ldd [%i2 + 0], %l6
72479! move %l6(lower) -> %o0(upper)
72480sllx %l6, 32, %o0
72481! move %l7(lower) -> %o0(lower)
72482or %l7, %o0, %o0
72483
72484P6928: !_MEMBAR (FP)
72485
72486P6929: !_BST [5] (maybe <- 0x42800107) (FP)
72487wr %g0, 0xf0, %asi
72488! preparing store val #0, next val will be in f32
72489fmovs %f16, %f20
72490fadds %f16, %f17, %f16
72491! preparing store val #1, next val will be in f33
72492fmovs %f16, %f21
72493fadds %f16, %f17, %f16
72494! preparing store val #2, next val will be in f35
72495fmovd %f20, %f32
72496fmovs %f16, %f21
72497fadds %f16, %f17, %f16
72498fmovd %f20, %f34
72499membar #Sync
72500stda %f32, [%i1 + 0 ] %asi
72501
72502P6930: !_MEMBAR (FP)
72503membar #StoreLoad
72504
72505P6931: !_DWLD [22] (Int) (CBR)
72506ldx [%i3 + 0], %o1
72507! move %o1(upper) -> %o1(upper)
72508! move %o1(lower) -> %o1(lower)
72509
72510! cbranch
72511andcc %l0, 1, %g0
72512be,pt %xcc, TARGET6931
72513nop
72514RET6931:
72515
72516! lfsr step begin
72517srlx %l0, 1, %l6
72518xnor %l6, %l0, %l6
72519sllx %l6, 63, %l6
72520or %l6, %l0, %l0
72521srlx %l0, 1, %l0
72522
72523
72524P6932: !_ST [23] (maybe <- 0x300016c) (Int)
72525stw %l4, [%i3 + 12 ]
72526add %l4, 1, %l4
72527
72528P6933: !_MEMBAR (FP)
72529
72530P6934: !_BST [13] (maybe <- 0x4280010a) (FP)
72531wr %g0, 0xf0, %asi
72532sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
72533sub %i0, %i3, %i3
72534! preparing store val #0, next val will be in f32
72535fmovs %f16, %f20
72536fadds %f16, %f17, %f16
72537! preparing store val #1, next val will be in f33
72538fmovs %f16, %f21
72539fadds %f16, %f17, %f16
72540! preparing store val #2, next val will be in f35
72541fmovd %f20, %f32
72542fmovs %f16, %f21
72543fadds %f16, %f17, %f16
72544fmovd %f20, %f34
72545membar #Sync
72546stda %f32, [%i3 + 0 ] %asi
72547
72548P6935: !_MEMBAR (FP)
72549membar #StoreLoad
72550
72551P6936: !_ST [9] (maybe <- 0x300016d) (Int)
72552stw %l4, [%i2 + 0 ]
72553add %l4, 1, %l4
72554
72555P6937: !_DWST_BINIT [15] (maybe <- 0x300016e) (Int)
72556wr %g0, 0xe2, %asi
72557sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
72558add %i0, %i2, %i2
72559sllx %l4, 32, %o5
72560add %l4, 1, %l4
72561or %o5, %l4, %o5
72562stxa %o5, [%i2 + 0] %asi
72563add %l4, 1, %l4
72564
72565P6938: !_MEMBAR (Int)
72566membar #StoreLoad
72567
72568P6939: !_CAS [8] (maybe <- 0x3000170) (Int)
72569sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
72570sub %i0, %i3, %i3
72571add %i3, 12, %o5
72572lduw [%o5], %o2
72573mov %o2, %l7
72574! move %l7(lower) -> %o2(upper)
72575sllx %l7, 32, %o2
72576mov %l4, %l6
72577cas [%o5], %l7, %l6
72578! move %l6(lower) -> %o2(lower)
72579srl %l6, 0, %l7
72580or %l7, %o2, %o2
72581add %l4, 1, %l4
72582
72583P6940: !_MEMBAR (FP)
72584
72585P6941: !_BST [8] (maybe <- 0x4280010d) (FP)
72586wr %g0, 0xf0, %asi
72587! preparing store val #0, next val will be in f32
72588fmovs %f16, %f20
72589fadds %f16, %f17, %f16
72590! preparing store val #1, next val will be in f33
72591fmovs %f16, %f21
72592fadds %f16, %f17, %f16
72593! preparing store val #2, next val will be in f35
72594fmovd %f20, %f32
72595fmovs %f16, %f21
72596fadds %f16, %f17, %f16
72597fmovd %f20, %f34
72598membar #Sync
72599stda %f32, [%i3 + 0 ] %asi
72600
72601P6942: !_MEMBAR (FP)
72602membar #StoreLoad
72603
72604P6943: !_SWAP [20] (maybe <- 0x3000171) (Int)
72605sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
72606sub %i0, %i2, %i2
72607mov %l4, %o3
72608swap [%i2 + 12], %o3
72609! move %o3(lower) -> %o3(upper)
72610sllx %o3, 32, %o3
72611add %l4, 1, %l4
72612
72613P6944: !_ST_BINIT [4] (maybe <- 0x3000172) (Int)
72614wr %g0, 0xe2, %asi
72615stwa %l4, [%i1 + 4] %asi
72616add %l4, 1, %l4
72617
72618P6945: !_MEMBAR (Int) (Branch target of P6838)
72619membar #StoreLoad
72620ba P6946
72621nop
72622
72623TARGET6838:
72624ba RET6838
72625nop
72626
72627
72628P6946: !_DWST_BINIT [9] (maybe <- 0x3000173) (Int)
72629wr %g0, 0xe2, %asi
72630sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
72631sub %i0, %i3, %i3
72632sllx %l4, 32, %o5
72633add %l4, 1, %l4
72634or %o5, %l4, %o5
72635stxa %o5, [%i3 + 0] %asi
72636add %l4, 1, %l4
72637
72638P6947: !_MEMBAR (Int)
72639membar #StoreLoad
72640
72641P6948: !_CASX [4] (maybe <- 0x3000175) (Int)
72642ldx [%i1], %l6
72643! move %l6(upper) -> %o3(lower)
72644srlx %l6, 32, %l7
72645or %l7, %o3, %o3
72646! move %l6(lower) -> %o4(upper)
72647sllx %l6, 32, %o4
72648mov %l6, %l7
72649sllx %l4, 32, %l6
72650add %l4, 1, %l4
72651or %l4, %l6, %l6
72652casx [%i1], %l7, %l6
72653! move %l6(upper) -> %o4(lower)
72654srlx %l6, 32, %l7
72655or %l7, %o4, %o4
72656!---- flushing int results buffer----
72657mov %o0, %l5
72658mov %o1, %l5
72659mov %o2, %l5
72660mov %o3, %l5
72661mov %o4, %l5
72662! move %l6(lower) -> %o0(upper)
72663sllx %l6, 32, %o0
72664add %l4, 1, %l4
72665
72666P6949: !_LDD [18] (Int)
72667ldd [%i2 + 0], %l6
72668! move %l6(lower) -> %o0(lower)
72669or %l6, %o0, %o0
72670! move %l7(lower) -> %o1(upper)
72671sllx %l7, 32, %o1
72672
72673P6950: !_CASX [5] (maybe <- 0x3000177) (Int)
72674add %i1, 8, %l6
72675ldx [%l6], %o5
72676! move %o5(upper) -> %o1(lower)
72677srlx %o5, 32, %l3
72678or %l3, %o1, %o1
72679! move %o5(lower) -> %o2(upper)
72680sllx %o5, 32, %o2
72681mov %o5, %l3
72682mov %l4, %o5
72683casx [%l6], %l3, %o5
72684! move %o5(upper) -> %o2(lower)
72685srlx %o5, 32, %l3
72686or %l3, %o2, %o2
72687! move %o5(lower) -> %o3(upper)
72688sllx %o5, 32, %o3
72689add %l4, 1, %l4
72690
72691P6951: !_ST_BINIT [16] (maybe <- 0x3000178) (Int)
72692wr %g0, 0xe2, %asi
72693sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
72694add %i0, %i2, %i2
72695stwa %l4, [%i2 + 4] %asi
72696add %l4, 1, %l4
72697
72698P6952: !_MEMBAR (Int)
72699membar #StoreLoad
72700
72701P6953: !_BLD [23] (FP)
72702wr %g0, 0xf0, %asi
72703sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
72704sub %i0, %i3, %i3
72705ldda [%i3 + 0] %asi, %f32
72706membar #Sync
72707! 3 addresses covered
72708fmovd %f32, %f18
72709fmovs %f18, %f3
72710fmovs %f19, %f4
72711fmovd %f34, %f18
72712fmovs %f19, %f5
72713
72714P6954: !_MEMBAR (FP)
72715
72716P6955: !_PREFETCH [2] (Int)
72717prefetch [%i0 + 12], 23
72718
72719P6956: !_CASX [6] (maybe <- 0x3000179) (Int)
72720sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
72721sub %i0, %i2, %i2
72722ldx [%i2], %l7
72723! move %l7(upper) -> %o3(lower)
72724srlx %l7, 32, %o5
72725or %o5, %o3, %o3
72726! move %l7(lower) -> %o4(upper)
72727sllx %l7, 32, %o4
72728mov %l7, %o5
72729sllx %l4, 32, %l7
72730add %l4, 1, %l4
72731or %l4, %l7, %l7
72732casx [%i2], %o5, %l7
72733! move %l7(upper) -> %o4(lower)
72734srlx %l7, 32, %o5
72735or %o5, %o4, %o4
72736!---- flushing int results buffer----
72737mov %o0, %l5
72738mov %o1, %l5
72739mov %o2, %l5
72740mov %o3, %l5
72741mov %o4, %l5
72742! move %l7(lower) -> %o0(upper)
72743sllx %l7, 32, %o0
72744add %l4, 1, %l4
72745
72746P6957: !_LDD [8] (Int)
72747ldd [%i2 + 8], %l6
72748! move %l7(lower) -> %o0(lower)
72749or %l7, %o0, %o0
72750
72751P6958: !_ST [18] (maybe <- 0x300017b) (Int)
72752sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
72753sub %i0, %i3, %i3
72754stw %l4, [%i3 + 0 ]
72755add %l4, 1, %l4
72756
72757P6959: !_ST_BINIT [13] (maybe <- 0x300017c) (Int)
72758wr %g0, 0xe2, %asi
72759sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
72760sub %i0, %i2, %i2
72761stwa %l4, [%i2 + 4] %asi
72762add %l4, 1, %l4
72763
72764P6960: !_MEMBAR (Int) (CBR)
72765membar #StoreLoad
72766
72767! cbranch
72768andcc %l0, 1, %g0
72769be,pn %xcc, TARGET6960
72770nop
72771RET6960:
72772
72773! lfsr step begin
72774srlx %l0, 1, %l7
72775xnor %l7, %l0, %l7
72776sllx %l7, 63, %l7
72777or %l7, %l0, %l0
72778srlx %l0, 1, %l0
72779
72780
72781P6961: !_PREFETCH [21] (Int)
72782sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
72783sub %i0, %i3, %i3
72784prefetch [%i3 + 0], 1
72785
72786P6962: !_MEMBAR (FP) (CBR)
72787membar #StoreLoad
72788
72789! cbranch
72790andcc %l0, 1, %g0
72791be,pn %xcc, TARGET6962
72792nop
72793RET6962:
72794
72795! lfsr step begin
72796srlx %l0, 1, %o5
72797xnor %o5, %l0, %o5
72798sllx %o5, 63, %o5
72799or %o5, %l0, %l0
72800srlx %l0, 1, %l0
72801
72802
72803P6963: !_BLD [9] (FP)
72804wr %g0, 0xf0, %asi
72805sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
72806sub %i0, %i2, %i2
72807ldda [%i2 + 0] %asi, %f32
72808membar #Sync
72809! 3 addresses covered
72810fmovd %f32, %f6
72811fmovd %f34, %f18
72812fmovs %f19, %f8
72813
72814P6964: !_MEMBAR (FP)
72815
72816P6965: !_LD [6] (Int)
72817sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
72818sub %i0, %i3, %i3
72819lduw [%i3 + 0], %o1
72820! move %o1(lower) -> %o1(upper)
72821sllx %o1, 32, %o1
72822
72823P6966: !_MEMBAR (FP)
72824membar #StoreLoad
72825
72826P6967: !_BLD [8] (FP)
72827wr %g0, 0xf0, %asi
72828ldda [%i3 + 0] %asi, %f32
72829membar #Sync
72830! 3 addresses covered
72831fmovd %f32, %f18
72832fmovs %f18, %f9
72833fmovs %f19, %f10
72834fmovd %f34, %f18
72835fmovs %f19, %f11
72836
72837P6968: !_MEMBAR (FP)
72838
72839P6969: !_DWST_BINIT [12] (maybe <- 0x300017d) (Int) (LE)
72840wr %g0, 0xea, %asi
72841sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
72842sub %i0, %i2, %i2
72843sllx %l4, 32, %l7
72844add %l4, 1, %l4
72845or %l7, %l4, %o5
72846! Change double-word-level endianess (big endian <-> little endian)
72847sethi %hi(0xff00ff00), %l3
72848or %l3, %lo(0xff00ff00), %l3
72849sllx %l3, 32, %l7
72850or %l3, %l7, %l3
72851and %o5, %l3, %l7
72852srlx %l7, 8, %l7
72853sllx %o5, 8, %o5
72854and %o5, %l3, %o5
72855or %o5, %l7, %o5
72856sethi %hi(0xffff0000), %l3
72857srlx %o5, 16, %l7
72858andn %l7, %l3, %l7
72859andn %o5, %l3, %o5
72860sllx %o5, 16, %o5
72861or %o5, %l7, %o5
72862srlx %o5, 32, %l7
72863sllx %o5, 32, %o5
72864or %o5, %l7, %l7
72865stxa %l7, [%i2 + 0 ] %asi
72866add %l4, 1, %l4
72867
72868P6970: !_MEMBAR (Int) (LE)
72869membar #StoreLoad
72870
72871P6971: !_DWST_BINIT [9] (maybe <- 0x300017f) (Int)
72872wr %g0, 0xe2, %asi
72873sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
72874sub %i0, %i3, %i3
72875sllx %l4, 32, %l6
72876add %l4, 1, %l4
72877or %l6, %l4, %l6
72878stxa %l6, [%i3 + 0] %asi
72879add %l4, 1, %l4
72880
72881P6972: !_MEMBAR (Int)
72882
72883P6973: !_BSTC [18] (maybe <- 0x42800110) (FP)
72884wr %g0, 0xe0, %asi
72885sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
72886sub %i0, %i2, %i2
72887! preparing store val #0, next val will be in f32
72888fmovs %f16, %f20
72889fadds %f16, %f17, %f16
72890! preparing store val #1, next val will be in f33
72891fmovs %f16, %f21
72892fadds %f16, %f17, %f16
72893! preparing store val #2, next val will be in f35
72894fmovd %f20, %f32
72895fmovs %f16, %f21
72896fadds %f16, %f17, %f16
72897fmovd %f20, %f34
72898membar #Sync
72899stda %f32, [%i2 + 0 ] %asi
72900
72901P6974: !_MEMBAR (FP)
72902membar #StoreLoad
72903
72904P6975: !_CASX [19] (maybe <- 0x3000181) (Int)
72905ldx [%i2], %o5
72906! move %o5(upper) -> %o1(lower)
72907srlx %o5, 32, %l3
72908or %l3, %o1, %o1
72909! move %o5(lower) -> %o2(upper)
72910sllx %o5, 32, %o2
72911mov %o5, %l3
72912sllx %l4, 32, %o5
72913add %l4, 1, %l4
72914or %l4, %o5, %o5
72915casx [%i2], %l3, %o5
72916! move %o5(upper) -> %o2(lower)
72917srlx %o5, 32, %l3
72918or %l3, %o2, %o2
72919! move %o5(lower) -> %o3(upper)
72920sllx %o5, 32, %o3
72921add %l4, 1, %l4
72922
72923P6976: !_MEMBAR (FP)
72924
72925P6977: !_BST [16] (maybe <- 0x42800113) (FP)
72926wr %g0, 0xf0, %asi
72927sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
72928add %i0, %i3, %i3
72929! preparing store val #0, next val will be in f32
72930fmovs %f16, %f20
72931fadds %f16, %f17, %f16
72932! preparing store val #1, next val will be in f33
72933fmovs %f16, %f21
72934fadds %f16, %f17, %f16
72935! preparing store val #2, next val will be in f35
72936fmovd %f20, %f32
72937fmovs %f16, %f21
72938fadds %f16, %f17, %f16
72939fmovd %f20, %f34
72940membar #Sync
72941stda %f32, [%i3 + 0 ] %asi
72942
72943P6978: !_MEMBAR (FP)
72944membar #StoreLoad
72945
72946P6979: !_ST [21] (maybe <- 0x3000183) (Int)
72947sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
72948sub %i0, %i2, %i2
72949stw %l4, [%i2 + 0 ]
72950add %l4, 1, %l4
72951
72952P6980: !_CASX [21] (maybe <- 0x3000184) (Int)
72953ldx [%i2], %l6
72954! move %l6(upper) -> %o3(lower)
72955srlx %l6, 32, %l7
72956or %l7, %o3, %o3
72957! move %l6(lower) -> %o4(upper)
72958sllx %l6, 32, %o4
72959mov %l6, %l7
72960sllx %l4, 32, %l6
72961add %l4, 1, %l4
72962or %l4, %l6, %l6
72963casx [%i2], %l7, %l6
72964! move %l6(upper) -> %o4(lower)
72965srlx %l6, 32, %l7
72966or %l7, %o4, %o4
72967!---- flushing int results buffer----
72968mov %o0, %l5
72969mov %o1, %l5
72970mov %o2, %l5
72971mov %o3, %l5
72972mov %o4, %l5
72973! move %l6(lower) -> %o0(upper)
72974sllx %l6, 32, %o0
72975add %l4, 1, %l4
72976
72977P6981: !_MEMBAR (FP) (Branch target of P6931)
72978membar #StoreLoad
72979ba P6982
72980nop
72981
72982TARGET6931:
72983ba RET6931
72984nop
72985
72986
72987P6982: !_BLD [9] (FP)
72988wr %g0, 0xf0, %asi
72989sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
72990sub %i0, %i3, %i3
72991ldda [%i3 + 0] %asi, %f32
72992membar #Sync
72993! 3 addresses covered
72994fmovd %f32, %f12
72995fmovd %f34, %f18
72996fmovs %f19, %f14
72997
72998P6983: !_MEMBAR (FP) (Branch target of P6075)
72999ba P6984
73000nop
73001
73002TARGET6075:
73003ba RET6075
73004nop
73005
73006
73007P6984: !_CASX [5] (maybe <- 0x3000186) (Int)
73008add %i1, 8, %o5
73009ldx [%o5], %l6
73010! move %l6(upper) -> %o0(lower)
73011srlx %l6, 32, %l7
73012or %l7, %o0, %o0
73013! move %l6(lower) -> %o1(upper)
73014sllx %l6, 32, %o1
73015mov %l6, %l7
73016mov %l4, %l6
73017casx [%o5], %l7, %l6
73018! move %l6(upper) -> %o1(lower)
73019srlx %l6, 32, %l7
73020or %l7, %o1, %o1
73021! move %l6(lower) -> %o2(upper)
73022sllx %l6, 32, %o2
73023add %l4, 1, %l4
73024
73025P6985: !_REPLACEMENT [6] (Int) (CBR)
73026sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
73027sub %i0, %i2, %i2
73028sethi %hi(0x20000), %l7
73029ld [%i2+0], %l3
73030st %l3, [%i2+0]
73031add %i2, %l7, %o5
73032ld [%o5+0], %l3
73033st %l3, [%o5+0]
73034add %o5, %l7, %o5
73035ld [%o5+0], %l3
73036st %l3, [%o5+0]
73037add %o5, %l7, %o5
73038ld [%o5+0], %l3
73039st %l3, [%o5+0]
73040add %o5, %l7, %o5
73041ld [%o5+0], %l3
73042st %l3, [%o5+0]
73043add %o5, %l7, %o5
73044ld [%o5+0], %l3
73045st %l3, [%o5+0]
73046add %o5, %l7, %o5
73047ld [%o5+0], %l3
73048st %l3, [%o5+0]
73049add %o5, %l7, %o5
73050ld [%o5+0], %l3
73051st %l3, [%o5+0]
73052
73053! cbranch
73054andcc %l0, 1, %g0
73055be,pt %xcc, TARGET6985
73056nop
73057RET6985:
73058
73059! lfsr step begin
73060srlx %l0, 1, %l6
73061xnor %l6, %l0, %l6
73062sllx %l6, 63, %l6
73063or %l6, %l0, %l0
73064srlx %l0, 1, %l0
73065
73066
73067P6986: !_CASX [13] (maybe <- 0x3000187) (Int)
73068sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
73069sub %i0, %i3, %i3
73070ldx [%i3], %l6
73071! move %l6(upper) -> %o2(lower)
73072srlx %l6, 32, %l7
73073or %l7, %o2, %o2
73074! move %l6(lower) -> %o3(upper)
73075sllx %l6, 32, %o3
73076mov %l6, %l7
73077sllx %l4, 32, %l6
73078add %l4, 1, %l4
73079or %l4, %l6, %l6
73080casx [%i3], %l7, %l6
73081! move %l6(upper) -> %o3(lower)
73082srlx %l6, 32, %l7
73083or %l7, %o3, %o3
73084! move %l6(lower) -> %o4(upper)
73085sllx %l6, 32, %o4
73086add %l4, 1, %l4
73087
73088P6987: !_LD [14] (Int) (Branch target of P6848)
73089lduw [%i3 + 12], %o5
73090! move %o5(lower) -> %o4(lower)
73091or %o5, %o4, %o4
73092!---- flushing int results buffer----
73093mov %o0, %l5
73094mov %o1, %l5
73095mov %o2, %l5
73096mov %o3, %l5
73097mov %o4, %l5
73098ba P6988
73099nop
73100
73101TARGET6848:
73102ba RET6848
73103nop
73104
73105
73106P6988: !_CASX [16] (maybe <- 0x3000189) (Int)
73107sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
73108add %i0, %i2, %i2
73109ldx [%i2], %o0
73110! move %o0(upper) -> %o0(upper)
73111! move %o0(lower) -> %o0(lower)
73112mov %o0, %l3
73113sllx %l4, 32, %o1
73114add %l4, 1, %l4
73115or %l4, %o1, %o1
73116casx [%i2], %l3, %o1
73117! move %o1(upper) -> %o1(upper)
73118! move %o1(lower) -> %o1(lower)
73119add %l4, 1, %l4
73120
73121P6989: !_CASX [8] (maybe <- 0x300018b) (Int)
73122sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
73123sub %i0, %i3, %i3
73124add %i3, 8, %l6
73125ldx [%l6], %o2
73126! move %o2(upper) -> %o2(upper)
73127! move %o2(lower) -> %o2(lower)
73128mov %o2, %l3
73129mov %l4, %o3
73130casx [%l6], %l3, %o3
73131! move %o3(upper) -> %o3(upper)
73132! move %o3(lower) -> %o3(lower)
73133add %l4, 1, %l4
73134
73135P6990: !_CASX [3] (maybe <- 0x300018c) (Int)
73136ldx [%i1], %o4
73137! move %o4(upper) -> %o4(upper)
73138! move %o4(lower) -> %o4(lower)
73139!---- flushing int results buffer----
73140mov %o0, %l5
73141mov %o1, %l5
73142mov %o2, %l5
73143mov %o3, %l5
73144mov %o4, %l5
73145mov %o4, %l3
73146sllx %l4, 32, %o0
73147add %l4, 1, %l4
73148or %l4, %o0, %o0
73149casx [%i1], %l3, %o0
73150! move %o0(upper) -> %o0(upper)
73151! move %o0(lower) -> %o0(lower)
73152add %l4, 1, %l4
73153
73154P6991: !_CASX [16] (maybe <- 0x300018e) (Int)
73155ldx [%i2], %o1
73156! move %o1(upper) -> %o1(upper)
73157! move %o1(lower) -> %o1(lower)
73158mov %o1, %l3
73159sllx %l4, 32, %o2
73160add %l4, 1, %l4
73161or %l4, %o2, %o2
73162casx [%i2], %l3, %o2
73163! move %o2(upper) -> %o2(upper)
73164! move %o2(lower) -> %o2(lower)
73165add %l4, 1, %l4
73166
73167P6992: !_DWST_BINIT [22] (maybe <- 0x3000190) (Int)
73168wr %g0, 0xe2, %asi
73169sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
73170sub %i0, %i2, %i2
73171sllx %l4, 32, %l3
73172add %l4, 1, %l4
73173or %l3, %l4, %l3
73174stxa %l3, [%i2 + 0] %asi
73175add %l4, 1, %l4
73176
73177P6993: !_MEMBAR (Int)
73178membar #StoreLoad
73179
73180P6994: !_PREFETCH [14] (Int)
73181sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
73182sub %i0, %i3, %i3
73183prefetch [%i3 + 12], 22
73184
73185P6995: !_SWAP [19] (maybe <- 0x3000192) (Int)
73186sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
73187sub %i0, %i2, %i2
73188mov %l4, %o3
73189swap [%i2 + 4], %o3
73190! move %o3(lower) -> %o3(upper)
73191sllx %o3, 32, %o3
73192add %l4, 1, %l4
73193
73194P6996: !_MEMBAR (FP) (Branch target of P6102)
73195membar #StoreLoad
73196ba P6997
73197nop
73198
73199TARGET6102:
73200ba RET6102
73201nop
73202
73203
73204P6997: !_BLD [4] (FP)
73205wr %g0, 0xf0, %asi
73206ldda [%i1 + 0] %asi, %f32
73207membar #Sync
73208! 3 addresses covered
73209fmovd %f32, %f18
73210fmovs %f18, %f15
73211!---- flushing fp results buffer to %f30 ----
73212fmovd %f0, %f30
73213fmovd %f2, %f30
73214fmovd %f4, %f30
73215fmovd %f6, %f30
73216fmovd %f8, %f30
73217fmovd %f10, %f30
73218fmovd %f12, %f30
73219fmovd %f14, %f30
73220!--
73221fmovs %f19, %f0
73222fmovd %f34, %f18
73223fmovs %f19, %f1
73224
73225P6998: !_MEMBAR (FP)
73226
73227P6999: !_DWST_BINIT [3] (maybe <- 0x3000193) (Int)
73228wr %g0, 0xe2, %asi
73229sllx %l4, 32, %l7
73230add %l4, 1, %l4
73231or %l7, %l4, %l7
73232stxa %l7, [%i1 + 0] %asi
73233add %l4, 1, %l4
73234
73235P7000: !_MEMBAR (Int)
73236
73237P7001: !_BST [3] (maybe <- 0x42800116) (FP)
73238wr %g0, 0xf0, %asi
73239! preparing store val #0, next val will be in f32
73240fmovs %f16, %f20
73241fadds %f16, %f17, %f16
73242! preparing store val #1, next val will be in f33
73243fmovs %f16, %f21
73244fadds %f16, %f17, %f16
73245! preparing store val #2, next val will be in f35
73246fmovd %f20, %f32
73247fmovs %f16, %f21
73248fadds %f16, %f17, %f16
73249fmovd %f20, %f34
73250membar #Sync
73251stda %f32, [%i1 + 0 ] %asi
73252
73253P7002: !_MEMBAR (FP)
73254membar #StoreLoad
73255
73256P7003: !_BLD [18] (FP)
73257wr %g0, 0xf0, %asi
73258ldda [%i2 + 0] %asi, %f32
73259membar #Sync
73260! 3 addresses covered
73261fmovd %f32, %f2
73262fmovd %f34, %f18
73263fmovs %f19, %f4
73264
73265P7004: !_MEMBAR (FP)
73266
73267P7005: !_LDD [10] (Int)
73268sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
73269sub %i0, %i3, %i3
73270ldd [%i3 + 0], %l6
73271! move %l6(lower) -> %o3(lower)
73272or %l6, %o3, %o3
73273! move %l7(lower) -> %o4(upper)
73274sllx %l7, 32, %o4
73275
73276P7006: !_SWAP [12] (maybe <- 0x3000195) (Int)
73277sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
73278sub %i0, %i2, %i2
73279mov %l4, %l7
73280swap [%i2 + 0], %l7
73281! move %l7(lower) -> %o4(lower)
73282srl %l7, 0, %l3
73283or %l3, %o4, %o4
73284!---- flushing int results buffer----
73285mov %o0, %l5
73286mov %o1, %l5
73287mov %o2, %l5
73288mov %o3, %l5
73289mov %o4, %l5
73290add %l4, 1, %l4
73291
73292P7007: !_ST_BINIT [17] (maybe <- 0x3000196) (Int)
73293wr %g0, 0xe2, %asi
73294sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
73295add %i0, %i3, %i3
73296stwa %l4, [%i3 + 12] %asi
73297add %l4, 1, %l4
73298
73299P7008: !_MEMBAR (Int) (Branch target of P6913)
73300membar #StoreLoad
73301ba P7009
73302nop
73303
73304TARGET6913:
73305ba RET6913
73306nop
73307
73308
73309P7009: !_ST_BINIT [2] (maybe <- 0x3000197) (Int)
73310wr %g0, 0xe2, %asi
73311stwa %l4, [%i0 + 12] %asi
73312add %l4, 1, %l4
73313
73314P7010: !_MEMBAR (Int)
73315membar #StoreLoad
73316
73317P7011: !_DWST_BINIT [1] (maybe <- 0x3000198) (Int)
73318wr %g0, 0xe2, %asi
73319sllx %l4, 32, %l6
73320add %l4, 1, %l4
73321or %l6, %l4, %l6
73322stxa %l6, [%i0 + 0] %asi
73323add %l4, 1, %l4
73324
73325P7012: !_MEMBAR (Int)
73326
73327P7013: !_BSTC [11] (maybe <- 0x42800119) (FP)
73328wr %g0, 0xe0, %asi
73329sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
73330sub %i0, %i2, %i2
73331! preparing store val #0, next val will be in f32
73332fmovs %f16, %f20
73333fadds %f16, %f17, %f16
73334! preparing store val #1, next val will be in f33
73335fmovs %f16, %f21
73336fadds %f16, %f17, %f16
73337! preparing store val #2, next val will be in f35
73338fmovd %f20, %f32
73339fmovs %f16, %f21
73340fadds %f16, %f17, %f16
73341fmovd %f20, %f34
73342membar #Sync
73343stda %f32, [%i2 + 0 ] %asi
73344
73345P7014: !_MEMBAR (FP) (Loop exit)
73346membar #StoreLoad
73347!---- flushing fp results buffer to %f30 ----
73348fmovd %f0, %f30
73349fmovd %f2, %f30
73350fmovs %f4, %f30
73351!--
73352
73353sethi %hi(0x200000), %o5
73354add %i1, %o5, %i1
73355!-- End Aliased access: base register for region 1 (%i1) restored
73356loop_exit_6_0:
73357sub %l2, 1, %l2
73358cmp %l2, 0
73359bg loop_entry_6_0
73360nop
73361
73362P7015: !_MEMBAR (Int)
73363membar #StoreLoad
73364
73365END_NODES6: ! Test instruction sequence for CPU 6 ends
73366sethi %hi(0xdead0e0f), %l3
73367or %l3, %lo(0xdead0e0f), %l3
73368! move %l3(lower) -> %o0(upper)
73369sllx %l3, 32, %o0
73370sethi %hi(0xdead0e0f), %l3
73371or %l3, %lo(0xdead0e0f), %l3
73372stw %l3, [%i5]
73373ld [%i5], %f0
73374!---- flushing int results buffer----
73375mov %o0, %l5
73376!---- flushing fp results buffer to %f30 ----
73377fmovs %f0, %f30
73378!--
73379
73380restore
73381retl
73382nop
73383!-----------------
73384
73385! register usage:
73386! %i0 %i1 : base registers for first 2 regions
73387! %i2 %i3 : cache registers for 8 regions
73388! %i4 fixed pointer to per-cpu results area
73389! %l1 moving pointer to per-cpu FP results area
73390! %o7 moving pointer to per-cpu integer results area
73391! %i5 pointer to per-cpu private area
73392! %l0 holds lfsr, used as source of random bits
73393! %l2 loop count register
73394! %f16 running counter for unique fp store values
73395! %f17 holds increment value for fp counter
73396! %l4 running counter for unique integer store values (increment value is always 1)
73397! %l5 move-to register for load values (simulation only)
73398! %f30 move-to register for FP values (simulation only)
73399! %i4 holds the instructions count which is used for interrupt ordering
73400! %i4 holds the thread_id (OBP only)
73401! %l5 holds the moving pointer for interrupt bonus data (OBP only). Conflicts with RTL/simulation usage
73402! %l3 %l6 %l7 %o5 : 4 temporary registers
73403! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers
73404! %f0-f15 FP results buffer registers
73405! %f32-f47 FP block load/store registers
73406
73407func7:
73408! instruction sequence begins
73409save %sp, -192, %sp
73410
73411! Force %i0-%i3 to be 64-byte aligned
73412add %i0, 63, %i0
73413andn %i0, 63, %i0
73414
73415add %i1, 63, %i1
73416andn %i1, 63, %i1
73417
73418add %i2, 63, %i2
73419andn %i2, 63, %i2
73420
73421add %i3, 63, %i3
73422andn %i3, 63, %i3
73423
73424add %i4, 63, %i4
73425andn %i4, 63, %i4
73426
73427add %i5, 63, %i5
73428andn %i5, 63, %i5
73429
73430
73431! Initialize pointer to FP load results area
73432mov %i4, %l1
73433
73434! Initialize pointer to integer load results area
73435sethi %hi(0x80000), %o7
73436or %o7, %lo(0x80000), %o7
73437add %o7, %l1, %o7
73438
73439! Reinitialize i4 to 0. i4 will be used to keep the count of analyzable node info
73440mov 0x0, %i4
73441
73442! Initialize %f0-%f62 to 0xdeadbee0deadbee1
73443sethi %hi(0xdeadbee0), %o5
73444or %o5, %lo(0xdeadbee0), %o5
73445stw %o5, [%i5]
73446sethi %hi(0xdeadbee1), %o5
73447or %o5, %lo(0xdeadbee1), %o5
73448stw %o5, [%i5+4]
73449ldd [%i5], %f0
73450fmovd %f0, %f2
73451fmovd %f0, %f4
73452fmovd %f0, %f6
73453fmovd %f0, %f8
73454fmovd %f0, %f10
73455fmovd %f0, %f12
73456fmovd %f0, %f14
73457fmovd %f0, %f16
73458fmovd %f0, %f18
73459fmovd %f0, %f20
73460fmovd %f0, %f22
73461fmovd %f0, %f24
73462fmovd %f0, %f26
73463fmovd %f0, %f28
73464fmovd %f0, %f30
73465fmovd %f0, %f32
73466fmovd %f0, %f34
73467fmovd %f0, %f36
73468fmovd %f0, %f38
73469fmovd %f0, %f40
73470fmovd %f0, %f42
73471fmovd %f0, %f44
73472fmovd %f0, %f46
73473fmovd %f0, %f48
73474fmovd %f0, %f50
73475fmovd %f0, %f52
73476fmovd %f0, %f54
73477fmovd %f0, %f56
73478fmovd %f0, %f58
73479fmovd %f0, %f60
73480fmovd %f0, %f62
73481
73482! Signature for extract_loads script to start extracting load values for this stream
73483sethi %hi(0x07deade1), %o5
73484or %o5, %lo(0x07deade1), %o5
73485stw %o5, [%i5]
73486ld [%i5], %f16
73487
73488! Initialize running integer counter in register %l4
73489sethi %hi(0x3800001), %l4
73490or %l4, %lo(0x3800001), %l4
73491
73492! Initialize running FP counter in register %f16
73493sethi %hi(0x43000001), %o5
73494or %o5, %lo(0x43000001), %o5
73495stw %o5, [%i5]
73496ld [%i5], %f16
73497
73498! Initialize FP counter increment value in register %f17 (constant)
73499sethi %hi(0x37800000), %o5
73500or %o5, %lo(0x37800000), %o5
73501stw %o5, [%i5]
73502ld [%i5], %f17
73503
73504! Initialize LFSR to 0x720b^4
73505sethi %hi(0x720b), %l0
73506or %l0, %lo(0x720b), %l0
73507mulx %l0, %l0, %l0
73508mulx %l0, %l0, %l0
73509
73510BEGIN_NODES7: ! Test instruction sequence for ISTREAM 7 begins
73511
73512P7016: !_CASX [22] (maybe <- 0x3800001) (Int) (Loop entry)
73513sethi %hi(0x1), %l2
73514or %l2, %lo(0x1), %l2
73515loop_entry_7_0:
73516sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
73517sub %i0, %i3, %i3
73518ldx [%i3], %o0
73519! move %o0(upper) -> %o0(upper)
73520! move %o0(lower) -> %o0(lower)
73521mov %o0, %l3
73522sllx %l4, 32, %o1
73523add %l4, 1, %l4
73524or %l4, %o1, %o1
73525casx [%i3], %l3, %o1
73526! move %o1(upper) -> %o1(upper)
73527! move %o1(lower) -> %o1(lower)
73528add %l4, 1, %l4
73529
73530P7017: !_DWST [5] (maybe <- 0x3800003) (Int)
73531mov %l4, %l3
73532stx %l3, [%i1 + 8]
73533add %l4, 1, %l4
73534
73535P7018: !_PREFETCH [7] (Int)
73536sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
73537sub %i0, %i2, %i2
73538prefetch [%i2 + 4], 1
73539
73540P7019: !_CASX [4] (maybe <- 0x3800004) (Int)
73541ldx [%i1], %o2
73542! move %o2(upper) -> %o2(upper)
73543! move %o2(lower) -> %o2(lower)
73544mov %o2, %o5
73545sllx %l4, 32, %o3
73546add %l4, 1, %l4
73547or %l4, %o3, %o3
73548casx [%i1], %o5, %o3
73549! move %o3(upper) -> %o3(upper)
73550! move %o3(lower) -> %o3(lower)
73551add %l4, 1, %l4
73552
73553P7020: !_MEMBAR (FP)
73554
73555P7021: !_BST [13] (maybe <- 0x43000001) (FP)
73556wr %g0, 0xf0, %asi
73557sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
73558sub %i0, %i3, %i3
73559! preparing store val #0, next val will be in f32
73560fmovs %f16, %f20
73561fadds %f16, %f17, %f16
73562! preparing store val #1, next val will be in f33
73563fmovs %f16, %f21
73564fadds %f16, %f17, %f16
73565! preparing store val #2, next val will be in f35
73566fmovd %f20, %f32
73567fmovs %f16, %f21
73568fadds %f16, %f17, %f16
73569fmovd %f20, %f34
73570membar #Sync
73571stda %f32, [%i3 + 0 ] %asi
73572
73573P7022: !_MEMBAR (FP)
73574membar #StoreLoad
73575
73576P7023: !_SWAP [7] (maybe <- 0x3800006) (Int)
73577mov %l4, %o4
73578swap [%i2 + 4], %o4
73579! move %o4(lower) -> %o4(upper)
73580sllx %o4, 32, %o4
73581add %l4, 1, %l4
73582
73583P7024: !_PREFETCH [7] (Int)
73584prefetch [%i2 + 4], 0
73585
73586P7025: !_DWLD [11] (Int)
73587sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
73588sub %i0, %i2, %i2
73589ldx [%i2 + 8], %l7
73590! move %l7(lower) -> %o4(lower)
73591srl %l7, 0, %l6
73592or %l6, %o4, %o4
73593!---- flushing int results buffer----
73594mov %o0, %l5
73595mov %o1, %l5
73596mov %o2, %l5
73597mov %o3, %l5
73598mov %o4, %l5
73599
73600P7026: !_LD [16] (Int)
73601sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
73602add %i0, %i3, %i3
73603lduw [%i3 + 4], %o0
73604! move %o0(lower) -> %o0(upper)
73605sllx %o0, 32, %o0
73606
73607P7027: !_MEMBAR (FP) (Branch target of P7621)
73608ba P7028
73609nop
73610
73611TARGET7621:
73612ba RET7621
73613nop
73614
73615
73616P7028: !_BSTC [14] (maybe <- 0x43000004) (FP) (Branch target of P7764)
73617wr %g0, 0xe0, %asi
73618sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
73619sub %i0, %i2, %i2
73620! preparing store val #0, next val will be in f32
73621fmovs %f16, %f20
73622fadds %f16, %f17, %f16
73623! preparing store val #1, next val will be in f33
73624fmovs %f16, %f21
73625fadds %f16, %f17, %f16
73626! preparing store val #2, next val will be in f35
73627fmovd %f20, %f32
73628fmovs %f16, %f21
73629fadds %f16, %f17, %f16
73630fmovd %f20, %f34
73631membar #Sync
73632stda %f32, [%i2 + 0 ] %asi
73633ba P7029
73634nop
73635
73636TARGET7764:
73637ba RET7764
73638nop
73639
73640
73641P7029: !_MEMBAR (FP)
73642membar #StoreLoad
73643
73644P7030: !_CAS [11] (maybe <- 0x3800007) (Int)
73645sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
73646sub %i0, %i3, %i3
73647add %i3, 12, %l6
73648lduw [%l6], %o5
73649mov %o5, %l3
73650! move %l3(lower) -> %o0(lower)
73651or %l3, %o0, %o0
73652mov %l4, %o1
73653cas [%l6], %l3, %o1
73654! move %o1(lower) -> %o1(upper)
73655sllx %o1, 32, %o1
73656add %l4, 1, %l4
73657
73658P7031: !_SWAP [21] (maybe <- 0x3800008) (Int)
73659sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
73660sub %i0, %i2, %i2
73661mov %l4, %l7
73662swap [%i2 + 0], %l7
73663! move %l7(lower) -> %o1(lower)
73664srl %l7, 0, %l3
73665or %l3, %o1, %o1
73666add %l4, 1, %l4
73667
73668P7032: !_ST_BINIT [22] (maybe <- 0x3800009) (Int)
73669wr %g0, 0xe2, %asi
73670stwa %l4, [%i2 + 4] %asi
73671add %l4, 1, %l4
73672
73673P7033: !_MEMBAR (Int)
73674membar #StoreLoad
73675
73676P7034: !_SWAP [15] (maybe <- 0x380000a) (Int)
73677sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
73678add %i0, %i3, %i3
73679mov %l4, %o2
73680swap [%i3 + 0], %o2
73681! move %o2(lower) -> %o2(upper)
73682sllx %o2, 32, %o2
73683add %l4, 1, %l4
73684
73685P7035: !_LDD [2] (Int)
73686ldd [%i0 + 8], %l6
73687! move %l7(lower) -> %o2(lower)
73688or %l7, %o2, %o2
73689
73690P7036: !_DWLD [2] (Int)
73691ldx [%i0 + 8], %o3
73692! move %o3(lower) -> %o3(upper)
73693sllx %o3, 32, %o3
73694
73695P7037: !_ST_BINIT [14] (maybe <- 0x380000b) (Int)
73696wr %g0, 0xe2, %asi
73697sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
73698sub %i0, %i2, %i2
73699stwa %l4, [%i2 + 12] %asi
73700add %l4, 1, %l4
73701
73702P7038: !_MEMBAR (Int)
73703membar #StoreLoad
73704
73705P7039: !_BLD [13] (FP)
73706wr %g0, 0xf0, %asi
73707ldda [%i2 + 0] %asi, %f0
73708membar #Sync
73709! 3 addresses covered
73710fmovs %f3, %f2
73711
73712P7040: !_MEMBAR (FP)
73713
73714P7041: !_BST [6] (maybe <- 0x43000007) (FP)
73715wr %g0, 0xf0, %asi
73716sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
73717sub %i0, %i3, %i3
73718! preparing store val #0, next val will be in f32
73719fmovs %f16, %f20
73720fadds %f16, %f17, %f16
73721! preparing store val #1, next val will be in f33
73722fmovs %f16, %f21
73723fadds %f16, %f17, %f16
73724! preparing store val #2, next val will be in f35
73725fmovd %f20, %f32
73726fmovs %f16, %f21
73727fadds %f16, %f17, %f16
73728fmovd %f20, %f34
73729membar #Sync
73730stda %f32, [%i3 + 0 ] %asi
73731
73732P7042: !_MEMBAR (FP)
73733membar #StoreLoad
73734
73735P7043: !_DWLD [23] (FP)
73736sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
73737sub %i0, %i2, %i2
73738ldd [%i2 + 8], %f18
73739! 1 addresses covered
73740fmovs %f19, %f3
73741
73742P7044: !_MEMBAR (FP)
73743
73744P7045: !_BST [3] (maybe <- 0x4300000a) (FP)
73745wr %g0, 0xf0, %asi
73746! preparing store val #0, next val will be in f32
73747fmovs %f16, %f20
73748fadds %f16, %f17, %f16
73749! preparing store val #1, next val will be in f33
73750fmovs %f16, %f21
73751fadds %f16, %f17, %f16
73752! preparing store val #2, next val will be in f35
73753fmovd %f20, %f32
73754fmovs %f16, %f21
73755fadds %f16, %f17, %f16
73756fmovd %f20, %f34
73757membar #Sync
73758stda %f32, [%i1 + 0 ] %asi
73759
73760P7046: !_MEMBAR (FP)
73761membar #StoreLoad
73762
73763P7047: !_ST_BINIT [5] (maybe <- 0x380000c) (Int) (Branch target of P7387)
73764wr %g0, 0xe2, %asi
73765stwa %l4, [%i1 + 12] %asi
73766add %l4, 1, %l4
73767ba P7048
73768nop
73769
73770TARGET7387:
73771ba RET7387
73772nop
73773
73774
73775P7048: !_MEMBAR (Int)
73776membar #StoreLoad
73777
73778P7049: !_DWLD [21] (Int)
73779ldx [%i2 + 0], %o5
73780! move %o5(upper) -> %o3(lower)
73781srlx %o5, 32, %l7
73782or %l7, %o3, %o3
73783! move %o5(lower) -> %o4(upper)
73784sllx %o5, 32, %o4
73785
73786P7050: !_CAS [2] (maybe <- 0x380000d) (Int)
73787add %i0, 12, %l6
73788lduw [%l6], %o5
73789mov %o5, %l3
73790! move %l3(lower) -> %o4(lower)
73791or %l3, %o4, %o4
73792!---- flushing int results buffer----
73793mov %o0, %l5
73794mov %o1, %l5
73795mov %o2, %l5
73796mov %o3, %l5
73797mov %o4, %l5
73798mov %l4, %o0
73799cas [%l6], %l3, %o0
73800! move %o0(lower) -> %o0(upper)
73801sllx %o0, 32, %o0
73802add %l4, 1, %l4
73803
73804P7051: !_MEMBAR (FP)
73805membar #StoreLoad
73806
73807P7052: !_BLD [17] (FP)
73808wr %g0, 0xf0, %asi
73809sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
73810add %i0, %i3, %i3
73811ldda [%i3 + 0] %asi, %f32
73812membar #Sync
73813! 3 addresses covered
73814fmovd %f32, %f4
73815fmovd %f34, %f18
73816fmovs %f19, %f6
73817
73818P7053: !_MEMBAR (FP)
73819
73820P7054: !_BST [13] (maybe <- 0x4300000d) (FP)
73821wr %g0, 0xf0, %asi
73822sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
73823sub %i0, %i2, %i2
73824! preparing store val #0, next val will be in f32
73825fmovs %f16, %f20
73826fadds %f16, %f17, %f16
73827! preparing store val #1, next val will be in f33
73828fmovs %f16, %f21
73829fadds %f16, %f17, %f16
73830! preparing store val #2, next val will be in f35
73831fmovd %f20, %f32
73832fmovs %f16, %f21
73833fadds %f16, %f17, %f16
73834fmovd %f20, %f34
73835membar #Sync
73836stda %f32, [%i2 + 0 ] %asi
73837
73838P7055: !_MEMBAR (FP)
73839membar #StoreLoad
73840
73841P7056: !_ST [15] (maybe <- 0x380000e) (Int) (LE)
73842wr %g0, 0x88, %asi
73843! Change single-word-level endianess (big endian <-> little endian)
73844sethi %hi(0xff00ff00), %l3
73845or %l3, %lo(0xff00ff00), %l3
73846and %l4, %l3, %l6
73847srl %l6, 8, %l6
73848sll %l4, 8, %o5
73849and %o5, %l3, %o5
73850or %o5, %l6, %o5
73851srl %o5, 16, %l6
73852sll %o5, 16, %o5
73853srl %o5, 0, %o5
73854or %o5, %l6, %o5
73855stwa %o5, [%i3 + 0] %asi
73856add %l4, 1, %l4
73857
73858P7057: !_DWST_BINIT [6] (maybe <- 0x380000f) (Int)
73859wr %g0, 0xe2, %asi
73860sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
73861sub %i0, %i3, %i3
73862sllx %l4, 32, %l7
73863add %l4, 1, %l4
73864or %l7, %l4, %l7
73865stxa %l7, [%i3 + 0] %asi
73866add %l4, 1, %l4
73867
73868P7058: !_MEMBAR (Int)
73869membar #StoreLoad
73870
73871P7059: !_ST_BINIT [21] (maybe <- 0x3800011) (Int)
73872wr %g0, 0xe2, %asi
73873sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
73874sub %i0, %i2, %i2
73875stwa %l4, [%i2 + 0] %asi
73876add %l4, 1, %l4
73877
73878P7060: !_MEMBAR (Int)
73879membar #StoreLoad
73880
73881P7061: !_DWST [7] (maybe <- 0x3800012) (Int) (LE)
73882wr %g0, 0x88, %asi
73883sllx %l4, 32, %l3
73884add %l4, 1, %l4
73885or %l3, %l4, %l6
73886! Change double-word-level endianess (big endian <-> little endian)
73887sethi %hi(0xff00ff00), %l7
73888or %l7, %lo(0xff00ff00), %l7
73889sllx %l7, 32, %l3
73890or %l7, %l3, %l7
73891and %l6, %l7, %l3
73892srlx %l3, 8, %l3
73893sllx %l6, 8, %l6
73894and %l6, %l7, %l6
73895or %l6, %l3, %l6
73896sethi %hi(0xffff0000), %l7
73897srlx %l6, 16, %l3
73898andn %l3, %l7, %l3
73899andn %l6, %l7, %l6
73900sllx %l6, 16, %l6
73901or %l6, %l3, %l6
73902srlx %l6, 32, %l3
73903sllx %l6, 32, %l6
73904or %l6, %l3, %l3
73905stxa %l3, [%i3 + 0 ] %asi
73906add %l4, 1, %l4
73907
73908P7062: !_CAS [6] (maybe <- 0x3800014) (Int)
73909lduw [%i3], %l7
73910mov %l7, %o5
73911! move %o5(lower) -> %o0(lower)
73912or %o5, %o0, %o0
73913mov %l4, %o1
73914cas [%i3], %o5, %o1
73915! move %o1(lower) -> %o1(upper)
73916sllx %o1, 32, %o1
73917add %l4, 1, %l4
73918
73919P7063: !_SWAP [22] (maybe <- 0x3800015) (Int)
73920mov %l4, %l6
73921swap [%i2 + 4], %l6
73922! move %l6(lower) -> %o1(lower)
73923srl %l6, 0, %o5
73924or %o5, %o1, %o1
73925add %l4, 1, %l4
73926
73927P7064: !_DWST_BINIT [19] (maybe <- 0x3800016) (Int)
73928wr %g0, 0xe2, %asi
73929sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
73930sub %i0, %i3, %i3
73931sllx %l4, 32, %l7
73932add %l4, 1, %l4
73933or %l7, %l4, %l7
73934stxa %l7, [%i3 + 0] %asi
73935add %l4, 1, %l4
73936
73937P7065: !_MEMBAR (Int) (Branch target of P7859)
73938membar #StoreLoad
73939ba P7066
73940nop
73941
73942TARGET7859:
73943ba RET7859
73944nop
73945
73946
73947P7066: !_LD [2] (Int) (Branch target of P7713)
73948lduw [%i0 + 12], %o2
73949! move %o2(lower) -> %o2(upper)
73950sllx %o2, 32, %o2
73951ba P7067
73952nop
73953
73954TARGET7713:
73955ba RET7713
73956nop
73957
73958
73959P7067: !_CAS [15] (maybe <- 0x3800018) (Int)
73960sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
73961add %i0, %i2, %i2
73962lduw [%i2], %l7
73963mov %l7, %o5
73964! move %o5(lower) -> %o2(lower)
73965or %o5, %o2, %o2
73966mov %l4, %o3
73967cas [%i2], %o5, %o3
73968! move %o3(lower) -> %o3(upper)
73969sllx %o3, 32, %o3
73970add %l4, 1, %l4
73971
73972P7068: !_REPLACEMENT [21] (Int)
73973sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
73974sub %i0, %i3, %i3
73975sethi %hi(0x20000), %o5
73976ld [%i3+0], %l6
73977st %l6, [%i3+0]
73978add %i3, %o5, %l3
73979ld [%l3+0], %l6
73980st %l6, [%l3+0]
73981add %l3, %o5, %l3
73982ld [%l3+0], %l6
73983st %l6, [%l3+0]
73984add %l3, %o5, %l3
73985ld [%l3+0], %l6
73986st %l6, [%l3+0]
73987add %l3, %o5, %l3
73988ld [%l3+0], %l6
73989st %l6, [%l3+0]
73990add %l3, %o5, %l3
73991ld [%l3+0], %l6
73992st %l6, [%l3+0]
73993add %l3, %o5, %l3
73994ld [%l3+0], %l6
73995st %l6, [%l3+0]
73996add %l3, %o5, %l3
73997ld [%l3+0], %l6
73998st %l6, [%l3+0]
73999
74000P7069: !_DWLD [8] (Int)
74001sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
74002sub %i0, %i2, %i2
74003ldx [%i2 + 8], %o5
74004! move %o5(lower) -> %o3(lower)
74005srl %o5, 0, %l7
74006or %l7, %o3, %o3
74007
74008P7070: !_PREFETCH [21] (Int)
74009sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
74010sub %i0, %i3, %i3
74011prefetch [%i3 + 0], 31
74012
74013P7071: !_SWAP [7] (maybe <- 0x3800019) (Int)
74014mov %l4, %o4
74015swap [%i2 + 4], %o4
74016! move %o4(lower) -> %o4(upper)
74017sllx %o4, 32, %o4
74018add %l4, 1, %l4
74019
74020P7072: !_DWST [19] (maybe <- 0x380001a) (Int)
74021sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
74022sub %i0, %i2, %i2
74023sllx %l4, 32, %o5
74024add %l4, 1, %l4
74025or %o5, %l4, %o5
74026stx %o5, [%i2 + 0]
74027add %l4, 1, %l4
74028
74029P7073: !_ST_BINIT [0] (maybe <- 0x380001c) (Int)
74030wr %g0, 0xe2, %asi
74031stwa %l4, [%i0 + 0] %asi
74032add %l4, 1, %l4
74033
74034P7074: !_MEMBAR (Int)
74035membar #StoreLoad
74036
74037P7075: !_ST [21] (maybe <- 0x380001d) (Int) (LE)
74038wr %g0, 0x88, %asi
74039! Change single-word-level endianess (big endian <-> little endian)
74040sethi %hi(0xff00ff00), %l7
74041or %l7, %lo(0xff00ff00), %l7
74042and %l4, %l7, %o5
74043srl %o5, 8, %o5
74044sll %l4, 8, %l6
74045and %l6, %l7, %l6
74046or %l6, %o5, %l6
74047srl %l6, 16, %o5
74048sll %l6, 16, %l6
74049srl %l6, 0, %l6
74050or %l6, %o5, %l6
74051stwa %l6, [%i3 + 0] %asi
74052add %l4, 1, %l4
74053
74054P7076: !_ST [4] (maybe <- 0x380001e) (Int)
74055stw %l4, [%i1 + 4 ]
74056add %l4, 1, %l4
74057
74058P7077: !_CAS [18] (maybe <- 0x380001f) (Int)
74059lduw [%i2], %l7
74060mov %l7, %o5
74061! move %o5(lower) -> %o4(lower)
74062or %o5, %o4, %o4
74063!---- flushing int results buffer----
74064mov %o0, %l5
74065mov %o1, %l5
74066mov %o2, %l5
74067mov %o3, %l5
74068mov %o4, %l5
74069mov %l4, %o0
74070cas [%i2], %o5, %o0
74071! move %o0(lower) -> %o0(upper)
74072sllx %o0, 32, %o0
74073add %l4, 1, %l4
74074
74075P7078: !_CASX [20] (maybe <- 0x3800020) (Int)
74076add %i2, 8, %l3
74077ldx [%l3], %l7
74078! move %l7(upper) -> %o0(lower)
74079srlx %l7, 32, %o5
74080or %o5, %o0, %o0
74081! move %l7(lower) -> %o1(upper)
74082sllx %l7, 32, %o1
74083mov %l7, %o5
74084mov %l4, %l7
74085casx [%l3], %o5, %l7
74086! move %l7(upper) -> %o1(lower)
74087srlx %l7, 32, %o5
74088or %o5, %o1, %o1
74089! move %l7(lower) -> %o2(upper)
74090sllx %l7, 32, %o2
74091add %l4, 1, %l4
74092
74093P7079: !_DWST [3] (maybe <- 0x3800021) (Int)
74094!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #1
74095!Logical addr: 3
74096
74097sethi %hi(0x200000), %o5
74098sub %i1, %o5, %i1
74099sllx %l4, 32, %l3
74100add %l4, 1, %l4
74101or %l3, %l4, %l3
74102stx %l3, [%i1 + 0]
74103add %l4, 1, %l4
74104
74105P7080: !_DWLD [6] (Int) (LE)
74106wr %g0, 0x88, %asi
74107sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
74108sub %i0, %i3, %i3
74109ldxa [%i3 + 0] %asi, %l3
74110! move %l3(lower) -> %o2(lower)
74111srl %l3, 0, %o5
74112or %o5, %o2, %o2
74113! move %l3(upper) -> %o3(upper)
74114or %l3, %g0, %o3
74115
74116P7081: !_CASX [3] (maybe <- 0x3800023) (Int)
74117ldx [%i1], %l3
74118! move %l3(upper) -> %o3(lower)
74119srlx %o3, 32, %o3
74120sllx %o3, 32, %o3
74121srlx %l3, 32, %l6
74122or %l6, %o3, %o3
74123! move %l3(lower) -> %o4(upper)
74124sllx %l3, 32, %o4
74125mov %l3, %l6
74126sllx %l4, 32, %l3
74127add %l4, 1, %l4
74128or %l4, %l3, %l3
74129casx [%i1], %l6, %l3
74130! move %l3(upper) -> %o4(lower)
74131srlx %l3, 32, %l6
74132or %l6, %o4, %o4
74133!---- flushing int results buffer----
74134mov %o0, %l5
74135mov %o1, %l5
74136mov %o2, %l5
74137mov %o3, %l5
74138mov %o4, %l5
74139! move %l3(lower) -> %o0(upper)
74140sllx %l3, 32, %o0
74141add %l4, 1, %l4
74142
74143P7082: !_MEMBAR (FP)
74144
74145P7083: !_BSTC [3] (maybe <- 0x43000010) (FP)
74146wr %g0, 0xe0, %asi
74147! preparing store val #0, next val will be in f32
74148fmovs %f16, %f20
74149fadds %f16, %f17, %f16
74150! preparing store val #1, next val will be in f33
74151fmovs %f16, %f21
74152fadds %f16, %f17, %f16
74153! preparing store val #2, next val will be in f35
74154fmovd %f20, %f32
74155fmovs %f16, %f21
74156fadds %f16, %f17, %f16
74157fmovd %f20, %f34
74158membar #Sync
74159stda %f32, [%i1 + 0 ] %asi
74160
74161P7084: !_MEMBAR (FP) (CBR)
74162membar #StoreLoad
74163
74164! cbranch
74165andcc %l0, 1, %g0
74166be,pt %xcc, TARGET7084
74167nop
74168RET7084:
74169
74170! lfsr step begin
74171srlx %l0, 1, %l3
74172xnor %l3, %l0, %l3
74173sllx %l3, 63, %l3
74174or %l3, %l0, %l0
74175srlx %l0, 1, %l0
74176
74177
74178P7085: !_PREFETCH [5] (Int)
74179prefetch [%i1 + 12], 0
74180
74181P7086: !_SWAP [13] (maybe <- 0x3800025) (Int)
74182sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
74183sub %i0, %i2, %i2
74184mov %l4, %o5
74185swap [%i2 + 4], %o5
74186! move %o5(lower) -> %o0(lower)
74187srl %o5, 0, %l6
74188or %l6, %o0, %o0
74189add %l4, 1, %l4
74190
74191P7087: !_SWAP [2] (maybe <- 0x3800026) (Int)
74192mov %l4, %o1
74193swap [%i0 + 12], %o1
74194! move %o1(lower) -> %o1(upper)
74195sllx %o1, 32, %o1
74196add %l4, 1, %l4
74197
74198P7088: !_MEMBAR (FP)
74199membar #StoreLoad
74200
74201P7089: !_BLD [14] (FP)
74202wr %g0, 0xf0, %asi
74203ldda [%i2 + 0] %asi, %f32
74204membar #Sync
74205! 3 addresses covered
74206fmovd %f32, %f18
74207fmovs %f18, %f7
74208fmovs %f19, %f8
74209fmovd %f34, %f18
74210fmovs %f19, %f9
74211
74212P7090: !_MEMBAR (FP) (Branch target of P7997)
74213ba P7091
74214nop
74215
74216TARGET7997:
74217ba RET7997
74218nop
74219
74220
74221P7091: !_SWAP [18] (maybe <- 0x3800027) (Int) (Branch target of P7657)
74222sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
74223sub %i0, %i3, %i3
74224mov %l4, %l6
74225swap [%i3 + 0], %l6
74226! move %l6(lower) -> %o1(lower)
74227srl %l6, 0, %o5
74228or %o5, %o1, %o1
74229add %l4, 1, %l4
74230ba P7092
74231nop
74232
74233TARGET7657:
74234ba RET7657
74235nop
74236
74237
74238P7092: !_DWST_BINIT [19] (maybe <- 0x3800028) (Int) (CBR)
74239wr %g0, 0xe2, %asi
74240sllx %l4, 32, %l7
74241add %l4, 1, %l4
74242or %l7, %l4, %l7
74243stxa %l7, [%i3 + 0] %asi
74244add %l4, 1, %l4
74245
74246! cbranch
74247andcc %l0, 1, %g0
74248be,pt %xcc, TARGET7092
74249nop
74250RET7092:
74251
74252! lfsr step begin
74253srlx %l0, 1, %l6
74254xnor %l6, %l0, %l6
74255sllx %l6, 63, %l6
74256or %l6, %l0, %l0
74257srlx %l0, 1, %l0
74258
74259
74260P7093: !_MEMBAR (Int) (CBR)
74261membar #StoreLoad
74262
74263! cbranch
74264andcc %l0, 1, %g0
74265be,pn %xcc, TARGET7093
74266nop
74267RET7093:
74268
74269! lfsr step begin
74270srlx %l0, 1, %l7
74271xnor %l7, %l0, %l7
74272sllx %l7, 63, %l7
74273or %l7, %l0, %l0
74274srlx %l0, 1, %l0
74275
74276
74277P7094: !_PREFETCH [19] (Int)
74278prefetch [%i3 + 4], 3
74279
74280P7095: !_PREFETCH [11] (Int)
74281sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
74282sub %i0, %i2, %i2
74283prefetch [%i2 + 12], 20
74284
74285P7096: !_MEMBAR (FP)
74286membar #StoreLoad
74287
74288P7097: !_BLD [2] (FP)
74289wr %g0, 0xf0, %asi
74290ldda [%i0 + 0] %asi, %f32
74291membar #Sync
74292! 3 addresses covered
74293fmovd %f32, %f10
74294fmovd %f34, %f18
74295fmovs %f19, %f12
74296
74297P7098: !_MEMBAR (FP)
74298
74299P7099: !_ST_BINIT [14] (maybe <- 0x380002a) (Int)
74300wr %g0, 0xe2, %asi
74301sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
74302sub %i0, %i3, %i3
74303stwa %l4, [%i3 + 12] %asi
74304add %l4, 1, %l4
74305
74306P7100: !_MEMBAR (Int)
74307membar #StoreLoad
74308
74309P7101: !_DWST [16] (maybe <- 0x380002b) (Int)
74310sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
74311add %i0, %i2, %i2
74312sllx %l4, 32, %l7
74313add %l4, 1, %l4
74314or %l7, %l4, %l7
74315stx %l7, [%i2 + 0]
74316add %l4, 1, %l4
74317
74318P7102: !_CAS [3] (maybe <- 0x380002d) (Int)
74319lduw [%i1], %o2
74320mov %o2, %l6
74321! move %l6(lower) -> %o2(upper)
74322sllx %l6, 32, %o2
74323mov %l4, %l3
74324cas [%i1], %l6, %l3
74325! move %l3(lower) -> %o2(lower)
74326srl %l3, 0, %l6
74327or %l6, %o2, %o2
74328add %l4, 1, %l4
74329
74330P7103: !_MEMBAR (FP)
74331
74332P7104: !_BST [8] (maybe <- 0x43000013) (FP)
74333wr %g0, 0xf0, %asi
74334sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
74335sub %i0, %i3, %i3
74336! preparing store val #0, next val will be in f32
74337fmovs %f16, %f20
74338fadds %f16, %f17, %f16
74339! preparing store val #1, next val will be in f33
74340fmovs %f16, %f21
74341fadds %f16, %f17, %f16
74342! preparing store val #2, next val will be in f35
74343fmovd %f20, %f32
74344fmovs %f16, %f21
74345fadds %f16, %f17, %f16
74346fmovd %f20, %f34
74347membar #Sync
74348stda %f32, [%i3 + 0 ] %asi
74349
74350P7105: !_MEMBAR (FP) (Branch target of P7264)
74351membar #StoreLoad
74352ba P7106
74353nop
74354
74355TARGET7264:
74356ba RET7264
74357nop
74358
74359
74360P7106: !_SWAP [13] (maybe <- 0x380002e) (Int)
74361sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
74362sub %i0, %i2, %i2
74363mov %l4, %o3
74364swap [%i2 + 4], %o3
74365! move %o3(lower) -> %o3(upper)
74366sllx %o3, 32, %o3
74367add %l4, 1, %l4
74368
74369P7107: !_REPLACEMENT [2] (Int)
74370sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
74371sub %i0, %i3, %i3
74372sethi %hi(0x20000), %o5
74373ld [%i3+12], %l6
74374st %l6, [%i3+12]
74375add %i3, %o5, %l3
74376ld [%l3+12], %l6
74377st %l6, [%l3+12]
74378add %l3, %o5, %l3
74379ld [%l3+12], %l6
74380st %l6, [%l3+12]
74381add %l3, %o5, %l3
74382ld [%l3+12], %l6
74383st %l6, [%l3+12]
74384add %l3, %o5, %l3
74385ld [%l3+12], %l6
74386st %l6, [%l3+12]
74387add %l3, %o5, %l3
74388ld [%l3+12], %l6
74389st %l6, [%l3+12]
74390add %l3, %o5, %l3
74391ld [%l3+12], %l6
74392st %l6, [%l3+12]
74393add %l3, %o5, %l3
74394ld [%l3+12], %l6
74395st %l6, [%l3+12]
74396
74397P7108: !_MEMBAR (FP)
74398
74399P7109: !_BSTC [10] (maybe <- 0x43000016) (FP)
74400wr %g0, 0xe0, %asi
74401sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
74402sub %i0, %i2, %i2
74403! preparing store val #0, next val will be in f32
74404fmovs %f16, %f20
74405fadds %f16, %f17, %f16
74406! preparing store val #1, next val will be in f33
74407fmovs %f16, %f21
74408fadds %f16, %f17, %f16
74409! preparing store val #2, next val will be in f35
74410fmovd %f20, %f32
74411fmovs %f16, %f21
74412fadds %f16, %f17, %f16
74413fmovd %f20, %f34
74414membar #Sync
74415stda %f32, [%i2 + 0 ] %asi
74416
74417P7110: !_MEMBAR (FP)
74418membar #StoreLoad
74419
74420P7111: !_LDD [21] (Int) (CBR)
74421sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
74422sub %i0, %i3, %i3
74423ldd [%i3 + 0], %l6
74424! move %l6(lower) -> %o3(lower)
74425or %l6, %o3, %o3
74426! move %l7(lower) -> %o4(upper)
74427sllx %l7, 32, %o4
74428
74429! cbranch
74430andcc %l0, 1, %g0
74431be,pt %xcc, TARGET7111
74432nop
74433RET7111:
74434
74435! lfsr step begin
74436srlx %l0, 1, %l3
74437xnor %l3, %l0, %l3
74438sllx %l3, 63, %l3
74439or %l3, %l0, %l0
74440srlx %l0, 1, %l0
74441
74442
74443P7112: !_REPLACEMENT [19] (Int)
74444sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
74445add %i0, %i2, %i2
74446sethi %hi(0x20000), %l6
74447ld [%i2+4], %o5
74448st %o5, [%i2+4]
74449add %i2, %l6, %l7
74450ld [%l7+4], %o5
74451st %o5, [%l7+4]
74452add %l7, %l6, %l7
74453ld [%l7+4], %o5
74454st %o5, [%l7+4]
74455add %l7, %l6, %l7
74456ld [%l7+4], %o5
74457st %o5, [%l7+4]
74458add %l7, %l6, %l7
74459ld [%l7+4], %o5
74460st %o5, [%l7+4]
74461add %l7, %l6, %l7
74462ld [%l7+4], %o5
74463st %o5, [%l7+4]
74464add %l7, %l6, %l7
74465ld [%l7+4], %o5
74466st %o5, [%l7+4]
74467add %l7, %l6, %l7
74468ld [%l7+4], %o5
74469st %o5, [%l7+4]
74470
74471P7113: !_DWST [23] (maybe <- 0x380002f) (Int) (Branch target of P7962)
74472mov %l4, %l3
74473stx %l3, [%i3 + 8]
74474add %l4, 1, %l4
74475ba P7114
74476nop
74477
74478TARGET7962:
74479ba RET7962
74480nop
74481
74482
74483P7114: !_CASX [13] (maybe <- 0x3800030) (Int) (LE)
74484sllx %l4, 32, %l3
74485add %l4, 1, %l4
74486or %l4, %l3, %l3
74487! Change double-word-level endianess (big endian <-> little endian)
74488sethi %hi(0xff00ff00), %o5
74489or %o5, %lo(0xff00ff00), %o5
74490sllx %o5, 32, %l6
74491or %o5, %l6, %o5
74492and %l3, %o5, %l6
74493srlx %l6, 8, %l6
74494sllx %l3, 8, %l3
74495and %l3, %o5, %l3
74496or %l3, %l6, %l3
74497sethi %hi(0xffff0000), %o5
74498srlx %l3, 16, %l6
74499andn %l6, %o5, %l6
74500andn %l3, %o5, %l3
74501sllx %l3, 16, %l3
74502or %l3, %l6, %l3
74503srlx %l3, 32, %l6
74504sllx %l3, 32, %l3
74505or %l3, %l6, %l6
74506wr %g0, 0x88, %asi
74507sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
74508sub %i0, %i3, %i3
74509ldxa [%i3] %asi, %l7
74510! move %l7(lower) -> %o4(lower)
74511srl %l7, 0, %o5
74512or %o5, %o4, %o4
74513!---- flushing int results buffer----
74514mov %o0, %l5
74515mov %o1, %l5
74516mov %o2, %l5
74517mov %o3, %l5
74518mov %o4, %l5
74519! move %l7(upper) -> %o0(upper)
74520or %l7, %g0, %o0
74521mov %l7, %o5
74522mov %l6, %l7
74523casxa [%i3] %asi, %o5, %l7
74524! move %l7(lower) -> %o0(lower)
74525srlx %o0, 32, %o0
74526sllx %o0, 32, %o0
74527srl %l7, 0, %o5
74528or %o5, %o0, %o0
74529! move %l7(upper) -> %o1(upper)
74530or %l7, %g0, %o1
74531add %l4, 1, %l4
74532
74533P7115: !_ST [23] (maybe <- 0x3800032) (Int)
74534sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
74535sub %i0, %i2, %i2
74536stw %l4, [%i2 + 12 ]
74537add %l4, 1, %l4
74538
74539P7116: !_PREFETCH [7] (Int)
74540sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
74541sub %i0, %i3, %i3
74542prefetch [%i3 + 4], 0
74543
74544P7117: !_LD [6] (Int)
74545lduw [%i3 + 0], %o5
74546! move %o5(lower) -> %o1(lower)
74547srlx %o1, 32, %o1
74548sllx %o1, 32, %o1
74549or %o5, %o1, %o1
74550
74551P7118: !_SWAP [20] (maybe <- 0x3800033) (Int)
74552sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
74553sub %i0, %i2, %i2
74554mov %l4, %o2
74555swap [%i2 + 12], %o2
74556! move %o2(lower) -> %o2(upper)
74557sllx %o2, 32, %o2
74558add %l4, 1, %l4
74559
74560P7119: !_MEMBAR (FP)
74561
74562P7120: !_BSTC [21] (maybe <- 0x43000019) (FP)
74563wr %g0, 0xe0, %asi
74564sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
74565sub %i0, %i3, %i3
74566! preparing store val #0, next val will be in f32
74567fmovs %f16, %f20
74568fadds %f16, %f17, %f16
74569! preparing store val #1, next val will be in f33
74570fmovs %f16, %f21
74571fadds %f16, %f17, %f16
74572! preparing store val #2, next val will be in f35
74573fmovd %f20, %f32
74574fmovs %f16, %f21
74575fadds %f16, %f17, %f16
74576fmovd %f20, %f34
74577membar #Sync
74578stda %f32, [%i3 + 0 ] %asi
74579
74580P7121: !_MEMBAR (FP)
74581membar #StoreLoad
74582
74583P7122: !_DWST [9] (maybe <- 0x3800034) (Int)
74584sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
74585sub %i0, %i2, %i2
74586sllx %l4, 32, %l7
74587add %l4, 1, %l4
74588or %l7, %l4, %l7
74589stx %l7, [%i2 + 0]
74590add %l4, 1, %l4
74591
74592P7123: !_DWST [5] (maybe <- 0x3800036) (Int)
74593mov %l4, %l6
74594stx %l6, [%i1 + 8]
74595add %l4, 1, %l4
74596
74597P7124: !_REPLACEMENT [13] (Int)
74598sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
74599add %i0, %i3, %i3
74600sethi %hi(0x20000), %l3
74601ld [%i3+4], %l7
74602st %l7, [%i3+4]
74603add %i3, %l3, %l6
74604ld [%l6+4], %l7
74605st %l7, [%l6+4]
74606add %l6, %l3, %l6
74607ld [%l6+4], %l7
74608st %l7, [%l6+4]
74609add %l6, %l3, %l6
74610ld [%l6+4], %l7
74611st %l7, [%l6+4]
74612add %l6, %l3, %l6
74613ld [%l6+4], %l7
74614st %l7, [%l6+4]
74615add %l6, %l3, %l6
74616ld [%l6+4], %l7
74617st %l7, [%l6+4]
74618add %l6, %l3, %l6
74619ld [%l6+4], %l7
74620st %l7, [%l6+4]
74621add %l6, %l3, %l6
74622ld [%l6+4], %l7
74623st %l7, [%l6+4]
74624
74625P7125: !_MEMBAR (FP)
74626
74627P7126: !_BST [18] (maybe <- 0x4300001c) (FP)
74628wr %g0, 0xf0, %asi
74629sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
74630sub %i0, %i2, %i2
74631! preparing store val #0, next val will be in f32
74632fmovs %f16, %f20
74633fadds %f16, %f17, %f16
74634! preparing store val #1, next val will be in f33
74635fmovs %f16, %f21
74636fadds %f16, %f17, %f16
74637! preparing store val #2, next val will be in f35
74638fmovd %f20, %f32
74639fmovs %f16, %f21
74640fadds %f16, %f17, %f16
74641fmovd %f20, %f34
74642membar #Sync
74643stda %f32, [%i2 + 0 ] %asi
74644
74645P7127: !_MEMBAR (FP)
74646membar #StoreLoad
74647
74648P7128: !_PREFETCH [17] (Int)
74649sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
74650add %i0, %i3, %i3
74651prefetch [%i3 + 12], 22
74652
74653P7129: !_DWST_BINIT [23] (maybe <- 0x3800037) (Int)
74654wr %g0, 0xe2, %asi
74655sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
74656sub %i0, %i2, %i2
74657mov %l4, %l7
74658stxa %l7, [%i2 + 8] %asi
74659add %l4, 1, %l4
74660
74661P7130: !_MEMBAR (Int)
74662membar #StoreLoad
74663
74664P7131: !_ST_BINIT [7] (maybe <- 0x3800038) (Int)
74665wr %g0, 0xe2, %asi
74666sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
74667sub %i0, %i3, %i3
74668stwa %l4, [%i3 + 4] %asi
74669add %l4, 1, %l4
74670
74671P7132: !_MEMBAR (Int)
74672membar #StoreLoad
74673
74674P7133: !_BLD [23] (FP)
74675wr %g0, 0xf0, %asi
74676ldda [%i2 + 0] %asi, %f32
74677membar #Sync
74678! 3 addresses covered
74679fmovd %f32, %f18
74680fmovs %f18, %f13
74681fmovs %f19, %f14
74682fmovd %f34, %f18
74683fmovs %f19, %f15
74684!---- flushing fp results buffer to %f30 ----
74685fmovd %f0, %f30
74686fmovd %f2, %f30
74687fmovd %f4, %f30
74688fmovd %f6, %f30
74689fmovd %f8, %f30
74690fmovd %f10, %f30
74691fmovd %f12, %f30
74692fmovd %f14, %f30
74693!--
74694
74695P7134: !_MEMBAR (FP)
74696
74697P7135: !_DWST [10] (maybe <- 0x3800039) (Int)
74698sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
74699sub %i0, %i2, %i2
74700sllx %l4, 32, %l3
74701add %l4, 1, %l4
74702or %l3, %l4, %l3
74703stx %l3, [%i2 + 0]
74704add %l4, 1, %l4
74705
74706P7136: !_CAS [23] (maybe <- 0x380003b) (Int)
74707sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
74708sub %i0, %i3, %i3
74709add %i3, 12, %l3
74710lduw [%l3], %l7
74711mov %l7, %o5
74712! move %o5(lower) -> %o2(lower)
74713or %o5, %o2, %o2
74714mov %l4, %o3
74715cas [%l3], %o5, %o3
74716! move %o3(lower) -> %o3(upper)
74717sllx %o3, 32, %o3
74718add %l4, 1, %l4
74719
74720P7137: !_DWLD [3] (Int)
74721ldx [%i1 + 0], %l3
74722! move %l3(upper) -> %o3(lower)
74723srlx %l3, 32, %o5
74724or %o5, %o3, %o3
74725! move %l3(lower) -> %o4(upper)
74726sllx %l3, 32, %o4
74727
74728P7138: !_LD [5] (Int)
74729lduw [%i1 + 12], %l7
74730! move %l7(lower) -> %o4(lower)
74731or %l7, %o4, %o4
74732!---- flushing int results buffer----
74733mov %o0, %l5
74734mov %o1, %l5
74735mov %o2, %l5
74736mov %o3, %l5
74737mov %o4, %l5
74738
74739P7139: !_CAS [10] (maybe <- 0x380003c) (Int) (Branch target of P7985)
74740add %i2, 4, %l3
74741lduw [%l3], %o0
74742mov %o0, %o5
74743! move %o5(lower) -> %o0(upper)
74744sllx %o5, 32, %o0
74745mov %l4, %l7
74746cas [%l3], %o5, %l7
74747! move %l7(lower) -> %o0(lower)
74748srl %l7, 0, %o5
74749or %o5, %o0, %o0
74750add %l4, 1, %l4
74751ba P7140
74752nop
74753
74754TARGET7985:
74755ba RET7985
74756nop
74757
74758
74759P7140: !_CAS [1] (maybe <- 0x380003d) (Int)
74760add %i0, 4, %l3
74761lduw [%l3], %o1
74762mov %o1, %o5
74763! move %o5(lower) -> %o1(upper)
74764sllx %o5, 32, %o1
74765mov %l4, %l7
74766cas [%l3], %o5, %l7
74767! move %l7(lower) -> %o1(lower)
74768srl %l7, 0, %o5
74769or %o5, %o1, %o1
74770add %l4, 1, %l4
74771
74772P7141: !_DWST_BINIT [7] (maybe <- 0x380003e) (Int)
74773wr %g0, 0xe2, %asi
74774sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
74775sub %i0, %i2, %i2
74776sllx %l4, 32, %o5
74777add %l4, 1, %l4
74778or %o5, %l4, %o5
74779stxa %o5, [%i2 + 0] %asi
74780add %l4, 1, %l4
74781
74782P7142: !_MEMBAR (Int)
74783membar #StoreLoad
74784
74785P7143: !_ST_BINIT [4] (maybe <- 0x3800040) (Int)
74786!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #2
74787!Logical addr: 4
74788
74789sethi %hi(0x200000), %l7
74790sub %i1, %l7, %i1
74791wr %g0, 0xe2, %asi
74792stwa %l4, [%i1 + 4] %asi
74793add %l4, 1, %l4
74794
74795P7144: !_MEMBAR (Int)
74796membar #StoreLoad
74797
74798P7145: !_PREFETCH [15] (Int)
74799sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
74800add %i0, %i3, %i3
74801prefetch [%i3 + 0], 2
74802
74803P7146: !_ST [10] (maybe <- 0x3800041) (Int)
74804sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
74805sub %i0, %i2, %i2
74806stw %l4, [%i2 + 4 ]
74807add %l4, 1, %l4
74808
74809P7147: !_SWAP [14] (maybe <- 0x3800042) (Int)
74810sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
74811sub %i0, %i3, %i3
74812mov %l4, %o2
74813swap [%i3 + 12], %o2
74814! move %o2(lower) -> %o2(upper)
74815sllx %o2, 32, %o2
74816add %l4, 1, %l4
74817
74818P7148: !_CASX [15] (maybe <- 0x3800043) (Int)
74819sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
74820add %i0, %i2, %i2
74821ldx [%i2], %o5
74822! move %o5(upper) -> %o2(lower)
74823srlx %o5, 32, %l3
74824or %l3, %o2, %o2
74825! move %o5(lower) -> %o3(upper)
74826sllx %o5, 32, %o3
74827mov %o5, %l3
74828sllx %l4, 32, %o5
74829add %l4, 1, %l4
74830or %l4, %o5, %o5
74831casx [%i2], %l3, %o5
74832! move %o5(upper) -> %o3(lower)
74833srlx %o5, 32, %l3
74834or %l3, %o3, %o3
74835! move %o5(lower) -> %o4(upper)
74836sllx %o5, 32, %o4
74837add %l4, 1, %l4
74838
74839P7149: !_LD [22] (Int)
74840sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
74841sub %i0, %i3, %i3
74842lduw [%i3 + 4], %l6
74843! move %l6(lower) -> %o4(lower)
74844or %l6, %o4, %o4
74845!---- flushing int results buffer----
74846mov %o0, %l5
74847mov %o1, %l5
74848mov %o2, %l5
74849mov %o3, %l5
74850mov %o4, %l5
74851
74852P7150: !_MEMBAR (FP)
74853
74854P7151: !_BSTC [19] (maybe <- 0x4300001f) (FP)
74855wr %g0, 0xe0, %asi
74856sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
74857sub %i0, %i2, %i2
74858! preparing store val #0, next val will be in f32
74859fmovs %f16, %f20
74860fadds %f16, %f17, %f16
74861! preparing store val #1, next val will be in f33
74862fmovs %f16, %f21
74863fadds %f16, %f17, %f16
74864! preparing store val #2, next val will be in f35
74865fmovd %f20, %f32
74866fmovs %f16, %f21
74867fadds %f16, %f17, %f16
74868fmovd %f20, %f34
74869membar #Sync
74870stda %f32, [%i2 + 0 ] %asi
74871
74872P7152: !_MEMBAR (FP)
74873membar #StoreLoad
74874
74875P7153: !_REPLACEMENT [9] (Int)
74876sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
74877sub %i0, %i3, %i3
74878sethi %hi(0x20000), %l6
74879ld [%i3+0], %o5
74880st %o5, [%i3+0]
74881add %i3, %l6, %l7
74882ld [%l7+0], %o5
74883st %o5, [%l7+0]
74884add %l7, %l6, %l7
74885ld [%l7+0], %o5
74886st %o5, [%l7+0]
74887add %l7, %l6, %l7
74888ld [%l7+0], %o5
74889st %o5, [%l7+0]
74890add %l7, %l6, %l7
74891ld [%l7+0], %o5
74892st %o5, [%l7+0]
74893add %l7, %l6, %l7
74894ld [%l7+0], %o5
74895st %o5, [%l7+0]
74896add %l7, %l6, %l7
74897ld [%l7+0], %o5
74898st %o5, [%l7+0]
74899add %l7, %l6, %l7
74900ld [%l7+0], %o5
74901st %o5, [%l7+0]
74902
74903P7154: !_CAS [22] (maybe <- 0x3800045) (Int)
74904sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
74905sub %i0, %i2, %i2
74906add %i2, 4, %l6
74907lduw [%l6], %o0
74908mov %o0, %l3
74909! move %l3(lower) -> %o0(upper)
74910sllx %l3, 32, %o0
74911mov %l4, %o5
74912cas [%l6], %l3, %o5
74913! move %o5(lower) -> %o0(lower)
74914srl %o5, 0, %l3
74915or %l3, %o0, %o0
74916add %l4, 1, %l4
74917
74918P7155: !_MEMBAR (FP)
74919membar #StoreLoad
74920
74921P7156: !_BLD [6] (FP)
74922wr %g0, 0xf0, %asi
74923sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
74924sub %i0, %i3, %i3
74925ldda [%i3 + 0] %asi, %f0
74926membar #Sync
74927! 3 addresses covered
74928fmovs %f3, %f2
74929
74930P7157: !_MEMBAR (FP)
74931
74932P7158: !_SWAP [22] (maybe <- 0x3800046) (Int)
74933mov %l4, %o1
74934swap [%i2 + 4], %o1
74935! move %o1(lower) -> %o1(upper)
74936sllx %o1, 32, %o1
74937add %l4, 1, %l4
74938
74939P7159: !_SWAP [16] (maybe <- 0x3800047) (Int)
74940sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
74941add %i0, %i2, %i2
74942mov %l4, %l6
74943swap [%i2 + 4], %l6
74944! move %l6(lower) -> %o1(lower)
74945srl %l6, 0, %o5
74946or %o5, %o1, %o1
74947add %l4, 1, %l4
74948
74949P7160: !_LDD [16] (Int)
74950ldd [%i2 + 0], %l6
74951! move %l6(lower) -> %o2(upper)
74952sllx %l6, 32, %o2
74953! move %l7(lower) -> %o2(lower)
74954or %l7, %o2, %o2
74955
74956P7161: !_DWLD [3] (Int) (CBR) (Branch target of P7111)
74957ldx [%i1 + 0], %o3
74958! move %o3(upper) -> %o3(upper)
74959! move %o3(lower) -> %o3(lower)
74960
74961! cbranch
74962andcc %l0, 1, %g0
74963be,pn %xcc, TARGET7161
74964nop
74965RET7161:
74966
74967! lfsr step begin
74968srlx %l0, 1, %l7
74969xnor %l7, %l0, %l7
74970sllx %l7, 63, %l7
74971or %l7, %l0, %l0
74972srlx %l0, 1, %l0
74973
74974ba P7162
74975nop
74976
74977TARGET7111:
74978ba RET7111
74979nop
74980
74981
74982P7162: !_CAS [5] (maybe <- 0x3800048) (Int)
74983add %i1, 12, %l3
74984lduw [%l3], %o4
74985mov %o4, %o5
74986! move %o5(lower) -> %o4(upper)
74987sllx %o5, 32, %o4
74988mov %l4, %l7
74989cas [%l3], %o5, %l7
74990! move %l7(lower) -> %o4(lower)
74991srl %l7, 0, %o5
74992or %o5, %o4, %o4
74993!---- flushing int results buffer----
74994mov %o0, %l5
74995mov %o1, %l5
74996mov %o2, %l5
74997mov %o3, %l5
74998mov %o4, %l5
74999add %l4, 1, %l4
75000
75001P7163: !_SWAP [21] (maybe <- 0x3800049) (Int)
75002sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
75003sub %i0, %i3, %i3
75004mov %l4, %o0
75005swap [%i3 + 0], %o0
75006! move %o0(lower) -> %o0(upper)
75007sllx %o0, 32, %o0
75008add %l4, 1, %l4
75009
75010P7164: !_DWST_BINIT [6] (maybe <- 0x380004a) (Int)
75011wr %g0, 0xe2, %asi
75012sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
75013sub %i0, %i2, %i2
75014sllx %l4, 32, %l7
75015add %l4, 1, %l4
75016or %l7, %l4, %l7
75017stxa %l7, [%i2 + 0] %asi
75018add %l4, 1, %l4
75019
75020P7165: !_MEMBAR (Int)
75021
75022P7166: !_BSTC [14] (maybe <- 0x43000022) (FP)
75023wr %g0, 0xe0, %asi
75024sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
75025sub %i0, %i3, %i3
75026! preparing store val #0, next val will be in f32
75027fmovs %f16, %f20
75028fadds %f16, %f17, %f16
75029! preparing store val #1, next val will be in f33
75030fmovs %f16, %f21
75031fadds %f16, %f17, %f16
75032! preparing store val #2, next val will be in f35
75033fmovd %f20, %f32
75034fmovs %f16, %f21
75035fadds %f16, %f17, %f16
75036fmovd %f20, %f34
75037membar #Sync
75038stda %f32, [%i3 + 0 ] %asi
75039
75040P7167: !_MEMBAR (FP)
75041
75042P7168: !_BSTC [5] (maybe <- 0x43000025) (FP)
75043wr %g0, 0xe0, %asi
75044! preparing store val #0, next val will be in f32
75045fmovs %f16, %f20
75046fadds %f16, %f17, %f16
75047! preparing store val #1, next val will be in f33
75048fmovs %f16, %f21
75049fadds %f16, %f17, %f16
75050! preparing store val #2, next val will be in f35
75051fmovd %f20, %f32
75052fmovs %f16, %f21
75053fadds %f16, %f17, %f16
75054fmovd %f20, %f34
75055membar #Sync
75056stda %f32, [%i1 + 0 ] %asi
75057
75058P7169: !_MEMBAR (FP)
75059membar #StoreLoad
75060
75061P7170: !_DWLD [2] (Int)
75062ldx [%i0 + 8], %l3
75063! move %l3(lower) -> %o0(lower)
75064srl %l3, 0, %o5
75065or %o5, %o0, %o0
75066
75067P7171: !_CASX [18] (maybe <- 0x380004c) (Int)
75068sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
75069sub %i0, %i2, %i2
75070ldx [%i2], %o1
75071! move %o1(upper) -> %o1(upper)
75072! move %o1(lower) -> %o1(lower)
75073mov %o1, %l6
75074sllx %l4, 32, %o2
75075add %l4, 1, %l4
75076or %l4, %o2, %o2
75077casx [%i2], %l6, %o2
75078! move %o2(upper) -> %o2(upper)
75079! move %o2(lower) -> %o2(lower)
75080add %l4, 1, %l4
75081
75082P7172: !_CASX [12] (maybe <- 0x380004e) (Int)
75083ldx [%i3], %o3
75084! move %o3(upper) -> %o3(upper)
75085! move %o3(lower) -> %o3(lower)
75086mov %o3, %l6
75087sllx %l4, 32, %o4
75088add %l4, 1, %l4
75089or %l4, %o4, %o4
75090casx [%i3], %l6, %o4
75091! move %o4(upper) -> %o4(upper)
75092! move %o4(lower) -> %o4(lower)
75093!---- flushing int results buffer----
75094mov %o0, %l5
75095mov %o1, %l5
75096mov %o2, %l5
75097mov %o3, %l5
75098mov %o4, %l5
75099add %l4, 1, %l4
75100
75101P7173: !_CAS [18] (maybe <- 0x3800050) (Int)
75102lduw [%i2], %o0
75103mov %o0, %l6
75104! move %l6(lower) -> %o0(upper)
75105sllx %l6, 32, %o0
75106mov %l4, %l3
75107cas [%i2], %l6, %l3
75108! move %l3(lower) -> %o0(lower)
75109srl %l3, 0, %l6
75110or %l6, %o0, %o0
75111add %l4, 1, %l4
75112
75113P7174: !_MEMBAR (FP) (CBR)
75114
75115! cbranch
75116andcc %l0, 1, %g0
75117be,pn %xcc, TARGET7174
75118nop
75119RET7174:
75120
75121! lfsr step begin
75122srlx %l0, 1, %l6
75123xnor %l6, %l0, %l6
75124sllx %l6, 63, %l6
75125or %l6, %l0, %l0
75126srlx %l0, 1, %l0
75127
75128
75129P7175: !_BST [15] (maybe <- 0x43000028) (FP)
75130wr %g0, 0xf0, %asi
75131sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
75132add %i0, %i3, %i3
75133! preparing store val #0, next val will be in f32
75134fmovs %f16, %f20
75135fadds %f16, %f17, %f16
75136! preparing store val #1, next val will be in f33
75137fmovs %f16, %f21
75138fadds %f16, %f17, %f16
75139! preparing store val #2, next val will be in f35
75140fmovd %f20, %f32
75141fmovs %f16, %f21
75142fadds %f16, %f17, %f16
75143fmovd %f20, %f34
75144membar #Sync
75145stda %f32, [%i3 + 0 ] %asi
75146
75147P7176: !_MEMBAR (FP)
75148membar #StoreLoad
75149
75150P7177: !_REPLACEMENT [9] (Int)
75151sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
75152sub %i0, %i2, %i2
75153sethi %hi(0x20000), %l6
75154ld [%i2+0], %o5
75155st %o5, [%i2+0]
75156add %i2, %l6, %l7
75157ld [%l7+0], %o5
75158st %o5, [%l7+0]
75159add %l7, %l6, %l7
75160ld [%l7+0], %o5
75161st %o5, [%l7+0]
75162add %l7, %l6, %l7
75163ld [%l7+0], %o5
75164st %o5, [%l7+0]
75165add %l7, %l6, %l7
75166ld [%l7+0], %o5
75167st %o5, [%l7+0]
75168add %l7, %l6, %l7
75169ld [%l7+0], %o5
75170st %o5, [%l7+0]
75171add %l7, %l6, %l7
75172ld [%l7+0], %o5
75173st %o5, [%l7+0]
75174add %l7, %l6, %l7
75175ld [%l7+0], %o5
75176st %o5, [%l7+0]
75177
75178P7178: !_MEMBAR (FP)
75179
75180P7179: !_BST [12] (maybe <- 0x4300002b) (FP)
75181wr %g0, 0xf0, %asi
75182sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
75183sub %i0, %i3, %i3
75184! preparing store val #0, next val will be in f32
75185fmovs %f16, %f20
75186fadds %f16, %f17, %f16
75187! preparing store val #1, next val will be in f33
75188fmovs %f16, %f21
75189fadds %f16, %f17, %f16
75190! preparing store val #2, next val will be in f35
75191fmovd %f20, %f32
75192fmovs %f16, %f21
75193fadds %f16, %f17, %f16
75194fmovd %f20, %f34
75195membar #Sync
75196stda %f32, [%i3 + 0 ] %asi
75197
75198P7180: !_MEMBAR (FP)
75199
75200P7181: !_BST [4] (maybe <- 0x4300002e) (FP)
75201wr %g0, 0xf0, %asi
75202! preparing store val #0, next val will be in f32
75203fmovs %f16, %f20
75204fadds %f16, %f17, %f16
75205! preparing store val #1, next val will be in f33
75206fmovs %f16, %f21
75207fadds %f16, %f17, %f16
75208! preparing store val #2, next val will be in f35
75209fmovd %f20, %f32
75210fmovs %f16, %f21
75211fadds %f16, %f17, %f16
75212fmovd %f20, %f34
75213membar #Sync
75214stda %f32, [%i1 + 0 ] %asi
75215
75216P7182: !_MEMBAR (FP) (Branch target of P7093)
75217ba P7183
75218nop
75219
75220TARGET7093:
75221ba RET7093
75222nop
75223
75224
75225P7183: !_BSTC [9] (maybe <- 0x43000031) (FP)
75226wr %g0, 0xe0, %asi
75227sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
75228sub %i0, %i2, %i2
75229! preparing store val #0, next val will be in f32
75230fmovs %f16, %f20
75231fadds %f16, %f17, %f16
75232! preparing store val #1, next val will be in f33
75233fmovs %f16, %f21
75234fadds %f16, %f17, %f16
75235! preparing store val #2, next val will be in f35
75236fmovd %f20, %f32
75237fmovs %f16, %f21
75238fadds %f16, %f17, %f16
75239fmovd %f20, %f34
75240membar #Sync
75241stda %f32, [%i2 + 0 ] %asi
75242
75243P7184: !_MEMBAR (FP)
75244membar #StoreLoad
75245
75246P7185: !_LDD [8] (Int)
75247sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
75248sub %i0, %i3, %i3
75249ldd [%i3 + 8], %l6
75250! move %l7(lower) -> %o1(upper)
75251sllx %l7, 32, %o1
75252
75253P7186: !_DWST [1] (maybe <- 0x3800051) (Int) (Branch target of P7360)
75254sllx %l4, 32, %l3
75255add %l4, 1, %l4
75256or %l3, %l4, %l3
75257stx %l3, [%i0 + 0]
75258add %l4, 1, %l4
75259ba P7187
75260nop
75261
75262TARGET7360:
75263ba RET7360
75264nop
75265
75266
75267P7187: !_MEMBAR (FP)
75268
75269P7188: !_BST [12] (maybe <- 0x43000034) (FP)
75270wr %g0, 0xf0, %asi
75271sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
75272sub %i0, %i2, %i2
75273! preparing store val #0, next val will be in f32
75274fmovs %f16, %f20
75275fadds %f16, %f17, %f16
75276! preparing store val #1, next val will be in f33
75277fmovs %f16, %f21
75278fadds %f16, %f17, %f16
75279! preparing store val #2, next val will be in f35
75280fmovd %f20, %f32
75281fmovs %f16, %f21
75282fadds %f16, %f17, %f16
75283fmovd %f20, %f34
75284membar #Sync
75285stda %f32, [%i2 + 0 ] %asi
75286
75287P7189: !_MEMBAR (FP)
75288membar #StoreLoad
75289
75290P7190: !_ST_BINIT [9] (maybe <- 0x3800053) (Int)
75291wr %g0, 0xe2, %asi
75292sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
75293sub %i0, %i3, %i3
75294stwa %l4, [%i3 + 0] %asi
75295add %l4, 1, %l4
75296
75297P7191: !_MEMBAR (Int)
75298membar #StoreLoad
75299
75300P7192: !_LD [15] (Int)
75301sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
75302add %i0, %i2, %i2
75303lduw [%i2 + 0], %l7
75304! move %l7(lower) -> %o1(lower)
75305or %l7, %o1, %o1
75306
75307P7193: !_MEMBAR (FP) (Branch target of P7674)
75308ba P7194
75309nop
75310
75311TARGET7674:
75312ba RET7674
75313nop
75314
75315
75316P7194: !_BSTC [3] (maybe <- 0x43000037) (FP)
75317wr %g0, 0xe0, %asi
75318! preparing store val #0, next val will be in f32
75319fmovs %f16, %f20
75320fadds %f16, %f17, %f16
75321! preparing store val #1, next val will be in f33
75322fmovs %f16, %f21
75323fadds %f16, %f17, %f16
75324! preparing store val #2, next val will be in f35
75325fmovd %f20, %f32
75326fmovs %f16, %f21
75327fadds %f16, %f17, %f16
75328fmovd %f20, %f34
75329membar #Sync
75330stda %f32, [%i1 + 0 ] %asi
75331
75332P7195: !_MEMBAR (FP)
75333membar #StoreLoad
75334
75335P7196: !_LD [4] (Int)
75336lduw [%i1 + 4], %o2
75337! move %o2(lower) -> %o2(upper)
75338sllx %o2, 32, %o2
75339
75340P7197: !_MEMBAR (FP)
75341
75342P7198: !_BST [20] (maybe <- 0x4300003a) (FP)
75343wr %g0, 0xf0, %asi
75344sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
75345sub %i0, %i3, %i3
75346! preparing store val #0, next val will be in f32
75347fmovs %f16, %f20
75348fadds %f16, %f17, %f16
75349! preparing store val #1, next val will be in f33
75350fmovs %f16, %f21
75351fadds %f16, %f17, %f16
75352! preparing store val #2, next val will be in f35
75353fmovd %f20, %f32
75354fmovs %f16, %f21
75355fadds %f16, %f17, %f16
75356fmovd %f20, %f34
75357membar #Sync
75358stda %f32, [%i3 + 0 ] %asi
75359
75360P7199: !_MEMBAR (FP)
75361membar #StoreLoad
75362
75363P7200: !_LD [3] (Int)
75364lduw [%i1 + 0], %l3
75365! move %l3(lower) -> %o2(lower)
75366or %l3, %o2, %o2
75367
75368P7201: !_MEMBAR (FP)
75369
75370P7202: !_BST [8] (maybe <- 0x4300003d) (FP)
75371wr %g0, 0xf0, %asi
75372sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
75373sub %i0, %i2, %i2
75374! preparing store val #0, next val will be in f32
75375fmovs %f16, %f20
75376fadds %f16, %f17, %f16
75377! preparing store val #1, next val will be in f33
75378fmovs %f16, %f21
75379fadds %f16, %f17, %f16
75380! preparing store val #2, next val will be in f35
75381fmovd %f20, %f32
75382fmovs %f16, %f21
75383fadds %f16, %f17, %f16
75384fmovd %f20, %f34
75385membar #Sync
75386stda %f32, [%i2 + 0 ] %asi
75387
75388P7203: !_MEMBAR (FP)
75389membar #StoreLoad
75390
75391P7204: !_REPLACEMENT [18] (Int)
75392sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
75393sub %i0, %i3, %i3
75394sethi %hi(0x20000), %l3
75395ld [%i3+0], %l7
75396st %l7, [%i3+0]
75397add %i3, %l3, %l6
75398ld [%l6+0], %l7
75399st %l7, [%l6+0]
75400add %l6, %l3, %l6
75401ld [%l6+0], %l7
75402st %l7, [%l6+0]
75403add %l6, %l3, %l6
75404ld [%l6+0], %l7
75405st %l7, [%l6+0]
75406add %l6, %l3, %l6
75407ld [%l6+0], %l7
75408st %l7, [%l6+0]
75409add %l6, %l3, %l6
75410ld [%l6+0], %l7
75411st %l7, [%l6+0]
75412add %l6, %l3, %l6
75413ld [%l6+0], %l7
75414st %l7, [%l6+0]
75415add %l6, %l3, %l6
75416ld [%l6+0], %l7
75417st %l7, [%l6+0]
75418
75419P7205: !_DWST [20] (maybe <- 0x3800054) (Int)
75420sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
75421sub %i0, %i2, %i2
75422mov %l4, %o5
75423stx %o5, [%i2 + 8]
75424add %l4, 1, %l4
75425
75426P7206: !_PREFETCH [18] (Int)
75427prefetch [%i2 + 0], 20
75428
75429P7207: !_MEMBAR (FP)
75430
75431P7208: !_BSTC [19] (maybe <- 0x43000040) (FP)
75432wr %g0, 0xe0, %asi
75433! preparing store val #0, next val will be in f32
75434fmovs %f16, %f20
75435fadds %f16, %f17, %f16
75436! preparing store val #1, next val will be in f33
75437fmovs %f16, %f21
75438fadds %f16, %f17, %f16
75439! preparing store val #2, next val will be in f35
75440fmovd %f20, %f32
75441fmovs %f16, %f21
75442fadds %f16, %f17, %f16
75443fmovd %f20, %f34
75444membar #Sync
75445stda %f32, [%i2 + 0 ] %asi
75446
75447P7209: !_MEMBAR (FP)
75448membar #StoreLoad
75449
75450P7210: !_DWST [19] (maybe <- 0x3800055) (Int)
75451sllx %l4, 32, %l7
75452add %l4, 1, %l4
75453or %l7, %l4, %l7
75454stx %l7, [%i2 + 0]
75455add %l4, 1, %l4
75456
75457P7211: !_MEMBAR (FP)
75458
75459P7212: !_BST [16] (maybe <- 0x43000043) (FP)
75460wr %g0, 0xf0, %asi
75461sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
75462add %i0, %i3, %i3
75463! preparing store val #0, next val will be in f32
75464fmovs %f16, %f20
75465fadds %f16, %f17, %f16
75466! preparing store val #1, next val will be in f33
75467fmovs %f16, %f21
75468fadds %f16, %f17, %f16
75469! preparing store val #2, next val will be in f35
75470fmovd %f20, %f32
75471fmovs %f16, %f21
75472fadds %f16, %f17, %f16
75473fmovd %f20, %f34
75474membar #Sync
75475stda %f32, [%i3 + 0 ] %asi
75476
75477P7213: !_MEMBAR (FP)
75478membar #StoreLoad
75479
75480P7214: !_PREFETCH [8] (Int) (LE)
75481wr %g0, 0x88, %asi
75482sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
75483sub %i0, %i2, %i2
75484prefetcha [%i2 + 12] %asi, 20
75485
75486P7215: !_LD [19] (Int)
75487sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
75488sub %i0, %i3, %i3
75489lduw [%i3 + 4], %o3
75490! move %o3(lower) -> %o3(upper)
75491sllx %o3, 32, %o3
75492
75493P7216: !_CAS [19] (maybe <- 0x3800057) (Int)
75494add %i3, 4, %o5
75495lduw [%o5], %l6
75496mov %l6, %l7
75497! move %l7(lower) -> %o3(lower)
75498or %l7, %o3, %o3
75499mov %l4, %o4
75500cas [%o5], %l7, %o4
75501! move %o4(lower) -> %o4(upper)
75502sllx %o4, 32, %o4
75503add %l4, 1, %l4
75504
75505P7217: !_ST [10] (maybe <- 0x3800058) (Int)
75506sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
75507sub %i0, %i2, %i2
75508stw %l4, [%i2 + 4 ]
75509add %l4, 1, %l4
75510
75511P7218: !_CAS [7] (maybe <- 0x3800059) (Int)
75512sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
75513sub %i0, %i3, %i3
75514add %i3, 4, %l7
75515lduw [%l7], %l3
75516mov %l3, %l6
75517! move %l6(lower) -> %o4(lower)
75518or %l6, %o4, %o4
75519!---- flushing int results buffer----
75520mov %o0, %l5
75521mov %o1, %l5
75522mov %o2, %l5
75523mov %o3, %l5
75524mov %o4, %l5
75525mov %l4, %o0
75526cas [%l7], %l6, %o0
75527! move %o0(lower) -> %o0(upper)
75528sllx %o0, 32, %o0
75529add %l4, 1, %l4
75530
75531P7219: !_CASX [6] (maybe <- 0x380005a) (Int)
75532ldx [%i3], %l3
75533! move %l3(upper) -> %o0(lower)
75534srlx %l3, 32, %l6
75535or %l6, %o0, %o0
75536! move %l3(lower) -> %o1(upper)
75537sllx %l3, 32, %o1
75538mov %l3, %l6
75539sllx %l4, 32, %l3
75540add %l4, 1, %l4
75541or %l4, %l3, %l3
75542casx [%i3], %l6, %l3
75543! move %l3(upper) -> %o1(lower)
75544srlx %l3, 32, %l6
75545or %l6, %o1, %o1
75546! move %l3(lower) -> %o2(upper)
75547sllx %l3, 32, %o2
75548add %l4, 1, %l4
75549
75550P7220: !_ST_BINIT [15] (maybe <- 0x380005c) (Int)
75551wr %g0, 0xe2, %asi
75552sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
75553add %i0, %i2, %i2
75554stwa %l4, [%i2 + 0] %asi
75555add %l4, 1, %l4
75556
75557P7221: !_MEMBAR (Int)
75558membar #StoreLoad
75559
75560P7222: !_SWAP [4] (maybe <- 0x380005d) (Int)
75561mov %l4, %l7
75562swap [%i1 + 4], %l7
75563! move %l7(lower) -> %o2(lower)
75564srl %l7, 0, %l3
75565or %l3, %o2, %o2
75566add %l4, 1, %l4
75567
75568P7223: !_CAS [18] (maybe <- 0x380005e) (Int)
75569sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
75570sub %i0, %i3, %i3
75571lduw [%i3], %o3
75572mov %o3, %o5
75573! move %o5(lower) -> %o3(upper)
75574sllx %o5, 32, %o3
75575mov %l4, %l7
75576cas [%i3], %o5, %l7
75577! move %l7(lower) -> %o3(lower)
75578srl %l7, 0, %o5
75579or %o5, %o3, %o3
75580add %l4, 1, %l4
75581
75582P7224: !_LDD [23] (Int)
75583sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
75584sub %i0, %i2, %i2
75585ldd [%i2 + 8], %l6
75586! move %l7(lower) -> %o4(upper)
75587sllx %l7, 32, %o4
75588
75589P7225: !_DWLD [14] (Int)
75590sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
75591sub %i0, %i3, %i3
75592ldx [%i3 + 8], %l6
75593! move %l6(lower) -> %o4(lower)
75594srl %l6, 0, %l3
75595or %l3, %o4, %o4
75596!---- flushing int results buffer----
75597mov %o0, %l5
75598mov %o1, %l5
75599mov %o2, %l5
75600mov %o3, %l5
75601mov %o4, %l5
75602
75603P7226: !_SWAP [10] (maybe <- 0x380005f) (Int)
75604sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
75605sub %i0, %i2, %i2
75606mov %l4, %o0
75607swap [%i2 + 4], %o0
75608! move %o0(lower) -> %o0(upper)
75609sllx %o0, 32, %o0
75610add %l4, 1, %l4
75611
75612P7227: !_SWAP [13] (maybe <- 0x3800060) (Int)
75613mov %l4, %o5
75614swap [%i3 + 4], %o5
75615! move %o5(lower) -> %o0(lower)
75616srl %o5, 0, %l6
75617or %l6, %o0, %o0
75618add %l4, 1, %l4
75619
75620P7228: !_MEMBAR (FP)
75621
75622P7229: !_BST [5] (maybe <- 0x43000046) (FP)
75623wr %g0, 0xf0, %asi
75624! preparing store val #0, next val will be in f32
75625fmovs %f16, %f20
75626fadds %f16, %f17, %f16
75627! preparing store val #1, next val will be in f33
75628fmovs %f16, %f21
75629fadds %f16, %f17, %f16
75630! preparing store val #2, next val will be in f35
75631fmovd %f20, %f32
75632fmovs %f16, %f21
75633fadds %f16, %f17, %f16
75634fmovd %f20, %f34
75635membar #Sync
75636stda %f32, [%i1 + 0 ] %asi
75637
75638P7230: !_MEMBAR (FP)
75639membar #StoreLoad
75640
75641P7231: !_ST [14] (maybe <- 0x3800061) (Int) (LE)
75642wr %g0, 0x88, %asi
75643! Change single-word-level endianess (big endian <-> little endian)
75644sethi %hi(0xff00ff00), %l3
75645or %l3, %lo(0xff00ff00), %l3
75646and %l4, %l3, %l6
75647srl %l6, 8, %l6
75648sll %l4, 8, %o5
75649and %o5, %l3, %o5
75650or %o5, %l6, %o5
75651srl %o5, 16, %l6
75652sll %o5, 16, %o5
75653srl %o5, 0, %o5
75654or %o5, %l6, %o5
75655stwa %o5, [%i3 + 12] %asi
75656add %l4, 1, %l4
75657
75658P7232: !_MEMBAR (FP)
75659
75660P7233: !_BSTC [4] (maybe <- 0x43000049) (FP) (Branch target of P7092)
75661wr %g0, 0xe0, %asi
75662! preparing store val #0, next val will be in f32
75663fmovs %f16, %f20
75664fadds %f16, %f17, %f16
75665! preparing store val #1, next val will be in f33
75666fmovs %f16, %f21
75667fadds %f16, %f17, %f16
75668! preparing store val #2, next val will be in f35
75669fmovd %f20, %f32
75670fmovs %f16, %f21
75671fadds %f16, %f17, %f16
75672fmovd %f20, %f34
75673membar #Sync
75674stda %f32, [%i1 + 0 ] %asi
75675ba P7234
75676nop
75677
75678TARGET7092:
75679ba RET7092
75680nop
75681
75682
75683P7234: !_MEMBAR (FP)
75684membar #StoreLoad
75685
75686P7235: !_ST_BINIT [16] (maybe <- 0x3800062) (Int)
75687wr %g0, 0xe2, %asi
75688sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
75689add %i0, %i3, %i3
75690stwa %l4, [%i3 + 4] %asi
75691add %l4, 1, %l4
75692
75693P7236: !_MEMBAR (Int)
75694membar #StoreLoad
75695
75696P7237: !_ST [13] (maybe <- 0x3800063) (Int)
75697sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
75698sub %i0, %i2, %i2
75699stw %l4, [%i2 + 4 ]
75700add %l4, 1, %l4
75701
75702P7238: !_MEMBAR (FP)
75703
75704P7239: !_BSTC [11] (maybe <- 0x4300004c) (FP)
75705wr %g0, 0xe0, %asi
75706sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
75707sub %i0, %i3, %i3
75708! preparing store val #0, next val will be in f32
75709fmovs %f16, %f20
75710fadds %f16, %f17, %f16
75711! preparing store val #1, next val will be in f33
75712fmovs %f16, %f21
75713fadds %f16, %f17, %f16
75714! preparing store val #2, next val will be in f35
75715fmovd %f20, %f32
75716fmovs %f16, %f21
75717fadds %f16, %f17, %f16
75718fmovd %f20, %f34
75719membar #Sync
75720stda %f32, [%i3 + 0 ] %asi
75721
75722P7240: !_MEMBAR (FP)
75723
75724P7241: !_BST [16] (maybe <- 0x4300004f) (FP)
75725wr %g0, 0xf0, %asi
75726sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
75727add %i0, %i2, %i2
75728! preparing store val #0, next val will be in f32
75729fmovs %f16, %f20
75730fadds %f16, %f17, %f16
75731! preparing store val #1, next val will be in f33
75732fmovs %f16, %f21
75733fadds %f16, %f17, %f16
75734! preparing store val #2, next val will be in f35
75735fmovd %f20, %f32
75736fmovs %f16, %f21
75737fadds %f16, %f17, %f16
75738fmovd %f20, %f34
75739membar #Sync
75740stda %f32, [%i2 + 0 ] %asi
75741
75742P7242: !_MEMBAR (FP)
75743membar #StoreLoad
75744
75745P7243: !_DWST_BINIT [10] (maybe <- 0x3800064) (Int)
75746wr %g0, 0xe2, %asi
75747sllx %l4, 32, %l6
75748add %l4, 1, %l4
75749or %l6, %l4, %l6
75750stxa %l6, [%i3 + 0] %asi
75751add %l4, 1, %l4
75752
75753P7244: !_MEMBAR (Int)
75754membar #StoreLoad
75755
75756P7245: !_CAS [20] (maybe <- 0x3800066) (Int)
75757sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
75758sub %i0, %i3, %i3
75759add %i3, 12, %l6
75760lduw [%l6], %o1
75761mov %o1, %l3
75762! move %l3(lower) -> %o1(upper)
75763sllx %l3, 32, %o1
75764mov %l4, %o5
75765cas [%l6], %l3, %o5
75766! move %o5(lower) -> %o1(lower)
75767srl %o5, 0, %l3
75768or %l3, %o1, %o1
75769add %l4, 1, %l4
75770
75771P7246: !_PREFETCH [9] (Int) (CBR)
75772sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
75773sub %i0, %i2, %i2
75774prefetch [%i2 + 0], 0
75775
75776! cbranch
75777andcc %l0, 1, %g0
75778be,pn %xcc, TARGET7246
75779nop
75780RET7246:
75781
75782! lfsr step begin
75783srlx %l0, 1, %l3
75784xnor %l3, %l0, %l3
75785sllx %l3, 63, %l3
75786or %l3, %l0, %l0
75787srlx %l0, 1, %l0
75788
75789
75790P7247: !_CASX [19] (maybe <- 0x3800067) (Int)
75791ldx [%i3], %o2
75792! move %o2(upper) -> %o2(upper)
75793! move %o2(lower) -> %o2(lower)
75794mov %o2, %l6
75795sllx %l4, 32, %o3
75796add %l4, 1, %l4
75797or %l4, %o3, %o3
75798casx [%i3], %l6, %o3
75799! move %o3(upper) -> %o3(upper)
75800! move %o3(lower) -> %o3(lower)
75801add %l4, 1, %l4
75802
75803P7248: !_DWST_BINIT [14] (maybe <- 0x3800069) (Int) (LE)
75804wr %g0, 0xea, %asi
75805sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
75806sub %i0, %i3, %i3
75807! Change single-word-level endianess (big endian <-> little endian)
75808sethi %hi(0xff00ff00), %l6
75809or %l6, %lo(0xff00ff00), %l6
75810and %l4, %l6, %o5
75811srl %o5, 8, %o5
75812sll %l4, 8, %l7
75813and %l7, %l6, %l7
75814or %l7, %o5, %l7
75815srl %l7, 16, %o5
75816sll %l7, 16, %l7
75817srl %l7, 0, %l7
75818or %l7, %o5, %l7
75819sllx %l7, 32, %l7
75820stxa %l7, [%i3 + 8 ] %asi
75821add %l4, 1, %l4
75822
75823P7249: !_MEMBAR (Int) (LE)
75824membar #StoreLoad
75825
75826P7250: !_CASX [13] (maybe <- 0x380006a) (Int)
75827ldx [%i3], %o4
75828! move %o4(upper) -> %o4(upper)
75829! move %o4(lower) -> %o4(lower)
75830!---- flushing int results buffer----
75831mov %o0, %l5
75832mov %o1, %l5
75833mov %o2, %l5
75834mov %o3, %l5
75835mov %o4, %l5
75836mov %o4, %l3
75837sllx %l4, 32, %o0
75838add %l4, 1, %l4
75839or %l4, %o0, %o0
75840casx [%i3], %l3, %o0
75841! move %o0(upper) -> %o0(upper)
75842! move %o0(lower) -> %o0(lower)
75843add %l4, 1, %l4
75844
75845P7251: !_LD [16] (Int)
75846sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
75847add %i0, %i2, %i2
75848lduw [%i2 + 4], %o1
75849! move %o1(lower) -> %o1(upper)
75850sllx %o1, 32, %o1
75851
75852P7252: !_CAS [22] (maybe <- 0x380006c) (Int)
75853sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
75854sub %i0, %i3, %i3
75855add %i3, 4, %o5
75856lduw [%o5], %l6
75857mov %l6, %l7
75858! move %l7(lower) -> %o1(lower)
75859or %l7, %o1, %o1
75860mov %l4, %o2
75861cas [%o5], %l7, %o2
75862! move %o2(lower) -> %o2(upper)
75863sllx %o2, 32, %o2
75864add %l4, 1, %l4
75865
75866P7253: !_REPLACEMENT [0] (Int)
75867sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
75868sub %i0, %i2, %i2
75869sethi %hi(0x20000), %l7
75870ld [%i2+0], %l3
75871st %l3, [%i2+0]
75872add %i2, %l7, %o5
75873ld [%o5+0], %l3
75874st %l3, [%o5+0]
75875add %o5, %l7, %o5
75876ld [%o5+0], %l3
75877st %l3, [%o5+0]
75878add %o5, %l7, %o5
75879ld [%o5+0], %l3
75880st %l3, [%o5+0]
75881add %o5, %l7, %o5
75882ld [%o5+0], %l3
75883st %l3, [%o5+0]
75884add %o5, %l7, %o5
75885ld [%o5+0], %l3
75886st %l3, [%o5+0]
75887add %o5, %l7, %o5
75888ld [%o5+0], %l3
75889st %l3, [%o5+0]
75890add %o5, %l7, %o5
75891ld [%o5+0], %l3
75892st %l3, [%o5+0]
75893
75894P7254: !_ST_BINIT [2] (maybe <- 0x380006d) (Int) (Branch target of P7882)
75895wr %g0, 0xe2, %asi
75896stwa %l4, [%i0 + 12] %asi
75897add %l4, 1, %l4
75898ba P7255
75899nop
75900
75901TARGET7882:
75902ba RET7882
75903nop
75904
75905
75906P7255: !_MEMBAR (Int)
75907membar #StoreLoad
75908
75909P7256: !_LDD [11] (Int)
75910sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
75911sub %i0, %i3, %i3
75912ldd [%i3 + 8], %l6
75913! move %l7(lower) -> %o2(lower)
75914or %l7, %o2, %o2
75915
75916P7257: !_DWLD [15] (Int)
75917sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
75918add %i0, %i2, %i2
75919ldx [%i2 + 0], %o3
75920! move %o3(upper) -> %o3(upper)
75921! move %o3(lower) -> %o3(lower)
75922
75923P7258: !_PREFETCH [19] (Int)
75924sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
75925sub %i0, %i3, %i3
75926prefetch [%i3 + 4], 1
75927
75928P7259: !_ST [2] (maybe <- 0x380006e) (Int)
75929stw %l4, [%i0 + 12 ]
75930add %l4, 1, %l4
75931
75932P7260: !_DWST [9] (maybe <- 0x43000052) (FP)
75933sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
75934sub %i0, %i2, %i2
75935! preparing store val #0, next val will be in f20
75936fmovs %f16, %f20
75937fadds %f16, %f17, %f16
75938! preparing store val #1, next val will be in f21
75939fmovs %f16, %f21
75940fadds %f16, %f17, %f16
75941std %f20, [%i2 + 0]
75942
75943P7261: !_MEMBAR (FP)
75944
75945P7262: !_BSTC [19] (maybe <- 0x43000054) (FP)
75946wr %g0, 0xe0, %asi
75947! preparing store val #0, next val will be in f32
75948fmovs %f16, %f20
75949fadds %f16, %f17, %f16
75950! preparing store val #1, next val will be in f33
75951fmovs %f16, %f21
75952fadds %f16, %f17, %f16
75953! preparing store val #2, next val will be in f35
75954fmovd %f20, %f32
75955fmovs %f16, %f21
75956fadds %f16, %f17, %f16
75957fmovd %f20, %f34
75958membar #Sync
75959stda %f32, [%i3 + 0 ] %asi
75960
75961P7263: !_MEMBAR (FP)
75962membar #StoreLoad
75963
75964P7264: !_CASX [6] (maybe <- 0x380006f) (Int) (CBR)
75965sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
75966sub %i0, %i3, %i3
75967ldx [%i3], %o4
75968! move %o4(upper) -> %o4(upper)
75969! move %o4(lower) -> %o4(lower)
75970!---- flushing int results buffer----
75971mov %o0, %l5
75972mov %o1, %l5
75973mov %o2, %l5
75974mov %o3, %l5
75975mov %o4, %l5
75976mov %o4, %o5
75977sllx %l4, 32, %o0
75978add %l4, 1, %l4
75979or %l4, %o0, %o0
75980casx [%i3], %o5, %o0
75981! move %o0(upper) -> %o0(upper)
75982! move %o0(lower) -> %o0(lower)
75983add %l4, 1, %l4
75984
75985! cbranch
75986andcc %l0, 1, %g0
75987be,pt %xcc, TARGET7264
75988nop
75989RET7264:
75990
75991! lfsr step begin
75992srlx %l0, 1, %o5
75993xnor %o5, %l0, %o5
75994sllx %o5, 63, %o5
75995or %o5, %l0, %l0
75996srlx %l0, 1, %l0
75997
75998
75999P7265: !_DWST [5] (maybe <- 0x3800071) (Int)
76000mov %l4, %l3
76001stx %l3, [%i1 + 8]
76002add %l4, 1, %l4
76003
76004P7266: !_MEMBAR (FP)
76005
76006P7267: !_BSTC [15] (maybe <- 0x43000057) (FP)
76007wr %g0, 0xe0, %asi
76008sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
76009add %i0, %i2, %i2
76010! preparing store val #0, next val will be in f32
76011fmovs %f16, %f20
76012fadds %f16, %f17, %f16
76013! preparing store val #1, next val will be in f33
76014fmovs %f16, %f21
76015fadds %f16, %f17, %f16
76016! preparing store val #2, next val will be in f35
76017fmovd %f20, %f32
76018fmovs %f16, %f21
76019fadds %f16, %f17, %f16
76020fmovd %f20, %f34
76021membar #Sync
76022stda %f32, [%i2 + 0 ] %asi
76023
76024P7268: !_MEMBAR (FP)
76025membar #StoreLoad
76026
76027P7269: !_LD [12] (Int)
76028sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
76029sub %i0, %i3, %i3
76030lduw [%i3 + 0], %o1
76031! move %o1(lower) -> %o1(upper)
76032sllx %o1, 32, %o1
76033
76034P7270: !_DWLD [9] (Int)
76035sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
76036sub %i0, %i2, %i2
76037ldx [%i2 + 0], %l6
76038! move %l6(upper) -> %o1(lower)
76039srlx %l6, 32, %l3
76040or %l3, %o1, %o1
76041! move %l6(lower) -> %o2(upper)
76042sllx %l6, 32, %o2
76043
76044P7271: !_REPLACEMENT [12] (Int)
76045sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
76046add %i0, %i3, %i3
76047sethi %hi(0x20000), %o5
76048ld [%i3+0], %l6
76049st %l6, [%i3+0]
76050add %i3, %o5, %l3
76051ld [%l3+0], %l6
76052st %l6, [%l3+0]
76053add %l3, %o5, %l3
76054ld [%l3+0], %l6
76055st %l6, [%l3+0]
76056add %l3, %o5, %l3
76057ld [%l3+0], %l6
76058st %l6, [%l3+0]
76059add %l3, %o5, %l3
76060ld [%l3+0], %l6
76061st %l6, [%l3+0]
76062add %l3, %o5, %l3
76063ld [%l3+0], %l6
76064st %l6, [%l3+0]
76065add %l3, %o5, %l3
76066ld [%l3+0], %l6
76067st %l6, [%l3+0]
76068add %l3, %o5, %l3
76069ld [%l3+0], %l6
76070st %l6, [%l3+0]
76071
76072P7272: !_MEMBAR (FP)
76073membar #StoreLoad
76074
76075P7273: !_BLD [17] (FP)
76076wr %g0, 0xf0, %asi
76077sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
76078add %i0, %i2, %i2
76079ldda [%i2 + 0] %asi, %f32
76080membar #Sync
76081! 3 addresses covered
76082fmovd %f32, %f18
76083fmovs %f18, %f3
76084fmovs %f19, %f4
76085fmovd %f34, %f18
76086fmovs %f19, %f5
76087
76088P7274: !_MEMBAR (FP)
76089
76090P7275: !_LD [16] (Int) (LE)
76091wr %g0, 0x88, %asi
76092lduwa [%i2 + 4] %asi, %o5
76093! move %o5(lower) -> %o2(lower)
76094or %o5, %o2, %o2
76095
76096P7276: !_DWST [0] (maybe <- 0x3800072) (Int)
76097sllx %l4, 32, %l3
76098add %l4, 1, %l4
76099or %l3, %l4, %l3
76100stx %l3, [%i0 + 0]
76101add %l4, 1, %l4
76102
76103P7277: !_DWST_BINIT [5] (maybe <- 0x3800074) (Int)
76104wr %g0, 0xe2, %asi
76105mov %l4, %o5
76106stxa %o5, [%i1 + 8] %asi
76107add %l4, 1, %l4
76108
76109P7278: !_MEMBAR (Int)
76110membar #StoreLoad
76111
76112P7279: !_DWLD [22] (Int)
76113sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
76114sub %i0, %i3, %i3
76115ldx [%i3 + 0], %o3
76116! move %o3(upper) -> %o3(upper)
76117! move %o3(lower) -> %o3(lower)
76118
76119P7280: !_DWST_BINIT [7] (maybe <- 0x3800075) (Int)
76120wr %g0, 0xe2, %asi
76121sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
76122sub %i0, %i2, %i2
76123sllx %l4, 32, %l3
76124add %l4, 1, %l4
76125or %l3, %l4, %l3
76126stxa %l3, [%i2 + 0] %asi
76127add %l4, 1, %l4
76128
76129P7281: !_MEMBAR (Int)
76130membar #StoreLoad
76131
76132P7282: !_DWST_BINIT [21] (maybe <- 0x3800077) (Int)
76133wr %g0, 0xe2, %asi
76134sllx %l4, 32, %o5
76135add %l4, 1, %l4
76136or %o5, %l4, %o5
76137stxa %o5, [%i3 + 0] %asi
76138add %l4, 1, %l4
76139
76140P7283: !_MEMBAR (Int)
76141membar #StoreLoad
76142
76143P7284: !_ST_BINIT [9] (maybe <- 0x3800079) (Int)
76144wr %g0, 0xe2, %asi
76145sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
76146sub %i0, %i3, %i3
76147stwa %l4, [%i3 + 0] %asi
76148add %l4, 1, %l4
76149
76150P7285: !_MEMBAR (Int)
76151membar #StoreLoad
76152
76153P7286: !_CASX [23] (maybe <- 0x380007a) (Int)
76154sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
76155sub %i0, %i2, %i2
76156add %i2, 8, %l7
76157ldx [%l7], %o4
76158! move %o4(upper) -> %o4(upper)
76159! move %o4(lower) -> %o4(lower)
76160!---- flushing int results buffer----
76161mov %o0, %l5
76162mov %o1, %l5
76163mov %o2, %l5
76164mov %o3, %l5
76165mov %o4, %l5
76166mov %o4, %l6
76167mov %l4, %o0
76168casx [%l7], %l6, %o0
76169! move %o0(upper) -> %o0(upper)
76170! move %o0(lower) -> %o0(lower)
76171add %l4, 1, %l4
76172
76173P7287: !_CASX [14] (maybe <- 0x380007b) (Int)
76174sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
76175sub %i0, %i3, %i3
76176add %i3, 8, %l7
76177ldx [%l7], %o1
76178! move %o1(upper) -> %o1(upper)
76179! move %o1(lower) -> %o1(lower)
76180mov %o1, %l6
76181mov %l4, %o2
76182casx [%l7], %l6, %o2
76183! move %o2(upper) -> %o2(upper)
76184! move %o2(lower) -> %o2(lower)
76185add %l4, 1, %l4
76186
76187P7288: !_MEMBAR (FP) (CBR) (Branch target of P7640)
76188membar #StoreLoad
76189
76190! cbranch
76191andcc %l0, 1, %g0
76192be,pt %xcc, TARGET7288
76193nop
76194RET7288:
76195
76196! lfsr step begin
76197srlx %l0, 1, %l6
76198xnor %l6, %l0, %l6
76199sllx %l6, 63, %l6
76200or %l6, %l0, %l0
76201srlx %l0, 1, %l0
76202
76203ba P7289
76204nop
76205
76206TARGET7640:
76207ba RET7640
76208nop
76209
76210
76211P7289: !_BLD [8] (FP)
76212wr %g0, 0xf0, %asi
76213sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
76214sub %i0, %i2, %i2
76215ldda [%i2 + 0] %asi, %f32
76216membar #Sync
76217! 3 addresses covered
76218fmovd %f32, %f6
76219fmovd %f34, %f18
76220fmovs %f19, %f8
76221
76222P7290: !_MEMBAR (FP)
76223
76224P7291: !_BSTC [0] (maybe <- 0x4300005a) (FP)
76225wr %g0, 0xe0, %asi
76226! preparing store val #0, next val will be in f32
76227fmovs %f16, %f20
76228fadds %f16, %f17, %f16
76229! preparing store val #1, next val will be in f33
76230fmovs %f16, %f21
76231fadds %f16, %f17, %f16
76232! preparing store val #2, next val will be in f35
76233fmovd %f20, %f32
76234fmovs %f16, %f21
76235fadds %f16, %f17, %f16
76236fmovd %f20, %f34
76237membar #Sync
76238stda %f32, [%i0 + 0 ] %asi
76239
76240P7292: !_MEMBAR (FP)
76241membar #StoreLoad
76242
76243P7293: !_LDD [17] (Int)
76244sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
76245add %i0, %i3, %i3
76246ldd [%i3 + 8], %l6
76247! move %l7(lower) -> %o3(upper)
76248sllx %l7, 32, %o3
76249
76250P7294: !_DWLD [14] (Int)
76251sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
76252sub %i0, %i2, %i2
76253ldx [%i2 + 8], %l6
76254! move %l6(lower) -> %o3(lower)
76255srl %l6, 0, %l3
76256or %l3, %o3, %o3
76257
76258P7295: !_DWST [21] (maybe <- 0x380007c) (Int)
76259sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
76260sub %i0, %i3, %i3
76261sllx %l4, 32, %l7
76262add %l4, 1, %l4
76263or %l7, %l4, %l7
76264stx %l7, [%i3 + 0]
76265add %l4, 1, %l4
76266
76267P7296: !_SWAP [22] (maybe <- 0x380007e) (Int)
76268mov %l4, %o4
76269swap [%i3 + 4], %o4
76270! move %o4(lower) -> %o4(upper)
76271sllx %o4, 32, %o4
76272add %l4, 1, %l4
76273
76274P7297: !_SWAP [22] (maybe <- 0x380007f) (Int)
76275mov %l4, %l7
76276swap [%i3 + 4], %l7
76277! move %l7(lower) -> %o4(lower)
76278srl %l7, 0, %l3
76279or %l3, %o4, %o4
76280!---- flushing int results buffer----
76281mov %o0, %l5
76282mov %o1, %l5
76283mov %o2, %l5
76284mov %o3, %l5
76285mov %o4, %l5
76286add %l4, 1, %l4
76287
76288P7298: !_CAS [8] (maybe <- 0x3800080) (Int)
76289sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
76290sub %i0, %i2, %i2
76291add %i2, 12, %l3
76292lduw [%l3], %o0
76293mov %o0, %o5
76294! move %o5(lower) -> %o0(upper)
76295sllx %o5, 32, %o0
76296mov %l4, %l7
76297cas [%l3], %o5, %l7
76298! move %l7(lower) -> %o0(lower)
76299srl %l7, 0, %o5
76300or %o5, %o0, %o0
76301add %l4, 1, %l4
76302
76303P7299: !_CASX [5] (maybe <- 0x3800081) (Int)
76304add %i1, 8, %l3
76305ldx [%l3], %o1
76306! move %o1(upper) -> %o1(upper)
76307! move %o1(lower) -> %o1(lower)
76308mov %o1, %o5
76309mov %l4, %o2
76310casx [%l3], %o5, %o2
76311! move %o2(upper) -> %o2(upper)
76312! move %o2(lower) -> %o2(lower)
76313add %l4, 1, %l4
76314
76315P7300: !_MEMBAR (FP) (CBR)
76316membar #StoreLoad
76317
76318! cbranch
76319andcc %l0, 1, %g0
76320be,pt %xcc, TARGET7300
76321nop
76322RET7300:
76323
76324! lfsr step begin
76325srlx %l0, 1, %o5
76326xnor %o5, %l0, %o5
76327sllx %o5, 63, %o5
76328or %o5, %l0, %l0
76329srlx %l0, 1, %l0
76330
76331
76332P7301: !_BLD [0] (FP)
76333wr %g0, 0xf0, %asi
76334ldda [%i0 + 0] %asi, %f32
76335membar #Sync
76336! 3 addresses covered
76337fmovd %f32, %f18
76338fmovs %f18, %f9
76339fmovs %f19, %f10
76340fmovd %f34, %f18
76341fmovs %f19, %f11
76342
76343P7302: !_MEMBAR (FP)
76344
76345P7303: !_DWST_BINIT [20] (maybe <- 0x3800082) (Int) (LE)
76346wr %g0, 0xea, %asi
76347sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
76348sub %i0, %i3, %i3
76349! Change single-word-level endianess (big endian <-> little endian)
76350sethi %hi(0xff00ff00), %l3
76351or %l3, %lo(0xff00ff00), %l3
76352and %l4, %l3, %l7
76353srl %l7, 8, %l7
76354sll %l4, 8, %l6
76355and %l6, %l3, %l6
76356or %l6, %l7, %l6
76357srl %l6, 16, %l7
76358sll %l6, 16, %l6
76359srl %l6, 0, %l6
76360or %l6, %l7, %l6
76361sllx %l6, 32, %l6
76362stxa %l6, [%i3 + 8 ] %asi
76363add %l4, 1, %l4
76364
76365P7304: !_MEMBAR (Int) (LE)
76366membar #StoreLoad
76367
76368P7305: !_PREFETCH [10] (Int)
76369sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
76370sub %i0, %i2, %i2
76371prefetch [%i2 + 4], 20
76372
76373P7306: !_ST [13] (maybe <- 0x3800083) (Int)
76374sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
76375sub %i0, %i3, %i3
76376stw %l4, [%i3 + 4 ]
76377add %l4, 1, %l4
76378
76379P7307: !_MEMBAR (FP)
76380membar #StoreLoad
76381
76382P7308: !_BLD [14] (FP)
76383wr %g0, 0xf0, %asi
76384ldda [%i3 + 0] %asi, %f32
76385membar #Sync
76386! 3 addresses covered
76387fmovd %f32, %f12
76388fmovd %f34, %f18
76389fmovs %f19, %f14
76390
76391P7309: !_MEMBAR (FP)
76392
76393P7310: !_DWST [7] (maybe <- 0x3800084) (Int)
76394sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
76395sub %i0, %i2, %i2
76396sllx %l4, 32, %l7
76397add %l4, 1, %l4
76398or %l7, %l4, %l7
76399stx %l7, [%i2 + 0]
76400add %l4, 1, %l4
76401
76402P7311: !_LDD [10] (Int)
76403sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i3
76404sub %i0, %i3, %i3
76405ldd [%i3 + 0], %l6
76406! move %l6(lower) -> %o3(upper)
76407sllx %l6, 32, %o3
76408! move %l7(lower) -> %o3(lower)
76409or %l7, %o3, %o3
76410
76411P7312: !_DWLD [13] (Int)
76412sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
76413sub %i0, %i2, %i2
76414ldx [%i2 + 0], %o4
76415! move %o4(upper) -> %o4(upper)
76416! move %o4(lower) -> %o4(lower)
76417!---- flushing int results buffer----
76418mov %o0, %l5
76419mov %o1, %l5
76420mov %o2, %l5
76421mov %o3, %l5
76422mov %o4, %l5
76423
76424P7313: !_LDD [19] (Int) (Branch target of P7362)
76425sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
76426sub %i0, %i3, %i3
76427ldd [%i3 + 0], %l6
76428! move %l6(lower) -> %o0(upper)
76429sllx %l6, 32, %o0
76430! move %l7(lower) -> %o0(lower)
76431or %l7, %o0, %o0
76432ba P7314
76433nop
76434
76435TARGET7362:
76436ba RET7362
76437nop
76438
76439
76440P7314: !_LD [19] (Int)
76441lduw [%i3 + 4], %o1
76442! move %o1(lower) -> %o1(upper)
76443sllx %o1, 32, %o1
76444
76445P7315: !_ST_BINIT [17] (maybe <- 0x3800086) (Int)
76446wr %g0, 0xe2, %asi
76447sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
76448add %i0, %i2, %i2
76449stwa %l4, [%i2 + 12] %asi
76450add %l4, 1, %l4
76451
76452P7316: !_MEMBAR (Int)
76453membar #StoreLoad
76454
76455P7317: !_BLD [1] (FP)
76456wr %g0, 0xf0, %asi
76457ldda [%i0 + 0] %asi, %f32
76458membar #Sync
76459! 3 addresses covered
76460fmovd %f32, %f18
76461fmovs %f18, %f15
76462!---- flushing fp results buffer to %f30 ----
76463fmovd %f0, %f30
76464fmovd %f2, %f30
76465fmovd %f4, %f30
76466fmovd %f6, %f30
76467fmovd %f8, %f30
76468fmovd %f10, %f30
76469fmovd %f12, %f30
76470fmovd %f14, %f30
76471!--
76472fmovs %f19, %f0
76473fmovd %f34, %f18
76474fmovs %f19, %f1
76475
76476P7318: !_MEMBAR (FP)
76477
76478P7319: !_REPLACEMENT [14] (Int)
76479sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
76480add %i0, %i3, %i3
76481sethi %hi(0x20000), %l6
76482ld [%i3+12], %o5
76483st %o5, [%i3+12]
76484add %i3, %l6, %l7
76485ld [%l7+12], %o5
76486st %o5, [%l7+12]
76487add %l7, %l6, %l7
76488ld [%l7+12], %o5
76489st %o5, [%l7+12]
76490add %l7, %l6, %l7
76491ld [%l7+12], %o5
76492st %o5, [%l7+12]
76493add %l7, %l6, %l7
76494ld [%l7+12], %o5
76495st %o5, [%l7+12]
76496add %l7, %l6, %l7
76497ld [%l7+12], %o5
76498st %o5, [%l7+12]
76499add %l7, %l6, %l7
76500ld [%l7+12], %o5
76501st %o5, [%l7+12]
76502add %l7, %l6, %l7
76503ld [%l7+12], %o5
76504st %o5, [%l7+12]
76505
76506P7320: !_DWST_BINIT [6] (maybe <- 0x3800087) (Int)
76507wr %g0, 0xe2, %asi
76508sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
76509sub %i0, %i2, %i2
76510sllx %l4, 32, %l3
76511add %l4, 1, %l4
76512or %l3, %l4, %l3
76513stxa %l3, [%i2 + 0] %asi
76514add %l4, 1, %l4
76515
76516P7321: !_MEMBAR (Int)
76517membar #StoreLoad
76518
76519P7322: !_ST [5] (maybe <- 0x3800089) (Int)
76520stw %l4, [%i1 + 12 ]
76521add %l4, 1, %l4
76522
76523P7323: !_ST [6] (maybe <- 0x380008a) (Int) (LE)
76524wr %g0, 0x88, %asi
76525! Change single-word-level endianess (big endian <-> little endian)
76526sethi %hi(0xff00ff00), %o5
76527or %o5, %lo(0xff00ff00), %o5
76528and %l4, %o5, %l3
76529srl %l3, 8, %l3
76530sll %l4, 8, %l7
76531and %l7, %o5, %l7
76532or %l7, %l3, %l7
76533srl %l7, 16, %l3
76534sll %l7, 16, %l7
76535srl %l7, 0, %l7
76536or %l7, %l3, %l7
76537stwa %l7, [%i2 + 0] %asi
76538add %l4, 1, %l4
76539
76540P7324: !_CAS [5] (maybe <- 0x380008b) (Int)
76541add %i1, 12, %l7
76542lduw [%l7], %l3
76543mov %l3, %l6
76544! move %l6(lower) -> %o1(lower)
76545or %l6, %o1, %o1
76546mov %l4, %o2
76547cas [%l7], %l6, %o2
76548! move %o2(lower) -> %o2(upper)
76549sllx %o2, 32, %o2
76550add %l4, 1, %l4
76551
76552P7325: !_CAS [14] (maybe <- 0x380008c) (Int)
76553sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
76554sub %i0, %i3, %i3
76555add %i3, 12, %l7
76556lduw [%l7], %l3
76557mov %l3, %l6
76558! move %l6(lower) -> %o2(lower)
76559or %l6, %o2, %o2
76560mov %l4, %o3
76561cas [%l7], %l6, %o3
76562! move %o3(lower) -> %o3(upper)
76563sllx %o3, 32, %o3
76564add %l4, 1, %l4
76565
76566P7326: !_MEMBAR (FP)
76567membar #StoreLoad
76568
76569P7327: !_BLD [15] (FP)
76570wr %g0, 0xf0, %asi
76571sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
76572add %i0, %i2, %i2
76573ldda [%i2 + 0] %asi, %f32
76574membar #Sync
76575! 3 addresses covered
76576fmovd %f32, %f2
76577fmovd %f34, %f18
76578fmovs %f19, %f4
76579
76580P7328: !_MEMBAR (FP)
76581
76582P7329: !_REPLACEMENT [9] (Int)
76583sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
76584add %i0, %i3, %i3
76585sethi %hi(0x20000), %l6
76586ld [%i3+0], %o5
76587st %o5, [%i3+0]
76588add %i3, %l6, %l7
76589ld [%l7+0], %o5
76590st %o5, [%l7+0]
76591add %l7, %l6, %l7
76592ld [%l7+0], %o5
76593st %o5, [%l7+0]
76594add %l7, %l6, %l7
76595ld [%l7+0], %o5
76596st %o5, [%l7+0]
76597add %l7, %l6, %l7
76598ld [%l7+0], %o5
76599st %o5, [%l7+0]
76600add %l7, %l6, %l7
76601ld [%l7+0], %o5
76602st %o5, [%l7+0]
76603add %l7, %l6, %l7
76604ld [%l7+0], %o5
76605st %o5, [%l7+0]
76606add %l7, %l6, %l7
76607ld [%l7+0], %o5
76608st %o5, [%l7+0]
76609
76610P7330: !_MEMBAR (FP) (Branch target of P7918)
76611membar #StoreLoad
76612ba P7331
76613nop
76614
76615TARGET7918:
76616ba RET7918
76617nop
76618
76619
76620P7331: !_BLD [21] (FP)
76621wr %g0, 0xf0, %asi
76622sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
76623sub %i0, %i2, %i2
76624ldda [%i2 + 0] %asi, %f32
76625membar #Sync
76626! 3 addresses covered
76627fmovd %f32, %f18
76628fmovs %f18, %f5
76629fmovs %f19, %f6
76630fmovd %f34, %f18
76631fmovs %f19, %f7
76632
76633P7332: !_MEMBAR (FP)
76634
76635P7333: !_PREFETCH [20] (Int)
76636sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
76637sub %i0, %i3, %i3
76638prefetch [%i3 + 12], 22
76639
76640P7334: !_ST [3] (maybe <- 0x380008d) (Int)
76641stw %l4, [%i1 + 0 ]
76642add %l4, 1, %l4
76643
76644P7335: !_REPLACEMENT [23] (Int)
76645sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
76646sub %i0, %i2, %i2
76647sethi %hi(0x20000), %l3
76648ld [%i2+12], %l7
76649st %l7, [%i2+12]
76650add %i2, %l3, %l6
76651ld [%l6+12], %l7
76652st %l7, [%l6+12]
76653add %l6, %l3, %l6
76654ld [%l6+12], %l7
76655st %l7, [%l6+12]
76656add %l6, %l3, %l6
76657ld [%l6+12], %l7
76658st %l7, [%l6+12]
76659add %l6, %l3, %l6
76660ld [%l6+12], %l7
76661st %l7, [%l6+12]
76662add %l6, %l3, %l6
76663ld [%l6+12], %l7
76664st %l7, [%l6+12]
76665add %l6, %l3, %l6
76666ld [%l6+12], %l7
76667st %l7, [%l6+12]
76668add %l6, %l3, %l6
76669ld [%l6+12], %l7
76670st %l7, [%l6+12]
76671
76672P7336: !_CAS [6] (maybe <- 0x380008e) (Int) (LE)
76673! Change single-word-level endianess (big endian <-> little endian)
76674sethi %hi(0xff00ff00), %l3
76675or %l3, %lo(0xff00ff00), %l3
76676and %l4, %l3, %o5
76677srl %o5, 8, %o5
76678sll %l4, 8, %l6
76679and %l6, %l3, %l6
76680or %l6, %o5, %l6
76681srl %l6, 16, %o5
76682sll %l6, 16, %l6
76683srl %l6, 0, %l6
76684or %l6, %o5, %l6
76685wr %g0, 0x88, %asi
76686sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
76687sub %i0, %i3, %i3
76688lduwa [%i3] %asi, %l7
76689mov %l7, %o5
76690! move %o5(lower) -> %o3(lower)
76691or %o5, %o3, %o3
76692mov %l6, %o4
76693casa [%i3] %asi, %o5, %o4
76694! move %o4(lower) -> %o4(upper)
76695sllx %o4, 32, %o4
76696add %l4, 1, %l4
76697
76698P7337: !_ST_BINIT [21] (maybe <- 0x380008f) (Int)
76699wr %g0, 0xe2, %asi
76700sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
76701sub %i0, %i2, %i2
76702stwa %l4, [%i2 + 0] %asi
76703add %l4, 1, %l4
76704
76705P7338: !_MEMBAR (Int)
76706membar #StoreLoad
76707
76708P7339: !_ST [15] (maybe <- 0x3800090) (Int)
76709sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
76710add %i0, %i3, %i3
76711stw %l4, [%i3 + 0 ]
76712add %l4, 1, %l4
76713
76714P7340: !_MEMBAR (FP)
76715membar #StoreLoad
76716
76717P7341: !_BLD [23] (FP)
76718wr %g0, 0xf0, %asi
76719ldda [%i2 + 0] %asi, %f32
76720membar #Sync
76721! 3 addresses covered
76722fmovd %f32, %f8
76723fmovd %f34, %f18
76724fmovs %f19, %f10
76725
76726P7342: !_MEMBAR (FP)
76727
76728P7343: !_BLD [7] (FP) (CBR)
76729wr %g0, 0xf0, %asi
76730sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
76731sub %i0, %i2, %i2
76732ldda [%i2 + 0] %asi, %f32
76733membar #Sync
76734! 3 addresses covered
76735fmovd %f32, %f18
76736fmovs %f18, %f11
76737fmovs %f19, %f12
76738fmovd %f34, %f18
76739fmovs %f19, %f13
76740
76741! cbranch
76742andcc %l0, 1, %g0
76743be,pn %xcc, TARGET7343
76744nop
76745RET7343:
76746
76747! lfsr step begin
76748srlx %l0, 1, %l6
76749xnor %l6, %l0, %l6
76750sllx %l6, 63, %l6
76751or %l6, %l0, %l0
76752srlx %l0, 1, %l0
76753
76754
76755P7344: !_MEMBAR (FP)
76756
76757P7345: !_DWST [22] (maybe <- 0x3800091) (Int)
76758sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
76759sub %i0, %i3, %i3
76760sllx %l4, 32, %l7
76761add %l4, 1, %l4
76762or %l7, %l4, %l7
76763stx %l7, [%i3 + 0]
76764add %l4, 1, %l4
76765
76766P7346: !_ST [15] (maybe <- 0x3800093) (Int)
76767sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
76768add %i0, %i2, %i2
76769stw %l4, [%i2 + 0 ]
76770add %l4, 1, %l4
76771
76772P7347: !_MEMBAR (FP)
76773
76774P7348: !_BSTC [21] (maybe <- 0x4300005d) (FP)
76775wr %g0, 0xe0, %asi
76776! preparing store val #0, next val will be in f32
76777fmovs %f16, %f20
76778fadds %f16, %f17, %f16
76779! preparing store val #1, next val will be in f33
76780fmovs %f16, %f21
76781fadds %f16, %f17, %f16
76782! preparing store val #2, next val will be in f35
76783fmovd %f20, %f32
76784fmovs %f16, %f21
76785fadds %f16, %f17, %f16
76786fmovd %f20, %f34
76787membar #Sync
76788stda %f32, [%i3 + 0 ] %asi
76789
76790P7349: !_MEMBAR (FP)
76791membar #StoreLoad
76792
76793P7350: !_PREFETCH [8] (Int) (Branch target of P7644)
76794sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
76795sub %i0, %i3, %i3
76796prefetch [%i3 + 12], 22
76797ba P7351
76798nop
76799
76800TARGET7644:
76801ba RET7644
76802nop
76803
76804
76805P7351: !_PREFETCH [7] (Int)
76806prefetch [%i3 + 4], 22
76807
76808P7352: !_DWST_BINIT [9] (maybe <- 0x3800094) (Int)
76809wr %g0, 0xe2, %asi
76810sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
76811sub %i0, %i2, %i2
76812sllx %l4, 32, %o5
76813add %l4, 1, %l4
76814or %o5, %l4, %o5
76815stxa %o5, [%i2 + 0] %asi
76816add %l4, 1, %l4
76817
76818P7353: !_MEMBAR (Int)
76819membar #StoreLoad
76820
76821P7354: !_LD [9] (Int)
76822lduw [%i2 + 0], %o5
76823! move %o5(lower) -> %o4(lower)
76824or %o5, %o4, %o4
76825!---- flushing int results buffer----
76826mov %o0, %l5
76827mov %o1, %l5
76828mov %o2, %l5
76829mov %o3, %l5
76830mov %o4, %l5
76831
76832P7355: !_LD [0] (Int)
76833lduw [%i0 + 0], %o0
76834! move %o0(lower) -> %o0(upper)
76835sllx %o0, 32, %o0
76836
76837P7356: !_DWST [20] (maybe <- 0x3800096) (Int)
76838sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
76839sub %i0, %i3, %i3
76840mov %l4, %l7
76841stx %l7, [%i3 + 8]
76842add %l4, 1, %l4
76843
76844P7357: !_SWAP [7] (maybe <- 0x3800097) (Int)
76845sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
76846sub %i0, %i2, %i2
76847mov %l4, %o5
76848swap [%i2 + 4], %o5
76849! move %o5(lower) -> %o0(lower)
76850srl %o5, 0, %l6
76851or %l6, %o0, %o0
76852add %l4, 1, %l4
76853
76854P7358: !_MEMBAR (FP)
76855
76856P7359: !_BST [1] (maybe <- 0x43000060) (FP)
76857wr %g0, 0xf0, %asi
76858! preparing store val #0, next val will be in f32
76859fmovs %f16, %f20
76860fadds %f16, %f17, %f16
76861! preparing store val #1, next val will be in f33
76862fmovs %f16, %f21
76863fadds %f16, %f17, %f16
76864! preparing store val #2, next val will be in f35
76865fmovd %f20, %f32
76866fmovs %f16, %f21
76867fadds %f16, %f17, %f16
76868fmovd %f20, %f34
76869membar #Sync
76870stda %f32, [%i0 + 0 ] %asi
76871
76872P7360: !_MEMBAR (FP) (CBR)
76873
76874! cbranch
76875andcc %l0, 1, %g0
76876be,pt %xcc, TARGET7360
76877nop
76878RET7360:
76879
76880! lfsr step begin
76881srlx %l0, 1, %o5
76882xnor %o5, %l0, %o5
76883sllx %o5, 63, %o5
76884or %o5, %l0, %l0
76885srlx %l0, 1, %l0
76886
76887
76888P7361: !_BSTC [3] (maybe <- 0x43000063) (FP)
76889wr %g0, 0xe0, %asi
76890! preparing store val #0, next val will be in f32
76891fmovs %f16, %f20
76892fadds %f16, %f17, %f16
76893! preparing store val #1, next val will be in f33
76894fmovs %f16, %f21
76895fadds %f16, %f17, %f16
76896! preparing store val #2, next val will be in f35
76897fmovd %f20, %f32
76898fmovs %f16, %f21
76899fadds %f16, %f17, %f16
76900fmovd %f20, %f34
76901membar #Sync
76902stda %f32, [%i1 + 0 ] %asi
76903
76904P7362: !_MEMBAR (FP) (CBR)
76905membar #StoreLoad
76906
76907! cbranch
76908andcc %l0, 1, %g0
76909be,pn %xcc, TARGET7362
76910nop
76911RET7362:
76912
76913! lfsr step begin
76914srlx %l0, 1, %o5
76915xnor %o5, %l0, %o5
76916sllx %o5, 63, %o5
76917or %o5, %l0, %l0
76918srlx %l0, 1, %l0
76919
76920
76921P7363: !_PREFETCH [18] (Int)
76922prefetch [%i3 + 0], 20
76923
76924P7364: !_LD [17] (Int)
76925sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
76926add %i0, %i3, %i3
76927lduw [%i3 + 12], %o1
76928! move %o1(lower) -> %o1(upper)
76929sllx %o1, 32, %o1
76930
76931P7365: !_LDD [12] (Int)
76932sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
76933sub %i0, %i2, %i2
76934ldd [%i2 + 0], %l6
76935! move %l6(lower) -> %o1(lower)
76936or %l6, %o1, %o1
76937! move %l7(lower) -> %o2(upper)
76938sllx %l7, 32, %o2
76939
76940P7366: !_MEMBAR (FP)
76941membar #StoreLoad
76942
76943P7367: !_BLD [13] (FP)
76944wr %g0, 0xf0, %asi
76945ldda [%i2 + 0] %asi, %f32
76946membar #Sync
76947! 3 addresses covered
76948fmovd %f32, %f14
76949!---- flushing fp results buffer to %f30 ----
76950fmovd %f0, %f30
76951fmovd %f2, %f30
76952fmovd %f4, %f30
76953fmovd %f6, %f30
76954fmovd %f8, %f30
76955fmovd %f10, %f30
76956fmovd %f12, %f30
76957fmovd %f14, %f30
76958!--
76959fmovd %f34, %f18
76960fmovs %f19, %f0
76961
76962P7368: !_MEMBAR (FP)
76963
76964P7369: !_SWAP [19] (maybe <- 0x3800098) (Int)
76965sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
76966sub %i0, %i3, %i3
76967mov %l4, %l7
76968swap [%i3 + 4], %l7
76969! move %l7(lower) -> %o2(lower)
76970srl %l7, 0, %l3
76971or %l3, %o2, %o2
76972add %l4, 1, %l4
76973
76974P7370: !_SWAP [15] (maybe <- 0x3800099) (Int)
76975sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
76976add %i0, %i2, %i2
76977mov %l4, %o3
76978swap [%i2 + 0], %o3
76979! move %o3(lower) -> %o3(upper)
76980sllx %o3, 32, %o3
76981add %l4, 1, %l4
76982
76983P7371: !_ST [16] (maybe <- 0x380009a) (Int)
76984stw %l4, [%i2 + 4 ]
76985add %l4, 1, %l4
76986
76987P7372: !_ST [3] (maybe <- 0x380009b) (Int)
76988stw %l4, [%i1 + 0 ]
76989add %l4, 1, %l4
76990
76991P7373: !_ST_BINIT [1] (maybe <- 0x380009c) (Int)
76992wr %g0, 0xe2, %asi
76993stwa %l4, [%i0 + 4] %asi
76994add %l4, 1, %l4
76995
76996P7374: !_MEMBAR (Int)
76997
76998P7375: !_BSTC [23] (maybe <- 0x43000066) (FP)
76999wr %g0, 0xe0, %asi
77000sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
77001sub %i0, %i3, %i3
77002! preparing store val #0, next val will be in f32
77003fmovs %f16, %f20
77004fadds %f16, %f17, %f16
77005! preparing store val #1, next val will be in f33
77006fmovs %f16, %f21
77007fadds %f16, %f17, %f16
77008! preparing store val #2, next val will be in f35
77009fmovd %f20, %f32
77010fmovs %f16, %f21
77011fadds %f16, %f17, %f16
77012fmovd %f20, %f34
77013membar #Sync
77014stda %f32, [%i3 + 0 ] %asi
77015
77016P7376: !_MEMBAR (FP)
77017membar #StoreLoad
77018
77019P7377: !_CAS [10] (maybe <- 0x380009d) (Int)
77020sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
77021sub %i0, %i2, %i2
77022add %i2, 4, %o5
77023lduw [%o5], %l6
77024mov %l6, %l7
77025! move %l7(lower) -> %o3(lower)
77026or %l7, %o3, %o3
77027mov %l4, %o4
77028cas [%o5], %l7, %o4
77029! move %o4(lower) -> %o4(upper)
77030sllx %o4, 32, %o4
77031add %l4, 1, %l4
77032
77033P7378: !_MEMBAR (FP)
77034
77035P7379: !_BST [23] (maybe <- 0x43000069) (FP) (Branch target of P7343)
77036wr %g0, 0xf0, %asi
77037! preparing store val #0, next val will be in f32
77038fmovs %f16, %f20
77039fadds %f16, %f17, %f16
77040! preparing store val #1, next val will be in f33
77041fmovs %f16, %f21
77042fadds %f16, %f17, %f16
77043! preparing store val #2, next val will be in f35
77044fmovd %f20, %f32
77045fmovs %f16, %f21
77046fadds %f16, %f17, %f16
77047fmovd %f20, %f34
77048membar #Sync
77049stda %f32, [%i3 + 0 ] %asi
77050ba P7380
77051nop
77052
77053TARGET7343:
77054ba RET7343
77055nop
77056
77057
77058P7380: !_MEMBAR (FP)
77059membar #StoreLoad
77060
77061P7381: !_SWAP [21] (maybe <- 0x380009e) (Int)
77062mov %l4, %o5
77063swap [%i3 + 0], %o5
77064! move %o5(lower) -> %o4(lower)
77065srl %o5, 0, %l6
77066or %l6, %o4, %o4
77067!---- flushing int results buffer----
77068mov %o0, %l5
77069mov %o1, %l5
77070mov %o2, %l5
77071mov %o3, %l5
77072mov %o4, %l5
77073add %l4, 1, %l4
77074
77075P7382: !_MEMBAR (FP)
77076membar #StoreLoad
77077
77078P7383: !_BLD [10] (FP)
77079wr %g0, 0xf0, %asi
77080ldda [%i2 + 0] %asi, %f32
77081membar #Sync
77082! 3 addresses covered
77083fmovd %f32, %f18
77084fmovs %f18, %f1
77085fmovs %f19, %f2
77086fmovd %f34, %f18
77087fmovs %f19, %f3
77088
77089P7384: !_MEMBAR (FP)
77090
77091P7385: !_BSTC [9] (maybe <- 0x4300006c) (FP) (Branch target of P7471)
77092wr %g0, 0xe0, %asi
77093! preparing store val #0, next val will be in f32
77094fmovs %f16, %f20
77095fadds %f16, %f17, %f16
77096! preparing store val #1, next val will be in f33
77097fmovs %f16, %f21
77098fadds %f16, %f17, %f16
77099! preparing store val #2, next val will be in f35
77100fmovd %f20, %f32
77101fmovs %f16, %f21
77102fadds %f16, %f17, %f16
77103fmovd %f20, %f34
77104membar #Sync
77105stda %f32, [%i2 + 0 ] %asi
77106ba P7386
77107nop
77108
77109TARGET7471:
77110ba RET7471
77111nop
77112
77113
77114P7386: !_MEMBAR (FP)
77115membar #StoreLoad
77116
77117P7387: !_DWST [8] (maybe <- 0x380009f) (Int) (CBR) (Branch target of P7161)
77118sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
77119sub %i0, %i3, %i3
77120mov %l4, %o5
77121stx %o5, [%i3 + 8]
77122add %l4, 1, %l4
77123
77124! cbranch
77125andcc %l0, 1, %g0
77126be,pt %xcc, TARGET7387
77127nop
77128RET7387:
77129
77130! lfsr step begin
77131srlx %l0, 1, %l7
77132xnor %l7, %l0, %l7
77133sllx %l7, 63, %l7
77134or %l7, %l0, %l0
77135srlx %l0, 1, %l0
77136
77137ba P7388
77138nop
77139
77140TARGET7161:
77141ba RET7161
77142nop
77143
77144
77145P7388: !_MEMBAR (FP)
77146
77147P7389: !_BST [13] (maybe <- 0x4300006f) (FP)
77148wr %g0, 0xf0, %asi
77149sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
77150sub %i0, %i2, %i2
77151! preparing store val #0, next val will be in f32
77152fmovs %f16, %f20
77153fadds %f16, %f17, %f16
77154! preparing store val #1, next val will be in f33
77155fmovs %f16, %f21
77156fadds %f16, %f17, %f16
77157! preparing store val #2, next val will be in f35
77158fmovd %f20, %f32
77159fmovs %f16, %f21
77160fadds %f16, %f17, %f16
77161fmovd %f20, %f34
77162membar #Sync
77163stda %f32, [%i2 + 0 ] %asi
77164
77165P7390: !_MEMBAR (FP)
77166membar #StoreLoad
77167
77168P7391: !_DWLD [23] (Int)
77169sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
77170sub %i0, %i3, %i3
77171ldx [%i3 + 8], %o0
77172! move %o0(lower) -> %o0(upper)
77173sllx %o0, 32, %o0
77174
77175P7392: !_LDD [4] (Int)
77176ldd [%i1 + 0], %l6
77177! move %l6(lower) -> %o0(lower)
77178or %l6, %o0, %o0
77179! move %l7(lower) -> %o1(upper)
77180sllx %l7, 32, %o1
77181
77182P7393: !_ST [5] (maybe <- 0x38000a0) (Int)
77183stw %l4, [%i1 + 12 ]
77184add %l4, 1, %l4
77185
77186P7394: !_DWLD [9] (Int)
77187sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS1_O), %i2
77188sub %i0, %i2, %i2
77189ldx [%i2 + 0], %l3
77190! move %l3(upper) -> %o1(lower)
77191srlx %l3, 32, %o5
77192or %o5, %o1, %o1
77193! move %l3(lower) -> %o2(upper)
77194sllx %l3, 32, %o2
77195
77196P7395: !_LD [6] (Int)
77197sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
77198sub %i0, %i3, %i3
77199lduw [%i3 + 0], %l7
77200! move %l7(lower) -> %o2(lower)
77201or %l7, %o2, %o2
77202
77203P7396: !_ST_BINIT [23] (maybe <- 0x38000a1) (Int) (Branch target of P7989)
77204wr %g0, 0xe2, %asi
77205sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
77206sub %i0, %i2, %i2
77207stwa %l4, [%i2 + 12] %asi
77208add %l4, 1, %l4
77209ba P7397
77210nop
77211
77212TARGET7989:
77213ba RET7989
77214nop
77215
77216
77217P7397: !_MEMBAR (Int)
77218membar #StoreLoad
77219
77220P7398: !_ST [6] (maybe <- 0x38000a2) (Int)
77221stw %l4, [%i3 + 0 ]
77222add %l4, 1, %l4
77223
77224P7399: !_CASX [9] (maybe <- 0x38000a3) (Int)
77225sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
77226sub %i0, %i3, %i3
77227ldx [%i3], %o3
77228! move %o3(upper) -> %o3(upper)
77229! move %o3(lower) -> %o3(lower)
77230mov %o3, %l7
77231sllx %l4, 32, %o4
77232add %l4, 1, %l4
77233or %l4, %o4, %o4
77234casx [%i3], %l7, %o4
77235! move %o4(upper) -> %o4(upper)
77236! move %o4(lower) -> %o4(lower)
77237!---- flushing int results buffer----
77238mov %o0, %l5
77239mov %o1, %l5
77240mov %o2, %l5
77241mov %o3, %l5
77242mov %o4, %l5
77243add %l4, 1, %l4
77244
77245P7400: !_DWST [19] (maybe <- 0x38000a5) (Int)
77246sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
77247sub %i0, %i2, %i2
77248sllx %l4, 32, %l7
77249add %l4, 1, %l4
77250or %l7, %l4, %l7
77251stx %l7, [%i2 + 0]
77252add %l4, 1, %l4
77253
77254P7401: !_CAS [0] (maybe <- 0x38000a7) (Int)
77255lduw [%i0], %o0
77256mov %o0, %l6
77257! move %l6(lower) -> %o0(upper)
77258sllx %l6, 32, %o0
77259mov %l4, %l3
77260cas [%i0], %l6, %l3
77261! move %l3(lower) -> %o0(lower)
77262srl %l3, 0, %l6
77263or %l6, %o0, %o0
77264add %l4, 1, %l4
77265
77266P7402: !_CASX [15] (maybe <- 0x38000a8) (Int)
77267sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
77268add %i0, %i3, %i3
77269ldx [%i3], %o1
77270! move %o1(upper) -> %o1(upper)
77271! move %o1(lower) -> %o1(lower)
77272mov %o1, %l6
77273sllx %l4, 32, %o2
77274add %l4, 1, %l4
77275or %l4, %o2, %o2
77276casx [%i3], %l6, %o2
77277! move %o2(upper) -> %o2(upper)
77278! move %o2(lower) -> %o2(lower)
77279add %l4, 1, %l4
77280
77281P7403: !_ST_BINIT [6] (maybe <- 0x38000aa) (Int)
77282wr %g0, 0xe2, %asi
77283sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
77284sub %i0, %i2, %i2
77285stwa %l4, [%i2 + 0] %asi
77286add %l4, 1, %l4
77287
77288P7404: !_MEMBAR (Int)
77289membar #StoreLoad
77290
77291P7405: !_LDD [2] (Int)
77292ldd [%i0 + 8], %l6
77293! move %l7(lower) -> %o3(upper)
77294sllx %l7, 32, %o3
77295
77296P7406: !_ST_BINIT [11] (maybe <- 0x38000ab) (Int)
77297wr %g0, 0xe2, %asi
77298sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
77299sub %i0, %i3, %i3
77300stwa %l4, [%i3 + 12] %asi
77301add %l4, 1, %l4
77302
77303P7407: !_MEMBAR (Int)
77304
77305P7408: !_BST [4] (maybe <- 0x43000072) (FP)
77306wr %g0, 0xf0, %asi
77307! preparing store val #0, next val will be in f32
77308fmovs %f16, %f20
77309fadds %f16, %f17, %f16
77310! preparing store val #1, next val will be in f33
77311fmovs %f16, %f21
77312fadds %f16, %f17, %f16
77313! preparing store val #2, next val will be in f35
77314fmovd %f20, %f32
77315fmovs %f16, %f21
77316fadds %f16, %f17, %f16
77317fmovd %f20, %f34
77318membar #Sync
77319stda %f32, [%i1 + 0 ] %asi
77320
77321P7409: !_MEMBAR (FP)
77322
77323P7410: !_BST [2] (maybe <- 0x43000075) (FP)
77324wr %g0, 0xf0, %asi
77325! preparing store val #0, next val will be in f32
77326fmovs %f16, %f20
77327fadds %f16, %f17, %f16
77328! preparing store val #1, next val will be in f33
77329fmovs %f16, %f21
77330fadds %f16, %f17, %f16
77331! preparing store val #2, next val will be in f35
77332fmovd %f20, %f32
77333fmovs %f16, %f21
77334fadds %f16, %f17, %f16
77335fmovd %f20, %f34
77336membar #Sync
77337stda %f32, [%i0 + 0 ] %asi
77338
77339P7411: !_MEMBAR (FP)
77340membar #StoreLoad
77341
77342P7412: !_DWST [16] (maybe <- 0x38000ac) (Int)
77343sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
77344add %i0, %i2, %i2
77345sllx %l4, 32, %l6
77346add %l4, 1, %l4
77347or %l6, %l4, %l6
77348stx %l6, [%i2 + 0]
77349add %l4, 1, %l4
77350
77351P7413: !_PREFETCH [14] (Int)
77352sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
77353sub %i0, %i3, %i3
77354prefetch [%i3 + 12], 16
77355
77356P7414: !_PREFETCH [10] (Int) (LE)
77357wr %g0, 0x88, %asi
77358sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
77359sub %i0, %i2, %i2
77360prefetcha [%i2 + 4] %asi, 31
77361
77362P7415: !_CAS [20] (maybe <- 0x38000ae) (Int)
77363sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
77364sub %i0, %i3, %i3
77365add %i3, 12, %l6
77366lduw [%l6], %o5
77367mov %o5, %l3
77368! move %l3(lower) -> %o3(lower)
77369or %l3, %o3, %o3
77370mov %l4, %o4
77371cas [%l6], %l3, %o4
77372! move %o4(lower) -> %o4(upper)
77373sllx %o4, 32, %o4
77374add %l4, 1, %l4
77375
77376P7416: !_LD [20] (Int)
77377lduw [%i3 + 12], %l6
77378! move %l6(lower) -> %o4(lower)
77379or %l6, %o4, %o4
77380!---- flushing int results buffer----
77381mov %o0, %l5
77382mov %o1, %l5
77383mov %o2, %l5
77384mov %o3, %l5
77385mov %o4, %l5
77386
77387P7417: !_MEMBAR (FP)
77388membar #StoreLoad
77389
77390P7418: !_BLD [23] (FP)
77391wr %g0, 0xf0, %asi
77392sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
77393sub %i0, %i2, %i2
77394ldda [%i2 + 0] %asi, %f32
77395membar #Sync
77396! 3 addresses covered
77397fmovd %f32, %f4
77398fmovd %f34, %f18
77399fmovs %f19, %f6
77400
77401P7419: !_MEMBAR (FP)
77402
77403P7420: !_DWLD [0] (Int)
77404ldx [%i0 + 0], %o0
77405! move %o0(upper) -> %o0(upper)
77406! move %o0(lower) -> %o0(lower)
77407
77408P7421: !_DWLD [5] (FP)
77409ldd [%i1 + 8], %f18
77410! 1 addresses covered
77411fmovs %f19, %f7
77412
77413P7422: !_DWLD [1] (Int)
77414ldx [%i0 + 0], %o1
77415! move %o1(upper) -> %o1(upper)
77416! move %o1(lower) -> %o1(lower)
77417
77418P7423: !_DWST_BINIT [13] (maybe <- 0x38000af) (Int)
77419wr %g0, 0xe2, %asi
77420sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
77421sub %i0, %i3, %i3
77422sllx %l4, 32, %l7
77423add %l4, 1, %l4
77424or %l7, %l4, %l7
77425stxa %l7, [%i3 + 0] %asi
77426add %l4, 1, %l4
77427
77428P7424: !_MEMBAR (Int)
77429membar #StoreLoad
77430
77431P7425: !_LDD [18] (Int)
77432sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
77433sub %i0, %i2, %i2
77434ldd [%i2 + 0], %l6
77435! move %l6(lower) -> %o2(upper)
77436sllx %l6, 32, %o2
77437! move %l7(lower) -> %o2(lower)
77438or %l7, %o2, %o2
77439
77440P7426: !_LDD [3] (Int)
77441ldd [%i1 + 0], %l6
77442! move %l6(lower) -> %o3(upper)
77443sllx %l6, 32, %o3
77444! move %l7(lower) -> %o3(lower)
77445or %l7, %o3, %o3
77446
77447P7427: !_SWAP [18] (maybe <- 0x38000b1) (Int)
77448mov %l4, %o4
77449swap [%i2 + 0], %o4
77450! move %o4(lower) -> %o4(upper)
77451sllx %o4, 32, %o4
77452add %l4, 1, %l4
77453
77454P7428: !_SWAP [7] (maybe <- 0x38000b2) (Int)
77455sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
77456sub %i0, %i3, %i3
77457mov %l4, %l6
77458swap [%i3 + 4], %l6
77459! move %l6(lower) -> %o4(lower)
77460srl %l6, 0, %o5
77461or %o5, %o4, %o4
77462!---- flushing int results buffer----
77463mov %o0, %l5
77464mov %o1, %l5
77465mov %o2, %l5
77466mov %o3, %l5
77467mov %o4, %l5
77468add %l4, 1, %l4
77469
77470P7429: !_MEMBAR (FP)
77471membar #StoreLoad
77472
77473P7430: !_BLD [3] (FP)
77474wr %g0, 0xf0, %asi
77475ldda [%i1 + 0] %asi, %f32
77476membar #Sync
77477! 3 addresses covered
77478fmovd %f32, %f8
77479fmovd %f34, %f18
77480fmovs %f19, %f10
77481
77482P7431: !_MEMBAR (FP)
77483
77484P7432: !_BSTC [8] (maybe <- 0x43000078) (FP)
77485wr %g0, 0xe0, %asi
77486! preparing store val #0, next val will be in f32
77487fmovs %f16, %f20
77488fadds %f16, %f17, %f16
77489! preparing store val #1, next val will be in f33
77490fmovs %f16, %f21
77491fadds %f16, %f17, %f16
77492! preparing store val #2, next val will be in f35
77493fmovd %f20, %f32
77494fmovs %f16, %f21
77495fadds %f16, %f17, %f16
77496fmovd %f20, %f34
77497membar #Sync
77498stda %f32, [%i3 + 0 ] %asi
77499
77500P7433: !_MEMBAR (FP)
77501membar #StoreLoad
77502
77503P7434: !_LD [13] (Int)
77504sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
77505sub %i0, %i2, %i2
77506lduw [%i2 + 4], %o0
77507! move %o0(lower) -> %o0(upper)
77508sllx %o0, 32, %o0
77509
77510P7435: !_SWAP [9] (maybe <- 0x38000b3) (Int)
77511sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
77512sub %i0, %i3, %i3
77513mov %l4, %l6
77514swap [%i3 + 0], %l6
77515! move %l6(lower) -> %o0(lower)
77516srl %l6, 0, %o5
77517or %o5, %o0, %o0
77518add %l4, 1, %l4
77519
77520P7436: !_MEMBAR (FP) (Branch target of P7880)
77521ba P7437
77522nop
77523
77524TARGET7880:
77525ba RET7880
77526nop
77527
77528
77529P7437: !_BSTC [19] (maybe <- 0x4300007b) (FP)
77530wr %g0, 0xe0, %asi
77531sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
77532sub %i0, %i2, %i2
77533! preparing store val #0, next val will be in f32
77534fmovs %f16, %f20
77535fadds %f16, %f17, %f16
77536! preparing store val #1, next val will be in f33
77537fmovs %f16, %f21
77538fadds %f16, %f17, %f16
77539! preparing store val #2, next val will be in f35
77540fmovd %f20, %f32
77541fmovs %f16, %f21
77542fadds %f16, %f17, %f16
77543fmovd %f20, %f34
77544membar #Sync
77545stda %f32, [%i2 + 0 ] %asi
77546
77547P7438: !_MEMBAR (FP)
77548membar #StoreLoad
77549
77550P7439: !_LDD [22] (Int)
77551sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
77552sub %i0, %i3, %i3
77553ldd [%i3 + 0], %l6
77554! move %l6(lower) -> %o1(upper)
77555sllx %l6, 32, %o1
77556! move %l7(lower) -> %o1(lower)
77557or %l7, %o1, %o1
77558
77559P7440: !_LDD [23] (Int)
77560ldd [%i3 + 8], %l6
77561! move %l7(lower) -> %o2(upper)
77562sllx %l7, 32, %o2
77563
77564P7441: !_CASX [20] (maybe <- 0x38000b4) (Int)
77565add %i2, 8, %l6
77566ldx [%l6], %o5
77567! move %o5(upper) -> %o2(lower)
77568srlx %o5, 32, %l3
77569or %l3, %o2, %o2
77570! move %o5(lower) -> %o3(upper)
77571sllx %o5, 32, %o3
77572mov %o5, %l3
77573mov %l4, %o5
77574casx [%l6], %l3, %o5
77575! move %o5(upper) -> %o3(lower)
77576srlx %o5, 32, %l3
77577or %l3, %o3, %o3
77578! move %o5(lower) -> %o4(upper)
77579sllx %o5, 32, %o4
77580add %l4, 1, %l4
77581
77582P7442: !_MEMBAR (FP)
77583
77584P7443: !_BSTC [16] (maybe <- 0x4300007e) (FP)
77585wr %g0, 0xe0, %asi
77586sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
77587add %i0, %i2, %i2
77588! preparing store val #0, next val will be in f32
77589fmovs %f16, %f20
77590fadds %f16, %f17, %f16
77591! preparing store val #1, next val will be in f33
77592fmovs %f16, %f21
77593fadds %f16, %f17, %f16
77594! preparing store val #2, next val will be in f35
77595fmovd %f20, %f32
77596fmovs %f16, %f21
77597fadds %f16, %f17, %f16
77598fmovd %f20, %f34
77599membar #Sync
77600stda %f32, [%i2 + 0 ] %asi
77601
77602P7444: !_MEMBAR (FP)
77603membar #StoreLoad
77604
77605P7445: !_PREFETCH [9] (Int)
77606sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
77607sub %i0, %i3, %i3
77608prefetch [%i3 + 0], 30
77609
77610P7446: !_MEMBAR (FP)
77611
77612P7447: !_BST [5] (maybe <- 0x43000081) (FP)
77613wr %g0, 0xf0, %asi
77614! preparing store val #0, next val will be in f32
77615fmovs %f16, %f20
77616fadds %f16, %f17, %f16
77617! preparing store val #1, next val will be in f33
77618fmovs %f16, %f21
77619fadds %f16, %f17, %f16
77620! preparing store val #2, next val will be in f35
77621fmovd %f20, %f32
77622fmovs %f16, %f21
77623fadds %f16, %f17, %f16
77624fmovd %f20, %f34
77625membar #Sync
77626stda %f32, [%i1 + 0 ] %asi
77627
77628P7448: !_MEMBAR (FP)
77629membar #StoreLoad
77630
77631P7449: !_ST [1] (maybe <- 0x38000b5) (Int)
77632stw %l4, [%i0 + 4 ]
77633add %l4, 1, %l4
77634
77635P7450: !_LDD [4] (Int)
77636ldd [%i1 + 0], %l6
77637! move %l6(lower) -> %o4(lower)
77638or %l6, %o4, %o4
77639!---- flushing int results buffer----
77640mov %o0, %l5
77641mov %o1, %l5
77642mov %o2, %l5
77643mov %o3, %l5
77644mov %o4, %l5
77645! move %l7(lower) -> %o0(upper)
77646sllx %l7, 32, %o0
77647
77648P7451: !_CAS [21] (maybe <- 0x38000b6) (Int)
77649sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
77650sub %i0, %i2, %i2
77651lduw [%i2], %o5
77652mov %o5, %l3
77653! move %l3(lower) -> %o0(lower)
77654or %l3, %o0, %o0
77655mov %l4, %o1
77656cas [%i2], %l3, %o1
77657! move %o1(lower) -> %o1(upper)
77658sllx %o1, 32, %o1
77659add %l4, 1, %l4
77660
77661P7452: !_SWAP [17] (maybe <- 0x38000b7) (Int)
77662sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
77663add %i0, %i3, %i3
77664mov %l4, %l7
77665swap [%i3 + 12], %l7
77666! move %l7(lower) -> %o1(lower)
77667srl %l7, 0, %l3
77668or %l3, %o1, %o1
77669add %l4, 1, %l4
77670
77671P7453: !_DWST [6] (maybe <- 0x38000b8) (Int)
77672sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
77673sub %i0, %i2, %i2
77674sllx %l4, 32, %o5
77675add %l4, 1, %l4
77676or %o5, %l4, %o5
77677stx %o5, [%i2 + 0]
77678add %l4, 1, %l4
77679
77680P7454: !_LD [10] (Int)
77681sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
77682sub %i0, %i3, %i3
77683lduw [%i3 + 4], %o2
77684! move %o2(lower) -> %o2(upper)
77685sllx %o2, 32, %o2
77686
77687P7455: !_REPLACEMENT [20] (Int)
77688sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
77689sub %i0, %i2, %i2
77690sethi %hi(0x20000), %l3
77691ld [%i2+12], %l7
77692st %l7, [%i2+12]
77693add %i2, %l3, %l6
77694ld [%l6+12], %l7
77695st %l7, [%l6+12]
77696add %l6, %l3, %l6
77697ld [%l6+12], %l7
77698st %l7, [%l6+12]
77699add %l6, %l3, %l6
77700ld [%l6+12], %l7
77701st %l7, [%l6+12]
77702add %l6, %l3, %l6
77703ld [%l6+12], %l7
77704st %l7, [%l6+12]
77705add %l6, %l3, %l6
77706ld [%l6+12], %l7
77707st %l7, [%l6+12]
77708add %l6, %l3, %l6
77709ld [%l6+12], %l7
77710st %l7, [%l6+12]
77711add %l6, %l3, %l6
77712ld [%l6+12], %l7
77713st %l7, [%l6+12]
77714
77715P7456: !_PREFETCH [16] (Int)
77716sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
77717add %i0, %i3, %i3
77718prefetch [%i3 + 4], 23
77719
77720P7457: !_CASX [20] (maybe <- 0x38000ba) (Int)
77721sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
77722sub %i0, %i2, %i2
77723add %i2, 8, %l3
77724ldx [%l3], %l7
77725! move %l7(upper) -> %o2(lower)
77726srlx %l7, 32, %o5
77727or %o5, %o2, %o2
77728! move %l7(lower) -> %o3(upper)
77729sllx %l7, 32, %o3
77730mov %l7, %o5
77731mov %l4, %l7
77732casx [%l3], %o5, %l7
77733! move %l7(upper) -> %o3(lower)
77734srlx %l7, 32, %o5
77735or %o5, %o3, %o3
77736! move %l7(lower) -> %o4(upper)
77737sllx %l7, 32, %o4
77738add %l4, 1, %l4
77739
77740P7458: !_MEMBAR (FP)
77741
77742P7459: !_BST [10] (maybe <- 0x43000084) (FP)
77743wr %g0, 0xf0, %asi
77744sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
77745sub %i0, %i3, %i3
77746! preparing store val #0, next val will be in f32
77747fmovs %f16, %f20
77748fadds %f16, %f17, %f16
77749! preparing store val #1, next val will be in f33
77750fmovs %f16, %f21
77751fadds %f16, %f17, %f16
77752! preparing store val #2, next val will be in f35
77753fmovd %f20, %f32
77754fmovs %f16, %f21
77755fadds %f16, %f17, %f16
77756fmovd %f20, %f34
77757membar #Sync
77758stda %f32, [%i3 + 0 ] %asi
77759
77760P7460: !_MEMBAR (FP)
77761membar #StoreLoad
77762
77763P7461: !_LDD [15] (Int)
77764sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
77765add %i0, %i2, %i2
77766ldd [%i2 + 0], %l6
77767! move %l6(lower) -> %o4(lower)
77768or %l6, %o4, %o4
77769!---- flushing int results buffer----
77770mov %o0, %l5
77771mov %o1, %l5
77772mov %o2, %l5
77773mov %o3, %l5
77774mov %o4, %l5
77775! move %l7(lower) -> %o0(upper)
77776sllx %l7, 32, %o0
77777
77778P7462: !_CASX [5] (maybe <- 0x38000bb) (Int)
77779add %i1, 8, %l6
77780ldx [%l6], %o5
77781! move %o5(upper) -> %o0(lower)
77782srlx %o5, 32, %l3
77783or %l3, %o0, %o0
77784! move %o5(lower) -> %o1(upper)
77785sllx %o5, 32, %o1
77786mov %o5, %l3
77787mov %l4, %o5
77788casx [%l6], %l3, %o5
77789! move %o5(upper) -> %o1(lower)
77790srlx %o5, 32, %l3
77791or %l3, %o1, %o1
77792! move %o5(lower) -> %o2(upper)
77793sllx %o5, 32, %o2
77794add %l4, 1, %l4
77795
77796P7463: !_ST [3] (maybe <- 0x38000bc) (Int)
77797!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #3
77798!Logical addr: 3
77799
77800sethi %hi(0x200000), %l3
77801sub %i1, %l3, %i1
77802stw %l4, [%i1 + 0 ]
77803add %l4, 1, %l4
77804
77805P7464: !_LD [23] (Int)
77806sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
77807sub %i0, %i3, %i3
77808lduw [%i3 + 12], %l6
77809! move %l6(lower) -> %o2(lower)
77810or %l6, %o2, %o2
77811
77812P7465: !_LDD [9] (Int)
77813sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
77814sub %i0, %i2, %i2
77815ldd [%i2 + 0], %l6
77816! move %l6(lower) -> %o3(upper)
77817sllx %l6, 32, %o3
77818! move %l7(lower) -> %o3(lower)
77819or %l7, %o3, %o3
77820
77821P7466: !_CASX [1] (maybe <- 0x38000bd) (Int)
77822ldx [%i0], %o4
77823! move %o4(upper) -> %o4(upper)
77824! move %o4(lower) -> %o4(lower)
77825!---- flushing int results buffer----
77826mov %o0, %l5
77827mov %o1, %l5
77828mov %o2, %l5
77829mov %o3, %l5
77830mov %o4, %l5
77831mov %o4, %l3
77832sllx %l4, 32, %o0
77833add %l4, 1, %l4
77834or %l4, %o0, %o0
77835casx [%i0], %l3, %o0
77836! move %o0(upper) -> %o0(upper)
77837! move %o0(lower) -> %o0(lower)
77838add %l4, 1, %l4
77839
77840P7467: !_MEMBAR (FP)
77841
77842P7468: !_BSTC [3] (maybe <- 0x43000087) (FP)
77843wr %g0, 0xe0, %asi
77844! preparing store val #0, next val will be in f32
77845fmovs %f16, %f20
77846fadds %f16, %f17, %f16
77847! preparing store val #1, next val will be in f33
77848fmovs %f16, %f21
77849fadds %f16, %f17, %f16
77850! preparing store val #2, next val will be in f35
77851fmovd %f20, %f32
77852fmovs %f16, %f21
77853fadds %f16, %f17, %f16
77854fmovd %f20, %f34
77855membar #Sync
77856stda %f32, [%i1 + 0 ] %asi
77857
77858P7469: !_MEMBAR (FP)
77859membar #StoreLoad
77860
77861P7470: !_LDD [13] (Int)
77862sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
77863sub %i0, %i3, %i3
77864ldd [%i3 + 0], %l6
77865! move %l6(lower) -> %o1(upper)
77866sllx %l6, 32, %o1
77867! move %l7(lower) -> %o1(lower)
77868or %l7, %o1, %o1
77869
77870P7471: !_LDD [4] (Int) (CBR)
77871ldd [%i1 + 0], %l6
77872! move %l6(lower) -> %o2(upper)
77873sllx %l6, 32, %o2
77874! move %l7(lower) -> %o2(lower)
77875or %l7, %o2, %o2
77876
77877! cbranch
77878andcc %l0, 1, %g0
77879be,pt %xcc, TARGET7471
77880nop
77881RET7471:
77882
77883! lfsr step begin
77884srlx %l0, 1, %l3
77885xnor %l3, %l0, %l3
77886sllx %l3, 63, %l3
77887or %l3, %l0, %l0
77888srlx %l0, 1, %l0
77889
77890
77891P7472: !_LDD [16] (Int)
77892sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
77893add %i0, %i2, %i2
77894ldd [%i2 + 0], %l6
77895! move %l6(lower) -> %o3(upper)
77896sllx %l6, 32, %o3
77897! move %l7(lower) -> %o3(lower)
77898or %l7, %o3, %o3
77899
77900P7473: !_SWAP [11] (maybe <- 0x38000bf) (Int)
77901sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
77902sub %i0, %i3, %i3
77903mov %l4, %o4
77904swap [%i3 + 12], %o4
77905! move %o4(lower) -> %o4(upper)
77906sllx %o4, 32, %o4
77907add %l4, 1, %l4
77908
77909P7474: !_LD [21] (Int)
77910sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
77911sub %i0, %i2, %i2
77912lduw [%i2 + 0], %l3
77913! move %l3(lower) -> %o4(lower)
77914or %l3, %o4, %o4
77915!---- flushing int results buffer----
77916mov %o0, %l5
77917mov %o1, %l5
77918mov %o2, %l5
77919mov %o3, %l5
77920mov %o4, %l5
77921
77922P7475: !_REPLACEMENT [16] (Int)
77923sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
77924sub %i0, %i3, %i3
77925sethi %hi(0x20000), %l6
77926ld [%i3+4], %o5
77927st %o5, [%i3+4]
77928add %i3, %l6, %l7
77929ld [%l7+4], %o5
77930st %o5, [%l7+4]
77931add %l7, %l6, %l7
77932ld [%l7+4], %o5
77933st %o5, [%l7+4]
77934add %l7, %l6, %l7
77935ld [%l7+4], %o5
77936st %o5, [%l7+4]
77937add %l7, %l6, %l7
77938ld [%l7+4], %o5
77939st %o5, [%l7+4]
77940add %l7, %l6, %l7
77941ld [%l7+4], %o5
77942st %o5, [%l7+4]
77943add %l7, %l6, %l7
77944ld [%l7+4], %o5
77945st %o5, [%l7+4]
77946add %l7, %l6, %l7
77947ld [%l7+4], %o5
77948st %o5, [%l7+4]
77949
77950P7476: !_LDD [18] (Int)
77951sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
77952sub %i0, %i2, %i2
77953ldd [%i2 + 0], %l6
77954! move %l6(lower) -> %o0(upper)
77955sllx %l6, 32, %o0
77956! move %l7(lower) -> %o0(lower)
77957or %l7, %o0, %o0
77958
77959P7477: !_ST_BINIT [0] (maybe <- 0x38000c0) (Int) (LE)
77960wr %g0, 0xea, %asi
77961! Change single-word-level endianess (big endian <-> little endian)
77962sethi %hi(0xff00ff00), %l6
77963or %l6, %lo(0xff00ff00), %l6
77964and %l4, %l6, %l7
77965srl %l7, 8, %l7
77966sll %l4, 8, %l3
77967and %l3, %l6, %l3
77968or %l3, %l7, %l3
77969srl %l3, 16, %l7
77970sll %l3, 16, %l3
77971srl %l3, 0, %l3
77972or %l3, %l7, %l3
77973stwa %l3, [%i0 + 0] %asi
77974add %l4, 1, %l4
77975
77976P7478: !_MEMBAR (Int) (LE)
77977membar #StoreLoad
77978
77979P7479: !_ST_BINIT [2] (maybe <- 0x38000c1) (Int)
77980wr %g0, 0xe2, %asi
77981stwa %l4, [%i0 + 12] %asi
77982add %l4, 1, %l4
77983
77984P7480: !_MEMBAR (Int)
77985membar #StoreLoad
77986
77987P7481: !_PREFETCH [18] (Int)
77988prefetch [%i2 + 0], 22
77989
77990P7482: !_SWAP [22] (maybe <- 0x38000c2) (Int)
77991sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
77992sub %i0, %i3, %i3
77993mov %l4, %o1
77994swap [%i3 + 4], %o1
77995! move %o1(lower) -> %o1(upper)
77996sllx %o1, 32, %o1
77997add %l4, 1, %l4
77998
77999P7483: !_DWST [23] (maybe <- 0x38000c3) (Int)
78000mov %l4, %l6
78001stx %l6, [%i3 + 8]
78002add %l4, 1, %l4
78003
78004P7484: !_LD [5] (Int)
78005lduw [%i1 + 12], %l6
78006! move %l6(lower) -> %o1(lower)
78007or %l6, %o1, %o1
78008
78009P7485: !_REPLACEMENT [20] (Int)
78010sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
78011sub %i0, %i2, %i2
78012sethi %hi(0x20000), %l7
78013ld [%i2+12], %l3
78014st %l3, [%i2+12]
78015add %i2, %l7, %o5
78016ld [%o5+12], %l3
78017st %l3, [%o5+12]
78018add %o5, %l7, %o5
78019ld [%o5+12], %l3
78020st %l3, [%o5+12]
78021add %o5, %l7, %o5
78022ld [%o5+12], %l3
78023st %l3, [%o5+12]
78024add %o5, %l7, %o5
78025ld [%o5+12], %l3
78026st %l3, [%o5+12]
78027add %o5, %l7, %o5
78028ld [%o5+12], %l3
78029st %l3, [%o5+12]
78030add %o5, %l7, %o5
78031ld [%o5+12], %l3
78032st %l3, [%o5+12]
78033add %o5, %l7, %o5
78034ld [%o5+12], %l3
78035st %l3, [%o5+12]
78036
78037P7486: !_CASX [22] (maybe <- 0x38000c4) (Int)
78038ldx [%i3], %o2
78039! move %o2(upper) -> %o2(upper)
78040! move %o2(lower) -> %o2(lower)
78041mov %o2, %l6
78042sllx %l4, 32, %o3
78043add %l4, 1, %l4
78044or %l4, %o3, %o3
78045casx [%i3], %l6, %o3
78046! move %o3(upper) -> %o3(upper)
78047! move %o3(lower) -> %o3(lower)
78048add %l4, 1, %l4
78049
78050P7487: !_DWLD [5] (Int)
78051ldx [%i1 + 8], %o4
78052! move %o4(lower) -> %o4(upper)
78053sllx %o4, 32, %o4
78054
78055P7488: !_LDD [10] (Int)
78056sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
78057sub %i0, %i3, %i3
78058ldd [%i3 + 0], %l6
78059! move %l6(lower) -> %o4(lower)
78060or %l6, %o4, %o4
78061!---- flushing int results buffer----
78062mov %o0, %l5
78063mov %o1, %l5
78064mov %o2, %l5
78065mov %o3, %l5
78066mov %o4, %l5
78067! move %l7(lower) -> %o0(upper)
78068sllx %l7, 32, %o0
78069
78070P7489: !_LD [1] (Int)
78071lduw [%i0 + 4], %l6
78072! move %l6(lower) -> %o0(lower)
78073or %l6, %o0, %o0
78074
78075P7490: !_DWLD [7] (Int)
78076sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
78077sub %i0, %i2, %i2
78078ldx [%i2 + 0], %o1
78079! move %o1(upper) -> %o1(upper)
78080! move %o1(lower) -> %o1(lower)
78081
78082P7491: !_DWST [12] (maybe <- 0x4300008a) (FP)
78083sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
78084sub %i0, %i3, %i3
78085! preparing store val #0, next val will be in f20
78086fmovs %f16, %f20
78087fadds %f16, %f17, %f16
78088! preparing store val #1, next val will be in f21
78089fmovs %f16, %f21
78090fadds %f16, %f17, %f16
78091std %f20, [%i3 + 0]
78092
78093P7492: !_MEMBAR (FP)
78094
78095P7493: !_BST [13] (maybe <- 0x4300008c) (FP)
78096wr %g0, 0xf0, %asi
78097! preparing store val #0, next val will be in f32
78098fmovs %f16, %f20
78099fadds %f16, %f17, %f16
78100! preparing store val #1, next val will be in f33
78101fmovs %f16, %f21
78102fadds %f16, %f17, %f16
78103! preparing store val #2, next val will be in f35
78104fmovd %f20, %f32
78105fmovs %f16, %f21
78106fadds %f16, %f17, %f16
78107fmovd %f20, %f34
78108membar #Sync
78109stda %f32, [%i3 + 0 ] %asi
78110
78111P7494: !_MEMBAR (FP)
78112membar #StoreLoad
78113
78114P7495: !_DWST [6] (maybe <- 0x38000c6) (Int)
78115sllx %l4, 32, %l7
78116add %l4, 1, %l4
78117or %l7, %l4, %l7
78118stx %l7, [%i2 + 0]
78119add %l4, 1, %l4
78120
78121P7496: !_REPLACEMENT [15] (Int)
78122sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
78123sub %i0, %i2, %i2
78124sethi %hi(0x20000), %l6
78125ld [%i2+0], %o5
78126st %o5, [%i2+0]
78127add %i2, %l6, %l7
78128ld [%l7+0], %o5
78129st %o5, [%l7+0]
78130add %l7, %l6, %l7
78131ld [%l7+0], %o5
78132st %o5, [%l7+0]
78133add %l7, %l6, %l7
78134ld [%l7+0], %o5
78135st %o5, [%l7+0]
78136add %l7, %l6, %l7
78137ld [%l7+0], %o5
78138st %o5, [%l7+0]
78139add %l7, %l6, %l7
78140ld [%l7+0], %o5
78141st %o5, [%l7+0]
78142add %l7, %l6, %l7
78143ld [%l7+0], %o5
78144st %o5, [%l7+0]
78145add %l7, %l6, %l7
78146ld [%l7+0], %o5
78147st %o5, [%l7+0]
78148
78149P7497: !_DWST_BINIT [2] (maybe <- 0x38000c8) (Int) (Branch target of P7883)
78150wr %g0, 0xe2, %asi
78151mov %l4, %l3
78152stxa %l3, [%i0 + 8] %asi
78153add %l4, 1, %l4
78154ba P7498
78155nop
78156
78157TARGET7883:
78158ba RET7883
78159nop
78160
78161
78162P7498: !_MEMBAR (Int)
78163membar #StoreLoad
78164
78165P7499: !_LD [15] (Int)
78166sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
78167add %i0, %i3, %i3
78168lduw [%i3 + 0], %o2
78169! move %o2(lower) -> %o2(upper)
78170sllx %o2, 32, %o2
78171
78172P7500: !_SWAP [21] (maybe <- 0x38000c9) (Int) (Branch target of P7835)
78173sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
78174sub %i0, %i2, %i2
78175mov %l4, %o5
78176swap [%i2 + 0], %o5
78177! move %o5(lower) -> %o2(lower)
78178srl %o5, 0, %l6
78179or %l6, %o2, %o2
78180add %l4, 1, %l4
78181ba P7501
78182nop
78183
78184TARGET7835:
78185ba RET7835
78186nop
78187
78188
78189P7501: !_PREFETCH [22] (Int)
78190prefetch [%i2 + 4], 19
78191
78192P7502: !_LDD [15] (Int)
78193ldd [%i3 + 0], %l6
78194! move %l6(lower) -> %o3(upper)
78195sllx %l6, 32, %o3
78196! move %l7(lower) -> %o3(lower)
78197or %l7, %o3, %o3
78198
78199P7503: !_PREFETCH [21] (Int)
78200prefetch [%i2 + 0], 3
78201
78202P7504: !_SWAP [5] (maybe <- 0x38000ca) (Int)
78203mov %l4, %o4
78204swap [%i1 + 12], %o4
78205! move %o4(lower) -> %o4(upper)
78206sllx %o4, 32, %o4
78207add %l4, 1, %l4
78208
78209P7505: !_MEMBAR (FP)
78210
78211P7506: !_BST [19] (maybe <- 0x4300008f) (FP)
78212wr %g0, 0xf0, %asi
78213sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
78214sub %i0, %i3, %i3
78215! preparing store val #0, next val will be in f32
78216fmovs %f16, %f20
78217fadds %f16, %f17, %f16
78218! preparing store val #1, next val will be in f33
78219fmovs %f16, %f21
78220fadds %f16, %f17, %f16
78221! preparing store val #2, next val will be in f35
78222fmovd %f20, %f32
78223fmovs %f16, %f21
78224fadds %f16, %f17, %f16
78225fmovd %f20, %f34
78226membar #Sync
78227stda %f32, [%i3 + 0 ] %asi
78228
78229P7507: !_MEMBAR (FP)
78230membar #StoreLoad
78231
78232P7508: !_DWST_BINIT [15] (maybe <- 0x38000cb) (Int)
78233wr %g0, 0xe2, %asi
78234sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
78235add %i0, %i2, %i2
78236sllx %l4, 32, %l7
78237add %l4, 1, %l4
78238or %l7, %l4, %l7
78239stxa %l7, [%i2 + 0] %asi
78240add %l4, 1, %l4
78241
78242P7509: !_MEMBAR (Int)
78243membar #StoreLoad
78244
78245P7510: !_DWLD [4] (FP)
78246ldd [%i1 + 0], %f18
78247! 2 addresses covered
78248fmovs %f18, %f11
78249fmovs %f19, %f12
78250
78251P7511: !_DWST [7] (maybe <- 0x38000cd) (Int)
78252sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
78253sub %i0, %i3, %i3
78254sllx %l4, 32, %l6
78255add %l4, 1, %l4
78256or %l6, %l4, %l6
78257stx %l6, [%i3 + 0]
78258add %l4, 1, %l4
78259
78260P7512: !_DWST [7] (maybe <- 0x38000cf) (Int)
78261sllx %l4, 32, %l3
78262add %l4, 1, %l4
78263or %l3, %l4, %l3
78264stx %l3, [%i3 + 0]
78265add %l4, 1, %l4
78266
78267P7513: !_DWST [22] (maybe <- 0x38000d1) (Int) (LE)
78268wr %g0, 0x88, %asi
78269sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
78270sub %i0, %i2, %i2
78271sllx %l4, 32, %o5
78272add %l4, 1, %l4
78273or %o5, %l4, %l3
78274! Change double-word-level endianess (big endian <-> little endian)
78275sethi %hi(0xff00ff00), %l6
78276or %l6, %lo(0xff00ff00), %l6
78277sllx %l6, 32, %o5
78278or %l6, %o5, %l6
78279and %l3, %l6, %o5
78280srlx %o5, 8, %o5
78281sllx %l3, 8, %l3
78282and %l3, %l6, %l3
78283or %l3, %o5, %l3
78284sethi %hi(0xffff0000), %l6
78285srlx %l3, 16, %o5
78286andn %o5, %l6, %o5
78287andn %l3, %l6, %l3
78288sllx %l3, 16, %l3
78289or %l3, %o5, %l3
78290srlx %l3, 32, %o5
78291sllx %l3, 32, %l3
78292or %l3, %o5, %o5
78293stxa %o5, [%i2 + 0 ] %asi
78294add %l4, 1, %l4
78295
78296P7514: !_MEMBAR (FP)
78297membar #StoreLoad
78298
78299P7515: !_BLD [0] (FP)
78300wr %g0, 0xf0, %asi
78301ldda [%i0 + 0] %asi, %f32
78302membar #Sync
78303! 3 addresses covered
78304fmovd %f32, %f18
78305fmovs %f18, %f13
78306fmovs %f19, %f14
78307fmovd %f34, %f18
78308fmovs %f19, %f15
78309!---- flushing fp results buffer to %f30 ----
78310fmovd %f0, %f30
78311fmovd %f2, %f30
78312fmovd %f4, %f30
78313fmovd %f6, %f30
78314fmovd %f8, %f30
78315fmovd %f10, %f30
78316fmovd %f12, %f30
78317fmovd %f14, %f30
78318!--
78319
78320P7516: !_MEMBAR (FP)
78321
78322P7517: !_DWST_BINIT [16] (maybe <- 0x38000d3) (Int)
78323wr %g0, 0xe2, %asi
78324sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
78325add %i0, %i3, %i3
78326sllx %l4, 32, %l7
78327add %l4, 1, %l4
78328or %l7, %l4, %l7
78329stxa %l7, [%i3 + 0] %asi
78330add %l4, 1, %l4
78331
78332P7518: !_MEMBAR (Int)
78333membar #StoreLoad
78334
78335P7519: !_DWST [15] (maybe <- 0x38000d5) (Int)
78336sllx %l4, 32, %l6
78337add %l4, 1, %l4
78338or %l6, %l4, %l6
78339stx %l6, [%i3 + 0]
78340add %l4, 1, %l4
78341
78342P7520: !_PREFETCH [6] (Int)
78343sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
78344sub %i0, %i2, %i2
78345prefetch [%i2 + 0], 20
78346
78347P7521: !_MEMBAR (FP)
78348
78349P7522: !_BST [12] (maybe <- 0x43000092) (FP)
78350wr %g0, 0xf0, %asi
78351sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
78352sub %i0, %i3, %i3
78353! preparing store val #0, next val will be in f32
78354fmovs %f16, %f20
78355fadds %f16, %f17, %f16
78356! preparing store val #1, next val will be in f33
78357fmovs %f16, %f21
78358fadds %f16, %f17, %f16
78359! preparing store val #2, next val will be in f35
78360fmovd %f20, %f32
78361fmovs %f16, %f21
78362fadds %f16, %f17, %f16
78363fmovd %f20, %f34
78364membar #Sync
78365stda %f32, [%i3 + 0 ] %asi
78366
78367P7523: !_MEMBAR (FP)
78368membar #StoreLoad
78369
78370P7524: !_ST [11] (maybe <- 0x38000d7) (Int)
78371sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
78372sub %i0, %i2, %i2
78373stw %l4, [%i2 + 12 ]
78374add %l4, 1, %l4
78375
78376P7525: !_MEMBAR (FP)
78377
78378P7526: !_BSTC [13] (maybe <- 0x43000095) (FP)
78379wr %g0, 0xe0, %asi
78380! preparing store val #0, next val will be in f32
78381fmovs %f16, %f20
78382fadds %f16, %f17, %f16
78383! preparing store val #1, next val will be in f33
78384fmovs %f16, %f21
78385fadds %f16, %f17, %f16
78386! preparing store val #2, next val will be in f35
78387fmovd %f20, %f32
78388fmovs %f16, %f21
78389fadds %f16, %f17, %f16
78390fmovd %f20, %f34
78391membar #Sync
78392stda %f32, [%i3 + 0 ] %asi
78393
78394P7527: !_MEMBAR (FP)
78395membar #StoreLoad
78396
78397P7528: !_DWLD [23] (Int) (CBR)
78398sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
78399sub %i0, %i3, %i3
78400ldx [%i3 + 8], %o5
78401! move %o5(lower) -> %o4(lower)
78402srl %o5, 0, %l7
78403or %l7, %o4, %o4
78404!---- flushing int results buffer----
78405mov %o0, %l5
78406mov %o1, %l5
78407mov %o2, %l5
78408mov %o3, %l5
78409mov %o4, %l5
78410
78411! cbranch
78412andcc %l0, 1, %g0
78413be,pn %xcc, TARGET7528
78414nop
78415RET7528:
78416
78417! lfsr step begin
78418srlx %l0, 1, %l3
78419xnor %l3, %l0, %l3
78420sllx %l3, 63, %l3
78421or %l3, %l0, %l0
78422srlx %l0, 1, %l0
78423
78424
78425P7529: !_DWLD [14] (Int)
78426sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
78427sub %i0, %i2, %i2
78428ldx [%i2 + 8], %o0
78429! move %o0(lower) -> %o0(upper)
78430sllx %o0, 32, %o0
78431
78432P7530: !_CASX [3] (maybe <- 0x38000d8) (Int)
78433ldx [%i1], %l7
78434! move %l7(upper) -> %o0(lower)
78435srlx %l7, 32, %o5
78436or %o5, %o0, %o0
78437! move %l7(lower) -> %o1(upper)
78438sllx %l7, 32, %o1
78439mov %l7, %o5
78440sllx %l4, 32, %l7
78441add %l4, 1, %l4
78442or %l4, %l7, %l7
78443casx [%i1], %o5, %l7
78444! move %l7(upper) -> %o1(lower)
78445srlx %l7, 32, %o5
78446or %o5, %o1, %o1
78447! move %l7(lower) -> %o2(upper)
78448sllx %l7, 32, %o2
78449add %l4, 1, %l4
78450
78451P7531: !_LD [20] (FP)
78452sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
78453sub %i0, %i3, %i3
78454ld [%i3 + 12], %f0
78455! 1 addresses covered
78456
78457P7532: !_DWLD [21] (Int)
78458sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
78459sub %i0, %i2, %i2
78460ldx [%i2 + 0], %l3
78461! move %l3(upper) -> %o2(lower)
78462srlx %l3, 32, %o5
78463or %o5, %o2, %o2
78464! move %l3(lower) -> %o3(upper)
78465sllx %l3, 32, %o3
78466
78467P7533: !_CAS [1] (maybe <- 0x38000da) (Int)
78468add %i0, 4, %l7
78469lduw [%l7], %l3
78470mov %l3, %l6
78471! move %l6(lower) -> %o3(lower)
78472or %l6, %o3, %o3
78473mov %l4, %o4
78474cas [%l7], %l6, %o4
78475! move %o4(lower) -> %o4(upper)
78476sllx %o4, 32, %o4
78477add %l4, 1, %l4
78478
78479P7534: !_REPLACEMENT [5] (Int)
78480sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
78481add %i0, %i3, %i3
78482sethi %hi(0x20000), %l6
78483ld [%i3+12], %o5
78484st %o5, [%i3+12]
78485add %i3, %l6, %l7
78486ld [%l7+12], %o5
78487st %o5, [%l7+12]
78488add %l7, %l6, %l7
78489ld [%l7+12], %o5
78490st %o5, [%l7+12]
78491add %l7, %l6, %l7
78492ld [%l7+12], %o5
78493st %o5, [%l7+12]
78494add %l7, %l6, %l7
78495ld [%l7+12], %o5
78496st %o5, [%l7+12]
78497add %l7, %l6, %l7
78498ld [%l7+12], %o5
78499st %o5, [%l7+12]
78500add %l7, %l6, %l7
78501ld [%l7+12], %o5
78502st %o5, [%l7+12]
78503add %l7, %l6, %l7
78504ld [%l7+12], %o5
78505st %o5, [%l7+12]
78506
78507P7535: !_SWAP [21] (maybe <- 0x38000db) (Int)
78508mov %l4, %l7
78509swap [%i2 + 0], %l7
78510! move %l7(lower) -> %o4(lower)
78511srl %l7, 0, %l3
78512or %l3, %o4, %o4
78513!---- flushing int results buffer----
78514mov %o0, %l5
78515mov %o1, %l5
78516mov %o2, %l5
78517mov %o3, %l5
78518mov %o4, %l5
78519add %l4, 1, %l4
78520
78521P7536: !_DWST_BINIT [11] (maybe <- 0x38000dc) (Int)
78522wr %g0, 0xe2, %asi
78523sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
78524sub %i0, %i2, %i2
78525mov %l4, %o5
78526stxa %o5, [%i2 + 8] %asi
78527add %l4, 1, %l4
78528
78529P7537: !_MEMBAR (Int)
78530membar #StoreLoad
78531
78532P7538: !_CAS [18] (maybe <- 0x38000dd) (Int) (Branch target of P7646)
78533sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
78534sub %i0, %i3, %i3
78535lduw [%i3], %o0
78536mov %o0, %l7
78537! move %l7(lower) -> %o0(upper)
78538sllx %l7, 32, %o0
78539mov %l4, %l6
78540cas [%i3], %l7, %l6
78541! move %l6(lower) -> %o0(lower)
78542srl %l6, 0, %l7
78543or %l7, %o0, %o0
78544add %l4, 1, %l4
78545ba P7539
78546nop
78547
78548TARGET7646:
78549ba RET7646
78550nop
78551
78552
78553P7539: !_MEMBAR (FP)
78554
78555P7540: !_BSTC [22] (maybe <- 0x43000098) (FP)
78556wr %g0, 0xe0, %asi
78557sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
78558sub %i0, %i2, %i2
78559! preparing store val #0, next val will be in f32
78560fmovs %f16, %f20
78561fadds %f16, %f17, %f16
78562! preparing store val #1, next val will be in f33
78563fmovs %f16, %f21
78564fadds %f16, %f17, %f16
78565! preparing store val #2, next val will be in f35
78566fmovd %f20, %f32
78567fmovs %f16, %f21
78568fadds %f16, %f17, %f16
78569fmovd %f20, %f34
78570membar #Sync
78571stda %f32, [%i2 + 0 ] %asi
78572
78573P7541: !_MEMBAR (FP) (Branch target of P7288)
78574membar #StoreLoad
78575ba P7542
78576nop
78577
78578TARGET7288:
78579ba RET7288
78580nop
78581
78582
78583P7542: !_DWLD [10] (Int)
78584sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
78585sub %i0, %i3, %i3
78586ldx [%i3 + 0], %o1
78587! move %o1(upper) -> %o1(upper)
78588! move %o1(lower) -> %o1(lower)
78589
78590P7543: !_CASX [11] (maybe <- 0x38000de) (Int) (CBR)
78591add %i3, 8, %l3
78592ldx [%l3], %o2
78593! move %o2(upper) -> %o2(upper)
78594! move %o2(lower) -> %o2(lower)
78595mov %o2, %o5
78596mov %l4, %o3
78597casx [%l3], %o5, %o3
78598! move %o3(upper) -> %o3(upper)
78599! move %o3(lower) -> %o3(lower)
78600add %l4, 1, %l4
78601
78602! cbranch
78603andcc %l0, 1, %g0
78604be,pn %xcc, TARGET7543
78605nop
78606RET7543:
78607
78608! lfsr step begin
78609srlx %l0, 1, %o5
78610xnor %o5, %l0, %o5
78611sllx %o5, 63, %o5
78612or %o5, %l0, %l0
78613srlx %l0, 1, %l0
78614
78615
78616P7544: !_MEMBAR (FP)
78617
78618P7545: !_BSTC [5] (maybe <- 0x4300009b) (FP)
78619wr %g0, 0xe0, %asi
78620! preparing store val #0, next val will be in f32
78621fmovs %f16, %f20
78622fadds %f16, %f17, %f16
78623! preparing store val #1, next val will be in f33
78624fmovs %f16, %f21
78625fadds %f16, %f17, %f16
78626! preparing store val #2, next val will be in f35
78627fmovd %f20, %f32
78628fmovs %f16, %f21
78629fadds %f16, %f17, %f16
78630fmovd %f20, %f34
78631membar #Sync
78632stda %f32, [%i1 + 0 ] %asi
78633
78634P7546: !_MEMBAR (FP)
78635membar #StoreLoad
78636
78637P7547: !_PREFETCH [7] (Int)
78638sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
78639sub %i0, %i2, %i2
78640prefetch [%i2 + 4], 25
78641
78642P7548: !_DWST_BINIT [14] (maybe <- 0x38000df) (Int)
78643wr %g0, 0xe2, %asi
78644sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
78645sub %i0, %i3, %i3
78646mov %l4, %o5
78647stxa %o5, [%i3 + 8] %asi
78648add %l4, 1, %l4
78649
78650P7549: !_MEMBAR (Int)
78651membar #StoreLoad
78652
78653P7550: !_REPLACEMENT [0] (Int)
78654sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i2
78655sub %i0, %i2, %i2
78656sethi %hi(0x20000), %l7
78657ld [%i2+0], %l3
78658st %l3, [%i2+0]
78659add %i2, %l7, %o5
78660ld [%o5+0], %l3
78661st %l3, [%o5+0]
78662add %o5, %l7, %o5
78663ld [%o5+0], %l3
78664st %l3, [%o5+0]
78665add %o5, %l7, %o5
78666ld [%o5+0], %l3
78667st %l3, [%o5+0]
78668add %o5, %l7, %o5
78669ld [%o5+0], %l3
78670st %l3, [%o5+0]
78671add %o5, %l7, %o5
78672ld [%o5+0], %l3
78673st %l3, [%o5+0]
78674add %o5, %l7, %o5
78675ld [%o5+0], %l3
78676st %l3, [%o5+0]
78677add %o5, %l7, %o5
78678ld [%o5+0], %l3
78679st %l3, [%o5+0]
78680
78681P7551: !_DWLD [17] (FP)
78682sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
78683add %i0, %i3, %i3
78684ldd [%i3 + 8], %f18
78685! 1 addresses covered
78686fmovs %f19, %f1
78687
78688P7552: !_CAS [23] (maybe <- 0x38000e0) (Int)
78689sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
78690sub %i0, %i2, %i2
78691add %i2, 12, %l7
78692lduw [%l7], %o4
78693mov %o4, %l6
78694! move %l6(lower) -> %o4(upper)
78695sllx %l6, 32, %o4
78696mov %l4, %l3
78697cas [%l7], %l6, %l3
78698! move %l3(lower) -> %o4(lower)
78699srl %l3, 0, %l6
78700or %l6, %o4, %o4
78701!---- flushing int results buffer----
78702mov %o0, %l5
78703mov %o1, %l5
78704mov %o2, %l5
78705mov %o3, %l5
78706mov %o4, %l5
78707add %l4, 1, %l4
78708
78709P7553: !_PREFETCH [15] (Int)
78710prefetch [%i3 + 0], 28
78711
78712P7554: !_PREFETCH [8] (Int)
78713sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
78714sub %i0, %i3, %i3
78715prefetch [%i3 + 12], 0
78716
78717P7555: !_DWLD [18] (Int)
78718sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
78719sub %i0, %i2, %i2
78720ldx [%i2 + 0], %o0
78721! move %o0(upper) -> %o0(upper)
78722! move %o0(lower) -> %o0(lower)
78723
78724P7556: !_MEMBAR (FP)
78725membar #StoreLoad
78726
78727P7557: !_BLD [13] (FP)
78728wr %g0, 0xf0, %asi
78729sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
78730sub %i0, %i3, %i3
78731ldda [%i3 + 0] %asi, %f32
78732membar #Sync
78733! 3 addresses covered
78734fmovd %f32, %f2
78735fmovd %f34, %f18
78736fmovs %f19, %f4
78737
78738P7558: !_MEMBAR (FP)
78739
78740P7559: !_ST [14] (maybe <- 0x38000e1) (Int)
78741stw %l4, [%i3 + 12 ]
78742add %l4, 1, %l4
78743
78744P7560: !_DWST [6] (maybe <- 0x4300009e) (FP)
78745sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
78746sub %i0, %i2, %i2
78747! preparing store val #0, next val will be in f20
78748fmovs %f16, %f20
78749fadds %f16, %f17, %f16
78750! preparing store val #1, next val will be in f21
78751fmovs %f16, %f21
78752fadds %f16, %f17, %f16
78753std %f20, [%i2 + 0]
78754
78755P7561: !_SWAP [8] (maybe <- 0x38000e2) (Int)
78756mov %l4, %o1
78757swap [%i2 + 12], %o1
78758! move %o1(lower) -> %o1(upper)
78759sllx %o1, 32, %o1
78760add %l4, 1, %l4
78761
78762P7562: !_SWAP [15] (maybe <- 0x38000e3) (Int)
78763sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
78764add %i0, %i3, %i3
78765mov %l4, %l7
78766swap [%i3 + 0], %l7
78767! move %l7(lower) -> %o1(lower)
78768srl %l7, 0, %l3
78769or %l3, %o1, %o1
78770add %l4, 1, %l4
78771
78772P7563: !_CASX [3] (maybe <- 0x38000e4) (Int)
78773ldx [%i1], %o2
78774! move %o2(upper) -> %o2(upper)
78775! move %o2(lower) -> %o2(lower)
78776mov %o2, %o5
78777sllx %l4, 32, %o3
78778add %l4, 1, %l4
78779or %l4, %o3, %o3
78780casx [%i1], %o5, %o3
78781! move %o3(upper) -> %o3(upper)
78782! move %o3(lower) -> %o3(lower)
78783add %l4, 1, %l4
78784
78785P7564: !_SWAP [2] (maybe <- 0x38000e6) (Int)
78786mov %l4, %o4
78787swap [%i0 + 12], %o4
78788! move %o4(lower) -> %o4(upper)
78789sllx %o4, 32, %o4
78790add %l4, 1, %l4
78791
78792P7565: !_MEMBAR (FP)
78793
78794P7566: !_BST [4] (maybe <- 0x430000a0) (FP)
78795wr %g0, 0xf0, %asi
78796! preparing store val #0, next val will be in f32
78797fmovs %f16, %f20
78798fadds %f16, %f17, %f16
78799! preparing store val #1, next val will be in f33
78800fmovs %f16, %f21
78801fadds %f16, %f17, %f16
78802! preparing store val #2, next val will be in f35
78803fmovd %f20, %f32
78804fmovs %f16, %f21
78805fadds %f16, %f17, %f16
78806fmovd %f20, %f34
78807membar #Sync
78808stda %f32, [%i1 + 0 ] %asi
78809
78810P7567: !_MEMBAR (FP)
78811membar #StoreLoad
78812
78813P7568: !_DWLD [13] (Int)
78814sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
78815sub %i0, %i2, %i2
78816ldx [%i2 + 0], %l7
78817! move %l7(upper) -> %o4(lower)
78818srlx %l7, 32, %l6
78819or %l6, %o4, %o4
78820!---- flushing int results buffer----
78821mov %o0, %l5
78822mov %o1, %l5
78823mov %o2, %l5
78824mov %o3, %l5
78825mov %o4, %l5
78826! move %l7(lower) -> %o0(upper)
78827sllx %l7, 32, %o0
78828
78829P7569: !_MEMBAR (FP)
78830membar #StoreLoad
78831
78832P7570: !_BLD [19] (FP)
78833wr %g0, 0xf0, %asi
78834sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
78835sub %i0, %i3, %i3
78836ldda [%i3 + 0] %asi, %f32
78837membar #Sync
78838! 3 addresses covered
78839fmovd %f32, %f18
78840fmovs %f18, %f5
78841fmovs %f19, %f6
78842fmovd %f34, %f18
78843fmovs %f19, %f7
78844
78845P7571: !_MEMBAR (FP)
78846
78847P7572: !_DWST_BINIT [22] (maybe <- 0x38000e7) (Int)
78848wr %g0, 0xe2, %asi
78849sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
78850sub %i0, %i2, %i2
78851sllx %l4, 32, %o5
78852add %l4, 1, %l4
78853or %o5, %l4, %o5
78854stxa %o5, [%i2 + 0] %asi
78855add %l4, 1, %l4
78856
78857P7573: !_MEMBAR (Int)
78858
78859P7574: !_BST [16] (maybe <- 0x430000a3) (FP)
78860wr %g0, 0xf0, %asi
78861sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
78862add %i0, %i3, %i3
78863! preparing store val #0, next val will be in f32
78864fmovs %f16, %f20
78865fadds %f16, %f17, %f16
78866! preparing store val #1, next val will be in f33
78867fmovs %f16, %f21
78868fadds %f16, %f17, %f16
78869! preparing store val #2, next val will be in f35
78870fmovd %f20, %f32
78871fmovs %f16, %f21
78872fadds %f16, %f17, %f16
78873fmovd %f20, %f34
78874membar #Sync
78875stda %f32, [%i3 + 0 ] %asi
78876
78877P7575: !_MEMBAR (FP)
78878membar #StoreLoad
78879
78880P7576: !_ST [1] (maybe <- 0x38000e9) (Int)
78881stw %l4, [%i0 + 4 ]
78882add %l4, 1, %l4
78883
78884P7577: !_CAS [1] (maybe <- 0x38000ea) (Int)
78885add %i0, 4, %l6
78886lduw [%l6], %o5
78887mov %o5, %l3
78888! move %l3(lower) -> %o0(lower)
78889or %l3, %o0, %o0
78890mov %l4, %o1
78891cas [%l6], %l3, %o1
78892! move %o1(lower) -> %o1(upper)
78893sllx %o1, 32, %o1
78894add %l4, 1, %l4
78895
78896P7578: !_LDD [4] (Int)
78897ldd [%i1 + 0], %l6
78898! move %l6(lower) -> %o1(lower)
78899or %l6, %o1, %o1
78900! move %l7(lower) -> %o2(upper)
78901sllx %l7, 32, %o2
78902
78903P7579: !_LDD [4] (Int) (Branch target of P7602)
78904ldd [%i1 + 0], %l6
78905! move %l6(lower) -> %o2(lower)
78906or %l6, %o2, %o2
78907! move %l7(lower) -> %o3(upper)
78908sllx %l7, 32, %o3
78909ba P7580
78910nop
78911
78912TARGET7602:
78913ba RET7602
78914nop
78915
78916
78917P7580: !_LD [8] (Int)
78918sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
78919sub %i0, %i2, %i2
78920lduw [%i2 + 12], %l6
78921! move %l6(lower) -> %o3(lower)
78922or %l6, %o3, %o3
78923
78924P7581: !_DWST_BINIT [21] (maybe <- 0x38000eb) (Int)
78925wr %g0, 0xe2, %asi
78926sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
78927sub %i0, %i3, %i3
78928sllx %l4, 32, %l7
78929add %l4, 1, %l4
78930or %l7, %l4, %l7
78931stxa %l7, [%i3 + 0] %asi
78932add %l4, 1, %l4
78933
78934P7582: !_MEMBAR (Int)
78935membar #StoreLoad
78936
78937P7583: !_REPLACEMENT [11] (Int)
78938sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i2
78939sub %i0, %i2, %i2
78940sethi %hi(0x20000), %l6
78941ld [%i2+12], %o5
78942st %o5, [%i2+12]
78943add %i2, %l6, %l7
78944ld [%l7+12], %o5
78945st %o5, [%l7+12]
78946add %l7, %l6, %l7
78947ld [%l7+12], %o5
78948st %o5, [%l7+12]
78949add %l7, %l6, %l7
78950ld [%l7+12], %o5
78951st %o5, [%l7+12]
78952add %l7, %l6, %l7
78953ld [%l7+12], %o5
78954st %o5, [%l7+12]
78955add %l7, %l6, %l7
78956ld [%l7+12], %o5
78957st %o5, [%l7+12]
78958add %l7, %l6, %l7
78959ld [%l7+12], %o5
78960st %o5, [%l7+12]
78961add %l7, %l6, %l7
78962ld [%l7+12], %o5
78963st %o5, [%l7+12]
78964
78965P7584: !_LDD [2] (Int)
78966ldd [%i0 + 8], %l6
78967! move %l7(lower) -> %o4(upper)
78968sllx %l7, 32, %o4
78969
78970P7585: !_REPLACEMENT [23] (Int)
78971sethi %hi(0x20000), %l3
78972ld [%i2+12], %l7
78973st %l7, [%i2+12]
78974add %i2, %l3, %l6
78975ld [%l6+12], %l7
78976st %l7, [%l6+12]
78977add %l6, %l3, %l6
78978ld [%l6+12], %l7
78979st %l7, [%l6+12]
78980add %l6, %l3, %l6
78981ld [%l6+12], %l7
78982st %l7, [%l6+12]
78983add %l6, %l3, %l6
78984ld [%l6+12], %l7
78985st %l7, [%l6+12]
78986add %l6, %l3, %l6
78987ld [%l6+12], %l7
78988st %l7, [%l6+12]
78989add %l6, %l3, %l6
78990ld [%l6+12], %l7
78991st %l7, [%l6+12]
78992add %l6, %l3, %l6
78993ld [%l6+12], %l7
78994st %l7, [%l6+12]
78995
78996P7586: !_DWST [8] (maybe <- 0x38000ed) (Int)
78997sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
78998sub %i0, %i3, %i3
78999mov %l4, %o5
79000stx %o5, [%i3 + 8]
79001add %l4, 1, %l4
79002
79003P7587: !_ST_BINIT [13] (maybe <- 0x38000ee) (Int)
79004wr %g0, 0xe2, %asi
79005sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
79006sub %i0, %i2, %i2
79007stwa %l4, [%i2 + 4] %asi
79008add %l4, 1, %l4
79009
79010P7588: !_MEMBAR (Int)
79011membar #StoreLoad
79012
79013P7589: !_PREFETCH [14] (Int)
79014prefetch [%i2 + 12], 0
79015
79016P7590: !_ST [16] (maybe <- 0x38000ef) (Int)
79017sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
79018add %i0, %i3, %i3
79019stw %l4, [%i3 + 4 ]
79020add %l4, 1, %l4
79021
79022P7591: !_DWST_BINIT [4] (maybe <- 0x38000f0) (Int) (CBR)
79023!-- Aliased access: Adjusting base register for region 1 (%i1) to use alias #0
79024!Logical addr: 4
79025
79026sethi %hi(0x600000), %l3
79027add %i1, %l3, %i1
79028wr %g0, 0xe2, %asi
79029sllx %l4, 32, %l6
79030add %l4, 1, %l4
79031or %l6, %l4, %l6
79032stxa %l6, [%i1 + 0] %asi
79033add %l4, 1, %l4
79034
79035! cbranch
79036andcc %l0, 1, %g0
79037be,pt %xcc, TARGET7591
79038nop
79039RET7591:
79040
79041! lfsr step begin
79042srlx %l0, 1, %l3
79043xnor %l3, %l0, %l3
79044sllx %l3, 63, %l3
79045or %l3, %l0, %l0
79046srlx %l0, 1, %l0
79047
79048
79049P7592: !_MEMBAR (Int)
79050membar #StoreLoad
79051
79052P7593: !_DWLD [19] (Int)
79053sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
79054sub %i0, %i2, %i2
79055ldx [%i2 + 0], %l7
79056! move %l7(upper) -> %o4(lower)
79057srlx %l7, 32, %l6
79058or %l6, %o4, %o4
79059!---- flushing int results buffer----
79060mov %o0, %l5
79061mov %o1, %l5
79062mov %o2, %l5
79063mov %o3, %l5
79064mov %o4, %l5
79065! move %l7(lower) -> %o0(upper)
79066sllx %l7, 32, %o0
79067
79068P7594: !_ST_BINIT [2] (maybe <- 0x38000f2) (Int)
79069wr %g0, 0xe2, %asi
79070stwa %l4, [%i0 + 12] %asi
79071add %l4, 1, %l4
79072
79073P7595: !_MEMBAR (Int)
79074membar #StoreLoad
79075
79076P7596: !_CAS [17] (maybe <- 0x38000f3) (Int)
79077add %i3, 12, %o5
79078lduw [%o5], %l6
79079mov %l6, %l7
79080! move %l7(lower) -> %o0(lower)
79081or %l7, %o0, %o0
79082mov %l4, %o1
79083cas [%o5], %l7, %o1
79084! move %o1(lower) -> %o1(upper)
79085sllx %o1, 32, %o1
79086add %l4, 1, %l4
79087
79088P7597: !_DWLD [7] (Int)
79089sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
79090sub %i0, %i3, %i3
79091ldx [%i3 + 0], %o5
79092! move %o5(upper) -> %o1(lower)
79093srlx %o5, 32, %l7
79094or %l7, %o1, %o1
79095! move %o5(lower) -> %o2(upper)
79096sllx %o5, 32, %o2
79097
79098P7598: !_LD [21] (Int)
79099sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
79100sub %i0, %i2, %i2
79101lduw [%i2 + 0], %l6
79102! move %l6(lower) -> %o2(lower)
79103or %l6, %o2, %o2
79104
79105P7599: !_REPLACEMENT [0] (Int)
79106sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS2_O), %i3
79107sub %i0, %i3, %i3
79108sethi %hi(0x20000), %l7
79109ld [%i3+0], %l3
79110st %l3, [%i3+0]
79111add %i3, %l7, %o5
79112ld [%o5+0], %l3
79113st %l3, [%o5+0]
79114add %o5, %l7, %o5
79115ld [%o5+0], %l3
79116st %l3, [%o5+0]
79117add %o5, %l7, %o5
79118ld [%o5+0], %l3
79119st %l3, [%o5+0]
79120add %o5, %l7, %o5
79121ld [%o5+0], %l3
79122st %l3, [%o5+0]
79123add %o5, %l7, %o5
79124ld [%o5+0], %l3
79125st %l3, [%o5+0]
79126add %o5, %l7, %o5
79127ld [%o5+0], %l3
79128st %l3, [%o5+0]
79129add %o5, %l7, %o5
79130ld [%o5+0], %l3
79131st %l3, [%o5+0]
79132
79133P7600: !_ST [10] (maybe <- 0x38000f4) (Int)
79134sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
79135sub %i0, %i2, %i2
79136stw %l4, [%i2 + 4 ]
79137add %l4, 1, %l4
79138
79139P7601: !_LD [20] (Int)
79140sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
79141sub %i0, %i3, %i3
79142lduw [%i3 + 12], %o3
79143! move %o3(lower) -> %o3(upper)
79144sllx %o3, 32, %o3
79145
79146P7602: !_DWST_BINIT [10] (maybe <- 0x38000f5) (Int) (CBR)
79147wr %g0, 0xe2, %asi
79148sllx %l4, 32, %l7
79149add %l4, 1, %l4
79150or %l7, %l4, %l7
79151stxa %l7, [%i2 + 0] %asi
79152add %l4, 1, %l4
79153
79154! cbranch
79155andcc %l0, 1, %g0
79156be,pn %xcc, TARGET7602
79157nop
79158RET7602:
79159
79160! lfsr step begin
79161srlx %l0, 1, %l6
79162xnor %l6, %l0, %l6
79163sllx %l6, 63, %l6
79164or %l6, %l0, %l0
79165srlx %l0, 1, %l0
79166
79167
79168P7603: !_MEMBAR (Int)
79169membar #StoreLoad
79170
79171P7604: !_LDD [13] (Int) (LE)
79172wr %g0, 0x88, %asi
79173sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
79174sub %i0, %i2, %i2
79175ldda [%i2 + 0] %asi, %l6
79176! move %l6(lower) -> %o3(lower)
79177or %l6, %o3, %o3
79178! move %l7(lower) -> %o4(upper)
79179sllx %l7, 32, %o4
79180
79181P7605: !_PREFETCH [12] (Int)
79182prefetch [%i2 + 0], 2
79183
79184P7606: !_PREFETCH [7] (Int)
79185sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
79186sub %i0, %i3, %i3
79187prefetch [%i3 + 4], 1
79188
79189P7607: !_MEMBAR (FP)
79190
79191P7608: !_BSTC [6] (maybe <- 0x430000a6) (FP)
79192wr %g0, 0xe0, %asi
79193! preparing store val #0, next val will be in f32
79194fmovs %f16, %f20
79195fadds %f16, %f17, %f16
79196! preparing store val #1, next val will be in f33
79197fmovs %f16, %f21
79198fadds %f16, %f17, %f16
79199! preparing store val #2, next val will be in f35
79200fmovd %f20, %f32
79201fmovs %f16, %f21
79202fadds %f16, %f17, %f16
79203fmovd %f20, %f34
79204membar #Sync
79205stda %f32, [%i3 + 0 ] %asi
79206
79207P7609: !_MEMBAR (FP)
79208membar #StoreLoad
79209
79210P7610: !_SWAP [21] (maybe <- 0x38000f7) (Int)
79211sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
79212sub %i0, %i2, %i2
79213mov %l4, %l6
79214swap [%i2 + 0], %l6
79215! move %l6(lower) -> %o4(lower)
79216srl %l6, 0, %o5
79217or %o5, %o4, %o4
79218!---- flushing int results buffer----
79219mov %o0, %l5
79220mov %o1, %l5
79221mov %o2, %l5
79222mov %o3, %l5
79223mov %o4, %l5
79224add %l4, 1, %l4
79225
79226P7611: !_PREFETCH [22] (Int)
79227prefetch [%i2 + 4], 19
79228
79229P7612: !_SWAP [6] (maybe <- 0x38000f8) (Int)
79230mov %l4, %o0
79231swap [%i3 + 0], %o0
79232! move %o0(lower) -> %o0(upper)
79233sllx %o0, 32, %o0
79234add %l4, 1, %l4
79235
79236P7613: !_MEMBAR (FP)
79237
79238P7614: !_BSTC [21] (maybe <- 0x430000a9) (FP)
79239wr %g0, 0xe0, %asi
79240! preparing store val #0, next val will be in f32
79241fmovs %f16, %f20
79242fadds %f16, %f17, %f16
79243! preparing store val #1, next val will be in f33
79244fmovs %f16, %f21
79245fadds %f16, %f17, %f16
79246! preparing store val #2, next val will be in f35
79247fmovd %f20, %f32
79248fmovs %f16, %f21
79249fadds %f16, %f17, %f16
79250fmovd %f20, %f34
79251membar #Sync
79252stda %f32, [%i2 + 0 ] %asi
79253
79254P7615: !_MEMBAR (FP)
79255membar #StoreLoad
79256
79257P7616: !_DWST [13] (maybe <- 0x38000f9) (Int)
79258sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
79259sub %i0, %i3, %i3
79260sllx %l4, 32, %l3
79261add %l4, 1, %l4
79262or %l3, %l4, %l3
79263stx %l3, [%i3 + 0]
79264add %l4, 1, %l4
79265
79266P7617: !_MEMBAR (FP)
79267membar #StoreLoad
79268
79269P7618: !_BLD [9] (FP)
79270wr %g0, 0xf0, %asi
79271sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
79272sub %i0, %i2, %i2
79273ldda [%i2 + 0] %asi, %f32
79274membar #Sync
79275! 3 addresses covered
79276fmovd %f32, %f8
79277fmovd %f34, %f18
79278fmovs %f19, %f10
79279
79280P7619: !_MEMBAR (FP)
79281
79282P7620: !_CASX [17] (maybe <- 0x38000fb) (Int)
79283sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
79284add %i0, %i3, %i3
79285add %i3, 8, %l3
79286ldx [%l3], %l7
79287! move %l7(upper) -> %o0(lower)
79288srlx %l7, 32, %o5
79289or %o5, %o0, %o0
79290! move %l7(lower) -> %o1(upper)
79291sllx %l7, 32, %o1
79292mov %l7, %o5
79293mov %l4, %l7
79294casx [%l3], %o5, %l7
79295! move %l7(upper) -> %o1(lower)
79296srlx %l7, 32, %o5
79297or %o5, %o1, %o1
79298! move %l7(lower) -> %o2(upper)
79299sllx %l7, 32, %o2
79300add %l4, 1, %l4
79301
79302P7621: !_DWST [11] (maybe <- 0x38000fc) (Int) (CBR)
79303mov %l4, %o5
79304stx %o5, [%i2 + 8]
79305add %l4, 1, %l4
79306
79307! cbranch
79308andcc %l0, 1, %g0
79309be,pn %xcc, TARGET7621
79310nop
79311RET7621:
79312
79313! lfsr step begin
79314srlx %l0, 1, %l7
79315xnor %l7, %l0, %l7
79316sllx %l7, 63, %l7
79317or %l7, %l0, %l0
79318srlx %l0, 1, %l0
79319
79320
79321P7622: !_ST [17] (maybe <- 0x38000fd) (Int)
79322stw %l4, [%i3 + 12 ]
79323add %l4, 1, %l4
79324
79325P7623: !_MEMBAR (FP)
79326
79327P7624: !_BSTC [3] (maybe <- 0x430000ac) (FP)
79328wr %g0, 0xe0, %asi
79329! preparing store val #0, next val will be in f32
79330fmovs %f16, %f20
79331fadds %f16, %f17, %f16
79332! preparing store val #1, next val will be in f33
79333fmovs %f16, %f21
79334fadds %f16, %f17, %f16
79335! preparing store val #2, next val will be in f35
79336fmovd %f20, %f32
79337fmovs %f16, %f21
79338fadds %f16, %f17, %f16
79339fmovd %f20, %f34
79340membar #Sync
79341stda %f32, [%i1 + 0 ] %asi
79342
79343P7625: !_MEMBAR (FP)
79344membar #StoreLoad
79345
79346P7626: !_CASX [9] (maybe <- 0x38000fe) (Int)
79347ldx [%i2], %l3
79348! move %l3(upper) -> %o2(lower)
79349srlx %l3, 32, %l6
79350or %l6, %o2, %o2
79351! move %l3(lower) -> %o3(upper)
79352sllx %l3, 32, %o3
79353mov %l3, %l6
79354sllx %l4, 32, %l3
79355add %l4, 1, %l4
79356or %l4, %l3, %l3
79357casx [%i2], %l6, %l3
79358! move %l3(upper) -> %o3(lower)
79359srlx %l3, 32, %l6
79360or %l6, %o3, %o3
79361! move %l3(lower) -> %o4(upper)
79362sllx %l3, 32, %o4
79363add %l4, 1, %l4
79364
79365P7627: !_MEMBAR (FP)
79366
79367P7628: !_BSTC [11] (maybe <- 0x430000af) (FP)
79368wr %g0, 0xe0, %asi
79369! preparing store val #0, next val will be in f32
79370fmovs %f16, %f20
79371fadds %f16, %f17, %f16
79372! preparing store val #1, next val will be in f33
79373fmovs %f16, %f21
79374fadds %f16, %f17, %f16
79375! preparing store val #2, next val will be in f35
79376fmovd %f20, %f32
79377fmovs %f16, %f21
79378fadds %f16, %f17, %f16
79379fmovd %f20, %f34
79380membar #Sync
79381stda %f32, [%i2 + 0 ] %asi
79382
79383P7629: !_MEMBAR (FP)
79384membar #StoreLoad
79385
79386P7630: !_LD [16] (Int)
79387lduw [%i3 + 4], %l6
79388! move %l6(lower) -> %o4(lower)
79389or %l6, %o4, %o4
79390!---- flushing int results buffer----
79391mov %o0, %l5
79392mov %o1, %l5
79393mov %o2, %l5
79394mov %o3, %l5
79395mov %o4, %l5
79396
79397P7631: !_MEMBAR (FP) (CBR)
79398membar #StoreLoad
79399
79400! cbranch
79401andcc %l0, 1, %g0
79402be,pn %xcc, TARGET7631
79403nop
79404RET7631:
79405
79406! lfsr step begin
79407srlx %l0, 1, %l7
79408xnor %l7, %l0, %l7
79409sllx %l7, 63, %l7
79410or %l7, %l0, %l0
79411srlx %l0, 1, %l0
79412
79413
79414P7632: !_BLD [7] (FP) (Branch target of P7956)
79415wr %g0, 0xf0, %asi
79416sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
79417sub %i0, %i2, %i2
79418ldda [%i2 + 0] %asi, %f32
79419membar #Sync
79420! 3 addresses covered
79421fmovd %f32, %f18
79422fmovs %f18, %f11
79423fmovs %f19, %f12
79424fmovd %f34, %f18
79425fmovs %f19, %f13
79426ba P7633
79427nop
79428
79429TARGET7956:
79430ba RET7956
79431nop
79432
79433
79434P7633: !_MEMBAR (FP)
79435
79436P7634: !_SWAP [1] (maybe <- 0x3800100) (Int)
79437mov %l4, %o0
79438swap [%i0 + 4], %o0
79439! move %o0(lower) -> %o0(upper)
79440sllx %o0, 32, %o0
79441add %l4, 1, %l4
79442
79443P7635: !_MEMBAR (FP)
79444
79445P7636: !_BSTC [1] (maybe <- 0x430000b2) (FP)
79446wr %g0, 0xe0, %asi
79447! preparing store val #0, next val will be in f32
79448fmovs %f16, %f20
79449fadds %f16, %f17, %f16
79450! preparing store val #1, next val will be in f33
79451fmovs %f16, %f21
79452fadds %f16, %f17, %f16
79453! preparing store val #2, next val will be in f35
79454fmovd %f20, %f32
79455fmovs %f16, %f21
79456fadds %f16, %f17, %f16
79457fmovd %f20, %f34
79458membar #Sync
79459stda %f32, [%i0 + 0 ] %asi
79460
79461P7637: !_MEMBAR (FP)
79462membar #StoreLoad
79463
79464P7638: !_DWLD [6] (Int)
79465ldx [%i2 + 0], %l7
79466! move %l7(upper) -> %o0(lower)
79467srlx %l7, 32, %l6
79468or %l6, %o0, %o0
79469! move %l7(lower) -> %o1(upper)
79470sllx %l7, 32, %o1
79471
79472P7639: !_CASX [15] (maybe <- 0x3800101) (Int)
79473ldx [%i3], %l7
79474! move %l7(upper) -> %o1(lower)
79475srlx %l7, 32, %o5
79476or %o5, %o1, %o1
79477! move %l7(lower) -> %o2(upper)
79478sllx %l7, 32, %o2
79479mov %l7, %o5
79480sllx %l4, 32, %l7
79481add %l4, 1, %l4
79482or %l4, %l7, %l7
79483casx [%i3], %o5, %l7
79484! move %l7(upper) -> %o2(lower)
79485srlx %l7, 32, %o5
79486or %o5, %o2, %o2
79487! move %l7(lower) -> %o3(upper)
79488sllx %l7, 32, %o3
79489add %l4, 1, %l4
79490
79491P7640: !_CASX [3] (maybe <- 0x3800103) (Int) (CBR)
79492ldx [%i1], %l7
79493! move %l7(upper) -> %o3(lower)
79494srlx %l7, 32, %o5
79495or %o5, %o3, %o3
79496! move %l7(lower) -> %o4(upper)
79497sllx %l7, 32, %o4
79498mov %l7, %o5
79499sllx %l4, 32, %l7
79500add %l4, 1, %l4
79501or %l4, %l7, %l7
79502casx [%i1], %o5, %l7
79503! move %l7(upper) -> %o4(lower)
79504srlx %l7, 32, %o5
79505or %o5, %o4, %o4
79506!---- flushing int results buffer----
79507mov %o0, %l5
79508mov %o1, %l5
79509mov %o2, %l5
79510mov %o3, %l5
79511mov %o4, %l5
79512! move %l7(lower) -> %o0(upper)
79513sllx %l7, 32, %o0
79514add %l4, 1, %l4
79515
79516! cbranch
79517andcc %l0, 1, %g0
79518be,pt %xcc, TARGET7640
79519nop
79520RET7640:
79521
79522! lfsr step begin
79523srlx %l0, 1, %o5
79524xnor %o5, %l0, %o5
79525sllx %o5, 63, %o5
79526or %o5, %l0, %l0
79527srlx %l0, 1, %l0
79528
79529
79530P7641: !_LDD [8] (Int) (Branch target of P7631)
79531ldd [%i2 + 8], %l6
79532! move %l7(lower) -> %o0(lower)
79533or %l7, %o0, %o0
79534ba P7642
79535nop
79536
79537TARGET7631:
79538ba RET7631
79539nop
79540
79541
79542P7642: !_DWLD [14] (Int)
79543sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
79544sub %i0, %i3, %i3
79545ldx [%i3 + 8], %o1
79546! move %o1(lower) -> %o1(upper)
79547sllx %o1, 32, %o1
79548
79549P7643: !_CAS [7] (maybe <- 0x3800105) (Int)
79550add %i2, 4, %o5
79551lduw [%o5], %l6
79552mov %l6, %l7
79553! move %l7(lower) -> %o1(lower)
79554or %l7, %o1, %o1
79555mov %l4, %o2
79556cas [%o5], %l7, %o2
79557! move %o2(lower) -> %o2(upper)
79558sllx %o2, 32, %o2
79559add %l4, 1, %l4
79560
79561P7644: !_SWAP [12] (maybe <- 0x3800106) (Int) (CBR)
79562mov %l4, %l3
79563swap [%i3 + 0], %l3
79564! move %l3(lower) -> %o2(lower)
79565srl %l3, 0, %l7
79566or %l7, %o2, %o2
79567add %l4, 1, %l4
79568
79569! cbranch
79570andcc %l0, 1, %g0
79571be,pn %xcc, TARGET7644
79572nop
79573RET7644:
79574
79575! lfsr step begin
79576srlx %l0, 1, %l6
79577xnor %l6, %l0, %l6
79578sllx %l6, 63, %l6
79579or %l6, %l0, %l0
79580srlx %l0, 1, %l0
79581
79582
79583P7645: !_REPLACEMENT [11] (Int) (CBR)
79584sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2
79585add %i0, %i2, %i2
79586sethi %hi(0x20000), %l7
79587ld [%i2+12], %l3
79588st %l3, [%i2+12]
79589add %i2, %l7, %o5
79590ld [%o5+12], %l3
79591st %l3, [%o5+12]
79592add %o5, %l7, %o5
79593ld [%o5+12], %l3
79594st %l3, [%o5+12]
79595add %o5, %l7, %o5
79596ld [%o5+12], %l3
79597st %l3, [%o5+12]
79598add %o5, %l7, %o5
79599ld [%o5+12], %l3
79600st %l3, [%o5+12]
79601add %o5, %l7, %o5
79602ld [%o5+12], %l3
79603st %l3, [%o5+12]
79604add %o5, %l7, %o5
79605ld [%o5+12], %l3
79606st %l3, [%o5+12]
79607add %o5, %l7, %o5
79608ld [%o5+12], %l3
79609st %l3, [%o5+12]
79610
79611! cbranch
79612andcc %l0, 1, %g0
79613be,pt %xcc, TARGET7645
79614nop
79615RET7645:
79616
79617! lfsr step begin
79618srlx %l0, 1, %l6
79619xnor %l6, %l0, %l6
79620sllx %l6, 63, %l6
79621or %l6, %l0, %l0
79622srlx %l0, 1, %l0
79623
79624
79625P7646: !_SWAP [19] (maybe <- 0x3800107) (Int) (CBR)
79626sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
79627sub %i0, %i3, %i3
79628mov %l4, %o3
79629swap [%i3 + 4], %o3
79630! move %o3(lower) -> %o3(upper)
79631sllx %o3, 32, %o3
79632add %l4, 1, %l4
79633
79634! cbranch
79635andcc %l0, 1, %g0
79636be,pn %xcc, TARGET7646
79637nop
79638RET7646:
79639
79640! lfsr step begin
79641srlx %l0, 1, %l6
79642xnor %l6, %l0, %l6
79643sllx %l6, 63, %l6
79644or %l6, %l0, %l0
79645srlx %l0, 1, %l0
79646
79647
79648P7647: !_LDD [8] (Int)
79649sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
79650sub %i0, %i2, %i2
79651ldd [%i2 + 8], %l6
79652! move %l7(lower) -> %o3(lower)
79653or %l7, %o3, %o3
79654
79655P7648: !_ST [15] (maybe <- 0x3800108) (Int)
79656sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
79657add %i0, %i3, %i3
79658stw %l4, [%i3 + 0 ]
79659add %l4, 1, %l4
79660
79661P7649: !_DWLD [22] (FP)
79662sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
79663sub %i0, %i2, %i2
79664ldd [%i2 + 0], %f14
79665! 2 addresses covered
79666!---- flushing fp results buffer to %f30 ----
79667fmovd %f0, %f30
79668fmovd %f2, %f30
79669fmovd %f4, %f30
79670fmovd %f6, %f30
79671fmovd %f8, %f30
79672fmovd %f10, %f30
79673fmovd %f12, %f30
79674fmovd %f14, %f30
79675!--
79676
79677P7650: !_PREFETCH [21] (Int) (CBR)
79678prefetch [%i2 + 0], 30
79679
79680! cbranch
79681andcc %l0, 1, %g0
79682be,pn %xcc, TARGET7650
79683nop
79684RET7650:
79685
79686! lfsr step begin
79687srlx %l0, 1, %o5
79688xnor %o5, %l0, %o5
79689sllx %o5, 63, %o5
79690or %o5, %l0, %l0
79691srlx %l0, 1, %l0
79692
79693
79694P7651: !_DWST [8] (maybe <- 0x3800109) (Int)
79695sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
79696sub %i0, %i3, %i3
79697mov %l4, %l3
79698stx %l3, [%i3 + 8]
79699add %l4, 1, %l4
79700
79701P7652: !_PREFETCH [21] (Int)
79702prefetch [%i2 + 0], 22
79703
79704P7653: !_MEMBAR (FP)
79705
79706P7654: !_BSTC [16] (maybe <- 0x430000b5) (FP)
79707wr %g0, 0xe0, %asi
79708sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
79709add %i0, %i2, %i2
79710! preparing store val #0, next val will be in f32
79711fmovs %f16, %f20
79712fadds %f16, %f17, %f16
79713! preparing store val #1, next val will be in f33
79714fmovs %f16, %f21
79715fadds %f16, %f17, %f16
79716! preparing store val #2, next val will be in f35
79717fmovd %f20, %f32
79718fmovs %f16, %f21
79719fadds %f16, %f17, %f16
79720fmovd %f20, %f34
79721membar #Sync
79722stda %f32, [%i2 + 0 ] %asi
79723
79724P7655: !_MEMBAR (FP)
79725membar #StoreLoad
79726
79727P7656: !_REPLACEMENT [16] (Int) (Branch target of P7811)
79728sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
79729sub %i0, %i3, %i3
79730sethi %hi(0x20000), %o5
79731ld [%i3+4], %l6
79732st %l6, [%i3+4]
79733add %i3, %o5, %l3
79734ld [%l3+4], %l6
79735st %l6, [%l3+4]
79736add %l3, %o5, %l3
79737ld [%l3+4], %l6
79738st %l6, [%l3+4]
79739add %l3, %o5, %l3
79740ld [%l3+4], %l6
79741st %l6, [%l3+4]
79742add %l3, %o5, %l3
79743ld [%l3+4], %l6
79744st %l6, [%l3+4]
79745add %l3, %o5, %l3
79746ld [%l3+4], %l6
79747st %l6, [%l3+4]
79748add %l3, %o5, %l3
79749ld [%l3+4], %l6
79750st %l6, [%l3+4]
79751add %l3, %o5, %l3
79752ld [%l3+4], %l6
79753st %l6, [%l3+4]
79754ba P7657
79755nop
79756
79757TARGET7811:
79758ba RET7811
79759nop
79760
79761
79762P7657: !_MEMBAR (FP) (CBR)
79763membar #StoreLoad
79764
79765! cbranch
79766andcc %l0, 1, %g0
79767be,pt %xcc, TARGET7657
79768nop
79769RET7657:
79770
79771! lfsr step begin
79772srlx %l0, 1, %l7
79773xnor %l7, %l0, %l7
79774sllx %l7, 63, %l7
79775or %l7, %l0, %l0
79776srlx %l0, 1, %l0
79777
79778
79779P7658: !_BLD [1] (FP)
79780wr %g0, 0xf0, %asi
79781ldda [%i0 + 0] %asi, %f0
79782membar #Sync
79783! 3 addresses covered
79784fmovs %f3, %f2
79785
79786P7659: !_MEMBAR (FP)
79787
79788P7660: !_BSTC [15] (maybe <- 0x430000b8) (FP)
79789wr %g0, 0xe0, %asi
79790! preparing store val #0, next val will be in f32
79791fmovs %f16, %f20
79792fadds %f16, %f17, %f16
79793! preparing store val #1, next val will be in f33
79794fmovs %f16, %f21
79795fadds %f16, %f17, %f16
79796! preparing store val #2, next val will be in f35
79797fmovd %f20, %f32
79798fmovs %f16, %f21
79799fadds %f16, %f17, %f16
79800fmovd %f20, %f34
79801membar #Sync
79802stda %f32, [%i2 + 0 ] %asi
79803
79804P7661: !_MEMBAR (FP)
79805membar #StoreLoad
79806
79807P7662: !_SWAP [6] (maybe <- 0x380010a) (Int)
79808sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
79809sub %i0, %i2, %i2
79810mov %l4, %o4
79811swap [%i2 + 0], %o4
79812! move %o4(lower) -> %o4(upper)
79813sllx %o4, 32, %o4
79814add %l4, 1, %l4
79815
79816P7663: !_SWAP [5] (maybe <- 0x380010b) (Int)
79817mov %l4, %o5
79818swap [%i1 + 12], %o5
79819! move %o5(lower) -> %o4(lower)
79820srl %o5, 0, %l6
79821or %l6, %o4, %o4
79822!---- flushing int results buffer----
79823mov %o0, %l5
79824mov %o1, %l5
79825mov %o2, %l5
79826mov %o3, %l5
79827mov %o4, %l5
79828add %l4, 1, %l4
79829
79830P7664: !_DWST [7] (maybe <- 0x380010c) (Int)
79831sllx %l4, 32, %l3
79832add %l4, 1, %l4
79833or %l3, %l4, %l3
79834stx %l3, [%i2 + 0]
79835add %l4, 1, %l4
79836
79837P7665: !_DWST_BINIT [17] (maybe <- 0x380010e) (Int)
79838wr %g0, 0xe2, %asi
79839sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
79840add %i0, %i3, %i3
79841mov %l4, %o5
79842stxa %o5, [%i3 + 8] %asi
79843add %l4, 1, %l4
79844
79845P7666: !_MEMBAR (Int)
79846membar #StoreLoad
79847
79848P7667: !_CAS [23] (maybe <- 0x380010f) (Int)
79849sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
79850sub %i0, %i2, %i2
79851add %i2, 12, %o5
79852lduw [%o5], %o0
79853mov %o0, %l7
79854! move %l7(lower) -> %o0(upper)
79855sllx %l7, 32, %o0
79856mov %l4, %l6
79857cas [%o5], %l7, %l6
79858! move %l6(lower) -> %o0(lower)
79859srl %l6, 0, %l7
79860or %l7, %o0, %o0
79861add %l4, 1, %l4
79862
79863P7668: !_REPLACEMENT [6] (Int)
79864sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
79865sub %i0, %i3, %i3
79866sethi %hi(0x20000), %l7
79867ld [%i3+0], %l3
79868st %l3, [%i3+0]
79869add %i3, %l7, %o5
79870ld [%o5+0], %l3
79871st %l3, [%o5+0]
79872add %o5, %l7, %o5
79873ld [%o5+0], %l3
79874st %l3, [%o5+0]
79875add %o5, %l7, %o5
79876ld [%o5+0], %l3
79877st %l3, [%o5+0]
79878add %o5, %l7, %o5
79879ld [%o5+0], %l3
79880st %l3, [%o5+0]
79881add %o5, %l7, %o5
79882ld [%o5+0], %l3
79883st %l3, [%o5+0]
79884add %o5, %l7, %o5
79885ld [%o5+0], %l3
79886st %l3, [%o5+0]
79887add %o5, %l7, %o5
79888ld [%o5+0], %l3
79889st %l3, [%o5+0]
79890
79891P7669: !_DWST_BINIT [6] (maybe <- 0x3800110) (Int)
79892wr %g0, 0xe2, %asi
79893sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
79894sub %i0, %i2, %i2
79895sllx %l4, 32, %l6
79896add %l4, 1, %l4
79897or %l6, %l4, %l6
79898stxa %l6, [%i2 + 0] %asi
79899add %l4, 1, %l4
79900
79901P7670: !_MEMBAR (Int)
79902membar #StoreLoad
79903
79904P7671: !_BLD [1] (FP)
79905wr %g0, 0xf0, %asi
79906ldda [%i0 + 0] %asi, %f32
79907membar #Sync
79908! 3 addresses covered
79909fmovd %f32, %f18
79910fmovs %f18, %f3
79911fmovs %f19, %f4
79912fmovd %f34, %f18
79913fmovs %f19, %f5
79914
79915P7672: !_MEMBAR (FP)
79916
79917P7673: !_DWST_BINIT [23] (maybe <- 0x3800112) (Int) (CBR)
79918wr %g0, 0xe2, %asi
79919sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
79920sub %i0, %i3, %i3
79921mov %l4, %l3
79922stxa %l3, [%i3 + 8] %asi
79923add %l4, 1, %l4
79924
79925! cbranch
79926andcc %l0, 1, %g0
79927be,pt %xcc, TARGET7673
79928nop
79929RET7673:
79930
79931! lfsr step begin
79932srlx %l0, 1, %o5
79933xnor %o5, %l0, %o5
79934sllx %o5, 63, %o5
79935or %o5, %l0, %l0
79936srlx %l0, 1, %l0
79937
79938
79939P7674: !_MEMBAR (Int) (CBR)
79940membar #StoreLoad
79941
79942! cbranch
79943andcc %l0, 1, %g0
79944be,pt %xcc, TARGET7674
79945nop
79946RET7674:
79947
79948! lfsr step begin
79949srlx %l0, 1, %l3
79950xnor %l3, %l0, %l3
79951sllx %l3, 63, %l3
79952or %l3, %l0, %l0
79953srlx %l0, 1, %l0
79954
79955
79956P7675: !_LD [21] (Int)
79957lduw [%i3 + 0], %o1
79958! move %o1(lower) -> %o1(upper)
79959sllx %o1, 32, %o1
79960
79961P7676: !_DWLD [1] (Int)
79962ldx [%i0 + 0], %l3
79963! move %l3(upper) -> %o1(lower)
79964srlx %l3, 32, %o5
79965or %o5, %o1, %o1
79966! move %l3(lower) -> %o2(upper)
79967sllx %l3, 32, %o2
79968
79969P7677: !_ST [17] (maybe <- 0x3800113) (Int)
79970sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
79971add %i0, %i2, %i2
79972stw %l4, [%i2 + 12 ]
79973add %l4, 1, %l4
79974
79975P7678: !_CAS [23] (maybe <- 0x3800114) (Int)
79976add %i3, 12, %l6
79977lduw [%l6], %o5
79978mov %o5, %l3
79979! move %l3(lower) -> %o2(lower)
79980or %l3, %o2, %o2
79981mov %l4, %o3
79982cas [%l6], %l3, %o3
79983! move %o3(lower) -> %o3(upper)
79984sllx %o3, 32, %o3
79985add %l4, 1, %l4
79986
79987P7679: !_PREFETCH [21] (Int)
79988prefetch [%i3 + 0], 21
79989
79990P7680: !_DWST [21] (maybe <- 0x3800115) (Int)
79991sllx %l4, 32, %l3
79992add %l4, 1, %l4
79993or %l3, %l4, %l3
79994stx %l3, [%i3 + 0]
79995add %l4, 1, %l4
79996
79997P7681: !_LDD [7] (Int)
79998sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
79999sub %i0, %i3, %i3
80000ldd [%i3 + 0], %l6
80001! move %l6(lower) -> %o3(lower)
80002or %l6, %o3, %o3
80003! move %l7(lower) -> %o4(upper)
80004sllx %l7, 32, %o4
80005
80006P7682: !_MEMBAR (FP)
80007
80008P7683: !_BSTC [1] (maybe <- 0x430000bb) (FP)
80009wr %g0, 0xe0, %asi
80010! preparing store val #0, next val will be in f32
80011fmovs %f16, %f20
80012fadds %f16, %f17, %f16
80013! preparing store val #1, next val will be in f33
80014fmovs %f16, %f21
80015fadds %f16, %f17, %f16
80016! preparing store val #2, next val will be in f35
80017fmovd %f20, %f32
80018fmovs %f16, %f21
80019fadds %f16, %f17, %f16
80020fmovd %f20, %f34
80021membar #Sync
80022stda %f32, [%i0 + 0 ] %asi
80023
80024P7684: !_MEMBAR (FP)
80025membar #StoreLoad
80026
80027P7685: !_DWST [9] (maybe <- 0x3800117) (Int)
80028sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
80029sub %i0, %i2, %i2
80030sllx %l4, 32, %o5
80031add %l4, 1, %l4
80032or %o5, %l4, %o5
80033stx %o5, [%i2 + 0]
80034add %l4, 1, %l4
80035
80036P7686: !_PREFETCH [19] (Int) (LE)
80037wr %g0, 0x88, %asi
80038sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
80039sub %i0, %i3, %i3
80040prefetcha [%i3 + 4] %asi, 0
80041
80042P7687: !_SWAP [3] (maybe <- 0x3800119) (Int)
80043mov %l4, %l3
80044swap [%i1 + 0], %l3
80045! move %l3(lower) -> %o4(lower)
80046srl %l3, 0, %l7
80047or %l7, %o4, %o4
80048!---- flushing int results buffer----
80049mov %o0, %l5
80050mov %o1, %l5
80051mov %o2, %l5
80052mov %o3, %l5
80053mov %o4, %l5
80054add %l4, 1, %l4
80055
80056P7688: !_PREFETCH [20] (Int)
80057prefetch [%i3 + 12], 31
80058
80059P7689: !_DWST_BINIT [0] (maybe <- 0x380011a) (Int)
80060wr %g0, 0xe2, %asi
80061sllx %l4, 32, %l6
80062add %l4, 1, %l4
80063or %l6, %l4, %l6
80064stxa %l6, [%i0 + 0] %asi
80065add %l4, 1, %l4
80066
80067P7690: !_MEMBAR (Int)
80068membar #StoreLoad
80069
80070P7691: !_ST_BINIT [7] (maybe <- 0x380011c) (Int)
80071wr %g0, 0xe2, %asi
80072sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
80073sub %i0, %i2, %i2
80074stwa %l4, [%i2 + 4] %asi
80075add %l4, 1, %l4
80076
80077P7692: !_MEMBAR (Int)
80078membar #StoreLoad
80079
80080P7693: !_DWST_BINIT [15] (maybe <- 0x380011d) (Int)
80081wr %g0, 0xe2, %asi
80082sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
80083add %i0, %i3, %i3
80084sllx %l4, 32, %o5
80085add %l4, 1, %l4
80086or %o5, %l4, %o5
80087stxa %o5, [%i3 + 0] %asi
80088add %l4, 1, %l4
80089
80090P7694: !_MEMBAR (Int)
80091membar #StoreLoad
80092
80093P7695: !_DWST_BINIT [13] (maybe <- 0x380011f) (Int)
80094wr %g0, 0xe2, %asi
80095sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
80096sub %i0, %i2, %i2
80097sllx %l4, 32, %l7
80098add %l4, 1, %l4
80099or %l7, %l4, %l7
80100stxa %l7, [%i2 + 0] %asi
80101add %l4, 1, %l4
80102
80103P7696: !_MEMBAR (Int)
80104membar #StoreLoad
80105
80106P7697: !_CASX [21] (maybe <- 0x3800121) (Int)
80107sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
80108sub %i0, %i3, %i3
80109ldx [%i3], %o0
80110! move %o0(upper) -> %o0(upper)
80111! move %o0(lower) -> %o0(lower)
80112mov %o0, %l6
80113sllx %l4, 32, %o1
80114add %l4, 1, %l4
80115or %l4, %o1, %o1
80116casx [%i3], %l6, %o1
80117! move %o1(upper) -> %o1(upper)
80118! move %o1(lower) -> %o1(lower)
80119add %l4, 1, %l4
80120
80121P7698: !_ST_BINIT [18] (maybe <- 0x3800123) (Int)
80122wr %g0, 0xe2, %asi
80123sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
80124sub %i0, %i2, %i2
80125stwa %l4, [%i2 + 0] %asi
80126add %l4, 1, %l4
80127
80128P7699: !_MEMBAR (Int)
80129membar #StoreLoad
80130
80131P7700: !_DWST [15] (maybe <- 0x3800124) (Int)
80132sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
80133add %i0, %i3, %i3
80134sllx %l4, 32, %l3
80135add %l4, 1, %l4
80136or %l3, %l4, %l3
80137stx %l3, [%i3 + 0]
80138add %l4, 1, %l4
80139
80140P7701: !_ST [19] (maybe <- 0x3800126) (Int)
80141stw %l4, [%i2 + 4 ]
80142add %l4, 1, %l4
80143
80144P7702: !_CAS [1] (maybe <- 0x3800127) (Int)
80145add %i0, 4, %o5
80146lduw [%o5], %o2
80147mov %o2, %l7
80148! move %l7(lower) -> %o2(upper)
80149sllx %l7, 32, %o2
80150mov %l4, %l6
80151cas [%o5], %l7, %l6
80152! move %l6(lower) -> %o2(lower)
80153srl %l6, 0, %l7
80154or %l7, %o2, %o2
80155add %l4, 1, %l4
80156
80157P7703: !_MEMBAR (FP) (CBR)
80158
80159! cbranch
80160andcc %l0, 1, %g0
80161be,pt %xcc, TARGET7703
80162nop
80163RET7703:
80164
80165! lfsr step begin
80166srlx %l0, 1, %l7
80167xnor %l7, %l0, %l7
80168sllx %l7, 63, %l7
80169or %l7, %l0, %l0
80170srlx %l0, 1, %l0
80171
80172
80173P7704: !_BSTC [7] (maybe <- 0x430000be) (FP)
80174wr %g0, 0xe0, %asi
80175sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
80176sub %i0, %i2, %i2
80177! preparing store val #0, next val will be in f32
80178fmovs %f16, %f20
80179fadds %f16, %f17, %f16
80180! preparing store val #1, next val will be in f33
80181fmovs %f16, %f21
80182fadds %f16, %f17, %f16
80183! preparing store val #2, next val will be in f35
80184fmovd %f20, %f32
80185fmovs %f16, %f21
80186fadds %f16, %f17, %f16
80187fmovd %f20, %f34
80188membar #Sync
80189stda %f32, [%i2 + 0 ] %asi
80190
80191P7705: !_MEMBAR (FP)
80192membar #StoreLoad
80193
80194P7706: !_SWAP [6] (maybe <- 0x3800128) (Int)
80195mov %l4, %o3
80196swap [%i2 + 0], %o3
80197! move %o3(lower) -> %o3(upper)
80198sllx %o3, 32, %o3
80199add %l4, 1, %l4
80200
80201P7707: !_ST [10] (maybe <- 0x3800129) (Int)
80202sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
80203sub %i0, %i3, %i3
80204stw %l4, [%i3 + 4 ]
80205add %l4, 1, %l4
80206
80207P7708: !_MEMBAR (FP)
80208
80209P7709: !_BSTC [9] (maybe <- 0x430000c1) (FP)
80210wr %g0, 0xe0, %asi
80211! preparing store val #0, next val will be in f32
80212fmovs %f16, %f20
80213fadds %f16, %f17, %f16
80214! preparing store val #1, next val will be in f33
80215fmovs %f16, %f21
80216fadds %f16, %f17, %f16
80217! preparing store val #2, next val will be in f35
80218fmovd %f20, %f32
80219fmovs %f16, %f21
80220fadds %f16, %f17, %f16
80221fmovd %f20, %f34
80222membar #Sync
80223stda %f32, [%i3 + 0 ] %asi
80224
80225P7710: !_MEMBAR (FP)
80226membar #StoreLoad
80227
80228P7711: !_DWLD [10] (Int)
80229ldx [%i3 + 0], %l3
80230! move %l3(upper) -> %o3(lower)
80231srlx %l3, 32, %o5
80232or %o5, %o3, %o3
80233! move %l3(lower) -> %o4(upper)
80234sllx %l3, 32, %o4
80235
80236P7712: !_MEMBAR (FP)
80237
80238P7713: !_BST [9] (maybe <- 0x430000c4) (FP) (CBR)
80239wr %g0, 0xf0, %asi
80240! preparing store val #0, next val will be in f32
80241fmovs %f16, %f20
80242fadds %f16, %f17, %f16
80243! preparing store val #1, next val will be in f33
80244fmovs %f16, %f21
80245fadds %f16, %f17, %f16
80246! preparing store val #2, next val will be in f35
80247fmovd %f20, %f32
80248fmovs %f16, %f21
80249fadds %f16, %f17, %f16
80250fmovd %f20, %f34
80251membar #Sync
80252stda %f32, [%i3 + 0 ] %asi
80253
80254! cbranch
80255andcc %l0, 1, %g0
80256be,pt %xcc, TARGET7713
80257nop
80258RET7713:
80259
80260! lfsr step begin
80261srlx %l0, 1, %l3
80262xnor %l3, %l0, %l3
80263sllx %l3, 63, %l3
80264or %l3, %l0, %l0
80265srlx %l0, 1, %l0
80266
80267
80268P7714: !_MEMBAR (FP)
80269membar #StoreLoad
80270
80271P7715: !_BLD [23] (FP)
80272wr %g0, 0xf0, %asi
80273sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
80274sub %i0, %i2, %i2
80275ldda [%i2 + 0] %asi, %f32
80276membar #Sync
80277! 3 addresses covered
80278fmovd %f32, %f6
80279fmovd %f34, %f18
80280fmovs %f19, %f8
80281
80282P7716: !_MEMBAR (FP)
80283
80284P7717: !_SWAP [11] (maybe <- 0x380012a) (Int)
80285mov %l4, %o5
80286swap [%i3 + 12], %o5
80287! move %o5(lower) -> %o4(lower)
80288srl %o5, 0, %l6
80289or %l6, %o4, %o4
80290!---- flushing int results buffer----
80291mov %o0, %l5
80292mov %o1, %l5
80293mov %o2, %l5
80294mov %o3, %l5
80295mov %o4, %l5
80296add %l4, 1, %l4
80297
80298P7718: !_ST_BINIT [22] (maybe <- 0x380012b) (Int)
80299wr %g0, 0xe2, %asi
80300stwa %l4, [%i2 + 4] %asi
80301add %l4, 1, %l4
80302
80303P7719: !_MEMBAR (Int)
80304membar #StoreLoad
80305
80306P7720: !_BLD [11] (FP)
80307wr %g0, 0xf0, %asi
80308ldda [%i3 + 0] %asi, %f32
80309membar #Sync
80310! 3 addresses covered
80311fmovd %f32, %f18
80312fmovs %f18, %f9
80313fmovs %f19, %f10
80314fmovd %f34, %f18
80315fmovs %f19, %f11
80316
80317P7721: !_MEMBAR (FP)
80318
80319P7722: !_BLD [11] (FP)
80320wr %g0, 0xf0, %asi
80321ldda [%i3 + 0] %asi, %f32
80322membar #Sync
80323! 3 addresses covered
80324fmovd %f32, %f12
80325fmovd %f34, %f18
80326fmovs %f19, %f14
80327
80328P7723: !_MEMBAR (FP)
80329
80330P7724: !_DWST [19] (maybe <- 0x380012c) (Int)
80331sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
80332sub %i0, %i3, %i3
80333sllx %l4, 32, %l3
80334add %l4, 1, %l4
80335or %l3, %l4, %l3
80336stx %l3, [%i3 + 0]
80337add %l4, 1, %l4
80338
80339P7725: !_DWST_BINIT [12] (maybe <- 0x380012e) (Int) (LE)
80340wr %g0, 0xea, %asi
80341sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
80342sub %i0, %i2, %i2
80343sllx %l4, 32, %o5
80344add %l4, 1, %l4
80345or %o5, %l4, %l3
80346! Change double-word-level endianess (big endian <-> little endian)
80347sethi %hi(0xff00ff00), %l6
80348or %l6, %lo(0xff00ff00), %l6
80349sllx %l6, 32, %o5
80350or %l6, %o5, %l6
80351and %l3, %l6, %o5
80352srlx %o5, 8, %o5
80353sllx %l3, 8, %l3
80354and %l3, %l6, %l3
80355or %l3, %o5, %l3
80356sethi %hi(0xffff0000), %l6
80357srlx %l3, 16, %o5
80358andn %o5, %l6, %o5
80359andn %l3, %l6, %l3
80360sllx %l3, 16, %l3
80361or %l3, %o5, %l3
80362srlx %l3, 32, %o5
80363sllx %l3, 32, %l3
80364or %l3, %o5, %o5
80365stxa %o5, [%i2 + 0 ] %asi
80366add %l4, 1, %l4
80367
80368P7726: !_MEMBAR (Int) (LE)
80369membar #StoreLoad
80370
80371P7727: !_LDD [21] (Int)
80372sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
80373sub %i0, %i3, %i3
80374ldd [%i3 + 0], %l6
80375! move %l6(lower) -> %o0(upper)
80376sllx %l6, 32, %o0
80377! move %l7(lower) -> %o0(lower)
80378or %l7, %o0, %o0
80379
80380P7728: !_CASX [12] (maybe <- 0x3800130) (Int)
80381ldx [%i2], %o1
80382! move %o1(upper) -> %o1(upper)
80383! move %o1(lower) -> %o1(lower)
80384mov %o1, %l3
80385sllx %l4, 32, %o2
80386add %l4, 1, %l4
80387or %l4, %o2, %o2
80388casx [%i2], %l3, %o2
80389! move %o2(upper) -> %o2(upper)
80390! move %o2(lower) -> %o2(lower)
80391add %l4, 1, %l4
80392
80393P7729: !_MEMBAR (FP)
80394
80395P7730: !_BSTC [22] (maybe <- 0x430000c7) (FP)
80396wr %g0, 0xe0, %asi
80397! preparing store val #0, next val will be in f32
80398fmovs %f16, %f20
80399fadds %f16, %f17, %f16
80400! preparing store val #1, next val will be in f33
80401fmovs %f16, %f21
80402fadds %f16, %f17, %f16
80403! preparing store val #2, next val will be in f35
80404fmovd %f20, %f32
80405fmovs %f16, %f21
80406fadds %f16, %f17, %f16
80407fmovd %f20, %f34
80408membar #Sync
80409stda %f32, [%i3 + 0 ] %asi
80410
80411P7731: !_MEMBAR (FP)
80412membar #StoreLoad
80413
80414P7732: !_CASX [10] (maybe <- 0x3800132) (Int)
80415sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
80416sub %i0, %i2, %i2
80417ldx [%i2], %o3
80418! move %o3(upper) -> %o3(upper)
80419! move %o3(lower) -> %o3(lower)
80420mov %o3, %o5
80421sllx %l4, 32, %o4
80422add %l4, 1, %l4
80423or %l4, %o4, %o4
80424casx [%i2], %o5, %o4
80425! move %o4(upper) -> %o4(upper)
80426! move %o4(lower) -> %o4(lower)
80427!---- flushing int results buffer----
80428mov %o0, %l5
80429mov %o1, %l5
80430mov %o2, %l5
80431mov %o3, %l5
80432mov %o4, %l5
80433add %l4, 1, %l4
80434
80435P7733: !_CASX [21] (maybe <- 0x3800134) (Int)
80436ldx [%i3], %o0
80437! move %o0(upper) -> %o0(upper)
80438! move %o0(lower) -> %o0(lower)
80439mov %o0, %o5
80440sllx %l4, 32, %o1
80441add %l4, 1, %l4
80442or %l4, %o1, %o1
80443casx [%i3], %o5, %o1
80444! move %o1(upper) -> %o1(upper)
80445! move %o1(lower) -> %o1(lower)
80446add %l4, 1, %l4
80447
80448P7734: !_SWAP [0] (maybe <- 0x3800136) (Int)
80449mov %l4, %o2
80450swap [%i0 + 0], %o2
80451! move %o2(lower) -> %o2(upper)
80452sllx %o2, 32, %o2
80453add %l4, 1, %l4
80454
80455P7735: !_MEMBAR (FP) (Branch target of P7703)
80456ba P7736
80457nop
80458
80459TARGET7703:
80460ba RET7703
80461nop
80462
80463
80464P7736: !_BST [21] (maybe <- 0x430000ca) (FP)
80465wr %g0, 0xf0, %asi
80466! preparing store val #0, next val will be in f32
80467fmovs %f16, %f20
80468fadds %f16, %f17, %f16
80469! preparing store val #1, next val will be in f33
80470fmovs %f16, %f21
80471fadds %f16, %f17, %f16
80472! preparing store val #2, next val will be in f35
80473fmovd %f20, %f32
80474fmovs %f16, %f21
80475fadds %f16, %f17, %f16
80476fmovd %f20, %f34
80477membar #Sync
80478stda %f32, [%i3 + 0 ] %asi
80479
80480P7737: !_MEMBAR (FP)
80481membar #StoreLoad
80482
80483P7738: !_ST [1] (maybe <- 0x3800137) (Int)
80484stw %l4, [%i0 + 4 ]
80485add %l4, 1, %l4
80486
80487P7739: !_LDD [18] (Int)
80488sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
80489sub %i0, %i3, %i3
80490ldd [%i3 + 0], %l6
80491! move %l6(lower) -> %o2(lower)
80492or %l6, %o2, %o2
80493! move %l7(lower) -> %o3(upper)
80494sllx %l7, 32, %o3
80495
80496P7740: !_DWST [17] (maybe <- 0x3800138) (Int)
80497sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
80498add %i0, %i2, %i2
80499mov %l4, %l3
80500stx %l3, [%i2 + 8]
80501add %l4, 1, %l4
80502
80503P7741: !_MEMBAR (FP)
80504
80505P7742: !_BST [10] (maybe <- 0x430000cd) (FP)
80506wr %g0, 0xf0, %asi
80507sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
80508sub %i0, %i3, %i3
80509! preparing store val #0, next val will be in f32
80510fmovs %f16, %f20
80511fadds %f16, %f17, %f16
80512! preparing store val #1, next val will be in f33
80513fmovs %f16, %f21
80514fadds %f16, %f17, %f16
80515! preparing store val #2, next val will be in f35
80516fmovd %f20, %f32
80517fmovs %f16, %f21
80518fadds %f16, %f17, %f16
80519fmovd %f20, %f34
80520membar #Sync
80521stda %f32, [%i3 + 0 ] %asi
80522
80523P7743: !_MEMBAR (FP)
80524membar #StoreLoad
80525
80526P7744: !_LD [14] (Int)
80527sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
80528sub %i0, %i2, %i2
80529lduw [%i2 + 12], %o5
80530! move %o5(lower) -> %o3(lower)
80531or %o5, %o3, %o3
80532
80533P7745: !_SWAP [13] (maybe <- 0x3800139) (Int)
80534mov %l4, %o4
80535swap [%i2 + 4], %o4
80536! move %o4(lower) -> %o4(upper)
80537sllx %o4, 32, %o4
80538add %l4, 1, %l4
80539
80540P7746: !_CAS [7] (maybe <- 0x380013a) (Int)
80541sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
80542sub %i0, %i3, %i3
80543add %i3, 4, %l3
80544lduw [%l3], %l7
80545mov %l7, %o5
80546! move %o5(lower) -> %o4(lower)
80547or %o5, %o4, %o4
80548!---- flushing int results buffer----
80549mov %o0, %l5
80550mov %o1, %l5
80551mov %o2, %l5
80552mov %o3, %l5
80553mov %o4, %l5
80554mov %l4, %o0
80555cas [%l3], %o5, %o0
80556! move %o0(lower) -> %o0(upper)
80557sllx %o0, 32, %o0
80558add %l4, 1, %l4
80559
80560P7747: !_DWST [20] (maybe <- 0x380013b) (Int)
80561sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
80562sub %i0, %i2, %i2
80563mov %l4, %o5
80564stx %o5, [%i2 + 8]
80565add %l4, 1, %l4
80566
80567P7748: !_CASX [7] (maybe <- 0x380013c) (Int)
80568ldx [%i3], %l6
80569! move %l6(upper) -> %o0(lower)
80570srlx %l6, 32, %l7
80571or %l7, %o0, %o0
80572! move %l6(lower) -> %o1(upper)
80573sllx %l6, 32, %o1
80574mov %l6, %l7
80575sllx %l4, 32, %l6
80576add %l4, 1, %l4
80577or %l4, %l6, %l6
80578casx [%i3], %l7, %l6
80579! move %l6(upper) -> %o1(lower)
80580srlx %l6, 32, %l7
80581or %l7, %o1, %o1
80582! move %l6(lower) -> %o2(upper)
80583sllx %l6, 32, %o2
80584add %l4, 1, %l4
80585
80586P7749: !_PREFETCH [3] (Int)
80587prefetch [%i1 + 0], 1
80588
80589P7750: !_DWST_BINIT [23] (maybe <- 0x380013e) (Int)
80590wr %g0, 0xe2, %asi
80591sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
80592sub %i0, %i3, %i3
80593mov %l4, %l7
80594stxa %l7, [%i3 + 8] %asi
80595add %l4, 1, %l4
80596
80597P7751: !_MEMBAR (Int)
80598
80599P7752: !_BSTC [11] (maybe <- 0x430000d0) (FP)
80600wr %g0, 0xe0, %asi
80601sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
80602sub %i0, %i2, %i2
80603! preparing store val #0, next val will be in f32
80604fmovs %f16, %f20
80605fadds %f16, %f17, %f16
80606! preparing store val #1, next val will be in f33
80607fmovs %f16, %f21
80608fadds %f16, %f17, %f16
80609! preparing store val #2, next val will be in f35
80610fmovd %f20, %f32
80611fmovs %f16, %f21
80612fadds %f16, %f17, %f16
80613fmovd %f20, %f34
80614membar #Sync
80615stda %f32, [%i2 + 0 ] %asi
80616
80617P7753: !_MEMBAR (FP)
80618membar #StoreLoad
80619
80620P7754: !_CASX [20] (maybe <- 0x380013f) (Int)
80621sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
80622sub %i0, %i3, %i3
80623add %i3, 8, %l6
80624ldx [%l6], %o5
80625! move %o5(upper) -> %o2(lower)
80626srlx %o5, 32, %l3
80627or %l3, %o2, %o2
80628! move %o5(lower) -> %o3(upper)
80629sllx %o5, 32, %o3
80630mov %o5, %l3
80631mov %l4, %o5
80632casx [%l6], %l3, %o5
80633! move %o5(upper) -> %o3(lower)
80634srlx %o5, 32, %l3
80635or %l3, %o3, %o3
80636! move %o5(lower) -> %o4(upper)
80637sllx %o5, 32, %o4
80638add %l4, 1, %l4
80639
80640P7755: !_CAS [12] (maybe <- 0x3800140) (Int)
80641sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
80642sub %i0, %i2, %i2
80643lduw [%i2], %o5
80644mov %o5, %l3
80645! move %l3(lower) -> %o4(lower)
80646or %l3, %o4, %o4
80647!---- flushing int results buffer----
80648mov %o0, %l5
80649mov %o1, %l5
80650mov %o2, %l5
80651mov %o3, %l5
80652mov %o4, %l5
80653mov %l4, %o0
80654cas [%i2], %l3, %o0
80655! move %o0(lower) -> %o0(upper)
80656sllx %o0, 32, %o0
80657add %l4, 1, %l4
80658
80659P7756: !_SWAP [17] (maybe <- 0x3800141) (Int)
80660sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i3
80661add %i0, %i3, %i3
80662mov %l4, %l7
80663swap [%i3 + 12], %l7
80664! move %l7(lower) -> %o0(lower)
80665srl %l7, 0, %l3
80666or %l3, %o0, %o0
80667add %l4, 1, %l4
80668
80669P7757: !_MEMBAR (FP)
80670membar #StoreLoad
80671
80672P7758: !_BLD [4] (FP)
80673wr %g0, 0xf0, %asi
80674ldda [%i1 + 0] %asi, %f32
80675membar #Sync
80676! 3 addresses covered
80677fmovd %f32, %f18
80678fmovs %f18, %f15
80679!---- flushing fp results buffer to %f30 ----
80680fmovd %f0, %f30
80681fmovd %f2, %f30
80682fmovd %f4, %f30
80683fmovd %f6, %f30
80684fmovd %f8, %f30
80685fmovd %f10, %f30
80686fmovd %f12, %f30
80687fmovd %f14, %f30
80688!--
80689fmovs %f19, %f0
80690fmovd %f34, %f18
80691fmovs %f19, %f1
80692
80693P7759: !_MEMBAR (FP)
80694
80695P7760: !_LD [12] (Int)
80696lduw [%i2 + 0], %o1
80697! move %o1(lower) -> %o1(upper)
80698sllx %o1, 32, %o1
80699
80700P7761: !_DWLD [5] (Int)
80701ldx [%i1 + 8], %l7
80702! move %l7(lower) -> %o1(lower)
80703srl %l7, 0, %l6
80704or %l6, %o1, %o1
80705
80706P7762: !_ST [9] (maybe <- 0x3800142) (Int)
80707sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
80708sub %i0, %i2, %i2
80709stw %l4, [%i2 + 0 ]
80710add %l4, 1, %l4
80711
80712P7763: !_ST [13] (maybe <- 0x3800143) (Int)
80713sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
80714sub %i0, %i3, %i3
80715stw %l4, [%i3 + 4 ]
80716add %l4, 1, %l4
80717
80718P7764: !_DWST [8] (maybe <- 0x3800144) (Int) (CBR)
80719sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
80720sub %i0, %i2, %i2
80721mov %l4, %l6
80722stx %l6, [%i2 + 8]
80723add %l4, 1, %l4
80724
80725! cbranch
80726andcc %l0, 1, %g0
80727be,pt %xcc, TARGET7764
80728nop
80729RET7764:
80730
80731! lfsr step begin
80732srlx %l0, 1, %l3
80733xnor %l3, %l0, %l3
80734sllx %l3, 63, %l3
80735or %l3, %l0, %l0
80736srlx %l0, 1, %l0
80737
80738
80739P7765: !_REPLACEMENT [11] (Int)
80740sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS1_O), %i3
80741sub %i0, %i3, %i3
80742sethi %hi(0x20000), %l6
80743ld [%i3+12], %o5
80744st %o5, [%i3+12]
80745add %i3, %l6, %l7
80746ld [%l7+12], %o5
80747st %o5, [%l7+12]
80748add %l7, %l6, %l7
80749ld [%l7+12], %o5
80750st %o5, [%l7+12]
80751add %l7, %l6, %l7
80752ld [%l7+12], %o5
80753st %o5, [%l7+12]
80754add %l7, %l6, %l7
80755ld [%l7+12], %o5
80756st %o5, [%l7+12]
80757add %l7, %l6, %l7
80758ld [%l7+12], %o5
80759st %o5, [%l7+12]
80760add %l7, %l6, %l7
80761ld [%l7+12], %o5
80762st %o5, [%l7+12]
80763add %l7, %l6, %l7
80764ld [%l7+12], %o5
80765st %o5, [%l7+12]
80766
80767P7766: !_PREFETCH [12] (Int)
80768sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
80769sub %i0, %i2, %i2
80770prefetch [%i2 + 0], 17
80771
80772P7767: !_CASX [4] (maybe <- 0x3800145) (Int)
80773ldx [%i1], %o2
80774! move %o2(upper) -> %o2(upper)
80775! move %o2(lower) -> %o2(lower)
80776mov %o2, %l3
80777sllx %l4, 32, %o3
80778add %l4, 1, %l4
80779or %l4, %o3, %o3
80780casx [%i1], %l3, %o3
80781! move %o3(upper) -> %o3(upper)
80782! move %o3(lower) -> %o3(lower)
80783add %l4, 1, %l4
80784
80785P7768: !_MEMBAR (FP)
80786
80787P7769: !_BSTC [11] (maybe <- 0x430000d3) (FP)
80788wr %g0, 0xe0, %asi
80789sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
80790sub %i0, %i3, %i3
80791! preparing store val #0, next val will be in f32
80792fmovs %f16, %f20
80793fadds %f16, %f17, %f16
80794! preparing store val #1, next val will be in f33
80795fmovs %f16, %f21
80796fadds %f16, %f17, %f16
80797! preparing store val #2, next val will be in f35
80798fmovd %f20, %f32
80799fmovs %f16, %f21
80800fadds %f16, %f17, %f16
80801fmovd %f20, %f34
80802membar #Sync
80803stda %f32, [%i3 + 0 ] %asi
80804
80805P7770: !_MEMBAR (FP)
80806membar #StoreLoad
80807
80808P7771: !_ST_BINIT [6] (maybe <- 0x3800147) (Int)
80809wr %g0, 0xe2, %asi
80810sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
80811sub %i0, %i2, %i2
80812stwa %l4, [%i2 + 0] %asi
80813add %l4, 1, %l4
80814
80815P7772: !_MEMBAR (Int)
80816membar #StoreLoad
80817
80818P7773: !_LD [9] (Int)
80819lduw [%i3 + 0], %o4
80820! move %o4(lower) -> %o4(upper)
80821sllx %o4, 32, %o4
80822
80823P7774: !_LD [4] (Int)
80824lduw [%i1 + 4], %l6
80825! move %l6(lower) -> %o4(lower)
80826or %l6, %o4, %o4
80827!---- flushing int results buffer----
80828mov %o0, %l5
80829mov %o1, %l5
80830mov %o2, %l5
80831mov %o3, %l5
80832mov %o4, %l5
80833
80834P7775: !_PREFETCH [14] (Int)
80835sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
80836sub %i0, %i3, %i3
80837prefetch [%i3 + 12], 3
80838
80839P7776: !_CAS [6] (maybe <- 0x3800148) (Int)
80840lduw [%i2], %o0
80841mov %o0, %l7
80842! move %l7(lower) -> %o0(upper)
80843sllx %l7, 32, %o0
80844mov %l4, %l6
80845cas [%i2], %l7, %l6
80846! move %l6(lower) -> %o0(lower)
80847srl %l6, 0, %l7
80848or %l7, %o0, %o0
80849add %l4, 1, %l4
80850
80851P7777: !_MEMBAR (FP)
80852
80853P7778: !_BST [5] (maybe <- 0x430000d6) (FP)
80854wr %g0, 0xf0, %asi
80855! preparing store val #0, next val will be in f32
80856fmovs %f16, %f20
80857fadds %f16, %f17, %f16
80858! preparing store val #1, next val will be in f33
80859fmovs %f16, %f21
80860fadds %f16, %f17, %f16
80861! preparing store val #2, next val will be in f35
80862fmovd %f20, %f32
80863fmovs %f16, %f21
80864fadds %f16, %f17, %f16
80865fmovd %f20, %f34
80866membar #Sync
80867stda %f32, [%i1 + 0 ] %asi
80868
80869P7779: !_MEMBAR (FP)
80870membar #StoreLoad
80871
80872P7780: !_LDD [21] (Int) (CBR) (Branch target of P7591)
80873sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
80874sub %i0, %i2, %i2
80875ldd [%i2 + 0], %l6
80876! move %l6(lower) -> %o1(upper)
80877sllx %l6, 32, %o1
80878! move %l7(lower) -> %o1(lower)
80879or %l7, %o1, %o1
80880
80881! cbranch
80882andcc %l0, 1, %g0
80883be,pn %xcc, TARGET7780
80884nop
80885RET7780:
80886
80887! lfsr step begin
80888srlx %l0, 1, %l3
80889xnor %l3, %l0, %l3
80890sllx %l3, 63, %l3
80891or %l3, %l0, %l0
80892srlx %l0, 1, %l0
80893
80894ba P7781
80895nop
80896
80897TARGET7591:
80898ba RET7591
80899nop
80900
80901
80902P7781: !_MEMBAR (FP)
80903membar #StoreLoad
80904
80905P7782: !_BLD [1] (FP) (Branch target of P7543)
80906wr %g0, 0xf0, %asi
80907ldda [%i0 + 0] %asi, %f32
80908membar #Sync
80909! 3 addresses covered
80910fmovd %f32, %f2
80911fmovd %f34, %f18
80912fmovs %f19, %f4
80913ba P7783
80914nop
80915
80916TARGET7543:
80917ba RET7543
80918nop
80919
80920
80921P7783: !_MEMBAR (FP)
80922
80923P7784: !_CAS [21] (maybe <- 0x3800149) (Int) (Branch target of P7806)
80924lduw [%i2], %o2
80925mov %o2, %l7
80926! move %l7(lower) -> %o2(upper)
80927sllx %l7, 32, %o2
80928mov %l4, %l6
80929cas [%i2], %l7, %l6
80930! move %l6(lower) -> %o2(lower)
80931srl %l6, 0, %l7
80932or %l7, %o2, %o2
80933add %l4, 1, %l4
80934ba P7785
80935nop
80936
80937TARGET7806:
80938ba RET7806
80939nop
80940
80941
80942P7785: !_DWST_BINIT [5] (maybe <- 0x380014a) (Int)
80943wr %g0, 0xe2, %asi
80944mov %l4, %l7
80945stxa %l7, [%i1 + 8] %asi
80946add %l4, 1, %l4
80947
80948P7786: !_MEMBAR (Int)
80949membar #StoreLoad
80950
80951P7787: !_LD [22] (Int)
80952lduw [%i2 + 4], %o3
80953! move %o3(lower) -> %o3(upper)
80954sllx %o3, 32, %o3
80955
80956P7788: !_SWAP [21] (maybe <- 0x380014b) (Int)
80957mov %l4, %l6
80958swap [%i2 + 0], %l6
80959! move %l6(lower) -> %o3(lower)
80960srl %l6, 0, %o5
80961or %o5, %o3, %o3
80962add %l4, 1, %l4
80963
80964P7789: !_MEMBAR (FP)
80965
80966P7790: !_BST [10] (maybe <- 0x430000d9) (FP)
80967wr %g0, 0xf0, %asi
80968sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
80969sub %i0, %i3, %i3
80970! preparing store val #0, next val will be in f32
80971fmovs %f16, %f20
80972fadds %f16, %f17, %f16
80973! preparing store val #1, next val will be in f33
80974fmovs %f16, %f21
80975fadds %f16, %f17, %f16
80976! preparing store val #2, next val will be in f35
80977fmovd %f20, %f32
80978fmovs %f16, %f21
80979fadds %f16, %f17, %f16
80980fmovd %f20, %f34
80981membar #Sync
80982stda %f32, [%i3 + 0 ] %asi
80983
80984P7791: !_MEMBAR (FP)
80985membar #StoreLoad
80986
80987P7792: !_DWST_BINIT [9] (maybe <- 0x380014c) (Int)
80988wr %g0, 0xe2, %asi
80989sllx %l4, 32, %l6
80990add %l4, 1, %l4
80991or %l6, %l4, %l6
80992stxa %l6, [%i3 + 0] %asi
80993add %l4, 1, %l4
80994
80995P7793: !_MEMBAR (Int)
80996membar #StoreLoad
80997
80998P7794: !_CASX [14] (maybe <- 0x380014e) (Int)
80999sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
81000sub %i0, %i2, %i2
81001add %i2, 8, %l6
81002ldx [%l6], %o4
81003! move %o4(upper) -> %o4(upper)
81004! move %o4(lower) -> %o4(lower)
81005!---- flushing int results buffer----
81006mov %o0, %l5
81007mov %o1, %l5
81008mov %o2, %l5
81009mov %o3, %l5
81010mov %o4, %l5
81011mov %o4, %l3
81012mov %l4, %o0
81013casx [%l6], %l3, %o0
81014! move %o0(upper) -> %o0(upper)
81015! move %o0(lower) -> %o0(lower)
81016add %l4, 1, %l4
81017
81018P7795: !_MEMBAR (FP)
81019membar #StoreLoad
81020
81021P7796: !_BLD [21] (FP)
81022wr %g0, 0xf0, %asi
81023sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
81024sub %i0, %i3, %i3
81025ldda [%i3 + 0] %asi, %f32
81026membar #Sync
81027! 3 addresses covered
81028fmovd %f32, %f18
81029fmovs %f18, %f5
81030fmovs %f19, %f6
81031fmovd %f34, %f18
81032fmovs %f19, %f7
81033
81034P7797: !_MEMBAR (FP)
81035
81036P7798: !_PREFETCH [22] (Int)
81037prefetch [%i3 + 4], 29
81038
81039P7799: !_MEMBAR (FP)
81040
81041P7800: !_BSTC [21] (maybe <- 0x430000dc) (FP)
81042wr %g0, 0xe0, %asi
81043! preparing store val #0, next val will be in f32
81044fmovs %f16, %f20
81045fadds %f16, %f17, %f16
81046! preparing store val #1, next val will be in f33
81047fmovs %f16, %f21
81048fadds %f16, %f17, %f16
81049! preparing store val #2, next val will be in f35
81050fmovd %f20, %f32
81051fmovs %f16, %f21
81052fadds %f16, %f17, %f16
81053fmovd %f20, %f34
81054membar #Sync
81055stda %f32, [%i3 + 0 ] %asi
81056
81057P7801: !_MEMBAR (FP)
81058membar #StoreLoad
81059
81060P7802: !_PREFETCH [4] (Int)
81061prefetch [%i1 + 4], 1
81062
81063P7803: !_MEMBAR (FP)
81064
81065P7804: !_BSTC [3] (maybe <- 0x430000df) (FP)
81066wr %g0, 0xe0, %asi
81067! preparing store val #0, next val will be in f32
81068fmovs %f16, %f20
81069fadds %f16, %f17, %f16
81070! preparing store val #1, next val will be in f33
81071fmovs %f16, %f21
81072fadds %f16, %f17, %f16
81073! preparing store val #2, next val will be in f35
81074fmovd %f20, %f32
81075fmovs %f16, %f21
81076fadds %f16, %f17, %f16
81077fmovd %f20, %f34
81078membar #Sync
81079stda %f32, [%i1 + 0 ] %asi
81080
81081P7805: !_MEMBAR (FP)
81082membar #StoreLoad
81083
81084P7806: !_ST_BINIT [19] (maybe <- 0x380014f) (Int) (LE) (CBR)
81085wr %g0, 0xea, %asi
81086sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
81087sub %i0, %i2, %i2
81088! Change single-word-level endianess (big endian <-> little endian)
81089sethi %hi(0xff00ff00), %o5
81090or %o5, %lo(0xff00ff00), %o5
81091and %l4, %o5, %l3
81092srl %l3, 8, %l3
81093sll %l4, 8, %l7
81094and %l7, %o5, %l7
81095or %l7, %l3, %l7
81096srl %l7, 16, %l3
81097sll %l7, 16, %l7
81098srl %l7, 0, %l7
81099or %l7, %l3, %l7
81100stwa %l7, [%i2 + 4] %asi
81101add %l4, 1, %l4
81102
81103! cbranch
81104andcc %l0, 1, %g0
81105be,pn %xcc, TARGET7806
81106nop
81107RET7806:
81108
81109! lfsr step begin
81110srlx %l0, 1, %l6
81111xnor %l6, %l0, %l6
81112sllx %l6, 63, %l6
81113or %l6, %l0, %l0
81114srlx %l0, 1, %l0
81115
81116
81117P7807: !_MEMBAR (Int) (LE)
81118membar #StoreLoad
81119
81120P7808: !_SWAP [5] (maybe <- 0x3800150) (Int)
81121mov %l4, %o1
81122swap [%i1 + 12], %o1
81123! move %o1(lower) -> %o1(upper)
81124sllx %o1, 32, %o1
81125add %l4, 1, %l4
81126
81127P7809: !_MEMBAR (FP)
81128
81129P7810: !_BST [21] (maybe <- 0x430000e2) (FP)
81130wr %g0, 0xf0, %asi
81131! preparing store val #0, next val will be in f32
81132fmovs %f16, %f20
81133fadds %f16, %f17, %f16
81134! preparing store val #1, next val will be in f33
81135fmovs %f16, %f21
81136fadds %f16, %f17, %f16
81137! preparing store val #2, next val will be in f35
81138fmovd %f20, %f32
81139fmovs %f16, %f21
81140fadds %f16, %f17, %f16
81141fmovd %f20, %f34
81142membar #Sync
81143stda %f32, [%i3 + 0 ] %asi
81144
81145P7811: !_MEMBAR (FP) (CBR)
81146membar #StoreLoad
81147
81148! cbranch
81149andcc %l0, 1, %g0
81150be,pt %xcc, TARGET7811
81151nop
81152RET7811:
81153
81154! lfsr step begin
81155srlx %l0, 1, %l3
81156xnor %l3, %l0, %l3
81157sllx %l3, 63, %l3
81158or %l3, %l0, %l0
81159srlx %l0, 1, %l0
81160
81161
81162P7812: !_LD [22] (Int)
81163lduw [%i3 + 4], %l7
81164! move %l7(lower) -> %o1(lower)
81165or %l7, %o1, %o1
81166
81167P7813: !_SWAP [14] (maybe <- 0x3800151) (Int)
81168sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
81169sub %i0, %i3, %i3
81170mov %l4, %o2
81171swap [%i3 + 12], %o2
81172! move %o2(lower) -> %o2(upper)
81173sllx %o2, 32, %o2
81174add %l4, 1, %l4
81175
81176P7814: !_MEMBAR (FP)
81177
81178P7815: !_BST [23] (maybe <- 0x430000e5) (FP)
81179wr %g0, 0xf0, %asi
81180sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
81181sub %i0, %i2, %i2
81182! preparing store val #0, next val will be in f32
81183fmovs %f16, %f20
81184fadds %f16, %f17, %f16
81185! preparing store val #1, next val will be in f33
81186fmovs %f16, %f21
81187fadds %f16, %f17, %f16
81188! preparing store val #2, next val will be in f35
81189fmovd %f20, %f32
81190fmovs %f16, %f21
81191fadds %f16, %f17, %f16
81192fmovd %f20, %f34
81193membar #Sync
81194stda %f32, [%i2 + 0 ] %asi
81195
81196P7816: !_MEMBAR (FP)
81197membar #StoreLoad
81198
81199P7817: !_LDD [10] (Int)
81200sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
81201sub %i0, %i3, %i3
81202ldd [%i3 + 0], %l6
81203! move %l6(lower) -> %o2(lower)
81204or %l6, %o2, %o2
81205! move %l7(lower) -> %o3(upper)
81206sllx %l7, 32, %o3
81207
81208P7818: !_CASX [15] (maybe <- 0x3800152) (Int)
81209sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
81210add %i0, %i2, %i2
81211ldx [%i2], %o5
81212! move %o5(upper) -> %o3(lower)
81213srlx %o5, 32, %l3
81214or %l3, %o3, %o3
81215! move %o5(lower) -> %o4(upper)
81216sllx %o5, 32, %o4
81217mov %o5, %l3
81218sllx %l4, 32, %o5
81219add %l4, 1, %l4
81220or %l4, %o5, %o5
81221casx [%i2], %l3, %o5
81222! move %o5(upper) -> %o4(lower)
81223srlx %o5, 32, %l3
81224or %l3, %o4, %o4
81225!---- flushing int results buffer----
81226mov %o0, %l5
81227mov %o1, %l5
81228mov %o2, %l5
81229mov %o3, %l5
81230mov %o4, %l5
81231! move %o5(lower) -> %o0(upper)
81232sllx %o5, 32, %o0
81233add %l4, 1, %l4
81234
81235P7819: !_MEMBAR (FP)
81236
81237P7820: !_BST [6] (maybe <- 0x430000e8) (FP)
81238wr %g0, 0xf0, %asi
81239sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
81240sub %i0, %i3, %i3
81241! preparing store val #0, next val will be in f32
81242fmovs %f16, %f20
81243fadds %f16, %f17, %f16
81244! preparing store val #1, next val will be in f33
81245fmovs %f16, %f21
81246fadds %f16, %f17, %f16
81247! preparing store val #2, next val will be in f35
81248fmovd %f20, %f32
81249fmovs %f16, %f21
81250fadds %f16, %f17, %f16
81251fmovd %f20, %f34
81252membar #Sync
81253stda %f32, [%i3 + 0 ] %asi
81254
81255P7821: !_MEMBAR (FP)
81256membar #StoreLoad
81257
81258P7822: !_REPLACEMENT [10] (Int)
81259sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
81260sub %i0, %i2, %i2
81261sethi %hi(0x20000), %o5
81262ld [%i2+4], %l6
81263st %l6, [%i2+4]
81264add %i2, %o5, %l3
81265ld [%l3+4], %l6
81266st %l6, [%l3+4]
81267add %l3, %o5, %l3
81268ld [%l3+4], %l6
81269st %l6, [%l3+4]
81270add %l3, %o5, %l3
81271ld [%l3+4], %l6
81272st %l6, [%l3+4]
81273add %l3, %o5, %l3
81274ld [%l3+4], %l6
81275st %l6, [%l3+4]
81276add %l3, %o5, %l3
81277ld [%l3+4], %l6
81278st %l6, [%l3+4]
81279add %l3, %o5, %l3
81280ld [%l3+4], %l6
81281st %l6, [%l3+4]
81282add %l3, %o5, %l3
81283ld [%l3+4], %l6
81284st %l6, [%l3+4]
81285
81286P7823: !_SWAP [10] (maybe <- 0x3800154) (Int)
81287sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
81288sub %i0, %i3, %i3
81289mov %l4, %l3
81290swap [%i3 + 4], %l3
81291! move %l3(lower) -> %o0(lower)
81292srl %l3, 0, %l7
81293or %l7, %o0, %o0
81294add %l4, 1, %l4
81295
81296P7824: !_MEMBAR (FP)
81297
81298P7825: !_BSTC [7] (maybe <- 0x430000eb) (FP)
81299wr %g0, 0xe0, %asi
81300sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
81301sub %i0, %i2, %i2
81302! preparing store val #0, next val will be in f32
81303fmovs %f16, %f20
81304fadds %f16, %f17, %f16
81305! preparing store val #1, next val will be in f33
81306fmovs %f16, %f21
81307fadds %f16, %f17, %f16
81308! preparing store val #2, next val will be in f35
81309fmovd %f20, %f32
81310fmovs %f16, %f21
81311fadds %f16, %f17, %f16
81312fmovd %f20, %f34
81313membar #Sync
81314stda %f32, [%i2 + 0 ] %asi
81315
81316P7826: !_MEMBAR (FP)
81317
81318P7827: !_BST [20] (maybe <- 0x430000ee) (FP)
81319wr %g0, 0xf0, %asi
81320sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
81321sub %i0, %i3, %i3
81322! preparing store val #0, next val will be in f32
81323fmovs %f16, %f20
81324fadds %f16, %f17, %f16
81325! preparing store val #1, next val will be in f33
81326fmovs %f16, %f21
81327fadds %f16, %f17, %f16
81328! preparing store val #2, next val will be in f35
81329fmovd %f20, %f32
81330fmovs %f16, %f21
81331fadds %f16, %f17, %f16
81332fmovd %f20, %f34
81333membar #Sync
81334stda %f32, [%i3 + 0 ] %asi
81335
81336P7828: !_MEMBAR (FP)
81337membar #StoreLoad
81338
81339P7829: !_DWST_BINIT [9] (maybe <- 0x3800155) (Int)
81340wr %g0, 0xe2, %asi
81341sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
81342sub %i0, %i2, %i2
81343sllx %l4, 32, %o5
81344add %l4, 1, %l4
81345or %o5, %l4, %o5
81346stxa %o5, [%i2 + 0] %asi
81347add %l4, 1, %l4
81348
81349P7830: !_MEMBAR (Int)
81350membar #StoreLoad
81351
81352P7831: !_SWAP [13] (maybe <- 0x3800157) (Int) (LE)
81353wr %g0, 0x88, %asi
81354sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
81355sub %i0, %i3, %i3
81356mov %l4, %o1
81357! Change single-word-level endianess (big endian <-> little endian)
81358sethi %hi(0xff00ff00), %l7
81359or %l7, %lo(0xff00ff00), %l7
81360and %o1, %l7, %o5
81361srl %o5, 8, %o5
81362sll %o1, 8, %o1
81363and %o1, %l7, %o1
81364or %o1, %o5, %o1
81365srl %o1, 16, %o5
81366sll %o1, 16, %o1
81367srl %o1, 0, %o1
81368or %o1, %o5, %o1
81369swapa [%i3 + 4] %asi, %o1
81370! move %o1(lower) -> %o1(upper)
81371sllx %o1, 32, %o1
81372add %l4, 1, %l4
81373
81374P7832: !_CASX [4] (maybe <- 0x3800158) (Int)
81375ldx [%i1], %l3
81376! move %l3(upper) -> %o1(lower)
81377srlx %l3, 32, %l6
81378or %l6, %o1, %o1
81379! move %l3(lower) -> %o2(upper)
81380sllx %l3, 32, %o2
81381mov %l3, %l6
81382sllx %l4, 32, %l3
81383add %l4, 1, %l4
81384or %l4, %l3, %l3
81385casx [%i1], %l6, %l3
81386! move %l3(upper) -> %o2(lower)
81387srlx %l3, 32, %l6
81388or %l6, %o2, %o2
81389! move %l3(lower) -> %o3(upper)
81390sllx %l3, 32, %o3
81391add %l4, 1, %l4
81392
81393P7833: !_DWLD [17] (FP)
81394sethi %hi(REGION5_ALIAS0_O-REGION0_ALIAS0_O), %i2
81395add %i0, %i2, %i2
81396ldd [%i2 + 8], %f8
81397! 1 addresses covered
81398fmovs %f9, %f8
81399
81400P7834: !_PREFETCH [10] (Int)
81401sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
81402sub %i0, %i3, %i3
81403prefetch [%i3 + 4], 23
81404
81405P7835: !_PREFETCH [5] (Int) (LE) (CBR)
81406wr %g0, 0x88, %asi
81407prefetcha [%i1 + 12] %asi, 4
81408
81409! cbranch
81410andcc %l0, 1, %g0
81411be,pt %xcc, TARGET7835
81412nop
81413RET7835:
81414
81415! lfsr step begin
81416srlx %l0, 1, %l6
81417xnor %l6, %l0, %l6
81418sllx %l6, 63, %l6
81419or %l6, %l0, %l0
81420srlx %l0, 1, %l0
81421
81422
81423P7836: !_DWLD [2] (Int)
81424ldx [%i0 + 8], %o5
81425! move %o5(lower) -> %o3(lower)
81426srl %o5, 0, %l7
81427or %l7, %o3, %o3
81428
81429P7837: !_MEMBAR (FP)
81430
81431P7838: !_BSTC [19] (maybe <- 0x430000f1) (FP)
81432wr %g0, 0xe0, %asi
81433sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
81434sub %i0, %i2, %i2
81435! preparing store val #0, next val will be in f32
81436fmovs %f16, %f20
81437fadds %f16, %f17, %f16
81438! preparing store val #1, next val will be in f33
81439fmovs %f16, %f21
81440fadds %f16, %f17, %f16
81441! preparing store val #2, next val will be in f35
81442fmovd %f20, %f32
81443fmovs %f16, %f21
81444fadds %f16, %f17, %f16
81445fmovd %f20, %f34
81446membar #Sync
81447stda %f32, [%i2 + 0 ] %asi
81448
81449P7839: !_MEMBAR (FP) (Branch target of P7892)
81450membar #StoreLoad
81451ba P7840
81452nop
81453
81454TARGET7892:
81455ba RET7892
81456nop
81457
81458
81459P7840: !_DWST [19] (maybe <- 0x430000f4) (FP)
81460! preparing store val #0, next val will be in f20
81461fmovs %f16, %f20
81462fadds %f16, %f17, %f16
81463! preparing store val #1, next val will be in f21
81464fmovs %f16, %f21
81465fadds %f16, %f17, %f16
81466std %f20, [%i2 + 0]
81467
81468P7841: !_DWST_BINIT [20] (maybe <- 0x380015a) (Int)
81469wr %g0, 0xe2, %asi
81470mov %l4, %l7
81471stxa %l7, [%i2 + 8] %asi
81472add %l4, 1, %l4
81473
81474P7842: !_MEMBAR (Int)
81475membar #StoreLoad
81476
81477P7843: !_DWST_BINIT [18] (maybe <- 0x380015b) (Int)
81478wr %g0, 0xe2, %asi
81479sllx %l4, 32, %l6
81480add %l4, 1, %l4
81481or %l6, %l4, %l6
81482stxa %l6, [%i2 + 0] %asi
81483add %l4, 1, %l4
81484
81485P7844: !_MEMBAR (Int) (Branch target of P7650)
81486membar #StoreLoad
81487ba P7845
81488nop
81489
81490TARGET7650:
81491ba RET7650
81492nop
81493
81494
81495P7845: !_SWAP [9] (maybe <- 0x380015d) (Int)
81496mov %l4, %o4
81497swap [%i3 + 0], %o4
81498! move %o4(lower) -> %o4(upper)
81499sllx %o4, 32, %o4
81500add %l4, 1, %l4
81501
81502P7846: !_MEMBAR (FP)
81503
81504P7847: !_BST [15] (maybe <- 0x430000f6) (FP)
81505wr %g0, 0xf0, %asi
81506sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
81507sub %i0, %i3, %i3
81508! preparing store val #0, next val will be in f32
81509fmovs %f16, %f20
81510fadds %f16, %f17, %f16
81511! preparing store val #1, next val will be in f33
81512fmovs %f16, %f21
81513fadds %f16, %f17, %f16
81514! preparing store val #2, next val will be in f35
81515fmovd %f20, %f32
81516fmovs %f16, %f21
81517fadds %f16, %f17, %f16
81518fmovd %f20, %f34
81519membar #Sync
81520stda %f32, [%i3 + 0 ] %asi
81521
81522P7848: !_MEMBAR (FP)
81523membar #StoreLoad
81524
81525P7849: !_LD [11] (Int)
81526sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
81527sub %i0, %i2, %i2
81528lduw [%i2 + 12], %l3
81529! move %l3(lower) -> %o4(lower)
81530or %l3, %o4, %o4
81531!---- flushing int results buffer----
81532mov %o0, %l5
81533mov %o1, %l5
81534mov %o2, %l5
81535mov %o3, %l5
81536mov %o4, %l5
81537
81538P7850: !_MEMBAR (FP)
81539
81540P7851: !_BST [10] (maybe <- 0x430000f9) (FP)
81541wr %g0, 0xf0, %asi
81542! preparing store val #0, next val will be in f32
81543fmovs %f16, %f20
81544fadds %f16, %f17, %f16
81545! preparing store val #1, next val will be in f33
81546fmovs %f16, %f21
81547fadds %f16, %f17, %f16
81548! preparing store val #2, next val will be in f35
81549fmovd %f20, %f32
81550fmovs %f16, %f21
81551fadds %f16, %f17, %f16
81552fmovd %f20, %f34
81553membar #Sync
81554stda %f32, [%i2 + 0 ] %asi
81555
81556P7852: !_MEMBAR (FP)
81557membar #StoreLoad
81558
81559P7853: !_CASX [2] (maybe <- 0x380015e) (Int)
81560add %i0, 8, %l6
81561ldx [%l6], %o0
81562! move %o0(upper) -> %o0(upper)
81563! move %o0(lower) -> %o0(lower)
81564mov %o0, %l3
81565mov %l4, %o1
81566casx [%l6], %l3, %o1
81567! move %o1(upper) -> %o1(upper)
81568! move %o1(lower) -> %o1(lower)
81569add %l4, 1, %l4
81570
81571P7854: !_PREFETCH [6] (Int)
81572sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
81573sub %i0, %i3, %i3
81574prefetch [%i3 + 0], 29
81575
81576P7855: !_PREFETCH [7] (Int)
81577prefetch [%i3 + 4], 20
81578
81579P7856: !_MEMBAR (FP)
81580
81581P7857: !_BSTC [7] (maybe <- 0x430000fc) (FP)
81582wr %g0, 0xe0, %asi
81583! preparing store val #0, next val will be in f32
81584fmovs %f16, %f20
81585fadds %f16, %f17, %f16
81586! preparing store val #1, next val will be in f33
81587fmovs %f16, %f21
81588fadds %f16, %f17, %f16
81589! preparing store val #2, next val will be in f35
81590fmovd %f20, %f32
81591fmovs %f16, %f21
81592fadds %f16, %f17, %f16
81593fmovd %f20, %f34
81594membar #Sync
81595stda %f32, [%i3 + 0 ] %asi
81596
81597P7858: !_MEMBAR (FP)
81598membar #StoreLoad
81599
81600P7859: !_CAS [5] (maybe <- 0x380015f) (Int) (CBR)
81601add %i1, 12, %l3
81602lduw [%l3], %o2
81603mov %o2, %o5
81604! move %o5(lower) -> %o2(upper)
81605sllx %o5, 32, %o2
81606mov %l4, %l7
81607cas [%l3], %o5, %l7
81608! move %l7(lower) -> %o2(lower)
81609srl %l7, 0, %o5
81610or %o5, %o2, %o2
81611add %l4, 1, %l4
81612
81613! cbranch
81614andcc %l0, 1, %g0
81615be,pt %xcc, TARGET7859
81616nop
81617RET7859:
81618
81619! lfsr step begin
81620srlx %l0, 1, %o5
81621xnor %o5, %l0, %o5
81622sllx %o5, 63, %o5
81623or %o5, %l0, %l0
81624srlx %l0, 1, %l0
81625
81626
81627P7860: !_CAS [9] (maybe <- 0x3800160) (Int)
81628lduw [%i2], %o3
81629mov %o3, %l3
81630! move %l3(lower) -> %o3(upper)
81631sllx %l3, 32, %o3
81632mov %l4, %o5
81633cas [%i2], %l3, %o5
81634! move %o5(lower) -> %o3(lower)
81635srl %o5, 0, %l3
81636or %l3, %o3, %o3
81637add %l4, 1, %l4
81638
81639P7861: !_SWAP [18] (maybe <- 0x3800161) (Int)
81640sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
81641sub %i0, %i2, %i2
81642mov %l4, %o4
81643swap [%i2 + 0], %o4
81644! move %o4(lower) -> %o4(upper)
81645sllx %o4, 32, %o4
81646add %l4, 1, %l4
81647
81648P7862: !_DWLD [0] (Int)
81649ldx [%i0 + 0], %l3
81650! move %l3(upper) -> %o4(lower)
81651srlx %l3, 32, %o5
81652or %o5, %o4, %o4
81653!---- flushing int results buffer----
81654mov %o0, %l5
81655mov %o1, %l5
81656mov %o2, %l5
81657mov %o3, %l5
81658mov %o4, %l5
81659! move %l3(lower) -> %o0(upper)
81660sllx %l3, 32, %o0
81661
81662P7863: !_ST [5] (maybe <- 0x3800162) (Int)
81663stw %l4, [%i1 + 12 ]
81664add %l4, 1, %l4
81665
81666P7864: !_DWST_BINIT [15] (maybe <- 0x3800163) (Int)
81667wr %g0, 0xe2, %asi
81668sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
81669sub %i0, %i3, %i3
81670sllx %l4, 32, %l3
81671add %l4, 1, %l4
81672or %l3, %l4, %l3
81673stxa %l3, [%i3 + 0] %asi
81674add %l4, 1, %l4
81675
81676P7865: !_MEMBAR (Int)
81677membar #StoreLoad
81678
81679P7866: !_DWLD [4] (Int)
81680ldx [%i1 + 0], %l3
81681! move %l3(upper) -> %o0(lower)
81682srlx %l3, 32, %o5
81683or %o5, %o0, %o0
81684! move %l3(lower) -> %o1(upper)
81685sllx %l3, 32, %o1
81686
81687P7867: !_MEMBAR (FP)
81688
81689P7868: !_BST [22] (maybe <- 0x430000ff) (FP)
81690wr %g0, 0xf0, %asi
81691sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
81692sub %i0, %i2, %i2
81693! preparing store val #0, next val will be in f32
81694fmovs %f16, %f20
81695fadds %f16, %f17, %f16
81696! preparing store val #1, next val will be in f33
81697fmovs %f16, %f21
81698fadds %f16, %f17, %f16
81699! preparing store val #2, next val will be in f35
81700fmovd %f20, %f32
81701fmovs %f16, %f21
81702fadds %f16, %f17, %f16
81703fmovd %f20, %f34
81704membar #Sync
81705stda %f32, [%i2 + 0 ] %asi
81706
81707P7869: !_MEMBAR (FP)
81708membar #StoreLoad
81709
81710P7870: !_DWST [11] (maybe <- 0x3800165) (Int)
81711sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
81712sub %i0, %i3, %i3
81713mov %l4, %l3
81714stx %l3, [%i3 + 8]
81715add %l4, 1, %l4
81716
81717P7871: !_CASX [14] (maybe <- 0x3800166) (Int)
81718sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
81719sub %i0, %i2, %i2
81720add %i2, 8, %l3
81721ldx [%l3], %l7
81722! move %l7(upper) -> %o1(lower)
81723srlx %l7, 32, %o5
81724or %o5, %o1, %o1
81725! move %l7(lower) -> %o2(upper)
81726sllx %l7, 32, %o2
81727mov %l7, %o5
81728mov %l4, %l7
81729casx [%l3], %o5, %l7
81730! move %l7(upper) -> %o2(lower)
81731srlx %l7, 32, %o5
81732or %o5, %o2, %o2
81733! move %l7(lower) -> %o3(upper)
81734sllx %l7, 32, %o3
81735add %l4, 1, %l4
81736
81737P7872: !_LD [21] (Int) (Branch target of P7246)
81738sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
81739sub %i0, %i3, %i3
81740lduw [%i3 + 0], %l3
81741! move %l3(lower) -> %o3(lower)
81742or %l3, %o3, %o3
81743ba P7873
81744nop
81745
81746TARGET7246:
81747ba RET7246
81748nop
81749
81750
81751P7873: !_DWST_BINIT [7] (maybe <- 0x3800167) (Int)
81752wr %g0, 0xe2, %asi
81753sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
81754sub %i0, %i2, %i2
81755sllx %l4, 32, %l6
81756add %l4, 1, %l4
81757or %l6, %l4, %l6
81758stxa %l6, [%i2 + 0] %asi
81759add %l4, 1, %l4
81760
81761P7874: !_MEMBAR (Int)
81762
81763P7875: !_BST [5] (maybe <- 0x43000102) (FP)
81764wr %g0, 0xf0, %asi
81765! preparing store val #0, next val will be in f32
81766fmovs %f16, %f20
81767fadds %f16, %f17, %f16
81768! preparing store val #1, next val will be in f33
81769fmovs %f16, %f21
81770fadds %f16, %f17, %f16
81771! preparing store val #2, next val will be in f35
81772fmovd %f20, %f32
81773fmovs %f16, %f21
81774fadds %f16, %f17, %f16
81775fmovd %f20, %f34
81776membar #Sync
81777stda %f32, [%i1 + 0 ] %asi
81778
81779P7876: !_MEMBAR (FP)
81780membar #StoreLoad
81781
81782P7877: !_ST_BINIT [7] (maybe <- 0x3800169) (Int)
81783wr %g0, 0xe2, %asi
81784stwa %l4, [%i2 + 4] %asi
81785add %l4, 1, %l4
81786
81787P7878: !_MEMBAR (Int)
81788membar #StoreLoad
81789
81790P7879: !_LDD [20] (Int)
81791sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
81792sub %i0, %i3, %i3
81793ldd [%i3 + 8], %l6
81794! move %l7(lower) -> %o4(upper)
81795sllx %l7, 32, %o4
81796
81797P7880: !_DWST_BINIT [19] (maybe <- 0x380016a) (Int) (CBR)
81798wr %g0, 0xe2, %asi
81799sllx %l4, 32, %l3
81800add %l4, 1, %l4
81801or %l3, %l4, %l3
81802stxa %l3, [%i3 + 0] %asi
81803add %l4, 1, %l4
81804
81805! cbranch
81806andcc %l0, 1, %g0
81807be,pn %xcc, TARGET7880
81808nop
81809RET7880:
81810
81811! lfsr step begin
81812srlx %l0, 1, %o5
81813xnor %o5, %l0, %o5
81814sllx %o5, 63, %o5
81815or %o5, %l0, %l0
81816srlx %l0, 1, %l0
81817
81818
81819P7881: !_MEMBAR (Int)
81820membar #StoreLoad
81821
81822P7882: !_DWLD [4] (Int) (CBR)
81823ldx [%i1 + 0], %l6
81824! move %l6(upper) -> %o4(lower)
81825srlx %l6, 32, %l3
81826or %l3, %o4, %o4
81827!---- flushing int results buffer----
81828mov %o0, %l5
81829mov %o1, %l5
81830mov %o2, %l5
81831mov %o3, %l5
81832mov %o4, %l5
81833! move %l6(lower) -> %o0(upper)
81834sllx %l6, 32, %o0
81835
81836! cbranch
81837andcc %l0, 1, %g0
81838be,pn %xcc, TARGET7882
81839nop
81840RET7882:
81841
81842! lfsr step begin
81843srlx %l0, 1, %l7
81844xnor %l7, %l0, %l7
81845sllx %l7, 63, %l7
81846or %l7, %l0, %l0
81847srlx %l0, 1, %l0
81848
81849
81850P7883: !_REPLACEMENT [9] (Int) (CBR)
81851sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
81852sub %i0, %i2, %i2
81853sethi %hi(0x20000), %o5
81854ld [%i2+0], %l6
81855st %l6, [%i2+0]
81856add %i2, %o5, %l3
81857ld [%l3+0], %l6
81858st %l6, [%l3+0]
81859add %l3, %o5, %l3
81860ld [%l3+0], %l6
81861st %l6, [%l3+0]
81862add %l3, %o5, %l3
81863ld [%l3+0], %l6
81864st %l6, [%l3+0]
81865add %l3, %o5, %l3
81866ld [%l3+0], %l6
81867st %l6, [%l3+0]
81868add %l3, %o5, %l3
81869ld [%l3+0], %l6
81870st %l6, [%l3+0]
81871add %l3, %o5, %l3
81872ld [%l3+0], %l6
81873st %l6, [%l3+0]
81874add %l3, %o5, %l3
81875ld [%l3+0], %l6
81876st %l6, [%l3+0]
81877
81878! cbranch
81879andcc %l0, 1, %g0
81880be,pt %xcc, TARGET7883
81881nop
81882RET7883:
81883
81884! lfsr step begin
81885srlx %l0, 1, %l7
81886xnor %l7, %l0, %l7
81887sllx %l7, 63, %l7
81888or %l7, %l0, %l0
81889srlx %l0, 1, %l0
81890
81891
81892P7884: !_LDD [6] (Int)
81893sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
81894sub %i0, %i3, %i3
81895ldd [%i3 + 0], %l6
81896! move %l6(lower) -> %o0(lower)
81897or %l6, %o0, %o0
81898! move %l7(lower) -> %o1(upper)
81899sllx %l7, 32, %o1
81900
81901P7885: !_PREFETCH [18] (Int)
81902sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
81903sub %i0, %i2, %i2
81904prefetch [%i2 + 0], 2
81905
81906P7886: !_SWAP [22] (maybe <- 0x380016c) (Int)
81907sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
81908sub %i0, %i3, %i3
81909mov %l4, %l7
81910swap [%i3 + 4], %l7
81911! move %l7(lower) -> %o1(lower)
81912srl %l7, 0, %l3
81913or %l3, %o1, %o1
81914add %l4, 1, %l4
81915
81916P7887: !_DWST [0] (maybe <- 0x380016d) (Int)
81917sllx %l4, 32, %o5
81918add %l4, 1, %l4
81919or %o5, %l4, %o5
81920stx %o5, [%i0 + 0]
81921add %l4, 1, %l4
81922
81923P7888: !_DWST [3] (maybe <- 0x43000105) (FP)
81924! preparing store val #0, next val will be in f20
81925fmovs %f16, %f20
81926fadds %f16, %f17, %f16
81927! preparing store val #1, next val will be in f21
81928fmovs %f16, %f21
81929fadds %f16, %f17, %f16
81930std %f20, [%i1 + 0]
81931
81932P7889: !_CASX [6] (maybe <- 0x380016f) (Int)
81933sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
81934sub %i0, %i2, %i2
81935ldx [%i2], %o2
81936! move %o2(upper) -> %o2(upper)
81937! move %o2(lower) -> %o2(lower)
81938mov %o2, %l6
81939sllx %l4, 32, %o3
81940add %l4, 1, %l4
81941or %l4, %o3, %o3
81942casx [%i2], %l6, %o3
81943! move %o3(upper) -> %o3(upper)
81944! move %o3(lower) -> %o3(lower)
81945add %l4, 1, %l4
81946
81947P7890: !_MEMBAR (FP)
81948
81949P7891: !_BST [4] (maybe <- 0x43000107) (FP)
81950wr %g0, 0xf0, %asi
81951! preparing store val #0, next val will be in f32
81952fmovs %f16, %f20
81953fadds %f16, %f17, %f16
81954! preparing store val #1, next val will be in f33
81955fmovs %f16, %f21
81956fadds %f16, %f17, %f16
81957! preparing store val #2, next val will be in f35
81958fmovd %f20, %f32
81959fmovs %f16, %f21
81960fadds %f16, %f17, %f16
81961fmovd %f20, %f34
81962membar #Sync
81963stda %f32, [%i1 + 0 ] %asi
81964
81965P7892: !_MEMBAR (FP) (CBR)
81966membar #StoreLoad
81967
81968! cbranch
81969andcc %l0, 1, %g0
81970be,pn %xcc, TARGET7892
81971nop
81972RET7892:
81973
81974! lfsr step begin
81975srlx %l0, 1, %l3
81976xnor %l3, %l0, %l3
81977sllx %l3, 63, %l3
81978or %l3, %l0, %l0
81979srlx %l0, 1, %l0
81980
81981
81982P7893: !_ST [4] (maybe <- 0x3800171) (Int) (LE) (Branch target of P7909)
81983wr %g0, 0x88, %asi
81984! Change single-word-level endianess (big endian <-> little endian)
81985sethi %hi(0xff00ff00), %l7
81986or %l7, %lo(0xff00ff00), %l7
81987and %l4, %l7, %o5
81988srl %o5, 8, %o5
81989sll %l4, 8, %l6
81990and %l6, %l7, %l6
81991or %l6, %o5, %l6
81992srl %l6, 16, %o5
81993sll %l6, 16, %l6
81994srl %l6, 0, %l6
81995or %l6, %o5, %l6
81996stwa %l6, [%i1 + 4] %asi
81997add %l4, 1, %l4
81998ba P7894
81999nop
82000
82001TARGET7909:
82002ba RET7909
82003nop
82004
82005
82006P7894: !_ST [15] (maybe <- 0x3800172) (Int)
82007sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
82008sub %i0, %i3, %i3
82009stw %l4, [%i3 + 0 ]
82010add %l4, 1, %l4
82011
82012P7895: !_MEMBAR (FP)
82013membar #StoreLoad
82014
82015P7896: !_BLD [4] (FP)
82016wr %g0, 0xf0, %asi
82017ldda [%i1 + 0] %asi, %f32
82018membar #Sync
82019! 3 addresses covered
82020fmovd %f32, %f18
82021fmovs %f18, %f9
82022fmovs %f19, %f10
82023fmovd %f34, %f18
82024fmovs %f19, %f11
82025
82026P7897: !_MEMBAR (FP)
82027
82028P7898: !_DWST [19] (maybe <- 0x3800173) (Int)
82029sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
82030sub %i0, %i2, %i2
82031sllx %l4, 32, %o5
82032add %l4, 1, %l4
82033or %o5, %l4, %o5
82034stx %o5, [%i2 + 0]
82035add %l4, 1, %l4
82036
82037P7899: !_REPLACEMENT [16] (Int) (Branch target of P7673)
82038sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i3
82039sub %i0, %i3, %i3
82040sethi %hi(0x20000), %l7
82041ld [%i3+4], %l3
82042st %l3, [%i3+4]
82043add %i3, %l7, %o5
82044ld [%o5+4], %l3
82045st %l3, [%o5+4]
82046add %o5, %l7, %o5
82047ld [%o5+4], %l3
82048st %l3, [%o5+4]
82049add %o5, %l7, %o5
82050ld [%o5+4], %l3
82051st %l3, [%o5+4]
82052add %o5, %l7, %o5
82053ld [%o5+4], %l3
82054st %l3, [%o5+4]
82055add %o5, %l7, %o5
82056ld [%o5+4], %l3
82057st %l3, [%o5+4]
82058add %o5, %l7, %o5
82059ld [%o5+4], %l3
82060st %l3, [%o5+4]
82061add %o5, %l7, %o5
82062ld [%o5+4], %l3
82063st %l3, [%o5+4]
82064ba P7900
82065nop
82066
82067TARGET7673:
82068ba RET7673
82069nop
82070
82071
82072P7900: !_ST_BINIT [19] (maybe <- 0x3800175) (Int)
82073wr %g0, 0xe2, %asi
82074stwa %l4, [%i2 + 4] %asi
82075add %l4, 1, %l4
82076
82077P7901: !_MEMBAR (Int)
82078membar #StoreLoad
82079
82080P7902: !_LD [18] (Int)
82081lduw [%i2 + 0], %o4
82082! move %o4(lower) -> %o4(upper)
82083sllx %o4, 32, %o4
82084
82085P7903: !_CASX [8] (maybe <- 0x3800176) (Int)
82086sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
82087sub %i0, %i2, %i2
82088add %i2, 8, %o5
82089ldx [%o5], %l6
82090! move %l6(upper) -> %o4(lower)
82091srlx %l6, 32, %l7
82092or %l7, %o4, %o4
82093!---- flushing int results buffer----
82094mov %o0, %l5
82095mov %o1, %l5
82096mov %o2, %l5
82097mov %o3, %l5
82098mov %o4, %l5
82099! move %l6(lower) -> %o0(upper)
82100sllx %l6, 32, %o0
82101mov %l6, %l7
82102mov %l4, %l6
82103casx [%o5], %l7, %l6
82104! move %l6(upper) -> %o0(lower)
82105srlx %l6, 32, %l7
82106or %l7, %o0, %o0
82107! move %l6(lower) -> %o1(upper)
82108sllx %l6, 32, %o1
82109add %l4, 1, %l4
82110
82111P7904: !_CASX [19] (maybe <- 0x3800177) (Int)
82112sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
82113sub %i0, %i3, %i3
82114ldx [%i3], %l6
82115! move %l6(upper) -> %o1(lower)
82116srlx %l6, 32, %l7
82117or %l7, %o1, %o1
82118! move %l6(lower) -> %o2(upper)
82119sllx %l6, 32, %o2
82120mov %l6, %l7
82121sllx %l4, 32, %l6
82122add %l4, 1, %l4
82123or %l4, %l6, %l6
82124casx [%i3], %l7, %l6
82125! move %l6(upper) -> %o2(lower)
82126srlx %l6, 32, %l7
82127or %l7, %o2, %o2
82128! move %l6(lower) -> %o3(upper)
82129sllx %l6, 32, %o3
82130add %l4, 1, %l4
82131
82132P7905: !_DWLD [22] (Int)
82133sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
82134sub %i0, %i2, %i2
82135ldx [%i2 + 0], %o5
82136! move %o5(upper) -> %o3(lower)
82137srlx %o5, 32, %l7
82138or %l7, %o3, %o3
82139! move %o5(lower) -> %o4(upper)
82140sllx %o5, 32, %o4
82141
82142P7906: !_LDD [6] (Int)
82143sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
82144sub %i0, %i3, %i3
82145ldd [%i3 + 0], %l6
82146! move %l6(lower) -> %o4(lower)
82147or %l6, %o4, %o4
82148!---- flushing int results buffer----
82149mov %o0, %l5
82150mov %o1, %l5
82151mov %o2, %l5
82152mov %o3, %l5
82153mov %o4, %l5
82154! move %l7(lower) -> %o0(upper)
82155sllx %l7, 32, %o0
82156
82157P7907: !_LDD [15] (Int) (Branch target of P7780)
82158sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
82159sub %i0, %i2, %i2
82160ldd [%i2 + 0], %l6
82161! move %l6(lower) -> %o0(lower)
82162or %l6, %o0, %o0
82163! move %l7(lower) -> %o1(upper)
82164sllx %l7, 32, %o1
82165ba P7908
82166nop
82167
82168TARGET7780:
82169ba RET7780
82170nop
82171
82172
82173P7908: !_REPLACEMENT [16] (Int)
82174sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3
82175add %i0, %i3, %i3
82176sethi %hi(0x20000), %l3
82177ld [%i3+4], %l7
82178st %l7, [%i3+4]
82179add %i3, %l3, %l6
82180ld [%l6+4], %l7
82181st %l7, [%l6+4]
82182add %l6, %l3, %l6
82183ld [%l6+4], %l7
82184st %l7, [%l6+4]
82185add %l6, %l3, %l6
82186ld [%l6+4], %l7
82187st %l7, [%l6+4]
82188add %l6, %l3, %l6
82189ld [%l6+4], %l7
82190st %l7, [%l6+4]
82191add %l6, %l3, %l6
82192ld [%l6+4], %l7
82193st %l7, [%l6+4]
82194add %l6, %l3, %l6
82195ld [%l6+4], %l7
82196st %l7, [%l6+4]
82197add %l6, %l3, %l6
82198ld [%l6+4], %l7
82199st %l7, [%l6+4]
82200
82201P7909: !_CASX [2] (maybe <- 0x3800179) (Int) (CBR)
82202add %i0, 8, %l3
82203ldx [%l3], %l7
82204! move %l7(upper) -> %o1(lower)
82205srlx %l7, 32, %o5
82206or %o5, %o1, %o1
82207! move %l7(lower) -> %o2(upper)
82208sllx %l7, 32, %o2
82209mov %l7, %o5
82210mov %l4, %l7
82211casx [%l3], %o5, %l7
82212! move %l7(upper) -> %o2(lower)
82213srlx %l7, 32, %o5
82214or %o5, %o2, %o2
82215! move %l7(lower) -> %o3(upper)
82216sllx %l7, 32, %o3
82217add %l4, 1, %l4
82218
82219! cbranch
82220andcc %l0, 1, %g0
82221be,pn %xcc, TARGET7909
82222nop
82223RET7909:
82224
82225! lfsr step begin
82226srlx %l0, 1, %o5
82227xnor %o5, %l0, %o5
82228sllx %o5, 63, %o5
82229or %o5, %l0, %l0
82230srlx %l0, 1, %l0
82231
82232
82233P7910: !_ST [2] (maybe <- 0x380017a) (Int)
82234stw %l4, [%i0 + 12 ]
82235add %l4, 1, %l4
82236
82237P7911: !_MEMBAR (FP)
82238
82239P7912: !_BST [8] (maybe <- 0x4300010a) (FP)
82240wr %g0, 0xf0, %asi
82241sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
82242sub %i0, %i2, %i2
82243! preparing store val #0, next val will be in f32
82244fmovs %f16, %f20
82245fadds %f16, %f17, %f16
82246! preparing store val #1, next val will be in f33
82247fmovs %f16, %f21
82248fadds %f16, %f17, %f16
82249! preparing store val #2, next val will be in f35
82250fmovd %f20, %f32
82251fmovs %f16, %f21
82252fadds %f16, %f17, %f16
82253fmovd %f20, %f34
82254membar #Sync
82255stda %f32, [%i2 + 0 ] %asi
82256
82257P7913: !_MEMBAR (FP)
82258
82259P7914: !_BST [12] (maybe <- 0x4300010d) (FP)
82260wr %g0, 0xf0, %asi
82261sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
82262sub %i0, %i3, %i3
82263! preparing store val #0, next val will be in f32
82264fmovs %f16, %f20
82265fadds %f16, %f17, %f16
82266! preparing store val #1, next val will be in f33
82267fmovs %f16, %f21
82268fadds %f16, %f17, %f16
82269! preparing store val #2, next val will be in f35
82270fmovd %f20, %f32
82271fmovs %f16, %f21
82272fadds %f16, %f17, %f16
82273fmovd %f20, %f34
82274membar #Sync
82275stda %f32, [%i3 + 0 ] %asi
82276
82277P7915: !_MEMBAR (FP)
82278membar #StoreLoad
82279
82280P7916: !_ST [7] (maybe <- 0x380017b) (Int)
82281stw %l4, [%i2 + 4 ]
82282add %l4, 1, %l4
82283
82284P7917: !_DWST_BINIT [17] (maybe <- 0x380017c) (Int)
82285wr %g0, 0xe2, %asi
82286sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
82287sub %i0, %i2, %i2
82288mov %l4, %l6
82289stxa %l6, [%i2 + 8] %asi
82290add %l4, 1, %l4
82291
82292P7918: !_MEMBAR (Int) (CBR) (Branch target of P7174)
82293membar #StoreLoad
82294
82295! cbranch
82296andcc %l0, 1, %g0
82297be,pn %xcc, TARGET7918
82298nop
82299RET7918:
82300
82301! lfsr step begin
82302srlx %l0, 1, %l3
82303xnor %l3, %l0, %l3
82304sllx %l3, 63, %l3
82305or %l3, %l0, %l0
82306srlx %l0, 1, %l0
82307
82308ba P7919
82309nop
82310
82311TARGET7174:
82312ba RET7174
82313nop
82314
82315
82316P7919: !_DWLD [16] (FP)
82317ldd [%i2 + 0], %f12
82318! 2 addresses covered
82319
82320P7920: !_SWAP [1] (maybe <- 0x380017d) (Int)
82321mov %l4, %o5
82322swap [%i0 + 4], %o5
82323! move %o5(lower) -> %o3(lower)
82324srl %o5, 0, %l6
82325or %l6, %o3, %o3
82326add %l4, 1, %l4
82327
82328P7921: !_MEMBAR (FP)
82329membar #StoreLoad
82330
82331P7922: !_BLD [7] (FP)
82332wr %g0, 0xf0, %asi
82333sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
82334sub %i0, %i3, %i3
82335ldda [%i3 + 0] %asi, %f32
82336membar #Sync
82337! 3 addresses covered
82338fmovd %f32, %f14
82339!---- flushing fp results buffer to %f30 ----
82340fmovd %f0, %f30
82341fmovd %f2, %f30
82342fmovd %f4, %f30
82343fmovd %f6, %f30
82344fmovd %f8, %f30
82345fmovd %f10, %f30
82346fmovd %f12, %f30
82347fmovd %f14, %f30
82348!--
82349fmovd %f34, %f18
82350fmovs %f19, %f0
82351
82352P7923: !_MEMBAR (FP)
82353
82354P7924: !_LD [17] (Int) (Branch target of P7996)
82355lduw [%i2 + 12], %o4
82356! move %o4(lower) -> %o4(upper)
82357sllx %o4, 32, %o4
82358ba P7925
82359nop
82360
82361TARGET7996:
82362ba RET7996
82363nop
82364
82365
82366P7925: !_DWLD [16] (Int)
82367ldx [%i2 + 0], %o5
82368! move %o5(upper) -> %o4(lower)
82369srlx %o5, 32, %l7
82370or %l7, %o4, %o4
82371!---- flushing int results buffer----
82372mov %o0, %l5
82373mov %o1, %l5
82374mov %o2, %l5
82375mov %o3, %l5
82376mov %o4, %l5
82377! move %o5(lower) -> %o0(upper)
82378sllx %o5, 32, %o0
82379
82380P7926: !_CASX [21] (maybe <- 0x380017e) (Int)
82381sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
82382sub %i0, %i2, %i2
82383ldx [%i2], %o5
82384! move %o5(upper) -> %o0(lower)
82385srlx %o5, 32, %l3
82386or %l3, %o0, %o0
82387! move %o5(lower) -> %o1(upper)
82388sllx %o5, 32, %o1
82389mov %o5, %l3
82390sllx %l4, 32, %o5
82391add %l4, 1, %l4
82392or %l4, %o5, %o5
82393casx [%i2], %l3, %o5
82394! move %o5(upper) -> %o1(lower)
82395srlx %o5, 32, %l3
82396or %l3, %o1, %o1
82397! move %o5(lower) -> %o2(upper)
82398sllx %o5, 32, %o2
82399add %l4, 1, %l4
82400
82401P7927: !_LDD [0] (Int)
82402ldd [%i0 + 0], %l6
82403! move %l6(lower) -> %o2(lower)
82404or %l6, %o2, %o2
82405! move %l7(lower) -> %o3(upper)
82406sllx %l7, 32, %o3
82407
82408P7928: !_DWST [16] (maybe <- 0x43000110) (FP)
82409sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
82410sub %i0, %i3, %i3
82411! preparing store val #0, next val will be in f20
82412fmovs %f16, %f20
82413fadds %f16, %f17, %f16
82414! preparing store val #1, next val will be in f21
82415fmovs %f16, %f21
82416fadds %f16, %f17, %f16
82417std %f20, [%i3 + 0]
82418
82419P7929: !_LDD [20] (Int) (Branch target of P7528)
82420sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
82421sub %i0, %i2, %i2
82422ldd [%i2 + 8], %l6
82423! move %l7(lower) -> %o3(lower)
82424or %l7, %o3, %o3
82425ba P7930
82426nop
82427
82428TARGET7528:
82429ba RET7528
82430nop
82431
82432
82433P7930: !_ST [20] (maybe <- 0x3800180) (Int)
82434stw %l4, [%i2 + 12 ]
82435add %l4, 1, %l4
82436
82437P7931: !_DWST_BINIT [19] (maybe <- 0x3800181) (Int)
82438wr %g0, 0xe2, %asi
82439sllx %l4, 32, %o5
82440add %l4, 1, %l4
82441or %o5, %l4, %o5
82442stxa %o5, [%i2 + 0] %asi
82443add %l4, 1, %l4
82444
82445P7932: !_MEMBAR (Int)
82446membar #StoreLoad
82447
82448P7933: !_DWST_BINIT [14] (maybe <- 0x3800183) (Int)
82449wr %g0, 0xe2, %asi
82450sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
82451sub %i0, %i3, %i3
82452mov %l4, %l7
82453stxa %l7, [%i3 + 8] %asi
82454add %l4, 1, %l4
82455
82456P7934: !_MEMBAR (Int)
82457membar #StoreLoad
82458
82459P7935: !_REPLACEMENT [23] (Int)
82460sethi %hi(REGION0_ALIAS0_O-REPLACEMENT0_ALIAS3_O), %i2
82461sub %i0, %i2, %i2
82462sethi %hi(0x20000), %l6
82463ld [%i2+12], %o5
82464st %o5, [%i2+12]
82465add %i2, %l6, %l7
82466ld [%l7+12], %o5
82467st %o5, [%l7+12]
82468add %l7, %l6, %l7
82469ld [%l7+12], %o5
82470st %o5, [%l7+12]
82471add %l7, %l6, %l7
82472ld [%l7+12], %o5
82473st %o5, [%l7+12]
82474add %l7, %l6, %l7
82475ld [%l7+12], %o5
82476st %o5, [%l7+12]
82477add %l7, %l6, %l7
82478ld [%l7+12], %o5
82479st %o5, [%l7+12]
82480add %l7, %l6, %l7
82481ld [%l7+12], %o5
82482st %o5, [%l7+12]
82483add %l7, %l6, %l7
82484ld [%l7+12], %o5
82485st %o5, [%l7+12]
82486
82487P7936: !_SWAP [0] (maybe <- 0x3800184) (Int)
82488mov %l4, %o4
82489swap [%i0 + 0], %o4
82490! move %o4(lower) -> %o4(upper)
82491sllx %o4, 32, %o4
82492add %l4, 1, %l4
82493
82494P7937: !_CASX [11] (maybe <- 0x3800185) (Int) (Branch target of P7300)
82495sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
82496sub %i0, %i3, %i3
82497add %i3, 8, %l3
82498ldx [%l3], %l7
82499! move %l7(upper) -> %o4(lower)
82500srlx %l7, 32, %o5
82501or %o5, %o4, %o4
82502!---- flushing int results buffer----
82503mov %o0, %l5
82504mov %o1, %l5
82505mov %o2, %l5
82506mov %o3, %l5
82507mov %o4, %l5
82508! move %l7(lower) -> %o0(upper)
82509sllx %l7, 32, %o0
82510mov %l7, %o5
82511mov %l4, %l7
82512casx [%l3], %o5, %l7
82513! move %l7(upper) -> %o0(lower)
82514srlx %l7, 32, %o5
82515or %o5, %o0, %o0
82516! move %l7(lower) -> %o1(upper)
82517sllx %l7, 32, %o1
82518add %l4, 1, %l4
82519ba P7938
82520nop
82521
82522TARGET7300:
82523ba RET7300
82524nop
82525
82526
82527P7938: !_ST_BINIT [8] (maybe <- 0x3800186) (Int)
82528wr %g0, 0xe2, %asi
82529sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
82530sub %i0, %i2, %i2
82531stwa %l4, [%i2 + 12] %asi
82532add %l4, 1, %l4
82533
82534P7939: !_MEMBAR (Int)
82535
82536P7940: !_BST [5] (maybe <- 0x43000112) (FP)
82537wr %g0, 0xf0, %asi
82538! preparing store val #0, next val will be in f32
82539fmovs %f16, %f20
82540fadds %f16, %f17, %f16
82541! preparing store val #1, next val will be in f33
82542fmovs %f16, %f21
82543fadds %f16, %f17, %f16
82544! preparing store val #2, next val will be in f35
82545fmovd %f20, %f32
82546fmovs %f16, %f21
82547fadds %f16, %f17, %f16
82548fmovd %f20, %f34
82549membar #Sync
82550stda %f32, [%i1 + 0 ] %asi
82551
82552P7941: !_MEMBAR (FP)
82553membar #StoreLoad
82554
82555P7942: !_DWLD [17] (Int)
82556sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
82557sub %i0, %i3, %i3
82558ldx [%i3 + 8], %l7
82559! move %l7(lower) -> %o1(lower)
82560srl %l7, 0, %l6
82561or %l6, %o1, %o1
82562
82563P7943: !_CAS [3] (maybe <- 0x3800187) (Int)
82564lduw [%i1], %o2
82565mov %o2, %o5
82566! move %o5(lower) -> %o2(upper)
82567sllx %o5, 32, %o2
82568mov %l4, %l7
82569cas [%i1], %o5, %l7
82570! move %l7(lower) -> %o2(lower)
82571srl %l7, 0, %o5
82572or %o5, %o2, %o2
82573add %l4, 1, %l4
82574
82575P7944: !_SWAP [4] (maybe <- 0x3800188) (Int)
82576mov %l4, %o3
82577swap [%i1 + 4], %o3
82578! move %o3(lower) -> %o3(upper)
82579sllx %o3, 32, %o3
82580add %l4, 1, %l4
82581
82582P7945: !_DWST_BINIT [14] (maybe <- 0x3800189) (Int)
82583wr %g0, 0xe2, %asi
82584sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
82585sub %i0, %i2, %i2
82586mov %l4, %l7
82587stxa %l7, [%i2 + 8] %asi
82588add %l4, 1, %l4
82589
82590P7946: !_MEMBAR (Int)
82591membar #StoreLoad
82592
82593P7947: !_BLD [18] (FP)
82594wr %g0, 0xf0, %asi
82595sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i3
82596sub %i0, %i3, %i3
82597ldda [%i3 + 0] %asi, %f32
82598membar #Sync
82599! 3 addresses covered
82600fmovd %f32, %f18
82601fmovs %f18, %f1
82602fmovs %f19, %f2
82603fmovd %f34, %f18
82604fmovs %f19, %f3
82605
82606P7948: !_MEMBAR (FP)
82607
82608P7949: !_DWST_BINIT [18] (maybe <- 0x380018a) (Int)
82609wr %g0, 0xe2, %asi
82610sllx %l4, 32, %l6
82611add %l4, 1, %l4
82612or %l6, %l4, %l6
82613stxa %l6, [%i3 + 0] %asi
82614add %l4, 1, %l4
82615
82616P7950: !_MEMBAR (Int)
82617membar #StoreLoad
82618
82619P7951: !_SWAP [18] (maybe <- 0x380018c) (Int)
82620mov %l4, %l7
82621swap [%i3 + 0], %l7
82622! move %l7(lower) -> %o3(lower)
82623srl %l7, 0, %l3
82624or %l3, %o3, %o3
82625add %l4, 1, %l4
82626
82627P7952: !_LDD [18] (Int)
82628ldd [%i3 + 0], %l6
82629! move %l6(lower) -> %o4(upper)
82630sllx %l6, 32, %o4
82631! move %l7(lower) -> %o4(lower)
82632or %l7, %o4, %o4
82633!---- flushing int results buffer----
82634mov %o0, %l5
82635mov %o1, %l5
82636mov %o2, %l5
82637mov %o3, %l5
82638mov %o4, %l5
82639
82640P7953: !_MEMBAR (FP)
82641
82642P7954: !_BSTC [21] (maybe <- 0x43000115) (FP)
82643wr %g0, 0xe0, %asi
82644sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
82645sub %i0, %i2, %i2
82646! preparing store val #0, next val will be in f32
82647fmovs %f16, %f20
82648fadds %f16, %f17, %f16
82649! preparing store val #1, next val will be in f33
82650fmovs %f16, %f21
82651fadds %f16, %f17, %f16
82652! preparing store val #2, next val will be in f35
82653fmovd %f20, %f32
82654fmovs %f16, %f21
82655fadds %f16, %f17, %f16
82656fmovd %f20, %f34
82657membar #Sync
82658stda %f32, [%i2 + 0 ] %asi
82659
82660P7955: !_MEMBAR (FP)
82661membar #StoreLoad
82662
82663P7956: !_ST [4] (maybe <- 0x380018d) (Int) (CBR)
82664stw %l4, [%i1 + 4 ]
82665add %l4, 1, %l4
82666
82667! cbranch
82668andcc %l0, 1, %g0
82669be,pt %xcc, TARGET7956
82670nop
82671RET7956:
82672
82673! lfsr step begin
82674srlx %l0, 1, %l7
82675xnor %l7, %l0, %l7
82676sllx %l7, 63, %l7
82677or %l7, %l0, %l0
82678srlx %l0, 1, %l0
82679
82680
82681P7957: !_LD [15] (Int)
82682sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
82683sub %i0, %i3, %i3
82684lduw [%i3 + 0], %o0
82685! move %o0(lower) -> %o0(upper)
82686sllx %o0, 32, %o0
82687
82688P7958: !_MEMBAR (FP)
82689membar #StoreLoad
82690
82691P7959: !_BLD [20] (FP)
82692wr %g0, 0xf0, %asi
82693sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
82694sub %i0, %i2, %i2
82695ldda [%i2 + 0] %asi, %f32
82696membar #Sync
82697! 3 addresses covered
82698fmovd %f32, %f4
82699fmovd %f34, %f18
82700fmovs %f19, %f6
82701
82702P7960: !_MEMBAR (FP)
82703
82704P7961: !_BSTC [7] (maybe <- 0x43000118) (FP)
82705wr %g0, 0xe0, %asi
82706sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i3
82707sub %i0, %i3, %i3
82708! preparing store val #0, next val will be in f32
82709fmovs %f16, %f20
82710fadds %f16, %f17, %f16
82711! preparing store val #1, next val will be in f33
82712fmovs %f16, %f21
82713fadds %f16, %f17, %f16
82714! preparing store val #2, next val will be in f35
82715fmovd %f20, %f32
82716fmovs %f16, %f21
82717fadds %f16, %f17, %f16
82718fmovd %f20, %f34
82719membar #Sync
82720stda %f32, [%i3 + 0 ] %asi
82721
82722P7962: !_MEMBAR (FP) (CBR)
82723
82724! cbranch
82725andcc %l0, 1, %g0
82726be,pt %xcc, TARGET7962
82727nop
82728RET7962:
82729
82730! lfsr step begin
82731srlx %l0, 1, %l3
82732xnor %l3, %l0, %l3
82733sllx %l3, 63, %l3
82734or %l3, %l0, %l0
82735srlx %l0, 1, %l0
82736
82737
82738P7963: !_BSTC [13] (maybe <- 0x4300011b) (FP)
82739wr %g0, 0xe0, %asi
82740sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
82741sub %i0, %i2, %i2
82742! preparing store val #0, next val will be in f32
82743fmovs %f16, %f20
82744fadds %f16, %f17, %f16
82745! preparing store val #1, next val will be in f33
82746fmovs %f16, %f21
82747fadds %f16, %f17, %f16
82748! preparing store val #2, next val will be in f35
82749fmovd %f20, %f32
82750fmovs %f16, %f21
82751fadds %f16, %f17, %f16
82752fmovd %f20, %f34
82753membar #Sync
82754stda %f32, [%i2 + 0 ] %asi
82755
82756P7964: !_MEMBAR (FP)
82757membar #StoreLoad
82758
82759P7965: !_SWAP [22] (maybe <- 0x380018e) (Int)
82760sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
82761sub %i0, %i3, %i3
82762mov %l4, %l7
82763swap [%i3 + 4], %l7
82764! move %l7(lower) -> %o0(lower)
82765srl %l7, 0, %l3
82766or %l3, %o0, %o0
82767add %l4, 1, %l4
82768
82769P7966: !_SWAP [18] (maybe <- 0x380018f) (Int)
82770sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS1_O), %i2
82771sub %i0, %i2, %i2
82772mov %l4, %o1
82773swap [%i2 + 0], %o1
82774! move %o1(lower) -> %o1(upper)
82775sllx %o1, 32, %o1
82776add %l4, 1, %l4
82777
82778P7967: !_MEMBAR (FP) (Branch target of P7084)
82779ba P7968
82780nop
82781
82782TARGET7084:
82783ba RET7084
82784nop
82785
82786
82787P7968: !_BSTC [21] (maybe <- 0x4300011e) (FP)
82788wr %g0, 0xe0, %asi
82789! preparing store val #0, next val will be in f32
82790fmovs %f16, %f20
82791fadds %f16, %f17, %f16
82792! preparing store val #1, next val will be in f33
82793fmovs %f16, %f21
82794fadds %f16, %f17, %f16
82795! preparing store val #2, next val will be in f35
82796fmovd %f20, %f32
82797fmovs %f16, %f21
82798fadds %f16, %f17, %f16
82799fmovd %f20, %f34
82800membar #Sync
82801stda %f32, [%i3 + 0 ] %asi
82802
82803P7969: !_MEMBAR (FP)
82804membar #StoreLoad
82805
82806P7970: !_DWST [17] (maybe <- 0x3800190) (Int)
82807sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
82808sub %i0, %i3, %i3
82809mov %l4, %l6
82810stx %l6, [%i3 + 8]
82811add %l4, 1, %l4
82812
82813P7971: !_LD [11] (FP)
82814sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i2
82815sub %i0, %i2, %i2
82816ld [%i2 + 12], %f7
82817! 1 addresses covered
82818
82819P7972: !_DWST_BINIT [0] (maybe <- 0x3800191) (Int) (LE)
82820wr %g0, 0xea, %asi
82821sllx %l4, 32, %l3
82822add %l4, 1, %l4
82823or %l3, %l4, %l6
82824! Change double-word-level endianess (big endian <-> little endian)
82825sethi %hi(0xff00ff00), %l7
82826or %l7, %lo(0xff00ff00), %l7
82827sllx %l7, 32, %l3
82828or %l7, %l3, %l7
82829and %l6, %l7, %l3
82830srlx %l3, 8, %l3
82831sllx %l6, 8, %l6
82832and %l6, %l7, %l6
82833or %l6, %l3, %l6
82834sethi %hi(0xffff0000), %l7
82835srlx %l6, 16, %l3
82836andn %l3, %l7, %l3
82837andn %l6, %l7, %l6
82838sllx %l6, 16, %l6
82839or %l6, %l3, %l6
82840srlx %l6, 32, %l3
82841sllx %l6, 32, %l6
82842or %l6, %l3, %l3
82843stxa %l3, [%i0 + 0 ] %asi
82844add %l4, 1, %l4
82845
82846P7973: !_MEMBAR (Int) (LE)
82847membar #StoreLoad
82848
82849P7974: !_DWST [4] (maybe <- 0x3800193) (Int) (LE)
82850wr %g0, 0x88, %asi
82851sllx %l4, 32, %o5
82852add %l4, 1, %l4
82853or %o5, %l4, %l3
82854! Change double-word-level endianess (big endian <-> little endian)
82855sethi %hi(0xff00ff00), %l6
82856or %l6, %lo(0xff00ff00), %l6
82857sllx %l6, 32, %o5
82858or %l6, %o5, %l6
82859and %l3, %l6, %o5
82860srlx %o5, 8, %o5
82861sllx %l3, 8, %l3
82862and %l3, %l6, %l3
82863or %l3, %o5, %l3
82864sethi %hi(0xffff0000), %l6
82865srlx %l3, 16, %o5
82866andn %o5, %l6, %o5
82867andn %l3, %l6, %l3
82868sllx %l3, 16, %l3
82869or %l3, %o5, %l3
82870srlx %l3, 32, %o5
82871sllx %l3, 32, %l3
82872or %l3, %o5, %o5
82873stxa %o5, [%i1 + 0 ] %asi
82874add %l4, 1, %l4
82875
82876P7975: !_DWST [18] (maybe <- 0x3800195) (Int)
82877sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
82878sub %i0, %i3, %i3
82879sllx %l4, 32, %o5
82880add %l4, 1, %l4
82881or %o5, %l4, %o5
82882stx %o5, [%i3 + 0]
82883add %l4, 1, %l4
82884
82885P7976: !_DWLD [0] (Int)
82886ldx [%i0 + 0], %o5
82887! move %o5(upper) -> %o1(lower)
82888srlx %o5, 32, %l7
82889or %l7, %o1, %o1
82890! move %o5(lower) -> %o2(upper)
82891sllx %o5, 32, %o2
82892
82893P7977: !_MEMBAR (FP)
82894membar #StoreLoad
82895
82896P7978: !_BLD [8] (FP)
82897wr %g0, 0xf0, %asi
82898sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
82899sub %i0, %i2, %i2
82900ldda [%i2 + 0] %asi, %f32
82901membar #Sync
82902! 3 addresses covered
82903fmovd %f32, %f8
82904fmovd %f34, %f18
82905fmovs %f19, %f10
82906
82907P7979: !_MEMBAR (FP)
82908
82909P7980: !_BST [16] (maybe <- 0x43000121) (FP)
82910wr %g0, 0xf0, %asi
82911sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
82912sub %i0, %i3, %i3
82913! preparing store val #0, next val will be in f32
82914fmovs %f16, %f20
82915fadds %f16, %f17, %f16
82916! preparing store val #1, next val will be in f33
82917fmovs %f16, %f21
82918fadds %f16, %f17, %f16
82919! preparing store val #2, next val will be in f35
82920fmovd %f20, %f32
82921fmovs %f16, %f21
82922fadds %f16, %f17, %f16
82923fmovd %f20, %f34
82924membar #Sync
82925stda %f32, [%i3 + 0 ] %asi
82926
82927P7981: !_MEMBAR (FP)
82928membar #StoreLoad
82929
82930P7982: !_DWST_BINIT [17] (maybe <- 0x3800197) (Int)
82931wr %g0, 0xe2, %asi
82932mov %l4, %o5
82933stxa %o5, [%i3 + 8] %asi
82934add %l4, 1, %l4
82935
82936P7983: !_MEMBAR (Int)
82937membar #StoreLoad
82938
82939P7984: !_LD [6] (Int)
82940lduw [%i2 + 0], %o5
82941! move %o5(lower) -> %o2(lower)
82942or %o5, %o2, %o2
82943
82944P7985: !_MEMBAR (FP) (CBR)
82945
82946! cbranch
82947andcc %l0, 1, %g0
82948be,pt %xcc, TARGET7985
82949nop
82950RET7985:
82951
82952! lfsr step begin
82953srlx %l0, 1, %l3
82954xnor %l3, %l0, %l3
82955sllx %l3, 63, %l3
82956or %l3, %l0, %l0
82957srlx %l0, 1, %l0
82958
82959
82960P7986: !_BSTC [8] (maybe <- 0x43000124) (FP)
82961wr %g0, 0xe0, %asi
82962! preparing store val #0, next val will be in f32
82963fmovs %f16, %f20
82964fadds %f16, %f17, %f16
82965! preparing store val #1, next val will be in f33
82966fmovs %f16, %f21
82967fadds %f16, %f17, %f16
82968! preparing store val #2, next val will be in f35
82969fmovd %f20, %f32
82970fmovs %f16, %f21
82971fadds %f16, %f17, %f16
82972fmovd %f20, %f34
82973membar #Sync
82974stda %f32, [%i2 + 0 ] %asi
82975
82976P7987: !_MEMBAR (FP)
82977membar #StoreLoad
82978
82979P7988: !_PREFETCH [14] (Int)
82980sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i2
82981sub %i0, %i2, %i2
82982prefetch [%i2 + 12], 23
82983
82984P7989: !_ST_BINIT [20] (maybe <- 0x3800198) (Int) (CBR)
82985wr %g0, 0xe2, %asi
82986sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i3
82987sub %i0, %i3, %i3
82988stwa %l4, [%i3 + 12] %asi
82989add %l4, 1, %l4
82990
82991! cbranch
82992andcc %l0, 1, %g0
82993be,pn %xcc, TARGET7989
82994nop
82995RET7989:
82996
82997! lfsr step begin
82998srlx %l0, 1, %o5
82999xnor %o5, %l0, %o5
83000sllx %o5, 63, %o5
83001or %o5, %l0, %l0
83002srlx %l0, 1, %l0
83003
83004
83005P7990: !_MEMBAR (Int)
83006
83007P7991: !_BST [18] (maybe <- 0x43000127) (FP)
83008wr %g0, 0xf0, %asi
83009! preparing store val #0, next val will be in f32
83010fmovs %f16, %f20
83011fadds %f16, %f17, %f16
83012! preparing store val #1, next val will be in f33
83013fmovs %f16, %f21
83014fadds %f16, %f17, %f16
83015! preparing store val #2, next val will be in f35
83016fmovd %f20, %f32
83017fmovs %f16, %f21
83018fadds %f16, %f17, %f16
83019fmovd %f20, %f34
83020membar #Sync
83021stda %f32, [%i3 + 0 ] %asi
83022
83023P7992: !_MEMBAR (FP)
83024
83025P7993: !_BST [5] (maybe <- 0x4300012a) (FP)
83026wr %g0, 0xf0, %asi
83027! preparing store val #0, next val will be in f32
83028fmovs %f16, %f20
83029fadds %f16, %f17, %f16
83030! preparing store val #1, next val will be in f33
83031fmovs %f16, %f21
83032fadds %f16, %f17, %f16
83033! preparing store val #2, next val will be in f35
83034fmovd %f20, %f32
83035fmovs %f16, %f21
83036fadds %f16, %f17, %f16
83037fmovd %f20, %f34
83038membar #Sync
83039stda %f32, [%i1 + 0 ] %asi
83040
83041P7994: !_MEMBAR (FP)
83042membar #StoreLoad
83043
83044P7995: !_LDD [23] (Int)
83045sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
83046sub %i0, %i2, %i2
83047ldd [%i2 + 8], %l6
83048! move %l7(lower) -> %o3(upper)
83049sllx %l7, 32, %o3
83050
83051P7996: !_LD [9] (Int) (CBR)
83052sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
83053sub %i0, %i3, %i3
83054lduw [%i3 + 0], %l6
83055! move %l6(lower) -> %o3(lower)
83056or %l6, %o3, %o3
83057
83058! cbranch
83059andcc %l0, 1, %g0
83060be,pt %xcc, TARGET7996
83061nop
83062RET7996:
83063
83064! lfsr step begin
83065srlx %l0, 1, %l7
83066xnor %l7, %l0, %l7
83067sllx %l7, 63, %l7
83068or %l7, %l0, %l0
83069srlx %l0, 1, %l0
83070
83071
83072P7997: !_CAS [19] (maybe <- 0x3800199) (Int) (CBR)
83073sethi %hi(REGION0_ALIAS0_O-REGION6_ALIAS2_O), %i2
83074sub %i0, %i2, %i2
83075add %i2, 4, %l3
83076lduw [%l3], %o4
83077mov %o4, %o5
83078! move %o5(lower) -> %o4(upper)
83079sllx %o5, 32, %o4
83080mov %l4, %l7
83081cas [%l3], %o5, %l7
83082! move %l7(lower) -> %o4(lower)
83083srl %l7, 0, %o5
83084or %o5, %o4, %o4
83085!---- flushing int results buffer----
83086mov %o0, %l5
83087mov %o1, %l5
83088mov %o2, %l5
83089mov %o3, %l5
83090mov %o4, %l5
83091add %l4, 1, %l4
83092
83093! cbranch
83094andcc %l0, 1, %g0
83095be,pt %xcc, TARGET7997
83096nop
83097RET7997:
83098
83099! lfsr step begin
83100srlx %l0, 1, %o5
83101xnor %o5, %l0, %o5
83102sllx %o5, 63, %o5
83103or %o5, %l0, %l0
83104srlx %l0, 1, %l0
83105
83106
83107P7998: !_MEMBAR (FP)
83108membar #StoreLoad
83109
83110P7999: !_BLD [14] (FP)
83111wr %g0, 0xf0, %asi
83112sethi %hi(REGION0_ALIAS0_O-REGION4_ALIAS1_O), %i3
83113sub %i0, %i3, %i3
83114ldda [%i3 + 0] %asi, %f32
83115membar #Sync
83116! 3 addresses covered
83117fmovd %f32, %f18
83118fmovs %f18, %f11
83119fmovs %f19, %f12
83120fmovd %f34, %f18
83121fmovs %f19, %f13
83122
83123P8000: !_MEMBAR (FP)
83124
83125P8001: !_BLD [2] (FP)
83126wr %g0, 0xf0, %asi
83127ldda [%i0 + 0] %asi, %f32
83128membar #Sync
83129! 3 addresses covered
83130fmovd %f32, %f14
83131!---- flushing fp results buffer to %f30 ----
83132fmovd %f0, %f30
83133fmovd %f2, %f30
83134fmovd %f4, %f30
83135fmovd %f6, %f30
83136fmovd %f8, %f30
83137fmovd %f10, %f30
83138fmovd %f12, %f30
83139fmovd %f14, %f30
83140!--
83141fmovd %f34, %f18
83142fmovs %f19, %f0
83143
83144P8002: !_MEMBAR (FP) (Branch target of P7645)
83145ba P8003
83146nop
83147
83148TARGET7645:
83149ba RET7645
83150nop
83151
83152
83153P8003: !_SWAP [16] (maybe <- 0x380019a) (Int)
83154sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i2
83155sub %i0, %i2, %i2
83156mov %l4, %o0
83157swap [%i2 + 4], %o0
83158! move %o0(lower) -> %o0(upper)
83159sllx %o0, 32, %o0
83160add %l4, 1, %l4
83161
83162P8004: !_DWLD [11] (Int)
83163sethi %hi(REGION0_ALIAS0_O-REGION3_ALIAS2_O), %i3
83164sub %i0, %i3, %i3
83165ldx [%i3 + 8], %l3
83166! move %l3(lower) -> %o0(lower)
83167srl %l3, 0, %o5
83168or %o5, %o0, %o0
83169
83170P8005: !_CASX [21] (maybe <- 0x380019b) (Int)
83171sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i2
83172sub %i0, %i2, %i2
83173ldx [%i2], %o1
83174! move %o1(upper) -> %o1(upper)
83175! move %o1(lower) -> %o1(lower)
83176mov %o1, %l6
83177sllx %l4, 32, %o2
83178add %l4, 1, %l4
83179or %l4, %o2, %o2
83180casx [%i2], %l6, %o2
83181! move %o2(upper) -> %o2(upper)
83182! move %o2(lower) -> %o2(lower)
83183add %l4, 1, %l4
83184
83185P8006: !_DWST [11] (maybe <- 0x380019d) (Int)
83186mov %l4, %l6
83187stx %l6, [%i3 + 8]
83188add %l4, 1, %l4
83189
83190P8007: !_MEMBAR (FP)
83191membar #StoreLoad
83192
83193P8008: !_BLD [11] (FP)
83194wr %g0, 0xf0, %asi
83195ldda [%i3 + 0] %asi, %f32
83196membar #Sync
83197! 3 addresses covered
83198fmovd %f32, %f18
83199fmovs %f18, %f1
83200fmovs %f19, %f2
83201fmovd %f34, %f18
83202fmovs %f19, %f3
83203
83204P8009: !_MEMBAR (FP)
83205
83206P8010: !_DWST [15] (maybe <- 0x380019e) (Int)
83207sethi %hi(REGION0_ALIAS0_O-REGION5_ALIAS1_O), %i3
83208sub %i0, %i3, %i3
83209sllx %l4, 32, %l3
83210add %l4, 1, %l4
83211or %l3, %l4, %l3
83212stx %l3, [%i3 + 0]
83213add %l4, 1, %l4
83214
83215P8011: !_LD [7] (Int)
83216sethi %hi(REGION0_ALIAS0_O-REGION2_ALIAS2_O), %i2
83217sub %i0, %i2, %i2
83218lduw [%i2 + 4], %o3
83219! move %o3(lower) -> %o3(upper)
83220sllx %o3, 32, %o3
83221
83222P8012: !_LD [2] (Int)
83223lduw [%i0 + 12], %l7
83224! move %l7(lower) -> %o3(lower)
83225or %l7, %o3, %o3
83226
83227P8013: !_SWAP [15] (maybe <- 0x38001a0) (Int)
83228mov %l4, %o4
83229swap [%i3 + 0], %o4
83230! move %o4(lower) -> %o4(upper)
83231sllx %o4, 32, %o4
83232add %l4, 1, %l4
83233
83234P8014: !_MEMBAR (FP)
83235
83236P8015: !_BSTC [23] (maybe <- 0x4300012d) (FP)
83237wr %g0, 0xe0, %asi
83238sethi %hi(REGION0_ALIAS0_O-REGION7_ALIAS1_O), %i3
83239sub %i0, %i3, %i3
83240! preparing store val #0, next val will be in f32
83241fmovs %f16, %f20
83242fadds %f16, %f17, %f16
83243! preparing store val #1, next val will be in f33
83244fmovs %f16, %f21
83245fadds %f16, %f17, %f16
83246! preparing store val #2, next val will be in f35
83247fmovd %f20, %f32
83248fmovs %f16, %f21
83249fadds %f16, %f17, %f16
83250fmovd %f20, %f34
83251membar #Sync
83252stda %f32, [%i3 + 0 ] %asi
83253
83254P8016: !_MEMBAR (FP)
83255membar #StoreLoad
83256
83257P8017: !_LD [3] (Int) (Loop exit)
83258lduw [%i1 + 0], %l7
83259! move %l7(lower) -> %o4(lower)
83260or %l7, %o4, %o4
83261!---- flushing int results buffer----
83262mov %o0, %l5
83263mov %o1, %l5
83264mov %o2, %l5
83265mov %o3, %l5
83266mov %o4, %l5
83267!---- flushing fp results buffer to %f30 ----
83268fmovd %f0, %f30
83269fmovd %f2, %f30
83270!--
83271loop_exit_7_0:
83272sub %l2, 1, %l2
83273cmp %l2, 0
83274bg loop_entry_7_0
83275nop
83276
83277P8018: !_MEMBAR (Int)
83278membar #StoreLoad
83279
83280END_NODES7: ! Test instruction sequence for CPU 7 ends
83281sethi %hi(0xdead0e0f), %l3
83282or %l3, %lo(0xdead0e0f), %l3
83283! move %l3(lower) -> %o0(upper)
83284sllx %l3, 32, %o0
83285sethi %hi(0xdead0e0f), %l3
83286or %l3, %lo(0xdead0e0f), %l3
83287stw %l3, [%i5]
83288ld [%i5], %f0
83289!---- flushing int results buffer----
83290mov %o0, %l5
83291!---- flushing fp results buffer to %f30 ----
83292fmovs %f0, %f30
83293!--
83294
83295restore
83296retl
83297nop
83298tsotool_text_end:
83299
83300
83301!#0 N1 P1 DWLD 6 -1 Int BE Pri Loop_entry
83302!#0 N2 P1 DWLD 7 -1 Int BE Pri Loop_entry
83303!#A N1 N2
83304!#0 N3 P2 MEMBAR
83305!#0 N4 P3 BSTC 3 0x3f800001 FP BE Pri
83306!#0 N5 P3 BSTC 4 0x3f800002 FP BE Pri
83307!#A N4 N5
83308!#0 N6 P3 BSTC 5 0x3f800003 FP BE Pri
83309!#0 N7 P4 MEMBAR
83310!#0 N8 P5 DWLD 12 -1 Int BE Pri
83311!#0 N9 P5 DWLD 13 -1 Int BE Pri
83312!#A N8 N9
83313!#0 N10 P6 DWLD 18 -1 Int BE Pri
83314!#0 N11 P6 DWLD 19 -1 Int BE Pri
83315!#A N10 N11
83316!#0 N12 P7 MEMBAR
83317!#0 N13 P8 BST 6 0x3f800004 FP BE Pri
83318!#0 N14 P8 BST 7 0x3f800005 FP BE Pri
83319!#A N13 N14
83320!#0 N15 P8 BST 8 0x3f800006 FP BE Pri
83321!#0 N16 P9 MEMBAR
83322!#0 N17 P10 LD 10 -1 Int BE Pri
83323!#0 N18 P11 LD 11 -1 Int BE Pri
83324!#0 N19 P12 DWST_BINIT 8 0x1 Int BE Pri
83325!#0 N20 P13 MEMBAR
83326!#0 N21 P14 DWST_BINIT 8 0x2 Int BE Pri
83327!#0 N22 P15 MEMBAR
83328!#0 N23 P16 DWST 17 0x3 Int BE Pri
83329!#0 N24 P17 SWAP 20 0xffffffff 0x4 Int BE Pri
83330!#0 N25 P18 ST 5 0x5 Int BE Pri
83331!#0 N26 P19 LD 8 -1 Int BE Pri
83332!#0 N27 P19 CAS 8 -1 N26 0x6 Int BE Pri
83333!#0 N28 P20 MEMBAR
83334!#0 N29 P21 BSTC 6 0x3f800007 FP BE Pri
83335!#0 N30 P21 BSTC 7 0x3f800008 FP BE Pri
83336!#A N29 N30
83337!#0 N31 P21 BSTC 8 0x3f800009 FP BE Pri
83338!#0 N32 P22 MEMBAR
83339!#0 N33 P23 BLD 3 -1 FP BE Pri
83340!#0 N34 P23 BLD 4 -1 FP BE Pri
83341!#A N33 N34
83342!#0 N35 P23 BLD 5 -1 FP BE Pri
83343!#0 N36 P24 MEMBAR
83344!#0 N37 P25 BSTC 21 0x3f80000a FP BE Pri
83345!#0 N38 P25 BSTC 22 0x3f80000b FP BE Pri
83346!#A N37 N38
83347!#0 N39 P25 BSTC 23 0x3f80000c FP BE Pri
83348!#0 N40 P26 MEMBAR
83349!#0 N41 P27 PREFETCH 6 Int BE Pri
83350!#0 N42 P28 MEMBAR
83351!#0 N43 P29 BST 21 0x3f80000d FP BE Pri
83352!#0 N44 P29 BST 22 0x3f80000e FP BE Pri
83353!#A N43 N44
83354!#0 N45 P29 BST 23 0x3f80000f FP BE Pri
83355!#0 N46 P30 MEMBAR
83356!#0 N47 P31 LD 8 -1 Int BE Pri
83357!#0 N48 P32 PREFETCH 14 Int BE Pri
83358!#0 N49 P33 LDD 15 -1 Int BE Pri
83359!#0 N50 P33 LDD 16 -1 Int BE Pri
83360!#A N49 N50
83361!#0 N51 P34 MEMBAR
83362!#0 N52 P35 BLD 6 -1 FP BE Pri
83363!#0 N53 P35 BLD 7 -1 FP BE Pri
83364!#A N52 N53
83365!#0 N54 P35 BLD 8 -1 FP BE Pri
83366!#0 N55 P36 MEMBAR
83367!#0 N56 P37 DWLD 8 -1 Int BE Pri
83368!#0 N57 P38 SWAP 17 0xffffffff 0x7 Int BE Pri
83369!#0 N58 P39 DWLD 18 -1 Int BE Pri
83370!#0 N59 P39 DWLD 19 -1 Int BE Pri
83371!#A N58 N59
83372!#0 N60 P39 CASX 18 -1 N58 0x8 Int BE Pri
83373!#0 N61 P39 CASX 19 -1 N59 0x9 Int BE Pri
83374!#A N60 N61
83375!#0 N62 P40 SWAP 23 0xffffffff 0xa Int BE Pri
83376!#0 N63 P41 DWLD 0 -1 Int BE Pri
83377!#0 N64 P41 DWLD 1 -1 Int BE Pri
83378!#A N63 N64
83379!#0 N65 P41 CASX 0 -1 N63 0xb Int BE Pri
83380!#0 N66 P41 CASX 1 -1 N64 0xc Int BE Pri
83381!#A N65 N66
83382!#0 N67 P42 LD 16 -1 Int BE Pri
83383!#0 N68 P42 CAS 16 -1 N67 0xd Int BE Pri
83384!#0 N69 P43 LDD 18 -1 Int BE Pri
83385!#0 N70 P43 LDD 19 -1 Int BE Pri
83386!#A N69 N70
83387!#0 N71 P44 LD 13 -1 Int BE Pri
83388!#0 N72 P45 MEMBAR
83389!#0 N73 P46 BST 9 0x3f800010 FP BE Pri
83390!#0 N74 P46 BST 10 0x3f800011 FP BE Pri
83391!#A N73 N74
83392!#0 N75 P46 BST 11 0x3f800012 FP BE Pri
83393!#0 N76 P47 MEMBAR
83394!#0 N77 P48 DWST 8 0xe Int BE Pri
83395!#0 N78 P49 MEMBAR
83396!#0 N79 P50 BST 9 0x3f800013 FP BE Pri
83397!#0 N80 P50 BST 10 0x3f800014 FP BE Pri
83398!#A N79 N80
83399!#0 N81 P50 BST 11 0x3f800015 FP BE Pri
83400!#0 N82 P51 MEMBAR
83401!#0 N83 P52 DWST_BINIT 3 0xf Int BE Pri
83402!#0 N84 P52 DWST_BINIT 4 0x10 Int BE Pri
83403!#A N83 N84
83404!#0 N85 P53 MEMBAR
83405!#0 N86 P54 BSTC 0 0x3f800016 FP BE Pri
83406!#0 N87 P54 BSTC 1 0x3f800017 FP BE Pri
83407!#A N86 N87
83408!#0 N88 P54 BSTC 2 0x3f800018 FP BE Pri
83409!#0 N89 P55 MEMBAR
83410!#0 N90 P56 BSTC 12 0x3f800019 FP BE Pri
83411!#0 N91 P56 BSTC 13 0x3f80001a FP BE Pri
83412!#A N90 N91
83413!#0 N92 P56 BSTC 14 0x3f80001b FP BE Pri
83414!#0 N93 P57 MEMBAR
83415!#0 N94 P58 BLD 6 -1 FP BE Pri
83416!#0 N95 P58 BLD 7 -1 FP BE Pri
83417!#A N94 N95
83418!#0 N96 P58 BLD 8 -1 FP BE Pri
83419!#0 N97 P59 MEMBAR
83420!#0 N98 P60 PREFETCH 18 Int BE Pri
83421!#0 N99 P61 REPLACEMENT 20 Int BE Pri
83422!#0 N100 P62 MEMBAR
83423!#0 N101 P63 BST 12 0x3f80001c FP BE Pri
83424!#0 N102 P63 BST 13 0x3f80001d FP BE Pri
83425!#A N101 N102
83426!#0 N103 P63 BST 14 0x3f80001e FP BE Pri
83427!#0 N104 P64 MEMBAR
83428!#0 N105 P65 DWST_BINIT 23 0x11 Int BE Pri
83429!#0 N106 P66 MEMBAR
83430!#0 N107 P67 LD 4 -1 Int BE Pri
83431!#0 N108 P67 CAS 4 -1 N107 0x12 Int BE Pri
83432!#0 N109 P68 ST 3 0x13 Int BE Pri
83433!#0 N110 P69 REPLACEMENT 4 Int BE Pri
83434!#0 N111 P70 MEMBAR
83435!#0 N112 P71 BLD 3 -1 FP BE Pri
83436!#0 N113 P71 BLD 4 -1 FP BE Pri
83437!#A N112 N113
83438!#0 N114 P71 BLD 5 -1 FP BE Pri
83439!#0 N115 P72 MEMBAR
83440!#0 N116 P73 ST 7 0x14 Int LE Pri
83441!#0 N117 P74 DWST 0 0x15 Int BE Pri
83442!#0 N118 P74 DWST 1 0x16 Int BE Pri
83443!#A N117 N118
83444!#0 N119 P75 DWLD 8 -1,0x0 Int BE Pri
83445!#0 N120 P75 CASX 8 -1,0x0 N119 0x17 Int BE Pri
83446!#0 N121 P76 SWAP 11 0xffffffff 0x18 Int BE Pri
83447!#0 N122 P77 LD 19 -1 Int BE Pri
83448!#0 N123 P78 SWAP 1 0xffffffff 0x19 Int BE Pri
83449!#0 N124 P79 DWST 0 0x1a Int BE Pri
83450!#0 N125 P79 DWST 1 0x1b Int BE Pri
83451!#A N124 N125
83452!#0 N126 P80 LD 0 -1 Int BE Pri
83453!#0 N127 P80 CAS 0 -1 N126 0x1c Int BE Pri
83454!#0 N128 P81 ST_BINIT 23 0x1d Int BE Pri
83455!#0 N129 P82 MEMBAR
83456!#0 N130 P83 LD 6 -1 Int BE Pri
83457!#0 N131 P83 CAS 6 -1 N130 0x1e Int BE Pri
83458!#0 N132 P84 DWLD 6 -1 Int BE Pri
83459!#0 N133 P84 DWLD 7 -1 Int BE Pri
83460!#A N132 N133
83461!#0 N134 P84 CASX 6 -1 N132 0x1f Int BE Pri
83462!#0 N135 P84 CASX 7 -1 N133 0x20 Int BE Pri
83463!#A N134 N135
83464!#0 N136 P85 DWLD 6 -1 Int BE Pri
83465!#0 N137 P85 DWLD 7 -1 Int BE Pri
83466!#A N136 N137
83467!#0 N138 P86 MEMBAR
83468!#0 N139 P87 BST 6 0x3f80001f FP BE Pri
83469!#0 N140 P87 BST 7 0x3f800020 FP BE Pri
83470!#A N139 N140
83471!#0 N141 P87 BST 8 0x3f800021 FP BE Pri
83472!#0 N142 P88 MEMBAR
83473!#0 N143 P89 BLD 6 -1 FP BE Pri
83474!#0 N144 P89 BLD 7 -1 FP BE Pri
83475!#A N143 N144
83476!#0 N145 P89 BLD 8 -1 FP BE Pri
83477!#0 N146 P90 MEMBAR
83478!#0 N147 P91 BST 21 0x3f800022 FP BE Pri
83479!#0 N148 P91 BST 22 0x3f800023 FP BE Pri
83480!#A N147 N148
83481!#0 N149 P91 BST 23 0x3f800024 FP BE Pri
83482!#0 N150 P92 MEMBAR
83483!#0 N151 P93 LDD 23 -1 Int BE Pri
83484!#0 N152 P94 LD 23 -1 Int LE Pri
83485!#0 N153 P95 MEMBAR
83486!#0 N154 P96 BST 3 0x3f800025 FP BE Pri
83487!#0 N155 P96 BST 4 0x3f800026 FP BE Pri
83488!#A N154 N155
83489!#0 N156 P96 BST 5 0x3f800027 FP BE Pri
83490!#0 N157 P97 MEMBAR
83491!#0 N158 P98 ST_BINIT 0 0x21 Int BE Pri
83492!#0 N159 P99 MEMBAR
83493!#0 N160 P100 DWST 15 0x22 Int BE Pri
83494!#0 N161 P100 DWST 16 0x23 Int BE Pri
83495!#A N160 N161
83496!#0 N162 P101 DWST 23 0x24 Int LE Pri
83497!#0 N163 P102 ST 16 0x25 Int BE Pri
83498!#0 N164 P103 PREFETCH 13 Int BE Pri
83499!#0 N165 P104 SWAP 18 0xffffffff 0x26 Int BE Pri
83500!#0 N166 P105 ST 2 0x27 Int BE Pri
83501!#0 N167 P106 DWST 20 0x28 Int BE Pri
83502!#0 N168 P107 DWST_BINIT 5 0x29 Int BE Pri
83503!#0 N169 P108 MEMBAR
83504!#0 N170 P109 ST 5 0x2a Int BE Pri
83505!#0 N171 P110 ST 16 0x2b Int BE Pri
83506!#0 N172 P111 REPLACEMENT 11 Int BE Pri
83507!#0 N173 P112 PREFETCH 1 Int BE Pri
83508!#0 N174 P113 DWST 21 0x2c Int BE Pri
83509!#0 N175 P113 DWST 22 0x2d Int BE Pri
83510!#A N174 N175
83511!#0 N176 P114 LD 2 -1 Int BE Pri
83512!#0 N177 P114 CAS 2 -1 N176 0x2e Int BE Pri
83513!#0 N178 P115 ST_BINIT 21 0x2f Int BE Pri
83514!#0 N179 P116 MEMBAR
83515!#0 N180 P117 LD 13 -1 Int BE Pri
83516!#0 N181 P117 CAS 13 -1 N180 0x30 Int BE Pri
83517!#0 N182 P118 LD 6 -1 Int BE Pri
83518!#0 N183 P118 CAS 6 -1 N182 0x31 Int BE Pri
83519!#0 N184 P119 LD 1 -1 Int LE Pri
83520!#0 N185 P119 CAS 1 -1 N184 0x32 Int LE Pri
83521!#0 N186 P120 SWAP 21 0xffffffff 0x33 Int BE Pri
83522!#0 N187 P121 SWAP 2 0xffffffff 0x34 Int BE Pri
83523!#0 N188 P122 DWLD 15 -1 Int LE Pri
83524!#0 N189 P122 DWLD 16 -1 Int LE Pri
83525!#A N188 N189
83526!#0 N190 P122 CASX 15 -1 N188 0x35 Int LE Pri
83527!#0 N191 P122 CASX 16 -1 N189 0x36 Int LE Pri
83528!#A N190 N191
83529!#0 N192 P123 SWAP 15 0xffffffff 0x37 Int BE Pri
83530!#0 N193 P124 LDD 9 -1 Int BE Pri
83531!#0 N194 P124 LDD 10 -1 Int BE Pri
83532!#A N193 N194
83533!#0 N195 P125 DWLD 14 -1,0x0 Int BE Pri
83534!#0 N196 P125 CASX 14 -1,0x0 N195 0x38 Int BE Pri
83535!#0 N197 P126 DWLD 0 -1 Int BE Pri
83536!#0 N198 P126 DWLD 1 -1 Int BE Pri
83537!#A N197 N198
83538!#0 N199 P127 LD 18 -1 Int LE Pri
83539!#0 N200 P127 CAS 18 -1 N199 0x39 Int LE Pri
83540!#0 N201 P128 DWLD 3 -1 Int BE Pri
83541!#0 N202 P128 DWLD 4 -1 Int BE Pri
83542!#A N201 N202
83543!#0 N203 P128 CASX 3 -1 N201 0x3a Int BE Pri
83544!#0 N204 P128 CASX 4 -1 N202 0x3b Int BE Pri
83545!#A N203 N204
83546!#0 N205 P129 DWLD 3 -1 Int BE Pri
83547!#0 N206 P129 DWLD 4 -1 Int BE Pri
83548!#A N205 N206
83549!#0 N207 P129 CASX 3 -1 N205 0x3c Int BE Pri
83550!#0 N208 P129 CASX 4 -1 N206 0x3d Int BE Pri
83551!#A N207 N208
83552!#0 N209 P130 LD 2 -1 Int BE Pri
83553!#0 N210 P130 CAS 2 -1 N209 0x3e Int BE Pri
83554!#0 N211 P131 ST_BINIT 6 0x3f Int BE Pri
83555!#0 N212 P132 MEMBAR
83556!#0 N213 P133 PREFETCH 23 Int BE Pri
83557!#0 N214 P134 MEMBAR
83558!#0 N215 P135 BSTC 6 0x3f800028 FP BE Pri
83559!#0 N216 P135 BSTC 7 0x3f800029 FP BE Pri
83560!#A N215 N216
83561!#0 N217 P135 BSTC 8 0x3f80002a FP BE Pri
83562!#0 N218 P136 MEMBAR
83563!#0 N219 P137 LD 21 -1 Int BE Pri
83564!#0 N220 P138 MEMBAR
83565!#0 N221 P139 BSTC 21 0x3f80002b FP BE Pri
83566!#0 N222 P139 BSTC 22 0x3f80002c FP BE Pri
83567!#A N221 N222
83568!#0 N223 P139 BSTC 23 0x3f80002d FP BE Pri
83569!#0 N224 P140 MEMBAR
83570!#0 N225 P141 ST 6 0x40 Int BE Pri
83571!#0 N226 P142 ST 8 0x41 Int LE Pri
83572!#0 N227 P143 SWAP 18 0xffffffff 0x42 Int BE Pri
83573!#0 N228 P144 SWAP 2 0xffffffff 0x43 Int BE Pri
83574!#0 N229 P145 DWLD 3 -1 Int BE Pri
83575!#0 N230 P145 DWLD 4 -1 Int BE Pri
83576!#A N229 N230
83577!#0 N231 P146 PREFETCH 12 Int BE Pri
83578!#0 N232 P147 DWLD 21 -1 Int BE Pri
83579!#0 N233 P147 DWLD 22 -1 Int BE Pri
83580!#A N232 N233
83581!#0 N234 P147 CASX 21 -1 N232 0x44 Int BE Pri
83582!#0 N235 P147 CASX 22 -1 N233 0x45 Int BE Pri
83583!#A N234 N235
83584!#0 N236 P148 ST 21 0x46 Int LE Pri
83585!#0 N237 P149 MEMBAR
83586!#0 N238 P150 BST 18 0x3f80002e FP BE Pri
83587!#0 N239 P150 BST 19 0x3f80002f FP BE Pri
83588!#A N238 N239
83589!#0 N240 P150 BST 20 0x3f800030 FP BE Pri
83590!#0 N241 P151 MEMBAR
83591!#0 N242 P152 LD 1 -1 Int BE Pri
83592!#0 N243 P152 CAS 1 -1 N242 0x47 Int BE Pri
83593!#0 N244 P153 LD 9 -1 Int BE Pri
83594!#0 N245 P153 CAS 9 -1 N244 0x48 Int BE Pri
83595!#0 N246 P154 ST_BINIT 20 0x49 Int BE Pri
83596!#0 N247 P155 MEMBAR
83597!#0 N248 P156 SWAP 19 0xffffffff 0x4a Int BE Pri
83598!#0 N249 P157 MEMBAR
83599!#0 N250 P158 BST 18 0x3f800031 FP BE Pri
83600!#0 N251 P158 BST 19 0x3f800032 FP BE Pri
83601!#A N250 N251
83602!#0 N252 P158 BST 20 0x3f800033 FP BE Pri
83603!#0 N253 P159 MEMBAR
83604!#0 N254 P160 DWST 2 0x4b Int BE Pri
83605!#0 N255 P161 LDD 20 -1 Int BE Pri
83606!#0 N256 P162 MEMBAR
83607!#0 N257 P163 BLD 15 -1 FP BE Pri
83608!#0 N258 P163 BLD 16 -1 FP BE Pri
83609!#A N257 N258
83610!#0 N259 P163 BLD 17 -1 FP BE Pri
83611!#0 N260 P164 MEMBAR
83612!#0 N261 P165 ST_BINIT 16 0x4c Int BE Pri
83613!#0 N262 P166 MEMBAR
83614!#0 N263 P167 BLD 6 -1 FP BE Pri
83615!#0 N264 P167 BLD 7 -1 FP BE Pri
83616!#A N263 N264
83617!#0 N265 P167 BLD 8 -1 FP BE Pri
83618!#0 N266 P168 MEMBAR
83619!#0 N267 P169 DWST 18 0x4d Int BE Pri
83620!#0 N268 P169 DWST 19 0x4e Int BE Pri
83621!#A N267 N268
83622!#0 N269 P170 DWST_BINIT 18 0x4f Int BE Pri
83623!#0 N270 P170 DWST_BINIT 19 0x50 Int BE Pri
83624!#A N269 N270
83625!#0 N271 P171 MEMBAR
83626!#0 N272 P172 DWST 14 0x51 Int BE Pri
83627!#0 N273 P173 LDD 6 -1 Int BE Pri
83628!#0 N274 P173 LDD 7 -1 Int BE Pri
83629!#A N273 N274
83630!#0 N275 P174 DWLD 3 -1 Int BE Pri
83631!#0 N276 P174 DWLD 4 -1 Int BE Pri
83632!#A N275 N276
83633!#0 N277 P175 MEMBAR
83634!#0 N278 P176 BLD 9 -1 FP BE Pri
83635!#0 N279 P176 BLD 10 -1 FP BE Pri
83636!#A N278 N279
83637!#0 N280 P176 BLD 11 -1 FP BE Pri
83638!#0 N281 P177 MEMBAR
83639!#0 N282 P178 BSTC 18 0x3f800034 FP BE Pri
83640!#0 N283 P178 BSTC 19 0x3f800035 FP BE Pri
83641!#A N282 N283
83642!#0 N284 P178 BSTC 20 0x3f800036 FP BE Pri
83643!#0 N285 P179 MEMBAR
83644!#0 N286 P180 BSTC 21 0x3f800037 FP BE Pri
83645!#0 N287 P180 BSTC 22 0x3f800038 FP BE Pri
83646!#A N286 N287
83647!#0 N288 P180 BSTC 23 0x3f800039 FP BE Pri
83648!#0 N289 P181 MEMBAR
83649!#0 N290 P182 LD 9 -1 Int BE Pri
83650!#0 N291 P182 CAS 9 -1 N290 0x52 Int BE Pri
83651!#0 N292 P183 DWLD 2 -1,0x0 Int BE Pri
83652!#0 N293 P183 CASX 2 -1,0x0 N292 0x53 Int BE Pri
83653!#0 N294 P184 DWST 12 0x54 Int BE Pri
83654!#0 N295 P184 DWST 13 0x55 Int BE Pri
83655!#A N294 N295
83656!#0 N296 P185 ST 7 0x56 Int BE Pri
83657!#0 N297 P186 DWST_BINIT 3 0x57 Int BE Pri
83658!#0 N298 P186 DWST_BINIT 4 0x58 Int BE Pri
83659!#A N297 N298
83660!#0 N299 P187 MEMBAR
83661!#0 N300 P188 ST_BINIT 9 0x59 Int BE Pri
83662!#0 N301 P189 MEMBAR
83663!#0 N302 P190 PREFETCH 3 Int BE Pri
83664!#0 N303 P191 LD 13 -1 Int BE Pri
83665!#0 N304 P191 CAS 13 -1 N303 0x5a Int BE Pri
83666!#0 N305 P192 DWST_BINIT 15 0x5b Int BE Pri
83667!#0 N306 P192 DWST_BINIT 16 0x5c Int BE Pri
83668!#A N305 N306
83669!#0 N307 P193 MEMBAR
83670!#0 N308 P194 ST_BINIT 14 0x5d Int BE Pri
83671!#0 N309 P195 MEMBAR
83672!#0 N310 P196 LD 12 -1 FP BE Pri
83673!#0 N311 P197 MEMBAR
83674!#0 N312 P198 BLD 3 -1 FP BE Pri
83675!#0 N313 P198 BLD 4 -1 FP BE Pri
83676!#A N312 N313
83677!#0 N314 P198 BLD 5 -1 FP BE Pri
83678!#0 N315 P199 MEMBAR
83679!#0 N316 P200 BSTC 0 0x3f80003a FP BE Pri
83680!#0 N317 P200 BSTC 1 0x3f80003b FP BE Pri
83681!#A N316 N317
83682!#0 N318 P200 BSTC 2 0x3f80003c FP BE Pri
83683!#0 N319 P201 MEMBAR
83684!#0 N320 P202 LD 2 -1 Int BE Pri
83685!#0 N321 P203 REPLACEMENT 15 Int BE Pri
83686!#0 N322 P204 DWST 18 0x5e Int BE Pri
83687!#0 N323 P204 DWST 19 0x5f Int BE Pri
83688!#A N322 N323
83689!#0 N324 P205 ST 17 0x60 Int BE Pri
83690!#0 N325 P206 MEMBAR
83691!#0 N326 P207 BSTC 9 0x3f80003d FP BE Pri
83692!#0 N327 P207 BSTC 10 0x3f80003e FP BE Pri
83693!#A N326 N327
83694!#0 N328 P207 BSTC 11 0x3f80003f FP BE Pri
83695!#0 N329 P208 MEMBAR
83696!#0 N330 P209 DWST 11 0x61 Int BE Pri
83697!#0 N331 P210 ST 12 0x3f800040 FP BE Pri
83698!#0 N332 P211 MEMBAR
83699!#0 N333 P212 BSTC 18 0x3f800041 FP BE Pri
83700!#0 N334 P212 BSTC 19 0x3f800042 FP BE Pri
83701!#A N333 N334
83702!#0 N335 P212 BSTC 20 0x3f800043 FP BE Pri
83703!#0 N336 P213 MEMBAR
83704!#0 N337 P214 LD 7 -1 Int BE Pri
83705!#0 N338 P214 CAS 7 -1 N337 0x62 Int BE Pri
83706!#0 N339 P215 DWLD 12 -1 Int BE Pri
83707!#0 N340 P215 DWLD 13 -1 Int BE Pri
83708!#A N339 N340
83709!#0 N341 P215 CASX 12 -1 N339 0x63 Int BE Pri
83710!#0 N342 P215 CASX 13 -1 N340 0x64 Int BE Pri
83711!#A N341 N342
83712!#0 N343 P216 DWLD 18 -1 Int BE Pri
83713!#0 N344 P216 DWLD 19 -1 Int BE Pri
83714!#A N343 N344
83715!#0 N345 P217 ST_BINIT 8 0x65 Int BE Pri
83716!#0 N346 P218 MEMBAR
83717!#0 N347 P219 SWAP 18 0xffffffff 0x66 Int BE Pri
83718!#0 N348 P220 MEMBAR
83719!#0 N349 P221 BLD 18 -1 FP BE Pri
83720!#0 N350 P221 BLD 19 -1 FP BE Pri
83721!#A N349 N350
83722!#0 N351 P221 BLD 20 -1 FP BE Pri
83723!#0 N352 P222 MEMBAR
83724!#0 N353 P223 BSTC 9 0x3f800044 FP BE Pri
83725!#0 N354 P223 BSTC 10 0x3f800045 FP BE Pri
83726!#A N353 N354
83727!#0 N355 P223 BSTC 11 0x3f800046 FP BE Pri
83728!#0 N356 P224 MEMBAR
83729!#0 N357 P225 SWAP 23 0xffffffff 0x67 Int BE Pri
83730!#0 N358 P226 DWST_BINIT 20 0x68 Int BE Pri
83731!#0 N359 P227 MEMBAR
83732!#0 N360 P228 DWST_BINIT 0 0x69 Int BE Pri
83733!#0 N361 P228 DWST_BINIT 1 0x6a Int BE Pri
83734!#A N360 N361
83735!#0 N362 P229 MEMBAR
83736!#0 N363 P230 BLD 9 -1 FP BE Pri
83737!#0 N364 P230 BLD 10 -1 FP BE Pri
83738!#A N363 N364
83739!#0 N365 P230 BLD 11 -1 FP BE Pri
83740!#0 N366 P231 MEMBAR
83741!#0 N367 P232 LD 23 -1 Int BE Pri
83742!#0 N368 P232 CAS 23 -1 N367 0x6b Int BE Pri
83743!#0 N369 P233 LD 21 -1 Int BE Pri
83744!#0 N370 P233 CAS 21 -1 N369 0x6c Int BE Pri
83745!#0 N371 P234 DWLD 18 -1 Int BE Pri
83746!#0 N372 P234 DWLD 19 -1 Int BE Pri
83747!#A N371 N372
83748!#0 N373 P234 CASX 18 -1 N371 0x6d Int BE Pri
83749!#0 N374 P234 CASX 19 -1 N372 0x6e Int BE Pri
83750!#A N373 N374
83751!#0 N375 P235 MEMBAR
83752!#0 N376 P236 BST 0 0x3f800047 FP BE Pri
83753!#0 N377 P236 BST 1 0x3f800048 FP BE Pri
83754!#A N376 N377
83755!#0 N378 P236 BST 2 0x3f800049 FP BE Pri
83756!#0 N379 P237 MEMBAR
83757!#0 N380 P238 PREFETCH 2 Int BE Pri
83758!#0 N381 P239 DWLD 20 -1,0x0 Int BE Pri
83759!#0 N382 P239 CASX 20 -1,0x0 N381 0x6f Int BE Pri
83760!#0 N383 P240 MEMBAR
83761!#0 N384 P241 BLD 0 -1 FP BE Pri
83762!#0 N385 P241 BLD 1 -1 FP BE Pri
83763!#A N384 N385
83764!#0 N386 P241 BLD 2 -1 FP BE Pri
83765!#0 N387 P242 MEMBAR
83766!#0 N388 P243 LD 3 -1 Int BE Pri
83767!#0 N389 P243 CAS 3 -1 N388 0x70 Int BE Pri
83768!#0 N390 P244 DWLD 21 -1 Int LE Pri
83769!#0 N391 P244 DWLD 22 -1 Int LE Pri
83770!#A N390 N391
83771!#0 N392 P245 ST_BINIT 2 0x71 Int BE Pri
83772!#0 N393 P246 MEMBAR
83773!#0 N394 P247 BLD 12 -1 FP BE Pri
83774!#0 N395 P247 BLD 13 -1 FP BE Pri
83775!#A N394 N395
83776!#0 N396 P247 BLD 14 -1 FP BE Pri
83777!#0 N397 P248 MEMBAR
83778!#0 N398 P249 ST_BINIT 16 0x72 Int BE Pri
83779!#0 N399 P250 MEMBAR
83780!#0 N400 P251 ST_BINIT 4 0x73 Int BE Pri
83781!#0 N401 P252 MEMBAR
83782!#0 N402 P253 BSTC 15 0x3f80004a FP BE Pri
83783!#0 N403 P253 BSTC 16 0x3f80004b FP BE Pri
83784!#A N402 N403
83785!#0 N404 P253 BSTC 17 0x3f80004c FP BE Pri
83786!#0 N405 P254 MEMBAR
83787!#0 N406 P255 SWAP 19 0xffffffff 0x74 Int BE Pri
83788!#0 N407 P256 LD 23 -1 Int BE Pri
83789!#0 N408 P256 CAS 23 -1 N407 0x75 Int BE Pri
83790!#0 N409 P257 MEMBAR
83791!#0 N410 P258 BST 3 0x3f80004d FP BE Pri
83792!#0 N411 P258 BST 4 0x3f80004e FP BE Pri
83793!#A N410 N411
83794!#0 N412 P258 BST 5 0x3f80004f FP BE Pri
83795!#0 N413 P259 MEMBAR
83796!#0 N414 P260 PREFETCH 3 Int BE Pri
83797!#0 N415 P261 SWAP 21 0xffffffff 0x76 Int BE Pri
83798!#0 N416 P262 ST_BINIT 19 0x77 Int BE Pri
83799!#0 N417 P263 MEMBAR
83800!#0 N418 P264 BSTC 21 0x3f800050 FP BE Pri
83801!#0 N419 P264 BSTC 22 0x3f800051 FP BE Pri
83802!#A N418 N419
83803!#0 N420 P264 BSTC 23 0x3f800052 FP BE Pri
83804!#0 N421 P265 MEMBAR
83805!#0 N422 P266 BLD 6 -1 FP BE Pri
83806!#0 N423 P266 BLD 7 -1 FP BE Pri
83807!#A N422 N423
83808!#0 N424 P266 BLD 8 -1 FP BE Pri
83809!#0 N425 P267 MEMBAR
83810!#0 N426 P268 DWST 12 0x78 Int BE Pri
83811!#0 N427 P268 DWST 13 0x79 Int BE Pri
83812!#A N426 N427
83813!#0 N428 P269 DWLD 0 -1 Int BE Pri
83814!#0 N429 P269 DWLD 1 -1 Int BE Pri
83815!#A N428 N429
83816!#0 N430 P269 CASX 0 -1 N428 0x7a Int BE Pri
83817!#0 N431 P269 CASX 1 -1 N429 0x7b Int BE Pri
83818!#A N430 N431
83819!#0 N432 P270 LD 20 -1 Int BE Pri
83820!#0 N433 P271 ST_BINIT 11 0x7c Int BE Pri
83821!#0 N434 P272 MEMBAR
83822!#0 N435 P273 PREFETCH 11 Int BE Pri
83823!#0 N436 P274 LD 2 -1 Int LE Pri
83824!#0 N437 P274 CAS 2 -1 N436 0x7d Int LE Pri
83825!#0 N438 P275 ST_BINIT 15 0x7e Int BE Pri
83826!#0 N439 P276 MEMBAR
83827!#0 N440 P277 DWST_BINIT 6 0x7f Int BE Pri
83828!#0 N441 P277 DWST_BINIT 7 0x80 Int BE Pri
83829!#A N440 N441
83830!#0 N442 P278 MEMBAR
83831!#0 N443 P279 REPLACEMENT 6 Int BE Pri
83832!#0 N444 P280 LDD 3 -1 Int BE Pri
83833!#0 N445 P280 LDD 4 -1 Int BE Pri
83834!#A N444 N445
83835!#0 N446 P281 LD 22 -1 Int BE Pri
83836!#0 N447 P282 LD 6 -1 Int LE Pri
83837!#0 N448 P283 DWLD 9 -1 Int BE Pri
83838!#0 N449 P283 DWLD 10 -1 Int BE Pri
83839!#A N448 N449
83840!#0 N450 P283 CASX 9 -1 N448 0x81 Int BE Pri
83841!#0 N451 P283 CASX 10 -1 N449 0x82 Int BE Pri
83842!#A N450 N451
83843!#0 N452 P284 DWLD 3 -1 Int BE Pri
83844!#0 N453 P284 DWLD 4 -1 Int BE Pri
83845!#A N452 N453
83846!#0 N454 P285 DWLD 9 -1 Int BE Pri
83847!#0 N455 P285 DWLD 10 -1 Int BE Pri
83848!#A N454 N455
83849!#0 N456 P285 CASX 9 -1 N454 0x83 Int BE Pri
83850!#0 N457 P285 CASX 10 -1 N455 0x84 Int BE Pri
83851!#A N456 N457
83852!#0 N458 P286 MEMBAR
83853!#0 N459 P287 BSTC 0 0x3f800053 FP BE Pri
83854!#0 N460 P287 BSTC 1 0x3f800054 FP BE Pri
83855!#A N459 N460
83856!#0 N461 P287 BSTC 2 0x3f800055 FP BE Pri
83857!#0 N462 P288 MEMBAR
83858!#0 N463 P289 BSTC 21 0x3f800056 FP BE Pri
83859!#0 N464 P289 BSTC 22 0x3f800057 FP BE Pri
83860!#A N463 N464
83861!#0 N465 P289 BSTC 23 0x3f800058 FP BE Pri
83862!#0 N466 P290 MEMBAR
83863!#0 N467 P291 BLD 15 -1 FP BE Pri
83864!#0 N468 P291 BLD 16 -1 FP BE Pri
83865!#A N467 N468
83866!#0 N469 P291 BLD 17 -1 FP BE Pri
83867!#0 N470 P292 MEMBAR
83868!#0 N471 P293 BSTC 15 0x3f800059 FP BE Pri
83869!#0 N472 P293 BSTC 16 0x3f80005a FP BE Pri
83870!#A N471 N472
83871!#0 N473 P293 BSTC 17 0x3f80005b FP BE Pri
83872!#0 N474 P294 MEMBAR
83873!#0 N475 P295 ST 4 0x85 Int BE Pri
83874!#0 N476 P296 LD 10 -1 Int LE Pri
83875!#0 N477 P296 CAS 10 -1 N476 0x86 Int LE Pri
83876!#0 N478 P297 ST_BINIT 16 0x87 Int BE Pri
83877!#0 N479 P298 MEMBAR
83878!#0 N480 P299 BST 12 0x3f80005c FP BE Pri
83879!#0 N481 P299 BST 13 0x3f80005d FP BE Pri
83880!#A N480 N481
83881!#0 N482 P299 BST 14 0x3f80005e FP BE Pri
83882!#0 N483 P300 MEMBAR
83883!#0 N484 P301 PREFETCH 6 Int BE Pri
83884!#0 N485 P302 LD 7 -1 Int BE Pri
83885!#0 N486 P303 REPLACEMENT 18 Int BE Pri
83886!#0 N487 P304 LD 16 -1 Int BE Pri
83887!#0 N488 P304 CAS 16 -1 N487 0x88 Int BE Pri
83888!#0 N489 P305 DWLD 14 -1,0x0 Int BE Pri
83889!#0 N490 P305 CASX 14 -1,0x0 N489 0x89 Int BE Pri
83890!#0 N491 P306 LD 22 -1 Int BE Pri
83891!#0 N492 P307 DWST_BINIT 6 0x8a Int BE Pri
83892!#0 N493 P307 DWST_BINIT 7 0x8b Int BE Pri
83893!#A N492 N493
83894!#0 N494 P308 MEMBAR
83895!#0 N495 P309 BLD 6 -1 FP BE Pri
83896!#0 N496 P309 BLD 7 -1 FP BE Pri
83897!#A N495 N496
83898!#0 N497 P309 BLD 8 -1 FP BE Pri
83899!#0 N498 P310 MEMBAR
83900!#0 N499 P311 BST 18 0x3f80005f FP BE Pri
83901!#0 N500 P311 BST 19 0x3f800060 FP BE Pri
83902!#A N499 N500
83903!#0 N501 P311 BST 20 0x3f800061 FP BE Pri
83904!#0 N502 P312 MEMBAR
83905!#0 N503 P313 DWLD 14 -1,0x0 Int BE Pri
83906!#0 N504 P313 CASX 14 -1,0x0 N503 0x8c Int BE Pri
83907!#0 N505 P314 MEMBAR
83908!#0 N506 P315 BST 21 0x3f800062 FP BE Pri
83909!#0 N507 P315 BST 22 0x3f800063 FP BE Pri
83910!#A N506 N507
83911!#0 N508 P315 BST 23 0x3f800064 FP BE Pri
83912!#0 N509 P316 MEMBAR
83913!#0 N510 P317 SWAP 17 0xffffffff 0x8d Int BE Pri
83914!#0 N511 P318 DWST_BINIT 20 0x8e Int BE Pri
83915!#0 N512 P319 MEMBAR
83916!#0 N513 P320 DWST_BINIT 6 0x8f Int BE Pri
83917!#0 N514 P320 DWST_BINIT 7 0x90 Int BE Pri
83918!#A N513 N514
83919!#0 N515 P321 MEMBAR
83920!#0 N516 P322 BST 21 0x3f800065 FP BE Pri
83921!#0 N517 P322 BST 22 0x3f800066 FP BE Pri
83922!#A N516 N517
83923!#0 N518 P322 BST 23 0x3f800067 FP BE Pri
83924!#0 N519 P323 MEMBAR
83925!#0 N520 P324 DWLD 18 -1 Int BE Pri
83926!#0 N521 P324 DWLD 19 -1 Int BE Pri
83927!#A N520 N521
83928!#0 N522 P325 PREFETCH 13 Int BE Pri
83929!#0 N523 P326 ST_BINIT 14 0x91 Int BE Pri
83930!#0 N524 P327 MEMBAR
83931!#0 N525 P328 BSTC 6 0x3f800068 FP BE Pri
83932!#0 N526 P328 BSTC 7 0x3f800069 FP BE Pri
83933!#A N525 N526
83934!#0 N527 P328 BSTC 8 0x3f80006a FP BE Pri
83935!#0 N528 P329 MEMBAR
83936!#0 N529 P330 SWAP 23 0xffffffff 0x92 Int BE Pri
83937!#0 N530 P331 DWLD 12 -1 Int BE Pri
83938!#0 N531 P331 DWLD 13 -1 Int BE Pri
83939!#A N530 N531
83940!#0 N532 P332 DWLD 18 -1 Int BE Pri
83941!#0 N533 P332 DWLD 19 -1 Int BE Pri
83942!#A N532 N533
83943!#0 N534 P333 LD 2 -1 Int BE Pri
83944!#0 N535 P334 SWAP 12 0xffffffff 0x93 Int BE Pri
83945!#0 N536 P335 MEMBAR
83946!#0 N537 P336 BST 18 0x3f80006b FP BE Pri
83947!#0 N538 P336 BST 19 0x3f80006c FP BE Pri
83948!#A N537 N538
83949!#0 N539 P336 BST 20 0x3f80006d FP BE Pri
83950!#0 N540 P337 MEMBAR
83951!#0 N541 P338 LD 8 -1 Int LE Pri
83952!#0 N542 P339 ST_BINIT 4 0x94 Int BE Pri
83953!#0 N543 P340 MEMBAR
83954!#0 N544 P341 LD 2 -1 Int BE Pri
83955!#0 N545 P341 CAS 2 -1 N544 0x95 Int BE Pri
83956!#0 N546 P342 DWST_BINIT 5 0x96 Int BE Pri
83957!#0 N547 P343 MEMBAR
83958!#0 N548 P344 BST 18 0x3f80006e FP BE Pri
83959!#0 N549 P344 BST 19 0x3f80006f FP BE Pri
83960!#A N548 N549
83961!#0 N550 P344 BST 20 0x3f800070 FP BE Pri
83962!#0 N551 P345 MEMBAR
83963!#0 N552 P346 DWST 6 0x97 Int LE Pri
83964!#0 N553 P346 DWST 7 0x98 Int LE Pri
83965!#A N552 N553
83966!#0 N554 P347 DWLD 15 -1 Int BE Pri
83967!#0 N555 P347 DWLD 16 -1 Int BE Pri
83968!#A N554 N555
83969!#0 N556 P347 CASX 15 -1 N554 0x99 Int BE Pri
83970!#0 N557 P347 CASX 16 -1 N555 0x9a Int BE Pri
83971!#A N556 N557
83972!#0 N558 P348 MEMBAR
83973!#0 N559 P349 BLD 18 -1 FP BE Pri
83974!#0 N560 P349 BLD 19 -1 FP BE Pri
83975!#A N559 N560
83976!#0 N561 P349 BLD 20 -1 FP BE Pri
83977!#0 N562 P350 MEMBAR
83978!#0 N563 P351 ST 10 0x3f800071 FP BE Pri
83979!#0 N564 P352 ST 16 0x9b Int BE Pri
83980!#0 N565 P353 MEMBAR
83981!#0 N566 P354 BSTC 15 0x3f800072 FP BE Pri
83982!#0 N567 P354 BSTC 16 0x3f800073 FP BE Pri
83983!#A N566 N567
83984!#0 N568 P354 BSTC 17 0x3f800074 FP BE Pri
83985!#0 N569 P355 MEMBAR
83986!#0 N570 P356 ST_BINIT 16 0x9c Int BE Pri
83987!#0 N571 P357 MEMBAR
83988!#0 N572 P358 BSTC 21 0x3f800075 FP BE Pri
83989!#0 N573 P358 BSTC 22 0x3f800076 FP BE Pri
83990!#A N572 N573
83991!#0 N574 P358 BSTC 23 0x3f800077 FP BE Pri
83992!#0 N575 P359 MEMBAR
83993!#0 N576 P360 BLD 18 -1 FP BE Pri
83994!#0 N577 P360 BLD 19 -1 FP BE Pri
83995!#A N576 N577
83996!#0 N578 P360 BLD 20 -1 FP BE Pri
83997!#0 N579 P361 MEMBAR
83998!#0 N580 P362 LD 0 -1 Int BE Pri
83999!#0 N581 P362 CAS 0 -1 N580 0x9d Int BE Pri
84000!#0 N582 P363 DWST_BINIT 0 0x9e Int BE Pri
84001!#0 N583 P363 DWST_BINIT 1 0x9f Int BE Pri
84002!#A N582 N583
84003!#0 N584 P364 MEMBAR
84004!#0 N585 P365 DWST 8 0xa0 Int BE Pri
84005!#0 N586 P366 PREFETCH 13 Int BE Pri
84006!#0 N587 P367 LD 9 -1 Int BE Pri
84007!#0 N588 P367 CAS 9 -1 N587 0xa1 Int BE Pri
84008!#0 N589 P368 MEMBAR
84009!#0 N590 P369 BST 6 0x3f800078 FP BE Pri
84010!#0 N591 P369 BST 7 0x3f800079 FP BE Pri
84011!#A N590 N591
84012!#0 N592 P369 BST 8 0x3f80007a FP BE Pri
84013!#0 N593 P370 MEMBAR
84014!#0 N594 P371 BLD 15 -1 FP BE Pri
84015!#0 N595 P371 BLD 16 -1 FP BE Pri
84016!#A N594 N595
84017!#0 N596 P371 BLD 17 -1 FP BE Pri
84018!#0 N597 P372 MEMBAR
84019!#0 N598 P373 SWAP 13 0xffffffff 0xa2 Int BE Pri
84020!#0 N599 P374 LDD 21 -1 Int BE Pri
84021!#0 N600 P374 LDD 22 -1 Int BE Pri
84022!#A N599 N600
84023!#0 N601 P375 DWST_BINIT 9 0xa3 Int BE Pri
84024!#0 N602 P375 DWST_BINIT 10 0xa4 Int BE Pri
84025!#A N601 N602
84026!#0 N603 P376 MEMBAR
84027!#0 N604 P377 ST_BINIT 17 0xa5 Int BE Pri
84028!#0 N605 P378 MEMBAR
84029!#0 N606 P379 BLD 15 -1 FP BE Pri
84030!#0 N607 P379 BLD 16 -1 FP BE Pri
84031!#A N606 N607
84032!#0 N608 P379 BLD 17 -1 FP BE Pri
84033!#0 N609 P380 MEMBAR
84034!#0 N610 P381 BLD 21 -1 FP BE Pri
84035!#0 N611 P381 BLD 22 -1 FP BE Pri
84036!#A N610 N611
84037!#0 N612 P381 BLD 23 -1 FP BE Pri
84038!#0 N613 P382 MEMBAR
84039!#0 N614 P383 LD 13 -1 Int BE Pri
84040!#0 N615 P383 CAS 13 -1 N614 0xa6 Int BE Pri
84041!#0 N616 P384 MEMBAR
84042!#0 N617 P385 BLD 3 -1 FP BE Pri
84043!#0 N618 P385 BLD 4 -1 FP BE Pri
84044!#A N617 N618
84045!#0 N619 P385 BLD 5 -1 FP BE Pri
84046!#0 N620 P386 MEMBAR
84047!#0 N621 P387 BSTC 0 0x3f80007b FP BE Pri
84048!#0 N622 P387 BSTC 1 0x3f80007c FP BE Pri
84049!#A N621 N622
84050!#0 N623 P387 BSTC 2 0x3f80007d FP BE Pri
84051!#0 N624 P388 MEMBAR
84052!#0 N625 P389 BLD 3 -1 FP BE Pri
84053!#0 N626 P389 BLD 4 -1 FP BE Pri
84054!#A N625 N626
84055!#0 N627 P389 BLD 5 -1 FP BE Pri
84056!#0 N628 P390 MEMBAR
84057!#0 N629 P391 DWST_BINIT 9 0xa7 Int BE Pri
84058!#0 N630 P391 DWST_BINIT 10 0xa8 Int BE Pri
84059!#A N629 N630
84060!#0 N631 P392 MEMBAR
84061!#0 N632 P393 LDD 3 -1 Int BE Pri
84062!#0 N633 P393 LDD 4 -1 Int BE Pri
84063!#A N632 N633
84064!#0 N634 P394 DWLD 18 -1 Int BE Pri
84065!#0 N635 P394 DWLD 19 -1 Int BE Pri
84066!#A N634 N635
84067!#0 N636 P394 CASX 18 -1 N634 0xa9 Int BE Pri
84068!#0 N637 P394 CASX 19 -1 N635 0xaa Int BE Pri
84069!#A N636 N637
84070!#0 N638 P395 DWLD 2 -1 Int BE Pri
84071!#0 N639 P396 MEMBAR
84072!#0 N640 P397 BLD 9 -1 FP BE Pri
84073!#0 N641 P397 BLD 10 -1 FP BE Pri
84074!#A N640 N641
84075!#0 N642 P397 BLD 11 -1 FP BE Pri
84076!#0 N643 P398 MEMBAR
84077!#0 N644 P399 LD 1 -1 Int BE Pri
84078!#0 N645 P400 DWST_BINIT 21 0xab Int BE Pri
84079!#0 N646 P400 DWST_BINIT 22 0xac Int BE Pri
84080!#A N645 N646
84081!#0 N647 P401 MEMBAR
84082!#0 N648 P402 BLD 9 -1 FP BE Pri
84083!#0 N649 P402 BLD 10 -1 FP BE Pri
84084!#A N648 N649
84085!#0 N650 P402 BLD 11 -1 FP BE Pri
84086!#0 N651 P403 MEMBAR
84087!#0 N652 P404 SWAP 20 0xffffffff 0xad Int BE Pri
84088!#0 N653 P405 PREFETCH 6 Int BE Pri
84089!#0 N654 P406 LDD 11 -1 Int BE Pri
84090!#0 N655 P407 MEMBAR
84091!#0 N656 P408 BSTC 18 0x3f80007e FP BE Pri
84092!#0 N657 P408 BSTC 19 0x3f80007f FP BE Pri
84093!#A N656 N657
84094!#0 N658 P408 BSTC 20 0x3f800080 FP BE Pri
84095!#0 N659 P409 MEMBAR
84096!#0 N660 P410 LD 12 -1 Int BE Pri
84097!#0 N661 P411 SWAP 2 0xffffffff 0xae Int BE Pri
84098!#0 N662 P412 LD 17 -1 Int BE Pri
84099!#0 N663 P412 CAS 17 -1 N662 0xaf Int BE Pri
84100!#0 N664 P413 MEMBAR
84101!#0 N665 P414 BSTC 3 0x3f800081 FP BE Pri
84102!#0 N666 P414 BSTC 4 0x3f800082 FP BE Pri
84103!#A N665 N666
84104!#0 N667 P414 BSTC 5 0x3f800083 FP BE Pri
84105!#0 N668 P415 MEMBAR
84106!#0 N669 P416 DWLD 20 -1,0x0 Int BE Pri
84107!#0 N670 P416 CASX 20 -1,0x0 N669 0xb0 Int BE Pri
84108!#0 N671 P417 MEMBAR
84109!#0 N672 P418 BSTC 9 0x3f800084 FP BE Pri
84110!#0 N673 P418 BSTC 10 0x3f800085 FP BE Pri
84111!#A N672 N673
84112!#0 N674 P418 BSTC 11 0x3f800086 FP BE Pri
84113!#0 N675 P419 MEMBAR
84114!#0 N676 P420 LD 19 -1 Int BE Pri
84115!#0 N677 P420 CAS 19 -1 N676 0xb1 Int BE Pri
84116!#0 N678 P421 DWLD 12 -1 Int BE Pri
84117!#0 N679 P421 DWLD 13 -1 Int BE Pri
84118!#A N678 N679
84119!#0 N680 P421 CASX 12 -1 N678 0xb2 Int BE Pri
84120!#0 N681 P421 CASX 13 -1 N679 0xb3 Int BE Pri
84121!#A N680 N681
84122!#0 N682 P422 LDD 9 -1 Int BE Pri
84123!#0 N683 P422 LDD 10 -1 Int BE Pri
84124!#A N682 N683
84125!#0 N684 P423 LD 22 -1 Int BE Pri
84126!#0 N685 P423 CAS 22 -1 N684 0xb4 Int BE Pri
84127!#0 N686 P424 MEMBAR
84128!#0 N687 P425 BLD 6 -1 FP BE Pri
84129!#0 N688 P425 BLD 7 -1 FP BE Pri
84130!#A N687 N688
84131!#0 N689 P425 BLD 8 -1 FP BE Pri
84132!#0 N690 P426 MEMBAR
84133!#0 N691 P427 LD 1 -1 Int BE Pri
84134!#0 N692 P427 CAS 1 -1 N691 0xb5 Int BE Pri
84135!#0 N693 P428 SWAP 15 0xffffffff 0xb6 Int BE Pri
84136!#0 N694 P429 MEMBAR
84137!#0 N695 P430 BSTC 0 0x3f800087 FP BE Pri
84138!#0 N696 P430 BSTC 1 0x3f800088 FP BE Pri
84139!#A N695 N696
84140!#0 N697 P430 BSTC 2 0x3f800089 FP BE Pri
84141!#0 N698 P431 MEMBAR
84142!#0 N699 P432 DWLD 12 -1 Int BE Pri
84143!#0 N700 P432 DWLD 13 -1 Int BE Pri
84144!#A N699 N700
84145!#0 N701 P432 CASX 12 -1 N699 0xb7 Int BE Pri
84146!#0 N702 P432 CASX 13 -1 N700 0xb8 Int BE Pri
84147!#A N701 N702
84148!#0 N703 P433 DWST_BINIT 23 0xb9 Int BE Pri
84149!#0 N704 P434 MEMBAR
84150!#0 N705 P435 ST_BINIT 13 0xba Int BE Pri
84151!#0 N706 P436 MEMBAR
84152!#0 N707 P437 DWST 18 0xbb Int BE Pri
84153!#0 N708 P437 DWST 19 0xbc Int BE Pri
84154!#A N707 N708
84155!#0 N709 P438 REPLACEMENT 8 Int BE Pri
84156!#0 N710 P439 DWST 20 0xbd Int BE Pri
84157!#0 N711 P440 MEMBAR
84158!#0 N712 P441 BLD 21 -1 FP BE Pri
84159!#0 N713 P441 BLD 22 -1 FP BE Pri
84160!#A N712 N713
84161!#0 N714 P441 BLD 23 -1 FP BE Pri
84162!#0 N715 P442 MEMBAR
84163!#0 N716 P443 LD 18 -1 Int BE Pri
84164!#0 N717 P444 DWLD 12 -1 Int BE Pri
84165!#0 N718 P444 DWLD 13 -1 Int BE Pri
84166!#A N717 N718
84167!#0 N719 P444 CASX 12 -1 N717 0xbe Int BE Pri
84168!#0 N720 P444 CASX 13 -1 N718 0xbf Int BE Pri
84169!#A N719 N720
84170!#0 N721 P445 SWAP 19 0xffffffff 0xc0 Int BE Pri
84171!#0 N722 P446 DWLD 12 -1 FP BE Pri
84172!#0 N723 P446 DWLD 13 -1 FP BE Pri
84173!#A N722 N723
84174!#0 N724 P447 LDD 15 -1 Int BE Pri
84175!#0 N725 P447 LDD 16 -1 Int BE Pri
84176!#A N724 N725
84177!#0 N726 P448 LD 7 -1 Int BE Pri
84178!#0 N727 P448 CAS 7 -1 N726 0xc1 Int BE Pri
84179!#0 N728 P449 MEMBAR
84180!#0 N729 P450 BLD 6 -1 FP BE Pri
84181!#0 N730 P450 BLD 7 -1 FP BE Pri
84182!#A N729 N730
84183!#0 N731 P450 BLD 8 -1 FP BE Pri
84184!#0 N732 P451 MEMBAR
84185!#0 N733 P452 DWST 9 0xc2 Int BE Pri
84186!#0 N734 P452 DWST 10 0xc3 Int BE Pri
84187!#A N733 N734
84188!#0 N735 P453 LD 11 -1 Int BE Pri
84189!#0 N736 P453 CAS 11 -1 N735 0xc4 Int BE Pri
84190!#0 N737 P454 DWLD 9 -1 Int BE Pri
84191!#0 N738 P454 DWLD 10 -1 Int BE Pri
84192!#A N737 N738
84193!#0 N739 P455 REPLACEMENT 20 Int BE Pri
84194!#0 N740 P456 DWLD 20 -1 Int BE Pri
84195!#0 N741 P457 DWLD 18 -1 Int BE Pri
84196!#0 N742 P457 DWLD 19 -1 Int BE Pri
84197!#A N741 N742
84198!#0 N743 P458 DWLD 11 -1 Int BE Pri
84199!#0 N744 P459 REPLACEMENT 19 Int BE Pri
84200!#0 N745 P460 SWAP 0 0xffffffff 0xc5 Int BE Pri
84201!#0 N746 P461 DWLD 23 -1,0x0 Int BE Pri
84202!#0 N747 P461 CASX 23 -1,0x0 N746 0xc6 Int BE Pri
84203!#0 N748 P462 DWLD 20 -1 Int LE Pri
84204!#0 N749 P463 LD 18 -1 Int BE Pri
84205!#0 N750 P464 LD 8 -1 Int BE Pri
84206!#0 N751 P464 CAS 8 -1 N750 0xc7 Int BE Pri
84207!#0 N752 P465 ST 9 0x3f80008a FP BE Pri
84208!#0 N753 P466 SWAP 1 0xffffffff 0xc8 Int BE Pri
84209!#0 N754 P467 ST_BINIT 8 0xc9 Int BE Pri
84210!#0 N755 P468 MEMBAR
84211!#0 N756 P469 DWLD 23 -1,0x0 Int BE Pri
84212!#0 N757 P469 CASX 23 -1,0x0 N756 0xca Int BE Pri
84213!#0 N758 P470 LD 11 -1 Int BE Pri
84214!#0 N759 P470 CAS 11 -1 N758 0xcb Int BE Pri
84215!#0 N760 P471 MEMBAR
84216!#0 N761 P472 BST 12 0x3f80008b FP BE Pri
84217!#0 N762 P472 BST 13 0x3f80008c FP BE Pri
84218!#A N761 N762
84219!#0 N763 P472 BST 14 0x3f80008d FP BE Pri
84220!#0 N764 P473 MEMBAR
84221!#0 N765 P474 DWLD 11 -1 Int BE Pri
84222!#0 N766 P475 DWST_BINIT 23 0xcc Int BE Pri
84223!#0 N767 P476 MEMBAR
84224!#0 N768 P477 DWST_BINIT 12 0xcd Int BE Pri
84225!#0 N769 P477 DWST_BINIT 13 0xce Int BE Pri
84226!#A N768 N769
84227!#0 N770 P478 MEMBAR
84228!#0 N771 P479 REPLACEMENT 10 Int BE Pri
84229!#0 N772 P480 ST_BINIT 18 0xcf Int BE Pri
84230!#0 N773 P481 MEMBAR
84231!#0 N774 P482 DWLD 6 -1 Int BE Pri
84232!#0 N775 P482 DWLD 7 -1 Int BE Pri
84233!#A N774 N775
84234!#0 N776 P482 CASX 6 -1 N774 0xd0 Int BE Pri
84235!#0 N777 P482 CASX 7 -1 N775 0xd1 Int BE Pri
84236!#A N776 N777
84237!#0 N778 P483 MEMBAR
84238!#0 N779 P484 BLD 9 -1 FP BE Pri
84239!#0 N780 P484 BLD 10 -1 FP BE Pri
84240!#A N779 N780
84241!#0 N781 P484 BLD 11 -1 FP BE Pri
84242!#0 N782 P485 MEMBAR
84243!#0 N783 P486 REPLACEMENT 14 Int BE Pri
84244!#0 N784 P487 SWAP 9 0xffffffff 0xd2 Int BE Pri
84245!#0 N785 P488 ST 2 0xd3 Int LE Pri
84246!#0 N786 P489 DWLD 14 -1,0x0 Int BE Pri
84247!#0 N787 P489 CASX 14 -1,0x0 N786 0xd4 Int BE Pri
84248!#0 N788 P490 MEMBAR
84249!#0 N789 P491 BST 18 0x3f80008e FP BE Pri
84250!#0 N790 P491 BST 19 0x3f80008f FP BE Pri
84251!#A N789 N790
84252!#0 N791 P491 BST 20 0x3f800090 FP BE Pri
84253!#0 N792 P492 MEMBAR
84254!#0 N793 P493 ST 6 0x3f800091 FP BE Pri
84255!#0 N794 P494 MEMBAR
84256!#0 N795 P495 BSTC 6 0x3f800092 FP BE Pri
84257!#0 N796 P495 BSTC 7 0x3f800093 FP BE Pri
84258!#A N795 N796
84259!#0 N797 P495 BSTC 8 0x3f800094 FP BE Pri
84260!#0 N798 P496 MEMBAR
84261!#0 N799 P497 LD 4 -1 Int BE Pri
84262!#0 N800 P498 DWST 3 0xd5 Int BE Pri
84263!#0 N801 P498 DWST 4 0xd6 Int BE Pri
84264!#A N800 N801
84265!#0 N802 P499 PREFETCH 6 Int BE Pri
84266!#0 N803 P500 ST 0 0xd7 Int BE Pri
84267!#0 N804 P501 LD 13 -1 Int BE Pri
84268!#0 N805 P501 CAS 13 -1 N804 0xd8 Int BE Pri
84269!#0 N806 P502 DWLD 3 -1 Int BE Pri
84270!#0 N807 P502 DWLD 4 -1 Int BE Pri
84271!#A N806 N807
84272!#0 N808 P503 DWST 14 0xd9 Int BE Pri
84273!#0 N809 P504 MEMBAR
84274!#0 N810 P505 BST 3 0x3f800095 FP BE Pri
84275!#0 N811 P505 BST 4 0x3f800096 FP BE Pri
84276!#A N810 N811
84277!#0 N812 P505 BST 5 0x3f800097 FP BE Pri
84278!#0 N813 P506 MEMBAR
84279!#0 N814 P507 LD 16 -1 Int BE Pri
84280!#0 N815 P507 CAS 16 -1 N814 0xda Int BE Pri
84281!#0 N816 P508 MEMBAR
84282!#0 N817 P509 BLD 18 -1 FP BE Pri
84283!#0 N818 P509 BLD 19 -1 FP BE Pri
84284!#A N817 N818
84285!#0 N819 P509 BLD 20 -1 FP BE Pri
84286!#0 N820 P510 MEMBAR
84287!#0 N821 P511 PREFETCH 15 Int BE Pri
84288!#0 N822 P512 MEMBAR
84289!#0 N823 P513 BSTC 15 0x3f800098 FP BE Pri
84290!#0 N824 P513 BSTC 16 0x3f800099 FP BE Pri
84291!#A N823 N824
84292!#0 N825 P513 BSTC 17 0x3f80009a FP BE Pri
84293!#0 N826 P514 MEMBAR
84294!#0 N827 P515 LD 22 -1 Int BE Pri
84295!#0 N828 P515 CAS 22 -1 N827 0xdb Int BE Pri
84296!#0 N829 P516 ST 0 0xdc Int BE Pri
84297!#0 N830 P517 SWAP 6 0xffffffff 0xdd Int LE Pri
84298!#0 N831 P518 SWAP 2 0xffffffff 0xde Int BE Pri
84299!#0 N832 P519 DWLD 0 -1 Int BE Pri
84300!#0 N833 P519 DWLD 1 -1 Int BE Pri
84301!#A N832 N833
84302!#0 N834 P520 MEMBAR
84303!#0 N835 P521 BSTC 18 0x3f80009b FP BE Pri
84304!#0 N836 P521 BSTC 19 0x3f80009c FP BE Pri
84305!#A N835 N836
84306!#0 N837 P521 BSTC 20 0x3f80009d FP BE Pri
84307!#0 N838 P522 MEMBAR
84308!#0 N839 P523 DWST 18 0xdf Int LE Pri
84309!#0 N840 P523 DWST 19 0xe0 Int LE Pri
84310!#A N839 N840
84311!#0 N841 P524 DWLD 21 -1 Int BE Pri
84312!#0 N842 P524 DWLD 22 -1 Int BE Pri
84313!#A N841 N842
84314!#0 N843 P525 DWLD 9 -1 Int BE Pri
84315!#0 N844 P525 DWLD 10 -1 Int BE Pri
84316!#A N843 N844
84317!#0 N845 P526 REPLACEMENT 1 Int BE Pri
84318!#0 N846 P527 DWLD 15 -1 Int BE Pri
84319!#0 N847 P527 DWLD 16 -1 Int BE Pri
84320!#A N846 N847
84321!#0 N848 P527 CASX 15 -1 N846 0xe1 Int BE Pri
84322!#0 N849 P527 CASX 16 -1 N847 0xe2 Int BE Pri
84323!#A N848 N849
84324!#0 N850 P528 ST_BINIT 0 0xe3 Int BE Pri
84325!#0 N851 P529 MEMBAR
84326!#0 N852 P530 LD 6 -1 Int BE Pri
84327!#0 N853 P530 CAS 6 -1 N852 0xe4 Int BE Pri
84328!#0 N854 P531 DWST 12 0xe5 Int LE Pri
84329!#0 N855 P531 DWST 13 0xe6 Int LE Pri
84330!#A N854 N855
84331!#0 N856 P532 DWST 11 0xe7 Int BE Pri
84332!#0 N857 P533 DWLD 15 -1 Int LE Pri
84333!#0 N858 P533 DWLD 16 -1 Int LE Pri
84334!#A N857 N858
84335!#0 N859 P533 CASX 15 -1 N857 0xe8 Int LE Pri
84336!#0 N860 P533 CASX 16 -1 N858 0xe9 Int LE Pri
84337!#A N859 N860
84338!#0 N861 P534 ST 21 0xea Int BE Pri
84339!#0 N862 P535 DWST_BINIT 18 0xeb Int BE Pri
84340!#0 N863 P535 DWST_BINIT 19 0xec Int BE Pri
84341!#A N862 N863
84342!#0 N864 P536 MEMBAR
84343!#0 N865 P537 BST 6 0x3f80009e FP BE Pri
84344!#0 N866 P537 BST 7 0x3f80009f FP BE Pri
84345!#A N865 N866
84346!#0 N867 P537 BST 8 0x3f8000a0 FP BE Pri
84347!#0 N868 P538 MEMBAR
84348!#0 N869 P539 SWAP 4 0xffffffff 0xed Int LE Pri
84349!#0 N870 P540 MEMBAR
84350!#0 N871 P541 BSTC 18 0x3f8000a1 FP BE Pri
84351!#0 N872 P541 BSTC 19 0x3f8000a2 FP BE Pri
84352!#A N871 N872
84353!#0 N873 P541 BSTC 20 0x3f8000a3 FP BE Pri
84354!#0 N874 P542 MEMBAR
84355!#0 N875 P543 LDD 3 -1 Int BE Pri
84356!#0 N876 P543 LDD 4 -1 Int BE Pri
84357!#A N875 N876
84358!#0 N877 P544 SWAP 16 0xffffffff 0xee Int BE Pri
84359!#0 N878 P545 LD 23 -1 Int BE Pri
84360!#0 N879 P545 CAS 23 -1 N878 0xef Int BE Pri
84361!#0 N880 P546 LDD 23 -1 Int BE Pri
84362!#0 N881 P547 REPLACEMENT 21 Int BE Pri
84363!#0 N882 P548 LDD 14 -1 Int BE Pri
84364!#0 N883 P549 MEMBAR
84365!#0 N884 P550 BLD 18 -1 FP BE Pri
84366!#0 N885 P550 BLD 19 -1 FP BE Pri
84367!#A N884 N885
84368!#0 N886 P550 BLD 20 -1 FP BE Pri
84369!#0 N887 P551 MEMBAR
84370!#0 N888 P552 ST_BINIT 7 0xf0 Int BE Pri
84371!#0 N889 P553 MEMBAR
84372!#0 N890 P554 BLD 15 -1 FP BE Pri
84373!#0 N891 P554 BLD 16 -1 FP BE Pri
84374!#A N890 N891
84375!#0 N892 P554 BLD 17 -1 FP BE Pri
84376!#0 N893 P555 MEMBAR
84377!#0 N894 P556 DWST_BINIT 18 0xf1 Int BE Pri
84378!#0 N895 P556 DWST_BINIT 19 0xf2 Int BE Pri
84379!#A N894 N895
84380!#0 N896 P557 MEMBAR
84381!#0 N897 P558 DWST_BINIT 2 0xf3 Int BE Pri
84382!#0 N898 P559 MEMBAR
84383!#0 N899 P560 DWST_BINIT 3 0xf4 Int BE Pri
84384!#0 N900 P560 DWST_BINIT 4 0xf5 Int BE Pri
84385!#A N899 N900
84386!#0 N901 P561 MEMBAR
84387!#0 N902 P562 LDD 12 -1 Int BE Pri
84388!#0 N903 P562 LDD 13 -1 Int BE Pri
84389!#A N902 N903
84390!#0 N904 P563 MEMBAR
84391!#0 N905 P564 BSTC 6 0x3f8000a4 FP BE Pri
84392!#0 N906 P564 BSTC 7 0x3f8000a5 FP BE Pri
84393!#A N905 N906
84394!#0 N907 P564 BSTC 8 0x3f8000a6 FP BE Pri
84395!#0 N908 P565 MEMBAR
84396!#0 N909 P566 ST_BINIT 6 0xf6 Int BE Pri
84397!#0 N910 P567 MEMBAR
84398!#0 N911 P568 SWAP 3 0xffffffff 0xf7 Int BE Pri
84399!#0 N912 P569 DWST 6 0xf8 Int BE Pri
84400!#0 N913 P569 DWST 7 0xf9 Int BE Pri
84401!#A N912 N913
84402!#0 N914 P570 MEMBAR
84403!#0 N915 P571 BST 18 0x3f8000a7 FP BE Pri
84404!#0 N916 P571 BST 19 0x3f8000a8 FP BE Pri
84405!#A N915 N916
84406!#0 N917 P571 BST 20 0x3f8000a9 FP BE Pri
84407!#0 N918 P572 MEMBAR
84408!#0 N919 P573 LD 13 -1 Int BE Pri
84409!#0 N920 P574 DWST_BINIT 3 0xfa Int BE Pri
84410!#0 N921 P574 DWST_BINIT 4 0xfb Int BE Pri
84411!#A N920 N921
84412!#0 N922 P575 MEMBAR
84413!#0 N923 P576 DWST 3 0xfc Int BE Pri
84414!#0 N924 P576 DWST 4 0xfd Int BE Pri
84415!#A N923 N924
84416!#0 N925 P577 MEMBAR
84417!#0 N926 P578 BSTC 6 0x3f8000aa FP BE Pri
84418!#0 N927 P578 BSTC 7 0x3f8000ab FP BE Pri
84419!#A N926 N927
84420!#0 N928 P578 BSTC 8 0x3f8000ac FP BE Pri
84421!#0 N929 P579 MEMBAR
84422!#0 N930 P580 SWAP 6 0xffffffff 0xfe Int BE Pri
84423!#0 N931 P581 MEMBAR
84424!#0 N932 P582 BST 6 0x3f8000ad FP BE Pri
84425!#0 N933 P582 BST 7 0x3f8000ae FP BE Pri
84426!#A N932 N933
84427!#0 N934 P582 BST 8 0x3f8000af FP BE Pri
84428!#0 N935 P583 MEMBAR
84429!#0 N936 P584 LDD 18 -1 Int BE Pri
84430!#0 N937 P584 LDD 19 -1 Int BE Pri
84431!#A N936 N937
84432!#0 N938 P585 ST_BINIT 9 0xff Int BE Pri
84433!#0 N939 P586 MEMBAR
84434!#0 N940 P587 DWST_BINIT 2 0x100 Int BE Pri
84435!#0 N941 P588 MEMBAR
84436!#0 N942 P589 DWST 0 0x101 Int BE Pri
84437!#0 N943 P589 DWST 1 0x102 Int BE Pri
84438!#A N942 N943
84439!#0 N944 P590 ST 2 0x103 Int BE Pri
84440!#0 N945 P591 MEMBAR
84441!#0 N946 P592 BST 15 0x3f8000b0 FP BE Pri
84442!#0 N947 P592 BST 16 0x3f8000b1 FP BE Pri
84443!#A N946 N947
84444!#0 N948 P592 BST 17 0x3f8000b2 FP BE Pri
84445!#0 N949 P593 MEMBAR
84446!#0 N950 P594 ST_BINIT 21 0x104 Int BE Pri
84447!#0 N951 P595 MEMBAR
84448!#0 N952 P596 DWST 12 0x105 Int BE Pri
84449!#0 N953 P596 DWST 13 0x106 Int BE Pri
84450!#A N952 N953
84451!#0 N954 P597 DWLD 3 -1 Int BE Pri
84452!#0 N955 P597 DWLD 4 -1 Int BE Pri
84453!#A N954 N955
84454!#0 N956 P597 CASX 3 -1 N954 0x107 Int BE Pri
84455!#0 N957 P597 CASX 4 -1 N955 0x108 Int BE Pri
84456!#A N956 N957
84457!#0 N958 P598 PREFETCH 7 Int BE Pri
84458!#0 N959 P599 DWLD 9 -1 Int BE Pri
84459!#0 N960 P599 DWLD 10 -1 Int BE Pri
84460!#A N959 N960
84461!#0 N961 P600 DWLD 18 -1 Int BE Pri
84462!#0 N962 P600 DWLD 19 -1 Int BE Pri
84463!#A N961 N962
84464!#0 N963 P600 CASX 18 -1 N961 0x109 Int BE Pri
84465!#0 N964 P600 CASX 19 -1 N962 0x10a Int BE Pri
84466!#A N963 N964
84467!#0 N965 P601 SWAP 12 0xffffffff 0x10b Int BE Pri
84468!#0 N966 P602 DWLD 8 -1 Int BE Pri
84469!#0 N967 P603 MEMBAR
84470!#0 N968 P604 BLD 0 -1 FP BE Pri
84471!#0 N969 P604 BLD 1 -1 FP BE Pri
84472!#A N968 N969
84473!#0 N970 P604 BLD 2 -1 FP BE Pri
84474!#0 N971 P605 MEMBAR
84475!#0 N972 P606 SWAP 7 0xffffffff 0x10c Int BE Pri
84476!#0 N973 P607 ST_BINIT 18 0x10d Int BE Pri
84477!#0 N974 P608 MEMBAR
84478!#0 N975 P609 ST 15 0x10e Int BE Pri
84479!#0 N976 P610 PREFETCH 18 Int BE Pri
84480!#0 N977 P611 PREFETCH 10 Int BE Pri
84481!#0 N978 P612 ST_BINIT 23 0x10f Int BE Pri
84482!#0 N979 P613 MEMBAR
84483!#0 N980 P614 BLD 6 -1 FP BE Pri
84484!#0 N981 P614 BLD 7 -1 FP BE Pri
84485!#A N980 N981
84486!#0 N982 P614 BLD 8 -1 FP BE Pri
84487!#0 N983 P615 MEMBAR
84488!#0 N984 P616 DWLD 9 -1 Int BE Pri
84489!#0 N985 P616 DWLD 10 -1 Int BE Pri
84490!#A N984 N985
84491!#0 N986 P617 DWLD 5 -1,0x0 Int BE Pri
84492!#0 N987 P617 CASX 5 -1,0x0 N986 0x110 Int BE Pri
84493!#0 N988 P618 MEMBAR
84494!#0 N989 P619 BSTC 21 0x3f8000b3 FP BE Pri
84495!#0 N990 P619 BSTC 22 0x3f8000b4 FP BE Pri
84496!#A N989 N990
84497!#0 N991 P619 BSTC 23 0x3f8000b5 FP BE Pri
84498!#0 N992 P620 MEMBAR
84499!#0 N993 P621 ST 20 0x111 Int BE Pri
84500!#0 N994 P622 ST_BINIT 15 0x112 Int BE Pri
84501!#0 N995 P623 MEMBAR
84502!#0 N996 P624 BSTC 21 0x3f8000b6 FP BE Pri
84503!#0 N997 P624 BSTC 22 0x3f8000b7 FP BE Pri
84504!#A N996 N997
84505!#0 N998 P624 BSTC 23 0x3f8000b8 FP BE Pri
84506!#0 N999 P625 MEMBAR
84507!#0 N1000 P626 DWST_BINIT 0 0x113 Int LE Pri
84508!#0 N1001 P626 DWST_BINIT 1 0x114 Int LE Pri
84509!#A N1000 N1001
84510!#0 N1002 P627 MEMBAR
84511!#0 N1003 P628 DWST_BINIT 11 0x115 Int LE Pri
84512!#0 N1004 P629 MEMBAR
84513!#0 N1005 P630 BST 15 0x3f8000b9 FP BE Pri
84514!#0 N1006 P630 BST 16 0x3f8000ba FP BE Pri
84515!#A N1005 N1006
84516!#0 N1007 P630 BST 17 0x3f8000bb FP BE Pri
84517!#0 N1008 P631 MEMBAR
84518!#0 N1009 P632 DWLD 5 -1,0x0 Int BE Pri
84519!#0 N1010 P632 CASX 5 -1,0x0 N1009 0x116 Int BE Pri
84520!#0 N1011 P633 ST 15 0x117 Int BE Pri
84521!#0 N1012 P634 SWAP 3 0xffffffff 0x118 Int BE Pri
84522!#0 N1013 P635 MEMBAR
84523!#0 N1014 P636 BST 21 0x3f8000bc FP BE Pri
84524!#0 N1015 P636 BST 22 0x3f8000bd FP BE Pri
84525!#A N1014 N1015
84526!#0 N1016 P636 BST 23 0x3f8000be FP BE Pri
84527!#0 N1017 P637 MEMBAR
84528!#0 N1018 P638 BST 21 0x3f8000bf FP BE Pri
84529!#0 N1019 P638 BST 22 0x3f8000c0 FP BE Pri
84530!#A N1018 N1019
84531!#0 N1020 P638 BST 23 0x3f8000c1 FP BE Pri
84532!#0 N1021 P639 MEMBAR
84533!#0 N1022 P640 ST 16 0x119 Int BE Pri
84534!#0 N1023 P641 DWLD 3 -1 Int BE Pri
84535!#0 N1024 P641 DWLD 4 -1 Int BE Pri
84536!#A N1023 N1024
84537!#0 N1025 P641 CASX 3 -1 N1023 0x11a Int BE Pri
84538!#0 N1026 P641 CASX 4 -1 N1024 0x11b Int BE Pri
84539!#A N1025 N1026
84540!#0 N1027 P642 DWST_BINIT 15 0x11c Int BE Pri
84541!#0 N1028 P642 DWST_BINIT 16 0x11d Int BE Pri
84542!#A N1027 N1028
84543!#0 N1029 P643 MEMBAR
84544!#0 N1030 P644 DWLD 0 -1 Int BE Pri
84545!#0 N1031 P644 DWLD 1 -1 Int BE Pri
84546!#A N1030 N1031
84547!#0 N1032 P644 CASX 0 -1 N1030 0x11e Int BE Pri
84548!#0 N1033 P644 CASX 1 -1 N1031 0x11f Int BE Pri
84549!#A N1032 N1033
84550!#0 N1034 P645 LDD 3 -1 Int BE Pri
84551!#0 N1035 P645 LDD 4 -1 Int BE Pri
84552!#A N1034 N1035
84553!#0 N1036 P646 PREFETCH 4 Int BE Pri
84554!#0 N1037 P647 DWLD 23 -1,0x0 Int BE Pri
84555!#0 N1038 P647 CASX 23 -1,0x0 N1037 0x120 Int BE Pri
84556!#0 N1039 P648 MEMBAR
84557!#0 N1040 P649 BSTC 3 0x3f8000c2 FP BE Pri
84558!#0 N1041 P649 BSTC 4 0x3f8000c3 FP BE Pri
84559!#A N1040 N1041
84560!#0 N1042 P649 BSTC 5 0x3f8000c4 FP BE Pri
84561!#0 N1043 P650 MEMBAR
84562!#0 N1044 P651 LDD 8 -1 Int BE Pri
84563!#0 N1045 P652 MEMBAR
84564!#0 N1046 P653 BSTC 3 0x3f8000c5 FP BE Pri
84565!#0 N1047 P653 BSTC 4 0x3f8000c6 FP BE Pri
84566!#A N1046 N1047
84567!#0 N1048 P653 BSTC 5 0x3f8000c7 FP BE Pri
84568!#0 N1049 P654 MEMBAR
84569!#0 N1050 P655 BST 9 0x3f8000c8 FP BE Pri
84570!#0 N1051 P655 BST 10 0x3f8000c9 FP BE Pri
84571!#A N1050 N1051
84572!#0 N1052 P655 BST 11 0x3f8000ca FP BE Pri
84573!#0 N1053 P656 MEMBAR
84574!#0 N1054 P657 DWLD 18 -1 Int BE Pri
84575!#0 N1055 P657 DWLD 19 -1 Int BE Pri
84576!#A N1054 N1055
84577!#0 N1056 P657 CASX 18 -1 N1054 0x121 Int BE Pri
84578!#0 N1057 P657 CASX 19 -1 N1055 0x122 Int BE Pri
84579!#A N1056 N1057
84580!#0 N1058 P658 LD 10 -1 Int BE Pri
84581!#0 N1059 P658 CAS 10 -1 N1058 0x123 Int BE Pri
84582!#0 N1060 P659 MEMBAR
84583!#0 N1061 P660 BSTC 9 0x3f8000cb FP BE Pri
84584!#0 N1062 P660 BSTC 10 0x3f8000cc FP BE Pri
84585!#A N1061 N1062
84586!#0 N1063 P660 BSTC 11 0x3f8000cd FP BE Pri
84587!#0 N1064 P661 MEMBAR
84588!#0 N1065 P662 BLD 6 -1 FP BE Pri
84589!#0 N1066 P662 BLD 7 -1 FP BE Pri
84590!#A N1065 N1066
84591!#0 N1067 P662 BLD 8 -1 FP BE Pri
84592!#0 N1068 P663 MEMBAR
84593!#0 N1069 P664 ST_BINIT 8 0x124 Int LE Pri
84594!#0 N1070 P665 MEMBAR
84595!#0 N1071 P666 LDD 21 -1 Int BE Pri
84596!#0 N1072 P666 LDD 22 -1 Int BE Pri
84597!#A N1071 N1072
84598!#0 N1073 P667 SWAP 2 0xffffffff 0x125 Int BE Pri
84599!#0 N1074 P668 MEMBAR
84600!#0 N1075 P669 BST 15 0x3f8000ce FP BE Pri
84601!#0 N1076 P669 BST 16 0x3f8000cf FP BE Pri
84602!#A N1075 N1076
84603!#0 N1077 P669 BST 17 0x3f8000d0 FP BE Pri
84604!#0 N1078 P670 MEMBAR
84605!#0 N1079 P671 PREFETCH 0 Int BE Pri
84606!#0 N1080 P672 SWAP 22 0xffffffff 0x126 Int BE Pri
84607!#0 N1081 P673 DWST 15 0x127 Int BE Pri
84608!#0 N1082 P673 DWST 16 0x128 Int BE Pri
84609!#A N1081 N1082
84610!#0 N1083 P674 LD 11 -1 Int BE Pri
84611!#0 N1084 P675 REPLACEMENT 13 Int BE Pri
84612!#0 N1085 P676 LDD 3 -1 Int BE Pri
84613!#0 N1086 P676 LDD 4 -1 Int BE Pri
84614!#A N1085 N1086
84615!#0 N1087 P677 DWST_BINIT 18 0x129 Int BE Pri
84616!#0 N1088 P677 DWST_BINIT 19 0x12a Int BE Pri
84617!#A N1087 N1088
84618!#0 N1089 P678 MEMBAR
84619!#0 N1090 P679 BST 9 0x3f8000d1 FP BE Pri
84620!#0 N1091 P679 BST 10 0x3f8000d2 FP BE Pri
84621!#A N1090 N1091
84622!#0 N1092 P679 BST 11 0x3f8000d3 FP BE Pri
84623!#0 N1093 P680 MEMBAR
84624!#0 N1094 P681 BLD 6 -1 FP BE Pri
84625!#0 N1095 P681 BLD 7 -1 FP BE Pri
84626!#A N1094 N1095
84627!#0 N1096 P681 BLD 8 -1 FP BE Pri
84628!#0 N1097 P682 MEMBAR
84629!#0 N1098 P683 BLD 9 -1 FP BE Pri
84630!#0 N1099 P683 BLD 10 -1 FP BE Pri
84631!#A N1098 N1099
84632!#0 N1100 P683 BLD 11 -1 FP BE Pri
84633!#0 N1101 P684 MEMBAR
84634!#0 N1102 P685 PREFETCH 17 Int BE Pri
84635!#0 N1103 P686 MEMBAR
84636!#0 N1104 P687 BST 0 0x3f8000d4 FP BE Pri
84637!#0 N1105 P687 BST 1 0x3f8000d5 FP BE Pri
84638!#A N1104 N1105
84639!#0 N1106 P687 BST 2 0x3f8000d6 FP BE Pri
84640!#0 N1107 P688 MEMBAR
84641!#0 N1108 P689 BST 3 0x3f8000d7 FP BE Pri
84642!#0 N1109 P689 BST 4 0x3f8000d8 FP BE Pri
84643!#A N1108 N1109
84644!#0 N1110 P689 BST 5 0x3f8000d9 FP BE Pri
84645!#0 N1111 P690 MEMBAR
84646!#0 N1112 P691 DWLD 11 -1 Int BE Pri
84647!#0 N1113 P692 MEMBAR
84648!#0 N1114 P693 BLD 3 -1 FP BE Pri
84649!#0 N1115 P693 BLD 4 -1 FP BE Pri
84650!#A N1114 N1115
84651!#0 N1116 P693 BLD 5 -1 FP BE Pri
84652!#0 N1117 P694 MEMBAR
84653!#0 N1118 P695 DWST_BINIT 21 0x12b Int BE Pri
84654!#0 N1119 P695 DWST_BINIT 22 0x12c Int BE Pri
84655!#A N1118 N1119
84656!#0 N1120 P696 MEMBAR
84657!#0 N1121 P697 LD 14 -1 Int BE Pri
84658!#0 N1122 P697 CAS 14 -1 N1121 0x12d Int BE Pri
84659!#0 N1123 P698 MEMBAR
84660!#0 N1124 P699 BSTC 15 0x3f8000da FP BE Pri
84661!#0 N1125 P699 BSTC 16 0x3f8000db FP BE Pri
84662!#A N1124 N1125
84663!#0 N1126 P699 BSTC 17 0x3f8000dc FP BE Pri
84664!#0 N1127 P700 MEMBAR
84665!#0 N1128 P701 DWST 20 0x12e Int BE Pri
84666!#0 N1129 P702 DWST 14 0x12f Int BE Pri
84667!#0 N1130 P703 MEMBAR
84668!#0 N1131 P704 BLD 21 -1 FP BE Pri
84669!#0 N1132 P704 BLD 22 -1 FP BE Pri
84670!#A N1131 N1132
84671!#0 N1133 P704 BLD 23 -1 FP BE Pri
84672!#0 N1134 P705 MEMBAR
84673!#0 N1135 P706 PREFETCH 2 Int BE Pri
84674!#0 N1136 P707 LD 3 -1 Int BE Pri
84675!#0 N1137 P708 DWST 12 0x130 Int BE Pri
84676!#0 N1138 P708 DWST 13 0x131 Int BE Pri
84677!#A N1137 N1138
84678!#0 N1139 P709 SWAP 5 0xffffffff 0x132 Int BE Pri
84679!#0 N1140 P710 MEMBAR
84680!#0 N1141 P711 BST 3 0x3f8000dd FP BE Pri
84681!#0 N1142 P711 BST 4 0x3f8000de FP BE Pri
84682!#A N1141 N1142
84683!#0 N1143 P711 BST 5 0x3f8000df FP BE Pri
84684!#0 N1144 P712 MEMBAR
84685!#0 N1145 P713 REPLACEMENT 19 Int BE Pri
84686!#0 N1146 P714 MEMBAR
84687!#0 N1147 P715 BST 21 0x3f8000e0 FP BE Pri
84688!#0 N1148 P715 BST 22 0x3f8000e1 FP BE Pri
84689!#A N1147 N1148
84690!#0 N1149 P715 BST 23 0x3f8000e2 FP BE Pri
84691!#0 N1150 P716 MEMBAR
84692!#0 N1151 P717 LD 18 -1 Int BE Pri
84693!#0 N1152 P718 LDD 12 -1 Int BE Pri
84694!#0 N1153 P718 LDD 13 -1 Int BE Pri
84695!#A N1152 N1153
84696!#0 N1154 P719 ST_BINIT 22 0x133 Int LE Pri
84697!#0 N1155 P720 MEMBAR
84698!#0 N1156 P721 SWAP 13 0xffffffff 0x134 Int BE Pri
84699!#0 N1157 P722 LD 11 -1 Int BE Pri
84700!#0 N1158 P723 DWLD 23 -1 FP BE Pri
84701!#0 N1159 P724 MEMBAR
84702!#0 N1160 P725 BSTC 3 0x3f8000e3 FP BE Pri
84703!#0 N1161 P725 BSTC 4 0x3f8000e4 FP BE Pri
84704!#A N1160 N1161
84705!#0 N1162 P725 BSTC 5 0x3f8000e5 FP BE Pri
84706!#0 N1163 P726 MEMBAR
84707!#0 N1164 P727 SWAP 5 0xffffffff 0x135 Int BE Pri
84708!#0 N1165 P728 LDD 6 -1 Int BE Pri
84709!#0 N1166 P728 LDD 7 -1 Int BE Pri
84710!#A N1165 N1166
84711!#0 N1167 P729 LDD 2 -1 Int BE Pri
84712!#0 N1168 P730 ST_BINIT 22 0x136 Int BE Pri
84713!#0 N1169 P731 MEMBAR
84714!#0 N1170 P732 BST 3 0x3f8000e6 FP BE Pri
84715!#0 N1171 P732 BST 4 0x3f8000e7 FP BE Pri
84716!#A N1170 N1171
84717!#0 N1172 P732 BST 5 0x3f8000e8 FP BE Pri
84718!#0 N1173 P733 MEMBAR
84719!#0 N1174 P734 ST_BINIT 4 0x137 Int BE Pri
84720!#0 N1175 P735 MEMBAR
84721!#0 N1176 P736 LDD 20 -1 Int BE Pri
84722!#0 N1177 P737 MEMBAR
84723!#0 N1178 P738 BSTC 0 0x3f8000e9 FP BE Pri
84724!#0 N1179 P738 BSTC 1 0x3f8000ea FP BE Pri
84725!#A N1178 N1179
84726!#0 N1180 P738 BSTC 2 0x3f8000eb FP BE Pri
84727!#0 N1181 P739 MEMBAR
84728!#0 N1182 P740 DWST 6 0x138 Int BE Pri
84729!#0 N1183 P740 DWST 7 0x139 Int BE Pri
84730!#A N1182 N1183
84731!#0 N1184 P741 LD 20 -1 Int BE Pri
84732!#0 N1185 P741 CAS 20 -1 N1184 0x13a Int BE Pri
84733!#0 N1186 P742 DWST 8 0x13b Int BE Pri
84734!#0 N1187 P743 LDD 12 -1 Int BE Pri
84735!#0 N1188 P743 LDD 13 -1 Int BE Pri
84736!#A N1187 N1188
84737!#0 N1189 P744 LDD 0 -1 Int BE Pri
84738!#0 N1190 P744 LDD 1 -1 Int BE Pri
84739!#A N1189 N1190
84740!#0 N1191 P745 DWST 12 0x13c Int BE Pri
84741!#0 N1192 P745 DWST 13 0x13d Int BE Pri
84742!#A N1191 N1192
84743!#0 N1193 P746 DWST 17 0x13e Int BE Pri
84744!#0 N1194 P747 DWLD 11 -1 Int BE Pri
84745!#0 N1195 P748 SWAP 23 0xffffffff 0x13f Int BE Pri
84746!#0 N1196 P749 LDD 18 -1 Int BE Pri
84747!#0 N1197 P749 LDD 19 -1 Int BE Pri
84748!#A N1196 N1197
84749!#0 N1198 P750 DWST_BINIT 15 0x140 Int BE Pri
84750!#0 N1199 P750 DWST_BINIT 16 0x141 Int BE Pri
84751!#A N1198 N1199
84752!#0 N1200 P751 MEMBAR
84753!#0 N1201 P752 LD 0 -1 Int LE Pri
84754!#0 N1202 P752 CAS 0 -1 N1201 0x142 Int LE Pri
84755!#0 N1203 P753 DWLD 12 -1 Int BE Pri
84756!#0 N1204 P753 DWLD 13 -1 Int BE Pri
84757!#A N1203 N1204
84758!#0 N1205 P753 CASX 12 -1 N1203 0x143 Int BE Pri
84759!#0 N1206 P753 CASX 13 -1 N1204 0x144 Int BE Pri
84760!#A N1205 N1206
84761!#0 N1207 P754 ST_BINIT 7 0x145 Int BE Pri
84762!#0 N1208 P755 MEMBAR
84763!#0 N1209 P756 LD 21 -1 Int BE Pri
84764!#0 N1210 P756 CAS 21 -1 N1209 0x146 Int BE Pri
84765!#0 N1211 P757 LD 13 -1 Int BE Pri
84766!#0 N1212 P758 DWST 15 0x147 Int BE Pri
84767!#0 N1213 P758 DWST 16 0x148 Int BE Pri
84768!#A N1212 N1213
84769!#0 N1214 P759 DWLD 0 -1 Int BE Pri
84770!#0 N1215 P759 DWLD 1 -1 Int BE Pri
84771!#A N1214 N1215
84772!#0 N1216 P760 PREFETCH 13 Int BE Pri
84773!#0 N1217 P761 PREFETCH 16 Int BE Pri
84774!#0 N1218 P762 DWLD 12 -1 Int BE Pri
84775!#0 N1219 P762 DWLD 13 -1 Int BE Pri
84776!#A N1218 N1219
84777!#0 N1220 P762 CASX 12 -1 N1218 0x149 Int BE Pri
84778!#0 N1221 P762 CASX 13 -1 N1219 0x14a Int BE Pri
84779!#A N1220 N1221
84780!#0 N1222 P763 SWAP 15 0xffffffff 0x14b Int BE Pri
84781!#0 N1223 P764 MEMBAR
84782!#0 N1224 P765 BLD 15 -1 FP BE Pri
84783!#0 N1225 P765 BLD 16 -1 FP BE Pri
84784!#A N1224 N1225
84785!#0 N1226 P765 BLD 17 -1 FP BE Pri
84786!#0 N1227 P766 MEMBAR
84787!#0 N1228 P767 BLD 0 -1 FP BE Pri
84788!#0 N1229 P767 BLD 1 -1 FP BE Pri
84789!#A N1228 N1229
84790!#0 N1230 P767 BLD 2 -1 FP BE Pri
84791!#0 N1231 P768 MEMBAR
84792!#0 N1232 P769 ST 6 0x14c Int BE Pri
84793!#0 N1233 P770 LD 0 -1 Int BE Pri
84794!#0 N1234 P771 MEMBAR
84795!#0 N1235 P772 BST 9 0x3f8000ec FP BE Pri
84796!#0 N1236 P772 BST 10 0x3f8000ed FP BE Pri
84797!#A N1235 N1236
84798!#0 N1237 P772 BST 11 0x3f8000ee FP BE Pri
84799!#0 N1238 P773 MEMBAR
84800!#0 N1239 P774 ST 5 0x14d Int BE Pri
84801!#0 N1240 P775 ST_BINIT 0 0x14e Int BE Pri
84802!#0 N1241 P776 MEMBAR
84803!#0 N1242 P777 DWLD 15 -1 Int BE Pri
84804!#0 N1243 P777 DWLD 16 -1 Int BE Pri
84805!#A N1242 N1243
84806!#0 N1244 P777 CASX 15 -1 N1242 0x14f Int BE Pri
84807!#0 N1245 P777 CASX 16 -1 N1243 0x150 Int BE Pri
84808!#A N1244 N1245
84809!#0 N1246 P778 LD 7 -1 Int BE Pri
84810!#0 N1247 P779 SWAP 12 0xffffffff 0x151 Int BE Pri
84811!#0 N1248 P780 SWAP 10 0xffffffff 0x152 Int BE Pri
84812!#0 N1249 P781 ST_BINIT 17 0x153 Int BE Pri
84813!#0 N1250 P782 MEMBAR
84814!#0 N1251 P783 LDD 9 -1 Int BE Pri
84815!#0 N1252 P783 LDD 10 -1 Int BE Pri
84816!#A N1251 N1252
84817!#0 N1253 P784 LD 0 -1 Int BE Pri
84818!#0 N1254 P784 CAS 0 -1 N1253 0x154 Int BE Pri
84819!#0 N1255 P785 DWLD 0 -1 Int BE Pri
84820!#0 N1256 P785 DWLD 1 -1 Int BE Pri
84821!#A N1255 N1256
84822!#0 N1257 P786 MEMBAR
84823!#0 N1258 P787 BSTC 18 0x3f8000ef FP BE Pri
84824!#0 N1259 P787 BSTC 19 0x3f8000f0 FP BE Pri
84825!#A N1258 N1259
84826!#0 N1260 P787 BSTC 20 0x3f8000f1 FP BE Pri
84827!#0 N1261 P788 MEMBAR
84828!#0 N1262 P789 LD 8 -1 Int LE Pri
84829!#0 N1263 P790 SWAP 4 0xffffffff 0x155 Int LE Pri
84830!#0 N1264 P791 SWAP 12 0xffffffff 0x156 Int BE Pri
84831!#0 N1265 P792 LD 7 -1 Int LE Pri
84832!#0 N1266 P793 ST_BINIT 18 0x157 Int BE Pri
84833!#0 N1267 P794 MEMBAR
84834!#0 N1268 P795 LD 13 -1 Int BE Pri
84835!#0 N1269 P796 PREFETCH 11 Int BE Pri
84836!#0 N1270 P797 ST_BINIT 19 0x158 Int BE Pri
84837!#0 N1271 P798 MEMBAR
84838!#0 N1272 P799 DWLD 18 -1 Int BE Pri
84839!#0 N1273 P799 DWLD 19 -1 Int BE Pri
84840!#A N1272 N1273
84841!#0 N1274 P799 CASX 18 -1 N1272 0x159 Int BE Pri
84842!#0 N1275 P799 CASX 19 -1 N1273 0x15a Int BE Pri
84843!#A N1274 N1275
84844!#0 N1276 P800 LDD 21 -1 Int BE Pri
84845!#0 N1277 P800 LDD 22 -1 Int BE Pri
84846!#A N1276 N1277
84847!#0 N1278 P801 LDD 18 -1 Int BE Pri
84848!#0 N1279 P801 LDD 19 -1 Int BE Pri
84849!#A N1278 N1279
84850!#0 N1280 P802 SWAP 1 0xffffffff 0x15b Int BE Pri
84851!#0 N1281 P803 MEMBAR
84852!#0 N1282 P804 BST 6 0x3f8000f2 FP BE Pri
84853!#0 N1283 P804 BST 7 0x3f8000f3 FP BE Pri
84854!#A N1282 N1283
84855!#0 N1284 P804 BST 8 0x3f8000f4 FP BE Pri
84856!#0 N1285 P805 MEMBAR
84857!#0 N1286 P806 ST_BINIT 7 0x15c Int BE Pri
84858!#0 N1287 P807 MEMBAR
84859!#0 N1288 P808 REPLACEMENT 8 Int BE Pri
84860!#0 N1289 P809 LD 16 -1 FP BE Pri
84861!#0 N1290 P810 MEMBAR
84862!#0 N1291 P811 BSTC 12 0x3f8000f5 FP BE Pri
84863!#0 N1292 P811 BSTC 13 0x3f8000f6 FP BE Pri
84864!#A N1291 N1292
84865!#0 N1293 P811 BSTC 14 0x3f8000f7 FP BE Pri
84866!#0 N1294 P812 MEMBAR
84867!#0 N1295 P813 BST 9 0x3f8000f8 FP BE Pri
84868!#0 N1296 P813 BST 10 0x3f8000f9 FP BE Pri
84869!#A N1295 N1296
84870!#0 N1297 P813 BST 11 0x3f8000fa FP BE Pri
84871!#0 N1298 P814 MEMBAR
84872!#0 N1299 P815 DWST_BINIT 12 0x15d Int BE Pri
84873!#0 N1300 P815 DWST_BINIT 13 0x15e Int BE Pri
84874!#A N1299 N1300
84875!#0 N1301 P816 MEMBAR
84876!#0 N1302 P817 DWLD 12 -1 Int BE Pri
84877!#0 N1303 P817 DWLD 13 -1 Int BE Pri
84878!#A N1302 N1303
84879!#0 N1304 P818 DWLD 8 -1,0x0 Int BE Pri
84880!#0 N1305 P818 CASX 8 -1,0x0 N1304 0x15f Int BE Pri
84881!#0 N1306 P819 MEMBAR
84882!#0 N1307 P820 BLD 12 -1 FP BE Pri
84883!#0 N1308 P820 BLD 13 -1 FP BE Pri
84884!#A N1307 N1308
84885!#0 N1309 P820 BLD 14 -1 FP BE Pri
84886!#0 N1310 P821 MEMBAR
84887!#0 N1311 P822 BST 6 0x3f8000fb FP BE Pri
84888!#0 N1312 P822 BST 7 0x3f8000fc FP BE Pri
84889!#A N1311 N1312
84890!#0 N1313 P822 BST 8 0x3f8000fd FP BE Pri
84891!#0 N1314 P823 MEMBAR
84892!#0 N1315 P824 BLD 18 -1 FP BE Pri
84893!#0 N1316 P824 BLD 19 -1 FP BE Pri
84894!#A N1315 N1316
84895!#0 N1317 P824 BLD 20 -1 FP BE Pri
84896!#0 N1318 P825 MEMBAR
84897!#0 N1319 P826 LD 17 -1 Int BE Pri
84898!#0 N1320 P826 CAS 17 -1 N1319 0x160 Int BE Pri
84899!#0 N1321 P827 MEMBAR
84900!#0 N1322 P828 BSTC 21 0x3f8000fe FP BE Pri
84901!#0 N1323 P828 BSTC 22 0x3f8000ff FP BE Pri
84902!#A N1322 N1323
84903!#0 N1324 P828 BSTC 23 0x3f800100 FP BE Pri
84904!#0 N1325 P829 MEMBAR
84905!#0 N1326 P830 BSTC 12 0x3f800101 FP BE Pri
84906!#0 N1327 P830 BSTC 13 0x3f800102 FP BE Pri
84907!#A N1326 N1327
84908!#0 N1328 P830 BSTC 14 0x3f800103 FP BE Pri
84909!#0 N1329 P831 MEMBAR
84910!#0 N1330 P832 DWLD 5 -1 FP BE Pri
84911!#0 N1331 P833 DWST 6 0x161 Int BE Pri
84912!#0 N1332 P833 DWST 7 0x162 Int BE Pri
84913!#A N1331 N1332
84914!#0 N1333 P834 LD 0 -1 Int BE Pri
84915!#0 N1334 P835 DWST 15 0x163 Int BE Pri
84916!#0 N1335 P835 DWST 16 0x164 Int BE Pri
84917!#A N1334 N1335
84918!#0 N1336 P836 MEMBAR
84919!#0 N1337 P837 BSTC 12 0x3f800104 FP BE Pri
84920!#0 N1338 P837 BSTC 13 0x3f800105 FP BE Pri
84921!#A N1337 N1338
84922!#0 N1339 P837 BSTC 14 0x3f800106 FP BE Pri
84923!#0 N1340 P838 MEMBAR
84924!#0 N1341 P839 LD 0 -1 Int BE Pri
84925!#0 N1342 P840 DWST_BINIT 14 0x165 Int BE Pri
84926!#0 N1343 P841 MEMBAR
84927!#0 N1344 P842 DWLD 21 -1 Int BE Pri
84928!#0 N1345 P842 DWLD 22 -1 Int BE Pri
84929!#A N1344 N1345
84930!#0 N1346 P842 CASX 21 -1 N1344 0x166 Int BE Pri
84931!#0 N1347 P842 CASX 22 -1 N1345 0x167 Int BE Pri
84932!#A N1346 N1347
84933!#0 N1348 P843 PREFETCH 6 Int BE Pri
84934!#0 N1349 P844 DWLD 14 -1,0x0 Int BE Pri
84935!#0 N1350 P844 CASX 14 -1,0x0 N1349 0x168 Int BE Pri
84936!#0 N1351 P845 MEMBAR
84937!#0 N1352 P846 BST 6 0x3f800107 FP BE Pri
84938!#0 N1353 P846 BST 7 0x3f800108 FP BE Pri
84939!#A N1352 N1353
84940!#0 N1354 P846 BST 8 0x3f800109 FP BE Pri
84941!#0 N1355 P847 MEMBAR
84942!#0 N1356 P848 BSTC 0 0x3f80010a FP BE Pri
84943!#0 N1357 P848 BSTC 1 0x3f80010b FP BE Pri
84944!#A N1356 N1357
84945!#0 N1358 P848 BSTC 2 0x3f80010c FP BE Pri
84946!#0 N1359 P849 MEMBAR
84947!#0 N1360 P850 SWAP 9 0xffffffff 0x169 Int BE Pri
84948!#0 N1361 P851 MEMBAR
84949!#0 N1362 P852 BST 6 0x3f80010d FP BE Pri
84950!#0 N1363 P852 BST 7 0x3f80010e FP BE Pri
84951!#A N1362 N1363
84952!#0 N1364 P852 BST 8 0x3f80010f FP BE Pri
84953!#0 N1365 P853 MEMBAR
84954!#0 N1366 P854 DWST 6 0x16a Int BE Pri
84955!#0 N1367 P854 DWST 7 0x16b Int BE Pri
84956!#A N1366 N1367
84957!#0 N1368 P855 SWAP 9 0xffffffff 0x16c Int BE Pri
84958!#0 N1369 P856 ST 21 0x16d Int BE Pri
84959!#0 N1370 P857 DWST_BINIT 0 0x16e Int BE Pri
84960!#0 N1371 P857 DWST_BINIT 1 0x16f Int BE Pri
84961!#A N1370 N1371
84962!#0 N1372 P858 MEMBAR
84963!#0 N1373 P859 DWLD 15 -1 Int BE Pri
84964!#0 N1374 P859 DWLD 16 -1 Int BE Pri
84965!#A N1373 N1374
84966!#0 N1375 P860 DWST 9 0x170 Int BE Pri
84967!#0 N1376 P860 DWST 10 0x171 Int BE Pri
84968!#A N1375 N1376
84969!#0 N1377 P861 DWST_BINIT 21 0x172 Int BE Pri
84970!#0 N1378 P861 DWST_BINIT 22 0x173 Int BE Pri
84971!#A N1377 N1378
84972!#0 N1379 P862 MEMBAR
84973!#0 N1380 P863 BLD 9 -1 FP BE Pri
84974!#0 N1381 P863 BLD 10 -1 FP BE Pri
84975!#A N1380 N1381
84976!#0 N1382 P863 BLD 11 -1 FP BE Pri
84977!#0 N1383 P864 MEMBAR
84978!#0 N1384 P865 BST 18 0x3f800110 FP BE Pri
84979!#0 N1385 P865 BST 19 0x3f800111 FP BE Pri
84980!#A N1384 N1385
84981!#0 N1386 P865 BST 20 0x3f800112 FP BE Pri
84982!#0 N1387 P866 MEMBAR
84983!#0 N1388 P867 DWLD 18 -1 FP BE Pri
84984!#0 N1389 P867 DWLD 19 -1 FP BE Pri
84985!#A N1388 N1389
84986!#0 N1390 P868 DWLD 18 -1 Int BE Pri
84987!#0 N1391 P868 DWLD 19 -1 Int BE Pri
84988!#A N1390 N1391
84989!#0 N1392 P868 CASX 18 -1 N1390 0x174 Int BE Pri
84990!#0 N1393 P868 CASX 19 -1 N1391 0x175 Int BE Pri
84991!#A N1392 N1393
84992!#0 N1394 P869 DWLD 3 -1 Int BE Pri
84993!#0 N1395 P869 DWLD 4 -1 Int BE Pri
84994!#A N1394 N1395
84995!#0 N1396 P869 CASX 3 -1 N1394 0x176 Int BE Pri
84996!#0 N1397 P869 CASX 4 -1 N1395 0x177 Int BE Pri
84997!#A N1396 N1397
84998!#0 N1398 P870 LDD 3 -1 Int BE Pri
84999!#0 N1399 P870 LDD 4 -1 Int BE Pri
85000!#A N1398 N1399
85001!#0 N1400 P871 LDD 12 -1 Int BE Pri
85002!#0 N1401 P871 LDD 13 -1 Int BE Pri
85003!#A N1400 N1401
85004!#0 N1402 P872 PREFETCH 8 Int BE Pri
85005!#0 N1403 P873 MEMBAR
85006!#0 N1404 P874 BST 3 0x3f800113 FP BE Pri
85007!#0 N1405 P874 BST 4 0x3f800114 FP BE Pri
85008!#A N1404 N1405
85009!#0 N1406 P874 BST 5 0x3f800115 FP BE Pri
85010!#0 N1407 P875 MEMBAR
85011!#0 N1408 P876 LD 4 -1 Int BE Pri
85012!#0 N1409 P876 CAS 4 -1 N1408 0x178 Int BE Pri
85013!#0 N1410 P877 MEMBAR
85014!#0 N1411 P878 BST 0 0x3f800116 FP BE Pri
85015!#0 N1412 P878 BST 1 0x3f800117 FP BE Pri
85016!#A N1411 N1412
85017!#0 N1413 P878 BST 2 0x3f800118 FP BE Pri
85018!#0 N1414 P879 MEMBAR
85019!#0 N1415 P880 DWST 18 0x179 Int BE Pri
85020!#0 N1416 P880 DWST 19 0x17a Int BE Pri
85021!#A N1415 N1416
85022!#0 N1417 P881 DWST_BINIT 8 0x17b Int BE Pri
85023!#0 N1418 P882 MEMBAR
85024!#0 N1419 P883 DWST_BINIT 18 0x17c Int BE Pri
85025!#0 N1420 P883 DWST_BINIT 19 0x17d Int BE Pri
85026!#A N1419 N1420
85027!#0 N1421 P884 MEMBAR
85028!#0 N1422 P885 ST_BINIT 6 0x17e Int BE Pri
85029!#0 N1423 P886 MEMBAR
85030!#0 N1424 P887 BSTC 12 0x3f800119 FP BE Pri
85031!#0 N1425 P887 BSTC 13 0x3f80011a FP BE Pri
85032!#A N1424 N1425
85033!#0 N1426 P887 BSTC 14 0x3f80011b FP BE Pri
85034!#0 N1427 P888 MEMBAR
85035!#0 N1428 P889 ST 14 0x17f Int BE Pri
85036!#0 N1429 P890 LD 23 -1 Int BE Pri
85037!#0 N1430 P890 CAS 23 -1 N1429 0x180 Int BE Pri
85038!#0 N1431 P891 DWST 21 0x181 Int BE Pri
85039!#0 N1432 P891 DWST 22 0x182 Int BE Pri
85040!#A N1431 N1432
85041!#0 N1433 P892 ST_BINIT 18 0x183 Int BE Pri
85042!#0 N1434 P893 MEMBAR
85043!#0 N1435 P894 DWST 0 0x184 Int BE Pri
85044!#0 N1436 P894 DWST 1 0x185 Int BE Pri
85045!#A N1435 N1436
85046!#0 N1437 P895 MEMBAR
85047!#0 N1438 P896 BLD 3 -1 FP BE Pri
85048!#0 N1439 P896 BLD 4 -1 FP BE Pri
85049!#A N1438 N1439
85050!#0 N1440 P896 BLD 5 -1 FP BE Pri
85051!#0 N1441 P897 MEMBAR
85052!#0 N1442 P898 PREFETCH 0 Int BE Pri
85053!#0 N1443 P899 DWLD 18 -1 FP BE Pri
85054!#0 N1444 P899 DWLD 19 -1 FP BE Pri
85055!#A N1443 N1444
85056!#0 N1445 P900 MEMBAR
85057!#0 N1446 P901 BSTC 0 0x3f80011c FP BE Pri
85058!#0 N1447 P901 BSTC 1 0x3f80011d FP BE Pri
85059!#A N1446 N1447
85060!#0 N1448 P901 BSTC 2 0x3f80011e FP BE Pri
85061!#0 N1449 P902 MEMBAR
85062!#0 N1450 P903 LD 1 -1 Int BE Pri
85063!#0 N1451 P903 CAS 1 -1 N1450 0x186 Int BE Pri
85064!#0 N1452 P904 MEMBAR
85065!#0 N1453 P905 BST 0 0x3f80011f FP BE Pri
85066!#0 N1454 P905 BST 1 0x3f800120 FP BE Pri
85067!#A N1453 N1454
85068!#0 N1455 P905 BST 2 0x3f800121 FP BE Pri
85069!#0 N1456 P906 MEMBAR
85070!#0 N1457 P907 BLD 9 -1 FP BE Pri
85071!#0 N1458 P907 BLD 10 -1 FP BE Pri
85072!#A N1457 N1458
85073!#0 N1459 P907 BLD 11 -1 FP BE Pri
85074!#0 N1460 P908 MEMBAR
85075!#0 N1461 P909 SWAP 16 0xffffffff 0x187 Int BE Pri
85076!#0 N1462 P910 LDD 0 -1 Int BE Pri
85077!#0 N1463 P910 LDD 1 -1 Int BE Pri
85078!#A N1462 N1463
85079!#0 N1464 P911 LD 10 -1 Int BE Pri
85080!#0 N1465 P912 SWAP 9 0xffffffff 0x188 Int BE Pri
85081!#0 N1466 P913 DWLD 0 -1 Int BE Pri
85082!#0 N1467 P913 DWLD 1 -1 Int BE Pri
85083!#A N1466 N1467
85084!#0 N1468 P913 CASX 0 -1 N1466 0x189 Int BE Pri
85085!#0 N1469 P913 CASX 1 -1 N1467 0x18a Int BE Pri
85086!#A N1468 N1469
85087!#0 N1470 P914 ST 23 0x18b Int BE Pri
85088!#0 N1471 P915 DWST 11 0x18c Int BE Pri
85089!#0 N1472 P916 ST 17 0x18d Int BE Pri
85090!#0 N1473 P917 DWLD 18 -1 Int BE Pri
85091!#0 N1474 P917 DWLD 19 -1 Int BE Pri
85092!#A N1473 N1474
85093!#0 N1475 P917 CASX 18 -1 N1473 0x18e Int BE Pri
85094!#0 N1476 P917 CASX 19 -1 N1474 0x18f Int BE Pri
85095!#A N1475 N1476
85096!#0 N1477 P918 ST_BINIT 11 0x190 Int LE Pri
85097!#0 N1478 P919 MEMBAR
85098!#0 N1479 P920 DWLD 20 -1,0x0 Int BE Pri
85099!#0 N1480 P920 CASX 20 -1,0x0 N1479 0x191 Int BE Pri
85100!#0 N1481 P921 DWLD 17 -1 Int BE Pri
85101!#0 N1482 P922 LD 16 -1 Int BE Pri
85102!#0 N1483 P922 CAS 16 -1 N1482 0x192 Int BE Pri
85103!#0 N1484 P923 LD 6 -1 Int BE Pri
85104!#0 N1485 P924 LD 7 -1 Int BE Pri
85105!#0 N1486 P925 DWLD 0 -1 Int BE Pri
85106!#0 N1487 P925 DWLD 1 -1 Int BE Pri
85107!#A N1486 N1487
85108!#0 N1488 P926 MEMBAR
85109!#0 N1489 P927 BLD 12 -1 FP BE Pri
85110!#0 N1490 P927 BLD 13 -1 FP BE Pri
85111!#A N1489 N1490
85112!#0 N1491 P927 BLD 14 -1 FP BE Pri
85113!#0 N1492 P928 MEMBAR
85114!#0 N1493 P929 DWLD 20 -1,0x0 Int BE Pri
85115!#0 N1494 P929 CASX 20 -1,0x0 N1493 0x193 Int BE Pri
85116!#0 N1495 P930 ST_BINIT 20 0x194 Int BE Pri
85117!#0 N1496 P931 MEMBAR
85118!#0 N1497 P932 DWLD 5 -1 Int BE Pri
85119!#0 N1498 P933 ST_BINIT 9 0x195 Int BE Pri
85120!#0 N1499 P934 MEMBAR
85121!#0 N1500 P935 ST_BINIT 0 0x196 Int BE Pri
85122!#0 N1501 P936 MEMBAR
85123!#0 N1502 P937 DWST_BINIT 0 0x197 Int BE Pri
85124!#0 N1503 P937 DWST_BINIT 1 0x198 Int BE Pri
85125!#A N1502 N1503
85126!#0 N1504 P938 MEMBAR
85127!#0 N1505 P939 ST_BINIT 21 0x199 Int BE Pri
85128!#0 N1506 P940 MEMBAR
85129!#0 N1507 P941 PREFETCH 3 Int BE Pri
85130!#0 N1508 P942 MEMBAR
85131!#0 N1509 P943 BLD 0 -1 FP BE Pri
85132!#0 N1510 P943 BLD 1 -1 FP BE Pri
85133!#A N1509 N1510
85134!#0 N1511 P943 BLD 2 -1 FP BE Pri
85135!#0 N1512 P944 MEMBAR
85136!#0 N1513 P945 DWLD 6 -1 Int BE Pri
85137!#0 N1514 P945 DWLD 7 -1 Int BE Pri
85138!#A N1513 N1514
85139!#0 N1515 P945 CASX 6 -1 N1513 0x19a Int BE Pri
85140!#0 N1516 P945 CASX 7 -1 N1514 0x19b Int BE Pri
85141!#A N1515 N1516
85142!#0 N1517 P946 ST_BINIT 9 0x19c Int BE Pri
85143!#0 N1518 P947 MEMBAR
85144!#0 N1519 P948 BLD 9 -1 FP BE Pri
85145!#0 N1520 P948 BLD 10 -1 FP BE Pri
85146!#A N1519 N1520
85147!#0 N1521 P948 BLD 11 -1 FP BE Pri
85148!#0 N1522 P949 MEMBAR
85149!#0 N1523 P950 ST_BINIT 3 0x19d Int BE Pri
85150!#0 N1524 P951 MEMBAR
85151!#0 N1525 P952 PREFETCH 18 Int BE Pri
85152!#0 N1526 P953 DWLD 3 -1 Int BE Pri
85153!#0 N1527 P953 DWLD 4 -1 Int BE Pri
85154!#A N1526 N1527
85155!#0 N1528 P954 ST_BINIT 15 0x19e Int BE Pri
85156!#0 N1529 P955 MEMBAR
85157!#0 N1530 P956 DWST_BINIT 15 0x19f Int BE Pri
85158!#0 N1531 P956 DWST_BINIT 16 0x1a0 Int BE Pri
85159!#A N1530 N1531
85160!#0 N1532 P957 MEMBAR
85161!#0 N1533 P958 ST_BINIT 11 0x1a1 Int BE Pri
85162!#0 N1534 P959 MEMBAR
85163!#0 N1535 P960 DWLD 0 -1 Int BE Pri
85164!#0 N1536 P960 DWLD 1 -1 Int BE Pri
85165!#A N1535 N1536
85166!#0 N1537 P961 LD 1 -1 Int BE Pri
85167!#0 N1538 P962 DWLD 18 -1 Int BE Pri
85168!#0 N1539 P962 DWLD 19 -1 Int BE Pri
85169!#A N1538 N1539
85170!#0 N1540 P962 CASX 18 -1 N1538 0x1a2 Int BE Pri
85171!#0 N1541 P962 CASX 19 -1 N1539 0x1a3 Int BE Pri
85172!#A N1540 N1541
85173!#0 N1542 P963 REPLACEMENT 20 Int BE Pri
85174!#0 N1543 P964 DWLD 9 -1 Int BE Pri
85175!#0 N1544 P964 DWLD 10 -1 Int BE Pri
85176!#A N1543 N1544
85177!#0 N1545 P965 SWAP 9 0xffffffff 0x1a4 Int BE Pri
85178!#0 N1546 P966 ST 13 0x1a5 Int BE Pri
85179!#0 N1547 P967 ST 5 0x1a6 Int BE Pri
85180!#0 N1548 P968 LD 4 -1 Int BE Pri
85181!#0 N1549 P968 CAS 4 -1 N1548 0x1a7 Int BE Pri
85182!#0 N1550 P969 LD 20 -1 Int BE Pri
85183!#0 N1551 P969 CAS 20 -1 N1550 0x1a8 Int BE Pri
85184!#0 N1552 P970 REPLACEMENT 5 Int BE Pri
85185!#0 N1553 P971 DWLD 3 -1 Int BE Pri
85186!#0 N1554 P971 DWLD 4 -1 Int BE Pri
85187!#A N1553 N1554
85188!#0 N1555 P972 LDD 20 -1 Int BE Pri
85189!#0 N1556 P973 ST 18 0x3f800122 FP BE Pri
85190!#0 N1557 P974 PREFETCH 17 Int BE Pri
85191!#0 N1558 P975 SWAP 17 0xffffffff 0x1a9 Int BE Pri
85192!#0 N1559 P976 PREFETCH 20 Int BE Pri
85193!#0 N1560 P977 DWLD 12 -1 Int BE Pri
85194!#0 N1561 P977 DWLD 13 -1 Int BE Pri
85195!#A N1560 N1561
85196!#0 N1562 P978 ST 0 0x1aa Int BE Pri
85197!#0 N1563 P979 DWLD 2 -1 Int BE Pri
85198!#0 N1564 P980 LD 1 -1 Int BE Pri
85199!#0 N1565 P981 MEMBAR
85200!#0 N1566 P982 BST 6 0x3f800123 FP BE Pri
85201!#0 N1567 P982 BST 7 0x3f800124 FP BE Pri
85202!#A N1566 N1567
85203!#0 N1568 P982 BST 8 0x3f800125 FP BE Pri
85204!#0 N1569 P983 MEMBAR
85205!#0 N1570 P984 DWST_BINIT 15 0x1ab Int BE Pri
85206!#0 N1571 P984 DWST_BINIT 16 0x1ac Int BE Pri
85207!#A N1570 N1571
85208!#0 N1572 P985 MEMBAR
85209!#0 N1573 P986 DWST_BINIT 18 0x1ad Int BE Pri
85210!#0 N1574 P986 DWST_BINIT 19 0x1ae Int BE Pri
85211!#A N1573 N1574
85212!#0 N1575 P987 MEMBAR
85213!#0 N1576 P988 DWLD 9 -1 Int BE Pri
85214!#0 N1577 P988 DWLD 10 -1 Int BE Pri
85215!#A N1576 N1577
85216!#0 N1578 P989 DWST 18 0x1af Int BE Pri
85217!#0 N1579 P989 DWST 19 0x1b0 Int BE Pri
85218!#A N1578 N1579
85219!#0 N1580 P990 DWLD 14 -1 Int BE Pri
85220!#0 N1581 P991 LDD 20 -1 Int BE Pri
85221!#0 N1582 P992 MEMBAR
85222!#0 N1583 P993 BSTC 6 0x3f800126 FP BE Pri
85223!#0 N1584 P993 BSTC 7 0x3f800127 FP BE Pri
85224!#A N1583 N1584
85225!#0 N1585 P993 BSTC 8 0x3f800128 FP BE Pri
85226!#0 N1586 P994 MEMBAR
85227!#0 N1587 P995 BLD 9 -1 FP BE Pri
85228!#0 N1588 P995 BLD 10 -1 FP BE Pri
85229!#A N1587 N1588
85230!#0 N1589 P995 BLD 11 -1 FP BE Pri
85231!#0 N1590 P996 MEMBAR
85232!#0 N1591 P997 BSTC 9 0x3f800129 FP BE Pri
85233!#0 N1592 P997 BSTC 10 0x3f80012a FP BE Pri
85234!#A N1591 N1592
85235!#0 N1593 P997 BSTC 11 0x3f80012b FP BE Pri
85236!#0 N1594 P998 MEMBAR
85237!#0 N1595 P999 DWLD 11 -1 Int BE Pri
85238!#0 N1596 P1000 PREFETCH 12 Int BE Pri Loop_exit
85239!#0 N1597 P1001 MEMBAR
85240!#1 N1598 P1002 LD 9 -1 Int BE Pri Loop_entry
85241!#1 N1599 P1003 MEMBAR
85242!#1 N1600 P1004 BLD 21 -1 FP BE Pri
85243!#1 N1601 P1004 BLD 22 -1 FP BE Pri
85244!#A N1600 N1601
85245!#1 N1602 P1004 BLD 23 -1 FP BE Pri
85246!#1 N1603 P1005 MEMBAR
85247!#1 N1604 P1006 LD 9 -1 Int BE Pri
85248!#1 N1605 P1006 CAS 9 -1 N1604 0x800001 Int BE Pri
85249!#1 N1606 P1007 LDD 9 -1 Int BE Pri
85250!#1 N1607 P1007 LDD 10 -1 Int BE Pri
85251!#A N1606 N1607
85252!#1 N1608 P1008 MEMBAR
85253!#1 N1609 P1009 BST 0 0x40000001 FP BE Pri
85254!#1 N1610 P1009 BST 1 0x40000002 FP BE Pri
85255!#A N1609 N1610
85256!#1 N1611 P1009 BST 2 0x40000003 FP BE Pri
85257!#1 N1612 P1010 MEMBAR
85258!#1 N1613 P1011 DWST_BINIT 21 0x800002 Int BE Pri
85259!#1 N1614 P1011 DWST_BINIT 22 0x800003 Int BE Pri
85260!#A N1613 N1614
85261!#1 N1615 P1012 MEMBAR
85262!#1 N1616 P1013 BST 15 0x40000004 FP BE Pri
85263!#1 N1617 P1013 BST 16 0x40000005 FP BE Pri
85264!#A N1616 N1617
85265!#1 N1618 P1013 BST 17 0x40000006 FP BE Pri
85266!#1 N1619 P1014 MEMBAR
85267!#1 N1620 P1015 ST_BINIT 0 0x800004 Int BE Pri
85268!#1 N1621 P1016 MEMBAR
85269!#1 N1622 P1017 ST 0 0x40000007 FP BE Pri
85270!#1 N1623 P1018 PREFETCH 0 Int BE Pri
85271!#1 N1624 P1019 DWLD 2 -1 Int BE Pri
85272!#1 N1625 P1020 SWAP 13 0xffffffff 0x800005 Int LE Pri
85273!#1 N1626 P1021 DWST_BINIT 6 0x800006 Int BE Pri
85274!#1 N1627 P1021 DWST_BINIT 7 0x800007 Int BE Pri
85275!#A N1626 N1627
85276!#1 N1628 P1022 MEMBAR
85277!#1 N1629 P1023 DWLD 6 -1 Int BE Pri
85278!#1 N1630 P1023 DWLD 7 -1 Int BE Pri
85279!#A N1629 N1630
85280!#1 N1631 P1023 CASX 6 -1 N1629 0x800008 Int BE Pri
85281!#1 N1632 P1023 CASX 7 -1 N1630 0x800009 Int BE Pri
85282!#A N1631 N1632
85283!#1 N1633 P1024 LD 8 -1 Int BE Pri
85284!#1 N1634 P1024 CAS 8 -1 N1633 0x80000a Int BE Pri
85285!#1 N1635 P1025 MEMBAR
85286!#1 N1636 P1026 BSTC 6 0x40000008 FP BE Pri
85287!#1 N1637 P1026 BSTC 7 0x40000009 FP BE Pri
85288!#A N1636 N1637
85289!#1 N1638 P1026 BSTC 8 0x4000000a FP BE Pri
85290!#1 N1639 P1027 MEMBAR
85291!#1 N1640 P1028 LD 8 -1 Int BE Pri
85292!#1 N1641 P1029 LD 23 -1 Int LE Pri
85293!#1 N1642 P1030 LDD 23 -1 Int BE Pri
85294!#1 N1643 P1031 ST_BINIT 21 0x80000b Int BE Pri
85295!#1 N1644 P1032 MEMBAR
85296!#1 N1645 P1033 BLD 12 -1 FP BE Pri
85297!#1 N1646 P1033 BLD 13 -1 FP BE Pri
85298!#A N1645 N1646
85299!#1 N1647 P1033 BLD 14 -1 FP BE Pri
85300!#1 N1648 P1034 MEMBAR
85301!#1 N1649 P1035 BSTC 9 0x4000000b FP BE Pri
85302!#1 N1650 P1035 BSTC 10 0x4000000c FP BE Pri
85303!#A N1649 N1650
85304!#1 N1651 P1035 BSTC 11 0x4000000d FP BE Pri
85305!#1 N1652 P1036 MEMBAR
85306!#1 N1653 P1037 DWLD 5 -1,0x0 Int BE Pri
85307!#1 N1654 P1037 CASX 5 -1,0x0 N1653 0x80000c Int BE Pri
85308!#1 N1655 P1038 ST_BINIT 7 0x80000d Int BE Pri
85309!#1 N1656 P1039 MEMBAR
85310!#1 N1657 P1040 DWLD 6 -1 Int BE Pri
85311!#1 N1658 P1040 DWLD 7 -1 Int BE Pri
85312!#A N1657 N1658
85313!#1 N1659 P1040 CASX 6 -1 N1657 0x80000e Int BE Pri
85314!#1 N1660 P1040 CASX 7 -1 N1658 0x80000f Int BE Pri
85315!#A N1659 N1660
85316!#1 N1661 P1041 ST_BINIT 1 0x800010 Int BE Pri
85317!#1 N1662 P1042 MEMBAR
85318!#1 N1663 P1043 LDD 12 -1 Int BE Pri
85319!#1 N1664 P1043 LDD 13 -1 Int BE Pri
85320!#A N1663 N1664
85321!#1 N1665 P1044 REPLACEMENT 7 Int BE Pri
85322!#1 N1666 P1045 DWLD 3 -1 Int BE Pri
85323!#1 N1667 P1045 DWLD 4 -1 Int BE Pri
85324!#A N1666 N1667
85325!#1 N1668 P1045 CASX 3 -1 N1666 0x800011 Int BE Pri
85326!#1 N1669 P1045 CASX 4 -1 N1667 0x800012 Int BE Pri
85327!#A N1668 N1669
85328!#1 N1670 P1046 DWLD 6 -1 Int LE Pri
85329!#1 N1671 P1046 DWLD 7 -1 Int LE Pri
85330!#A N1670 N1671
85331!#1 N1672 P1046 CASX 6 -1 N1670 0x800013 Int LE Pri
85332!#1 N1673 P1046 CASX 7 -1 N1671 0x800014 Int LE Pri
85333!#A N1672 N1673
85334!#1 N1674 P1047 ST_BINIT 11 0x800015 Int LE Pri
85335!#1 N1675 P1048 MEMBAR
85336!#1 N1676 P1049 LDD 9 -1 Int BE Pri
85337!#1 N1677 P1049 LDD 10 -1 Int BE Pri
85338!#A N1676 N1677
85339!#1 N1678 P1050 MEMBAR
85340!#1 N1679 P1051 BSTC 6 0x4000000e FP BE Pri
85341!#1 N1680 P1051 BSTC 7 0x4000000f FP BE Pri
85342!#A N1679 N1680
85343!#1 N1681 P1051 BSTC 8 0x40000010 FP BE Pri
85344!#1 N1682 P1052 MEMBAR
85345!#1 N1683 P1053 PREFETCH 19 Int BE Pri
85346!#1 N1684 P1054 LD 7 -1 Int BE Pri
85347!#1 N1685 P1054 CAS 7 -1 N1684 0x800016 Int BE Pri
85348!#1 N1686 P1055 LDD 12 -1 Int BE Pri
85349!#1 N1687 P1055 LDD 13 -1 Int BE Pri
85350!#A N1686 N1687
85351!#1 N1688 P1056 DWST 6 0x40000011 FP BE Pri
85352!#1 N1689 P1056 DWST 7 0x40000012 FP BE Pri
85353!#A N1688 N1689
85354!#1 N1690 P1057 PREFETCH 8 Int BE Pri
85355!#1 N1691 P1058 DWLD 20 -1,0x0 Int BE Pri
85356!#1 N1692 P1058 CASX 20 -1,0x0 N1691 0x800017 Int BE Pri
85357!#1 N1693 P1059 PREFETCH 3 Int BE Pri
85358!#1 N1694 P1060 DWST 2 0x800018 Int BE Pri
85359!#1 N1695 P1061 SWAP 19 0xffffffff 0x800019 Int BE Pri
85360!#1 N1696 P1062 DWST_BINIT 18 0x80001a Int BE Pri
85361!#1 N1697 P1062 DWST_BINIT 19 0x80001b Int BE Pri
85362!#A N1696 N1697
85363!#1 N1698 P1063 MEMBAR
85364!#1 N1699 P1064 ST_BINIT 18 0x80001c Int BE Pri
85365!#1 N1700 P1065 MEMBAR
85366!#1 N1701 P1066 BLD 9 -1 FP BE Pri
85367!#1 N1702 P1066 BLD 10 -1 FP BE Pri
85368!#A N1701 N1702
85369!#1 N1703 P1066 BLD 11 -1 FP BE Pri
85370!#1 N1704 P1067 MEMBAR
85371!#1 N1705 P1068 LD 17 -1 FP BE Pri
85372!#1 N1706 P1069 ST_BINIT 6 0x80001d Int BE Pri
85373!#1 N1707 P1070 MEMBAR
85374!#1 N1708 P1071 LD 22 -1 Int BE Pri
85375!#1 N1709 P1072 SWAP 7 0xffffffff 0x80001e Int LE Pri
85376!#1 N1710 P1073 ST 17 0x80001f Int BE Pri
85377!#1 N1711 P1074 ST 20 0x800020 Int LE Pri
85378!#1 N1712 P1075 LDD 8 -1 Int BE Pri
85379!#1 N1713 P1076 MEMBAR
85380!#1 N1714 P1077 BSTC 9 0x40000013 FP BE Pri
85381!#1 N1715 P1077 BSTC 10 0x40000014 FP BE Pri
85382!#A N1714 N1715
85383!#1 N1716 P1077 BSTC 11 0x40000015 FP BE Pri
85384!#1 N1717 P1078 MEMBAR
85385!#1 N1718 P1079 DWST 3 0x800021 Int BE Pri
85386!#1 N1719 P1079 DWST 4 0x800022 Int BE Pri
85387!#A N1718 N1719
85388!#1 N1720 P1080 LD 16 -1 Int BE Pri
85389!#1 N1721 P1080 CAS 16 -1 N1720 0x800023 Int BE Pri
85390!#1 N1722 P1081 LD 22 -1 Int BE Pri
85391!#1 N1723 P1082 DWLD 17 -1,0x0 Int BE Pri
85392!#1 N1724 P1082 CASX 17 -1,0x0 N1723 0x800024 Int BE Pri
85393!#1 N1725 P1083 DWST_BINIT 6 0x800025 Int BE Pri
85394!#1 N1726 P1083 DWST_BINIT 7 0x800026 Int BE Pri
85395!#A N1725 N1726
85396!#1 N1727 P1084 MEMBAR
85397!#1 N1728 P1085 LD 9 -1 Int BE Pri
85398!#1 N1729 P1085 CAS 9 -1 N1728 0x800027 Int BE Pri
85399!#1 N1730 P1086 SWAP 19 0xffffffff 0x800028 Int BE Pri
85400!#1 N1731 P1087 MEMBAR
85401!#1 N1732 P1088 BLD 21 -1 FP BE Pri
85402!#1 N1733 P1088 BLD 22 -1 FP BE Pri
85403!#A N1732 N1733
85404!#1 N1734 P1088 BLD 23 -1 FP BE Pri
85405!#1 N1735 P1089 MEMBAR
85406!#1 N1736 P1090 DWLD 17 -1 Int BE Pri
85407!#1 N1737 P1091 LD 19 -1 Int BE Pri
85408!#1 N1738 P1092 MEMBAR
85409!#1 N1739 P1093 BLD 12 -1 FP BE Pri
85410!#1 N1740 P1093 BLD 13 -1 FP BE Pri
85411!#A N1739 N1740
85412!#1 N1741 P1093 BLD 14 -1 FP BE Pri
85413!#1 N1742 P1094 MEMBAR
85414!#1 N1743 P1095 DWLD 18 -1 Int BE Pri
85415!#1 N1744 P1095 DWLD 19 -1 Int BE Pri
85416!#A N1743 N1744
85417!#1 N1745 P1096 MEMBAR
85418!#1 N1746 P1097 BST 3 0x40000016 FP BE Pri
85419!#1 N1747 P1097 BST 4 0x40000017 FP BE Pri
85420!#A N1746 N1747
85421!#1 N1748 P1097 BST 5 0x40000018 FP BE Pri
85422!#1 N1749 P1098 MEMBAR
85423!#1 N1750 P1099 DWLD 23 -1,0x0 Int BE Pri
85424!#1 N1751 P1099 CASX 23 -1,0x0 N1750 0x800029 Int BE Pri
85425!#1 N1752 P1100 LDD 6 -1 Int BE Pri
85426!#1 N1753 P1100 LDD 7 -1 Int BE Pri
85427!#A N1752 N1753
85428!#1 N1754 P1101 PREFETCH 9 Int BE Pri
85429!#1 N1755 P1102 LDD 21 -1 Int BE Pri
85430!#1 N1756 P1102 LDD 22 -1 Int BE Pri
85431!#A N1755 N1756
85432!#1 N1757 P1103 DWLD 6 -1 Int BE Pri
85433!#1 N1758 P1103 DWLD 7 -1 Int BE Pri
85434!#A N1757 N1758
85435!#1 N1759 P1103 CASX 6 -1 N1757 0x80002a Int BE Pri
85436!#1 N1760 P1103 CASX 7 -1 N1758 0x80002b Int BE Pri
85437!#A N1759 N1760
85438!#1 N1761 P1104 DWST_BINIT 8 0x80002c Int BE Pri
85439!#1 N1762 P1105 MEMBAR
85440!#1 N1763 P1106 DWLD 12 -1 Int BE Pri
85441!#1 N1764 P1106 DWLD 13 -1 Int BE Pri
85442!#A N1763 N1764
85443!#1 N1765 P1107 LD 17 -1 Int BE Pri
85444!#1 N1766 P1107 CAS 17 -1 N1765 0x80002d Int BE Pri
85445!#1 N1767 P1108 DWST_BINIT 0 0x80002e Int BE Pri
85446!#1 N1768 P1108 DWST_BINIT 1 0x80002f Int BE Pri
85447!#A N1767 N1768
85448!#1 N1769 P1109 MEMBAR
85449!#1 N1770 P1110 DWLD 9 -1 FP BE Pri
85450!#1 N1771 P1110 DWLD 10 -1 FP BE Pri
85451!#A N1770 N1771
85452!#1 N1772 P1111 DWST_BINIT 12 0x800030 Int BE Pri
85453!#1 N1773 P1111 DWST_BINIT 13 0x800031 Int BE Pri
85454!#A N1772 N1773
85455!#1 N1774 P1112 MEMBAR
85456!#1 N1775 P1113 BST 18 0x40000019 FP BE Pri
85457!#1 N1776 P1113 BST 19 0x4000001a FP BE Pri
85458!#A N1775 N1776
85459!#1 N1777 P1113 BST 20 0x4000001b FP BE Pri
85460!#1 N1778 P1114 MEMBAR
85461!#1 N1779 P1115 DWLD 17 -1 Int BE Pri
85462!#1 N1780 P1116 LD 15 -1 Int BE Pri
85463!#1 N1781 P1116 CAS 15 -1 N1780 0x800032 Int BE Pri
85464!#1 N1782 P1117 DWLD 15 -1 Int BE Pri
85465!#1 N1783 P1117 DWLD 16 -1 Int BE Pri
85466!#A N1782 N1783
85467!#1 N1784 P1117 CASX 15 -1 N1782 0x800033 Int BE Pri
85468!#1 N1785 P1117 CASX 16 -1 N1783 0x800034 Int BE Pri
85469!#A N1784 N1785
85470!#1 N1786 P1118 LD 12 -1 Int BE Pri
85471!#1 N1787 P1119 SWAP 4 0xffffffff 0x800035 Int LE Pri
85472!#1 N1788 P1120 ST 10 0x800036 Int BE Pri
85473!#1 N1789 P1121 LD 0 -1 Int BE Pri
85474!#1 N1790 P1122 LDD 9 -1 Int BE Pri
85475!#1 N1791 P1122 LDD 10 -1 Int BE Pri
85476!#A N1790 N1791
85477!#1 N1792 P1123 MEMBAR
85478!#1 N1793 P1124 BST 6 0x4000001c FP BE Pri
85479!#1 N1794 P1124 BST 7 0x4000001d FP BE Pri
85480!#A N1793 N1794
85481!#1 N1795 P1124 BST 8 0x4000001e FP BE Pri
85482!#1 N1796 P1125 MEMBAR
85483!#1 N1797 P1126 DWLD 15 -1 Int BE Pri
85484!#1 N1798 P1126 DWLD 16 -1 Int BE Pri
85485!#A N1797 N1798
85486!#1 N1799 P1127 LDD 9 -1 Int BE Pri
85487!#1 N1800 P1127 LDD 10 -1 Int BE Pri
85488!#A N1799 N1800
85489!#1 N1801 P1128 MEMBAR
85490!#1 N1802 P1129 BLD 18 -1 FP BE Pri
85491!#1 N1803 P1129 BLD 19 -1 FP BE Pri
85492!#A N1802 N1803
85493!#1 N1804 P1129 BLD 20 -1 FP BE Pri
85494!#1 N1805 P1130 MEMBAR
85495!#1 N1806 P1131 BLD 9 -1 FP BE Pri
85496!#1 N1807 P1131 BLD 10 -1 FP BE Pri
85497!#A N1806 N1807
85498!#1 N1808 P1131 BLD 11 -1 FP BE Pri
85499!#1 N1809 P1132 MEMBAR
85500!#1 N1810 P1133 BLD 6 -1 FP BE Pri
85501!#1 N1811 P1133 BLD 7 -1 FP BE Pri
85502!#A N1810 N1811
85503!#1 N1812 P1133 BLD 8 -1 FP BE Pri
85504!#1 N1813 P1134 MEMBAR
85505!#1 N1814 P1135 SWAP 11 0xffffffff 0x800037 Int BE Pri
85506!#1 N1815 P1136 DWLD 9 -1 Int BE Pri
85507!#1 N1816 P1136 DWLD 10 -1 Int BE Pri
85508!#A N1815 N1816
85509!#1 N1817 P1136 CASX 9 -1 N1815 0x800038 Int BE Pri
85510!#1 N1818 P1136 CASX 10 -1 N1816 0x800039 Int BE Pri
85511!#A N1817 N1818
85512!#1 N1819 P1137 DWST_BINIT 15 0x80003a Int BE Pri
85513!#1 N1820 P1137 DWST_BINIT 16 0x80003b Int BE Pri
85514!#A N1819 N1820
85515!#1 N1821 P1138 MEMBAR
85516!#1 N1822 P1139 DWLD 6 -1 Int BE Pri
85517!#1 N1823 P1139 DWLD 7 -1 Int BE Pri
85518!#A N1822 N1823
85519!#1 N1824 P1140 LD 16 -1 Int BE Pri
85520!#1 N1825 P1141 DWST_BINIT 12 0x80003c Int BE Pri
85521!#1 N1826 P1141 DWST_BINIT 13 0x80003d Int BE Pri
85522!#A N1825 N1826
85523!#1 N1827 P1142 MEMBAR
85524!#1 N1828 P1143 DWST 3 0x80003e Int BE Pri
85525!#1 N1829 P1143 DWST 4 0x80003f Int BE Pri
85526!#A N1828 N1829
85527!#1 N1830 P1144 DWLD 9 -1 Int BE Pri
85528!#1 N1831 P1144 DWLD 10 -1 Int BE Pri
85529!#A N1830 N1831
85530!#1 N1832 P1144 CASX 9 -1 N1830 0x800040 Int BE Pri
85531!#1 N1833 P1144 CASX 10 -1 N1831 0x800041 Int BE Pri
85532!#A N1832 N1833
85533!#1 N1834 P1145 DWLD 15 -1 Int BE Pri
85534!#1 N1835 P1145 DWLD 16 -1 Int BE Pri
85535!#A N1834 N1835
85536!#1 N1836 P1146 LD 4 -1 Int BE Pri
85537!#1 N1837 P1147 DWST 0 0x4000001f FP BE Pri
85538!#1 N1838 P1147 DWST 1 0x40000020 FP BE Pri
85539!#A N1837 N1838
85540!#1 N1839 P1148 LDD 6 -1 Int BE Pri
85541!#1 N1840 P1148 LDD 7 -1 Int BE Pri
85542!#A N1839 N1840
85543!#1 N1841 P1149 DWLD 12 -1 Int BE Pri
85544!#1 N1842 P1149 DWLD 13 -1 Int BE Pri
85545!#A N1841 N1842
85546!#1 N1843 P1149 CASX 12 -1 N1841 0x800042 Int BE Pri
85547!#1 N1844 P1149 CASX 13 -1 N1842 0x800043 Int BE Pri
85548!#A N1843 N1844
85549!#1 N1845 P1150 LDD 12 -1 Int BE Pri
85550!#1 N1846 P1150 LDD 13 -1 Int BE Pri
85551!#A N1845 N1846
85552!#1 N1847 P1151 MEMBAR
85553!#1 N1848 P1152 BSTC 9 0x40000021 FP BE Pri
85554!#1 N1849 P1152 BSTC 10 0x40000022 FP BE Pri
85555!#A N1848 N1849
85556!#1 N1850 P1152 BSTC 11 0x40000023 FP BE Pri
85557!#1 N1851 P1153 MEMBAR
85558!#1 N1852 P1154 BSTC 9 0x40000024 FP BE Pri
85559!#1 N1853 P1154 BSTC 10 0x40000025 FP BE Pri
85560!#A N1852 N1853
85561!#1 N1854 P1154 BSTC 11 0x40000026 FP BE Pri
85562!#1 N1855 P1155 MEMBAR
85563!#1 N1856 P1156 BST 18 0x40000027 FP BE Pri
85564!#1 N1857 P1156 BST 19 0x40000028 FP BE Pri
85565!#A N1856 N1857
85566!#1 N1858 P1156 BST 20 0x40000029 FP BE Pri
85567!#1 N1859 P1157 MEMBAR
85568!#1 N1860 P1158 LDD 6 -1 Int BE Pri
85569!#1 N1861 P1158 LDD 7 -1 Int BE Pri
85570!#A N1860 N1861
85571!#1 N1862 P1159 MEMBAR
85572!#1 N1863 P1160 BST 9 0x4000002a FP BE Pri
85573!#1 N1864 P1160 BST 10 0x4000002b FP BE Pri
85574!#A N1863 N1864
85575!#1 N1865 P1160 BST 11 0x4000002c FP BE Pri
85576!#1 N1866 P1161 MEMBAR
85577!#1 N1867 P1162 BST 12 0x4000002d FP BE Pri
85578!#1 N1868 P1162 BST 13 0x4000002e FP BE Pri
85579!#A N1867 N1868
85580!#1 N1869 P1162 BST 14 0x4000002f FP BE Pri
85581!#1 N1870 P1163 MEMBAR
85582!#1 N1871 P1164 BST 6 0x40000030 FP BE Pri
85583!#1 N1872 P1164 BST 7 0x40000031 FP BE Pri
85584!#A N1871 N1872
85585!#1 N1873 P1164 BST 8 0x40000032 FP BE Pri
85586!#1 N1874 P1165 MEMBAR
85587!#1 N1875 P1166 DWST_BINIT 18 0x800044 Int BE Pri
85588!#1 N1876 P1166 DWST_BINIT 19 0x800045 Int BE Pri
85589!#A N1875 N1876
85590!#1 N1877 P1167 MEMBAR
85591!#1 N1878 P1168 DWLD 23 -1 FP BE Pri
85592!#1 N1879 P1169 DWLD 15 -1 Int BE Pri
85593!#1 N1880 P1169 DWLD 16 -1 Int BE Pri
85594!#A N1879 N1880
85595!#1 N1881 P1169 CASX 15 -1 N1879 0x800046 Int BE Pri
85596!#1 N1882 P1169 CASX 16 -1 N1880 0x800047 Int BE Pri
85597!#A N1881 N1882
85598!#1 N1883 P1170 DWST 8 0x40000033 FP BE Pri
85599!#1 N1884 P1171 ST 2 0x800048 Int BE Pri
85600!#1 N1885 P1172 MEMBAR
85601!#1 N1886 P1173 BST 6 0x40000034 FP BE Pri
85602!#1 N1887 P1173 BST 7 0x40000035 FP BE Pri
85603!#A N1886 N1887
85604!#1 N1888 P1173 BST 8 0x40000036 FP BE Pri
85605!#1 N1889 P1174 MEMBAR
85606!#1 N1890 P1175 ST_BINIT 10 0x800049 Int BE Pri
85607!#1 N1891 P1176 MEMBAR
85608!#1 N1892 P1177 SWAP 17 0xffffffff 0x80004a Int BE Pri
85609!#1 N1893 P1178 MEMBAR
85610!#1 N1894 P1179 BSTC 9 0x40000037 FP BE Pri
85611!#1 N1895 P1179 BSTC 10 0x40000038 FP BE Pri
85612!#A N1894 N1895
85613!#1 N1896 P1179 BSTC 11 0x40000039 FP BE Pri
85614!#1 N1897 P1180 MEMBAR
85615!#1 N1898 P1181 DWST 9 0x80004b Int BE Pri
85616!#1 N1899 P1181 DWST 10 0x80004c Int BE Pri
85617!#A N1898 N1899
85618!#1 N1900 P1182 PREFETCH 5 Int BE Pri
85619!#1 N1901 P1183 DWLD 11 -1,0x0 Int BE Pri
85620!#1 N1902 P1183 CASX 11 -1,0x0 N1901 0x80004d Int BE Pri
85621!#1 N1903 P1184 LD 20 -1 Int BE Pri
85622!#1 N1904 P1185 DWST_BINIT 14 0x80004e Int BE Pri
85623!#1 N1905 P1186 MEMBAR
85624!#1 N1906 P1187 PREFETCH 18 Int BE Pri
85625!#1 N1907 P1188 LD 4 -1 Int BE Pri
85626!#1 N1908 P1188 CAS 4 -1 N1907 0x80004f Int BE Pri
85627!#1 N1909 P1189 MEMBAR
85628!#1 N1910 P1190 BLD 18 -1 FP BE Pri
85629!#1 N1911 P1190 BLD 19 -1 FP BE Pri
85630!#A N1910 N1911
85631!#1 N1912 P1190 BLD 20 -1 FP BE Pri
85632!#1 N1913 P1191 MEMBAR
85633!#1 N1914 P1192 BLD 3 -1 FP BE Pri
85634!#1 N1915 P1192 BLD 4 -1 FP BE Pri
85635!#A N1914 N1915
85636!#1 N1916 P1192 BLD 5 -1 FP BE Pri
85637!#1 N1917 P1193 MEMBAR
85638!#1 N1918 P1194 LD 2 -1 FP BE Pri
85639!#1 N1919 P1195 REPLACEMENT 13 Int BE Pri
85640!#1 N1920 P1196 LD 22 -1 Int BE Pri
85641!#1 N1921 P1197 LD 20 -1 Int BE Pri
85642!#1 N1922 P1197 CAS 20 -1 N1921 0x800050 Int BE Pri
85643!#1 N1923 P1198 SWAP 21 0xffffffff 0x800051 Int BE Pri
85644!#1 N1924 P1199 ST 13 0x800052 Int BE Pri
85645!#1 N1925 P1200 DWST_BINIT 8 0x800053 Int BE Pri
85646!#1 N1926 P1201 MEMBAR
85647!#1 N1927 P1202 PREFETCH 0 Int BE Pri
85648!#1 N1928 P1203 SWAP 23 0xffffffff 0x800054 Int BE Pri
85649!#1 N1929 P1204 SWAP 4 0xffffffff 0x800055 Int BE Pri
85650!#1 N1930 P1205 DWLD 5 -1,0x0 Int BE Pri
85651!#1 N1931 P1205 CASX 5 -1,0x0 N1930 0x800056 Int BE Pri
85652!#1 N1932 P1206 MEMBAR
85653!#1 N1933 P1207 BSTC 9 0x4000003a FP BE Pri
85654!#1 N1934 P1207 BSTC 10 0x4000003b FP BE Pri
85655!#A N1933 N1934
85656!#1 N1935 P1207 BSTC 11 0x4000003c FP BE Pri
85657!#1 N1936 P1208 MEMBAR
85658!#1 N1937 P1209 BST 15 0x4000003d FP BE Pri
85659!#1 N1938 P1209 BST 16 0x4000003e FP BE Pri
85660!#A N1937 N1938
85661!#1 N1939 P1209 BST 17 0x4000003f FP BE Pri
85662!#1 N1940 P1210 MEMBAR
85663!#1 N1941 P1211 DWST 18 0x800057 Int BE Pri
85664!#1 N1942 P1211 DWST 19 0x800058 Int BE Pri
85665!#A N1941 N1942
85666!#1 N1943 P1212 DWST_BINIT 20 0x800059 Int BE Pri
85667!#1 N1944 P1213 MEMBAR
85668!#1 N1945 P1214 DWLD 3 -1 Int BE Pri
85669!#1 N1946 P1214 DWLD 4 -1 Int BE Pri
85670!#A N1945 N1946
85671!#1 N1947 P1215 LD 17 -1 Int BE Pri
85672!#1 N1948 P1215 CAS 17 -1 N1947 0x80005a Int BE Pri
85673!#1 N1949 P1216 DWST_BINIT 9 0x80005b Int BE Pri
85674!#1 N1950 P1216 DWST_BINIT 10 0x80005c Int BE Pri
85675!#A N1949 N1950
85676!#1 N1951 P1217 MEMBAR
85677!#1 N1952 P1218 BST 21 0x40000040 FP BE Pri
85678!#1 N1953 P1218 BST 22 0x40000041 FP BE Pri
85679!#A N1952 N1953
85680!#1 N1954 P1218 BST 23 0x40000042 FP BE Pri
85681!#1 N1955 P1219 MEMBAR
85682!#1 N1956 P1220 DWST 12 0x80005d Int BE Pri
85683!#1 N1957 P1220 DWST 13 0x80005e Int BE Pri
85684!#A N1956 N1957
85685!#1 N1958 P1221 MEMBAR
85686!#1 N1959 P1222 BST 6 0x40000043 FP BE Pri
85687!#1 N1960 P1222 BST 7 0x40000044 FP BE Pri
85688!#A N1959 N1960
85689!#1 N1961 P1222 BST 8 0x40000045 FP BE Pri
85690!#1 N1962 P1223 MEMBAR
85691!#1 N1963 P1224 PREFETCH 13 Int BE Pri
85692!#1 N1964 P1225 REPLACEMENT 20 Int BE Pri
85693!#1 N1965 P1226 ST 6 0x80005f Int BE Pri
85694!#1 N1966 P1227 SWAP 15 0xffffffff 0x800060 Int BE Pri
85695!#1 N1967 P1228 ST 1 0x800061 Int BE Pri
85696!#1 N1968 P1229 REPLACEMENT 21 Int BE Pri
85697!#1 N1969 P1230 SWAP 20 0xffffffff 0x800062 Int BE Pri
85698!#1 N1970 P1231 LD 13 -1 Int LE Pri
85699!#1 N1971 P1232 MEMBAR
85700!#1 N1972 P1233 BST 6 0x40000046 FP BE Pri
85701!#1 N1973 P1233 BST 7 0x40000047 FP BE Pri
85702!#A N1972 N1973
85703!#1 N1974 P1233 BST 8 0x40000048 FP BE Pri
85704!#1 N1975 P1234 MEMBAR
85705!#1 N1976 P1235 DWST_BINIT 0 0x800063 Int BE Pri
85706!#1 N1977 P1235 DWST_BINIT 1 0x800064 Int BE Pri
85707!#A N1976 N1977
85708!#1 N1978 P1236 MEMBAR
85709!#1 N1979 P1237 PREFETCH 22 Int LE Pri
85710!#1 N1980 P1238 MEMBAR
85711!#1 N1981 P1239 BLD 0 -1 FP BE Pri
85712!#1 N1982 P1239 BLD 1 -1 FP BE Pri
85713!#A N1981 N1982
85714!#1 N1983 P1239 BLD 2 -1 FP BE Pri
85715!#1 N1984 P1240 MEMBAR
85716!#1 N1985 P1241 ST 21 0x800065 Int BE Pri
85717!#1 N1986 P1242 DWST_BINIT 0 0x800066 Int BE Pri
85718!#1 N1987 P1242 DWST_BINIT 1 0x800067 Int BE Pri
85719!#A N1986 N1987
85720!#1 N1988 P1243 MEMBAR
85721!#1 N1989 P1244 DWST_BINIT 15 0x800068 Int BE Pri
85722!#1 N1990 P1244 DWST_BINIT 16 0x800069 Int BE Pri
85723!#A N1989 N1990
85724!#1 N1991 P1245 MEMBAR
85725!#1 N1992 P1246 PREFETCH 23 Int BE Pri
85726!#1 N1993 P1247 MEMBAR
85727!#1 N1994 P1248 BST 3 0x40000049 FP BE Pri
85728!#1 N1995 P1248 BST 4 0x4000004a FP BE Pri
85729!#A N1994 N1995
85730!#1 N1996 P1248 BST 5 0x4000004b FP BE Pri
85731!#1 N1997 P1249 MEMBAR
85732!#1 N1998 P1250 SWAP 21 0xffffffff 0x80006a Int BE Pri
85733!#1 N1999 P1251 LD 23 -1 Int BE Pri
85734!#1 N2000 P1252 ST 23 0x80006b Int BE Pri
85735!#1 N2001 P1253 REPLACEMENT 19 Int BE Pri
85736!#1 N2002 P1254 LDD 18 -1 Int BE Pri
85737!#1 N2003 P1254 LDD 19 -1 Int BE Pri
85738!#A N2002 N2003
85739!#1 N2004 P1255 ST_BINIT 11 0x80006c Int BE Pri
85740!#1 N2005 P1256 MEMBAR
85741!#1 N2006 P1257 LD 22 -1 Int BE Pri
85742!#1 N2007 P1257 CAS 22 -1 N2006 0x80006d Int BE Pri
85743!#1 N2008 P1258 ST 17 0x4000004c FP BE Pri
85744!#1 N2009 P1259 PREFETCH 13 Int BE Pri
85745!#1 N2010 P1260 ST 8 0x80006e Int BE Pri
85746!#1 N2011 P1261 LD 15 -1 Int BE Pri
85747!#1 N2012 P1261 CAS 15 -1 N2011 0x80006f Int BE Pri
85748!#1 N2013 P1262 DWLD 14 -1 Int BE Pri
85749!#1 N2014 P1263 DWST 6 0x800070 Int BE Pri
85750!#1 N2015 P1263 DWST 7 0x800071 Int BE Pri
85751!#A N2014 N2015
85752!#1 N2016 P1264 LDD 9 -1 Int BE Pri
85753!#1 N2017 P1264 LDD 10 -1 Int BE Pri
85754!#A N2016 N2017
85755!#1 N2018 P1265 DWLD 12 -1 Int BE Pri
85756!#1 N2019 P1265 DWLD 13 -1 Int BE Pri
85757!#A N2018 N2019
85758!#1 N2020 P1265 CASX 12 -1 N2018 0x800072 Int BE Pri
85759!#1 N2021 P1265 CASX 13 -1 N2019 0x800073 Int BE Pri
85760!#A N2020 N2021
85761!#1 N2022 P1266 REPLACEMENT 22 Int BE Pri
85762!#1 N2023 P1267 PREFETCH 7 Int BE Pri
85763!#1 N2024 P1268 LDD 9 -1 Int BE Pri
85764!#1 N2025 P1268 LDD 10 -1 Int BE Pri
85765!#A N2024 N2025
85766!#1 N2026 P1269 SWAP 23 0xffffffff 0x800074 Int BE Pri
85767!#1 N2027 P1270 SWAP 15 0xffffffff 0x800075 Int BE Pri
85768!#1 N2028 P1271 DWLD 18 -1 Int BE Pri
85769!#1 N2029 P1271 DWLD 19 -1 Int BE Pri
85770!#A N2028 N2029
85771!#1 N2030 P1272 SWAP 12 0xffffffff 0x800076 Int BE Pri
85772!#1 N2031 P1273 DWST 3 0x800077 Int BE Pri
85773!#1 N2032 P1273 DWST 4 0x800078 Int BE Pri
85774!#A N2031 N2032
85775!#1 N2033 P1274 DWST 0 0x800079 Int BE Pri
85776!#1 N2034 P1274 DWST 1 0x80007a Int BE Pri
85777!#A N2033 N2034
85778!#1 N2035 P1275 LD 15 -1 Int BE Pri
85779!#1 N2036 P1275 CAS 15 -1 N2035 0x80007b Int BE Pri
85780!#1 N2037 P1276 LDD 8 -1 Int BE Pri
85781!#1 N2038 P1277 MEMBAR
85782!#1 N2039 P1278 BSTC 6 0x4000004d FP BE Pri
85783!#1 N2040 P1278 BSTC 7 0x4000004e FP BE Pri
85784!#A N2039 N2040
85785!#1 N2041 P1278 BSTC 8 0x4000004f FP BE Pri
85786!#1 N2042 P1279 MEMBAR
85787!#1 N2043 P1280 LD 20 -1 Int BE Pri
85788!#1 N2044 P1281 MEMBAR
85789!#1 N2045 P1282 BST 21 0x40000050 FP BE Pri
85790!#1 N2046 P1282 BST 22 0x40000051 FP BE Pri
85791!#A N2045 N2046
85792!#1 N2047 P1282 BST 23 0x40000052 FP BE Pri
85793!#1 N2048 P1283 MEMBAR
85794!#1 N2049 P1284 BST 21 0x40000053 FP BE Pri
85795!#1 N2050 P1284 BST 22 0x40000054 FP BE Pri
85796!#A N2049 N2050
85797!#1 N2051 P1284 BST 23 0x40000055 FP BE Pri
85798!#1 N2052 P1285 MEMBAR
85799!#1 N2053 P1286 BSTC 6 0x40000056 FP BE Pri
85800!#1 N2054 P1286 BSTC 7 0x40000057 FP BE Pri
85801!#A N2053 N2054
85802!#1 N2055 P1286 BSTC 8 0x40000058 FP BE Pri
85803!#1 N2056 P1287 MEMBAR
85804!#1 N2057 P1288 BLD 18 -1 FP BE Pri
85805!#1 N2058 P1288 BLD 19 -1 FP BE Pri
85806!#A N2057 N2058
85807!#1 N2059 P1288 BLD 20 -1 FP BE Pri
85808!#1 N2060 P1289 MEMBAR
85809!#1 N2061 P1290 BSTC 6 0x40000059 FP BE Pri
85810!#1 N2062 P1290 BSTC 7 0x4000005a FP BE Pri
85811!#A N2061 N2062
85812!#1 N2063 P1290 BSTC 8 0x4000005b FP BE Pri
85813!#1 N2064 P1291 MEMBAR
85814!#1 N2065 P1292 ST_BINIT 21 0x80007c Int BE Pri
85815!#1 N2066 P1293 MEMBAR
85816!#1 N2067 P1294 ST_BINIT 23 0x80007d Int BE Pri
85817!#1 N2068 P1295 MEMBAR
85818!#1 N2069 P1296 BSTC 9 0x4000005c FP BE Pri
85819!#1 N2070 P1296 BSTC 10 0x4000005d FP BE Pri
85820!#A N2069 N2070
85821!#1 N2071 P1296 BSTC 11 0x4000005e FP BE Pri
85822!#1 N2072 P1297 MEMBAR
85823!#1 N2073 P1298 LDD 12 -1 Int BE Pri
85824!#1 N2074 P1298 LDD 13 -1 Int BE Pri
85825!#A N2073 N2074
85826!#1 N2075 P1299 LD 17 -1 Int BE Pri
85827!#1 N2076 P1299 CAS 17 -1 N2075 0x80007e Int BE Pri
85828!#1 N2077 P1300 DWLD 6 -1 Int BE Pri
85829!#1 N2078 P1300 DWLD 7 -1 Int BE Pri
85830!#A N2077 N2078
85831!#1 N2079 P1301 DWLD 21 -1 Int BE Pri
85832!#1 N2080 P1301 DWLD 22 -1 Int BE Pri
85833!#A N2079 N2080
85834!#1 N2081 P1301 CASX 21 -1 N2079 0x80007f Int BE Pri
85835!#1 N2082 P1301 CASX 22 -1 N2080 0x800080 Int BE Pri
85836!#A N2081 N2082
85837!#1 N2083 P1302 MEMBAR
85838!#1 N2084 P1303 BSTC 0 0x4000005f FP BE Pri
85839!#1 N2085 P1303 BSTC 1 0x40000060 FP BE Pri
85840!#A N2084 N2085
85841!#1 N2086 P1303 BSTC 2 0x40000061 FP BE Pri
85842!#1 N2087 P1304 MEMBAR
85843!#1 N2088 P1305 PREFETCH 5 Int BE Pri
85844!#1 N2089 P1306 LDD 9 -1 Int BE Pri
85845!#1 N2090 P1306 LDD 10 -1 Int BE Pri
85846!#A N2089 N2090
85847!#1 N2091 P1307 LD 16 -1 Int BE Pri
85848!#1 N2092 P1307 CAS 16 -1 N2091 0x800081 Int BE Pri
85849!#1 N2093 P1308 DWLD 9 -1 Int BE Pri
85850!#1 N2094 P1308 DWLD 10 -1 Int BE Pri
85851!#A N2093 N2094
85852!#1 N2095 P1309 MEMBAR
85853!#1 N2096 P1310 BLD 0 -1 FP BE Pri
85854!#1 N2097 P1310 BLD 1 -1 FP BE Pri
85855!#A N2096 N2097
85856!#1 N2098 P1310 BLD 2 -1 FP BE Pri
85857!#1 N2099 P1311 MEMBAR
85858!#1 N2100 P1312 ST_BINIT 2 0x800082 Int BE Pri
85859!#1 N2101 P1313 MEMBAR
85860!#1 N2102 P1314 DWST_BINIT 20 0x800083 Int BE Pri
85861!#1 N2103 P1315 MEMBAR
85862!#1 N2104 P1316 DWST 14 0x800084 Int BE Pri
85863!#1 N2105 P1317 LDD 15 -1 Int BE Pri
85864!#1 N2106 P1317 LDD 16 -1 Int BE Pri
85865!#A N2105 N2106
85866!#1 N2107 P1318 MEMBAR
85867!#1 N2108 P1319 BSTC 18 0x40000062 FP BE Pri
85868!#1 N2109 P1319 BSTC 19 0x40000063 FP BE Pri
85869!#A N2108 N2109
85870!#1 N2110 P1319 BSTC 20 0x40000064 FP BE Pri
85871!#1 N2111 P1320 MEMBAR
85872!#1 N2112 P1321 BLD 3 -1 FP BE Pri
85873!#1 N2113 P1321 BLD 4 -1 FP BE Pri
85874!#A N2112 N2113
85875!#1 N2114 P1321 BLD 5 -1 FP BE Pri
85876!#1 N2115 P1322 MEMBAR
85877!#1 N2116 P1323 BSTC 15 0x40000065 FP BE Pri
85878!#1 N2117 P1323 BSTC 16 0x40000066 FP BE Pri
85879!#A N2116 N2117
85880!#1 N2118 P1323 BSTC 17 0x40000067 FP BE Pri
85881!#1 N2119 P1324 MEMBAR
85882!#1 N2120 P1325 BLD 15 -1 FP BE Pri
85883!#1 N2121 P1325 BLD 16 -1 FP BE Pri
85884!#A N2120 N2121
85885!#1 N2122 P1325 BLD 17 -1 FP BE Pri
85886!#1 N2123 P1326 MEMBAR
85887!#1 N2124 P1327 ST_BINIT 1 0x800085 Int BE Pri
85888!#1 N2125 P1328 MEMBAR
85889!#1 N2126 P1329 DWST 14 0x800086 Int BE Pri
85890!#1 N2127 P1330 DWLD 3 -1 Int BE Pri
85891!#1 N2128 P1330 DWLD 4 -1 Int BE Pri
85892!#A N2127 N2128
85893!#1 N2129 P1330 CASX 3 -1 N2127 0x800087 Int BE Pri
85894!#1 N2130 P1330 CASX 4 -1 N2128 0x800088 Int BE Pri
85895!#A N2129 N2130
85896!#1 N2131 P1331 ST 21 0x800089 Int BE Pri
85897!#1 N2132 P1332 LD 21 -1 Int BE Pri
85898!#1 N2133 P1332 CAS 21 -1 N2132 0x80008a Int BE Pri
85899!#1 N2134 P1333 SWAP 11 0xffffffff 0x80008b Int BE Pri
85900!#1 N2135 P1334 DWLD 11 -1 FP BE Pri
85901!#1 N2136 P1335 LD 3 -1 Int BE Pri
85902!#1 N2137 P1336 REPLACEMENT 15 Int BE Pri
85903!#1 N2138 P1337 LD 8 -1 Int BE Pri
85904!#1 N2139 P1337 CAS 8 -1 N2138 0x80008c Int BE Pri
85905!#1 N2140 P1338 DWST_BINIT 15 0x80008d Int BE Pri
85906!#1 N2141 P1338 DWST_BINIT 16 0x80008e Int BE Pri
85907!#A N2140 N2141
85908!#1 N2142 P1339 MEMBAR
85909!#1 N2143 P1340 DWST 5 0x40000068 FP BE Pri
85910!#1 N2144 P1341 SWAP 17 0xffffffff 0x80008f Int BE Pri
85911!#1 N2145 P1342 DWST_BINIT 21 0x800090 Int BE Pri
85912!#1 N2146 P1342 DWST_BINIT 22 0x800091 Int BE Pri
85913!#A N2145 N2146
85914!#1 N2147 P1343 MEMBAR
85915!#1 N2148 P1344 LD 11 -1 Int BE Pri
85916!#1 N2149 P1345 MEMBAR
85917!#1 N2150 P1346 BLD 9 -1 FP BE Pri
85918!#1 N2151 P1346 BLD 10 -1 FP BE Pri
85919!#A N2150 N2151
85920!#1 N2152 P1346 BLD 11 -1 FP BE Pri
85921!#1 N2153 P1347 MEMBAR
85922!#1 N2154 P1348 LD 0 -1 Int BE Pri
85923!#1 N2155 P1349 LDD 6 -1 Int BE Pri
85924!#1 N2156 P1349 LDD 7 -1 Int BE Pri
85925!#A N2155 N2156
85926!#1 N2157 P1350 LD 2 -1 Int BE Pri
85927!#1 N2158 P1350 CAS 2 -1 N2157 0x800092 Int BE Pri
85928!#1 N2159 P1351 MEMBAR
85929!#1 N2160 P1352 BSTC 18 0x40000069 FP BE Pri
85930!#1 N2161 P1352 BSTC 19 0x4000006a FP BE Pri
85931!#A N2160 N2161
85932!#1 N2162 P1352 BSTC 20 0x4000006b FP BE Pri
85933!#1 N2163 P1353 MEMBAR
85934!#1 N2164 P1354 SWAP 15 0xffffffff 0x800093 Int BE Pri
85935!#1 N2165 P1355 SWAP 23 0xffffffff 0x800094 Int BE Pri
85936!#1 N2166 P1356 DWLD 8 -1 Int BE Pri
85937!#1 N2167 P1357 PREFETCH 10 Int BE Pri
85938!#1 N2168 P1358 MEMBAR
85939!#1 N2169 P1359 BST 12 0x4000006c FP BE Pri
85940!#1 N2170 P1359 BST 13 0x4000006d FP BE Pri
85941!#A N2169 N2170
85942!#1 N2171 P1359 BST 14 0x4000006e FP BE Pri
85943!#1 N2172 P1360 MEMBAR
85944!#1 N2173 P1361 LDD 21 -1 Int LE Pri
85945!#1 N2174 P1361 LDD 22 -1 Int LE Pri
85946!#A N2173 N2174
85947!#1 N2175 P1362 ST 6 0x800095 Int BE Pri
85948!#1 N2176 P1363 PREFETCH 3 Int BE Pri
85949!#1 N2177 P1364 DWST_BINIT 15 0x800096 Int BE Pri
85950!#1 N2178 P1364 DWST_BINIT 16 0x800097 Int BE Pri
85951!#A N2177 N2178
85952!#1 N2179 P1365 MEMBAR
85953!#1 N2180 P1366 DWLD 3 -1 Int BE Pri
85954!#1 N2181 P1366 DWLD 4 -1 Int BE Pri
85955!#A N2180 N2181
85956!#1 N2182 P1367 LD 1 -1 Int BE Pri
85957!#1 N2183 P1367 CAS 1 -1 N2182 0x800098 Int BE Pri
85958!#1 N2184 P1368 DWLD 15 -1 FP BE Pri
85959!#1 N2185 P1368 DWLD 16 -1 FP BE Pri
85960!#A N2184 N2185
85961!#1 N2186 P1369 ST_BINIT 11 0x800099 Int BE Pri
85962!#1 N2187 P1370 MEMBAR
85963!#1 N2188 P1371 BST 12 0x4000006f FP BE Pri
85964!#1 N2189 P1371 BST 13 0x40000070 FP BE Pri
85965!#A N2188 N2189
85966!#1 N2190 P1371 BST 14 0x40000071 FP BE Pri
85967!#1 N2191 P1372 MEMBAR
85968!#1 N2192 P1373 LD 6 -1 Int BE Pri
85969!#1 N2193 P1373 CAS 6 -1 N2192 0x80009a Int BE Pri
85970!#1 N2194 P1374 SWAP 15 0xffffffff 0x80009b Int BE Pri
85971!#1 N2195 P1375 REPLACEMENT 23 Int BE Pri
85972!#1 N2196 P1376 ST_BINIT 22 0x80009c Int BE Pri
85973!#1 N2197 P1377 MEMBAR
85974!#1 N2198 P1378 DWST_BINIT 21 0x80009d Int BE Pri
85975!#1 N2199 P1378 DWST_BINIT 22 0x80009e Int BE Pri
85976!#A N2198 N2199
85977!#1 N2200 P1379 MEMBAR
85978!#1 N2201 P1380 DWLD 9 -1 Int BE Pri
85979!#1 N2202 P1380 DWLD 10 -1 Int BE Pri
85980!#A N2201 N2202
85981!#1 N2203 P1381 ST 0 0x80009f Int BE Pri
85982!#1 N2204 P1382 ST_BINIT 22 0x8000a0 Int BE Pri
85983!#1 N2205 P1383 MEMBAR
85984!#1 N2206 P1384 ST 18 0x8000a1 Int BE Pri
85985!#1 N2207 P1385 MEMBAR
85986!#1 N2208 P1386 BSTC 0 0x40000072 FP BE Pri
85987!#1 N2209 P1386 BSTC 1 0x40000073 FP BE Pri
85988!#A N2208 N2209
85989!#1 N2210 P1386 BSTC 2 0x40000074 FP BE Pri
85990!#1 N2211 P1387 MEMBAR
85991!#1 N2212 P1388 ST 12 0x8000a2 Int BE Pri
85992!#1 N2213 P1389 MEMBAR
85993!#1 N2214 P1390 BST 0 0x40000075 FP BE Pri
85994!#1 N2215 P1390 BST 1 0x40000076 FP BE Pri
85995!#A N2214 N2215
85996!#1 N2216 P1390 BST 2 0x40000077 FP BE Pri
85997!#1 N2217 P1391 MEMBAR
85998!#1 N2218 P1392 LD 2 -1 Int BE Pri
85999!#1 N2219 P1393 LD 15 -1 Int BE Pri
86000!#1 N2220 P1393 CAS 15 -1 N2219 0x8000a3 Int BE Pri
86001!#1 N2221 P1394 LD 12 -1 Int BE Pri
86002!#1 N2222 P1395 MEMBAR
86003!#1 N2223 P1396 BLD 6 -1 FP BE Pri
86004!#1 N2224 P1396 BLD 7 -1 FP BE Pri
86005!#A N2223 N2224
86006!#1 N2225 P1396 BLD 8 -1 FP BE Pri
86007!#1 N2226 P1397 MEMBAR
86008!#1 N2227 P1398 LDD 6 -1 Int BE Pri
86009!#1 N2228 P1398 LDD 7 -1 Int BE Pri
86010!#A N2227 N2228
86011!#1 N2229 P1399 MEMBAR
86012!#1 N2230 P1400 BLD 21 -1 FP BE Pri
86013!#1 N2231 P1400 BLD 22 -1 FP BE Pri
86014!#A N2230 N2231
86015!#1 N2232 P1400 BLD 23 -1 FP BE Pri
86016!#1 N2233 P1401 MEMBAR
86017!#1 N2234 P1402 SWAP 10 0xffffffff 0x8000a4 Int BE Pri
86018!#1 N2235 P1403 LDD 18 -1 Int BE Pri
86019!#1 N2236 P1403 LDD 19 -1 Int BE Pri
86020!#A N2235 N2236
86021!#1 N2237 P1404 LD 6 -1 Int BE Pri
86022!#1 N2238 P1404 CAS 6 -1 N2237 0x8000a5 Int BE Pri
86023!#1 N2239 P1405 DWST_BINIT 0 0x8000a6 Int BE Pri
86024!#1 N2240 P1405 DWST_BINIT 1 0x8000a7 Int BE Pri
86025!#A N2239 N2240
86026!#1 N2241 P1406 MEMBAR
86027!#1 N2242 P1407 PREFETCH 1 Int BE Pri
86028!#1 N2243 P1408 ST 16 0x8000a8 Int BE Pri
86029!#1 N2244 P1409 DWST 3 0x8000a9 Int BE Pri
86030!#1 N2245 P1409 DWST 4 0x8000aa Int BE Pri
86031!#A N2244 N2245
86032!#1 N2246 P1410 MEMBAR
86033!#1 N2247 P1411 BLD 21 -1 FP BE Pri
86034!#1 N2248 P1411 BLD 22 -1 FP BE Pri
86035!#A N2247 N2248
86036!#1 N2249 P1411 BLD 23 -1 FP BE Pri
86037!#1 N2250 P1412 MEMBAR
86038!#1 N2251 P1413 DWST 6 0x8000ab Int BE Pri
86039!#1 N2252 P1413 DWST 7 0x8000ac Int BE Pri
86040!#A N2251 N2252
86041!#1 N2253 P1414 SWAP 18 0xffffffff 0x8000ad Int BE Pri
86042!#1 N2254 P1415 ST 1 0x8000ae Int BE Pri
86043!#1 N2255 P1416 ST 12 0x40000078 FP BE Pri
86044!#1 N2256 P1417 ST 22 0x8000af Int BE Pri
86045!#1 N2257 P1418 PREFETCH 10 Int BE Pri
86046!#1 N2258 P1419 DWLD 0 -1 Int BE Pri
86047!#1 N2259 P1419 DWLD 1 -1 Int BE Pri
86048!#A N2258 N2259
86049!#1 N2260 P1420 LD 14 -1 Int BE Pri
86050!#1 N2261 P1420 CAS 14 -1 N2260 0x8000b0 Int BE Pri
86051!#1 N2262 P1421 MEMBAR
86052!#1 N2263 P1422 BSTC 6 0x40000079 FP BE Pri
86053!#1 N2264 P1422 BSTC 7 0x4000007a FP BE Pri
86054!#A N2263 N2264
86055!#1 N2265 P1422 BSTC 8 0x4000007b FP BE Pri
86056!#1 N2266 P1423 MEMBAR
86057!#1 N2267 P1424 LD 9 -1 Int BE Pri
86058!#1 N2268 P1424 CAS 9 -1 N2267 0x8000b1 Int BE Pri
86059!#1 N2269 P1425 MEMBAR
86060!#1 N2270 P1426 BST 12 0x4000007c FP BE Pri
86061!#1 N2271 P1426 BST 13 0x4000007d FP BE Pri
86062!#A N2270 N2271
86063!#1 N2272 P1426 BST 14 0x4000007e FP BE Pri
86064!#1 N2273 P1427 MEMBAR
86065!#1 N2274 P1428 ST_BINIT 17 0x8000b2 Int BE Pri
86066!#1 N2275 P1429 MEMBAR
86067!#1 N2276 P1430 DWLD 18 -1 Int BE Pri
86068!#1 N2277 P1430 DWLD 19 -1 Int BE Pri
86069!#A N2276 N2277
86070!#1 N2278 P1431 DWLD 11 -1,0x0 Int BE Pri
86071!#1 N2279 P1431 CASX 11 -1,0x0 N2278 0x8000b3 Int BE Pri
86072!#1 N2280 P1432 DWLD 9 -1 FP BE Pri
86073!#1 N2281 P1432 DWLD 10 -1 FP BE Pri
86074!#A N2280 N2281
86075!#1 N2282 P1433 MEMBAR
86076!#1 N2283 P1434 BST 9 0x4000007f FP BE Pri
86077!#1 N2284 P1434 BST 10 0x40000080 FP BE Pri
86078!#A N2283 N2284
86079!#1 N2285 P1434 BST 11 0x40000081 FP BE Pri
86080!#1 N2286 P1435 MEMBAR
86081!#1 N2287 P1436 SWAP 4 0xffffffff 0x8000b4 Int BE Pri
86082!#1 N2288 P1437 DWLD 0 -1 Int BE Pri
86083!#1 N2289 P1437 DWLD 1 -1 Int BE Pri
86084!#A N2288 N2289
86085!#1 N2290 P1438 ST 17 0x8000b5 Int BE Pri
86086!#1 N2291 P1439 REPLACEMENT 18 Int BE Pri
86087!#1 N2292 P1440 MEMBAR
86088!#1 N2293 P1441 BLD 9 -1 FP BE Pri
86089!#1 N2294 P1441 BLD 10 -1 FP BE Pri
86090!#A N2293 N2294
86091!#1 N2295 P1441 BLD 11 -1 FP BE Pri
86092!#1 N2296 P1442 MEMBAR
86093!#1 N2297 P1443 BSTC 21 0x40000082 FP BE Pri
86094!#1 N2298 P1443 BSTC 22 0x40000083 FP BE Pri
86095!#A N2297 N2298
86096!#1 N2299 P1443 BSTC 23 0x40000084 FP BE Pri
86097!#1 N2300 P1444 MEMBAR
86098!#1 N2301 P1445 BST 18 0x40000085 FP BE Pri
86099!#1 N2302 P1445 BST 19 0x40000086 FP BE Pri
86100!#A N2301 N2302
86101!#1 N2303 P1445 BST 20 0x40000087 FP BE Pri
86102!#1 N2304 P1446 MEMBAR
86103!#1 N2305 P1447 PREFETCH 14 Int BE Pri
86104!#1 N2306 P1448 PREFETCH 17 Int BE Pri
86105!#1 N2307 P1449 LDD 0 -1 Int BE Pri
86106!#1 N2308 P1449 LDD 1 -1 Int BE Pri
86107!#A N2307 N2308
86108!#1 N2309 P1450 DWST_BINIT 3 0x8000b6 Int BE Pri
86109!#1 N2310 P1450 DWST_BINIT 4 0x8000b7 Int BE Pri
86110!#A N2309 N2310
86111!#1 N2311 P1451 MEMBAR
86112!#1 N2312 P1452 BST 6 0x40000088 FP BE Pri
86113!#1 N2313 P1452 BST 7 0x40000089 FP BE Pri
86114!#A N2312 N2313
86115!#1 N2314 P1452 BST 8 0x4000008a FP BE Pri
86116!#1 N2315 P1453 MEMBAR
86117!#1 N2316 P1454 SWAP 9 0xffffffff 0x8000b8 Int BE Pri
86118!#1 N2317 P1455 REPLACEMENT 1 Int BE Pri
86119!#1 N2318 P1456 MEMBAR
86120!#1 N2319 P1457 BST 3 0x4000008b FP BE Pri
86121!#1 N2320 P1457 BST 4 0x4000008c FP BE Pri
86122!#A N2319 N2320
86123!#1 N2321 P1457 BST 5 0x4000008d FP BE Pri
86124!#1 N2322 P1458 MEMBAR
86125!#1 N2323 P1459 BST 0 0x4000008e FP BE Pri
86126!#1 N2324 P1459 BST 1 0x4000008f FP BE Pri
86127!#A N2323 N2324
86128!#1 N2325 P1459 BST 2 0x40000090 FP BE Pri
86129!#1 N2326 P1460 MEMBAR
86130!#1 N2327 P1461 LD 6 -1 Int BE Pri
86131!#1 N2328 P1462 MEMBAR
86132!#1 N2329 P1463 BST 12 0x40000091 FP BE Pri
86133!#1 N2330 P1463 BST 13 0x40000092 FP BE Pri
86134!#A N2329 N2330
86135!#1 N2331 P1463 BST 14 0x40000093 FP BE Pri
86136!#1 N2332 P1464 MEMBAR
86137!#1 N2333 P1465 DWST 9 0x40000094 FP BE Pri
86138!#1 N2334 P1465 DWST 10 0x40000095 FP BE Pri
86139!#A N2333 N2334
86140!#1 N2335 P1466 MEMBAR
86141!#1 N2336 P1467 BST 3 0x40000096 FP BE Pri
86142!#1 N2337 P1467 BST 4 0x40000097 FP BE Pri
86143!#A N2336 N2337
86144!#1 N2338 P1467 BST 5 0x40000098 FP BE Pri
86145!#1 N2339 P1468 MEMBAR
86146!#1 N2340 P1469 PREFETCH 5 Int BE Pri
86147!#1 N2341 P1470 LD 16 -1 FP BE Pri
86148!#1 N2342 P1471 SWAP 15 0xffffffff 0x8000b9 Int BE Pri
86149!#1 N2343 P1472 SWAP 18 0xffffffff 0x8000ba Int BE Pri
86150!#1 N2344 P1473 DWLD 17 -1,0x0 Int BE Pri
86151!#1 N2345 P1473 CASX 17 -1,0x0 N2344 0x8000bb Int BE Pri
86152!#1 N2346 P1474 SWAP 14 0xffffffff 0x8000bc Int BE Pri
86153!#1 N2347 P1475 DWLD 9 -1 Int BE Pri
86154!#1 N2348 P1475 DWLD 10 -1 Int BE Pri
86155!#A N2347 N2348
86156!#1 N2349 P1476 DWST 6 0x8000bd Int BE Pri
86157!#1 N2350 P1476 DWST 7 0x8000be Int BE Pri
86158!#A N2349 N2350
86159!#1 N2351 P1477 DWST_BINIT 18 0x8000bf Int BE Pri
86160!#1 N2352 P1477 DWST_BINIT 19 0x8000c0 Int BE Pri
86161!#A N2351 N2352
86162!#1 N2353 P1478 MEMBAR
86163!#1 N2354 P1479 BLD 6 -1 FP BE Pri
86164!#1 N2355 P1479 BLD 7 -1 FP BE Pri
86165!#A N2354 N2355
86166!#1 N2356 P1479 BLD 8 -1 FP BE Pri
86167!#1 N2357 P1480 MEMBAR
86168!#1 N2358 P1481 DWLD 17 -1,0x0 Int LE Pri
86169!#1 N2359 P1481 CASX 17 -1,0x0 N2358 0x8000c1 Int LE Pri
86170!#1 N2360 P1482 REPLACEMENT 3 Int BE Pri
86171!#1 N2361 P1483 ST 10 0x40000099 FP BE Pri
86172!#1 N2362 P1484 MEMBAR
86173!#1 N2363 P1485 BLD 15 -1 FP BE Pri
86174!#1 N2364 P1485 BLD 16 -1 FP BE Pri
86175!#A N2363 N2364
86176!#1 N2365 P1485 BLD 17 -1 FP BE Pri
86177!#1 N2366 P1486 MEMBAR
86178!#1 N2367 P1487 DWLD 6 -1 Int BE Pri
86179!#1 N2368 P1487 DWLD 7 -1 Int BE Pri
86180!#A N2367 N2368
86181!#1 N2369 P1487 CASX 6 -1 N2367 0x8000c2 Int BE Pri
86182!#1 N2370 P1487 CASX 7 -1 N2368 0x8000c3 Int BE Pri
86183!#A N2369 N2370
86184!#1 N2371 P1488 ST_BINIT 6 0x8000c4 Int BE Pri
86185!#1 N2372 P1489 MEMBAR
86186!#1 N2373 P1490 DWST_BINIT 12 0x8000c5 Int BE Pri
86187!#1 N2374 P1490 DWST_BINIT 13 0x8000c6 Int BE Pri
86188!#A N2373 N2374
86189!#1 N2375 P1491 MEMBAR
86190!#1 N2376 P1492 REPLACEMENT 18 Int BE Pri
86191!#1 N2377 P1493 DWLD 8 -1 Int BE Pri
86192!#1 N2378 P1494 MEMBAR
86193!#1 N2379 P1495 BSTC 18 0x4000009a FP BE Pri
86194!#1 N2380 P1495 BSTC 19 0x4000009b FP BE Pri
86195!#A N2379 N2380
86196!#1 N2381 P1495 BSTC 20 0x4000009c FP BE Pri
86197!#1 N2382 P1496 MEMBAR
86198!#1 N2383 P1497 ST 19 0x8000c7 Int BE Pri
86199!#1 N2384 P1498 ST 12 0x8000c8 Int BE Pri
86200!#1 N2385 P1499 DWLD 5 -1,0x0 Int BE Pri
86201!#1 N2386 P1499 CASX 5 -1,0x0 N2385 0x8000c9 Int BE Pri
86202!#1 N2387 P1500 REPLACEMENT 11 Int BE Pri
86203!#1 N2388 P1501 MEMBAR
86204!#1 N2389 P1502 BST 0 0x4000009d FP BE Pri
86205!#1 N2390 P1502 BST 1 0x4000009e FP BE Pri
86206!#A N2389 N2390
86207!#1 N2391 P1502 BST 2 0x4000009f FP BE Pri
86208!#1 N2392 P1503 MEMBAR
86209!#1 N2393 P1504 SWAP 3 0xffffffff 0x8000ca Int BE Pri
86210!#1 N2394 P1505 ST_BINIT 10 0x8000cb Int BE Pri
86211!#1 N2395 P1506 MEMBAR
86212!#1 N2396 P1507 LDD 15 -1 Int BE Pri
86213!#1 N2397 P1507 LDD 16 -1 Int BE Pri
86214!#A N2396 N2397
86215!#1 N2398 P1508 DWLD 5 -1 Int BE Pri
86216!#1 N2399 P1509 DWLD 14 -1 Int BE Pri
86217!#1 N2400 P1510 REPLACEMENT 12 Int BE Pri
86218!#1 N2401 P1511 ST 15 0x8000cc Int BE Pri
86219!#1 N2402 P1512 LD 3 -1 Int BE Pri
86220!#1 N2403 P1513 PREFETCH 3 Int BE Pri
86221!#1 N2404 P1514 MEMBAR
86222!#1 N2405 P1515 BSTC 0 0x400000a0 FP BE Pri
86223!#1 N2406 P1515 BSTC 1 0x400000a1 FP BE Pri
86224!#A N2405 N2406
86225!#1 N2407 P1515 BSTC 2 0x400000a2 FP BE Pri
86226!#1 N2408 P1516 MEMBAR
86227!#1 N2409 P1517 BSTC 12 0x400000a3 FP BE Pri
86228!#1 N2410 P1517 BSTC 13 0x400000a4 FP BE Pri
86229!#A N2409 N2410
86230!#1 N2411 P1517 BSTC 14 0x400000a5 FP BE Pri
86231!#1 N2412 P1518 MEMBAR
86232!#1 N2413 P1519 BSTC 3 0x400000a6 FP BE Pri
86233!#1 N2414 P1519 BSTC 4 0x400000a7 FP BE Pri
86234!#A N2413 N2414
86235!#1 N2415 P1519 BSTC 5 0x400000a8 FP BE Pri
86236!#1 N2416 P1520 MEMBAR
86237!#1 N2417 P1521 ST 2 0x400000a9 FP BE Pri
86238!#1 N2418 P1522 MEMBAR
86239!#1 N2419 P1523 BLD 9 -1 FP BE Pri
86240!#1 N2420 P1523 BLD 10 -1 FP BE Pri
86241!#A N2419 N2420
86242!#1 N2421 P1523 BLD 11 -1 FP BE Pri
86243!#1 N2422 P1524 MEMBAR
86244!#1 N2423 P1525 ST 21 0x8000cd Int BE Pri
86245!#1 N2424 P1526 LDD 12 -1 Int BE Pri
86246!#1 N2425 P1526 LDD 13 -1 Int BE Pri
86247!#A N2424 N2425
86248!#1 N2426 P1527 MEMBAR
86249!#1 N2427 P1528 BSTC 3 0x400000aa FP BE Pri
86250!#1 N2428 P1528 BSTC 4 0x400000ab FP BE Pri
86251!#A N2427 N2428
86252!#1 N2429 P1528 BSTC 5 0x400000ac FP BE Pri
86253!#1 N2430 P1529 MEMBAR
86254!#1 N2431 P1530 BST 12 0x400000ad FP BE Pri
86255!#1 N2432 P1530 BST 13 0x400000ae FP BE Pri
86256!#A N2431 N2432
86257!#1 N2433 P1530 BST 14 0x400000af FP BE Pri
86258!#1 N2434 P1531 MEMBAR
86259!#1 N2435 P1532 ST 6 0x8000ce Int BE Pri
86260!#1 N2436 P1533 MEMBAR
86261!#1 N2437 P1534 BLD 0 -1 FP BE Pri
86262!#1 N2438 P1534 BLD 1 -1 FP BE Pri
86263!#A N2437 N2438
86264!#1 N2439 P1534 BLD 2 -1 FP BE Pri
86265!#1 N2440 P1535 MEMBAR
86266!#1 N2441 P1536 SWAP 5 0xffffffff 0x8000cf Int BE Pri
86267!#1 N2442 P1537 DWLD 18 -1 Int BE Pri
86268!#1 N2443 P1537 DWLD 19 -1 Int BE Pri
86269!#A N2442 N2443
86270!#1 N2444 P1537 CASX 18 -1 N2442 0x8000d0 Int BE Pri
86271!#1 N2445 P1537 CASX 19 -1 N2443 0x8000d1 Int BE Pri
86272!#A N2444 N2445
86273!#1 N2446 P1538 ST_BINIT 14 0x8000d2 Int BE Pri
86274!#1 N2447 P1539 MEMBAR
86275!#1 N2448 P1540 LD 15 -1 Int BE Pri
86276!#1 N2449 P1541 DWLD 11 -1,0x0 Int BE Pri
86277!#1 N2450 P1541 CASX 11 -1,0x0 N2449 0x8000d3 Int BE Pri
86278!#1 N2451 P1542 MEMBAR
86279!#1 N2452 P1543 BSTC 6 0x400000b0 FP BE Pri
86280!#1 N2453 P1543 BSTC 7 0x400000b1 FP BE Pri
86281!#A N2452 N2453
86282!#1 N2454 P1543 BSTC 8 0x400000b2 FP BE Pri
86283!#1 N2455 P1544 MEMBAR
86284!#1 N2456 P1545 DWLD 0 -1 Int BE Pri
86285!#1 N2457 P1545 DWLD 1 -1 Int BE Pri
86286!#A N2456 N2457
86287!#1 N2458 P1546 REPLACEMENT 4 Int BE Pri
86288!#1 N2459 P1547 DWST 9 0x400000b3 FP BE Pri
86289!#1 N2460 P1547 DWST 10 0x400000b4 FP BE Pri
86290!#A N2459 N2460
86291!#1 N2461 P1548 MEMBAR
86292!#1 N2462 P1549 BST 18 0x400000b5 FP BE Pri
86293!#1 N2463 P1549 BST 19 0x400000b6 FP BE Pri
86294!#A N2462 N2463
86295!#1 N2464 P1549 BST 20 0x400000b7 FP BE Pri
86296!#1 N2465 P1550 MEMBAR
86297!#1 N2466 P1551 LDD 6 -1 Int BE Pri
86298!#1 N2467 P1551 LDD 7 -1 Int BE Pri
86299!#A N2466 N2467
86300!#1 N2468 P1552 MEMBAR
86301!#1 N2469 P1553 BSTC 18 0x400000b8 FP BE Pri
86302!#1 N2470 P1553 BSTC 19 0x400000b9 FP BE Pri
86303!#A N2469 N2470
86304!#1 N2471 P1553 BSTC 20 0x400000ba FP BE Pri
86305!#1 N2472 P1554 MEMBAR
86306!#1 N2473 P1555 BST 3 0x400000bb FP BE Pri
86307!#1 N2474 P1555 BST 4 0x400000bc FP BE Pri
86308!#A N2473 N2474
86309!#1 N2475 P1555 BST 5 0x400000bd FP BE Pri
86310!#1 N2476 P1556 MEMBAR
86311!#1 N2477 P1557 LDD 11 -1 Int BE Pri
86312!#1 N2478 P1558 REPLACEMENT 6 Int BE Pri
86313!#1 N2479 P1559 MEMBAR
86314!#1 N2480 P1560 BSTC 15 0x400000be FP BE Pri
86315!#1 N2481 P1560 BSTC 16 0x400000bf FP BE Pri
86316!#A N2480 N2481
86317!#1 N2482 P1560 BSTC 17 0x400000c0 FP BE Pri
86318!#1 N2483 P1561 MEMBAR
86319!#1 N2484 P1562 BSTC 12 0x400000c1 FP BE Pri
86320!#1 N2485 P1562 BSTC 13 0x400000c2 FP BE Pri
86321!#A N2484 N2485
86322!#1 N2486 P1562 BSTC 14 0x400000c3 FP BE Pri
86323!#1 N2487 P1563 MEMBAR
86324!#1 N2488 P1564 LD 9 -1 Int BE Pri
86325!#1 N2489 P1564 CAS 9 -1 N2488 0x8000d4 Int BE Pri
86326!#1 N2490 P1565 ST 17 0x8000d5 Int BE Pri
86327!#1 N2491 P1566 LD 20 -1 Int BE Pri
86328!#1 N2492 P1567 LD 19 -1 Int BE Pri
86329!#1 N2493 P1568 DWLD 0 -1 Int BE Pri
86330!#1 N2494 P1568 DWLD 1 -1 Int BE Pri
86331!#A N2493 N2494
86332!#1 N2495 P1568 CASX 0 -1 N2493 0x8000d6 Int BE Pri
86333!#1 N2496 P1568 CASX 1 -1 N2494 0x8000d7 Int BE Pri
86334!#A N2495 N2496
86335!#1 N2497 P1569 ST_BINIT 11 0x8000d8 Int BE Pri
86336!#1 N2498 P1570 MEMBAR
86337!#1 N2499 P1571 SWAP 11 0xffffffff 0x8000d9 Int BE Pri
86338!#1 N2500 P1572 LD 7 -1 Int BE Pri
86339!#1 N2501 P1573 MEMBAR
86340!#1 N2502 P1574 BLD 9 -1 FP BE Pri
86341!#1 N2503 P1574 BLD 10 -1 FP BE Pri
86342!#A N2502 N2503
86343!#1 N2504 P1574 BLD 11 -1 FP BE Pri
86344!#1 N2505 P1575 MEMBAR
86345!#1 N2506 P1576 DWLD 18 -1 FP BE Pri
86346!#1 N2507 P1576 DWLD 19 -1 FP BE Pri
86347!#A N2506 N2507
86348!#1 N2508 P1577 ST 1 0x8000da Int BE Pri
86349!#1 N2509 P1578 LD 8 -1 Int BE Pri
86350!#1 N2510 P1578 CAS 8 -1 N2509 0x8000db Int BE Pri
86351!#1 N2511 P1579 SWAP 16 0xffffffff 0x8000dc Int BE Pri
86352!#1 N2512 P1580 ST_BINIT 23 0x8000dd Int BE Pri
86353!#1 N2513 P1581 MEMBAR
86354!#1 N2514 P1582 DWLD 0 -1 Int BE Pri
86355!#1 N2515 P1582 DWLD 1 -1 Int BE Pri
86356!#A N2514 N2515
86357!#1 N2516 P1583 PREFETCH 17 Int BE Pri
86358!#1 N2517 P1584 LD 3 -1 Int LE Pri
86359!#1 N2518 P1585 ST 17 0x8000de Int BE Pri
86360!#1 N2519 P1586 LD 21 -1 Int BE Pri
86361!#1 N2520 P1586 CAS 21 -1 N2519 0x8000df Int BE Pri
86362!#1 N2521 P1587 MEMBAR
86363!#1 N2522 P1588 BSTC 3 0x400000c4 FP BE Pri
86364!#1 N2523 P1588 BSTC 4 0x400000c5 FP BE Pri
86365!#A N2522 N2523
86366!#1 N2524 P1588 BSTC 5 0x400000c6 FP BE Pri
86367!#1 N2525 P1589 MEMBAR
86368!#1 N2526 P1590 LD 15 -1 Int BE Pri
86369!#1 N2527 P1590 CAS 15 -1 N2526 0x8000e0 Int BE Pri
86370!#1 N2528 P1591 ST_BINIT 7 0x8000e1 Int BE Pri
86371!#1 N2529 P1592 MEMBAR
86372!#1 N2530 P1593 BLD 15 -1 FP BE Pri
86373!#1 N2531 P1593 BLD 16 -1 FP BE Pri
86374!#A N2530 N2531
86375!#1 N2532 P1593 BLD 17 -1 FP BE Pri
86376!#1 N2533 P1594 MEMBAR
86377!#1 N2534 P1595 LDD 9 -1 Int BE Pri
86378!#1 N2535 P1595 LDD 10 -1 Int BE Pri
86379!#A N2534 N2535
86380!#1 N2536 P1596 ST 22 0x8000e2 Int BE Pri
86381!#1 N2537 P1597 LD 7 -1 Int BE Pri
86382!#1 N2538 P1597 CAS 7 -1 N2537 0x8000e3 Int BE Pri
86383!#1 N2539 P1598 LD 22 -1 Int BE Pri
86384!#1 N2540 P1598 CAS 22 -1 N2539 0x8000e4 Int BE Pri
86385!#1 N2541 P1599 LD 12 -1 Int BE Pri
86386!#1 N2542 P1600 DWST_BINIT 0 0x8000e5 Int BE Pri
86387!#1 N2543 P1600 DWST_BINIT 1 0x8000e6 Int BE Pri
86388!#A N2542 N2543
86389!#1 N2544 P1601 MEMBAR
86390!#1 N2545 P1602 DWST_BINIT 15 0x8000e7 Int BE Pri
86391!#1 N2546 P1602 DWST_BINIT 16 0x8000e8 Int BE Pri
86392!#A N2545 N2546
86393!#1 N2547 P1603 MEMBAR
86394!#1 N2548 P1604 DWST 2 0x8000e9 Int BE Pri
86395!#1 N2549 P1605 MEMBAR
86396!#1 N2550 P1606 BST 18 0x400000c7 FP BE Pri
86397!#1 N2551 P1606 BST 19 0x400000c8 FP BE Pri
86398!#A N2550 N2551
86399!#1 N2552 P1606 BST 20 0x400000c9 FP BE Pri
86400!#1 N2553 P1607 MEMBAR
86401!#1 N2554 P1608 LDD 11 -1 Int BE Pri
86402!#1 N2555 P1609 ST_BINIT 0 0x8000ea Int BE Pri
86403!#1 N2556 P1610 MEMBAR
86404!#1 N2557 P1611 LD 19 -1 FP BE Pri
86405!#1 N2558 P1612 PREFETCH 22 Int BE Pri
86406!#1 N2559 P1613 PREFETCH 14 Int BE Pri
86407!#1 N2560 P1614 SWAP 7 0xffffffff 0x8000eb Int BE Pri
86408!#1 N2561 P1615 DWST_BINIT 6 0x8000ec Int BE Pri
86409!#1 N2562 P1615 DWST_BINIT 7 0x8000ed Int BE Pri
86410!#A N2561 N2562
86411!#1 N2563 P1616 MEMBAR
86412!#1 N2564 P1617 DWLD 6 -1 Int BE Pri
86413!#1 N2565 P1617 DWLD 7 -1 Int BE Pri
86414!#A N2564 N2565
86415!#1 N2566 P1618 LDD 5 -1 Int LE Pri
86416!#1 N2567 P1619 DWST 3 0x400000ca FP BE Pri
86417!#1 N2568 P1619 DWST 4 0x400000cb FP BE Pri
86418!#A N2567 N2568
86419!#1 N2569 P1620 DWST_BINIT 17 0x8000ee Int BE Pri
86420!#1 N2570 P1621 MEMBAR
86421!#1 N2571 P1622 DWLD 2 -1 Int BE Pri
86422!#1 N2572 P1623 MEMBAR
86423!#1 N2573 P1624 BLD 3 -1 FP BE Pri
86424!#1 N2574 P1624 BLD 4 -1 FP BE Pri
86425!#A N2573 N2574
86426!#1 N2575 P1624 BLD 5 -1 FP BE Pri
86427!#1 N2576 P1625 MEMBAR
86428!#1 N2577 P1626 LDD 18 -1 Int BE Pri
86429!#1 N2578 P1626 LDD 19 -1 Int BE Pri
86430!#A N2577 N2578
86431!#1 N2579 P1627 MEMBAR
86432!#1 N2580 P1628 BSTC 18 0x400000cc FP BE Pri
86433!#1 N2581 P1628 BSTC 19 0x400000cd FP BE Pri
86434!#A N2580 N2581
86435!#1 N2582 P1628 BSTC 20 0x400000ce FP BE Pri
86436!#1 N2583 P1629 MEMBAR
86437!#1 N2584 P1630 LD 16 -1 Int BE Pri
86438!#1 N2585 P1631 MEMBAR
86439!#1 N2586 P1632 BLD 0 -1 FP BE Pri
86440!#1 N2587 P1632 BLD 1 -1 FP BE Pri
86441!#A N2586 N2587
86442!#1 N2588 P1632 BLD 2 -1 FP BE Pri
86443!#1 N2589 P1633 MEMBAR
86444!#1 N2590 P1634 LD 4 -1 Int BE Pri
86445!#1 N2591 P1634 CAS 4 -1 N2590 0x8000ef Int BE Pri
86446!#1 N2592 P1635 ST_BINIT 1 0x8000f0 Int BE Pri
86447!#1 N2593 P1636 MEMBAR
86448!#1 N2594 P1637 BSTC 9 0x400000cf FP BE Pri
86449!#1 N2595 P1637 BSTC 10 0x400000d0 FP BE Pri
86450!#A N2594 N2595
86451!#1 N2596 P1637 BSTC 11 0x400000d1 FP BE Pri
86452!#1 N2597 P1638 MEMBAR
86453!#1 N2598 P1639 DWLD 6 -1 Int BE Pri
86454!#1 N2599 P1639 DWLD 7 -1 Int BE Pri
86455!#A N2598 N2599
86456!#1 N2600 P1639 CASX 6 -1 N2598 0x8000f1 Int BE Pri
86457!#1 N2601 P1639 CASX 7 -1 N2599 0x8000f2 Int BE Pri
86458!#A N2600 N2601
86459!#1 N2602 P1640 PREFETCH 0 Int BE Pri
86460!#1 N2603 P1641 SWAP 1 0xffffffff 0x8000f3 Int BE Pri
86461!#1 N2604 P1642 MEMBAR
86462!#1 N2605 P1643 BST 3 0x400000d2 FP BE Pri
86463!#1 N2606 P1643 BST 4 0x400000d3 FP BE Pri
86464!#A N2605 N2606
86465!#1 N2607 P1643 BST 5 0x400000d4 FP BE Pri
86466!#1 N2608 P1644 MEMBAR
86467!#1 N2609 P1645 ST 18 0x8000f4 Int BE Pri
86468!#1 N2610 P1646 PREFETCH 13 Int LE Pri
86469!#1 N2611 P1647 DWLD 18 -1 Int LE Pri
86470!#1 N2612 P1647 DWLD 19 -1 Int LE Pri
86471!#A N2611 N2612
86472!#1 N2613 P1647 CASX 18 -1 N2611 0x8000f5 Int LE Pri
86473!#1 N2614 P1647 CASX 19 -1 N2612 0x8000f6 Int LE Pri
86474!#A N2613 N2614
86475!#1 N2615 P1648 DWST 0 0x8000f7 Int BE Pri
86476!#1 N2616 P1648 DWST 1 0x8000f8 Int BE Pri
86477!#A N2615 N2616
86478!#1 N2617 P1649 ST_BINIT 13 0x8000f9 Int BE Pri
86479!#1 N2618 P1650 MEMBAR
86480!#1 N2619 P1651 DWLD 18 -1 Int BE Pri
86481!#1 N2620 P1651 DWLD 19 -1 Int BE Pri
86482!#A N2619 N2620
86483!#1 N2621 P1651 CASX 18 -1 N2619 0x8000fa Int BE Pri
86484!#1 N2622 P1651 CASX 19 -1 N2620 0x8000fb Int BE Pri
86485!#A N2621 N2622
86486!#1 N2623 P1652 MEMBAR
86487!#1 N2624 P1653 BST 12 0x400000d5 FP BE Pri
86488!#1 N2625 P1653 BST 13 0x400000d6 FP BE Pri
86489!#A N2624 N2625
86490!#1 N2626 P1653 BST 14 0x400000d7 FP BE Pri
86491!#1 N2627 P1654 MEMBAR
86492!#1 N2628 P1655 ST_BINIT 11 0x8000fc Int BE Pri
86493!#1 N2629 P1656 MEMBAR
86494!#1 N2630 P1657 ST_BINIT 14 0x8000fd Int BE Pri
86495!#1 N2631 P1658 MEMBAR
86496!#1 N2632 P1659 ST 21 0x8000fe Int BE Pri
86497!#1 N2633 P1660 REPLACEMENT 12 Int BE Pri
86498!#1 N2634 P1661 LD 1 -1 Int BE Pri
86499!#1 N2635 P1661 CAS 1 -1 N2634 0x8000ff Int BE Pri
86500!#1 N2636 P1662 MEMBAR
86501!#1 N2637 P1663 BSTC 3 0x400000d8 FP BE Pri
86502!#1 N2638 P1663 BSTC 4 0x400000d9 FP BE Pri
86503!#A N2637 N2638
86504!#1 N2639 P1663 BSTC 5 0x400000da FP BE Pri
86505!#1 N2640 P1664 MEMBAR
86506!#1 N2641 P1665 DWLD 15 -1 Int BE Pri
86507!#1 N2642 P1665 DWLD 16 -1 Int BE Pri
86508!#A N2641 N2642
86509!#1 N2643 P1666 LD 3 -1 Int BE Pri
86510!#1 N2644 P1667 DWST_BINIT 3 0x800100 Int BE Pri
86511!#1 N2645 P1667 DWST_BINIT 4 0x800101 Int BE Pri
86512!#A N2644 N2645
86513!#1 N2646 P1668 MEMBAR
86514!#1 N2647 P1669 DWST 3 0x800102 Int BE Pri
86515!#1 N2648 P1669 DWST 4 0x800103 Int BE Pri
86516!#A N2647 N2648
86517!#1 N2649 P1670 DWST 0 0x800104 Int BE Pri
86518!#1 N2650 P1670 DWST 1 0x800105 Int BE Pri
86519!#A N2649 N2650
86520!#1 N2651 P1671 MEMBAR
86521!#1 N2652 P1672 BSTC 3 0x400000db FP BE Pri
86522!#1 N2653 P1672 BSTC 4 0x400000dc FP BE Pri
86523!#A N2652 N2653
86524!#1 N2654 P1672 BSTC 5 0x400000dd FP BE Pri
86525!#1 N2655 P1673 MEMBAR
86526!#1 N2656 P1674 DWLD 3 -1 Int BE Pri
86527!#1 N2657 P1674 DWLD 4 -1 Int BE Pri
86528!#A N2656 N2657
86529!#1 N2658 P1675 DWST_BINIT 2 0x800106 Int BE Pri
86530!#1 N2659 P1676 MEMBAR
86531!#1 N2660 P1677 ST_BINIT 1 0x800107 Int BE Pri
86532!#1 N2661 P1678 MEMBAR
86533!#1 N2662 P1679 LD 3 -1 Int BE Pri
86534!#1 N2663 P1680 MEMBAR
86535!#1 N2664 P1681 BLD 18 -1 FP BE Pri
86536!#1 N2665 P1681 BLD 19 -1 FP BE Pri
86537!#A N2664 N2665
86538!#1 N2666 P1681 BLD 20 -1 FP BE Pri
86539!#1 N2667 P1682 MEMBAR
86540!#1 N2668 P1683 DWLD 18 -1 Int BE Pri
86541!#1 N2669 P1683 DWLD 19 -1 Int BE Pri
86542!#A N2668 N2669
86543!#1 N2670 P1684 LD 5 -1 Int BE Pri
86544!#1 N2671 P1685 LDD 14 -1 Int BE Pri
86545!#1 N2672 P1686 ST 15 0x800108 Int BE Pri
86546!#1 N2673 P1687 PREFETCH 13 Int BE Pri
86547!#1 N2674 P1688 ST_BINIT 6 0x800109 Int BE Pri
86548!#1 N2675 P1689 MEMBAR
86549!#1 N2676 P1690 DWLD 12 -1 Int BE Pri
86550!#1 N2677 P1690 DWLD 13 -1 Int BE Pri
86551!#A N2676 N2677
86552!#1 N2678 P1691 LD 14 -1 Int BE Pri
86553!#1 N2679 P1692 MEMBAR
86554!#1 N2680 P1693 BST 0 0x400000de FP BE Pri
86555!#1 N2681 P1693 BST 1 0x400000df FP BE Pri
86556!#A N2680 N2681
86557!#1 N2682 P1693 BST 2 0x400000e0 FP BE Pri
86558!#1 N2683 P1694 MEMBAR
86559!#1 N2684 P1695 BST 6 0x400000e1 FP BE Pri
86560!#1 N2685 P1695 BST 7 0x400000e2 FP BE Pri
86561!#A N2684 N2685
86562!#1 N2686 P1695 BST 8 0x400000e3 FP BE Pri
86563!#1 N2687 P1696 MEMBAR
86564!#1 N2688 P1697 ST 10 0x80010a Int BE Pri
86565!#1 N2689 P1698 DWST 5 0x80010b Int BE Pri
86566!#1 N2690 P1699 DWST 20 0x80010c Int BE Pri
86567!#1 N2691 P1700 DWST_BINIT 11 0x80010d Int BE Pri
86568!#1 N2692 P1701 MEMBAR
86569!#1 N2693 P1702 BSTC 6 0x400000e4 FP BE Pri
86570!#1 N2694 P1702 BSTC 7 0x400000e5 FP BE Pri
86571!#A N2693 N2694
86572!#1 N2695 P1702 BSTC 8 0x400000e6 FP BE Pri
86573!#1 N2696 P1703 MEMBAR
86574!#1 N2697 P1704 LD 2 -1 Int BE Pri
86575!#1 N2698 P1704 CAS 2 -1 N2697 0x80010e Int BE Pri
86576!#1 N2699 P1705 MEMBAR
86577!#1 N2700 P1706 BST 6 0x400000e7 FP BE Pri
86578!#1 N2701 P1706 BST 7 0x400000e8 FP BE Pri
86579!#A N2700 N2701
86580!#1 N2702 P1706 BST 8 0x400000e9 FP BE Pri
86581!#1 N2703 P1707 MEMBAR
86582!#1 N2704 P1708 PREFETCH 1 Int BE Pri
86583!#1 N2705 P1709 SWAP 23 0xffffffff 0x80010f Int BE Pri
86584!#1 N2706 P1710 ST_BINIT 4 0x800110 Int BE Pri
86585!#1 N2707 P1711 MEMBAR
86586!#1 N2708 P1712 DWST_BINIT 15 0x800111 Int BE Pri
86587!#1 N2709 P1712 DWST_BINIT 16 0x800112 Int BE Pri
86588!#A N2708 N2709
86589!#1 N2710 P1713 MEMBAR
86590!#1 N2711 P1714 BST 6 0x400000ea FP BE Pri
86591!#1 N2712 P1714 BST 7 0x400000eb FP BE Pri
86592!#A N2711 N2712
86593!#1 N2713 P1714 BST 8 0x400000ec FP BE Pri
86594!#1 N2714 P1715 MEMBAR
86595!#1 N2715 P1716 LDD 18 -1 Int BE Pri
86596!#1 N2716 P1716 LDD 19 -1 Int BE Pri
86597!#A N2715 N2716
86598!#1 N2717 P1717 SWAP 1 0xffffffff 0x800113 Int BE Pri
86599!#1 N2718 P1718 MEMBAR
86600!#1 N2719 P1719 BLD 21 -1 FP BE Pri
86601!#1 N2720 P1719 BLD 22 -1 FP BE Pri
86602!#A N2719 N2720
86603!#1 N2721 P1719 BLD 23 -1 FP BE Pri
86604!#1 N2722 P1720 MEMBAR
86605!#1 N2723 P1721 ST_BINIT 20 0x800114 Int BE Pri
86606!#1 N2724 P1722 MEMBAR
86607!#1 N2725 P1723 BSTC 3 0x400000ed FP BE Pri
86608!#1 N2726 P1723 BSTC 4 0x400000ee FP BE Pri
86609!#A N2725 N2726
86610!#1 N2727 P1723 BSTC 5 0x400000ef FP BE Pri
86611!#1 N2728 P1724 MEMBAR
86612!#1 N2729 P1725 SWAP 0 0xffffffff 0x800115 Int BE Pri
86613!#1 N2730 P1726 MEMBAR
86614!#1 N2731 P1727 BSTC 6 0x400000f0 FP BE Pri
86615!#1 N2732 P1727 BSTC 7 0x400000f1 FP BE Pri
86616!#A N2731 N2732
86617!#1 N2733 P1727 BSTC 8 0x400000f2 FP BE Pri
86618!#1 N2734 P1728 MEMBAR
86619!#1 N2735 P1729 REPLACEMENT 8 Int BE Pri
86620!#1 N2736 P1730 LD 21 -1 Int BE Pri
86621!#1 N2737 P1730 CAS 21 -1 N2736 0x800116 Int BE Pri
86622!#1 N2738 P1731 DWLD 20 -1 Int BE Pri
86623!#1 N2739 P1732 DWST 9 0x800117 Int BE Pri
86624!#1 N2740 P1732 DWST 10 0x800118 Int BE Pri
86625!#A N2739 N2740
86626!#1 N2741 P1733 DWST 20 0x800119 Int BE Pri
86627!#1 N2742 P1734 DWST_BINIT 21 0x80011a Int BE Pri
86628!#1 N2743 P1734 DWST_BINIT 22 0x80011b Int BE Pri
86629!#A N2742 N2743
86630!#1 N2744 P1735 MEMBAR
86631!#1 N2745 P1736 DWST 18 0x80011c Int BE Pri
86632!#1 N2746 P1736 DWST 19 0x80011d Int BE Pri
86633!#A N2745 N2746
86634!#1 N2747 P1737 DWLD 18 -1 Int BE Pri
86635!#1 N2748 P1737 DWLD 19 -1 Int BE Pri
86636!#A N2747 N2748
86637!#1 N2749 P1738 PREFETCH 15 Int BE Pri
86638!#1 N2750 P1739 MEMBAR
86639!#1 N2751 P1740 BST 21 0x400000f3 FP BE Pri
86640!#1 N2752 P1740 BST 22 0x400000f4 FP BE Pri
86641!#A N2751 N2752
86642!#1 N2753 P1740 BST 23 0x400000f5 FP BE Pri
86643!#1 N2754 P1741 MEMBAR
86644!#1 N2755 P1742 LDD 15 -1 Int BE Pri
86645!#1 N2756 P1742 LDD 16 -1 Int BE Pri
86646!#A N2755 N2756
86647!#1 N2757 P1743 MEMBAR
86648!#1 N2758 P1744 BSTC 9 0x400000f6 FP BE Pri
86649!#1 N2759 P1744 BSTC 10 0x400000f7 FP BE Pri
86650!#A N2758 N2759
86651!#1 N2760 P1744 BSTC 11 0x400000f8 FP BE Pri
86652!#1 N2761 P1745 MEMBAR
86653!#1 N2762 P1746 BLD 12 -1 FP BE Pri
86654!#1 N2763 P1746 BLD 13 -1 FP BE Pri
86655!#A N2762 N2763
86656!#1 N2764 P1746 BLD 14 -1 FP BE Pri
86657!#1 N2765 P1747 MEMBAR
86658!#1 N2766 P1748 DWST_BINIT 0 0x80011e Int BE Pri
86659!#1 N2767 P1748 DWST_BINIT 1 0x80011f Int BE Pri
86660!#A N2766 N2767
86661!#1 N2768 P1749 MEMBAR
86662!#1 N2769 P1750 DWST 21 0x800120 Int BE Pri
86663!#1 N2770 P1750 DWST 22 0x800121 Int BE Pri
86664!#A N2769 N2770
86665!#1 N2771 P1751 MEMBAR
86666!#1 N2772 P1752 BSTC 0 0x400000f9 FP BE Pri
86667!#1 N2773 P1752 BSTC 1 0x400000fa FP BE Pri
86668!#A N2772 N2773
86669!#1 N2774 P1752 BSTC 2 0x400000fb FP BE Pri
86670!#1 N2775 P1753 MEMBAR
86671!#1 N2776 P1754 PREFETCH 3 Int BE Pri
86672!#1 N2777 P1755 DWST 15 0x400000fc FP BE Pri
86673!#1 N2778 P1755 DWST 16 0x400000fd FP BE Pri
86674!#A N2777 N2778
86675!#1 N2779 P1756 DWST_BINIT 8 0x800122 Int BE Pri
86676!#1 N2780 P1757 MEMBAR
86677!#1 N2781 P1758 ST 9 0x800123 Int BE Pri
86678!#1 N2782 P1759 DWST 6 0x800124 Int BE Pri
86679!#1 N2783 P1759 DWST 7 0x800125 Int BE Pri
86680!#A N2782 N2783
86681!#1 N2784 P1760 LD 18 -1 FP BE Pri
86682!#1 N2785 P1761 DWST_BINIT 6 0x800126 Int BE Pri
86683!#1 N2786 P1761 DWST_BINIT 7 0x800127 Int BE Pri
86684!#A N2785 N2786
86685!#1 N2787 P1762 MEMBAR
86686!#1 N2788 P1763 SWAP 8 0xffffffff 0x800128 Int BE Pri
86687!#1 N2789 P1764 ST 23 0x400000fe FP BE Pri
86688!#1 N2790 P1765 ST 17 0x800129 Int BE Pri
86689!#1 N2791 P1766 SWAP 5 0xffffffff 0x80012a Int BE Pri
86690!#1 N2792 P1767 DWST_BINIT 11 0x80012b Int BE Pri
86691!#1 N2793 P1768 MEMBAR
86692!#1 N2794 P1769 BST 21 0x400000ff FP BE Pri
86693!#1 N2795 P1769 BST 22 0x40000100 FP BE Pri
86694!#A N2794 N2795
86695!#1 N2796 P1769 BST 23 0x40000101 FP BE Pri
86696!#1 N2797 P1770 MEMBAR
86697!#1 N2798 P1771 LDD 11 -1 Int BE Pri
86698!#1 N2799 P1772 LD 20 -1 Int BE Pri
86699!#1 N2800 P1772 CAS 20 -1 N2799 0x80012c Int BE Pri
86700!#1 N2801 P1773 DWST 0 0x80012d Int BE Pri
86701!#1 N2802 P1773 DWST 1 0x80012e Int BE Pri
86702!#A N2801 N2802
86703!#1 N2803 P1774 LDD 3 -1 Int BE Pri
86704!#1 N2804 P1774 LDD 4 -1 Int BE Pri
86705!#A N2803 N2804
86706!#1 N2805 P1775 MEMBAR
86707!#1 N2806 P1776 BST 12 0x40000102 FP BE Pri
86708!#1 N2807 P1776 BST 13 0x40000103 FP BE Pri
86709!#A N2806 N2807
86710!#1 N2808 P1776 BST 14 0x40000104 FP BE Pri
86711!#1 N2809 P1777 MEMBAR
86712!#1 N2810 P1778 PREFETCH 2 Int BE Pri
86713!#1 N2811 P1779 LDD 3 -1 Int BE Pri
86714!#1 N2812 P1779 LDD 4 -1 Int BE Pri
86715!#A N2811 N2812
86716!#1 N2813 P1780 MEMBAR
86717!#1 N2814 P1781 BST 12 0x40000105 FP BE Pri
86718!#1 N2815 P1781 BST 13 0x40000106 FP BE Pri
86719!#A N2814 N2815
86720!#1 N2816 P1781 BST 14 0x40000107 FP BE Pri
86721!#1 N2817 P1782 MEMBAR
86722!#1 N2818 P1783 REPLACEMENT 0 Int BE Pri
86723!#1 N2819 P1784 MEMBAR
86724!#1 N2820 P1785 BST 9 0x40000108 FP BE Pri
86725!#1 N2821 P1785 BST 10 0x40000109 FP BE Pri
86726!#A N2820 N2821
86727!#1 N2822 P1785 BST 11 0x4000010a FP BE Pri
86728!#1 N2823 P1786 MEMBAR
86729!#1 N2824 P1787 BSTC 6 0x4000010b FP BE Pri
86730!#1 N2825 P1787 BSTC 7 0x4000010c FP BE Pri
86731!#A N2824 N2825
86732!#1 N2826 P1787 BSTC 8 0x4000010d FP BE Pri
86733!#1 N2827 P1788 MEMBAR
86734!#1 N2828 P1789 ST_BINIT 5 0x80012f Int BE Pri
86735!#1 N2829 P1790 MEMBAR
86736!#1 N2830 P1791 SWAP 6 0xffffffff 0x800130 Int BE Pri
86737!#1 N2831 P1792 MEMBAR
86738!#1 N2832 P1793 BSTC 0 0x4000010e FP BE Pri
86739!#1 N2833 P1793 BSTC 1 0x4000010f FP BE Pri
86740!#A N2832 N2833
86741!#1 N2834 P1793 BSTC 2 0x40000110 FP BE Pri
86742!#1 N2835 P1794 MEMBAR
86743!#1 N2836 P1795 DWST 11 0x800131 Int BE Pri
86744!#1 N2837 P1796 LD 7 -1 Int BE Pri
86745!#1 N2838 P1796 CAS 7 -1 N2837 0x800132 Int BE Pri
86746!#1 N2839 P1797 LD 23 -1 Int BE Pri
86747!#1 N2840 P1797 CAS 23 -1 N2839 0x800133 Int BE Pri
86748!#1 N2841 P1798 MEMBAR
86749!#1 N2842 P1799 BST 6 0x40000111 FP BE Pri
86750!#1 N2843 P1799 BST 7 0x40000112 FP BE Pri
86751!#A N2842 N2843
86752!#1 N2844 P1799 BST 8 0x40000113 FP BE Pri
86753!#1 N2845 P1800 MEMBAR
86754!#1 N2846 P1801 REPLACEMENT 18 Int BE Pri
86755!#1 N2847 P1802 MEMBAR
86756!#1 N2848 P1803 BST 6 0x40000114 FP BE Pri
86757!#1 N2849 P1803 BST 7 0x40000115 FP BE Pri
86758!#A N2848 N2849
86759!#1 N2850 P1803 BST 8 0x40000116 FP BE Pri
86760!#1 N2851 P1804 MEMBAR
86761!#1 N2852 P1805 ST_BINIT 11 0x800134 Int BE Pri
86762!#1 N2853 P1806 MEMBAR
86763!#1 N2854 P1807 ST_BINIT 12 0x800135 Int BE Pri
86764!#1 N2855 P1808 MEMBAR
86765!#1 N2856 P1809 PREFETCH 2 Int BE Pri
86766!#1 N2857 P1810 MEMBAR
86767!#1 N2858 P1811 BST 18 0x40000117 FP BE Pri
86768!#1 N2859 P1811 BST 19 0x40000118 FP BE Pri
86769!#A N2858 N2859
86770!#1 N2860 P1811 BST 20 0x40000119 FP BE Pri
86771!#1 N2861 P1812 MEMBAR
86772!#1 N2862 P1813 ST_BINIT 22 0x800136 Int BE Pri
86773!#1 N2863 P1814 MEMBAR
86774!#1 N2864 P1815 BSTC 0 0x4000011a FP BE Pri
86775!#1 N2865 P1815 BSTC 1 0x4000011b FP BE Pri
86776!#A N2864 N2865
86777!#1 N2866 P1815 BSTC 2 0x4000011c FP BE Pri
86778!#1 N2867 P1816 MEMBAR
86779!#1 N2868 P1817 DWLD 15 -1 Int BE Pri
86780!#1 N2869 P1817 DWLD 16 -1 Int BE Pri
86781!#A N2868 N2869
86782!#1 N2870 P1817 CASX 15 -1 N2868 0x800137 Int BE Pri
86783!#1 N2871 P1817 CASX 16 -1 N2869 0x800138 Int BE Pri
86784!#A N2870 N2871
86785!#1 N2872 P1818 ST 23 0x800139 Int BE Pri
86786!#1 N2873 P1819 LDD 0 -1 Int BE Pri
86787!#1 N2874 P1819 LDD 1 -1 Int BE Pri
86788!#A N2873 N2874
86789!#1 N2875 P1820 DWLD 3 -1 Int BE Pri
86790!#1 N2876 P1820 DWLD 4 -1 Int BE Pri
86791!#A N2875 N2876
86792!#1 N2877 P1820 CASX 3 -1 N2875 0x80013a Int BE Pri
86793!#1 N2878 P1820 CASX 4 -1 N2876 0x80013b Int BE Pri
86794!#A N2877 N2878
86795!#1 N2879 P1821 MEMBAR
86796!#1 N2880 P1822 BST 6 0x4000011d FP BE Pri
86797!#1 N2881 P1822 BST 7 0x4000011e FP BE Pri
86798!#A N2880 N2881
86799!#1 N2882 P1822 BST 8 0x4000011f FP BE Pri
86800!#1 N2883 P1823 MEMBAR
86801!#1 N2884 P1824 PREFETCH 12 Int BE Pri
86802!#1 N2885 P1825 LD 8 -1 Int BE Pri
86803!#1 N2886 P1825 CAS 8 -1 N2885 0x80013c Int BE Pri
86804!#1 N2887 P1826 MEMBAR
86805!#1 N2888 P1827 BST 21 0x40000120 FP BE Pri
86806!#1 N2889 P1827 BST 22 0x40000121 FP BE Pri
86807!#A N2888 N2889
86808!#1 N2890 P1827 BST 23 0x40000122 FP BE Pri
86809!#1 N2891 P1828 MEMBAR
86810!#1 N2892 P1829 BSTC 12 0x40000123 FP BE Pri
86811!#1 N2893 P1829 BSTC 13 0x40000124 FP BE Pri
86812!#A N2892 N2893
86813!#1 N2894 P1829 BSTC 14 0x40000125 FP BE Pri
86814!#1 N2895 P1830 MEMBAR
86815!#1 N2896 P1831 LDD 18 -1 Int BE Pri
86816!#1 N2897 P1831 LDD 19 -1 Int BE Pri
86817!#A N2896 N2897
86818!#1 N2898 P1832 ST 0 0x40000126 FP BE Pri
86819!#1 N2899 P1833 MEMBAR
86820!#1 N2900 P1834 BST 12 0x40000127 FP BE Pri
86821!#1 N2901 P1834 BST 13 0x40000128 FP BE Pri
86822!#A N2900 N2901
86823!#1 N2902 P1834 BST 14 0x40000129 FP BE Pri
86824!#1 N2903 P1835 MEMBAR
86825!#1 N2904 P1836 PREFETCH 23 Int BE Pri
86826!#1 N2905 P1837 DWLD 15 -1 Int BE Pri
86827!#1 N2906 P1837 DWLD 16 -1 Int BE Pri
86828!#A N2905 N2906
86829!#1 N2907 P1837 CASX 15 -1 N2905 0x80013d Int BE Pri
86830!#1 N2908 P1837 CASX 16 -1 N2906 0x80013e Int BE Pri
86831!#A N2907 N2908
86832!#1 N2909 P1838 SWAP 10 0xffffffff 0x80013f Int BE Pri
86833!#1 N2910 P1839 SWAP 12 0xffffffff 0x800140 Int BE Pri
86834!#1 N2911 P1840 LD 12 -1 Int BE Pri
86835!#1 N2912 P1840 CAS 12 -1 N2911 0x800141 Int BE Pri
86836!#1 N2913 P1841 PREFETCH 19 Int BE Pri
86837!#1 N2914 P1842 LD 9 -1 Int BE Pri
86838!#1 N2915 P1842 CAS 9 -1 N2914 0x800142 Int BE Pri
86839!#1 N2916 P1843 LDD 0 -1 Int LE Pri
86840!#1 N2917 P1843 LDD 1 -1 Int LE Pri
86841!#A N2916 N2917
86842!#1 N2918 P1844 DWST_BINIT 18 0x800143 Int BE Pri
86843!#1 N2919 P1844 DWST_BINIT 19 0x800144 Int BE Pri
86844!#A N2918 N2919
86845!#1 N2920 P1845 MEMBAR
86846!#1 N2921 P1846 DWLD 3 -1 Int BE Pri
86847!#1 N2922 P1846 DWLD 4 -1 Int BE Pri
86848!#A N2921 N2922
86849!#1 N2923 P1847 SWAP 17 0xffffffff 0x800145 Int BE Pri
86850!#1 N2924 P1848 MEMBAR
86851!#1 N2925 P1849 BST 15 0x4000012a FP BE Pri
86852!#1 N2926 P1849 BST 16 0x4000012b FP BE Pri
86853!#A N2925 N2926
86854!#1 N2927 P1849 BST 17 0x4000012c FP BE Pri
86855!#1 N2928 P1850 MEMBAR
86856!#1 N2929 P1851 BSTC 0 0x4000012d FP BE Pri
86857!#1 N2930 P1851 BSTC 1 0x4000012e FP BE Pri
86858!#A N2929 N2930
86859!#1 N2931 P1851 BSTC 2 0x4000012f FP BE Pri
86860!#1 N2932 P1852 MEMBAR
86861!#1 N2933 P1853 BLD 12 -1 FP BE Pri
86862!#1 N2934 P1853 BLD 13 -1 FP BE Pri
86863!#A N2933 N2934
86864!#1 N2935 P1853 BLD 14 -1 FP BE Pri
86865!#1 N2936 P1854 MEMBAR
86866!#1 N2937 P1855 DWST_BINIT 0 0x800146 Int BE Pri
86867!#1 N2938 P1855 DWST_BINIT 1 0x800147 Int BE Pri
86868!#A N2937 N2938
86869!#1 N2939 P1856 MEMBAR
86870!#1 N2940 P1857 ST_BINIT 4 0x800148 Int BE Pri
86871!#1 N2941 P1858 MEMBAR
86872!#1 N2942 P1859 LD 16 -1 Int BE Pri
86873!#1 N2943 P1859 CAS 16 -1 N2942 0x800149 Int BE Pri
86874!#1 N2944 P1860 DWST_BINIT 21 0x80014a Int BE Pri
86875!#1 N2945 P1860 DWST_BINIT 22 0x80014b Int BE Pri
86876!#A N2944 N2945
86877!#1 N2946 P1861 MEMBAR
86878!#1 N2947 P1862 LDD 17 -1 Int BE Pri
86879!#1 N2948 P1863 ST 0 0x80014c Int BE Pri
86880!#1 N2949 P1864 DWST 15 0x80014d Int BE Pri
86881!#1 N2950 P1864 DWST 16 0x80014e Int BE Pri
86882!#A N2949 N2950
86883!#1 N2951 P1865 MEMBAR
86884!#1 N2952 P1866 BLD 9 -1 FP BE Pri
86885!#1 N2953 P1866 BLD 10 -1 FP BE Pri
86886!#A N2952 N2953
86887!#1 N2954 P1866 BLD 11 -1 FP BE Pri
86888!#1 N2955 P1867 MEMBAR
86889!#1 N2956 P1868 BSTC 21 0x40000130 FP BE Pri
86890!#1 N2957 P1868 BSTC 22 0x40000131 FP BE Pri
86891!#A N2956 N2957
86892!#1 N2958 P1868 BSTC 23 0x40000132 FP BE Pri
86893!#1 N2959 P1869 MEMBAR
86894!#1 N2960 P1870 ST 20 0x80014f Int BE Pri
86895!#1 N2961 P1871 PREFETCH 22 Int BE Pri
86896!#1 N2962 P1872 MEMBAR
86897!#1 N2963 P1873 BLD 15 -1 FP BE Pri
86898!#1 N2964 P1873 BLD 16 -1 FP BE Pri
86899!#A N2963 N2964
86900!#1 N2965 P1873 BLD 17 -1 FP BE Pri
86901!#1 N2966 P1874 MEMBAR
86902!#1 N2967 P1875 LDD 18 -1 Int BE Pri
86903!#1 N2968 P1875 LDD 19 -1 Int BE Pri
86904!#A N2967 N2968
86905!#1 N2969 P1876 LD 10 -1 Int BE Pri
86906!#1 N2970 P1876 CAS 10 -1 N2969 0x800150 Int BE Pri
86907!#1 N2971 P1877 MEMBAR
86908!#1 N2972 P1878 BSTC 12 0x40000133 FP BE Pri
86909!#1 N2973 P1878 BSTC 13 0x40000134 FP BE Pri
86910!#A N2972 N2973
86911!#1 N2974 P1878 BSTC 14 0x40000135 FP BE Pri
86912!#1 N2975 P1879 MEMBAR
86913!#1 N2976 P1880 BLD 3 -1 FP BE Pri
86914!#1 N2977 P1880 BLD 4 -1 FP BE Pri
86915!#A N2976 N2977
86916!#1 N2978 P1880 BLD 5 -1 FP BE Pri
86917!#1 N2979 P1881 MEMBAR
86918!#1 N2980 P1882 LD 6 -1 Int BE Pri
86919!#1 N2981 P1883 LDD 0 -1 Int BE Pri
86920!#1 N2982 P1883 LDD 1 -1 Int BE Pri
86921!#A N2981 N2982
86922!#1 N2983 P1884 MEMBAR
86923!#1 N2984 P1885 BSTC 15 0x40000136 FP BE Pri
86924!#1 N2985 P1885 BSTC 16 0x40000137 FP BE Pri
86925!#A N2984 N2985
86926!#1 N2986 P1885 BSTC 17 0x40000138 FP BE Pri
86927!#1 N2987 P1886 MEMBAR
86928!#1 N2988 P1887 DWLD 21 -1 Int BE Pri
86929!#1 N2989 P1887 DWLD 22 -1 Int BE Pri
86930!#A N2988 N2989
86931!#1 N2990 P1888 LD 17 -1 Int LE Pri
86932!#1 N2991 P1888 CAS 17 -1 N2990 0x800151 Int LE Pri
86933!#1 N2992 P1889 DWLD 18 -1 Int BE Pri
86934!#1 N2993 P1889 DWLD 19 -1 Int BE Pri
86935!#A N2992 N2993
86936!#1 N2994 P1889 CASX 18 -1 N2992 0x800152 Int BE Pri
86937!#1 N2995 P1889 CASX 19 -1 N2993 0x800153 Int BE Pri
86938!#A N2994 N2995
86939!#1 N2996 P1890 LDD 15 -1 Int BE Pri
86940!#1 N2997 P1890 LDD 16 -1 Int BE Pri
86941!#A N2996 N2997
86942!#1 N2998 P1891 MEMBAR
86943!#1 N2999 P1892 BLD 3 -1 FP BE Pri
86944!#1 N3000 P1892 BLD 4 -1 FP BE Pri
86945!#A N2999 N3000
86946!#1 N3001 P1892 BLD 5 -1 FP BE Pri
86947!#1 N3002 P1893 MEMBAR
86948!#1 N3003 P1894 ST 17 0x800154 Int BE Pri
86949!#1 N3004 P1895 LD 1 -1 Int BE Pri
86950!#1 N3005 P1895 CAS 1 -1 N3004 0x800155 Int BE Pri
86951!#1 N3006 P1896 SWAP 20 0xffffffff 0x800156 Int BE Pri
86952!#1 N3007 P1897 LD 22 -1 Int BE Pri
86953!#1 N3008 P1897 CAS 22 -1 N3007 0x800157 Int BE Pri
86954!#1 N3009 P1898 LDD 5 -1 Int BE Pri
86955!#1 N3010 P1899 DWLD 21 -1 Int BE Pri
86956!#1 N3011 P1899 DWLD 22 -1 Int BE Pri
86957!#A N3010 N3011
86958!#1 N3012 P1899 CASX 21 -1 N3010 0x800158 Int BE Pri
86959!#1 N3013 P1899 CASX 22 -1 N3011 0x800159 Int BE Pri
86960!#A N3012 N3013
86961!#1 N3014 P1900 LDD 15 -1 Int BE Pri
86962!#1 N3015 P1900 LDD 16 -1 Int BE Pri
86963!#A N3014 N3015
86964!#1 N3016 P1901 MEMBAR
86965!#1 N3017 P1902 BST 6 0x40000139 FP BE Pri
86966!#1 N3018 P1902 BST 7 0x4000013a FP BE Pri
86967!#A N3017 N3018
86968!#1 N3019 P1902 BST 8 0x4000013b FP BE Pri
86969!#1 N3020 P1903 MEMBAR
86970!#1 N3021 P1904 BST 0 0x4000013c FP BE Pri
86971!#1 N3022 P1904 BST 1 0x4000013d FP BE Pri
86972!#A N3021 N3022
86973!#1 N3023 P1904 BST 2 0x4000013e FP BE Pri
86974!#1 N3024 P1905 MEMBAR
86975!#1 N3025 P1906 BLD 21 -1 FP BE Pri
86976!#1 N3026 P1906 BLD 22 -1 FP BE Pri
86977!#A N3025 N3026
86978!#1 N3027 P1906 BLD 23 -1 FP BE Pri
86979!#1 N3028 P1907 MEMBAR
86980!#1 N3029 P1908 LD 13 -1 Int BE Pri
86981!#1 N3030 P1909 PREFETCH 21 Int BE Pri
86982!#1 N3031 P1910 MEMBAR
86983!#1 N3032 P1911 BST 0 0x4000013f FP BE Pri
86984!#1 N3033 P1911 BST 1 0x40000140 FP BE Pri
86985!#A N3032 N3033
86986!#1 N3034 P1911 BST 2 0x40000141 FP BE Pri
86987!#1 N3035 P1912 MEMBAR
86988!#1 N3036 P1913 DWST 0 0x80015a Int BE Pri
86989!#1 N3037 P1913 DWST 1 0x80015b Int BE Pri
86990!#A N3036 N3037
86991!#1 N3038 P1914 MEMBAR
86992!#1 N3039 P1915 BSTC 15 0x40000142 FP BE Pri
86993!#1 N3040 P1915 BSTC 16 0x40000143 FP BE Pri
86994!#A N3039 N3040
86995!#1 N3041 P1915 BSTC 17 0x40000144 FP BE Pri
86996!#1 N3042 P1916 MEMBAR
86997!#1 N3043 P1917 BSTC 18 0x40000145 FP BE Pri
86998!#1 N3044 P1917 BSTC 19 0x40000146 FP BE Pri
86999!#A N3043 N3044
87000!#1 N3045 P1917 BSTC 20 0x40000147 FP BE Pri
87001!#1 N3046 P1918 MEMBAR
87002!#1 N3047 P1919 DWLD 11 -1,0x0 Int BE Pri
87003!#1 N3048 P1919 CASX 11 -1,0x0 N3047 0x80015c Int BE Pri
87004!#1 N3049 P1920 SWAP 2 0xffffffff 0x80015d Int BE Pri
87005!#1 N3050 P1921 LD 22 -1 Int BE Pri
87006!#1 N3051 P1922 MEMBAR
87007!#1 N3052 P1923 BLD 18 -1 FP BE Pri
87008!#1 N3053 P1923 BLD 19 -1 FP BE Pri
87009!#A N3052 N3053
87010!#1 N3054 P1923 BLD 20 -1 FP BE Pri
87011!#1 N3055 P1924 MEMBAR
87012!#1 N3056 P1925 DWLD 15 -1 Int BE Pri
87013!#1 N3057 P1925 DWLD 16 -1 Int BE Pri
87014!#A N3056 N3057
87015!#1 N3058 P1925 CASX 15 -1 N3056 0x80015e Int BE Pri
87016!#1 N3059 P1925 CASX 16 -1 N3057 0x80015f Int BE Pri
87017!#A N3058 N3059
87018!#1 N3060 P1926 SWAP 18 0xffffffff 0x800160 Int BE Pri
87019!#1 N3061 P1927 LDD 21 -1 Int BE Pri
87020!#1 N3062 P1927 LDD 22 -1 Int BE Pri
87021!#A N3061 N3062
87022!#1 N3063 P1928 LD 1 -1 Int BE Pri
87023!#1 N3064 P1929 ST 10 0x800161 Int BE Pri
87024!#1 N3065 P1930 MEMBAR
87025!#1 N3066 P1931 BST 12 0x40000148 FP BE Pri
87026!#1 N3067 P1931 BST 13 0x40000149 FP BE Pri
87027!#A N3066 N3067
87028!#1 N3068 P1931 BST 14 0x4000014a FP BE Pri
87029!#1 N3069 P1932 MEMBAR
87030!#1 N3070 P1933 LD 8 -1 Int BE Pri
87031!#1 N3071 P1933 CAS 8 -1 N3070 0x800162 Int BE Pri
87032!#1 N3072 P1934 ST_BINIT 5 0x800163 Int BE Pri
87033!#1 N3073 P1935 MEMBAR
87034!#1 N3074 P1936 SWAP 8 0xffffffff 0x800164 Int BE Pri
87035!#1 N3075 P1937 MEMBAR
87036!#1 N3076 P1938 BLD 12 -1 FP BE Pri
87037!#1 N3077 P1938 BLD 13 -1 FP BE Pri
87038!#A N3076 N3077
87039!#1 N3078 P1938 BLD 14 -1 FP BE Pri
87040!#1 N3079 P1939 MEMBAR
87041!#1 N3080 P1940 DWST_BINIT 21 0x800165 Int BE Pri
87042!#1 N3081 P1940 DWST_BINIT 22 0x800166 Int BE Pri
87043!#A N3080 N3081
87044!#1 N3082 P1941 MEMBAR
87045!#1 N3083 P1942 ST_BINIT 9 0x800167 Int BE Pri
87046!#1 N3084 P1943 MEMBAR
87047!#1 N3085 P1944 DWLD 17 -1,0x0 Int BE Pri
87048!#1 N3086 P1944 CASX 17 -1,0x0 N3085 0x800168 Int BE Pri
87049!#1 N3087 P1945 MEMBAR
87050!#1 N3088 P1946 BLD 3 -1 FP BE Pri
87051!#1 N3089 P1946 BLD 4 -1 FP BE Pri
87052!#A N3088 N3089
87053!#1 N3090 P1946 BLD 5 -1 FP BE Pri
87054!#1 N3091 P1947 MEMBAR
87055!#1 N3092 P1948 LDD 12 -1 Int BE Pri
87056!#1 N3093 P1948 LDD 13 -1 Int BE Pri
87057!#A N3092 N3093
87058!#1 N3094 P1949 ST_BINIT 20 0x800169 Int BE Pri
87059!#1 N3095 P1950 MEMBAR
87060!#1 N3096 P1951 DWLD 12 -1 Int BE Pri
87061!#1 N3097 P1951 DWLD 13 -1 Int BE Pri
87062!#A N3096 N3097
87063!#1 N3098 P1952 ST_BINIT 0 0x80016a Int BE Pri
87064!#1 N3099 P1953 MEMBAR
87065!#1 N3100 P1954 BLD 3 -1 FP BE Pri
87066!#1 N3101 P1954 BLD 4 -1 FP BE Pri
87067!#A N3100 N3101
87068!#1 N3102 P1954 BLD 5 -1 FP BE Pri
87069!#1 N3103 P1955 MEMBAR
87070!#1 N3104 P1956 DWLD 3 -1 Int BE Pri
87071!#1 N3105 P1956 DWLD 4 -1 Int BE Pri
87072!#A N3104 N3105
87073!#1 N3106 P1957 SWAP 4 0xffffffff 0x80016b Int BE Pri
87074!#1 N3107 P1958 LD 14 -1 Int BE Pri
87075!#1 N3108 P1958 CAS 14 -1 N3107 0x80016c Int BE Pri
87076!#1 N3109 P1959 ST 4 0x80016d Int BE Pri
87077!#1 N3110 P1960 MEMBAR
87078!#1 N3111 P1961 BST 15 0x4000014b FP BE Pri
87079!#1 N3112 P1961 BST 16 0x4000014c FP BE Pri
87080!#A N3111 N3112
87081!#1 N3113 P1961 BST 17 0x4000014d FP BE Pri
87082!#1 N3114 P1962 MEMBAR
87083!#1 N3115 P1963 BST 21 0x4000014e FP BE Pri
87084!#1 N3116 P1963 BST 22 0x4000014f FP BE Pri
87085!#A N3115 N3116
87086!#1 N3117 P1963 BST 23 0x40000150 FP BE Pri
87087!#1 N3118 P1964 MEMBAR
87088!#1 N3119 P1965 BSTC 18 0x40000151 FP BE Pri
87089!#1 N3120 P1965 BSTC 19 0x40000152 FP BE Pri
87090!#A N3119 N3120
87091!#1 N3121 P1965 BSTC 20 0x40000153 FP BE Pri
87092!#1 N3122 P1966 MEMBAR
87093!#1 N3123 P1967 BSTC 9 0x40000154 FP BE Pri
87094!#1 N3124 P1967 BSTC 10 0x40000155 FP BE Pri
87095!#A N3123 N3124
87096!#1 N3125 P1967 BSTC 11 0x40000156 FP BE Pri
87097!#1 N3126 P1968 MEMBAR
87098!#1 N3127 P1969 BSTC 0 0x40000157 FP BE Pri
87099!#1 N3128 P1969 BSTC 1 0x40000158 FP BE Pri
87100!#A N3127 N3128
87101!#1 N3129 P1969 BSTC 2 0x40000159 FP BE Pri
87102!#1 N3130 P1970 MEMBAR
87103!#1 N3131 P1971 DWLD 3 -1 Int BE Pri
87104!#1 N3132 P1971 DWLD 4 -1 Int BE Pri
87105!#A N3131 N3132
87106!#1 N3133 P1971 CASX 3 -1 N3131 0x80016e Int BE Pri
87107!#1 N3134 P1971 CASX 4 -1 N3132 0x80016f Int BE Pri
87108!#A N3133 N3134
87109!#1 N3135 P1972 DWST 15 0x800170 Int BE Pri
87110!#1 N3136 P1972 DWST 16 0x800171 Int BE Pri
87111!#A N3135 N3136
87112!#1 N3137 P1973 SWAP 2 0xffffffff 0x800172 Int BE Pri
87113!#1 N3138 P1974 DWST 6 0x800173 Int LE Pri
87114!#1 N3139 P1974 DWST 7 0x800174 Int LE Pri
87115!#A N3138 N3139
87116!#1 N3140 P1975 DWLD 21 -1 Int BE Pri
87117!#1 N3141 P1975 DWLD 22 -1 Int BE Pri
87118!#A N3140 N3141
87119!#1 N3142 P1975 CASX 21 -1 N3140 0x800175 Int BE Pri
87120!#1 N3143 P1975 CASX 22 -1 N3141 0x800176 Int BE Pri
87121!#A N3142 N3143
87122!#1 N3144 P1976 MEMBAR
87123!#1 N3145 P1977 BLD 21 -1 FP BE Pri
87124!#1 N3146 P1977 BLD 22 -1 FP BE Pri
87125!#A N3145 N3146
87126!#1 N3147 P1977 BLD 23 -1 FP BE Pri
87127!#1 N3148 P1978 MEMBAR
87128!#1 N3149 P1979 SWAP 16 0xffffffff 0x800177 Int BE Pri
87129!#1 N3150 P1980 REPLACEMENT 12 Int BE Pri
87130!#1 N3151 P1981 SWAP 21 0xffffffff 0x800178 Int BE Pri
87131!#1 N3152 P1982 DWLD 0 -1 Int BE Pri
87132!#1 N3153 P1982 DWLD 1 -1 Int BE Pri
87133!#A N3152 N3153
87134!#1 N3154 P1983 MEMBAR
87135!#1 N3155 P1984 BSTC 0 0x4000015a FP BE Pri
87136!#1 N3156 P1984 BSTC 1 0x4000015b FP BE Pri
87137!#A N3155 N3156
87138!#1 N3157 P1984 BSTC 2 0x4000015c FP BE Pri
87139!#1 N3158 P1985 MEMBAR
87140!#1 N3159 P1986 BST 18 0x4000015d FP BE Pri
87141!#1 N3160 P1986 BST 19 0x4000015e FP BE Pri
87142!#A N3159 N3160
87143!#1 N3161 P1986 BST 20 0x4000015f FP BE Pri
87144!#1 N3162 P1987 MEMBAR
87145!#1 N3163 P1988 BLD 12 -1 FP BE Pri
87146!#1 N3164 P1988 BLD 13 -1 FP BE Pri
87147!#A N3163 N3164
87148!#1 N3165 P1988 BLD 14 -1 FP BE Pri
87149!#1 N3166 P1989 MEMBAR
87150!#1 N3167 P1990 SWAP 18 0xffffffff 0x800179 Int BE Pri
87151!#1 N3168 P1991 ST_BINIT 11 0x80017a Int BE Pri
87152!#1 N3169 P1992 MEMBAR
87153!#1 N3170 P1993 DWLD 20 -1,0x0 Int BE Pri
87154!#1 N3171 P1993 CASX 20 -1,0x0 N3170 0x80017b Int BE Pri
87155!#1 N3172 P1994 DWST 17 0x80017c Int BE Pri
87156!#1 N3173 P1995 LDD 17 -1 Int BE Pri
87157!#1 N3174 P1996 DWLD 18 -1 Int BE Pri
87158!#1 N3175 P1996 DWLD 19 -1 Int BE Pri
87159!#A N3174 N3175
87160!#1 N3176 P1997 MEMBAR
87161!#1 N3177 P1998 BLD 12 -1 FP BE Pri
87162!#1 N3178 P1998 BLD 13 -1 FP BE Pri
87163!#A N3177 N3178
87164!#1 N3179 P1998 BLD 14 -1 FP BE Pri
87165!#1 N3180 P1999 MEMBAR
87166!#1 N3181 P2000 LDD 12 -1 Int BE Pri
87167!#1 N3182 P2000 LDD 13 -1 Int BE Pri
87168!#A N3181 N3182
87169!#1 N3183 P2001 LD 18 -1 Int BE Pri
87170!#1 N3184 P2002 LD 18 -1 Int BE Pri Loop_exit
87171!#1 N3185 P2003 MEMBAR
87172!#2 N3186 P2004 DWLD 0 -1 Int BE Pri Loop_entry
87173!#2 N3187 P2004 DWLD 1 -1 Int BE Pri Loop_entry
87174!#A N3186 N3187
87175!#2 N3188 P2005 ST_BINIT 10 0x1000001 Int BE Pri
87176!#2 N3189 P2006 MEMBAR
87177!#2 N3190 P2007 SWAP 5 0xffffffff 0x1000002 Int BE Pri
87178!#2 N3191 P2008 ST_BINIT 6 0x1000003 Int BE Pri
87179!#2 N3192 P2009 MEMBAR
87180!#2 N3193 P2010 ST_BINIT 18 0x1000004 Int BE Pri
87181!#2 N3194 P2011 MEMBAR
87182!#2 N3195 P2012 ST 7 0x1000005 Int BE Pri
87183!#2 N3196 P2013 ST_BINIT 4 0x1000006 Int BE Pri
87184!#2 N3197 P2014 MEMBAR
87185!#2 N3198 P2015 DWLD 8 -1,0x0 Int BE Pri
87186!#2 N3199 P2015 CASX 8 -1,0x0 N3198 0x1000007 Int BE Pri
87187!#2 N3200 P2016 PREFETCH 10 Int BE Pri
87188!#2 N3201 P2017 MEMBAR
87189!#2 N3202 P2018 BLD 18 -1 FP BE Pri
87190!#2 N3203 P2018 BLD 19 -1 FP BE Pri
87191!#A N3202 N3203
87192!#2 N3204 P2018 BLD 20 -1 FP BE Pri
87193!#2 N3205 P2019 MEMBAR
87194!#2 N3206 P2020 BSTC 18 0x40800001 FP BE Pri
87195!#2 N3207 P2020 BSTC 19 0x40800002 FP BE Pri
87196!#A N3206 N3207
87197!#2 N3208 P2020 BSTC 20 0x40800003 FP BE Pri
87198!#2 N3209 P2021 MEMBAR
87199!#2 N3210 P2022 ST 7 0x1000008 Int BE Pri
87200!#2 N3211 P2023 LDD 12 -1 Int BE Pri
87201!#2 N3212 P2023 LDD 13 -1 Int BE Pri
87202!#A N3211 N3212
87203!#2 N3213 P2024 LD 3 -1 Int BE Pri
87204!#2 N3214 P2025 DWST 0 0x1000009 Int BE Pri
87205!#2 N3215 P2025 DWST 1 0x100000a Int BE Pri
87206!#A N3214 N3215
87207!#2 N3216 P2026 ST 21 0x100000b Int BE Pri
87208!#2 N3217 P2027 REPLACEMENT 15 Int BE Pri
87209!#2 N3218 P2028 MEMBAR
87210!#2 N3219 P2029 BST 21 0x40800004 FP BE Pri
87211!#2 N3220 P2029 BST 22 0x40800005 FP BE Pri
87212!#A N3219 N3220
87213!#2 N3221 P2029 BST 23 0x40800006 FP BE Pri
87214!#2 N3222 P2030 MEMBAR
87215!#2 N3223 P2031 LDD 3 -1 Int BE Pri
87216!#2 N3224 P2031 LDD 4 -1 Int BE Pri
87217!#A N3223 N3224
87218!#2 N3225 P2032 PREFETCH 7 Int BE Pri
87219!#2 N3226 P2033 LDD 15 -1 Int BE Pri
87220!#2 N3227 P2033 LDD 16 -1 Int BE Pri
87221!#A N3226 N3227
87222!#2 N3228 P2034 MEMBAR
87223!#2 N3229 P2035 BSTC 12 0x40800007 FP BE Pri
87224!#2 N3230 P2035 BSTC 13 0x40800008 FP BE Pri
87225!#A N3229 N3230
87226!#2 N3231 P2035 BSTC 14 0x40800009 FP BE Pri
87227!#2 N3232 P2036 MEMBAR
87228!#2 N3233 P2037 LD 5 -1 Int BE Pri
87229!#2 N3234 P2037 CAS 5 -1 N3233 0x100000c Int BE Pri
87230!#2 N3235 P2038 MEMBAR
87231!#2 N3236 P2039 BST 15 0x4080000a FP BE Pri
87232!#2 N3237 P2039 BST 16 0x4080000b FP BE Pri
87233!#A N3236 N3237
87234!#2 N3238 P2039 BST 17 0x4080000c FP BE Pri
87235!#2 N3239 P2040 MEMBAR
87236!#2 N3240 P2041 REPLACEMENT 7 Int BE Pri
87237!#2 N3241 P2042 ST_BINIT 13 0x100000d Int LE Pri
87238!#2 N3242 P2043 MEMBAR
87239!#2 N3243 P2044 ST 5 0x4080000d FP BE Pri
87240!#2 N3244 P2045 MEMBAR
87241!#2 N3245 P2046 BST 0 0x4080000e FP BE Pri
87242!#2 N3246 P2046 BST 1 0x4080000f FP BE Pri
87243!#A N3245 N3246
87244!#2 N3247 P2046 BST 2 0x40800010 FP BE Pri
87245!#2 N3248 P2047 MEMBAR
87246!#2 N3249 P2048 REPLACEMENT 15 Int BE Pri
87247!#2 N3250 P2049 LD 14 -1 Int BE Pri
87248!#2 N3251 P2049 CAS 14 -1 N3250 0x100000e Int BE Pri
87249!#2 N3252 P2050 MEMBAR
87250!#2 N3253 P2051 BSTC 3 0x40800011 FP BE Pri
87251!#2 N3254 P2051 BSTC 4 0x40800012 FP BE Pri
87252!#A N3253 N3254
87253!#2 N3255 P2051 BSTC 5 0x40800013 FP BE Pri
87254!#2 N3256 P2052 MEMBAR
87255!#2 N3257 P2053 DWLD 17 -1,0x0 Int BE Pri
87256!#2 N3258 P2053 CASX 17 -1,0x0 N3257 0x100000f Int BE Pri
87257!#2 N3259 P2054 ST_BINIT 7 0x1000010 Int BE Pri
87258!#2 N3260 P2055 MEMBAR
87259!#2 N3261 P2056 SWAP 10 0xffffffff 0x1000011 Int BE Pri
87260!#2 N3262 P2057 SWAP 12 0xffffffff 0x1000012 Int BE Pri
87261!#2 N3263 P2058 DWST_BINIT 9 0x1000013 Int BE Pri
87262!#2 N3264 P2058 DWST_BINIT 10 0x1000014 Int BE Pri
87263!#A N3263 N3264
87264!#2 N3265 P2059 MEMBAR
87265!#2 N3266 P2060 SWAP 1 0xffffffff 0x1000015 Int BE Pri
87266!#2 N3267 P2061 PREFETCH 1 Int BE Pri
87267!#2 N3268 P2062 ST 23 0x40800014 FP BE Pri
87268!#2 N3269 P2063 DWST 0 0x1000016 Int BE Pri
87269!#2 N3270 P2063 DWST 1 0x1000017 Int BE Pri
87270!#A N3269 N3270
87271!#2 N3271 P2064 DWST 0 0x1000018 Int BE Pri
87272!#2 N3272 P2064 DWST 1 0x1000019 Int BE Pri
87273!#A N3271 N3272
87274!#2 N3273 P2065 DWST_BINIT 3 0x100001a Int BE Pri
87275!#2 N3274 P2065 DWST_BINIT 4 0x100001b Int BE Pri
87276!#A N3273 N3274
87277!#2 N3275 P2066 MEMBAR
87278!#2 N3276 P2067 DWLD 21 -1 Int BE Pri
87279!#2 N3277 P2067 DWLD 22 -1 Int BE Pri
87280!#A N3276 N3277
87281!#2 N3278 P2067 CASX 21 -1 N3276 0x100001c Int BE Pri
87282!#2 N3279 P2067 CASX 22 -1 N3277 0x100001d Int BE Pri
87283!#A N3278 N3279
87284!#2 N3280 P2068 SWAP 16 0xffffffff 0x100001e Int BE Pri
87285!#2 N3281 P2069 DWLD 0 -1 Int BE Pri
87286!#2 N3282 P2069 DWLD 1 -1 Int BE Pri
87287!#A N3281 N3282
87288!#2 N3283 P2070 DWLD 12 -1 Int BE Pri
87289!#2 N3284 P2070 DWLD 13 -1 Int BE Pri
87290!#A N3283 N3284
87291!#2 N3285 P2071 LD 18 -1 Int BE Pri
87292!#2 N3286 P2071 CAS 18 -1 N3285 0x100001f Int BE Pri
87293!#2 N3287 P2072 SWAP 1 0xffffffff 0x1000020 Int BE Pri
87294!#2 N3288 P2073 DWST 14 0x1000021 Int BE Pri
87295!#2 N3289 P2074 ST 23 0x1000022 Int BE Pri
87296!#2 N3290 P2075 MEMBAR
87297!#2 N3291 P2076 BST 12 0x40800015 FP BE Pri
87298!#2 N3292 P2076 BST 13 0x40800016 FP BE Pri
87299!#A N3291 N3292
87300!#2 N3293 P2076 BST 14 0x40800017 FP BE Pri
87301!#2 N3294 P2077 MEMBAR
87302!#2 N3295 P2078 SWAP 18 0xffffffff 0x1000023 Int BE Pri
87303!#2 N3296 P2079 ST 4 0x40800018 FP BE Pri
87304!#2 N3297 P2080 DWST_BINIT 14 0x1000024 Int BE Pri
87305!#2 N3298 P2081 MEMBAR
87306!#2 N3299 P2082 DWLD 2 -1,0x0 Int BE Pri
87307!#2 N3300 P2082 CASX 2 -1,0x0 N3299 0x1000025 Int BE Pri
87308!#2 N3301 P2083 MEMBAR
87309!#2 N3302 P2084 BSTC 15 0x40800019 FP BE Pri
87310!#2 N3303 P2084 BSTC 16 0x4080001a FP BE Pri
87311!#A N3302 N3303
87312!#2 N3304 P2084 BSTC 17 0x4080001b FP BE Pri
87313!#2 N3305 P2085 MEMBAR
87314!#2 N3306 P2086 DWLD 11 -1 Int BE Pri
87315!#2 N3307 P2087 ST 23 0x1000026 Int BE Pri
87316!#2 N3308 P2088 MEMBAR
87317!#2 N3309 P2089 BSTC 12 0x4080001c FP BE Pri
87318!#2 N3310 P2089 BSTC 13 0x4080001d FP BE Pri
87319!#A N3309 N3310
87320!#2 N3311 P2089 BSTC 14 0x4080001e FP BE Pri
87321!#2 N3312 P2090 MEMBAR
87322!#2 N3313 P2091 ST 4 0x1000027 Int BE Pri
87323!#2 N3314 P2092 ST_BINIT 6 0x1000028 Int BE Pri
87324!#2 N3315 P2093 MEMBAR
87325!#2 N3316 P2094 SWAP 7 0xffffffff 0x1000029 Int BE Pri
87326!#2 N3317 P2095 DWLD 0 -1 Int BE Pri
87327!#2 N3318 P2095 DWLD 1 -1 Int BE Pri
87328!#A N3317 N3318
87329!#2 N3319 P2096 MEMBAR
87330!#2 N3320 P2097 BSTC 21 0x4080001f FP BE Pri
87331!#2 N3321 P2097 BSTC 22 0x40800020 FP BE Pri
87332!#A N3320 N3321
87333!#2 N3322 P2097 BSTC 23 0x40800021 FP BE Pri
87334!#2 N3323 P2098 MEMBAR
87335!#2 N3324 P2099 PREFETCH 22 Int BE Pri
87336!#2 N3325 P2100 SWAP 7 0xffffffff 0x100002a Int BE Pri
87337!#2 N3326 P2101 LD 12 -1 Int BE Pri
87338!#2 N3327 P2101 CAS 12 -1 N3326 0x100002b Int BE Pri
87339!#2 N3328 P2102 MEMBAR
87340!#2 N3329 P2103 BLD 9 -1 FP BE Pri
87341!#2 N3330 P2103 BLD 10 -1 FP BE Pri
87342!#A N3329 N3330
87343!#2 N3331 P2103 BLD 11 -1 FP BE Pri
87344!#2 N3332 P2104 MEMBAR
87345!#2 N3333 P2105 PREFETCH 10 Int BE Pri
87346!#2 N3334 P2106 MEMBAR
87347!#2 N3335 P2107 BSTC 18 0x40800022 FP BE Pri
87348!#2 N3336 P2107 BSTC 19 0x40800023 FP BE Pri
87349!#A N3335 N3336
87350!#2 N3337 P2107 BSTC 20 0x40800024 FP BE Pri
87351!#2 N3338 P2108 MEMBAR
87352!#2 N3339 P2109 REPLACEMENT 16 Int BE Pri
87353!#2 N3340 P2110 ST_BINIT 12 0x100002c Int BE Pri
87354!#2 N3341 P2111 MEMBAR
87355!#2 N3342 P2112 BST 12 0x40800025 FP BE Pri
87356!#2 N3343 P2112 BST 13 0x40800026 FP BE Pri
87357!#A N3342 N3343
87358!#2 N3344 P2112 BST 14 0x40800027 FP BE Pri
87359!#2 N3345 P2113 MEMBAR
87360!#2 N3346 P2114 BLD 21 -1 FP BE Pri
87361!#2 N3347 P2114 BLD 22 -1 FP BE Pri
87362!#A N3346 N3347
87363!#2 N3348 P2114 BLD 23 -1 FP BE Pri
87364!#2 N3349 P2115 MEMBAR
87365!#2 N3350 P2116 LD 21 -1 Int BE Pri
87366!#2 N3351 P2116 CAS 21 -1 N3350 0x100002d Int BE Pri
87367!#2 N3352 P2117 DWST_BINIT 3 0x100002e Int BE Pri
87368!#2 N3353 P2117 DWST_BINIT 4 0x100002f Int BE Pri
87369!#A N3352 N3353
87370!#2 N3354 P2118 MEMBAR
87371!#2 N3355 P2119 BSTC 12 0x40800028 FP BE Pri
87372!#2 N3356 P2119 BSTC 13 0x40800029 FP BE Pri
87373!#A N3355 N3356
87374!#2 N3357 P2119 BSTC 14 0x4080002a FP BE Pri
87375!#2 N3358 P2120 MEMBAR
87376!#2 N3359 P2121 BSTC 9 0x4080002b FP BE Pri
87377!#2 N3360 P2121 BSTC 10 0x4080002c FP BE Pri
87378!#A N3359 N3360
87379!#2 N3361 P2121 BSTC 11 0x4080002d FP BE Pri
87380!#2 N3362 P2122 MEMBAR
87381!#2 N3363 P2123 LD 4 -1 Int BE Pri
87382!#2 N3364 P2124 LD 6 -1 Int BE Pri
87383!#2 N3365 P2125 LD 20 -1 Int BE Pri
87384!#2 N3366 P2126 DWLD 12 -1 Int BE Pri
87385!#2 N3367 P2126 DWLD 13 -1 Int BE Pri
87386!#A N3366 N3367
87387!#2 N3368 P2126 CASX 12 -1 N3366 0x1000030 Int BE Pri
87388!#2 N3369 P2126 CASX 13 -1 N3367 0x1000031 Int BE Pri
87389!#A N3368 N3369
87390!#2 N3370 P2127 ST_BINIT 1 0x1000032 Int BE Pri
87391!#2 N3371 P2128 MEMBAR
87392!#2 N3372 P2129 BLD 0 -1 FP BE Pri
87393!#2 N3373 P2129 BLD 1 -1 FP BE Pri
87394!#A N3372 N3373
87395!#2 N3374 P2129 BLD 2 -1 FP BE Pri
87396!#2 N3375 P2130 MEMBAR
87397!#2 N3376 P2131 DWST 0 0x1000033 Int BE Pri
87398!#2 N3377 P2131 DWST 1 0x1000034 Int BE Pri
87399!#A N3376 N3377
87400!#2 N3378 P2132 DWLD 18 -1 Int BE Pri
87401!#2 N3379 P2132 DWLD 19 -1 Int BE Pri
87402!#A N3378 N3379
87403!#2 N3380 P2133 DWLD 3 -1 Int BE Pri
87404!#2 N3381 P2133 DWLD 4 -1 Int BE Pri
87405!#A N3380 N3381
87406!#2 N3382 P2133 CASX 3 -1 N3380 0x1000035 Int BE Pri
87407!#2 N3383 P2133 CASX 4 -1 N3381 0x1000036 Int BE Pri
87408!#A N3382 N3383
87409!#2 N3384 P2134 LD 21 -1 Int BE Pri
87410!#2 N3385 P2134 CAS 21 -1 N3384 0x1000037 Int BE Pri
87411!#2 N3386 P2135 MEMBAR
87412!#2 N3387 P2136 BST 6 0x4080002e FP BE Pri
87413!#2 N3388 P2136 BST 7 0x4080002f FP BE Pri
87414!#A N3387 N3388
87415!#2 N3389 P2136 BST 8 0x40800030 FP BE Pri
87416!#2 N3390 P2137 MEMBAR
87417!#2 N3391 P2138 SWAP 0 0xffffffff 0x1000038 Int LE Pri
87418!#2 N3392 P2139 DWLD 23 -1,0x0 Int BE Pri
87419!#2 N3393 P2139 CASX 23 -1,0x0 N3392 0x1000039 Int BE Pri
87420!#2 N3394 P2140 LD 6 -1 Int BE Pri
87421!#2 N3395 P2140 CAS 6 -1 N3394 0x100003a Int BE Pri
87422!#2 N3396 P2141 ST 11 0x100003b Int BE Pri
87423!#2 N3397 P2142 LDD 8 -1 Int BE Pri
87424!#2 N3398 P2143 MEMBAR
87425!#2 N3399 P2144 BLD 3 -1 FP BE Pri
87426!#2 N3400 P2144 BLD 4 -1 FP BE Pri
87427!#A N3399 N3400
87428!#2 N3401 P2144 BLD 5 -1 FP BE Pri
87429!#2 N3402 P2145 MEMBAR
87430!#2 N3403 P2146 DWLD 2 -1,0x0 Int BE Pri
87431!#2 N3404 P2146 CASX 2 -1,0x0 N3403 0x100003c Int BE Pri
87432!#2 N3405 P2147 MEMBAR
87433!#2 N3406 P2148 BSTC 9 0x40800031 FP BE Pri
87434!#2 N3407 P2148 BSTC 10 0x40800032 FP BE Pri
87435!#A N3406 N3407
87436!#2 N3408 P2148 BSTC 11 0x40800033 FP BE Pri
87437!#2 N3409 P2149 MEMBAR
87438!#2 N3410 P2150 LDD 15 -1 Int BE Pri
87439!#2 N3411 P2150 LDD 16 -1 Int BE Pri
87440!#A N3410 N3411
87441!#2 N3412 P2151 DWST_BINIT 12 0x100003d Int BE Pri
87442!#2 N3413 P2151 DWST_BINIT 13 0x100003e Int BE Pri
87443!#A N3412 N3413
87444!#2 N3414 P2152 MEMBAR
87445!#2 N3415 P2153 BST 15 0x40800034 FP BE Pri
87446!#2 N3416 P2153 BST 16 0x40800035 FP BE Pri
87447!#A N3415 N3416
87448!#2 N3417 P2153 BST 17 0x40800036 FP BE Pri
87449!#2 N3418 P2154 MEMBAR
87450!#2 N3419 P2155 BST 21 0x40800037 FP BE Pri
87451!#2 N3420 P2155 BST 22 0x40800038 FP BE Pri
87452!#A N3419 N3420
87453!#2 N3421 P2155 BST 23 0x40800039 FP BE Pri
87454!#2 N3422 P2156 MEMBAR
87455!#2 N3423 P2157 DWST_BINIT 12 0x100003f Int BE Pri
87456!#2 N3424 P2157 DWST_BINIT 13 0x1000040 Int BE Pri
87457!#A N3423 N3424
87458!#2 N3425 P2158 MEMBAR
87459!#2 N3426 P2159 LDD 15 -1 Int BE Pri
87460!#2 N3427 P2159 LDD 16 -1 Int BE Pri
87461!#A N3426 N3427
87462!#2 N3428 P2160 DWST_BINIT 23 0x1000041 Int BE Pri
87463!#2 N3429 P2161 MEMBAR
87464!#2 N3430 P2162 BSTC 12 0x4080003a FP BE Pri
87465!#2 N3431 P2162 BSTC 13 0x4080003b FP BE Pri
87466!#A N3430 N3431
87467!#2 N3432 P2162 BSTC 14 0x4080003c FP BE Pri
87468!#2 N3433 P2163 MEMBAR
87469!#2 N3434 P2164 SWAP 10 0xffffffff 0x1000042 Int BE Pri
87470!#2 N3435 P2165 PREFETCH 18 Int BE Pri
87471!#2 N3436 P2166 MEMBAR
87472!#2 N3437 P2167 BLD 15 -1 FP BE Pri
87473!#2 N3438 P2167 BLD 16 -1 FP BE Pri
87474!#A N3437 N3438
87475!#2 N3439 P2167 BLD 17 -1 FP BE Pri
87476!#2 N3440 P2168 MEMBAR
87477!#2 N3441 P2169 ST 13 0x4080003d FP BE Pri
87478!#2 N3442 P2170 DWST_BINIT 12 0x1000043 Int BE Pri
87479!#2 N3443 P2170 DWST_BINIT 13 0x1000044 Int BE Pri
87480!#A N3442 N3443
87481!#2 N3444 P2171 MEMBAR
87482!#2 N3445 P2172 DWST 12 0x1000045 Int BE Pri
87483!#2 N3446 P2172 DWST 13 0x1000046 Int BE Pri
87484!#A N3445 N3446
87485!#2 N3447 P2173 DWLD 2 -1,0x0 Int BE Pri
87486!#2 N3448 P2173 CASX 2 -1,0x0 N3447 0x1000047 Int BE Pri
87487!#2 N3449 P2174 ST_BINIT 13 0x1000048 Int BE Pri
87488!#2 N3450 P2175 MEMBAR
87489!#2 N3451 P2176 BLD 9 -1 FP BE Pri
87490!#2 N3452 P2176 BLD 10 -1 FP BE Pri
87491!#A N3451 N3452
87492!#2 N3453 P2176 BLD 11 -1 FP BE Pri
87493!#2 N3454 P2177 MEMBAR
87494!#2 N3455 P2178 DWST 15 0x1000049 Int BE Pri
87495!#2 N3456 P2178 DWST 16 0x100004a Int BE Pri
87496!#A N3455 N3456
87497!#2 N3457 P2179 LD 5 -1 Int BE Pri
87498!#2 N3458 P2179 CAS 5 -1 N3457 0x100004b Int BE Pri
87499!#2 N3459 P2180 LD 4 -1 Int BE Pri
87500!#2 N3460 P2181 LD 22 -1 Int BE Pri
87501!#2 N3461 P2181 CAS 22 -1 N3460 0x100004c Int BE Pri
87502!#2 N3462 P2182 DWLD 18 -1 Int BE Pri
87503!#2 N3463 P2182 DWLD 19 -1 Int BE Pri
87504!#A N3462 N3463
87505!#2 N3464 P2183 DWLD 15 -1 Int BE Pri
87506!#2 N3465 P2183 DWLD 16 -1 Int BE Pri
87507!#A N3464 N3465
87508!#2 N3466 P2183 CASX 15 -1 N3464 0x100004d Int BE Pri
87509!#2 N3467 P2183 CASX 16 -1 N3465 0x100004e Int BE Pri
87510!#A N3466 N3467
87511!#2 N3468 P2184 DWLD 9 -1 Int BE Pri
87512!#2 N3469 P2184 DWLD 10 -1 Int BE Pri
87513!#A N3468 N3469
87514!#2 N3470 P2185 ST_BINIT 19 0x100004f Int BE Pri
87515!#2 N3471 P2186 MEMBAR
87516!#2 N3472 P2187 SWAP 21 0xffffffff 0x1000050 Int BE Pri
87517!#2 N3473 P2188 DWLD 18 -1 FP BE Pri
87518!#2 N3474 P2188 DWLD 19 -1 FP BE Pri
87519!#A N3473 N3474
87520!#2 N3475 P2189 MEMBAR
87521!#2 N3476 P2190 BST 0 0x4080003e FP BE Pri
87522!#2 N3477 P2190 BST 1 0x4080003f FP BE Pri
87523!#A N3476 N3477
87524!#2 N3478 P2190 BST 2 0x40800040 FP BE Pri
87525!#2 N3479 P2191 MEMBAR
87526!#2 N3480 P2192 LDD 18 -1 Int BE Pri
87527!#2 N3481 P2192 LDD 19 -1 Int BE Pri
87528!#A N3480 N3481
87529!#2 N3482 P2193 DWLD 21 -1 Int BE Pri
87530!#2 N3483 P2193 DWLD 22 -1 Int BE Pri
87531!#A N3482 N3483
87532!#2 N3484 P2193 CASX 21 -1 N3482 0x1000051 Int BE Pri
87533!#2 N3485 P2193 CASX 22 -1 N3483 0x1000052 Int BE Pri
87534!#A N3484 N3485
87535!#2 N3486 P2194 MEMBAR
87536!#2 N3487 P2195 BSTC 12 0x40800041 FP BE Pri
87537!#2 N3488 P2195 BSTC 13 0x40800042 FP BE Pri
87538!#A N3487 N3488
87539!#2 N3489 P2195 BSTC 14 0x40800043 FP BE Pri
87540!#2 N3490 P2196 MEMBAR
87541!#2 N3491 P2197 ST 16 0x1000053 Int LE Pri
87542!#2 N3492 P2198 LDD 15 -1 Int BE Pri
87543!#2 N3493 P2198 LDD 16 -1 Int BE Pri
87544!#A N3492 N3493
87545!#2 N3494 P2199 LD 18 -1 Int BE Pri
87546!#2 N3495 P2199 CAS 18 -1 N3494 0x1000054 Int BE Pri
87547!#2 N3496 P2200 LD 1 -1 FP BE Pri
87548!#2 N3497 P2201 DWST_BINIT 6 0x1000055 Int BE Pri
87549!#2 N3498 P2201 DWST_BINIT 7 0x1000056 Int BE Pri
87550!#A N3497 N3498
87551!#2 N3499 P2202 MEMBAR
87552!#2 N3500 P2203 DWST_BINIT 14 0x1000057 Int BE Pri
87553!#2 N3501 P2204 MEMBAR
87554!#2 N3502 P2205 DWST_BINIT 23 0x1000058 Int BE Pri
87555!#2 N3503 P2206 MEMBAR
87556!#2 N3504 P2207 REPLACEMENT 12 Int BE Pri
87557!#2 N3505 P2208 DWST 12 0x1000059 Int BE Pri
87558!#2 N3506 P2208 DWST 13 0x100005a Int BE Pri
87559!#A N3505 N3506
87560!#2 N3507 P2209 LDD 11 -1 Int BE Pri
87561!#2 N3508 P2210 MEMBAR
87562!#2 N3509 P2211 BLD 0 -1 FP BE Pri
87563!#2 N3510 P2211 BLD 1 -1 FP BE Pri
87564!#A N3509 N3510
87565!#2 N3511 P2211 BLD 2 -1 FP BE Pri
87566!#2 N3512 P2212 MEMBAR
87567!#2 N3513 P2213 BST 21 0x40800044 FP BE Pri
87568!#2 N3514 P2213 BST 22 0x40800045 FP BE Pri
87569!#A N3513 N3514
87570!#2 N3515 P2213 BST 23 0x40800046 FP BE Pri
87571!#2 N3516 P2214 MEMBAR
87572!#2 N3517 P2215 LD 3 -1 Int BE Pri
87573!#2 N3518 P2215 CAS 3 -1 N3517 0x100005b Int BE Pri
87574!#2 N3519 P2216 DWST_BINIT 6 0x100005c Int BE Pri
87575!#2 N3520 P2216 DWST_BINIT 7 0x100005d Int BE Pri
87576!#A N3519 N3520
87577!#2 N3521 P2217 MEMBAR
87578!#2 N3522 P2218 ST_BINIT 23 0x100005e Int BE Pri
87579!#2 N3523 P2219 MEMBAR
87580!#2 N3524 P2220 BLD 9 -1 FP BE Pri
87581!#2 N3525 P2220 BLD 10 -1 FP BE Pri
87582!#A N3524 N3525
87583!#2 N3526 P2220 BLD 11 -1 FP BE Pri
87584!#2 N3527 P2221 MEMBAR
87585!#2 N3528 P2222 LD 8 -1 Int BE Pri
87586!#2 N3529 P2222 CAS 8 -1 N3528 0x100005f Int BE Pri
87587!#2 N3530 P2223 MEMBAR
87588!#2 N3531 P2224 BST 15 0x40800047 FP BE Pri
87589!#2 N3532 P2224 BST 16 0x40800048 FP BE Pri
87590!#A N3531 N3532
87591!#2 N3533 P2224 BST 17 0x40800049 FP BE Pri
87592!#2 N3534 P2225 MEMBAR
87593!#2 N3535 P2226 BST 15 0x4080004a FP BE Pri
87594!#2 N3536 P2226 BST 16 0x4080004b FP BE Pri
87595!#A N3535 N3536
87596!#2 N3537 P2226 BST 17 0x4080004c FP BE Pri
87597!#2 N3538 P2227 MEMBAR
87598!#2 N3539 P2228 BST 0 0x4080004d FP BE Pri
87599!#2 N3540 P2228 BST 1 0x4080004e FP BE Pri
87600!#A N3539 N3540
87601!#2 N3541 P2228 BST 2 0x4080004f FP BE Pri
87602!#2 N3542 P2229 MEMBAR
87603!#2 N3543 P2230 ST_BINIT 1 0x1000060 Int BE Pri
87604!#2 N3544 P2231 MEMBAR
87605!#2 N3545 P2232 DWLD 6 -1 Int LE Pri
87606!#2 N3546 P2232 DWLD 7 -1 Int LE Pri
87607!#A N3545 N3546
87608!#2 N3547 P2233 ST_BINIT 5 0x1000061 Int BE Pri
87609!#2 N3548 P2234 MEMBAR
87610!#2 N3549 P2235 ST 16 0x1000062 Int BE Pri
87611!#2 N3550 P2236 DWLD 2 -1 FP BE Pri
87612!#2 N3551 P2237 ST_BINIT 15 0x1000063 Int BE Pri
87613!#2 N3552 P2238 MEMBAR
87614!#2 N3553 P2239 DWST 15 0x1000064 Int BE Pri
87615!#2 N3554 P2239 DWST 16 0x1000065 Int BE Pri
87616!#A N3553 N3554
87617!#2 N3555 P2240 ST_BINIT 21 0x1000066 Int BE Pri
87618!#2 N3556 P2241 MEMBAR
87619!#2 N3557 P2242 DWLD 12 -1 Int BE Pri
87620!#2 N3558 P2242 DWLD 13 -1 Int BE Pri
87621!#A N3557 N3558
87622!#2 N3559 P2242 CASX 12 -1 N3557 0x1000067 Int BE Pri
87623!#2 N3560 P2242 CASX 13 -1 N3558 0x1000068 Int BE Pri
87624!#A N3559 N3560
87625!#2 N3561 P2243 MEMBAR
87626!#2 N3562 P2244 BLD 6 -1 FP BE Pri
87627!#2 N3563 P2244 BLD 7 -1 FP BE Pri
87628!#A N3562 N3563
87629!#2 N3564 P2244 BLD 8 -1 FP BE Pri
87630!#2 N3565 P2245 MEMBAR
87631!#2 N3566 P2246 BST 9 0x40800050 FP BE Pri
87632!#2 N3567 P2246 BST 10 0x40800051 FP BE Pri
87633!#A N3566 N3567
87634!#2 N3568 P2246 BST 11 0x40800052 FP BE Pri
87635!#2 N3569 P2247 MEMBAR
87636!#2 N3570 P2248 SWAP 23 0xffffffff 0x1000069 Int BE Pri
87637!#2 N3571 P2249 PREFETCH 18 Int LE Pri
87638!#2 N3572 P2250 DWST_BINIT 15 0x100006a Int LE Pri
87639!#2 N3573 P2250 DWST_BINIT 16 0x100006b Int LE Pri
87640!#A N3572 N3573
87641!#2 N3574 P2251 MEMBAR
87642!#2 N3575 P2252 SWAP 4 0xffffffff 0x100006c Int BE Pri
87643!#2 N3576 P2253 DWST 8 0x100006d Int BE Pri
87644!#2 N3577 P2254 PREFETCH 1 Int BE Pri
87645!#2 N3578 P2255 LD 20 -1 Int BE Pri
87646!#2 N3579 P2256 LD 15 -1 Int BE Pri
87647!#2 N3580 P2257 MEMBAR
87648!#2 N3581 P2258 BLD 9 -1 FP BE Pri
87649!#2 N3582 P2258 BLD 10 -1 FP BE Pri
87650!#A N3581 N3582
87651!#2 N3583 P2258 BLD 11 -1 FP BE Pri
87652!#2 N3584 P2259 MEMBAR
87653!#2 N3585 P2260 SWAP 19 0xffffffff 0x100006e Int BE Pri
87654!#2 N3586 P2261 DWLD 21 -1 Int BE Pri
87655!#2 N3587 P2261 DWLD 22 -1 Int BE Pri
87656!#A N3586 N3587
87657!#2 N3588 P2261 CASX 21 -1 N3586 0x100006f Int BE Pri
87658!#2 N3589 P2261 CASX 22 -1 N3587 0x1000070 Int BE Pri
87659!#A N3588 N3589
87660!#2 N3590 P2262 LDD 12 -1 Int BE Pri
87661!#2 N3591 P2262 LDD 13 -1 Int BE Pri
87662!#A N3590 N3591
87663!#2 N3592 P2263 ST 21 0x1000071 Int BE Pri
87664!#2 N3593 P2264 PREFETCH 12 Int BE Pri
87665!#2 N3594 P2265 MEMBAR
87666!#2 N3595 P2266 BSTC 18 0x40800053 FP BE Pri
87667!#2 N3596 P2266 BSTC 19 0x40800054 FP BE Pri
87668!#A N3595 N3596
87669!#2 N3597 P2266 BSTC 20 0x40800055 FP BE Pri
87670!#2 N3598 P2267 MEMBAR
87671!#2 N3599 P2268 LDD 3 -1 Int BE Pri
87672!#2 N3600 P2268 LDD 4 -1 Int BE Pri
87673!#A N3599 N3600
87674!#2 N3601 P2269 MEMBAR
87675!#2 N3602 P2270 BSTC 6 0x40800056 FP BE Pri
87676!#2 N3603 P2270 BSTC 7 0x40800057 FP BE Pri
87677!#A N3602 N3603
87678!#2 N3604 P2270 BSTC 8 0x40800058 FP BE Pri
87679!#2 N3605 P2271 MEMBAR
87680!#2 N3606 P2272 PREFETCH 17 Int BE Pri
87681!#2 N3607 P2273 MEMBAR
87682!#2 N3608 P2274 BLD 3 -1 FP BE Pri
87683!#2 N3609 P2274 BLD 4 -1 FP BE Pri
87684!#A N3608 N3609
87685!#2 N3610 P2274 BLD 5 -1 FP BE Pri
87686!#2 N3611 P2275 MEMBAR
87687!#2 N3612 P2276 DWLD 18 -1 Int BE Pri
87688!#2 N3613 P2276 DWLD 19 -1 Int BE Pri
87689!#A N3612 N3613
87690!#2 N3614 P2277 DWLD 20 -1,0x0 Int BE Pri
87691!#2 N3615 P2277 CASX 20 -1,0x0 N3614 0x1000072 Int BE Pri
87692!#2 N3616 P2278 MEMBAR
87693!#2 N3617 P2279 BSTC 15 0x40800059 FP BE Pri
87694!#2 N3618 P2279 BSTC 16 0x4080005a FP BE Pri
87695!#A N3617 N3618
87696!#2 N3619 P2279 BSTC 17 0x4080005b FP BE Pri
87697!#2 N3620 P2280 MEMBAR
87698!#2 N3621 P2281 PREFETCH 3 Int BE Pri
87699!#2 N3622 P2282 DWLD 11 -1,0x0 Int BE Pri
87700!#2 N3623 P2282 CASX 11 -1,0x0 N3622 0x1000073 Int BE Pri
87701!#2 N3624 P2283 ST 3 0x1000074 Int BE Pri
87702!#2 N3625 P2284 DWLD 20 -1 Int BE Pri
87703!#2 N3626 P2285 DWLD 15 -1 Int BE Pri
87704!#2 N3627 P2285 DWLD 16 -1 Int BE Pri
87705!#A N3626 N3627
87706!#2 N3628 P2286 MEMBAR
87707!#2 N3629 P2287 BSTC 3 0x4080005c FP BE Pri
87708!#2 N3630 P2287 BSTC 4 0x4080005d FP BE Pri
87709!#A N3629 N3630
87710!#2 N3631 P2287 BSTC 5 0x4080005e FP BE Pri
87711!#2 N3632 P2288 MEMBAR
87712!#2 N3633 P2289 LD 1 -1 FP BE Pri
87713!#2 N3634 P2290 LD 1 -1 Int BE Pri
87714!#2 N3635 P2290 CAS 1 -1 N3634 0x1000075 Int BE Pri
87715!#2 N3636 P2291 MEMBAR
87716!#2 N3637 P2292 BST 3 0x4080005f FP BE Pri
87717!#2 N3638 P2292 BST 4 0x40800060 FP BE Pri
87718!#A N3637 N3638
87719!#2 N3639 P2292 BST 5 0x40800061 FP BE Pri
87720!#2 N3640 P2293 MEMBAR
87721!#2 N3641 P2294 BSTC 18 0x40800062 FP BE Pri
87722!#2 N3642 P2294 BSTC 19 0x40800063 FP BE Pri
87723!#A N3641 N3642
87724!#2 N3643 P2294 BSTC 20 0x40800064 FP BE Pri
87725!#2 N3644 P2295 MEMBAR
87726!#2 N3645 P2296 BLD 18 -1 FP BE Pri
87727!#2 N3646 P2296 BLD 19 -1 FP BE Pri
87728!#A N3645 N3646
87729!#2 N3647 P2296 BLD 20 -1 FP BE Pri
87730!#2 N3648 P2297 MEMBAR
87731!#2 N3649 P2298 PREFETCH 3 Int BE Pri
87732!#2 N3650 P2299 LD 8 -1 Int BE Pri
87733!#2 N3651 P2299 CAS 8 -1 N3650 0x1000076 Int BE Pri
87734!#2 N3652 P2300 MEMBAR
87735!#2 N3653 P2301 BST 12 0x40800065 FP BE Pri
87736!#2 N3654 P2301 BST 13 0x40800066 FP BE Pri
87737!#A N3653 N3654
87738!#2 N3655 P2301 BST 14 0x40800067 FP BE Pri
87739!#2 N3656 P2302 MEMBAR
87740!#2 N3657 P2303 PREFETCH 16 Int BE Pri
87741!#2 N3658 P2304 MEMBAR
87742!#2 N3659 P2305 BLD 9 -1 FP BE Pri
87743!#2 N3660 P2305 BLD 10 -1 FP BE Pri
87744!#A N3659 N3660
87745!#2 N3661 P2305 BLD 11 -1 FP BE Pri
87746!#2 N3662 P2306 MEMBAR
87747!#2 N3663 P2307 BST 15 0x40800068 FP BE Pri
87748!#2 N3664 P2307 BST 16 0x40800069 FP BE Pri
87749!#A N3663 N3664
87750!#2 N3665 P2307 BST 17 0x4080006a FP BE Pri
87751!#2 N3666 P2308 MEMBAR
87752!#2 N3667 P2309 BLD 6 -1 FP BE Pri
87753!#2 N3668 P2309 BLD 7 -1 FP BE Pri
87754!#A N3667 N3668
87755!#2 N3669 P2309 BLD 8 -1 FP BE Pri
87756!#2 N3670 P2310 MEMBAR
87757!#2 N3671 P2311 LD 15 -1 Int BE Pri
87758!#2 N3672 P2312 DWST 14 0x1000077 Int BE Pri
87759!#2 N3673 P2313 DWLD 21 -1 Int BE Pri
87760!#2 N3674 P2313 DWLD 22 -1 Int BE Pri
87761!#A N3673 N3674
87762!#2 N3675 P2313 CASX 21 -1 N3673 0x1000078 Int BE Pri
87763!#2 N3676 P2313 CASX 22 -1 N3674 0x1000079 Int BE Pri
87764!#A N3675 N3676
87765!#2 N3677 P2314 DWST_BINIT 15 0x100007a Int BE Pri
87766!#2 N3678 P2314 DWST_BINIT 16 0x100007b Int BE Pri
87767!#A N3677 N3678
87768!#2 N3679 P2315 MEMBAR
87769!#2 N3680 P2316 DWST_BINIT 17 0x100007c Int BE Pri
87770!#2 N3681 P2317 MEMBAR
87771!#2 N3682 P2318 ST 19 0x4080006b FP BE Pri
87772!#2 N3683 P2319 DWST 20 0x100007d Int BE Pri
87773!#2 N3684 P2320 DWST_BINIT 3 0x100007e Int BE Pri
87774!#2 N3685 P2320 DWST_BINIT 4 0x100007f Int BE Pri
87775!#A N3684 N3685
87776!#2 N3686 P2321 MEMBAR
87777!#2 N3687 P2322 SWAP 11 0xffffffff 0x1000080 Int BE Pri
87778!#2 N3688 P2323 PREFETCH 23 Int BE Pri
87779!#2 N3689 P2324 MEMBAR
87780!#2 N3690 P2325 BSTC 9 0x4080006c FP BE Pri
87781!#2 N3691 P2325 BSTC 10 0x4080006d FP BE Pri
87782!#A N3690 N3691
87783!#2 N3692 P2325 BSTC 11 0x4080006e FP BE Pri
87784!#2 N3693 P2326 MEMBAR
87785!#2 N3694 P2327 BST 6 0x4080006f FP BE Pri
87786!#2 N3695 P2327 BST 7 0x40800070 FP BE Pri
87787!#A N3694 N3695
87788!#2 N3696 P2327 BST 8 0x40800071 FP BE Pri
87789!#2 N3697 P2328 MEMBAR
87790!#2 N3698 P2329 LDD 12 -1 Int BE Pri
87791!#2 N3699 P2329 LDD 13 -1 Int BE Pri
87792!#A N3698 N3699
87793!#2 N3700 P2330 PREFETCH 22 Int BE Pri
87794!#2 N3701 P2331 LDD 8 -1 Int BE Pri
87795!#2 N3702 P2332 DWST 2 0x1000081 Int BE Pri
87796!#2 N3703 P2333 MEMBAR
87797!#2 N3704 P2334 BLD 15 -1 FP BE Pri
87798!#2 N3705 P2334 BLD 16 -1 FP BE Pri
87799!#A N3704 N3705
87800!#2 N3706 P2334 BLD 17 -1 FP BE Pri
87801!#2 N3707 P2335 MEMBAR
87802!#2 N3708 P2336 DWLD 18 -1 Int BE Pri
87803!#2 N3709 P2336 DWLD 19 -1 Int BE Pri
87804!#A N3708 N3709
87805!#2 N3710 P2337 MEMBAR
87806!#2 N3711 P2338 BLD 21 -1 FP BE Pri
87807!#2 N3712 P2338 BLD 22 -1 FP BE Pri
87808!#A N3711 N3712
87809!#2 N3713 P2338 BLD 23 -1 FP BE Pri
87810!#2 N3714 P2339 MEMBAR
87811!#2 N3715 P2340 PREFETCH 15 Int BE Pri
87812!#2 N3716 P2341 DWLD 3 -1 Int BE Pri
87813!#2 N3717 P2341 DWLD 4 -1 Int BE Pri
87814!#A N3716 N3717
87815!#2 N3718 P2342 DWST_BINIT 3 0x1000082 Int BE Pri
87816!#2 N3719 P2342 DWST_BINIT 4 0x1000083 Int BE Pri
87817!#A N3718 N3719
87818!#2 N3720 P2343 MEMBAR
87819!#2 N3721 P2344 LD 7 -1 Int BE Pri
87820!#2 N3722 P2344 CAS 7 -1 N3721 0x1000084 Int BE Pri
87821!#2 N3723 P2345 MEMBAR
87822!#2 N3724 P2346 BSTC 6 0x40800072 FP BE Pri
87823!#2 N3725 P2346 BSTC 7 0x40800073 FP BE Pri
87824!#A N3724 N3725
87825!#2 N3726 P2346 BSTC 8 0x40800074 FP BE Pri
87826!#2 N3727 P2347 MEMBAR
87827!#2 N3728 P2348 BST 15 0x40800075 FP BE Pri
87828!#2 N3729 P2348 BST 16 0x40800076 FP BE Pri
87829!#A N3728 N3729
87830!#2 N3730 P2348 BST 17 0x40800077 FP BE Pri
87831!#2 N3731 P2349 MEMBAR
87832!#2 N3732 P2350 ST 1 0x40800078 FP BE Pri
87833!#2 N3733 P2351 SWAP 5 0xffffffff 0x1000085 Int BE Pri
87834!#2 N3734 P2352 LDD 9 -1 Int BE Pri
87835!#2 N3735 P2352 LDD 10 -1 Int BE Pri
87836!#A N3734 N3735
87837!#2 N3736 P2353 ST 1 0x1000086 Int BE Pri
87838!#2 N3737 P2354 ST_BINIT 2 0x1000087 Int BE Pri
87839!#2 N3738 P2355 MEMBAR
87840!#2 N3739 P2356 DWLD 18 -1 Int BE Pri
87841!#2 N3740 P2356 DWLD 19 -1 Int BE Pri
87842!#A N3739 N3740
87843!#2 N3741 P2357 LDD 0 -1 Int BE Pri
87844!#2 N3742 P2357 LDD 1 -1 Int BE Pri
87845!#A N3741 N3742
87846!#2 N3743 P2358 LDD 21 -1 Int BE Pri
87847!#2 N3744 P2358 LDD 22 -1 Int BE Pri
87848!#A N3743 N3744
87849!#2 N3745 P2359 ST_BINIT 16 0x1000088 Int BE Pri
87850!#2 N3746 P2360 MEMBAR
87851!#2 N3747 P2361 LDD 0 -1 Int BE Pri
87852!#2 N3748 P2361 LDD 1 -1 Int BE Pri
87853!#A N3747 N3748
87854!#2 N3749 P2362 DWLD 18 -1 Int BE Pri
87855!#2 N3750 P2362 DWLD 19 -1 Int BE Pri
87856!#A N3749 N3750
87857!#2 N3751 P2363 MEMBAR
87858!#2 N3752 P2364 BST 3 0x40800079 FP BE Pri
87859!#2 N3753 P2364 BST 4 0x4080007a FP BE Pri
87860!#A N3752 N3753
87861!#2 N3754 P2364 BST 5 0x4080007b FP BE Pri
87862!#2 N3755 P2365 MEMBAR
87863!#2 N3756 P2366 DWLD 9 -1 Int BE Pri
87864!#2 N3757 P2366 DWLD 10 -1 Int BE Pri
87865!#A N3756 N3757
87866!#2 N3758 P2367 ST 1 0x4080007c FP BE Pri
87867!#2 N3759 P2368 MEMBAR
87868!#2 N3760 P2369 BST 18 0x4080007d FP BE Pri
87869!#2 N3761 P2369 BST 19 0x4080007e FP BE Pri
87870!#A N3760 N3761
87871!#2 N3762 P2369 BST 20 0x4080007f FP BE Pri
87872!#2 N3763 P2370 MEMBAR
87873!#2 N3764 P2371 SWAP 20 0xffffffff 0x1000089 Int BE Pri
87874!#2 N3765 P2372 LDD 9 -1 Int BE Pri
87875!#2 N3766 P2372 LDD 10 -1 Int BE Pri
87876!#A N3765 N3766
87877!#2 N3767 P2373 PREFETCH 9 Int BE Pri
87878!#2 N3768 P2374 LD 12 -1 Int BE Pri
87879!#2 N3769 P2375 LD 10 -1 FP BE Pri
87880!#2 N3770 P2376 LD 13 -1 Int BE Pri
87881!#2 N3771 P2376 CAS 13 -1 N3770 0x100008a Int BE Pri
87882!#2 N3772 P2377 MEMBAR
87883!#2 N3773 P2378 BST 3 0x40800080 FP BE Pri
87884!#2 N3774 P2378 BST 4 0x40800081 FP BE Pri
87885!#A N3773 N3774
87886!#2 N3775 P2378 BST 5 0x40800082 FP BE Pri
87887!#2 N3776 P2379 MEMBAR
87888!#2 N3777 P2380 PREFETCH 13 Int BE Pri
87889!#2 N3778 P2381 PREFETCH 18 Int BE Pri
87890!#2 N3779 P2382 LD 23 -1 Int BE Pri
87891!#2 N3780 P2383 DWLD 12 -1 Int BE Pri
87892!#2 N3781 P2383 DWLD 13 -1 Int BE Pri
87893!#A N3780 N3781
87894!#2 N3782 P2383 CASX 12 -1 N3780 0x100008b Int BE Pri
87895!#2 N3783 P2383 CASX 13 -1 N3781 0x100008c Int BE Pri
87896!#A N3782 N3783
87897!#2 N3784 P2384 MEMBAR
87898!#2 N3785 P2385 BLD 0 -1 FP BE Pri
87899!#2 N3786 P2385 BLD 1 -1 FP BE Pri
87900!#A N3785 N3786
87901!#2 N3787 P2385 BLD 2 -1 FP BE Pri
87902!#2 N3788 P2386 MEMBAR
87903!#2 N3789 P2387 BSTC 12 0x40800083 FP BE Pri
87904!#2 N3790 P2387 BSTC 13 0x40800084 FP BE Pri
87905!#A N3789 N3790
87906!#2 N3791 P2387 BSTC 14 0x40800085 FP BE Pri
87907!#2 N3792 P2388 MEMBAR
87908!#2 N3793 P2389 BSTC 12 0x40800086 FP BE Pri
87909!#2 N3794 P2389 BSTC 13 0x40800087 FP BE Pri
87910!#A N3793 N3794
87911!#2 N3795 P2389 BSTC 14 0x40800088 FP BE Pri
87912!#2 N3796 P2390 MEMBAR
87913!#2 N3797 P2391 BSTC 0 0x40800089 FP BE Pri
87914!#2 N3798 P2391 BSTC 1 0x4080008a FP BE Pri
87915!#A N3797 N3798
87916!#2 N3799 P2391 BSTC 2 0x4080008b FP BE Pri
87917!#2 N3800 P2392 MEMBAR
87918!#2 N3801 P2393 ST 23 0x100008d Int BE Pri
87919!#2 N3802 P2394 DWST_BINIT 5 0x100008e Int BE Pri
87920!#2 N3803 P2395 MEMBAR
87921!#2 N3804 P2396 BLD 18 -1 FP BE Pri
87922!#2 N3805 P2396 BLD 19 -1 FP BE Pri
87923!#A N3804 N3805
87924!#2 N3806 P2396 BLD 20 -1 FP BE Pri
87925!#2 N3807 P2397 MEMBAR
87926!#2 N3808 P2398 DWLD 6 -1 Int BE Pri
87927!#2 N3809 P2398 DWLD 7 -1 Int BE Pri
87928!#A N3808 N3809
87929!#2 N3810 P2398 CASX 6 -1 N3808 0x100008f Int BE Pri
87930!#2 N3811 P2398 CASX 7 -1 N3809 0x1000090 Int BE Pri
87931!#A N3810 N3811
87932!#2 N3812 P2399 MEMBAR
87933!#2 N3813 P2400 BST 21 0x4080008c FP BE Pri
87934!#2 N3814 P2400 BST 22 0x4080008d FP BE Pri
87935!#A N3813 N3814
87936!#2 N3815 P2400 BST 23 0x4080008e FP BE Pri
87937!#2 N3816 P2401 MEMBAR
87938!#2 N3817 P2402 BSTC 15 0x4080008f FP BE Pri
87939!#2 N3818 P2402 BSTC 16 0x40800090 FP BE Pri
87940!#A N3817 N3818
87941!#2 N3819 P2402 BSTC 17 0x40800091 FP BE Pri
87942!#2 N3820 P2403 MEMBAR
87943!#2 N3821 P2404 BLD 6 -1 FP BE Pri
87944!#2 N3822 P2404 BLD 7 -1 FP BE Pri
87945!#A N3821 N3822
87946!#2 N3823 P2404 BLD 8 -1 FP BE Pri
87947!#2 N3824 P2405 MEMBAR
87948!#2 N3825 P2406 BLD 15 -1 FP BE Pri
87949!#2 N3826 P2406 BLD 16 -1 FP BE Pri
87950!#A N3825 N3826
87951!#2 N3827 P2406 BLD 17 -1 FP BE Pri
87952!#2 N3828 P2407 MEMBAR
87953!#2 N3829 P2408 ST 19 0x1000091 Int BE Pri
87954!#2 N3830 P2409 MEMBAR
87955!#2 N3831 P2410 BLD 12 -1 FP BE Pri
87956!#2 N3832 P2410 BLD 13 -1 FP BE Pri
87957!#A N3831 N3832
87958!#2 N3833 P2410 BLD 14 -1 FP BE Pri
87959!#2 N3834 P2411 MEMBAR
87960!#2 N3835 P2412 ST_BINIT 6 0x1000092 Int BE Pri
87961!#2 N3836 P2413 MEMBAR
87962!#2 N3837 P2414 PREFETCH 2 Int BE Pri
87963!#2 N3838 P2415 DWLD 20 -1 Int BE Pri
87964!#2 N3839 P2416 SWAP 22 0xffffffff 0x1000093 Int BE Pri
87965!#2 N3840 P2417 MEMBAR
87966!#2 N3841 P2418 BST 6 0x40800092 FP BE Pri
87967!#2 N3842 P2418 BST 7 0x40800093 FP BE Pri
87968!#A N3841 N3842
87969!#2 N3843 P2418 BST 8 0x40800094 FP BE Pri
87970!#2 N3844 P2419 MEMBAR
87971!#2 N3845 P2420 DWLD 5 -1,0x0 Int BE Pri
87972!#2 N3846 P2420 CASX 5 -1,0x0 N3845 0x1000094 Int BE Pri
87973!#2 N3847 P2421 MEMBAR
87974!#2 N3848 P2422 BST 6 0x40800095 FP BE Pri
87975!#2 N3849 P2422 BST 7 0x40800096 FP BE Pri
87976!#A N3848 N3849
87977!#2 N3850 P2422 BST 8 0x40800097 FP BE Pri
87978!#2 N3851 P2423 MEMBAR
87979!#2 N3852 P2424 SWAP 6 0xffffffff 0x1000095 Int BE Pri
87980!#2 N3853 P2425 DWST 15 0x1000096 Int BE Pri
87981!#2 N3854 P2425 DWST 16 0x1000097 Int BE Pri
87982!#A N3853 N3854
87983!#2 N3855 P2426 LD 17 -1 Int BE Pri
87984!#2 N3856 P2427 DWST 11 0x1000098 Int BE Pri
87985!#2 N3857 P2428 LD 16 -1 Int BE Pri
87986!#2 N3858 P2428 CAS 16 -1 N3857 0x1000099 Int BE Pri
87987!#2 N3859 P2429 LD 18 -1 Int BE Pri
87988!#2 N3860 P2429 CAS 18 -1 N3859 0x100009a Int BE Pri
87989!#2 N3861 P2430 ST 8 0x100009b Int BE Pri
87990!#2 N3862 P2431 MEMBAR
87991!#2 N3863 P2432 BST 18 0x40800098 FP BE Pri
87992!#2 N3864 P2432 BST 19 0x40800099 FP BE Pri
87993!#A N3863 N3864
87994!#2 N3865 P2432 BST 20 0x4080009a FP BE Pri
87995!#2 N3866 P2433 MEMBAR
87996!#2 N3867 P2434 LD 21 -1 Int BE Pri
87997!#2 N3868 P2434 CAS 21 -1 N3867 0x100009c Int BE Pri
87998!#2 N3869 P2435 REPLACEMENT 21 Int BE Pri
87999!#2 N3870 P2436 ST 4 0x100009d Int BE Pri
88000!#2 N3871 P2437 LD 6 -1 Int BE Pri
88001!#2 N3872 P2437 CAS 6 -1 N3871 0x100009e Int BE Pri
88002!#2 N3873 P2438 DWST_BINIT 14 0x100009f Int BE Pri
88003!#2 N3874 P2439 MEMBAR
88004!#2 N3875 P2440 DWST_BINIT 15 0x10000a0 Int BE Pri
88005!#2 N3876 P2440 DWST_BINIT 16 0x10000a1 Int BE Pri
88006!#A N3875 N3876
88007!#2 N3877 P2441 MEMBAR
88008!#2 N3878 P2442 BSTC 0 0x4080009b FP BE Pri
88009!#2 N3879 P2442 BSTC 1 0x4080009c FP BE Pri
88010!#A N3878 N3879
88011!#2 N3880 P2442 BSTC 2 0x4080009d FP BE Pri
88012!#2 N3881 P2443 MEMBAR
88013!#2 N3882 P2444 BLD 6 -1 FP BE Pri
88014!#2 N3883 P2444 BLD 7 -1 FP BE Pri
88015!#A N3882 N3883
88016!#2 N3884 P2444 BLD 8 -1 FP BE Pri
88017!#2 N3885 P2445 MEMBAR
88018!#2 N3886 P2446 LDD 9 -1 Int BE Pri
88019!#2 N3887 P2446 LDD 10 -1 Int BE Pri
88020!#A N3886 N3887
88021!#2 N3888 P2447 DWLD 0 -1 Int BE Pri
88022!#2 N3889 P2447 DWLD 1 -1 Int BE Pri
88023!#A N3888 N3889
88024!#2 N3890 P2448 MEMBAR
88025!#2 N3891 P2449 BSTC 18 0x4080009e FP BE Pri
88026!#2 N3892 P2449 BSTC 19 0x4080009f FP BE Pri
88027!#A N3891 N3892
88028!#2 N3893 P2449 BSTC 20 0x408000a0 FP BE Pri
88029!#2 N3894 P2450 MEMBAR
88030!#2 N3895 P2451 BST 12 0x408000a1 FP BE Pri
88031!#2 N3896 P2451 BST 13 0x408000a2 FP BE Pri
88032!#A N3895 N3896
88033!#2 N3897 P2451 BST 14 0x408000a3 FP BE Pri
88034!#2 N3898 P2452 MEMBAR
88035!#2 N3899 P2453 ST 12 0x10000a2 Int BE Pri
88036!#2 N3900 P2454 LDD 18 -1 Int BE Pri
88037!#2 N3901 P2454 LDD 19 -1 Int BE Pri
88038!#A N3900 N3901
88039!#2 N3902 P2455 DWLD 15 -1 Int BE Pri
88040!#2 N3903 P2455 DWLD 16 -1 Int BE Pri
88041!#A N3902 N3903
88042!#2 N3904 P2455 CASX 15 -1 N3902 0x10000a3 Int BE Pri
88043!#2 N3905 P2455 CASX 16 -1 N3903 0x10000a4 Int BE Pri
88044!#A N3904 N3905
88045!#2 N3906 P2456 DWLD 0 -1 Int BE Pri
88046!#2 N3907 P2456 DWLD 1 -1 Int BE Pri
88047!#A N3906 N3907
88048!#2 N3908 P2456 CASX 0 -1 N3906 0x10000a5 Int BE Pri
88049!#2 N3909 P2456 CASX 1 -1 N3907 0x10000a6 Int BE Pri
88050!#A N3908 N3909
88051!#2 N3910 P2457 REPLACEMENT 1 Int BE Pri
88052!#2 N3911 P2458 MEMBAR
88053!#2 N3912 P2459 BLD 15 -1 FP BE Pri
88054!#2 N3913 P2459 BLD 16 -1 FP BE Pri
88055!#A N3912 N3913
88056!#2 N3914 P2459 BLD 17 -1 FP BE Pri
88057!#2 N3915 P2460 MEMBAR
88058!#2 N3916 P2461 DWLD 0 -1 Int BE Pri
88059!#2 N3917 P2461 DWLD 1 -1 Int BE Pri
88060!#A N3916 N3917
88061!#2 N3918 P2462 ST_BINIT 6 0x10000a7 Int BE Pri
88062!#2 N3919 P2463 MEMBAR
88063!#2 N3920 P2464 DWLD 12 -1 Int BE Pri
88064!#2 N3921 P2464 DWLD 13 -1 Int BE Pri
88065!#A N3920 N3921
88066!#2 N3922 P2465 LD 16 -1 Int BE Pri
88067!#2 N3923 P2465 CAS 16 -1 N3922 0x10000a8 Int BE Pri
88068!#2 N3924 P2466 ST 0 0x408000a4 FP BE Pri
88069!#2 N3925 P2467 DWLD 15 -1 Int BE Pri
88070!#2 N3926 P2467 DWLD 16 -1 Int BE Pri
88071!#A N3925 N3926
88072!#2 N3927 P2467 CASX 15 -1 N3925 0x10000a9 Int BE Pri
88073!#2 N3928 P2467 CASX 16 -1 N3926 0x10000aa Int BE Pri
88074!#A N3927 N3928
88075!#2 N3929 P2468 MEMBAR
88076!#2 N3930 P2469 BLD 6 -1 FP BE Pri
88077!#2 N3931 P2469 BLD 7 -1 FP BE Pri
88078!#A N3930 N3931
88079!#2 N3932 P2469 BLD 8 -1 FP BE Pri
88080!#2 N3933 P2470 MEMBAR
88081!#2 N3934 P2471 DWST_BINIT 21 0x10000ab Int BE Pri
88082!#2 N3935 P2471 DWST_BINIT 22 0x10000ac Int BE Pri
88083!#A N3934 N3935
88084!#2 N3936 P2472 MEMBAR
88085!#2 N3937 P2473 ST_BINIT 3 0x10000ad Int BE Pri
88086!#2 N3938 P2474 MEMBAR
88087!#2 N3939 P2475 BSTC 15 0x408000a5 FP BE Pri
88088!#2 N3940 P2475 BSTC 16 0x408000a6 FP BE Pri
88089!#A N3939 N3940
88090!#2 N3941 P2475 BSTC 17 0x408000a7 FP BE Pri
88091!#2 N3942 P2476 MEMBAR
88092!#2 N3943 P2477 ST 13 0x10000ae Int LE Pri
88093!#2 N3944 P2478 MEMBAR
88094!#2 N3945 P2479 BLD 18 -1 FP BE Pri
88095!#2 N3946 P2479 BLD 19 -1 FP BE Pri
88096!#A N3945 N3946
88097!#2 N3947 P2479 BLD 20 -1 FP BE Pri
88098!#2 N3948 P2480 MEMBAR
88099!#2 N3949 P2481 ST_BINIT 19 0x10000af Int BE Pri
88100!#2 N3950 P2482 MEMBAR
88101!#2 N3951 P2483 ST 8 0x10000b0 Int BE Pri
88102!#2 N3952 P2484 DWLD 15 -1 Int BE Pri
88103!#2 N3953 P2484 DWLD 16 -1 Int BE Pri
88104!#A N3952 N3953
88105!#2 N3954 P2485 DWLD 6 -1 Int BE Pri
88106!#2 N3955 P2485 DWLD 7 -1 Int BE Pri
88107!#A N3954 N3955
88108!#2 N3956 P2486 MEMBAR
88109!#2 N3957 P2487 BSTC 18 0x408000a8 FP BE Pri
88110!#2 N3958 P2487 BSTC 19 0x408000a9 FP BE Pri
88111!#A N3957 N3958
88112!#2 N3959 P2487 BSTC 20 0x408000aa FP BE Pri
88113!#2 N3960 P2488 MEMBAR
88114!#2 N3961 P2489 PREFETCH 21 Int BE Pri
88115!#2 N3962 P2490 ST_BINIT 22 0x10000b1 Int BE Pri
88116!#2 N3963 P2491 MEMBAR
88117!#2 N3964 P2492 PREFETCH 0 Int BE Pri
88118!#2 N3965 P2493 ST_BINIT 2 0x10000b2 Int BE Pri
88119!#2 N3966 P2494 MEMBAR
88120!#2 N3967 P2495 PREFETCH 8 Int BE Pri
88121!#2 N3968 P2496 ST 21 0x10000b3 Int BE Pri
88122!#2 N3969 P2497 DWST_BINIT 8 0x10000b4 Int BE Pri
88123!#2 N3970 P2498 MEMBAR
88124!#2 N3971 P2499 DWLD 3 -1 Int BE Pri
88125!#2 N3972 P2499 DWLD 4 -1 Int BE Pri
88126!#A N3971 N3972
88127!#2 N3973 P2500 DWLD 9 -1 FP BE Pri
88128!#2 N3974 P2500 DWLD 10 -1 FP BE Pri
88129!#A N3973 N3974
88130!#2 N3975 P2501 DWST_BINIT 5 0x10000b5 Int BE Pri
88131!#2 N3976 P2502 MEMBAR
88132!#2 N3977 P2503 ST 4 0x10000b6 Int BE Pri
88133!#2 N3978 P2504 DWST 0 0x10000b7 Int BE Pri
88134!#2 N3979 P2504 DWST 1 0x10000b8 Int BE Pri
88135!#A N3978 N3979
88136!#2 N3980 P2505 DWST_BINIT 12 0x10000b9 Int BE Pri
88137!#2 N3981 P2505 DWST_BINIT 13 0x10000ba Int BE Pri
88138!#A N3980 N3981
88139!#2 N3982 P2506 MEMBAR
88140!#2 N3983 P2507 LDD 12 -1 Int BE Pri
88141!#2 N3984 P2507 LDD 13 -1 Int BE Pri
88142!#A N3983 N3984
88143!#2 N3985 P2508 MEMBAR
88144!#2 N3986 P2509 BST 9 0x408000ab FP BE Pri
88145!#2 N3987 P2509 BST 10 0x408000ac FP BE Pri
88146!#A N3986 N3987
88147!#2 N3988 P2509 BST 11 0x408000ad FP BE Pri
88148!#2 N3989 P2510 MEMBAR
88149!#2 N3990 P2511 ST_BINIT 0 0x10000bb Int BE Pri
88150!#2 N3991 P2512 MEMBAR
88151!#2 N3992 P2513 LD 1 -1 Int BE Pri
88152!#2 N3993 P2513 CAS 1 -1 N3992 0x10000bc Int BE Pri
88153!#2 N3994 P2514 MEMBAR
88154!#2 N3995 P2515 BLD 15 -1 FP BE Pri
88155!#2 N3996 P2515 BLD 16 -1 FP BE Pri
88156!#A N3995 N3996
88157!#2 N3997 P2515 BLD 17 -1 FP BE Pri
88158!#2 N3998 P2516 MEMBAR
88159!#2 N3999 P2517 PREFETCH 9 Int BE Pri
88160!#2 N4000 P2518 LDD 0 -1 Int BE Pri
88161!#2 N4001 P2518 LDD 1 -1 Int BE Pri
88162!#A N4000 N4001
88163!#2 N4002 P2519 SWAP 14 0xffffffff 0x10000bd Int BE Pri
88164!#2 N4003 P2520 DWST_BINIT 5 0x10000be Int BE Pri
88165!#2 N4004 P2521 MEMBAR
88166!#2 N4005 P2522 LD 5 -1 Int BE Pri
88167!#2 N4006 P2522 CAS 5 -1 N4005 0x10000bf Int BE Pri
88168!#2 N4007 P2523 MEMBAR
88169!#2 N4008 P2524 BSTC 18 0x408000ae FP BE Pri
88170!#2 N4009 P2524 BSTC 19 0x408000af FP BE Pri
88171!#A N4008 N4009
88172!#2 N4010 P2524 BSTC 20 0x408000b0 FP BE Pri
88173!#2 N4011 P2525 MEMBAR
88174!#2 N4012 P2526 ST_BINIT 14 0x10000c0 Int BE Pri
88175!#2 N4013 P2527 MEMBAR
88176!#2 N4014 P2528 DWLD 2 -1,0x0 Int BE Pri
88177!#2 N4015 P2528 CASX 2 -1,0x0 N4014 0x10000c1 Int BE Pri
88178!#2 N4016 P2529 DWST_BINIT 9 0x10000c2 Int BE Pri
88179!#2 N4017 P2529 DWST_BINIT 10 0x10000c3 Int BE Pri
88180!#A N4016 N4017
88181!#2 N4018 P2530 MEMBAR
88182!#2 N4019 P2531 DWLD 17 -1 Int BE Pri
88183!#2 N4020 P2532 MEMBAR
88184!#2 N4021 P2533 BST 0 0x408000b1 FP BE Pri
88185!#2 N4022 P2533 BST 1 0x408000b2 FP BE Pri
88186!#A N4021 N4022
88187!#2 N4023 P2533 BST 2 0x408000b3 FP BE Pri
88188!#2 N4024 P2534 MEMBAR
88189!#2 N4025 P2535 ST_BINIT 17 0x10000c4 Int BE Pri
88190!#2 N4026 P2536 MEMBAR
88191!#2 N4027 P2537 BST 0 0x408000b4 FP BE Pri
88192!#2 N4028 P2537 BST 1 0x408000b5 FP BE Pri
88193!#A N4027 N4028
88194!#2 N4029 P2537 BST 2 0x408000b6 FP BE Pri
88195!#2 N4030 P2538 MEMBAR
88196!#2 N4031 P2539 BLD 12 -1 FP BE Pri
88197!#2 N4032 P2539 BLD 13 -1 FP BE Pri
88198!#A N4031 N4032
88199!#2 N4033 P2539 BLD 14 -1 FP BE Pri
88200!#2 N4034 P2540 MEMBAR
88201!#2 N4035 P2541 LD 0 -1 Int BE Pri
88202!#2 N4036 P2541 CAS 0 -1 N4035 0x10000c5 Int BE Pri
88203!#2 N4037 P2542 PREFETCH 5 Int BE Pri
88204!#2 N4038 P2543 PREFETCH 13 Int BE Pri
88205!#2 N4039 P2544 DWST 15 0x10000c6 Int BE Pri
88206!#2 N4040 P2544 DWST 16 0x10000c7 Int BE Pri
88207!#A N4039 N4040
88208!#2 N4041 P2545 DWST_BINIT 2 0x10000c8 Int BE Pri
88209!#2 N4042 P2546 MEMBAR
88210!#2 N4043 P2547 BLD 18 -1 FP BE Pri
88211!#2 N4044 P2547 BLD 19 -1 FP BE Pri
88212!#A N4043 N4044
88213!#2 N4045 P2547 BLD 20 -1 FP BE Pri
88214!#2 N4046 P2548 MEMBAR
88215!#2 N4047 P2549 ST 21 0x10000c9 Int BE Pri
88216!#2 N4048 P2550 MEMBAR
88217!#2 N4049 P2551 BLD 21 -1 FP BE Pri
88218!#2 N4050 P2551 BLD 22 -1 FP BE Pri
88219!#A N4049 N4050
88220!#2 N4051 P2551 BLD 23 -1 FP BE Pri
88221!#2 N4052 P2552 MEMBAR
88222!#2 N4053 P2553 DWLD 18 -1 Int BE Pri
88223!#2 N4054 P2553 DWLD 19 -1 Int BE Pri
88224!#A N4053 N4054
88225!#2 N4055 P2553 CASX 18 -1 N4053 0x10000ca Int BE Pri
88226!#2 N4056 P2553 CASX 19 -1 N4054 0x10000cb Int BE Pri
88227!#A N4055 N4056
88228!#2 N4057 P2554 DWST_BINIT 0 0x10000cc Int BE Pri
88229!#2 N4058 P2554 DWST_BINIT 1 0x10000cd Int BE Pri
88230!#A N4057 N4058
88231!#2 N4059 P2555 MEMBAR
88232!#2 N4060 P2556 PREFETCH 20 Int BE Pri
88233!#2 N4061 P2557 MEMBAR
88234!#2 N4062 P2558 BLD 9 -1 FP BE Pri
88235!#2 N4063 P2558 BLD 10 -1 FP BE Pri
88236!#A N4062 N4063
88237!#2 N4064 P2558 BLD 11 -1 FP BE Pri
88238!#2 N4065 P2559 MEMBAR
88239!#2 N4066 P2560 DWLD 20 -1 Int BE Pri
88240!#2 N4067 P2561 DWLD 14 -1 Int BE Pri
88241!#2 N4068 P2562 LD 18 -1 Int BE Pri
88242!#2 N4069 P2563 SWAP 7 0xffffffff 0x10000ce Int BE Pri
88243!#2 N4070 P2564 MEMBAR
88244!#2 N4071 P2565 BST 6 0x408000b7 FP BE Pri
88245!#2 N4072 P2565 BST 7 0x408000b8 FP BE Pri
88246!#A N4071 N4072
88247!#2 N4073 P2565 BST 8 0x408000b9 FP BE Pri
88248!#2 N4074 P2566 MEMBAR
88249!#2 N4075 P2567 LD 15 -1 Int BE Pri
88250!#2 N4076 P2568 PREFETCH 7 Int BE Pri
88251!#2 N4077 P2569 PREFETCH 11 Int BE Pri
88252!#2 N4078 P2570 LDD 5 -1 Int BE Pri
88253!#2 N4079 P2571 LD 14 -1 Int BE Pri
88254!#2 N4080 P2571 CAS 14 -1 N4079 0x10000cf Int BE Pri
88255!#2 N4081 P2572 PREFETCH 21 Int LE Pri
88256!#2 N4082 P2573 DWLD 12 -1 Int BE Pri
88257!#2 N4083 P2573 DWLD 13 -1 Int BE Pri
88258!#A N4082 N4083
88259!#2 N4084 P2573 CASX 12 -1 N4082 0x10000d0 Int BE Pri
88260!#2 N4085 P2573 CASX 13 -1 N4083 0x10000d1 Int BE Pri
88261!#A N4084 N4085
88262!#2 N4086 P2574 SWAP 14 0xffffffff 0x10000d2 Int BE Pri
88263!#2 N4087 P2575 DWST_BINIT 6 0x10000d3 Int BE Pri
88264!#2 N4088 P2575 DWST_BINIT 7 0x10000d4 Int BE Pri
88265!#A N4087 N4088
88266!#2 N4089 P2576 MEMBAR
88267!#2 N4090 P2577 DWLD 12 -1 FP BE Pri
88268!#2 N4091 P2577 DWLD 13 -1 FP BE Pri
88269!#A N4090 N4091
88270!#2 N4092 P2578 DWST_BINIT 0 0x10000d5 Int BE Pri
88271!#2 N4093 P2578 DWST_BINIT 1 0x10000d6 Int BE Pri
88272!#A N4092 N4093
88273!#2 N4094 P2579 MEMBAR
88274!#2 N4095 P2580 BSTC 3 0x408000ba FP BE Pri
88275!#2 N4096 P2580 BSTC 4 0x408000bb FP BE Pri
88276!#A N4095 N4096
88277!#2 N4097 P2580 BSTC 5 0x408000bc FP BE Pri
88278!#2 N4098 P2581 MEMBAR
88279!#2 N4099 P2582 LD 22 -1 Int BE Pri
88280!#2 N4100 P2582 CAS 22 -1 N4099 0x10000d7 Int BE Pri
88281!#2 N4101 P2583 LDD 3 -1 Int BE Pri
88282!#2 N4102 P2583 LDD 4 -1 Int BE Pri
88283!#A N4101 N4102
88284!#2 N4103 P2584 LD 18 -1 Int BE Pri
88285!#2 N4104 P2584 CAS 18 -1 N4103 0x10000d8 Int BE Pri
88286!#2 N4105 P2585 MEMBAR
88287!#2 N4106 P2586 BST 15 0x408000bd FP BE Pri
88288!#2 N4107 P2586 BST 16 0x408000be FP BE Pri
88289!#A N4106 N4107
88290!#2 N4108 P2586 BST 17 0x408000bf FP BE Pri
88291!#2 N4109 P2587 MEMBAR
88292!#2 N4110 P2588 DWST_BINIT 11 0x10000d9 Int BE Pri
88293!#2 N4111 P2589 MEMBAR
88294!#2 N4112 P2590 ST 13 0x10000da Int BE Pri
88295!#2 N4113 P2591 LD 18 -1 Int BE Pri
88296!#2 N4114 P2591 CAS 18 -1 N4113 0x10000db Int BE Pri
88297!#2 N4115 P2592 DWLD 0 -1 Int BE Pri
88298!#2 N4116 P2592 DWLD 1 -1 Int BE Pri
88299!#A N4115 N4116
88300!#2 N4117 P2592 CASX 0 -1 N4115 0x10000dc Int BE Pri
88301!#2 N4118 P2592 CASX 1 -1 N4116 0x10000dd Int BE Pri
88302!#A N4117 N4118
88303!#2 N4119 P2593 DWST_BINIT 17 0x10000de Int BE Pri
88304!#2 N4120 P2594 MEMBAR
88305!#2 N4121 P2595 BST 18 0x408000c0 FP BE Pri
88306!#2 N4122 P2595 BST 19 0x408000c1 FP BE Pri
88307!#A N4121 N4122
88308!#2 N4123 P2595 BST 20 0x408000c2 FP BE Pri
88309!#2 N4124 P2596 MEMBAR
88310!#2 N4125 P2597 BST 21 0x408000c3 FP BE Pri
88311!#2 N4126 P2597 BST 22 0x408000c4 FP BE Pri
88312!#A N4125 N4126
88313!#2 N4127 P2597 BST 23 0x408000c5 FP BE Pri
88314!#2 N4128 P2598 MEMBAR
88315!#2 N4129 P2599 ST_BINIT 6 0x10000df Int BE Pri
88316!#2 N4130 P2600 MEMBAR
88317!#2 N4131 P2601 LD 20 -1 Int BE Pri
88318!#2 N4132 P2602 DWLD 18 -1 Int LE Pri
88319!#2 N4133 P2602 DWLD 19 -1 Int LE Pri
88320!#A N4132 N4133
88321!#2 N4134 P2603 ST 20 0x408000c6 FP BE Pri
88322!#2 N4135 P2604 LD 21 -1 Int BE Pri
88323!#2 N4136 P2604 CAS 21 -1 N4135 0x10000e0 Int BE Pri
88324!#2 N4137 P2605 LD 23 -1 Int LE Pri
88325!#2 N4138 P2606 DWST_BINIT 21 0x10000e1 Int BE Pri
88326!#2 N4139 P2606 DWST_BINIT 22 0x10000e2 Int BE Pri
88327!#A N4138 N4139
88328!#2 N4140 P2607 MEMBAR
88329!#2 N4141 P2608 SWAP 7 0xffffffff 0x10000e3 Int BE Pri
88330!#2 N4142 P2609 LD 9 -1 Int BE Pri
88331!#2 N4143 P2610 DWLD 9 -1 Int BE Pri
88332!#2 N4144 P2610 DWLD 10 -1 Int BE Pri
88333!#A N4143 N4144
88334!#2 N4145 P2610 CASX 9 -1 N4143 0x10000e4 Int BE Pri
88335!#2 N4146 P2610 CASX 10 -1 N4144 0x10000e5 Int BE Pri
88336!#A N4145 N4146
88337!#2 N4147 P2611 ST 14 0x10000e6 Int BE Pri
88338!#2 N4148 P2612 LDD 20 -1 Int BE Pri
88339!#2 N4149 P2613 LDD 12 -1 Int BE Pri
88340!#2 N4150 P2613 LDD 13 -1 Int BE Pri
88341!#A N4149 N4150
88342!#2 N4151 P2614 DWLD 5 -1,0x0 Int BE Pri
88343!#2 N4152 P2614 CASX 5 -1,0x0 N4151 0x10000e7 Int BE Pri
88344!#2 N4153 P2615 DWLD 14 -1,0x0 Int BE Pri
88345!#2 N4154 P2615 CASX 14 -1,0x0 N4153 0x10000e8 Int BE Pri
88346!#2 N4155 P2616 DWLD 0 -1 Int BE Pri
88347!#2 N4156 P2616 DWLD 1 -1 Int BE Pri
88348!#A N4155 N4156
88349!#2 N4157 P2616 CASX 0 -1 N4155 0x10000e9 Int BE Pri
88350!#2 N4158 P2616 CASX 1 -1 N4156 0x10000ea Int BE Pri
88351!#A N4157 N4158
88352!#2 N4159 P2617 MEMBAR
88353!#2 N4160 P2618 BLD 18 -1 FP BE Pri
88354!#2 N4161 P2618 BLD 19 -1 FP BE Pri
88355!#A N4160 N4161
88356!#2 N4162 P2618 BLD 20 -1 FP BE Pri
88357!#2 N4163 P2619 MEMBAR
88358!#2 N4164 P2620 PREFETCH 18 Int BE Pri
88359!#2 N4165 P2621 ST 12 0x10000eb Int BE Pri
88360!#2 N4166 P2622 ST_BINIT 5 0x10000ec Int BE Pri
88361!#2 N4167 P2623 MEMBAR
88362!#2 N4168 P2624 BST 3 0x408000c7 FP BE Pri
88363!#2 N4169 P2624 BST 4 0x408000c8 FP BE Pri
88364!#A N4168 N4169
88365!#2 N4170 P2624 BST 5 0x408000c9 FP BE Pri
88366!#2 N4171 P2625 MEMBAR
88367!#2 N4172 P2626 DWST 6 0x10000ed Int BE Pri
88368!#2 N4173 P2626 DWST 7 0x10000ee Int BE Pri
88369!#A N4172 N4173
88370!#2 N4174 P2627 SWAP 23 0xffffffff 0x10000ef Int BE Pri
88371!#2 N4175 P2628 ST 12 0x10000f0 Int BE Pri
88372!#2 N4176 P2629 LD 9 -1 Int BE Pri
88373!#2 N4177 P2630 MEMBAR
88374!#2 N4178 P2631 BLD 15 -1 FP BE Pri
88375!#2 N4179 P2631 BLD 16 -1 FP BE Pri
88376!#A N4178 N4179
88377!#2 N4180 P2631 BLD 17 -1 FP BE Pri
88378!#2 N4181 P2632 MEMBAR
88379!#2 N4182 P2633 BLD 12 -1 FP BE Pri
88380!#2 N4183 P2633 BLD 13 -1 FP BE Pri
88381!#A N4182 N4183
88382!#2 N4184 P2633 BLD 14 -1 FP BE Pri
88383!#2 N4185 P2634 MEMBAR
88384!#2 N4186 P2635 LD 21 -1 Int BE Pri
88385!#2 N4187 P2635 CAS 21 -1 N4186 0x10000f1 Int BE Pri
88386!#2 N4188 P2636 DWLD 14 -1,0x0 Int BE Pri
88387!#2 N4189 P2636 CASX 14 -1,0x0 N4188 0x10000f2 Int BE Pri
88388!#2 N4190 P2637 LDD 6 -1 Int BE Pri
88389!#2 N4191 P2637 LDD 7 -1 Int BE Pri
88390!#A N4190 N4191
88391!#2 N4192 P2638 LD 17 -1 Int BE Pri
88392!#2 N4193 P2639 ST 17 0x10000f3 Int BE Pri
88393!#2 N4194 P2640 MEMBAR
88394!#2 N4195 P2641 BLD 6 -1 FP BE Pri
88395!#2 N4196 P2641 BLD 7 -1 FP BE Pri
88396!#A N4195 N4196
88397!#2 N4197 P2641 BLD 8 -1 FP BE Pri
88398!#2 N4198 P2642 MEMBAR
88399!#2 N4199 P2643 DWST 15 0x10000f4 Int BE Pri
88400!#2 N4200 P2643 DWST 16 0x10000f5 Int BE Pri
88401!#A N4199 N4200
88402!#2 N4201 P2644 LD 16 -1 Int BE Pri
88403!#2 N4202 P2645 MEMBAR
88404!#2 N4203 P2646 BST 21 0x408000ca FP BE Pri
88405!#2 N4204 P2646 BST 22 0x408000cb FP BE Pri
88406!#A N4203 N4204
88407!#2 N4205 P2646 BST 23 0x408000cc FP BE Pri
88408!#2 N4206 P2647 MEMBAR
88409!#2 N4207 P2648 PREFETCH 22 Int BE Pri
88410!#2 N4208 P2649 MEMBAR
88411!#2 N4209 P2650 BSTC 9 0x408000cd FP BE Pri
88412!#2 N4210 P2650 BSTC 10 0x408000ce FP BE Pri
88413!#A N4209 N4210
88414!#2 N4211 P2650 BSTC 11 0x408000cf FP BE Pri
88415!#2 N4212 P2651 MEMBAR
88416!#2 N4213 P2652 DWLD 3 -1 Int BE Pri
88417!#2 N4214 P2652 DWLD 4 -1 Int BE Pri
88418!#A N4213 N4214
88419!#2 N4215 P2652 CASX 3 -1 N4213 0x10000f6 Int BE Pri
88420!#2 N4216 P2652 CASX 4 -1 N4214 0x10000f7 Int BE Pri
88421!#A N4215 N4216
88422!#2 N4217 P2653 PREFETCH 2 Int BE Pri
88423!#2 N4218 P2654 DWLD 8 -1,0x0 Int BE Pri
88424!#2 N4219 P2654 CASX 8 -1,0x0 N4218 0x10000f8 Int BE Pri
88425!#2 N4220 P2655 SWAP 20 0xffffffff 0x10000f9 Int LE Pri
88426!#2 N4221 P2656 DWLD 8 -1 Int BE Pri
88427!#2 N4222 P2657 DWLD 6 -1 Int BE Pri
88428!#2 N4223 P2657 DWLD 7 -1 Int BE Pri
88429!#A N4222 N4223
88430!#2 N4224 P2657 CASX 6 -1 N4222 0x10000fa Int BE Pri
88431!#2 N4225 P2657 CASX 7 -1 N4223 0x10000fb Int BE Pri
88432!#A N4224 N4225
88433!#2 N4226 P2658 ST 15 0x10000fc Int BE Pri
88434!#2 N4227 P2659 MEMBAR
88435!#2 N4228 P2660 BLD 12 -1 FP BE Pri
88436!#2 N4229 P2660 BLD 13 -1 FP BE Pri
88437!#A N4228 N4229
88438!#2 N4230 P2660 BLD 14 -1 FP BE Pri
88439!#2 N4231 P2661 MEMBAR
88440!#2 N4232 P2662 BLD 9 -1 FP BE Pri
88441!#2 N4233 P2662 BLD 10 -1 FP BE Pri
88442!#A N4232 N4233
88443!#2 N4234 P2662 BLD 11 -1 FP BE Pri
88444!#2 N4235 P2663 MEMBAR
88445!#2 N4236 P2664 LD 15 -1 Int BE Pri
88446!#2 N4237 P2664 CAS 15 -1 N4236 0x10000fd Int BE Pri
88447!#2 N4238 P2665 DWST_BINIT 21 0x10000fe Int BE Pri
88448!#2 N4239 P2665 DWST_BINIT 22 0x10000ff Int BE Pri
88449!#A N4238 N4239
88450!#2 N4240 P2666 MEMBAR
88451!#2 N4241 P2667 DWST 17 0x1000100 Int BE Pri
88452!#2 N4242 P2668 PREFETCH 7 Int BE Pri
88453!#2 N4243 P2669 MEMBAR
88454!#2 N4244 P2670 BSTC 18 0x408000d0 FP BE Pri
88455!#2 N4245 P2670 BSTC 19 0x408000d1 FP BE Pri
88456!#A N4244 N4245
88457!#2 N4246 P2670 BSTC 20 0x408000d2 FP BE Pri
88458!#2 N4247 P2671 MEMBAR
88459!#2 N4248 P2672 SWAP 14 0xffffffff 0x1000101 Int BE Pri
88460!#2 N4249 P2673 LD 19 -1 Int BE Pri
88461!#2 N4250 P2673 CAS 19 -1 N4249 0x1000102 Int BE Pri
88462!#2 N4251 P2674 LDD 18 -1 Int BE Pri
88463!#2 N4252 P2674 LDD 19 -1 Int BE Pri
88464!#A N4251 N4252
88465!#2 N4253 P2675 DWST_BINIT 23 0x1000103 Int BE Pri
88466!#2 N4254 P2676 MEMBAR
88467!#2 N4255 P2677 BLD 9 -1 FP BE Pri
88468!#2 N4256 P2677 BLD 10 -1 FP BE Pri
88469!#A N4255 N4256
88470!#2 N4257 P2677 BLD 11 -1 FP BE Pri
88471!#2 N4258 P2678 MEMBAR
88472!#2 N4259 P2679 REPLACEMENT 6 Int BE Pri
88473!#2 N4260 P2680 REPLACEMENT 13 Int BE Pri
88474!#2 N4261 P2681 REPLACEMENT 20 Int BE Pri
88475!#2 N4262 P2682 PREFETCH 19 Int BE Pri
88476!#2 N4263 P2683 MEMBAR
88477!#2 N4264 P2684 BLD 15 -1 FP BE Pri
88478!#2 N4265 P2684 BLD 16 -1 FP BE Pri
88479!#A N4264 N4265
88480!#2 N4266 P2684 BLD 17 -1 FP BE Pri
88481!#2 N4267 P2685 MEMBAR
88482!#2 N4268 P2686 SWAP 22 0xffffffff 0x1000104 Int BE Pri
88483!#2 N4269 P2687 PREFETCH 21 Int BE Pri
88484!#2 N4270 P2688 DWLD 12 -1 Int BE Pri
88485!#2 N4271 P2688 DWLD 13 -1 Int BE Pri
88486!#A N4270 N4271
88487!#2 N4272 P2688 CASX 12 -1 N4270 0x1000105 Int BE Pri
88488!#2 N4273 P2688 CASX 13 -1 N4271 0x1000106 Int BE Pri
88489!#A N4272 N4273
88490!#2 N4274 P2689 ST 23 0x1000107 Int BE Pri
88491!#2 N4275 P2690 DWLD 12 -1 Int BE Pri
88492!#2 N4276 P2690 DWLD 13 -1 Int BE Pri
88493!#A N4275 N4276
88494!#2 N4277 P2690 CASX 12 -1 N4275 0x1000108 Int BE Pri
88495!#2 N4278 P2690 CASX 13 -1 N4276 0x1000109 Int BE Pri
88496!#A N4277 N4278
88497!#2 N4279 P2691 MEMBAR
88498!#2 N4280 P2692 BSTC 9 0x408000d3 FP BE Pri
88499!#2 N4281 P2692 BSTC 10 0x408000d4 FP BE Pri
88500!#A N4280 N4281
88501!#2 N4282 P2692 BSTC 11 0x408000d5 FP BE Pri
88502!#2 N4283 P2693 MEMBAR
88503!#2 N4284 P2694 BSTC 9 0x408000d6 FP BE Pri
88504!#2 N4285 P2694 BSTC 10 0x408000d7 FP BE Pri
88505!#A N4284 N4285
88506!#2 N4286 P2694 BSTC 11 0x408000d8 FP BE Pri
88507!#2 N4287 P2695 MEMBAR
88508!#2 N4288 P2696 ST_BINIT 0 0x100010a Int BE Pri
88509!#2 N4289 P2697 MEMBAR
88510!#2 N4290 P2698 REPLACEMENT 1 Int BE Pri
88511!#2 N4291 P2699 DWLD 21 -1 Int BE Pri
88512!#2 N4292 P2699 DWLD 22 -1 Int BE Pri
88513!#A N4291 N4292
88514!#2 N4293 P2699 CASX 21 -1 N4291 0x100010b Int BE Pri
88515!#2 N4294 P2699 CASX 22 -1 N4292 0x100010c Int BE Pri
88516!#A N4293 N4294
88517!#2 N4295 P2700 LD 1 -1 Int BE Pri
88518!#2 N4296 P2701 LD 19 -1 Int BE Pri
88519!#2 N4297 P2702 DWST_BINIT 3 0x100010d Int BE Pri
88520!#2 N4298 P2702 DWST_BINIT 4 0x100010e Int BE Pri
88521!#A N4297 N4298
88522!#2 N4299 P2703 MEMBAR
88523!#2 N4300 P2704 PREFETCH 6 Int BE Pri
88524!#2 N4301 P2705 REPLACEMENT 3 Int BE Pri
88525!#2 N4302 P2706 ST_BINIT 13 0x100010f Int BE Pri
88526!#2 N4303 P2707 MEMBAR
88527!#2 N4304 P2708 DWLD 8 -1,0x0 Int BE Pri
88528!#2 N4305 P2708 CASX 8 -1,0x0 N4304 0x1000110 Int BE Pri
88529!#2 N4306 P2709 DWLD 3 -1 Int BE Pri
88530!#2 N4307 P2709 DWLD 4 -1 Int BE Pri
88531!#A N4306 N4307
88532!#2 N4308 P2709 CASX 3 -1 N4306 0x1000111 Int BE Pri
88533!#2 N4309 P2709 CASX 4 -1 N4307 0x1000112 Int BE Pri
88534!#A N4308 N4309
88535!#2 N4310 P2710 DWST 21 0x1000113 Int BE Pri
88536!#2 N4311 P2710 DWST 22 0x1000114 Int BE Pri
88537!#A N4310 N4311
88538!#2 N4312 P2711 LDD 6 -1 Int BE Pri
88539!#2 N4313 P2711 LDD 7 -1 Int BE Pri
88540!#A N4312 N4313
88541!#2 N4314 P2712 LD 21 -1 Int BE Pri
88542!#2 N4315 P2713 PREFETCH 12 Int BE Pri
88543!#2 N4316 P2714 SWAP 23 0xffffffff 0x1000115 Int BE Pri
88544!#2 N4317 P2715 SWAP 5 0xffffffff 0x1000116 Int BE Pri
88545!#2 N4318 P2716 ST_BINIT 2 0x1000117 Int BE Pri
88546!#2 N4319 P2717 MEMBAR
88547!#2 N4320 P2718 SWAP 12 0xffffffff 0x1000118 Int BE Pri
88548!#2 N4321 P2719 ST_BINIT 20 0x1000119 Int BE Pri
88549!#2 N4322 P2720 MEMBAR
88550!#2 N4323 P2721 DWST_BINIT 18 0x100011a Int BE Pri
88551!#2 N4324 P2721 DWST_BINIT 19 0x100011b Int BE Pri
88552!#A N4323 N4324
88553!#2 N4325 P2722 MEMBAR
88554!#2 N4326 P2723 PREFETCH 23 Int BE Pri
88555!#2 N4327 P2724 PREFETCH 13 Int BE Pri
88556!#2 N4328 P2725 PREFETCH 16 Int BE Pri
88557!#2 N4329 P2726 REPLACEMENT 1 Int BE Pri
88558!#2 N4330 P2727 MEMBAR
88559!#2 N4331 P2728 BLD 21 -1 FP BE Pri
88560!#2 N4332 P2728 BLD 22 -1 FP BE Pri
88561!#A N4331 N4332
88562!#2 N4333 P2728 BLD 23 -1 FP BE Pri
88563!#2 N4334 P2729 MEMBAR
88564!#2 N4335 P2730 ST_BINIT 19 0x100011c Int BE Pri
88565!#2 N4336 P2731 MEMBAR
88566!#2 N4337 P2732 ST_BINIT 1 0x100011d Int BE Pri
88567!#2 N4338 P2733 MEMBAR
88568!#2 N4339 P2734 BST 6 0x408000d9 FP BE Pri
88569!#2 N4340 P2734 BST 7 0x408000da FP BE Pri
88570!#A N4339 N4340
88571!#2 N4341 P2734 BST 8 0x408000db FP BE Pri
88572!#2 N4342 P2735 MEMBAR
88573!#2 N4343 P2736 DWST 0 0x100011e Int BE Pri
88574!#2 N4344 P2736 DWST 1 0x100011f Int BE Pri
88575!#A N4343 N4344
88576!#2 N4345 P2737 ST_BINIT 16 0x1000120 Int BE Pri
88577!#2 N4346 P2738 MEMBAR
88578!#2 N4347 P2739 PREFETCH 9 Int BE Pri
88579!#2 N4348 P2740 PREFETCH 19 Int BE Pri
88580!#2 N4349 P2741 DWST_BINIT 6 0x1000121 Int BE Pri
88581!#2 N4350 P2741 DWST_BINIT 7 0x1000122 Int BE Pri
88582!#A N4349 N4350
88583!#2 N4351 P2742 MEMBAR
88584!#2 N4352 P2743 BST 3 0x408000dc FP BE Pri
88585!#2 N4353 P2743 BST 4 0x408000dd FP BE Pri
88586!#A N4352 N4353
88587!#2 N4354 P2743 BST 5 0x408000de FP BE Pri
88588!#2 N4355 P2744 MEMBAR
88589!#2 N4356 P2745 PREFETCH 3 Int BE Pri
88590!#2 N4357 P2746 DWLD 9 -1 Int BE Pri
88591!#2 N4358 P2746 DWLD 10 -1 Int BE Pri
88592!#A N4357 N4358
88593!#2 N4359 P2747 MEMBAR
88594!#2 N4360 P2748 BSTC 21 0x408000df FP BE Pri
88595!#2 N4361 P2748 BSTC 22 0x408000e0 FP BE Pri
88596!#A N4360 N4361
88597!#2 N4362 P2748 BSTC 23 0x408000e1 FP BE Pri
88598!#2 N4363 P2749 MEMBAR
88599!#2 N4364 P2750 DWLD 3 -1 Int BE Pri
88600!#2 N4365 P2750 DWLD 4 -1 Int BE Pri
88601!#A N4364 N4365
88602!#2 N4366 P2751 SWAP 15 0xffffffff 0x1000123 Int BE Pri
88603!#2 N4367 P2752 PREFETCH 4 Int BE Pri
88604!#2 N4368 P2753 LD 11 -1 Int BE Pri
88605!#2 N4369 P2754 MEMBAR
88606!#2 N4370 P2755 BLD 3 -1 FP BE Pri
88607!#2 N4371 P2755 BLD 4 -1 FP BE Pri
88608!#A N4370 N4371
88609!#2 N4372 P2755 BLD 5 -1 FP BE Pri
88610!#2 N4373 P2756 MEMBAR
88611!#2 N4374 P2757 PREFETCH 5 Int BE Pri
88612!#2 N4375 P2758 MEMBAR
88613!#2 N4376 P2759 BST 15 0x408000e2 FP BE Pri
88614!#2 N4377 P2759 BST 16 0x408000e3 FP BE Pri
88615!#A N4376 N4377
88616!#2 N4378 P2759 BST 17 0x408000e4 FP BE Pri
88617!#2 N4379 P2760 MEMBAR
88618!#2 N4380 P2761 ST_BINIT 5 0x1000124 Int LE Pri
88619!#2 N4381 P2762 MEMBAR
88620!#2 N4382 P2763 ST 12 0x1000125 Int BE Pri
88621!#2 N4383 P2764 MEMBAR
88622!#2 N4384 P2765 BST 9 0x408000e5 FP BE Pri
88623!#2 N4385 P2765 BST 10 0x408000e6 FP BE Pri
88624!#A N4384 N4385
88625!#2 N4386 P2765 BST 11 0x408000e7 FP BE Pri
88626!#2 N4387 P2766 MEMBAR
88627!#2 N4388 P2767 LDD 9 -1 Int BE Pri
88628!#2 N4389 P2767 LDD 10 -1 Int BE Pri
88629!#A N4388 N4389
88630!#2 N4390 P2768 ST_BINIT 8 0x1000126 Int BE Pri
88631!#2 N4391 P2769 MEMBAR
88632!#2 N4392 P2770 BSTC 3 0x408000e8 FP BE Pri
88633!#2 N4393 P2770 BSTC 4 0x408000e9 FP BE Pri
88634!#A N4392 N4393
88635!#2 N4394 P2770 BSTC 5 0x408000ea FP BE Pri
88636!#2 N4395 P2771 MEMBAR
88637!#2 N4396 P2772 LD 4 -1 Int BE Pri
88638!#2 N4397 P2773 ST_BINIT 20 0x1000127 Int BE Pri
88639!#2 N4398 P2774 MEMBAR
88640!#2 N4399 P2775 ST 0 0x1000128 Int BE Pri
88641!#2 N4400 P2776 PREFETCH 2 Int BE Pri
88642!#2 N4401 P2777 DWST 0 0x1000129 Int BE Pri
88643!#2 N4402 P2777 DWST 1 0x100012a Int BE Pri
88644!#A N4401 N4402
88645!#2 N4403 P2778 MEMBAR
88646!#2 N4404 P2779 BST 18 0x408000eb FP BE Pri
88647!#2 N4405 P2779 BST 19 0x408000ec FP BE Pri
88648!#A N4404 N4405
88649!#2 N4406 P2779 BST 20 0x408000ed FP BE Pri
88650!#2 N4407 P2780 MEMBAR
88651!#2 N4408 P2781 DWST 6 0x408000ee FP BE Pri
88652!#2 N4409 P2781 DWST 7 0x408000ef FP BE Pri
88653!#A N4408 N4409
88654!#2 N4410 P2782 LDD 0 -1 Int BE Pri
88655!#2 N4411 P2782 LDD 1 -1 Int BE Pri
88656!#A N4410 N4411
88657!#2 N4412 P2783 SWAP 8 0xffffffff 0x100012b Int BE Pri
88658!#2 N4413 P2784 MEMBAR
88659!#2 N4414 P2785 BSTC 18 0x408000f0 FP BE Pri
88660!#2 N4415 P2785 BSTC 19 0x408000f1 FP BE Pri
88661!#A N4414 N4415
88662!#2 N4416 P2785 BSTC 20 0x408000f2 FP BE Pri
88663!#2 N4417 P2786 MEMBAR
88664!#2 N4418 P2787 PREFETCH 17 Int BE Pri
88665!#2 N4419 P2788 LD 2 -1 Int BE Pri
88666!#2 N4420 P2789 ST_BINIT 3 0x100012c Int BE Pri
88667!#2 N4421 P2790 MEMBAR
88668!#2 N4422 P2791 PREFETCH 15 Int BE Pri
88669!#2 N4423 P2792 REPLACEMENT 1 Int BE Pri
88670!#2 N4424 P2793 DWLD 8 -1,0x0 Int BE Pri
88671!#2 N4425 P2793 CASX 8 -1,0x0 N4424 0x100012d Int BE Pri
88672!#2 N4426 P2794 ST_BINIT 15 0x100012e Int BE Pri
88673!#2 N4427 P2795 MEMBAR
88674!#2 N4428 P2796 BST 0 0x408000f3 FP BE Pri
88675!#2 N4429 P2796 BST 1 0x408000f4 FP BE Pri
88676!#A N4428 N4429
88677!#2 N4430 P2796 BST 2 0x408000f5 FP BE Pri
88678!#2 N4431 P2797 MEMBAR
88679!#2 N4432 P2798 DWST 0 0x100012f Int BE Pri
88680!#2 N4433 P2798 DWST 1 0x1000130 Int BE Pri
88681!#A N4432 N4433
88682!#2 N4434 P2799 DWST 17 0x1000131 Int BE Pri
88683!#2 N4435 P2800 LD 20 -1 Int BE Pri
88684!#2 N4436 P2800 CAS 20 -1 N4435 0x1000132 Int BE Pri
88685!#2 N4437 P2801 LD 18 -1 Int LE Pri
88686!#2 N4438 P2801 CAS 18 -1 N4437 0x1000133 Int LE Pri
88687!#2 N4439 P2802 DWLD 9 -1 Int BE Pri
88688!#2 N4440 P2802 DWLD 10 -1 Int BE Pri
88689!#A N4439 N4440
88690!#2 N4441 P2803 DWST_BINIT 18 0x1000134 Int BE Pri
88691!#2 N4442 P2803 DWST_BINIT 19 0x1000135 Int BE Pri
88692!#A N4441 N4442
88693!#2 N4443 P2804 MEMBAR
88694!#2 N4444 P2805 PREFETCH 6 Int BE Pri
88695!#2 N4445 P2806 DWLD 6 -1 Int BE Pri
88696!#2 N4446 P2806 DWLD 7 -1 Int BE Pri
88697!#A N4445 N4446
88698!#2 N4447 P2806 CASX 6 -1 N4445 0x1000136 Int BE Pri
88699!#2 N4448 P2806 CASX 7 -1 N4446 0x1000137 Int BE Pri
88700!#A N4447 N4448
88701!#2 N4449 P2807 SWAP 17 0xffffffff 0x1000138 Int BE Pri
88702!#2 N4450 P2808 LDD 6 -1 Int BE Pri
88703!#2 N4451 P2808 LDD 7 -1 Int BE Pri
88704!#A N4450 N4451
88705!#2 N4452 P2809 MEMBAR
88706!#2 N4453 P2810 BLD 6 -1 FP BE Pri
88707!#2 N4454 P2810 BLD 7 -1 FP BE Pri
88708!#A N4453 N4454
88709!#2 N4455 P2810 BLD 8 -1 FP BE Pri
88710!#2 N4456 P2811 MEMBAR
88711!#2 N4457 P2812 BLD 3 -1 FP BE Pri
88712!#2 N4458 P2812 BLD 4 -1 FP BE Pri
88713!#A N4457 N4458
88714!#2 N4459 P2812 BLD 5 -1 FP BE Pri
88715!#2 N4460 P2813 MEMBAR
88716!#2 N4461 P2814 DWLD 14 -1 Int LE Pri
88717!#2 N4462 P2815 REPLACEMENT 15 Int BE Pri
88718!#2 N4463 P2816 MEMBAR
88719!#2 N4464 P2817 BSTC 18 0x408000f6 FP BE Pri
88720!#2 N4465 P2817 BSTC 19 0x408000f7 FP BE Pri
88721!#A N4464 N4465
88722!#2 N4466 P2817 BSTC 20 0x408000f8 FP BE Pri
88723!#2 N4467 P2818 MEMBAR
88724!#2 N4468 P2819 ST_BINIT 15 0x1000139 Int BE Pri
88725!#2 N4469 P2820 MEMBAR
88726!#2 N4470 P2821 DWLD 12 -1 Int BE Pri
88727!#2 N4471 P2821 DWLD 13 -1 Int BE Pri
88728!#A N4470 N4471
88729!#2 N4472 P2822 MEMBAR
88730!#2 N4473 P2823 BSTC 9 0x408000f9 FP BE Pri
88731!#2 N4474 P2823 BSTC 10 0x408000fa FP BE Pri
88732!#A N4473 N4474
88733!#2 N4475 P2823 BSTC 11 0x408000fb FP BE Pri
88734!#2 N4476 P2824 MEMBAR
88735!#2 N4477 P2825 DWST_BINIT 18 0x100013a Int BE Pri
88736!#2 N4478 P2825 DWST_BINIT 19 0x100013b Int BE Pri
88737!#A N4477 N4478
88738!#2 N4479 P2826 MEMBAR
88739!#2 N4480 P2827 ST_BINIT 1 0x100013c Int BE Pri
88740!#2 N4481 P2828 MEMBAR
88741!#2 N4482 P2829 LD 1 -1 Int BE Pri
88742!#2 N4483 P2830 ST 21 0x100013d Int BE Pri
88743!#2 N4484 P2831 PREFETCH 18 Int BE Pri
88744!#2 N4485 P2832 MEMBAR
88745!#2 N4486 P2833 BLD 18 -1 FP BE Pri
88746!#2 N4487 P2833 BLD 19 -1 FP BE Pri
88747!#A N4486 N4487
88748!#2 N4488 P2833 BLD 20 -1 FP BE Pri
88749!#2 N4489 P2834 MEMBAR
88750!#2 N4490 P2835 DWLD 3 -1 Int BE Pri
88751!#2 N4491 P2835 DWLD 4 -1 Int BE Pri
88752!#A N4490 N4491
88753!#2 N4492 P2835 CASX 3 -1 N4490 0x100013e Int BE Pri
88754!#2 N4493 P2835 CASX 4 -1 N4491 0x100013f Int BE Pri
88755!#A N4492 N4493
88756!#2 N4494 P2836 LD 10 -1 Int BE Pri
88757!#2 N4495 P2836 CAS 10 -1 N4494 0x1000140 Int BE Pri
88758!#2 N4496 P2837 MEMBAR
88759!#2 N4497 P2838 BSTC 21 0x408000fc FP BE Pri
88760!#2 N4498 P2838 BSTC 22 0x408000fd FP BE Pri
88761!#A N4497 N4498
88762!#2 N4499 P2838 BSTC 23 0x408000fe FP BE Pri
88763!#2 N4500 P2839 MEMBAR
88764!#2 N4501 P2840 REPLACEMENT 4 Int BE Pri
88765!#2 N4502 P2841 ST_BINIT 19 0x1000141 Int BE Pri
88766!#2 N4503 P2842 MEMBAR
88767!#2 N4504 P2843 DWLD 9 -1 Int BE Pri
88768!#2 N4505 P2843 DWLD 10 -1 Int BE Pri
88769!#A N4504 N4505
88770!#2 N4506 P2843 CASX 9 -1 N4504 0x1000142 Int BE Pri
88771!#2 N4507 P2843 CASX 10 -1 N4505 0x1000143 Int BE Pri
88772!#A N4506 N4507
88773!#2 N4508 P2844 PREFETCH 12 Int BE Pri
88774!#2 N4509 P2845 DWST_BINIT 6 0x1000144 Int BE Pri
88775!#2 N4510 P2845 DWST_BINIT 7 0x1000145 Int BE Pri
88776!#A N4509 N4510
88777!#2 N4511 P2846 MEMBAR
88778!#2 N4512 P2847 BLD 9 -1 FP BE Pri
88779!#2 N4513 P2847 BLD 10 -1 FP BE Pri
88780!#A N4512 N4513
88781!#2 N4514 P2847 BLD 11 -1 FP BE Pri
88782!#2 N4515 P2848 MEMBAR
88783!#2 N4516 P2849 DWST 3 0x1000146 Int BE Pri
88784!#2 N4517 P2849 DWST 4 0x1000147 Int BE Pri
88785!#A N4516 N4517
88786!#2 N4518 P2850 DWST_BINIT 15 0x1000148 Int BE Pri
88787!#2 N4519 P2850 DWST_BINIT 16 0x1000149 Int BE Pri
88788!#A N4518 N4519
88789!#2 N4520 P2851 MEMBAR
88790!#2 N4521 P2852 DWLD 21 -1 Int BE Pri
88791!#2 N4522 P2852 DWLD 22 -1 Int BE Pri
88792!#A N4521 N4522
88793!#2 N4523 P2853 MEMBAR
88794!#2 N4524 P2854 BSTC 18 0x408000ff FP BE Pri
88795!#2 N4525 P2854 BSTC 19 0x40800100 FP BE Pri
88796!#A N4524 N4525
88797!#2 N4526 P2854 BSTC 20 0x40800101 FP BE Pri
88798!#2 N4527 P2855 MEMBAR
88799!#2 N4528 P2856 BST 15 0x40800102 FP BE Pri
88800!#2 N4529 P2856 BST 16 0x40800103 FP BE Pri
88801!#A N4528 N4529
88802!#2 N4530 P2856 BST 17 0x40800104 FP BE Pri
88803!#2 N4531 P2857 MEMBAR
88804!#2 N4532 P2858 BLD 0 -1 FP BE Pri
88805!#2 N4533 P2858 BLD 1 -1 FP BE Pri
88806!#A N4532 N4533
88807!#2 N4534 P2858 BLD 2 -1 FP BE Pri
88808!#2 N4535 P2859 MEMBAR
88809!#2 N4536 P2860 ST 14 0x100014a Int BE Pri
88810!#2 N4537 P2861 DWST_BINIT 11 0x100014b Int BE Pri
88811!#2 N4538 P2862 MEMBAR
88812!#2 N4539 P2863 SWAP 16 0xffffffff 0x100014c Int BE Pri
88813!#2 N4540 P2864 MEMBAR
88814!#2 N4541 P2865 BLD 15 -1 FP BE Pri
88815!#2 N4542 P2865 BLD 16 -1 FP BE Pri
88816!#A N4541 N4542
88817!#2 N4543 P2865 BLD 17 -1 FP BE Pri
88818!#2 N4544 P2866 MEMBAR
88819!#2 N4545 P2867 BSTC 6 0x40800105 FP BE Pri
88820!#2 N4546 P2867 BSTC 7 0x40800106 FP BE Pri
88821!#A N4545 N4546
88822!#2 N4547 P2867 BSTC 8 0x40800107 FP BE Pri
88823!#2 N4548 P2868 MEMBAR
88824!#2 N4549 P2869 REPLACEMENT 6 Int BE Pri
88825!#2 N4550 P2870 LD 3 -1 Int LE Pri
88826!#2 N4551 P2870 CAS 3 -1 N4550 0x100014d Int LE Pri
88827!#2 N4552 P2871 MEMBAR
88828!#2 N4553 P2872 BLD 9 -1 FP BE Pri
88829!#2 N4554 P2872 BLD 10 -1 FP BE Pri
88830!#A N4553 N4554
88831!#2 N4555 P2872 BLD 11 -1 FP BE Pri
88832!#2 N4556 P2873 MEMBAR
88833!#2 N4557 P2874 BSTC 12 0x40800108 FP BE Pri
88834!#2 N4558 P2874 BSTC 13 0x40800109 FP BE Pri
88835!#A N4557 N4558
88836!#2 N4559 P2874 BSTC 14 0x4080010a FP BE Pri
88837!#2 N4560 P2875 MEMBAR
88838!#2 N4561 P2876 REPLACEMENT 6 Int BE Pri
88839!#2 N4562 P2877 PREFETCH 4 Int BE Pri
88840!#2 N4563 P2878 MEMBAR
88841!#2 N4564 P2879 BLD 3 -1 FP BE Pri
88842!#2 N4565 P2879 BLD 4 -1 FP BE Pri
88843!#A N4564 N4565
88844!#2 N4566 P2879 BLD 5 -1 FP BE Pri
88845!#2 N4567 P2880 MEMBAR
88846!#2 N4568 P2881 BST 3 0x4080010b FP BE Pri
88847!#2 N4569 P2881 BST 4 0x4080010c FP BE Pri
88848!#A N4568 N4569
88849!#2 N4570 P2881 BST 5 0x4080010d FP BE Pri
88850!#2 N4571 P2882 MEMBAR
88851!#2 N4572 P2883 DWLD 9 -1 Int BE Pri
88852!#2 N4573 P2883 DWLD 10 -1 Int BE Pri
88853!#A N4572 N4573
88854!#2 N4574 P2884 LD 5 -1 Int BE Pri
88855!#2 N4575 P2884 CAS 5 -1 N4574 0x100014e Int BE Pri
88856!#2 N4576 P2885 MEMBAR
88857!#2 N4577 P2886 BLD 21 -1 FP BE Pri
88858!#2 N4578 P2886 BLD 22 -1 FP BE Pri
88859!#A N4577 N4578
88860!#2 N4579 P2886 BLD 23 -1 FP BE Pri
88861!#2 N4580 P2887 MEMBAR
88862!#2 N4581 P2888 BSTC 21 0x4080010e FP BE Pri
88863!#2 N4582 P2888 BSTC 22 0x4080010f FP BE Pri
88864!#A N4581 N4582
88865!#2 N4583 P2888 BSTC 23 0x40800110 FP BE Pri
88866!#2 N4584 P2889 MEMBAR
88867!#2 N4585 P2890 ST_BINIT 10 0x100014f Int BE Pri
88868!#2 N4586 P2891 MEMBAR
88869!#2 N4587 P2892 BSTC 0 0x40800111 FP BE Pri
88870!#2 N4588 P2892 BSTC 1 0x40800112 FP BE Pri
88871!#A N4587 N4588
88872!#2 N4589 P2892 BSTC 2 0x40800113 FP BE Pri
88873!#2 N4590 P2893 MEMBAR
88874!#2 N4591 P2894 DWLD 14 -1,0x0 Int BE Pri
88875!#2 N4592 P2894 CASX 14 -1,0x0 N4591 0x1000150 Int BE Pri
88876!#2 N4593 P2895 MEMBAR
88877!#2 N4594 P2896 BST 15 0x40800114 FP BE Pri
88878!#2 N4595 P2896 BST 16 0x40800115 FP BE Pri
88879!#A N4594 N4595
88880!#2 N4596 P2896 BST 17 0x40800116 FP BE Pri
88881!#2 N4597 P2897 MEMBAR
88882!#2 N4598 P2898 BSTC 18 0x40800117 FP BE Pri
88883!#2 N4599 P2898 BSTC 19 0x40800118 FP BE Pri
88884!#A N4598 N4599
88885!#2 N4600 P2898 BSTC 20 0x40800119 FP BE Pri
88886!#2 N4601 P2899 MEMBAR
88887!#2 N4602 P2900 BST 6 0x4080011a FP BE Pri
88888!#2 N4603 P2900 BST 7 0x4080011b FP BE Pri
88889!#A N4602 N4603
88890!#2 N4604 P2900 BST 8 0x4080011c FP BE Pri
88891!#2 N4605 P2901 MEMBAR
88892!#2 N4606 P2902 BSTC 0 0x4080011d FP BE Pri
88893!#2 N4607 P2902 BSTC 1 0x4080011e FP BE Pri
88894!#A N4606 N4607
88895!#2 N4608 P2902 BSTC 2 0x4080011f FP BE Pri
88896!#2 N4609 P2903 MEMBAR
88897!#2 N4610 P2904 DWLD 17 -1 Int BE Pri
88898!#2 N4611 P2905 LD 10 -1 Int BE Pri
88899!#2 N4612 P2905 CAS 10 -1 N4611 0x1000151 Int BE Pri
88900!#2 N4613 P2906 LD 8 -1 Int BE Pri
88901!#2 N4614 P2906 CAS 8 -1 N4613 0x1000152 Int BE Pri
88902!#2 N4615 P2907 LD 19 -1 FP BE Pri
88903!#2 N4616 P2908 PREFETCH 4 Int BE Pri
88904!#2 N4617 P2909 DWST 9 0x40800120 FP BE Pri
88905!#2 N4618 P2909 DWST 10 0x40800121 FP BE Pri
88906!#A N4617 N4618
88907!#2 N4619 P2910 ST_BINIT 20 0x1000153 Int BE Pri
88908!#2 N4620 P2911 MEMBAR
88909!#2 N4621 P2912 LD 17 -1 Int BE Pri
88910!#2 N4622 P2913 DWST 15 0x1000154 Int LE Pri
88911!#2 N4623 P2913 DWST 16 0x1000155 Int LE Pri
88912!#A N4622 N4623
88913!#2 N4624 P2914 ST_BINIT 12 0x1000156 Int BE Pri
88914!#2 N4625 P2915 MEMBAR
88915!#2 N4626 P2916 LD 17 -1 Int BE Pri
88916!#2 N4627 P2916 CAS 17 -1 N4626 0x1000157 Int BE Pri
88917!#2 N4628 P2917 LDD 23 -1 Int BE Pri
88918!#2 N4629 P2918 MEMBAR
88919!#2 N4630 P2919 BSTC 15 0x40800122 FP BE Pri
88920!#2 N4631 P2919 BSTC 16 0x40800123 FP BE Pri
88921!#A N4630 N4631
88922!#2 N4632 P2919 BSTC 17 0x40800124 FP BE Pri
88923!#2 N4633 P2920 MEMBAR
88924!#2 N4634 P2921 BST 15 0x40800125 FP BE Pri
88925!#2 N4635 P2921 BST 16 0x40800126 FP BE Pri
88926!#A N4634 N4635
88927!#2 N4636 P2921 BST 17 0x40800127 FP BE Pri
88928!#2 N4637 P2922 MEMBAR
88929!#2 N4638 P2923 DWLD 15 -1 Int BE Pri
88930!#2 N4639 P2923 DWLD 16 -1 Int BE Pri
88931!#A N4638 N4639
88932!#2 N4640 P2923 CASX 15 -1 N4638 0x1000158 Int BE Pri
88933!#2 N4641 P2923 CASX 16 -1 N4639 0x1000159 Int BE Pri
88934!#A N4640 N4641
88935!#2 N4642 P2924 MEMBAR
88936!#2 N4643 P2925 BSTC 15 0x40800128 FP BE Pri
88937!#2 N4644 P2925 BSTC 16 0x40800129 FP BE Pri
88938!#A N4643 N4644
88939!#2 N4645 P2925 BSTC 17 0x4080012a FP BE Pri
88940!#2 N4646 P2926 MEMBAR
88941!#2 N4647 P2927 LD 2 -1 Int BE Pri
88942!#2 N4648 P2928 LD 6 -1 Int BE Pri
88943!#2 N4649 P2929 ST_BINIT 13 0x100015a Int BE Pri
88944!#2 N4650 P2930 MEMBAR
88945!#2 N4651 P2931 DWST_BINIT 11 0x100015b Int BE Pri
88946!#2 N4652 P2932 MEMBAR
88947!#2 N4653 P2933 DWST 2 0x100015c Int BE Pri
88948!#2 N4654 P2934 MEMBAR
88949!#2 N4655 P2935 BLD 18 -1 FP BE Pri
88950!#2 N4656 P2935 BLD 19 -1 FP BE Pri
88951!#A N4655 N4656
88952!#2 N4657 P2935 BLD 20 -1 FP BE Pri
88953!#2 N4658 P2936 MEMBAR
88954!#2 N4659 P2937 SWAP 23 0xffffffff 0x100015d Int BE Pri
88955!#2 N4660 P2938 MEMBAR
88956!#2 N4661 P2939 BSTC 21 0x4080012b FP BE Pri
88957!#2 N4662 P2939 BSTC 22 0x4080012c FP BE Pri
88958!#A N4661 N4662
88959!#2 N4663 P2939 BSTC 23 0x4080012d FP BE Pri
88960!#2 N4664 P2940 MEMBAR
88961!#2 N4665 P2941 LD 21 -1 Int BE Pri
88962!#2 N4666 P2941 CAS 21 -1 N4665 0x100015e Int BE Pri
88963!#2 N4667 P2942 ST 20 0x100015f Int BE Pri
88964!#2 N4668 P2943 MEMBAR
88965!#2 N4669 P2944 BST 0 0x4080012e FP BE Pri
88966!#2 N4670 P2944 BST 1 0x4080012f FP BE Pri
88967!#A N4669 N4670
88968!#2 N4671 P2944 BST 2 0x40800130 FP BE Pri
88969!#2 N4672 P2945 MEMBAR
88970!#2 N4673 P2946 REPLACEMENT 15 Int BE Pri
88971!#2 N4674 P2947 LDD 9 -1 Int BE Pri
88972!#2 N4675 P2947 LDD 10 -1 Int BE Pri
88973!#A N4674 N4675
88974!#2 N4676 P2948 MEMBAR
88975!#2 N4677 P2949 BST 12 0x40800131 FP BE Pri
88976!#2 N4678 P2949 BST 13 0x40800132 FP BE Pri
88977!#A N4677 N4678
88978!#2 N4679 P2949 BST 14 0x40800133 FP BE Pri
88979!#2 N4680 P2950 MEMBAR
88980!#2 N4681 P2951 DWLD 8 -1 Int BE Pri
88981!#2 N4682 P2952 ST_BINIT 16 0x1000160 Int BE Pri
88982!#2 N4683 P2953 MEMBAR
88983!#2 N4684 P2954 ST_BINIT 16 0x1000161 Int BE Pri
88984!#2 N4685 P2955 MEMBAR
88985!#2 N4686 P2956 ST_BINIT 12 0x1000162 Int BE Pri
88986!#2 N4687 P2957 MEMBAR
88987!#2 N4688 P2958 BLD 6 -1 FP BE Pri
88988!#2 N4689 P2958 BLD 7 -1 FP BE Pri
88989!#A N4688 N4689
88990!#2 N4690 P2958 BLD 8 -1 FP BE Pri
88991!#2 N4691 P2959 MEMBAR
88992!#2 N4692 P2960 LDD 21 -1 Int BE Pri
88993!#2 N4693 P2960 LDD 22 -1 Int BE Pri
88994!#A N4692 N4693
88995!#2 N4694 P2961 LD 0 -1 Int BE Pri
88996!#2 N4695 P2962 LD 23 -1 Int BE Pri
88997!#2 N4696 P2962 CAS 23 -1 N4695 0x1000163 Int BE Pri
88998!#2 N4697 P2963 LDD 2 -1 Int BE Pri
88999!#2 N4698 P2964 MEMBAR
89000!#2 N4699 P2965 BST 3 0x40800134 FP BE Pri
89001!#2 N4700 P2965 BST 4 0x40800135 FP BE Pri
89002!#A N4699 N4700
89003!#2 N4701 P2965 BST 5 0x40800136 FP BE Pri
89004!#2 N4702 P2966 MEMBAR
89005!#2 N4703 P2967 DWST_BINIT 11 0x1000164 Int BE Pri
89006!#2 N4704 P2968 MEMBAR
89007!#2 N4705 P2969 DWST 0 0x1000165 Int BE Pri
89008!#2 N4706 P2969 DWST 1 0x1000166 Int BE Pri
89009!#A N4705 N4706
89010!#2 N4707 P2970 DWST 21 0x1000167 Int BE Pri
89011!#2 N4708 P2970 DWST 22 0x1000168 Int BE Pri
89012!#A N4707 N4708
89013!#2 N4709 P2971 REPLACEMENT 15 Int BE Pri
89014!#2 N4710 P2972 DWLD 2 -1 Int BE Pri
89015!#2 N4711 P2973 SWAP 3 0xffffffff 0x1000169 Int BE Pri
89016!#2 N4712 P2974 ST_BINIT 12 0x100016a Int BE Pri
89017!#2 N4713 P2975 MEMBAR
89018!#2 N4714 P2976 BLD 18 -1 FP BE Pri
89019!#2 N4715 P2976 BLD 19 -1 FP BE Pri
89020!#A N4714 N4715
89021!#2 N4716 P2976 BLD 20 -1 FP BE Pri
89022!#2 N4717 P2977 MEMBAR
89023!#2 N4718 P2978 REPLACEMENT 18 Int BE Pri
89024!#2 N4719 P2979 ST 0 0x100016b Int BE Pri
89025!#2 N4720 P2980 DWST_BINIT 12 0x100016c Int BE Pri
89026!#2 N4721 P2980 DWST_BINIT 13 0x100016d Int BE Pri
89027!#A N4720 N4721
89028!#2 N4722 P2981 MEMBAR
89029!#2 N4723 P2982 BLD 12 -1 FP BE Pri
89030!#2 N4724 P2982 BLD 13 -1 FP BE Pri
89031!#A N4723 N4724
89032!#2 N4725 P2982 BLD 14 -1 FP BE Pri
89033!#2 N4726 P2983 MEMBAR
89034!#2 N4727 P2984 BST 12 0x40800137 FP BE Pri
89035!#2 N4728 P2984 BST 13 0x40800138 FP BE Pri
89036!#A N4727 N4728
89037!#2 N4729 P2984 BST 14 0x40800139 FP BE Pri
89038!#2 N4730 P2985 MEMBAR
89039!#2 N4731 P2986 LD 7 -1 Int BE Pri
89040!#2 N4732 P2986 CAS 7 -1 N4731 0x100016e Int BE Pri
89041!#2 N4733 P2987 DWST 0 0x100016f Int BE Pri
89042!#2 N4734 P2987 DWST 1 0x1000170 Int BE Pri
89043!#A N4733 N4734
89044!#2 N4735 P2988 SWAP 12 0xffffffff 0x1000171 Int BE Pri
89045!#2 N4736 P2989 MEMBAR
89046!#2 N4737 P2990 BLD 15 -1 FP BE Pri
89047!#2 N4738 P2990 BLD 16 -1 FP BE Pri
89048!#A N4737 N4738
89049!#2 N4739 P2990 BLD 17 -1 FP BE Pri
89050!#2 N4740 P2991 MEMBAR
89051!#2 N4741 P2992 DWLD 23 -1,0x0 Int BE Pri
89052!#2 N4742 P2992 CASX 23 -1,0x0 N4741 0x1000172 Int BE Pri
89053!#2 N4743 P2993 LDD 15 -1 Int BE Pri
89054!#2 N4744 P2993 LDD 16 -1 Int BE Pri
89055!#A N4743 N4744
89056!#2 N4745 P2994 ST_BINIT 20 0x1000173 Int BE Pri
89057!#2 N4746 P2995 MEMBAR
89058!#2 N4747 P2996 LDD 0 -1 Int BE Pri
89059!#2 N4748 P2996 LDD 1 -1 Int BE Pri
89060!#A N4747 N4748
89061!#2 N4749 P2997 PREFETCH 13 Int BE Pri
89062!#2 N4750 P2998 ST_BINIT 3 0x1000174 Int BE Pri
89063!#2 N4751 P2999 MEMBAR
89064!#2 N4752 P3000 DWST 2 0x1000175 Int BE Pri
89065!#2 N4753 P3001 DWST_BINIT 23 0x1000176 Int BE Pri
89066!#2 N4754 P3002 MEMBAR
89067!#2 N4755 P3003 ST_BINIT 14 0x1000177 Int BE Pri
89068!#2 N4756 P3004 MEMBAR
89069!#2 N4757 P3005 MEMBAR
89070!#3 N4758 P3006 ST_BINIT 0 0x1800001 Int BE Pri Loop_entry
89071!#3 N4759 P3007 MEMBAR
89072!#3 N4760 P3008 LDD 12 -1 Int BE Pri
89073!#3 N4761 P3008 LDD 13 -1 Int BE Pri
89074!#A N4760 N4761
89075!#3 N4762 P3009 LD 0 -1 Int BE Pri
89076!#3 N4763 P3009 CAS 0 -1 N4762 0x1800002 Int BE Pri
89077!#3 N4764 P3010 DWLD 6 -1 Int LE Pri
89078!#3 N4765 P3010 DWLD 7 -1 Int LE Pri
89079!#A N4764 N4765
89080!#3 N4766 P3010 CASX 6 -1 N4764 0x1800003 Int LE Pri
89081!#3 N4767 P3010 CASX 7 -1 N4765 0x1800004 Int LE Pri
89082!#A N4766 N4767
89083!#3 N4768 P3011 DWST_BINIT 3 0x1800005 Int BE Pri
89084!#3 N4769 P3011 DWST_BINIT 4 0x1800006 Int BE Pri
89085!#A N4768 N4769
89086!#3 N4770 P3012 MEMBAR
89087!#3 N4771 P3013 LDD 12 -1 Int BE Pri
89088!#3 N4772 P3013 LDD 13 -1 Int BE Pri
89089!#A N4771 N4772
89090!#3 N4773 P3014 ST_BINIT 11 0x1800007 Int BE Pri
89091!#3 N4774 P3015 MEMBAR
89092!#3 N4775 P3016 REPLACEMENT 0 Int BE Pri
89093!#3 N4776 P3017 LD 22 -1 Int BE Pri
89094!#3 N4777 P3018 PREFETCH 21 Int BE Pri
89095!#3 N4778 P3019 MEMBAR
89096!#3 N4779 P3020 BSTC 18 0x41000001 FP BE Pri
89097!#3 N4780 P3020 BSTC 19 0x41000002 FP BE Pri
89098!#A N4779 N4780
89099!#3 N4781 P3020 BSTC 20 0x41000003 FP BE Pri
89100!#3 N4782 P3021 MEMBAR
89101!#3 N4783 P3022 SWAP 3 0xffffffff 0x1800008 Int BE Pri
89102!#3 N4784 P3023 DWLD 11 -1 FP BE Pri
89103!#3 N4785 P3024 SWAP 10 0xffffffff 0x1800009 Int BE Pri
89104!#3 N4786 P3025 DWLD 14 -1 FP BE Pri
89105!#3 N4787 P3026 ST 16 0x180000a Int BE Pri
89106!#3 N4788 P3027 ST 22 0x180000b Int BE Pri
89107!#3 N4789 P3028 DWST_BINIT 23 0x180000c Int BE Pri
89108!#3 N4790 P3029 MEMBAR
89109!#3 N4791 P3030 DWST_BINIT 3 0x180000d Int BE Pri
89110!#3 N4792 P3030 DWST_BINIT 4 0x180000e Int BE Pri
89111!#A N4791 N4792
89112!#3 N4793 P3031 MEMBAR
89113!#3 N4794 P3032 DWLD 5 -1,0x0 Int BE Pri
89114!#3 N4795 P3032 CASX 5 -1,0x0 N4794 0x180000f Int BE Pri
89115!#3 N4796 P3033 DWST 18 0x1800010 Int BE Pri
89116!#3 N4797 P3033 DWST 19 0x1800011 Int BE Pri
89117!#A N4796 N4797
89118!#3 N4798 P3034 DWST 2 0x1800012 Int BE Pri
89119!#3 N4799 P3035 MEMBAR
89120!#3 N4800 P3036 BST 18 0x41000004 FP BE Pri
89121!#3 N4801 P3036 BST 19 0x41000005 FP BE Pri
89122!#A N4800 N4801
89123!#3 N4802 P3036 BST 20 0x41000006 FP BE Pri
89124!#3 N4803 P3037 MEMBAR
89125!#3 N4804 P3038 DWST_BINIT 21 0x1800013 Int BE Pri
89126!#3 N4805 P3038 DWST_BINIT 22 0x1800014 Int BE Pri
89127!#A N4804 N4805
89128!#3 N4806 P3039 MEMBAR
89129!#3 N4807 P3040 LDD 20 -1 Int BE Pri
89130!#3 N4808 P3041 PREFETCH 9 Int BE Pri
89131!#3 N4809 P3042 MEMBAR
89132!#3 N4810 P3043 BLD 3 -1 FP BE Pri
89133!#3 N4811 P3043 BLD 4 -1 FP BE Pri
89134!#A N4810 N4811
89135!#3 N4812 P3043 BLD 5 -1 FP BE Pri
89136!#3 N4813 P3044 MEMBAR
89137!#3 N4814 P3045 ST_BINIT 0 0x1800015 Int BE Pri
89138!#3 N4815 P3046 MEMBAR
89139!#3 N4816 P3047 DWST_BINIT 12 0x1800016 Int BE Pri
89140!#3 N4817 P3047 DWST_BINIT 13 0x1800017 Int BE Pri
89141!#A N4816 N4817
89142!#3 N4818 P3048 MEMBAR
89143!#3 N4819 P3049 LD 1 -1 Int BE Pri
89144!#3 N4820 P3049 CAS 1 -1 N4819 0x1800018 Int BE Pri
89145!#3 N4821 P3050 SWAP 12 0xffffffff 0x1800019 Int BE Pri
89146!#3 N4822 P3051 ST 4 0x180001a Int BE Pri
89147!#3 N4823 P3052 DWST 6 0x180001b Int BE Pri
89148!#3 N4824 P3052 DWST 7 0x180001c Int BE Pri
89149!#A N4823 N4824
89150!#3 N4825 P3053 DWST_BINIT 6 0x180001d Int BE Pri
89151!#3 N4826 P3053 DWST_BINIT 7 0x180001e Int BE Pri
89152!#A N4825 N4826
89153!#3 N4827 P3054 MEMBAR
89154!#3 N4828 P3055 LD 5 -1 Int BE Pri
89155!#3 N4829 P3056 ST_BINIT 2 0x180001f Int BE Pri
89156!#3 N4830 P3057 MEMBAR
89157!#3 N4831 P3058 LD 5 -1 Int BE Pri
89158!#3 N4832 P3059 PREFETCH 10 Int BE Pri
89159!#3 N4833 P3060 DWST_BINIT 15 0x1800020 Int BE Pri
89160!#3 N4834 P3060 DWST_BINIT 16 0x1800021 Int BE Pri
89161!#A N4833 N4834
89162!#3 N4835 P3061 MEMBAR
89163!#3 N4836 P3062 BLD 21 -1 FP BE Pri
89164!#3 N4837 P3062 BLD 22 -1 FP BE Pri
89165!#A N4836 N4837
89166!#3 N4838 P3062 BLD 23 -1 FP BE Pri
89167!#3 N4839 P3063 MEMBAR
89168!#3 N4840 P3064 LD 20 -1 Int LE Pri
89169!#3 N4841 P3065 DWST_BINIT 15 0x1800022 Int BE Pri
89170!#3 N4842 P3065 DWST_BINIT 16 0x1800023 Int BE Pri
89171!#A N4841 N4842
89172!#3 N4843 P3066 MEMBAR
89173!#3 N4844 P3067 BLD 6 -1 FP BE Pri
89174!#3 N4845 P3067 BLD 7 -1 FP BE Pri
89175!#A N4844 N4845
89176!#3 N4846 P3067 BLD 8 -1 FP BE Pri
89177!#3 N4847 P3068 MEMBAR
89178!#3 N4848 P3069 DWLD 21 -1 Int BE Pri
89179!#3 N4849 P3069 DWLD 22 -1 Int BE Pri
89180!#A N4848 N4849
89181!#3 N4850 P3070 DWST 21 0x1800024 Int BE Pri
89182!#3 N4851 P3070 DWST 22 0x1800025 Int BE Pri
89183!#A N4850 N4851
89184!#3 N4852 P3071 LDD 18 -1 Int BE Pri
89185!#3 N4853 P3071 LDD 19 -1 Int BE Pri
89186!#A N4852 N4853
89187!#3 N4854 P3072 DWLD 18 -1 Int BE Pri
89188!#3 N4855 P3072 DWLD 19 -1 Int BE Pri
89189!#A N4854 N4855
89190!#3 N4856 P3072 CASX 18 -1 N4854 0x1800026 Int BE Pri
89191!#3 N4857 P3072 CASX 19 -1 N4855 0x1800027 Int BE Pri
89192!#A N4856 N4857
89193!#3 N4858 P3073 REPLACEMENT 15 Int BE Pri
89194!#3 N4859 P3074 MEMBAR
89195!#3 N4860 P3075 BLD 21 -1 FP BE Pri
89196!#3 N4861 P3075 BLD 22 -1 FP BE Pri
89197!#A N4860 N4861
89198!#3 N4862 P3075 BLD 23 -1 FP BE Pri
89199!#3 N4863 P3076 MEMBAR
89200!#3 N4864 P3077 PREFETCH 12 Int BE Pri
89201!#3 N4865 P3078 SWAP 9 0xffffffff 0x1800028 Int BE Pri
89202!#3 N4866 P3079 ST 15 0x1800029 Int BE Pri
89203!#3 N4867 P3080 LDD 20 -1 Int BE Pri
89204!#3 N4868 P3081 DWLD 9 -1 Int BE Pri
89205!#3 N4869 P3081 DWLD 10 -1 Int BE Pri
89206!#A N4868 N4869
89207!#3 N4870 P3081 CASX 9 -1 N4868 0x180002a Int BE Pri
89208!#3 N4871 P3081 CASX 10 -1 N4869 0x180002b Int BE Pri
89209!#A N4870 N4871
89210!#3 N4872 P3082 MEMBAR
89211!#3 N4873 P3083 BSTC 18 0x41000007 FP BE Pri
89212!#3 N4874 P3083 BSTC 19 0x41000008 FP BE Pri
89213!#A N4873 N4874
89214!#3 N4875 P3083 BSTC 20 0x41000009 FP BE Pri
89215!#3 N4876 P3084 MEMBAR
89216!#3 N4877 P3085 REPLACEMENT 14 Int BE Pri
89217!#3 N4878 P3086 PREFETCH 21 Int LE Pri
89218!#3 N4879 P3087 LD 10 -1 Int BE Pri
89219!#3 N4880 P3087 CAS 10 -1 N4879 0x180002c Int BE Pri
89220!#3 N4881 P3088 ST_BINIT 15 0x180002d Int BE Pri
89221!#3 N4882 P3089 MEMBAR
89222!#3 N4883 P3090 BLD 15 -1 FP BE Pri
89223!#3 N4884 P3090 BLD 16 -1 FP BE Pri
89224!#A N4883 N4884
89225!#3 N4885 P3090 BLD 17 -1 FP BE Pri
89226!#3 N4886 P3091 MEMBAR
89227!#3 N4887 P3092 ST_BINIT 7 0x180002e Int BE Pri
89228!#3 N4888 P3093 MEMBAR
89229!#3 N4889 P3094 DWST 18 0x180002f Int BE Pri
89230!#3 N4890 P3094 DWST 19 0x1800030 Int BE Pri
89231!#A N4889 N4890
89232!#3 N4891 P3095 MEMBAR
89233!#3 N4892 P3096 BST 3 0x4100000a FP BE Pri
89234!#3 N4893 P3096 BST 4 0x4100000b FP BE Pri
89235!#A N4892 N4893
89236!#3 N4894 P3096 BST 5 0x4100000c FP BE Pri
89237!#3 N4895 P3097 MEMBAR
89238!#3 N4896 P3098 DWST 8 0x1800031 Int BE Pri
89239!#3 N4897 P3099 LD 15 -1 Int BE Pri
89240!#3 N4898 P3100 DWLD 17 -1,0x0 Int BE Pri
89241!#3 N4899 P3100 CASX 17 -1,0x0 N4898 0x1800032 Int BE Pri
89242!#3 N4900 P3101 DWLD 0 -1 Int BE Pri
89243!#3 N4901 P3101 DWLD 1 -1 Int BE Pri
89244!#A N4900 N4901
89245!#3 N4902 P3101 CASX 0 -1 N4900 0x1800033 Int BE Pri
89246!#3 N4903 P3101 CASX 1 -1 N4901 0x1800034 Int BE Pri
89247!#A N4902 N4903
89248!#3 N4904 P3102 LDD 21 -1 Int BE Pri
89249!#3 N4905 P3102 LDD 22 -1 Int BE Pri
89250!#A N4904 N4905
89251!#3 N4906 P3103 MEMBAR
89252!#3 N4907 P3104 BLD 3 -1 FP BE Pri
89253!#3 N4908 P3104 BLD 4 -1 FP BE Pri
89254!#A N4907 N4908
89255!#3 N4909 P3104 BLD 5 -1 FP BE Pri
89256!#3 N4910 P3105 MEMBAR
89257!#3 N4911 P3106 BLD 12 -1 FP BE Pri
89258!#3 N4912 P3106 BLD 13 -1 FP BE Pri
89259!#A N4911 N4912
89260!#3 N4913 P3106 BLD 14 -1 FP BE Pri
89261!#3 N4914 P3107 MEMBAR
89262!#3 N4915 P3108 BLD 12 -1 FP BE Pri
89263!#3 N4916 P3108 BLD 13 -1 FP BE Pri
89264!#A N4915 N4916
89265!#3 N4917 P3108 BLD 14 -1 FP BE Pri
89266!#3 N4918 P3109 MEMBAR
89267!#3 N4919 P3110 DWLD 8 -1,0x0 Int BE Pri
89268!#3 N4920 P3110 CASX 8 -1,0x0 N4919 0x1800035 Int BE Pri
89269!#3 N4921 P3111 LDD 9 -1 Int BE Pri
89270!#3 N4922 P3111 LDD 10 -1 Int BE Pri
89271!#A N4921 N4922
89272!#3 N4923 P3112 DWST_BINIT 14 0x1800036 Int BE Pri
89273!#3 N4924 P3113 MEMBAR
89274!#3 N4925 P3114 LD 17 -1 Int BE Pri
89275!#3 N4926 P3115 LD 5 -1 Int BE Pri
89276!#3 N4927 P3115 CAS 5 -1 N4926 0x1800037 Int BE Pri
89277!#3 N4928 P3116 LD 1 -1 Int BE Pri
89278!#3 N4929 P3116 CAS 1 -1 N4928 0x1800038 Int BE Pri
89279!#3 N4930 P3117 PREFETCH 9 Int BE Pri
89280!#3 N4931 P3118 DWLD 14 -1 Int BE Pri
89281!#3 N4932 P3119 MEMBAR
89282!#3 N4933 P3120 BSTC 15 0x4100000d FP BE Pri
89283!#3 N4934 P3120 BSTC 16 0x4100000e FP BE Pri
89284!#A N4933 N4934
89285!#3 N4935 P3120 BSTC 17 0x4100000f FP BE Pri
89286!#3 N4936 P3121 MEMBAR
89287!#3 N4937 P3122 LDD 0 -1 Int BE Pri
89288!#3 N4938 P3122 LDD 1 -1 Int BE Pri
89289!#A N4937 N4938
89290!#3 N4939 P3123 MEMBAR
89291!#3 N4940 P3124 BST 21 0x41000010 FP BE Pri
89292!#3 N4941 P3124 BST 22 0x41000011 FP BE Pri
89293!#A N4940 N4941
89294!#3 N4942 P3124 BST 23 0x41000012 FP BE Pri
89295!#3 N4943 P3125 MEMBAR
89296!#3 N4944 P3126 DWLD 23 -1,0x0 Int BE Pri
89297!#3 N4945 P3126 CASX 23 -1,0x0 N4944 0x1800039 Int BE Pri
89298!#3 N4946 P3127 MEMBAR
89299!#3 N4947 P3128 BST 21 0x41000013 FP BE Pri
89300!#3 N4948 P3128 BST 22 0x41000014 FP BE Pri
89301!#A N4947 N4948
89302!#3 N4949 P3128 BST 23 0x41000015 FP BE Pri
89303!#3 N4950 P3129 MEMBAR
89304!#3 N4951 P3130 BLD 3 -1 FP BE Pri
89305!#3 N4952 P3130 BLD 4 -1 FP BE Pri
89306!#A N4951 N4952
89307!#3 N4953 P3130 BLD 5 -1 FP BE Pri
89308!#3 N4954 P3131 MEMBAR
89309!#3 N4955 P3132 DWST_BINIT 3 0x180003a Int BE Pri
89310!#3 N4956 P3132 DWST_BINIT 4 0x180003b Int BE Pri
89311!#A N4955 N4956
89312!#3 N4957 P3133 MEMBAR
89313!#3 N4958 P3134 ST_BINIT 7 0x180003c Int BE Pri
89314!#3 N4959 P3135 MEMBAR
89315!#3 N4960 P3136 BSTC 18 0x41000016 FP BE Pri
89316!#3 N4961 P3136 BSTC 19 0x41000017 FP BE Pri
89317!#A N4960 N4961
89318!#3 N4962 P3136 BSTC 20 0x41000018 FP BE Pri
89319!#3 N4963 P3137 MEMBAR
89320!#3 N4964 P3138 REPLACEMENT 5 Int BE Pri
89321!#3 N4965 P3139 REPLACEMENT 10 Int BE Pri
89322!#3 N4966 P3140 LD 18 -1 Int BE Pri
89323!#3 N4967 P3141 DWLD 3 -1 Int BE Pri
89324!#3 N4968 P3141 DWLD 4 -1 Int BE Pri
89325!#A N4967 N4968
89326!#3 N4969 P3142 DWLD 15 -1 Int BE Pri
89327!#3 N4970 P3142 DWLD 16 -1 Int BE Pri
89328!#A N4969 N4970
89329!#3 N4971 P3142 CASX 15 -1 N4969 0x180003d Int BE Pri
89330!#3 N4972 P3142 CASX 16 -1 N4970 0x180003e Int BE Pri
89331!#A N4971 N4972
89332!#3 N4973 P3143 SWAP 19 0xffffffff 0x180003f Int BE Pri
89333!#3 N4974 P3144 LD 17 -1 Int BE Pri
89334!#3 N4975 P3144 CAS 17 -1 N4974 0x1800040 Int BE Pri
89335!#3 N4976 P3145 PREFETCH 15 Int BE Pri
89336!#3 N4977 P3146 DWLD 18 -1 Int BE Pri
89337!#3 N4978 P3146 DWLD 19 -1 Int BE Pri
89338!#A N4977 N4978
89339!#3 N4979 P3146 CASX 18 -1 N4977 0x1800041 Int BE Pri
89340!#3 N4980 P3146 CASX 19 -1 N4978 0x1800042 Int BE Pri
89341!#A N4979 N4980
89342!#3 N4981 P3147 ST_BINIT 1 0x1800043 Int BE Pri
89343!#3 N4982 P3148 MEMBAR
89344!#3 N4983 P3149 DWST 18 0x1800044 Int BE Pri
89345!#3 N4984 P3149 DWST 19 0x1800045 Int BE Pri
89346!#A N4983 N4984
89347!#3 N4985 P3150 LDD 5 -1 Int BE Pri
89348!#3 N4986 P3151 LD 1 -1 Int BE Pri
89349!#3 N4987 P3152 MEMBAR
89350!#3 N4988 P3153 BLD 9 -1 FP BE Pri
89351!#3 N4989 P3153 BLD 10 -1 FP BE Pri
89352!#A N4988 N4989
89353!#3 N4990 P3153 BLD 11 -1 FP BE Pri
89354!#3 N4991 P3154 MEMBAR
89355!#3 N4992 P3155 BLD 0 -1 FP BE Pri
89356!#3 N4993 P3155 BLD 1 -1 FP BE Pri
89357!#A N4992 N4993
89358!#3 N4994 P3155 BLD 2 -1 FP BE Pri
89359!#3 N4995 P3156 MEMBAR
89360!#3 N4996 P3157 LDD 20 -1 Int BE Pri
89361!#3 N4997 P3158 LDD 18 -1 Int BE Pri
89362!#3 N4998 P3158 LDD 19 -1 Int BE Pri
89363!#A N4997 N4998
89364!#3 N4999 P3159 MEMBAR
89365!#3 N5000 P3160 BSTC 12 0x41000019 FP BE Pri
89366!#3 N5001 P3160 BSTC 13 0x4100001a FP BE Pri
89367!#A N5000 N5001
89368!#3 N5002 P3160 BSTC 14 0x4100001b FP BE Pri
89369!#3 N5003 P3161 MEMBAR
89370!#3 N5004 P3162 DWST 12 0x1800046 Int BE Pri
89371!#3 N5005 P3162 DWST 13 0x1800047 Int BE Pri
89372!#A N5004 N5005
89373!#3 N5006 P3163 ST_BINIT 7 0x1800048 Int BE Pri
89374!#3 N5007 P3164 MEMBAR
89375!#3 N5008 P3165 PREFETCH 15 Int BE Pri
89376!#3 N5009 P3166 DWLD 23 -1,0x0 Int BE Pri
89377!#3 N5010 P3166 CASX 23 -1,0x0 N5009 0x1800049 Int BE Pri
89378!#3 N5011 P3167 LD 4 -1 Int BE Pri
89379!#3 N5012 P3167 CAS 4 -1 N5011 0x180004a Int BE Pri
89380!#3 N5013 P3168 DWLD 9 -1 Int BE Pri
89381!#3 N5014 P3168 DWLD 10 -1 Int BE Pri
89382!#A N5013 N5014
89383!#3 N5015 P3169 MEMBAR
89384!#3 N5016 P3170 BLD 12 -1 FP BE Pri
89385!#3 N5017 P3170 BLD 13 -1 FP BE Pri
89386!#A N5016 N5017
89387!#3 N5018 P3170 BLD 14 -1 FP BE Pri
89388!#3 N5019 P3171 MEMBAR
89389!#3 N5020 P3172 BST 3 0x4100001c FP BE Pri
89390!#3 N5021 P3172 BST 4 0x4100001d FP BE Pri
89391!#A N5020 N5021
89392!#3 N5022 P3172 BST 5 0x4100001e FP BE Pri
89393!#3 N5023 P3173 MEMBAR
89394!#3 N5024 P3174 BST 0 0x4100001f FP BE Pri
89395!#3 N5025 P3174 BST 1 0x41000020 FP BE Pri
89396!#A N5024 N5025
89397!#3 N5026 P3174 BST 2 0x41000021 FP BE Pri
89398!#3 N5027 P3175 MEMBAR
89399!#3 N5028 P3176 REPLACEMENT 6 Int BE Pri
89400!#3 N5029 P3177 LD 4 -1 Int BE Pri
89401!#3 N5030 P3178 MEMBAR
89402!#3 N5031 P3179 BSTC 12 0x41000022 FP BE Pri
89403!#3 N5032 P3179 BSTC 13 0x41000023 FP BE Pri
89404!#A N5031 N5032
89405!#3 N5033 P3179 BSTC 14 0x41000024 FP BE Pri
89406!#3 N5034 P3180 MEMBAR
89407!#3 N5035 P3181 SWAP 2 0xffffffff 0x180004b Int BE Pri
89408!#3 N5036 P3182 LD 5 -1 Int LE Pri
89409!#3 N5037 P3182 CAS 5 -1 N5036 0x180004c Int LE Pri
89410!#3 N5038 P3183 MEMBAR
89411!#3 N5039 P3184 BLD 18 -1 FP BE Pri
89412!#3 N5040 P3184 BLD 19 -1 FP BE Pri
89413!#A N5039 N5040
89414!#3 N5041 P3184 BLD 20 -1 FP BE Pri
89415!#3 N5042 P3185 MEMBAR
89416!#3 N5043 P3186 LDD 9 -1 Int BE Pri
89417!#3 N5044 P3186 LDD 10 -1 Int BE Pri
89418!#A N5043 N5044
89419!#3 N5045 P3187 DWST_BINIT 12 0x180004d Int BE Pri
89420!#3 N5046 P3187 DWST_BINIT 13 0x180004e Int BE Pri
89421!#A N5045 N5046
89422!#3 N5047 P3188 MEMBAR
89423!#3 N5048 P3189 LD 22 -1 Int BE Pri
89424!#3 N5049 P3189 CAS 22 -1 N5048 0x180004f Int BE Pri
89425!#3 N5050 P3190 LD 2 -1 Int BE Pri
89426!#3 N5051 P3191 MEMBAR
89427!#3 N5052 P3192 BLD 6 -1 FP BE Pri
89428!#3 N5053 P3192 BLD 7 -1 FP BE Pri
89429!#A N5052 N5053
89430!#3 N5054 P3192 BLD 8 -1 FP BE Pri
89431!#3 N5055 P3193 MEMBAR
89432!#3 N5056 P3194 BSTC 9 0x41000025 FP BE Pri
89433!#3 N5057 P3194 BSTC 10 0x41000026 FP BE Pri
89434!#A N5056 N5057
89435!#3 N5058 P3194 BSTC 11 0x41000027 FP BE Pri
89436!#3 N5059 P3195 MEMBAR
89437!#3 N5060 P3196 LD 1 -1 Int BE Pri
89438!#3 N5061 P3197 REPLACEMENT 9 Int BE Pri
89439!#3 N5062 P3198 DWST 0 0x1800050 Int BE Pri
89440!#3 N5063 P3198 DWST 1 0x1800051 Int BE Pri
89441!#A N5062 N5063
89442!#3 N5064 P3199 LD 19 -1 Int BE Pri
89443!#3 N5065 P3199 CAS 19 -1 N5064 0x1800052 Int BE Pri
89444!#3 N5066 P3200 DWST_BINIT 2 0x1800053 Int BE Pri
89445!#3 N5067 P3201 MEMBAR
89446!#3 N5068 P3202 DWST 6 0x1800054 Int BE Pri
89447!#3 N5069 P3202 DWST 7 0x1800055 Int BE Pri
89448!#A N5068 N5069
89449!#3 N5070 P3203 MEMBAR
89450!#3 N5071 P3204 BST 15 0x41000028 FP BE Pri
89451!#3 N5072 P3204 BST 16 0x41000029 FP BE Pri
89452!#A N5071 N5072
89453!#3 N5073 P3204 BST 17 0x4100002a FP BE Pri
89454!#3 N5074 P3205 MEMBAR
89455!#3 N5075 P3206 ST 16 0x1800056 Int BE Pri
89456!#3 N5076 P3207 LD 15 -1 Int BE Pri
89457!#3 N5077 P3207 CAS 15 -1 N5076 0x1800057 Int BE Pri
89458!#3 N5078 P3208 LD 13 -1 Int BE Pri
89459!#3 N5079 P3209 DWLD 15 -1 Int BE Pri
89460!#3 N5080 P3209 DWLD 16 -1 Int BE Pri
89461!#A N5079 N5080
89462!#3 N5081 P3209 CASX 15 -1 N5079 0x1800058 Int BE Pri
89463!#3 N5082 P3209 CASX 16 -1 N5080 0x1800059 Int BE Pri
89464!#A N5081 N5082
89465!#3 N5083 P3210 DWST_BINIT 0 0x180005a Int BE Pri
89466!#3 N5084 P3210 DWST_BINIT 1 0x180005b Int BE Pri
89467!#A N5083 N5084
89468!#3 N5085 P3211 MEMBAR
89469!#3 N5086 P3212 DWST 21 0x180005c Int BE Pri
89470!#3 N5087 P3212 DWST 22 0x180005d Int BE Pri
89471!#A N5086 N5087
89472!#3 N5088 P3213 DWLD 12 -1 Int BE Pri
89473!#3 N5089 P3213 DWLD 13 -1 Int BE Pri
89474!#A N5088 N5089
89475!#3 N5090 P3214 SWAP 11 0xffffffff 0x180005e Int BE Pri
89476!#3 N5091 P3215 MEMBAR
89477!#3 N5092 P3216 BLD 0 -1 FP BE Pri
89478!#3 N5093 P3216 BLD 1 -1 FP BE Pri
89479!#A N5092 N5093
89480!#3 N5094 P3216 BLD 2 -1 FP BE Pri
89481!#3 N5095 P3217 MEMBAR
89482!#3 N5096 P3218 BLD 21 -1 FP BE Pri
89483!#3 N5097 P3218 BLD 22 -1 FP BE Pri
89484!#A N5096 N5097
89485!#3 N5098 P3218 BLD 23 -1 FP BE Pri
89486!#3 N5099 P3219 MEMBAR
89487!#3 N5100 P3220 BST 18 0x4100002b FP BE Pri
89488!#3 N5101 P3220 BST 19 0x4100002c FP BE Pri
89489!#A N5100 N5101
89490!#3 N5102 P3220 BST 20 0x4100002d FP BE Pri
89491!#3 N5103 P3221 MEMBAR
89492!#3 N5104 P3222 PREFETCH 2 Int BE Pri
89493!#3 N5105 P3223 MEMBAR
89494!#3 N5106 P3224 BSTC 6 0x4100002e FP BE Pri
89495!#3 N5107 P3224 BSTC 7 0x4100002f FP BE Pri
89496!#A N5106 N5107
89497!#3 N5108 P3224 BSTC 8 0x41000030 FP BE Pri
89498!#3 N5109 P3225 MEMBAR
89499!#3 N5110 P3226 DWST 0 0x180005f Int BE Pri
89500!#3 N5111 P3226 DWST 1 0x1800060 Int BE Pri
89501!#A N5110 N5111
89502!#3 N5112 P3227 ST 13 0x1800061 Int BE Pri
89503!#3 N5113 P3228 LD 19 -1 Int BE Pri
89504!#3 N5114 P3228 CAS 19 -1 N5113 0x1800062 Int BE Pri
89505!#3 N5115 P3229 DWLD 0 -1 Int BE Pri
89506!#3 N5116 P3229 DWLD 1 -1 Int BE Pri
89507!#A N5115 N5116
89508!#3 N5117 P3230 DWLD 15 -1 Int BE Pri
89509!#3 N5118 P3230 DWLD 16 -1 Int BE Pri
89510!#A N5117 N5118
89511!#3 N5119 P3230 CASX 15 -1 N5117 0x1800063 Int BE Pri
89512!#3 N5120 P3230 CASX 16 -1 N5118 0x1800064 Int BE Pri
89513!#A N5119 N5120
89514!#3 N5121 P3231 DWLD 0 -1 Int BE Pri
89515!#3 N5122 P3231 DWLD 1 -1 Int BE Pri
89516!#A N5121 N5122
89517!#3 N5123 P3231 CASX 0 -1 N5121 0x1800065 Int BE Pri
89518!#3 N5124 P3231 CASX 1 -1 N5122 0x1800066 Int BE Pri
89519!#A N5123 N5124
89520!#3 N5125 P3232 LD 22 -1 Int BE Pri
89521!#3 N5126 P3233 DWST 21 0x1800067 Int BE Pri
89522!#3 N5127 P3233 DWST 22 0x1800068 Int BE Pri
89523!#A N5126 N5127
89524!#3 N5128 P3234 LDD 21 -1 Int BE Pri
89525!#3 N5129 P3234 LDD 22 -1 Int BE Pri
89526!#A N5128 N5129
89527!#3 N5130 P3235 MEMBAR
89528!#3 N5131 P3236 BLD 12 -1 FP BE Pri
89529!#3 N5132 P3236 BLD 13 -1 FP BE Pri
89530!#A N5131 N5132
89531!#3 N5133 P3236 BLD 14 -1 FP BE Pri
89532!#3 N5134 P3237 MEMBAR
89533!#3 N5135 P3238 DWLD 0 -1 Int BE Pri
89534!#3 N5136 P3238 DWLD 1 -1 Int BE Pri
89535!#A N5135 N5136
89536!#3 N5137 P3239 LDD 0 -1 Int BE Pri
89537!#3 N5138 P3239 LDD 1 -1 Int BE Pri
89538!#A N5137 N5138
89539!#3 N5139 P3240 LD 14 -1 Int BE Pri
89540!#3 N5140 P3241 LD 22 -1 Int BE Pri
89541!#3 N5141 P3241 CAS 22 -1 N5140 0x1800069 Int BE Pri
89542!#3 N5142 P3242 SWAP 1 0xffffffff 0x180006a Int BE Pri
89543!#3 N5143 P3243 LD 8 -1 Int BE Pri
89544!#3 N5144 P3244 ST_BINIT 6 0x180006b Int BE Pri
89545!#3 N5145 P3245 MEMBAR
89546!#3 N5146 P3246 LD 4 -1 Int BE Pri
89547!#3 N5147 P3246 CAS 4 -1 N5146 0x180006c Int BE Pri
89548!#3 N5148 P3247 DWST_BINIT 23 0x180006d Int BE Pri
89549!#3 N5149 P3248 MEMBAR
89550!#3 N5150 P3249 LDD 21 -1 Int BE Pri
89551!#3 N5151 P3249 LDD 22 -1 Int BE Pri
89552!#A N5150 N5151
89553!#3 N5152 P3250 ST 22 0x180006e Int BE Pri
89554!#3 N5153 P3251 LDD 6 -1 Int BE Pri
89555!#3 N5154 P3251 LDD 7 -1 Int BE Pri
89556!#A N5153 N5154
89557!#3 N5155 P3252 ST 3 0x180006f Int BE Pri
89558!#3 N5156 P3253 MEMBAR
89559!#3 N5157 P3254 BST 0 0x41000031 FP BE Pri
89560!#3 N5158 P3254 BST 1 0x41000032 FP BE Pri
89561!#A N5157 N5158
89562!#3 N5159 P3254 BST 2 0x41000033 FP BE Pri
89563!#3 N5160 P3255 MEMBAR
89564!#3 N5161 P3256 ST_BINIT 2 0x1800070 Int BE Pri
89565!#3 N5162 P3257 MEMBAR
89566!#3 N5163 P3258 LD 17 -1 Int BE Pri
89567!#3 N5164 P3259 MEMBAR
89568!#3 N5165 P3260 BST 18 0x41000034 FP BE Pri
89569!#3 N5166 P3260 BST 19 0x41000035 FP BE Pri
89570!#A N5165 N5166
89571!#3 N5167 P3260 BST 20 0x41000036 FP BE Pri
89572!#3 N5168 P3261 MEMBAR
89573!#3 N5169 P3262 LDD 0 -1 Int BE Pri
89574!#3 N5170 P3262 LDD 1 -1 Int BE Pri
89575!#A N5169 N5170
89576!#3 N5171 P3263 MEMBAR
89577!#3 N5172 P3264 BSTC 6 0x41000037 FP BE Pri
89578!#3 N5173 P3264 BSTC 7 0x41000038 FP BE Pri
89579!#A N5172 N5173
89580!#3 N5174 P3264 BSTC 8 0x41000039 FP BE Pri
89581!#3 N5175 P3265 MEMBAR
89582!#3 N5176 P3266 BST 0 0x4100003a FP BE Pri
89583!#3 N5177 P3266 BST 1 0x4100003b FP BE Pri
89584!#A N5176 N5177
89585!#3 N5178 P3266 BST 2 0x4100003c FP BE Pri
89586!#3 N5179 P3267 MEMBAR
89587!#3 N5180 P3268 DWST_BINIT 5 0x1800071 Int LE Pri
89588!#3 N5181 P3269 MEMBAR
89589!#3 N5182 P3270 DWST 15 0x1800072 Int BE Pri
89590!#3 N5183 P3270 DWST 16 0x1800073 Int BE Pri
89591!#A N5182 N5183
89592!#3 N5184 P3271 ST 13 0x1800074 Int BE Pri
89593!#3 N5185 P3272 REPLACEMENT 23 Int BE Pri
89594!#3 N5186 P3273 DWST 15 0x1800075 Int BE Pri
89595!#3 N5187 P3273 DWST 16 0x1800076 Int BE Pri
89596!#A N5186 N5187
89597!#3 N5188 P3274 REPLACEMENT 1 Int BE Pri
89598!#3 N5189 P3275 DWLD 6 -1 Int BE Pri
89599!#3 N5190 P3275 DWLD 7 -1 Int BE Pri
89600!#A N5189 N5190
89601!#3 N5191 P3275 CASX 6 -1 N5189 0x1800077 Int BE Pri
89602!#3 N5192 P3275 CASX 7 -1 N5190 0x1800078 Int BE Pri
89603!#A N5191 N5192
89604!#3 N5193 P3276 DWLD 9 -1 Int BE Pri
89605!#3 N5194 P3276 DWLD 10 -1 Int BE Pri
89606!#A N5193 N5194
89607!#3 N5195 P3277 SWAP 6 0xffffffff 0x1800079 Int BE Pri
89608!#3 N5196 P3278 MEMBAR
89609!#3 N5197 P3279 BLD 12 -1 FP BE Pri
89610!#3 N5198 P3279 BLD 13 -1 FP BE Pri
89611!#A N5197 N5198
89612!#3 N5199 P3279 BLD 14 -1 FP BE Pri
89613!#3 N5200 P3280 MEMBAR
89614!#3 N5201 P3281 ST_BINIT 9 0x180007a Int BE Pri
89615!#3 N5202 P3282 MEMBAR
89616!#3 N5203 P3283 LDD 2 -1 Int BE Pri
89617!#3 N5204 P3284 MEMBAR
89618!#3 N5205 P3285 BST 18 0x4100003d FP BE Pri
89619!#3 N5206 P3285 BST 19 0x4100003e FP BE Pri
89620!#A N5205 N5206
89621!#3 N5207 P3285 BST 20 0x4100003f FP BE Pri
89622!#3 N5208 P3286 MEMBAR
89623!#3 N5209 P3287 DWLD 15 -1 Int BE Pri
89624!#3 N5210 P3287 DWLD 16 -1 Int BE Pri
89625!#A N5209 N5210
89626!#3 N5211 P3287 CASX 15 -1 N5209 0x180007b Int BE Pri
89627!#3 N5212 P3287 CASX 16 -1 N5210 0x180007c Int BE Pri
89628!#A N5211 N5212
89629!#3 N5213 P3288 DWST_BINIT 0 0x180007d Int BE Pri
89630!#3 N5214 P3288 DWST_BINIT 1 0x180007e Int BE Pri
89631!#A N5213 N5214
89632!#3 N5215 P3289 MEMBAR
89633!#3 N5216 P3290 BST 9 0x41000040 FP BE Pri
89634!#3 N5217 P3290 BST 10 0x41000041 FP BE Pri
89635!#A N5216 N5217
89636!#3 N5218 P3290 BST 11 0x41000042 FP BE Pri
89637!#3 N5219 P3291 MEMBAR
89638!#3 N5220 P3292 ST 18 0x41000043 FP BE Pri
89639!#3 N5221 P3293 DWST_BINIT 3 0x180007f Int BE Pri
89640!#3 N5222 P3293 DWST_BINIT 4 0x1800080 Int BE Pri
89641!#A N5221 N5222
89642!#3 N5223 P3294 MEMBAR
89643!#3 N5224 P3295 LDD 14 -1 Int BE Pri
89644!#3 N5225 P3296 LD 16 -1 Int BE Pri
89645!#3 N5226 P3297 DWST_BINIT 12 0x1800081 Int BE Pri
89646!#3 N5227 P3297 DWST_BINIT 13 0x1800082 Int BE Pri
89647!#A N5226 N5227
89648!#3 N5228 P3298 MEMBAR
89649!#3 N5229 P3299 LD 20 -1 Int LE Pri
89650!#3 N5230 P3299 CAS 20 -1 N5229 0x1800083 Int LE Pri
89651!#3 N5231 P3300 ST 22 0x1800084 Int BE Pri
89652!#3 N5232 P3301 MEMBAR
89653!#3 N5233 P3302 BST 3 0x41000044 FP BE Pri
89654!#3 N5234 P3302 BST 4 0x41000045 FP BE Pri
89655!#A N5233 N5234
89656!#3 N5235 P3302 BST 5 0x41000046 FP BE Pri
89657!#3 N5236 P3303 MEMBAR
89658!#3 N5237 P3304 BSTC 0 0x41000047 FP BE Pri
89659!#3 N5238 P3304 BSTC 1 0x41000048 FP BE Pri
89660!#A N5237 N5238
89661!#3 N5239 P3304 BSTC 2 0x41000049 FP BE Pri
89662!#3 N5240 P3305 MEMBAR
89663!#3 N5241 P3306 REPLACEMENT 9 Int BE Pri
89664!#3 N5242 P3307 MEMBAR
89665!#3 N5243 P3308 BST 6 0x4100004a FP BE Pri
89666!#3 N5244 P3308 BST 7 0x4100004b FP BE Pri
89667!#A N5243 N5244
89668!#3 N5245 P3308 BST 8 0x4100004c FP BE Pri
89669!#3 N5246 P3309 MEMBAR
89670!#3 N5247 P3310 DWLD 18 -1 Int BE Pri
89671!#3 N5248 P3310 DWLD 19 -1 Int BE Pri
89672!#A N5247 N5248
89673!#3 N5249 P3310 CASX 18 -1 N5247 0x1800085 Int BE Pri
89674!#3 N5250 P3310 CASX 19 -1 N5248 0x1800086 Int BE Pri
89675!#A N5249 N5250
89676!#3 N5251 P3311 DWLD 9 -1 Int BE Pri
89677!#3 N5252 P3311 DWLD 10 -1 Int BE Pri
89678!#A N5251 N5252
89679!#3 N5253 P3311 CASX 9 -1 N5251 0x1800087 Int BE Pri
89680!#3 N5254 P3311 CASX 10 -1 N5252 0x1800088 Int BE Pri
89681!#A N5253 N5254
89682!#3 N5255 P3312 LDD 3 -1 Int BE Pri
89683!#3 N5256 P3312 LDD 4 -1 Int BE Pri
89684!#A N5255 N5256
89685!#3 N5257 P3313 PREFETCH 15 Int BE Pri
89686!#3 N5258 P3314 ST_BINIT 10 0x1800089 Int BE Pri
89687!#3 N5259 P3315 MEMBAR
89688!#3 N5260 P3316 DWST 15 0x180008a Int BE Pri
89689!#3 N5261 P3316 DWST 16 0x180008b Int BE Pri
89690!#A N5260 N5261
89691!#3 N5262 P3317 MEMBAR
89692!#3 N5263 P3318 BLD 0 -1 FP BE Pri
89693!#3 N5264 P3318 BLD 1 -1 FP BE Pri
89694!#A N5263 N5264
89695!#3 N5265 P3318 BLD 2 -1 FP BE Pri
89696!#3 N5266 P3319 MEMBAR
89697!#3 N5267 P3320 PREFETCH 1 Int BE Pri
89698!#3 N5268 P3321 REPLACEMENT 8 Int BE Pri
89699!#3 N5269 P3322 ST 9 0x180008c Int LE Pri
89700!#3 N5270 P3323 PREFETCH 16 Int BE Pri
89701!#3 N5271 P3324 ST_BINIT 19 0x180008d Int BE Pri
89702!#3 N5272 P3325 MEMBAR
89703!#3 N5273 P3326 ST_BINIT 6 0x180008e Int BE Pri
89704!#3 N5274 P3327 MEMBAR
89705!#3 N5275 P3328 LD 7 -1 Int BE Pri
89706!#3 N5276 P3328 CAS 7 -1 N5275 0x180008f Int BE Pri
89707!#3 N5277 P3329 PREFETCH 4 Int BE Pri
89708!#3 N5278 P3330 DWST_BINIT 17 0x1800090 Int BE Pri
89709!#3 N5279 P3331 MEMBAR
89710!#3 N5280 P3332 LDD 12 -1 Int LE Pri
89711!#3 N5281 P3332 LDD 13 -1 Int LE Pri
89712!#A N5280 N5281
89713!#3 N5282 P3333 MEMBAR
89714!#3 N5283 P3334 BST 6 0x4100004d FP BE Pri
89715!#3 N5284 P3334 BST 7 0x4100004e FP BE Pri
89716!#A N5283 N5284
89717!#3 N5285 P3334 BST 8 0x4100004f FP BE Pri
89718!#3 N5286 P3335 MEMBAR
89719!#3 N5287 P3336 LD 22 -1 Int BE Pri
89720!#3 N5288 P3337 MEMBAR
89721!#3 N5289 P3338 BLD 6 -1 FP BE Pri
89722!#3 N5290 P3338 BLD 7 -1 FP BE Pri
89723!#A N5289 N5290
89724!#3 N5291 P3338 BLD 8 -1 FP BE Pri
89725!#3 N5292 P3339 MEMBAR
89726!#3 N5293 P3340 SWAP 17 0xffffffff 0x1800091 Int BE Pri
89727!#3 N5294 P3341 SWAP 8 0xffffffff 0x1800092 Int BE Pri
89728!#3 N5295 P3342 SWAP 6 0xffffffff 0x1800093 Int BE Pri
89729!#3 N5296 P3343 ST_BINIT 21 0x1800094 Int BE Pri
89730!#3 N5297 P3344 MEMBAR
89731!#3 N5298 P3345 DWLD 8 -1 FP BE Pri
89732!#3 N5299 P3346 DWST 21 0x1800095 Int BE Pri
89733!#3 N5300 P3346 DWST 22 0x1800096 Int BE Pri
89734!#A N5299 N5300
89735!#3 N5301 P3347 LD 5 -1 Int BE Pri
89736!#3 N5302 P3348 SWAP 1 0xffffffff 0x1800097 Int BE Pri
89737!#3 N5303 P3349 LD 7 -1 Int BE Pri
89738!#3 N5304 P3349 CAS 7 -1 N5303 0x1800098 Int BE Pri
89739!#3 N5305 P3350 MEMBAR
89740!#3 N5306 P3351 BLD 3 -1 FP BE Pri
89741!#3 N5307 P3351 BLD 4 -1 FP BE Pri
89742!#A N5306 N5307
89743!#3 N5308 P3351 BLD 5 -1 FP BE Pri
89744!#3 N5309 P3352 MEMBAR
89745!#3 N5310 P3353 BST 12 0x41000050 FP BE Pri
89746!#3 N5311 P3353 BST 13 0x41000051 FP BE Pri
89747!#A N5310 N5311
89748!#3 N5312 P3353 BST 14 0x41000052 FP BE Pri
89749!#3 N5313 P3354 MEMBAR
89750!#3 N5314 P3355 PREFETCH 12 Int BE Pri
89751!#3 N5315 P3356 DWLD 21 -1 Int BE Pri
89752!#3 N5316 P3356 DWLD 22 -1 Int BE Pri
89753!#A N5315 N5316
89754!#3 N5317 P3356 CASX 21 -1 N5315 0x1800099 Int BE Pri
89755!#3 N5318 P3356 CASX 22 -1 N5316 0x180009a Int BE Pri
89756!#A N5317 N5318
89757!#3 N5319 P3357 SWAP 6 0xffffffff 0x180009b Int BE Pri
89758!#3 N5320 P3358 PREFETCH 8 Int LE Pri
89759!#3 N5321 P3359 DWST 20 0x180009c Int BE Pri
89760!#3 N5322 P3360 DWLD 3 -1 Int BE Pri
89761!#3 N5323 P3360 DWLD 4 -1 Int BE Pri
89762!#A N5322 N5323
89763!#3 N5324 P3360 CASX 3 -1 N5322 0x180009d Int BE Pri
89764!#3 N5325 P3360 CASX 4 -1 N5323 0x180009e Int BE Pri
89765!#A N5324 N5325
89766!#3 N5326 P3361 LD 9 -1 Int BE Pri
89767!#3 N5327 P3362 ST 7 0x180009f Int BE Pri
89768!#3 N5328 P3363 LDD 9 -1 Int BE Pri
89769!#3 N5329 P3363 LDD 10 -1 Int BE Pri
89770!#A N5328 N5329
89771!#3 N5330 P3364 ST_BINIT 15 0x18000a0 Int BE Pri
89772!#3 N5331 P3365 MEMBAR
89773!#3 N5332 P3366 LD 4 -1 Int BE Pri
89774!#3 N5333 P3366 CAS 4 -1 N5332 0x18000a1 Int BE Pri
89775!#3 N5334 P3367 MEMBAR
89776!#3 N5335 P3368 BLD 21 -1 FP BE Pri
89777!#3 N5336 P3368 BLD 22 -1 FP BE Pri
89778!#A N5335 N5336
89779!#3 N5337 P3368 BLD 23 -1 FP BE Pri
89780!#3 N5338 P3369 MEMBAR
89781!#3 N5339 P3370 BLD 6 -1 FP BE Pri
89782!#3 N5340 P3370 BLD 7 -1 FP BE Pri
89783!#A N5339 N5340
89784!#3 N5341 P3370 BLD 8 -1 FP BE Pri
89785!#3 N5342 P3371 MEMBAR
89786!#3 N5343 P3372 ST_BINIT 14 0x18000a2 Int BE Pri
89787!#3 N5344 P3373 MEMBAR
89788!#3 N5345 P3374 BSTC 15 0x41000053 FP BE Pri
89789!#3 N5346 P3374 BSTC 16 0x41000054 FP BE Pri
89790!#A N5345 N5346
89791!#3 N5347 P3374 BSTC 17 0x41000055 FP BE Pri
89792!#3 N5348 P3375 MEMBAR
89793!#3 N5349 P3376 BSTC 21 0x41000056 FP BE Pri
89794!#3 N5350 P3376 BSTC 22 0x41000057 FP BE Pri
89795!#A N5349 N5350
89796!#3 N5351 P3376 BSTC 23 0x41000058 FP BE Pri
89797!#3 N5352 P3377 MEMBAR
89798!#3 N5353 P3378 DWLD 3 -1 Int BE Pri
89799!#3 N5354 P3378 DWLD 4 -1 Int BE Pri
89800!#A N5353 N5354
89801!#3 N5355 P3378 CASX 3 -1 N5353 0x18000a3 Int BE Pri
89802!#3 N5356 P3378 CASX 4 -1 N5354 0x18000a4 Int BE Pri
89803!#A N5355 N5356
89804!#3 N5357 P3379 DWST 21 0x18000a5 Int BE Pri
89805!#3 N5358 P3379 DWST 22 0x18000a6 Int BE Pri
89806!#A N5357 N5358
89807!#3 N5359 P3380 LD 2 -1 Int BE Pri
89808!#3 N5360 P3380 CAS 2 -1 N5359 0x18000a7 Int BE Pri
89809!#3 N5361 P3381 SWAP 3 0xffffffff 0x18000a8 Int BE Pri
89810!#3 N5362 P3382 DWLD 21 -1 Int BE Pri
89811!#3 N5363 P3382 DWLD 22 -1 Int BE Pri
89812!#A N5362 N5363
89813!#3 N5364 P3383 MEMBAR
89814!#3 N5365 P3384 BST 18 0x41000059 FP BE Pri
89815!#3 N5366 P3384 BST 19 0x4100005a FP BE Pri
89816!#A N5365 N5366
89817!#3 N5367 P3384 BST 20 0x4100005b FP BE Pri
89818!#3 N5368 P3385 MEMBAR
89819!#3 N5369 P3386 LD 3 -1 Int BE Pri
89820!#3 N5370 P3386 CAS 3 -1 N5369 0x18000a9 Int BE Pri
89821!#3 N5371 P3387 LD 8 -1 Int BE Pri
89822!#3 N5372 P3387 CAS 8 -1 N5371 0x18000aa Int BE Pri
89823!#3 N5373 P3388 ST 8 0x4100005c FP BE Pri
89824!#3 N5374 P3389 LD 5 -1 Int BE Pri
89825!#3 N5375 P3390 ST_BINIT 12 0x18000ab Int BE Pri
89826!#3 N5376 P3391 MEMBAR
89827!#3 N5377 P3392 ST_BINIT 17 0x18000ac Int BE Pri
89828!#3 N5378 P3393 MEMBAR
89829!#3 N5379 P3394 PREFETCH 9 Int BE Pri
89830!#3 N5380 P3395 PREFETCH 8 Int BE Pri
89831!#3 N5381 P3396 MEMBAR
89832!#3 N5382 P3397 BST 21 0x4100005d FP BE Pri
89833!#3 N5383 P3397 BST 22 0x4100005e FP BE Pri
89834!#A N5382 N5383
89835!#3 N5384 P3397 BST 23 0x4100005f FP BE Pri
89836!#3 N5385 P3398 MEMBAR
89837!#3 N5386 P3399 PREFETCH 19 Int BE Pri
89838!#3 N5387 P3400 DWST_BINIT 2 0x18000ad Int BE Pri
89839!#3 N5388 P3401 MEMBAR
89840!#3 N5389 P3402 DWLD 6 -1 Int BE Pri
89841!#3 N5390 P3402 DWLD 7 -1 Int BE Pri
89842!#A N5389 N5390
89843!#3 N5391 P3402 CASX 6 -1 N5389 0x18000ae Int BE Pri
89844!#3 N5392 P3402 CASX 7 -1 N5390 0x18000af Int BE Pri
89845!#A N5391 N5392
89846!#3 N5393 P3403 LDD 3 -1 Int BE Pri
89847!#3 N5394 P3403 LDD 4 -1 Int BE Pri
89848!#A N5393 N5394
89849!#3 N5395 P3404 DWLD 12 -1 Int BE Pri
89850!#3 N5396 P3404 DWLD 13 -1 Int BE Pri
89851!#A N5395 N5396
89852!#3 N5397 P3404 CASX 12 -1 N5395 0x18000b0 Int BE Pri
89853!#3 N5398 P3404 CASX 13 -1 N5396 0x18000b1 Int BE Pri
89854!#A N5397 N5398
89855!#3 N5399 P3405 DWST 6 0x18000b2 Int BE Pri
89856!#3 N5400 P3405 DWST 7 0x18000b3 Int BE Pri
89857!#A N5399 N5400
89858!#3 N5401 P3406 LD 13 -1 FP BE Pri
89859!#3 N5402 P3407 DWLD 12 -1 Int BE Pri
89860!#3 N5403 P3407 DWLD 13 -1 Int BE Pri
89861!#A N5402 N5403
89862!#3 N5404 P3408 MEMBAR
89863!#3 N5405 P3409 BSTC 0 0x41000060 FP BE Pri
89864!#3 N5406 P3409 BSTC 1 0x41000061 FP BE Pri
89865!#A N5405 N5406
89866!#3 N5407 P3409 BSTC 2 0x41000062 FP BE Pri
89867!#3 N5408 P3410 MEMBAR
89868!#3 N5409 P3411 DWST 14 0x18000b4 Int BE Pri
89869!#3 N5410 P3412 ST_BINIT 13 0x18000b5 Int BE Pri
89870!#3 N5411 P3413 MEMBAR
89871!#3 N5412 P3414 LDD 17 -1 Int BE Pri
89872!#3 N5413 P3415 MEMBAR
89873!#3 N5414 P3416 BLD 15 -1 FP BE Pri
89874!#3 N5415 P3416 BLD 16 -1 FP BE Pri
89875!#A N5414 N5415
89876!#3 N5416 P3416 BLD 17 -1 FP BE Pri
89877!#3 N5417 P3417 MEMBAR
89878!#3 N5418 P3418 LDD 15 -1 Int BE Pri
89879!#3 N5419 P3418 LDD 16 -1 Int BE Pri
89880!#A N5418 N5419
89881!#3 N5420 P3419 LDD 3 -1 Int BE Pri
89882!#3 N5421 P3419 LDD 4 -1 Int BE Pri
89883!#A N5420 N5421
89884!#3 N5422 P3420 LD 9 -1 Int BE Pri
89885!#3 N5423 P3420 CAS 9 -1 N5422 0x18000b6 Int BE Pri
89886!#3 N5424 P3421 DWST_BINIT 18 0x18000b7 Int BE Pri
89887!#3 N5425 P3421 DWST_BINIT 19 0x18000b8 Int BE Pri
89888!#A N5424 N5425
89889!#3 N5426 P3422 MEMBAR
89890!#3 N5427 P3423 LD 16 -1 Int BE Pri
89891!#3 N5428 P3423 CAS 16 -1 N5427 0x18000b9 Int BE Pri
89892!#3 N5429 P3424 SWAP 9 0xffffffff 0x18000ba Int BE Pri
89893!#3 N5430 P3425 LD 21 -1 Int BE Pri
89894!#3 N5431 P3425 CAS 21 -1 N5430 0x18000bb Int BE Pri
89895!#3 N5432 P3426 DWST_BINIT 18 0x18000bc Int BE Pri
89896!#3 N5433 P3426 DWST_BINIT 19 0x18000bd Int BE Pri
89897!#A N5432 N5433
89898!#3 N5434 P3427 MEMBAR
89899!#3 N5435 P3428 BLD 15 -1 FP BE Pri
89900!#3 N5436 P3428 BLD 16 -1 FP BE Pri
89901!#A N5435 N5436
89902!#3 N5437 P3428 BLD 17 -1 FP BE Pri
89903!#3 N5438 P3429 MEMBAR
89904!#3 N5439 P3430 REPLACEMENT 19 Int BE Pri
89905!#3 N5440 P3431 ST 5 0x18000be Int BE Pri
89906!#3 N5441 P3432 ST_BINIT 10 0x18000bf Int BE Pri
89907!#3 N5442 P3433 MEMBAR
89908!#3 N5443 P3434 LD 12 -1 Int BE Pri
89909!#3 N5444 P3434 CAS 12 -1 N5443 0x18000c0 Int BE Pri
89910!#3 N5445 P3435 MEMBAR
89911!#3 N5446 P3436 BLD 9 -1 FP BE Pri
89912!#3 N5447 P3436 BLD 10 -1 FP BE Pri
89913!#A N5446 N5447
89914!#3 N5448 P3436 BLD 11 -1 FP BE Pri
89915!#3 N5449 P3437 MEMBAR
89916!#3 N5450 P3438 BLD 12 -1 FP BE Pri
89917!#3 N5451 P3438 BLD 13 -1 FP BE Pri
89918!#A N5450 N5451
89919!#3 N5452 P3438 BLD 14 -1 FP BE Pri
89920!#3 N5453 P3439 MEMBAR
89921!#3 N5454 P3440 PREFETCH 20 Int BE Pri
89922!#3 N5455 P3441 REPLACEMENT 23 Int BE Pri
89923!#3 N5456 P3442 DWST 15 0x18000c1 Int BE Pri
89924!#3 N5457 P3442 DWST 16 0x18000c2 Int BE Pri
89925!#A N5456 N5457
89926!#3 N5458 P3443 LD 19 -1 Int BE Pri
89927!#3 N5459 P3444 LDD 14 -1 Int BE Pri
89928!#3 N5460 P3445 MEMBAR
89929!#3 N5461 P3446 BSTC 9 0x41000063 FP BE Pri
89930!#3 N5462 P3446 BSTC 10 0x41000064 FP BE Pri
89931!#A N5461 N5462
89932!#3 N5463 P3446 BSTC 11 0x41000065 FP BE Pri
89933!#3 N5464 P3447 MEMBAR
89934!#3 N5465 P3448 BLD 21 -1 FP BE Pri
89935!#3 N5466 P3448 BLD 22 -1 FP BE Pri
89936!#A N5465 N5466
89937!#3 N5467 P3448 BLD 23 -1 FP BE Pri
89938!#3 N5468 P3449 MEMBAR
89939!#3 N5469 P3450 BST 15 0x41000066 FP BE Pri
89940!#3 N5470 P3450 BST 16 0x41000067 FP BE Pri
89941!#A N5469 N5470
89942!#3 N5471 P3450 BST 17 0x41000068 FP BE Pri
89943!#3 N5472 P3451 MEMBAR
89944!#3 N5473 P3452 ST 7 0x18000c3 Int BE Pri
89945!#3 N5474 P3453 DWLD 8 -1,0x0 Int BE Pri
89946!#3 N5475 P3453 CASX 8 -1,0x0 N5474 0x18000c4 Int BE Pri
89947!#3 N5476 P3454 ST_BINIT 15 0x18000c5 Int BE Pri
89948!#3 N5477 P3455 MEMBAR
89949!#3 N5478 P3456 BSTC 0 0x41000069 FP BE Pri
89950!#3 N5479 P3456 BSTC 1 0x4100006a FP BE Pri
89951!#A N5478 N5479
89952!#3 N5480 P3456 BSTC 2 0x4100006b FP BE Pri
89953!#3 N5481 P3457 MEMBAR
89954!#3 N5482 P3458 BLD 0 -1 FP BE Pri
89955!#3 N5483 P3458 BLD 1 -1 FP BE Pri
89956!#A N5482 N5483
89957!#3 N5484 P3458 BLD 2 -1 FP BE Pri
89958!#3 N5485 P3459 MEMBAR
89959!#3 N5486 P3460 LD 17 -1 Int BE Pri
89960!#3 N5487 P3461 DWLD 18 -1 Int BE Pri
89961!#3 N5488 P3461 DWLD 19 -1 Int BE Pri
89962!#A N5487 N5488
89963!#3 N5489 P3462 DWST_BINIT 17 0x18000c6 Int BE Pri
89964!#3 N5490 P3463 MEMBAR
89965!#3 N5491 P3464 DWST 15 0x18000c7 Int BE Pri
89966!#3 N5492 P3464 DWST 16 0x18000c8 Int BE Pri
89967!#A N5491 N5492
89968!#3 N5493 P3465 REPLACEMENT 18 Int BE Pri
89969!#3 N5494 P3466 ST 2 0x18000c9 Int LE Pri
89970!#3 N5495 P3467 DWLD 0 -1 Int BE Pri
89971!#3 N5496 P3467 DWLD 1 -1 Int BE Pri
89972!#A N5495 N5496
89973!#3 N5497 P3468 LD 2 -1 Int BE Pri
89974!#3 N5498 P3468 CAS 2 -1 N5497 0x18000ca Int BE Pri
89975!#3 N5499 P3469 ST 15 0x18000cb Int BE Pri
89976!#3 N5500 P3470 ST 14 0x18000cc Int BE Pri
89977!#3 N5501 P3471 MEMBAR
89978!#3 N5502 P3472 BLD 12 -1 FP BE Pri
89979!#3 N5503 P3472 BLD 13 -1 FP BE Pri
89980!#A N5502 N5503
89981!#3 N5504 P3472 BLD 14 -1 FP BE Pri
89982!#3 N5505 P3473 MEMBAR
89983!#3 N5506 P3474 PREFETCH 8 Int BE Pri
89984!#3 N5507 P3475 LD 11 -1 Int BE Pri
89985!#3 N5508 P3476 SWAP 13 0xffffffff 0x18000cd Int BE Pri
89986!#3 N5509 P3477 LD 7 -1 Int BE Pri
89987!#3 N5510 P3478 DWST 14 0x18000ce Int BE Pri
89988!#3 N5511 P3479 MEMBAR
89989!#3 N5512 P3480 BST 9 0x4100006c FP BE Pri
89990!#3 N5513 P3480 BST 10 0x4100006d FP BE Pri
89991!#A N5512 N5513
89992!#3 N5514 P3480 BST 11 0x4100006e FP BE Pri
89993!#3 N5515 P3481 MEMBAR
89994!#3 N5516 P3482 ST 23 0x18000cf Int BE Pri
89995!#3 N5517 P3483 DWST_BINIT 9 0x18000d0 Int BE Pri
89996!#3 N5518 P3483 DWST_BINIT 10 0x18000d1 Int BE Pri
89997!#A N5517 N5518
89998!#3 N5519 P3484 MEMBAR
89999!#3 N5520 P3485 BLD 12 -1 FP BE Pri
90000!#3 N5521 P3485 BLD 13 -1 FP BE Pri
90001!#A N5520 N5521
90002!#3 N5522 P3485 BLD 14 -1 FP BE Pri
90003!#3 N5523 P3486 MEMBAR
90004!#3 N5524 P3487 DWLD 12 -1 Int BE Pri
90005!#3 N5525 P3487 DWLD 13 -1 Int BE Pri
90006!#A N5524 N5525
90007!#3 N5526 P3487 CASX 12 -1 N5524 0x18000d2 Int BE Pri
90008!#3 N5527 P3487 CASX 13 -1 N5525 0x18000d3 Int BE Pri
90009!#A N5526 N5527
90010!#3 N5528 P3488 LDD 11 -1 Int BE Pri
90011!#3 N5529 P3489 LD 19 -1 Int BE Pri
90012!#3 N5530 P3490 MEMBAR
90013!#3 N5531 P3491 BLD 9 -1 FP BE Pri
90014!#3 N5532 P3491 BLD 10 -1 FP BE Pri
90015!#A N5531 N5532
90016!#3 N5533 P3491 BLD 11 -1 FP BE Pri
90017!#3 N5534 P3492 MEMBAR
90018!#3 N5535 P3493 BSTC 12 0x4100006f FP BE Pri
90019!#3 N5536 P3493 BSTC 13 0x41000070 FP BE Pri
90020!#A N5535 N5536
90021!#3 N5537 P3493 BSTC 14 0x41000071 FP BE Pri
90022!#3 N5538 P3494 MEMBAR
90023!#3 N5539 P3495 DWLD 0 -1 Int BE Pri
90024!#3 N5540 P3495 DWLD 1 -1 Int BE Pri
90025!#A N5539 N5540
90026!#3 N5541 P3496 MEMBAR
90027!#3 N5542 P3497 BST 15 0x41000072 FP BE Pri
90028!#3 N5543 P3497 BST 16 0x41000073 FP BE Pri
90029!#A N5542 N5543
90030!#3 N5544 P3497 BST 17 0x41000074 FP BE Pri
90031!#3 N5545 P3498 MEMBAR
90032!#3 N5546 P3499 DWLD 15 -1 FP BE Pri
90033!#3 N5547 P3499 DWLD 16 -1 FP BE Pri
90034!#A N5546 N5547
90035!#3 N5548 P3500 DWLD 6 -1 Int BE Pri
90036!#3 N5549 P3500 DWLD 7 -1 Int BE Pri
90037!#A N5548 N5549
90038!#3 N5550 P3501 ST 17 0x18000d4 Int BE Pri
90039!#3 N5551 P3502 LD 13 -1 Int BE Pri
90040!#3 N5552 P3502 CAS 13 -1 N5551 0x18000d5 Int BE Pri
90041!#3 N5553 P3503 ST_BINIT 13 0x18000d6 Int BE Pri
90042!#3 N5554 P3504 MEMBAR
90043!#3 N5555 P3505 ST_BINIT 18 0x18000d7 Int BE Pri
90044!#3 N5556 P3506 MEMBAR
90045!#3 N5557 P3507 BLD 18 -1 FP BE Pri
90046!#3 N5558 P3507 BLD 19 -1 FP BE Pri
90047!#A N5557 N5558
90048!#3 N5559 P3507 BLD 20 -1 FP BE Pri
90049!#3 N5560 P3508 MEMBAR
90050!#3 N5561 P3509 DWLD 3 -1 Int BE Pri
90051!#3 N5562 P3509 DWLD 4 -1 Int BE Pri
90052!#A N5561 N5562
90053!#3 N5563 P3510 DWLD 9 -1 Int BE Pri
90054!#3 N5564 P3510 DWLD 10 -1 Int BE Pri
90055!#A N5563 N5564
90056!#3 N5565 P3510 CASX 9 -1 N5563 0x18000d8 Int BE Pri
90057!#3 N5566 P3510 CASX 10 -1 N5564 0x18000d9 Int BE Pri
90058!#A N5565 N5566
90059!#3 N5567 P3511 MEMBAR
90060!#3 N5568 P3512 BLD 3 -1 FP BE Pri
90061!#3 N5569 P3512 BLD 4 -1 FP BE Pri
90062!#A N5568 N5569
90063!#3 N5570 P3512 BLD 5 -1 FP BE Pri
90064!#3 N5571 P3513 MEMBAR
90065!#3 N5572 P3514 ST 17 0x18000da Int LE Pri
90066!#3 N5573 P3515 ST_BINIT 13 0x18000db Int BE Pri
90067!#3 N5574 P3516 MEMBAR
90068!#3 N5575 P3517 ST 10 0x18000dc Int BE Pri
90069!#3 N5576 P3518 ST 12 0x18000dd Int BE Pri
90070!#3 N5577 P3519 ST_BINIT 6 0x18000de Int BE Pri
90071!#3 N5578 P3520 MEMBAR
90072!#3 N5579 P3521 SWAP 16 0xffffffff 0x18000df Int BE Pri
90073!#3 N5580 P3522 MEMBAR
90074!#3 N5581 P3523 BSTC 18 0x41000075 FP BE Pri
90075!#3 N5582 P3523 BSTC 19 0x41000076 FP BE Pri
90076!#A N5581 N5582
90077!#3 N5583 P3523 BSTC 20 0x41000077 FP BE Pri
90078!#3 N5584 P3524 MEMBAR
90079!#3 N5585 P3525 SWAP 6 0xffffffff 0x18000e0 Int BE Pri
90080!#3 N5586 P3526 SWAP 1 0xffffffff 0x18000e1 Int BE Pri
90081!#3 N5587 P3527 PREFETCH 10 Int BE Pri
90082!#3 N5588 P3528 ST 21 0x18000e2 Int BE Pri
90083!#3 N5589 P3529 DWLD 17 -1,0x0 Int BE Pri
90084!#3 N5590 P3529 CASX 17 -1,0x0 N5589 0x18000e3 Int BE Pri
90085!#3 N5591 P3530 SWAP 22 0xffffffff 0x18000e4 Int BE Pri
90086!#3 N5592 P3531 MEMBAR
90087!#3 N5593 P3532 BST 21 0x41000078 FP BE Pri
90088!#3 N5594 P3532 BST 22 0x41000079 FP BE Pri
90089!#A N5593 N5594
90090!#3 N5595 P3532 BST 23 0x4100007a FP BE Pri
90091!#3 N5596 P3533 MEMBAR
90092!#3 N5597 P3534 LD 20 -1 Int BE Pri
90093!#3 N5598 P3535 LD 19 -1 Int BE Pri
90094!#3 N5599 P3535 CAS 19 -1 N5598 0x18000e5 Int BE Pri
90095!#3 N5600 P3536 REPLACEMENT 4 Int BE Pri
90096!#3 N5601 P3537 ST 5 0x18000e6 Int BE Pri
90097!#3 N5602 P3538 DWLD 17 -1 Int BE Pri
90098!#3 N5603 P3539 LDD 6 -1 Int BE Pri
90099!#3 N5604 P3539 LDD 7 -1 Int BE Pri
90100!#A N5603 N5604
90101!#3 N5605 P3540 MEMBAR
90102!#3 N5606 P3541 BSTC 12 0x4100007b FP BE Pri
90103!#3 N5607 P3541 BSTC 13 0x4100007c FP BE Pri
90104!#A N5606 N5607
90105!#3 N5608 P3541 BSTC 14 0x4100007d FP BE Pri
90106!#3 N5609 P3542 MEMBAR
90107!#3 N5610 P3543 BST 3 0x4100007e FP BE Pri
90108!#3 N5611 P3543 BST 4 0x4100007f FP BE Pri
90109!#A N5610 N5611
90110!#3 N5612 P3543 BST 5 0x41000080 FP BE Pri
90111!#3 N5613 P3544 MEMBAR
90112!#3 N5614 P3545 PREFETCH 11 Int BE Pri
90113!#3 N5615 P3546 MEMBAR
90114!#3 N5616 P3547 BLD 9 -1 FP BE Pri
90115!#3 N5617 P3547 BLD 10 -1 FP BE Pri
90116!#A N5616 N5617
90117!#3 N5618 P3547 BLD 11 -1 FP BE Pri
90118!#3 N5619 P3548 MEMBAR
90119!#3 N5620 P3549 ST_BINIT 8 0x18000e7 Int BE Pri
90120!#3 N5621 P3550 MEMBAR
90121!#3 N5622 P3551 ST_BINIT 6 0x18000e8 Int BE Pri
90122!#3 N5623 P3552 MEMBAR
90123!#3 N5624 P3553 ST_BINIT 5 0x18000e9 Int BE Pri
90124!#3 N5625 P3554 MEMBAR
90125!#3 N5626 P3555 ST_BINIT 0 0x18000ea Int BE Pri
90126!#3 N5627 P3556 MEMBAR
90127!#3 N5628 P3557 LD 1 -1 Int BE Pri
90128!#3 N5629 P3557 CAS 1 -1 N5628 0x18000eb Int BE Pri
90129!#3 N5630 P3558 SWAP 13 0xffffffff 0x18000ec Int BE Pri
90130!#3 N5631 P3559 ST_BINIT 0 0x18000ed Int BE Pri
90131!#3 N5632 P3560 MEMBAR
90132!#3 N5633 P3561 BST 9 0x41000081 FP BE Pri
90133!#3 N5634 P3561 BST 10 0x41000082 FP BE Pri
90134!#A N5633 N5634
90135!#3 N5635 P3561 BST 11 0x41000083 FP BE Pri
90136!#3 N5636 P3562 MEMBAR
90137!#3 N5637 P3563 ST 16 0x18000ee Int BE Pri
90138!#3 N5638 P3564 PREFETCH 11 Int BE Pri
90139!#3 N5639 P3565 REPLACEMENT 12 Int BE Pri
90140!#3 N5640 P3566 ST_BINIT 22 0x18000ef Int BE Pri
90141!#3 N5641 P3567 MEMBAR
90142!#3 N5642 P3568 LD 15 -1 Int BE Pri
90143!#3 N5643 P3568 CAS 15 -1 N5642 0x18000f0 Int BE Pri
90144!#3 N5644 P3569 ST 15 0x18000f1 Int BE Pri
90145!#3 N5645 P3570 LD 4 -1 Int BE Pri
90146!#3 N5646 P3570 CAS 4 -1 N5645 0x18000f2 Int BE Pri
90147!#3 N5647 P3571 DWST_BINIT 14 0x18000f3 Int BE Pri
90148!#3 N5648 P3572 MEMBAR
90149!#3 N5649 P3573 BST 15 0x41000084 FP BE Pri
90150!#3 N5650 P3573 BST 16 0x41000085 FP BE Pri
90151!#A N5649 N5650
90152!#3 N5651 P3573 BST 17 0x41000086 FP BE Pri
90153!#3 N5652 P3574 MEMBAR
90154!#3 N5653 P3575 LD 2 -1 Int BE Pri
90155!#3 N5654 P3575 CAS 2 -1 N5653 0x18000f4 Int BE Pri
90156!#3 N5655 P3576 ST 1 0x18000f5 Int BE Pri
90157!#3 N5656 P3577 MEMBAR
90158!#3 N5657 P3578 BST 9 0x41000087 FP BE Pri
90159!#3 N5658 P3578 BST 10 0x41000088 FP BE Pri
90160!#A N5657 N5658
90161!#3 N5659 P3578 BST 11 0x41000089 FP BE Pri
90162!#3 N5660 P3579 MEMBAR
90163!#3 N5661 P3580 SWAP 13 0xffffffff 0x18000f6 Int BE Pri
90164!#3 N5662 P3581 SWAP 8 0xffffffff 0x18000f7 Int BE Pri
90165!#3 N5663 P3582 DWST 9 0x18000f8 Int BE Pri
90166!#3 N5664 P3582 DWST 10 0x18000f9 Int BE Pri
90167!#A N5663 N5664
90168!#3 N5665 P3583 ST_BINIT 7 0x18000fa Int BE Pri
90169!#3 N5666 P3584 MEMBAR
90170!#3 N5667 P3585 BST 12 0x4100008a FP BE Pri
90171!#3 N5668 P3585 BST 13 0x4100008b FP BE Pri
90172!#A N5667 N5668
90173!#3 N5669 P3585 BST 14 0x4100008c FP BE Pri
90174!#3 N5670 P3586 MEMBAR
90175!#3 N5671 P3587 BLD 6 -1 FP BE Pri
90176!#3 N5672 P3587 BLD 7 -1 FP BE Pri
90177!#A N5671 N5672
90178!#3 N5673 P3587 BLD 8 -1 FP BE Pri
90179!#3 N5674 P3588 MEMBAR
90180!#3 N5675 P3589 DWST 6 0x18000fb Int BE Pri
90181!#3 N5676 P3589 DWST 7 0x18000fc Int BE Pri
90182!#A N5675 N5676
90183!#3 N5677 P3590 DWST 18 0x18000fd Int BE Pri
90184!#3 N5678 P3590 DWST 19 0x18000fe Int BE Pri
90185!#A N5677 N5678
90186!#3 N5679 P3591 PREFETCH 4 Int BE Pri
90187!#3 N5680 P3592 DWST_BINIT 6 0x18000ff Int LE Pri
90188!#3 N5681 P3592 DWST_BINIT 7 0x1800100 Int LE Pri
90189!#A N5680 N5681
90190!#3 N5682 P3593 MEMBAR
90191!#3 N5683 P3594 LD 13 -1 Int BE Pri
90192!#3 N5684 P3595 MEMBAR
90193!#3 N5685 P3596 BSTC 21 0x4100008d FP BE Pri
90194!#3 N5686 P3596 BSTC 22 0x4100008e FP BE Pri
90195!#A N5685 N5686
90196!#3 N5687 P3596 BSTC 23 0x4100008f FP BE Pri
90197!#3 N5688 P3597 MEMBAR
90198!#3 N5689 P3598 ST 23 0x41000090 FP BE Pri
90199!#3 N5690 P3599 MEMBAR
90200!#3 N5691 P3600 BSTC 6 0x41000091 FP BE Pri
90201!#3 N5692 P3600 BSTC 7 0x41000092 FP BE Pri
90202!#A N5691 N5692
90203!#3 N5693 P3600 BSTC 8 0x41000093 FP BE Pri
90204!#3 N5694 P3601 MEMBAR
90205!#3 N5695 P3602 BLD 6 -1 FP BE Pri
90206!#3 N5696 P3602 BLD 7 -1 FP BE Pri
90207!#A N5695 N5696
90208!#3 N5697 P3602 BLD 8 -1 FP BE Pri
90209!#3 N5698 P3603 MEMBAR
90210!#3 N5699 P3604 BLD 12 -1 FP BE Pri
90211!#3 N5700 P3604 BLD 13 -1 FP BE Pri
90212!#A N5699 N5700
90213!#3 N5701 P3604 BLD 14 -1 FP BE Pri
90214!#3 N5702 P3605 MEMBAR
90215!#3 N5703 P3606 LD 18 -1 Int BE Pri
90216!#3 N5704 P3607 DWST_BINIT 17 0x1800101 Int BE Pri
90217!#3 N5705 P3608 MEMBAR
90218!#3 N5706 P3609 REPLACEMENT 17 Int BE Pri
90219!#3 N5707 P3610 DWLD 21 -1 Int BE Pri
90220!#3 N5708 P3610 DWLD 22 -1 Int BE Pri
90221!#A N5707 N5708
90222!#3 N5709 P3610 CASX 21 -1 N5707 0x1800102 Int BE Pri
90223!#3 N5710 P3610 CASX 22 -1 N5708 0x1800103 Int BE Pri
90224!#A N5709 N5710
90225!#3 N5711 P3611 PREFETCH 20 Int BE Pri
90226!#3 N5712 P3612 LD 8 -1 Int BE Pri
90227!#3 N5713 P3612 CAS 8 -1 N5712 0x1800104 Int BE Pri
90228!#3 N5714 P3613 MEMBAR
90229!#3 N5715 P3614 BST 18 0x41000094 FP BE Pri
90230!#3 N5716 P3614 BST 19 0x41000095 FP BE Pri
90231!#A N5715 N5716
90232!#3 N5717 P3614 BST 20 0x41000096 FP BE Pri
90233!#3 N5718 P3615 MEMBAR
90234!#3 N5719 P3616 PREFETCH 10 Int BE Pri
90235!#3 N5720 P3617 MEMBAR
90236!#3 N5721 P3618 BSTC 12 0x41000097 FP BE Pri
90237!#3 N5722 P3618 BSTC 13 0x41000098 FP BE Pri
90238!#A N5721 N5722
90239!#3 N5723 P3618 BSTC 14 0x41000099 FP BE Pri
90240!#3 N5724 P3619 MEMBAR
90241!#3 N5725 P3620 DWLD 0 -1 Int BE Pri
90242!#3 N5726 P3620 DWLD 1 -1 Int BE Pri
90243!#A N5725 N5726
90244!#3 N5727 P3621 DWST 17 0x1800105 Int BE Pri
90245!#3 N5728 P3622 DWLD 12 -1 FP BE Pri
90246!#3 N5729 P3622 DWLD 13 -1 FP BE Pri
90247!#A N5728 N5729
90248!#3 N5730 P3623 LD 0 -1 Int BE Pri
90249!#3 N5731 P3624 LD 3 -1 Int BE Pri
90250!#3 N5732 P3624 CAS 3 -1 N5731 0x1800106 Int BE Pri
90251!#3 N5733 P3625 MEMBAR
90252!#3 N5734 P3626 BSTC 3 0x4100009a FP BE Pri
90253!#3 N5735 P3626 BSTC 4 0x4100009b FP BE Pri
90254!#A N5734 N5735
90255!#3 N5736 P3626 BSTC 5 0x4100009c FP BE Pri
90256!#3 N5737 P3627 MEMBAR
90257!#3 N5738 P3628 LDD 2 -1 Int BE Pri
90258!#3 N5739 P3629 MEMBAR
90259!#3 N5740 P3630 BLD 3 -1 FP BE Pri
90260!#3 N5741 P3630 BLD 4 -1 FP BE Pri
90261!#A N5740 N5741
90262!#3 N5742 P3630 BLD 5 -1 FP BE Pri
90263!#3 N5743 P3631 MEMBAR
90264!#3 N5744 P3632 PREFETCH 20 Int BE Pri
90265!#3 N5745 P3633 DWLD 21 -1 Int BE Pri
90266!#3 N5746 P3633 DWLD 22 -1 Int BE Pri
90267!#A N5745 N5746
90268!#3 N5747 P3634 DWLD 0 -1 Int BE Pri
90269!#3 N5748 P3634 DWLD 1 -1 Int BE Pri
90270!#A N5747 N5748
90271!#3 N5749 P3635 DWLD 6 -1 Int BE Pri
90272!#3 N5750 P3635 DWLD 7 -1 Int BE Pri
90273!#A N5749 N5750
90274!#3 N5751 P3635 CASX 6 -1 N5749 0x1800107 Int BE Pri
90275!#3 N5752 P3635 CASX 7 -1 N5750 0x1800108 Int BE Pri
90276!#A N5751 N5752
90277!#3 N5753 P3636 PREFETCH 8 Int BE Pri
90278!#3 N5754 P3637 DWLD 6 -1 Int LE Pri
90279!#3 N5755 P3637 DWLD 7 -1 Int LE Pri
90280!#A N5754 N5755
90281!#3 N5756 P3637 CASX 6 -1 N5754 0x1800109 Int LE Pri
90282!#3 N5757 P3637 CASX 7 -1 N5755 0x180010a Int LE Pri
90283!#A N5756 N5757
90284!#3 N5758 P3638 MEMBAR
90285!#3 N5759 P3639 BLD 15 -1 FP BE Pri
90286!#3 N5760 P3639 BLD 16 -1 FP BE Pri
90287!#A N5759 N5760
90288!#3 N5761 P3639 BLD 17 -1 FP BE Pri
90289!#3 N5762 P3640 MEMBAR
90290!#3 N5763 P3641 SWAP 13 0xffffffff 0x180010b Int BE Pri
90291!#3 N5764 P3642 DWLD 5 -1,0x0 Int BE Pri
90292!#3 N5765 P3642 CASX 5 -1,0x0 N5764 0x180010c Int BE Pri
90293!#3 N5766 P3643 LD 22 -1 Int BE Pri
90294!#3 N5767 P3643 CAS 22 -1 N5766 0x180010d Int BE Pri
90295!#3 N5768 P3644 PREFETCH 1 Int BE Pri
90296!#3 N5769 P3645 DWLD 5 -1,0x0 Int BE Pri
90297!#3 N5770 P3645 CASX 5 -1,0x0 N5769 0x180010e Int BE Pri
90298!#3 N5771 P3646 ST 9 0x180010f Int BE Pri
90299!#3 N5772 P3647 MEMBAR
90300!#3 N5773 P3648 BLD 3 -1 FP BE Pri
90301!#3 N5774 P3648 BLD 4 -1 FP BE Pri
90302!#A N5773 N5774
90303!#3 N5775 P3648 BLD 5 -1 FP BE Pri
90304!#3 N5776 P3649 MEMBAR
90305!#3 N5777 P3650 LDD 23 -1 Int BE Pri
90306!#3 N5778 P3651 ST 19 0x1800110 Int BE Pri
90307!#3 N5779 P3652 LD 12 -1 Int BE Pri
90308!#3 N5780 P3653 LD 7 -1 Int BE Pri
90309!#3 N5781 P3653 CAS 7 -1 N5780 0x1800111 Int BE Pri
90310!#3 N5782 P3654 DWLD 6 -1 Int BE Pri
90311!#3 N5783 P3654 DWLD 7 -1 Int BE Pri
90312!#A N5782 N5783
90313!#3 N5784 P3654 CASX 6 -1 N5782 0x1800112 Int BE Pri
90314!#3 N5785 P3654 CASX 7 -1 N5783 0x1800113 Int BE Pri
90315!#A N5784 N5785
90316!#3 N5786 P3655 SWAP 12 0xffffffff 0x1800114 Int BE Pri
90317!#3 N5787 P3656 MEMBAR
90318!#3 N5788 P3657 BST 3 0x4100009d FP BE Pri
90319!#3 N5789 P3657 BST 4 0x4100009e FP BE Pri
90320!#A N5788 N5789
90321!#3 N5790 P3657 BST 5 0x4100009f FP BE Pri
90322!#3 N5791 P3658 MEMBAR
90323!#3 N5792 P3659 DWLD 18 -1 Int LE Pri
90324!#3 N5793 P3659 DWLD 19 -1 Int LE Pri
90325!#A N5792 N5793
90326!#3 N5794 P3660 ST 1 0x1800115 Int BE Pri
90327!#3 N5795 P3661 ST_BINIT 16 0x1800116 Int BE Pri
90328!#3 N5796 P3662 MEMBAR
90329!#3 N5797 P3663 SWAP 16 0xffffffff 0x1800117 Int BE Pri
90330!#3 N5798 P3664 MEMBAR
90331!#3 N5799 P3665 BLD 3 -1 FP BE Pri
90332!#3 N5800 P3665 BLD 4 -1 FP BE Pri
90333!#A N5799 N5800
90334!#3 N5801 P3665 BLD 5 -1 FP BE Pri
90335!#3 N5802 P3666 MEMBAR
90336!#3 N5803 P3667 BLD 15 -1 FP BE Pri
90337!#3 N5804 P3667 BLD 16 -1 FP BE Pri
90338!#A N5803 N5804
90339!#3 N5805 P3667 BLD 17 -1 FP BE Pri
90340!#3 N5806 P3668 MEMBAR
90341!#3 N5807 P3669 ST 15 0x1800118 Int BE Pri
90342!#3 N5808 P3670 MEMBAR
90343!#3 N5809 P3671 BLD 3 -1 FP BE Pri
90344!#3 N5810 P3671 BLD 4 -1 FP BE Pri
90345!#A N5809 N5810
90346!#3 N5811 P3671 BLD 5 -1 FP BE Pri
90347!#3 N5812 P3672 MEMBAR
90348!#3 N5813 P3673 ST 20 0x1800119 Int BE Pri
90349!#3 N5814 P3674 MEMBAR
90350!#3 N5815 P3675 BLD 9 -1 FP BE Pri
90351!#3 N5816 P3675 BLD 10 -1 FP BE Pri
90352!#A N5815 N5816
90353!#3 N5817 P3675 BLD 11 -1 FP BE Pri
90354!#3 N5818 P3676 MEMBAR
90355!#3 N5819 P3677 ST 8 0x180011a Int BE Pri
90356!#3 N5820 P3678 LD 11 -1 Int BE Pri
90357!#3 N5821 P3679 ST 11 0x180011b Int BE Pri
90358!#3 N5822 P3680 ST 17 0x180011c Int BE Pri
90359!#3 N5823 P3681 DWLD 15 -1 Int BE Pri
90360!#3 N5824 P3681 DWLD 16 -1 Int BE Pri
90361!#A N5823 N5824
90362!#3 N5825 P3681 CASX 15 -1 N5823 0x180011d Int BE Pri
90363!#3 N5826 P3681 CASX 16 -1 N5824 0x180011e Int BE Pri
90364!#A N5825 N5826
90365!#3 N5827 P3682 DWST_BINIT 23 0x180011f Int BE Pri
90366!#3 N5828 P3683 MEMBAR
90367!#3 N5829 P3684 BSTC 18 0x410000a0 FP BE Pri
90368!#3 N5830 P3684 BSTC 19 0x410000a1 FP BE Pri
90369!#A N5829 N5830
90370!#3 N5831 P3684 BSTC 20 0x410000a2 FP BE Pri
90371!#3 N5832 P3685 MEMBAR
90372!#3 N5833 P3686 DWLD 0 -1 Int BE Pri
90373!#3 N5834 P3686 DWLD 1 -1 Int BE Pri
90374!#A N5833 N5834
90375!#3 N5835 P3686 CASX 0 -1 N5833 0x1800120 Int BE Pri
90376!#3 N5836 P3686 CASX 1 -1 N5834 0x1800121 Int BE Pri
90377!#A N5835 N5836
90378!#3 N5837 P3687 PREFETCH 23 Int BE Pri
90379!#3 N5838 P3688 LD 11 -1 Int BE Pri
90380!#3 N5839 P3689 MEMBAR
90381!#3 N5840 P3690 BST 6 0x410000a3 FP BE Pri
90382!#3 N5841 P3690 BST 7 0x410000a4 FP BE Pri
90383!#A N5840 N5841
90384!#3 N5842 P3690 BST 8 0x410000a5 FP BE Pri
90385!#3 N5843 P3691 MEMBAR
90386!#3 N5844 P3692 SWAP 14 0xffffffff 0x1800122 Int BE Pri
90387!#3 N5845 P3693 DWLD 9 -1 Int BE Pri
90388!#3 N5846 P3693 DWLD 10 -1 Int BE Pri
90389!#A N5845 N5846
90390!#3 N5847 P3693 CASX 9 -1 N5845 0x1800123 Int BE Pri
90391!#3 N5848 P3693 CASX 10 -1 N5846 0x1800124 Int BE Pri
90392!#A N5847 N5848
90393!#3 N5849 P3694 MEMBAR
90394!#3 N5850 P3695 BSTC 0 0x410000a6 FP BE Pri
90395!#3 N5851 P3695 BSTC 1 0x410000a7 FP BE Pri
90396!#A N5850 N5851
90397!#3 N5852 P3695 BSTC 2 0x410000a8 FP BE Pri
90398!#3 N5853 P3696 MEMBAR
90399!#3 N5854 P3697 LD 11 -1 Int BE Pri
90400!#3 N5855 P3698 LD 11 -1 Int BE Pri
90401!#3 N5856 P3699 LD 19 -1 FP BE Pri
90402!#3 N5857 P3700 DWLD 0 -1 Int BE Pri
90403!#3 N5858 P3700 DWLD 1 -1 Int BE Pri
90404!#A N5857 N5858
90405!#3 N5859 P3701 ST 12 0x1800125 Int BE Pri
90406!#3 N5860 P3702 DWST_BINIT 0 0x1800126 Int BE Pri
90407!#3 N5861 P3702 DWST_BINIT 1 0x1800127 Int BE Pri
90408!#A N5860 N5861
90409!#3 N5862 P3703 MEMBAR
90410!#3 N5863 P3704 BLD 0 -1 FP BE Pri
90411!#3 N5864 P3704 BLD 1 -1 FP BE Pri
90412!#A N5863 N5864
90413!#3 N5865 P3704 BLD 2 -1 FP BE Pri
90414!#3 N5866 P3705 MEMBAR
90415!#3 N5867 P3706 DWST_BINIT 6 0x1800128 Int BE Pri
90416!#3 N5868 P3706 DWST_BINIT 7 0x1800129 Int BE Pri
90417!#A N5867 N5868
90418!#3 N5869 P3707 MEMBAR
90419!#3 N5870 P3708 DWLD 9 -1 Int BE Pri
90420!#3 N5871 P3708 DWLD 10 -1 Int BE Pri
90421!#A N5870 N5871
90422!#3 N5872 P3708 CASX 9 -1 N5870 0x180012a Int BE Pri
90423!#3 N5873 P3708 CASX 10 -1 N5871 0x180012b Int BE Pri
90424!#A N5872 N5873
90425!#3 N5874 P3709 LD 22 -1 Int BE Pri
90426!#3 N5875 P3710 MEMBAR
90427!#3 N5876 P3711 BSTC 12 0x410000a9 FP BE Pri
90428!#3 N5877 P3711 BSTC 13 0x410000aa FP BE Pri
90429!#A N5876 N5877
90430!#3 N5878 P3711 BSTC 14 0x410000ab FP BE Pri
90431!#3 N5879 P3712 MEMBAR
90432!#3 N5880 P3713 BLD 6 -1 FP BE Pri
90433!#3 N5881 P3713 BLD 7 -1 FP BE Pri
90434!#A N5880 N5881
90435!#3 N5882 P3713 BLD 8 -1 FP BE Pri
90436!#3 N5883 P3714 MEMBAR
90437!#3 N5884 P3715 ST_BINIT 13 0x180012c Int BE Pri
90438!#3 N5885 P3716 MEMBAR
90439!#3 N5886 P3717 PREFETCH 9 Int BE Pri
90440!#3 N5887 P3718 LD 13 -1 Int BE Pri
90441!#3 N5888 P3718 CAS 13 -1 N5887 0x180012d Int BE Pri
90442!#3 N5889 P3719 DWST_BINIT 14 0x180012e Int BE Pri
90443!#3 N5890 P3720 MEMBAR
90444!#3 N5891 P3721 REPLACEMENT 21 Int BE Pri
90445!#3 N5892 P3722 ST_BINIT 13 0x180012f Int BE Pri
90446!#3 N5893 P3723 MEMBAR
90447!#3 N5894 P3724 LD 3 -1 Int BE Pri
90448!#3 N5895 P3725 LD 23 -1 Int BE Pri
90449!#3 N5896 P3725 CAS 23 -1 N5895 0x1800130 Int BE Pri
90450!#3 N5897 P3726 MEMBAR
90451!#3 N5898 P3727 BSTC 18 0x410000ac FP BE Pri
90452!#3 N5899 P3727 BSTC 19 0x410000ad FP BE Pri
90453!#A N5898 N5899
90454!#3 N5900 P3727 BSTC 20 0x410000ae FP BE Pri
90455!#3 N5901 P3728 MEMBAR
90456!#3 N5902 P3729 LD 19 -1 Int BE Pri
90457!#3 N5903 P3730 PREFETCH 15 Int BE Pri
90458!#3 N5904 P3731 DWLD 12 -1 Int BE Pri
90459!#3 N5905 P3731 DWLD 13 -1 Int BE Pri
90460!#A N5904 N5905
90461!#3 N5906 P3731 CASX 12 -1 N5904 0x1800131 Int BE Pri
90462!#3 N5907 P3731 CASX 13 -1 N5905 0x1800132 Int BE Pri
90463!#A N5906 N5907
90464!#3 N5908 P3732 DWST_BINIT 15 0x1800133 Int BE Pri
90465!#3 N5909 P3732 DWST_BINIT 16 0x1800134 Int BE Pri
90466!#A N5908 N5909
90467!#3 N5910 P3733 MEMBAR
90468!#3 N5911 P3734 SWAP 15 0xffffffff 0x1800135 Int BE Pri
90469!#3 N5912 P3735 DWLD 6 -1 Int BE Pri
90470!#3 N5913 P3735 DWLD 7 -1 Int BE Pri
90471!#A N5912 N5913
90472!#3 N5914 P3735 CASX 6 -1 N5912 0x1800136 Int BE Pri
90473!#3 N5915 P3735 CASX 7 -1 N5913 0x1800137 Int BE Pri
90474!#A N5914 N5915
90475!#3 N5916 P3736 LD 16 -1 Int BE Pri
90476!#3 N5917 P3737 SWAP 3 0xffffffff 0x1800138 Int BE Pri
90477!#3 N5918 P3738 DWST_BINIT 11 0x1800139 Int BE Pri
90478!#3 N5919 P3739 MEMBAR
90479!#3 N5920 P3740 BLD 9 -1 FP BE Pri
90480!#3 N5921 P3740 BLD 10 -1 FP BE Pri
90481!#A N5920 N5921
90482!#3 N5922 P3740 BLD 11 -1 FP BE Pri
90483!#3 N5923 P3741 MEMBAR
90484!#3 N5924 P3742 BLD 0 -1 FP BE Pri
90485!#3 N5925 P3742 BLD 1 -1 FP BE Pri
90486!#A N5924 N5925
90487!#3 N5926 P3742 BLD 2 -1 FP BE Pri
90488!#3 N5927 P3743 MEMBAR
90489!#3 N5928 P3744 LDD 18 -1 Int BE Pri
90490!#3 N5929 P3744 LDD 19 -1 Int BE Pri
90491!#A N5928 N5929
90492!#3 N5930 P3745 DWST_BINIT 14 0x180013a Int BE Pri
90493!#3 N5931 P3746 MEMBAR
90494!#3 N5932 P3747 BSTC 12 0x410000af FP BE Pri
90495!#3 N5933 P3747 BSTC 13 0x410000b0 FP BE Pri
90496!#A N5932 N5933
90497!#3 N5934 P3747 BSTC 14 0x410000b1 FP BE Pri
90498!#3 N5935 P3748 MEMBAR
90499!#3 N5936 P3749 DWLD 20 -1 Int BE Pri
90500!#3 N5937 P3750 ST_BINIT 7 0x180013b Int BE Pri
90501!#3 N5938 P3751 MEMBAR
90502!#3 N5939 P3752 BLD 12 -1 FP BE Pri
90503!#3 N5940 P3752 BLD 13 -1 FP BE Pri
90504!#A N5939 N5940
90505!#3 N5941 P3752 BLD 14 -1 FP BE Pri
90506!#3 N5942 P3753 MEMBAR
90507!#3 N5943 P3754 LD 7 -1 Int BE Pri
90508!#3 N5944 P3755 PREFETCH 13 Int BE Pri
90509!#3 N5945 P3756 LDD 17 -1 Int BE Pri
90510!#3 N5946 P3757 REPLACEMENT 13 Int BE Pri
90511!#3 N5947 P3758 REPLACEMENT 5 Int BE Pri
90512!#3 N5948 P3759 MEMBAR
90513!#3 N5949 P3760 BLD 6 -1 FP BE Pri
90514!#3 N5950 P3760 BLD 7 -1 FP BE Pri
90515!#A N5949 N5950
90516!#3 N5951 P3760 BLD 8 -1 FP BE Pri
90517!#3 N5952 P3761 MEMBAR
90518!#3 N5953 P3762 DWST 14 0x180013c Int BE Pri
90519!#3 N5954 P3763 MEMBAR
90520!#3 N5955 P3764 BLD 15 -1 FP BE Pri
90521!#3 N5956 P3764 BLD 16 -1 FP BE Pri
90522!#A N5955 N5956
90523!#3 N5957 P3764 BLD 17 -1 FP BE Pri
90524!#3 N5958 P3765 MEMBAR
90525!#3 N5959 P3766 REPLACEMENT 21 Int BE Pri
90526!#3 N5960 P3767 DWST 5 0x180013d Int BE Pri
90527!#3 N5961 P3768 SWAP 1 0xffffffff 0x180013e Int BE Pri
90528!#3 N5962 P3769 MEMBAR
90529!#3 N5963 P3770 BSTC 18 0x410000b2 FP BE Pri
90530!#3 N5964 P3770 BSTC 19 0x410000b3 FP BE Pri
90531!#A N5963 N5964
90532!#3 N5965 P3770 BSTC 20 0x410000b4 FP BE Pri
90533!#3 N5966 P3771 MEMBAR
90534!#3 N5967 P3772 BSTC 15 0x410000b5 FP BE Pri
90535!#3 N5968 P3772 BSTC 16 0x410000b6 FP BE Pri
90536!#A N5967 N5968
90537!#3 N5969 P3772 BSTC 17 0x410000b7 FP BE Pri
90538!#3 N5970 P3773 MEMBAR
90539!#3 N5971 P3774 ST_BINIT 11 0x180013f Int BE Pri
90540!#3 N5972 P3775 MEMBAR
90541!#3 N5973 P3776 ST_BINIT 7 0x1800140 Int BE Pri
90542!#3 N5974 P3777 MEMBAR
90543!#3 N5975 P3778 BLD 9 -1 FP BE Pri
90544!#3 N5976 P3778 BLD 10 -1 FP BE Pri
90545!#A N5975 N5976
90546!#3 N5977 P3778 BLD 11 -1 FP BE Pri
90547!#3 N5978 P3779 MEMBAR
90548!#3 N5979 P3780 LDD 6 -1 Int BE Pri
90549!#3 N5980 P3780 LDD 7 -1 Int BE Pri
90550!#A N5979 N5980
90551!#3 N5981 P3781 DWST 5 0x1800141 Int BE Pri
90552!#3 N5982 P3782 MEMBAR
90553!#3 N5983 P3783 BLD 15 -1 FP BE Pri
90554!#3 N5984 P3783 BLD 16 -1 FP BE Pri
90555!#A N5983 N5984
90556!#3 N5985 P3783 BLD 17 -1 FP BE Pri
90557!#3 N5986 P3784 MEMBAR
90558!#3 N5987 P3785 ST_BINIT 4 0x1800142 Int LE Pri
90559!#3 N5988 P3786 MEMBAR
90560!#3 N5989 P3787 PREFETCH 13 Int BE Pri
90561!#3 N5990 P3788 SWAP 17 0xffffffff 0x1800143 Int BE Pri
90562!#3 N5991 P3789 DWLD 6 -1 Int BE Pri
90563!#3 N5992 P3789 DWLD 7 -1 Int BE Pri
90564!#A N5991 N5992
90565!#3 N5993 P3790 LDD 0 -1 Int BE Pri
90566!#3 N5994 P3790 LDD 1 -1 Int BE Pri
90567!#A N5993 N5994
90568!#3 N5995 P3791 LD 12 -1 Int BE Pri
90569!#3 N5996 P3792 DWLD 3 -1 Int BE Pri
90570!#3 N5997 P3792 DWLD 4 -1 Int BE Pri
90571!#A N5996 N5997
90572!#3 N5998 P3793 DWLD 3 -1 Int BE Pri
90573!#3 N5999 P3793 DWLD 4 -1 Int BE Pri
90574!#A N5998 N5999
90575!#3 N6000 P3794 LD 17 -1 Int BE Pri
90576!#3 N6001 P3794 CAS 17 -1 N6000 0x1800144 Int BE Pri
90577!#3 N6002 P3795 DWLD 0 -1 Int BE Pri
90578!#3 N6003 P3795 DWLD 1 -1 Int BE Pri
90579!#A N6002 N6003
90580!#3 N6004 P3795 CASX 0 -1 N6002 0x1800145 Int BE Pri
90581!#3 N6005 P3795 CASX 1 -1 N6003 0x1800146 Int BE Pri
90582!#A N6004 N6005
90583!#3 N6006 P3796 MEMBAR
90584!#3 N6007 P3797 BSTC 18 0x410000b8 FP BE Pri
90585!#3 N6008 P3797 BSTC 19 0x410000b9 FP BE Pri
90586!#A N6007 N6008
90587!#3 N6009 P3797 BSTC 20 0x410000ba FP BE Pri
90588!#3 N6010 P3798 MEMBAR
90589!#3 N6011 P3799 BST 3 0x410000bb FP BE Pri
90590!#3 N6012 P3799 BST 4 0x410000bc FP BE Pri
90591!#A N6011 N6012
90592!#3 N6013 P3799 BST 5 0x410000bd FP BE Pri
90593!#3 N6014 P3800 MEMBAR
90594!#3 N6015 P3801 ST_BINIT 17 0x1800147 Int BE Pri
90595!#3 N6016 P3802 MEMBAR
90596!#3 N6017 P3803 DWST_BINIT 8 0x1800148 Int BE Pri
90597!#3 N6018 P3804 MEMBAR
90598!#3 N6019 P3805 ST_BINIT 6 0x1800149 Int BE Pri
90599!#3 N6020 P3806 MEMBAR
90600!#3 N6021 P3807 LDD 0 -1 Int BE Pri
90601!#3 N6022 P3807 LDD 1 -1 Int BE Pri
90602!#A N6021 N6022
90603!#3 N6023 P3808 DWST_BINIT 18 0x180014a Int BE Pri
90604!#3 N6024 P3808 DWST_BINIT 19 0x180014b Int BE Pri
90605!#A N6023 N6024
90606!#3 N6025 P3809 MEMBAR
90607!#3 N6026 P3810 BSTC 15 0x410000be FP BE Pri
90608!#3 N6027 P3810 BSTC 16 0x410000bf FP BE Pri
90609!#A N6026 N6027
90610!#3 N6028 P3810 BSTC 17 0x410000c0 FP BE Pri
90611!#3 N6029 P3811 MEMBAR
90612!#3 N6030 P3812 ST 20 0x180014c Int BE Pri
90613!#3 N6031 P3813 MEMBAR
90614!#3 N6032 P3814 BSTC 18 0x410000c1 FP BE Pri
90615!#3 N6033 P3814 BSTC 19 0x410000c2 FP BE Pri
90616!#A N6032 N6033
90617!#3 N6034 P3814 BSTC 20 0x410000c3 FP BE Pri
90618!#3 N6035 P3815 MEMBAR
90619!#3 N6036 P3816 LD 14 -1 Int BE Pri
90620!#3 N6037 P3817 LD 5 -1 Int BE Pri
90621!#3 N6038 P3817 CAS 5 -1 N6037 0x180014d Int BE Pri
90622!#3 N6039 P3818 LD 6 -1 Int BE Pri
90623!#3 N6040 P3818 CAS 6 -1 N6039 0x180014e Int BE Pri
90624!#3 N6041 P3819 MEMBAR
90625!#3 N6042 P3820 BSTC 18 0x410000c4 FP BE Pri
90626!#3 N6043 P3820 BSTC 19 0x410000c5 FP BE Pri
90627!#A N6042 N6043
90628!#3 N6044 P3820 BSTC 20 0x410000c6 FP BE Pri
90629!#3 N6045 P3821 MEMBAR
90630!#3 N6046 P3822 DWLD 15 -1 Int BE Pri
90631!#3 N6047 P3822 DWLD 16 -1 Int BE Pri
90632!#A N6046 N6047
90633!#3 N6048 P3823 LDD 0 -1 Int BE Pri
90634!#3 N6049 P3823 LDD 1 -1 Int BE Pri
90635!#A N6048 N6049
90636!#3 N6050 P3824 MEMBAR
90637!#3 N6051 P3825 BST 9 0x410000c7 FP BE Pri
90638!#3 N6052 P3825 BST 10 0x410000c8 FP BE Pri
90639!#A N6051 N6052
90640!#3 N6053 P3825 BST 11 0x410000c9 FP BE Pri
90641!#3 N6054 P3826 MEMBAR
90642!#3 N6055 P3827 PREFETCH 2 Int BE Pri
90643!#3 N6056 P3828 DWST_BINIT 0 0x180014f Int BE Pri
90644!#3 N6057 P3828 DWST_BINIT 1 0x1800150 Int BE Pri
90645!#A N6056 N6057
90646!#3 N6058 P3829 MEMBAR
90647!#3 N6059 P3830 BST 21 0x410000ca FP BE Pri
90648!#3 N6060 P3830 BST 22 0x410000cb FP BE Pri
90649!#A N6059 N6060
90650!#3 N6061 P3830 BST 23 0x410000cc FP BE Pri
90651!#3 N6062 P3831 MEMBAR
90652!#3 N6063 P3832 DWST_BINIT 6 0x1800151 Int BE Pri
90653!#3 N6064 P3832 DWST_BINIT 7 0x1800152 Int BE Pri
90654!#A N6063 N6064
90655!#3 N6065 P3833 MEMBAR
90656!#3 N6066 P3834 DWLD 3 -1 Int BE Pri
90657!#3 N6067 P3834 DWLD 4 -1 Int BE Pri
90658!#A N6066 N6067
90659!#3 N6068 P3834 CASX 3 -1 N6066 0x1800153 Int BE Pri
90660!#3 N6069 P3834 CASX 4 -1 N6067 0x1800154 Int BE Pri
90661!#A N6068 N6069
90662!#3 N6070 P3835 ST_BINIT 3 0x1800155 Int BE Pri
90663!#3 N6071 P3836 MEMBAR
90664!#3 N6072 P3837 BST 21 0x410000cd FP BE Pri
90665!#3 N6073 P3837 BST 22 0x410000ce FP BE Pri
90666!#A N6072 N6073
90667!#3 N6074 P3837 BST 23 0x410000cf FP BE Pri
90668!#3 N6075 P3838 MEMBAR
90669!#3 N6076 P3839 DWST 3 0x1800156 Int BE Pri
90670!#3 N6077 P3839 DWST 4 0x1800157 Int BE Pri
90671!#A N6076 N6077
90672!#3 N6078 P3840 LDD 6 -1 Int BE Pri
90673!#3 N6079 P3840 LDD 7 -1 Int BE Pri
90674!#A N6078 N6079
90675!#3 N6080 P3841 DWST 11 0x1800158 Int BE Pri
90676!#3 N6081 P3842 MEMBAR
90677!#3 N6082 P3843 BSTC 21 0x410000d0 FP BE Pri
90678!#3 N6083 P3843 BSTC 22 0x410000d1 FP BE Pri
90679!#A N6082 N6083
90680!#3 N6084 P3843 BSTC 23 0x410000d2 FP BE Pri
90681!#3 N6085 P3844 MEMBAR
90682!#3 N6086 P3845 BLD 9 -1 FP BE Pri
90683!#3 N6087 P3845 BLD 10 -1 FP BE Pri
90684!#A N6086 N6087
90685!#3 N6088 P3845 BLD 11 -1 FP BE Pri
90686!#3 N6089 P3846 MEMBAR
90687!#3 N6090 P3847 BLD 12 -1 FP BE Pri
90688!#3 N6091 P3847 BLD 13 -1 FP BE Pri
90689!#A N6090 N6091
90690!#3 N6092 P3847 BLD 14 -1 FP BE Pri
90691!#3 N6093 P3848 MEMBAR
90692!#3 N6094 P3849 ST_BINIT 8 0x1800159 Int BE Pri
90693!#3 N6095 P3850 MEMBAR
90694!#3 N6096 P3851 DWST 18 0x180015a Int BE Pri
90695!#3 N6097 P3851 DWST 19 0x180015b Int BE Pri
90696!#A N6096 N6097
90697!#3 N6098 P3852 DWLD 0 -1 Int BE Pri
90698!#3 N6099 P3852 DWLD 1 -1 Int BE Pri
90699!#A N6098 N6099
90700!#3 N6100 P3852 CASX 0 -1 N6098 0x180015c Int BE Pri
90701!#3 N6101 P3852 CASX 1 -1 N6099 0x180015d Int BE Pri
90702!#A N6100 N6101
90703!#3 N6102 P3853 DWLD 17 -1,0x0 Int BE Pri
90704!#3 N6103 P3853 CASX 17 -1,0x0 N6102 0x180015e Int BE Pri
90705!#3 N6104 P3854 REPLACEMENT 6 Int BE Pri
90706!#3 N6105 P3855 MEMBAR
90707!#3 N6106 P3856 BSTC 9 0x410000d3 FP BE Pri
90708!#3 N6107 P3856 BSTC 10 0x410000d4 FP BE Pri
90709!#A N6106 N6107
90710!#3 N6108 P3856 BSTC 11 0x410000d5 FP BE Pri
90711!#3 N6109 P3857 MEMBAR
90712!#3 N6110 P3858 DWLD 18 -1 Int BE Pri
90713!#3 N6111 P3858 DWLD 19 -1 Int BE Pri
90714!#A N6110 N6111
90715!#3 N6112 P3859 DWST 21 0x410000d6 FP BE Pri
90716!#3 N6113 P3859 DWST 22 0x410000d7 FP BE Pri
90717!#A N6112 N6113
90718!#3 N6114 P3860 MEMBAR
90719!#3 N6115 P3861 BSTC 15 0x410000d8 FP BE Pri
90720!#3 N6116 P3861 BSTC 16 0x410000d9 FP BE Pri
90721!#A N6115 N6116
90722!#3 N6117 P3861 BSTC 17 0x410000da FP BE Pri
90723!#3 N6118 P3862 MEMBAR
90724!#3 N6119 P3863 DWLD 15 -1 Int BE Pri
90725!#3 N6120 P3863 DWLD 16 -1 Int BE Pri
90726!#A N6119 N6120
90727!#3 N6121 P3863 CASX 15 -1 N6119 0x180015f Int BE Pri
90728!#3 N6122 P3863 CASX 16 -1 N6120 0x1800160 Int BE Pri
90729!#A N6121 N6122
90730!#3 N6123 P3864 SWAP 1 0xffffffff 0x1800161 Int BE Pri
90731!#3 N6124 P3865 DWLD 18 -1 Int BE Pri
90732!#3 N6125 P3865 DWLD 19 -1 Int BE Pri
90733!#A N6124 N6125
90734!#3 N6126 P3865 CASX 18 -1 N6124 0x1800162 Int BE Pri
90735!#3 N6127 P3865 CASX 19 -1 N6125 0x1800163 Int BE Pri
90736!#A N6126 N6127
90737!#3 N6128 P3866 DWLD 18 -1 Int BE Pri
90738!#3 N6129 P3866 DWLD 19 -1 Int BE Pri
90739!#A N6128 N6129
90740!#3 N6130 P3866 CASX 18 -1 N6128 0x1800164 Int BE Pri
90741!#3 N6131 P3866 CASX 19 -1 N6129 0x1800165 Int BE Pri
90742!#A N6130 N6131
90743!#3 N6132 P3867 DWLD 12 -1 Int BE Pri
90744!#3 N6133 P3867 DWLD 13 -1 Int BE Pri
90745!#A N6132 N6133
90746!#3 N6134 P3868 MEMBAR
90747!#3 N6135 P3869 BST 12 0x410000db FP BE Pri
90748!#3 N6136 P3869 BST 13 0x410000dc FP BE Pri
90749!#A N6135 N6136
90750!#3 N6137 P3869 BST 14 0x410000dd FP BE Pri
90751!#3 N6138 P3870 MEMBAR
90752!#3 N6139 P3871 BLD 21 -1 FP BE Pri
90753!#3 N6140 P3871 BLD 22 -1 FP BE Pri
90754!#A N6139 N6140
90755!#3 N6141 P3871 BLD 23 -1 FP BE Pri
90756!#3 N6142 P3872 MEMBAR
90757!#3 N6143 P3873 LD 16 -1 Int BE Pri
90758!#3 N6144 P3874 MEMBAR
90759!#3 N6145 P3875 BSTC 12 0x410000de FP BE Pri
90760!#3 N6146 P3875 BSTC 13 0x410000df FP BE Pri
90761!#A N6145 N6146
90762!#3 N6147 P3875 BSTC 14 0x410000e0 FP BE Pri
90763!#3 N6148 P3876 MEMBAR
90764!#3 N6149 P3877 PREFETCH 22 Int BE Pri
90765!#3 N6150 P3878 MEMBAR
90766!#3 N6151 P3879 BSTC 21 0x410000e1 FP BE Pri
90767!#3 N6152 P3879 BSTC 22 0x410000e2 FP BE Pri
90768!#A N6151 N6152
90769!#3 N6153 P3879 BSTC 23 0x410000e3 FP BE Pri
90770!#3 N6154 P3880 MEMBAR
90771!#3 N6155 P3881 LDD 3 -1 Int BE Pri
90772!#3 N6156 P3881 LDD 4 -1 Int BE Pri
90773!#A N6155 N6156
90774!#3 N6157 P3882 MEMBAR
90775!#3 N6158 P3883 BLD 12 -1 FP BE Pri
90776!#3 N6159 P3883 BLD 13 -1 FP BE Pri
90777!#A N6158 N6159
90778!#3 N6160 P3883 BLD 14 -1 FP BE Pri
90779!#3 N6161 P3884 MEMBAR
90780!#3 N6162 P3885 BLD 21 -1 FP BE Pri
90781!#3 N6163 P3885 BLD 22 -1 FP BE Pri
90782!#A N6162 N6163
90783!#3 N6164 P3885 BLD 23 -1 FP BE Pri
90784!#3 N6165 P3886 MEMBAR
90785!#3 N6166 P3887 LD 0 -1 Int BE Pri
90786!#3 N6167 P3887 CAS 0 -1 N6166 0x1800166 Int BE Pri
90787!#3 N6168 P3888 DWLD 0 -1 Int BE Pri
90788!#3 N6169 P3888 DWLD 1 -1 Int BE Pri
90789!#A N6168 N6169
90790!#3 N6170 P3889 MEMBAR
90791!#3 N6171 P3890 BLD 6 -1 FP BE Pri
90792!#3 N6172 P3890 BLD 7 -1 FP BE Pri
90793!#A N6171 N6172
90794!#3 N6173 P3890 BLD 8 -1 FP BE Pri
90795!#3 N6174 P3891 MEMBAR
90796!#3 N6175 P3892 LD 20 -1 Int BE Pri
90797!#3 N6176 P3893 SWAP 15 0xffffffff 0x1800167 Int BE Pri
90798!#3 N6177 P3894 DWLD 20 -1,0x0 Int BE Pri
90799!#3 N6178 P3894 CASX 20 -1,0x0 N6177 0x1800168 Int BE Pri
90800!#3 N6179 P3895 ST 22 0x1800169 Int BE Pri
90801!#3 N6180 P3896 MEMBAR
90802!#3 N6181 P3897 BST 12 0x410000e4 FP BE Pri
90803!#3 N6182 P3897 BST 13 0x410000e5 FP BE Pri
90804!#A N6181 N6182
90805!#3 N6183 P3897 BST 14 0x410000e6 FP BE Pri
90806!#3 N6184 P3898 MEMBAR
90807!#3 N6185 P3899 LD 3 -1 Int BE Pri
90808!#3 N6186 P3900 DWLD 12 -1 Int BE Pri
90809!#3 N6187 P3900 DWLD 13 -1 Int BE Pri
90810!#A N6186 N6187
90811!#3 N6188 P3901 ST 9 0x180016a Int BE Pri
90812!#3 N6189 P3902 MEMBAR
90813!#3 N6190 P3903 BST 12 0x410000e7 FP BE Pri
90814!#3 N6191 P3903 BST 13 0x410000e8 FP BE Pri
90815!#A N6190 N6191
90816!#3 N6192 P3903 BST 14 0x410000e9 FP BE Pri
90817!#3 N6193 P3904 MEMBAR
90818!#3 N6194 P3905 SWAP 20 0xffffffff 0x180016b Int BE Pri
90819!#3 N6195 P3906 ST_BINIT 12 0x180016c Int BE Pri
90820!#3 N6196 P3907 MEMBAR
90821!#3 N6197 P3908 DWLD 0 -1 Int BE Pri
90822!#3 N6198 P3908 DWLD 1 -1 Int BE Pri
90823!#A N6197 N6198
90824!#3 N6199 P3908 CASX 0 -1 N6197 0x180016d Int BE Pri
90825!#3 N6200 P3908 CASX 1 -1 N6198 0x180016e Int BE Pri
90826!#A N6199 N6200
90827!#3 N6201 P3909 DWST_BINIT 2 0x180016f Int BE Pri
90828!#3 N6202 P3910 MEMBAR
90829!#3 N6203 P3911 ST 18 0x1800170 Int BE Pri
90830!#3 N6204 P3912 MEMBAR
90831!#3 N6205 P3913 BSTC 0 0x410000ea FP BE Pri
90832!#3 N6206 P3913 BSTC 1 0x410000eb FP BE Pri
90833!#A N6205 N6206
90834!#3 N6207 P3913 BSTC 2 0x410000ec FP BE Pri
90835!#3 N6208 P3914 MEMBAR
90836!#3 N6209 P3915 LD 13 -1 Int LE Pri
90837!#3 N6210 P3915 CAS 13 -1 N6209 0x1800171 Int LE Pri
90838!#3 N6211 P3916 SWAP 0 0xffffffff 0x1800172 Int BE Pri
90839!#3 N6212 P3917 MEMBAR
90840!#3 N6213 P3918 BLD 0 -1 FP BE Pri
90841!#3 N6214 P3918 BLD 1 -1 FP BE Pri
90842!#A N6213 N6214
90843!#3 N6215 P3918 BLD 2 -1 FP BE Pri
90844!#3 N6216 P3919 MEMBAR
90845!#3 N6217 P3920 LDD 5 -1 Int BE Pri
90846!#3 N6218 P3921 SWAP 20 0xffffffff 0x1800173 Int BE Pri
90847!#3 N6219 P3922 MEMBAR
90848!#3 N6220 P3923 BSTC 9 0x410000ed FP BE Pri
90849!#3 N6221 P3923 BSTC 10 0x410000ee FP BE Pri
90850!#A N6220 N6221
90851!#3 N6222 P3923 BSTC 11 0x410000ef FP BE Pri
90852!#3 N6223 P3924 MEMBAR
90853!#3 N6224 P3925 BSTC 21 0x410000f0 FP BE Pri
90854!#3 N6225 P3925 BSTC 22 0x410000f1 FP BE Pri
90855!#A N6224 N6225
90856!#3 N6226 P3925 BSTC 23 0x410000f2 FP BE Pri
90857!#3 N6227 P3926 MEMBAR
90858!#3 N6228 P3927 BLD 6 -1 FP BE Pri
90859!#3 N6229 P3927 BLD 7 -1 FP BE Pri
90860!#A N6228 N6229
90861!#3 N6230 P3927 BLD 8 -1 FP BE Pri
90862!#3 N6231 P3928 MEMBAR
90863!#3 N6232 P3929 REPLACEMENT 4 Int BE Pri
90864!#3 N6233 P3930 DWST_BINIT 3 0x1800174 Int BE Pri
90865!#3 N6234 P3930 DWST_BINIT 4 0x1800175 Int BE Pri
90866!#A N6233 N6234
90867!#3 N6235 P3931 MEMBAR
90868!#3 N6236 P3932 PREFETCH 23 Int BE Pri
90869!#3 N6237 P3933 DWLD 6 -1 Int BE Pri
90870!#3 N6238 P3933 DWLD 7 -1 Int BE Pri
90871!#A N6237 N6238
90872!#3 N6239 P3934 LD 3 -1 Int BE Pri
90873!#3 N6240 P3934 CAS 3 -1 N6239 0x1800176 Int BE Pri
90874!#3 N6241 P3935 LD 11 -1 Int BE Pri
90875!#3 N6242 P3936 LD 0 -1 Int LE Pri
90876!#3 N6243 P3937 ST 1 0x1800177 Int BE Pri
90877!#3 N6244 P3938 LD 17 -1 Int BE Pri
90878!#3 N6245 P3939 LD 5 -1 Int BE Pri
90879!#3 N6246 P3940 MEMBAR
90880!#3 N6247 P3941 BLD 6 -1 FP BE Pri
90881!#3 N6248 P3941 BLD 7 -1 FP BE Pri
90882!#A N6247 N6248
90883!#3 N6249 P3941 BLD 8 -1 FP BE Pri
90884!#3 N6250 P3942 MEMBAR
90885!#3 N6251 P3943 SWAP 0 0xffffffff 0x1800178 Int BE Pri
90886!#3 N6252 P3944 MEMBAR
90887!#3 N6253 P3945 BLD 21 -1 FP BE Pri
90888!#3 N6254 P3945 BLD 22 -1 FP BE Pri
90889!#A N6253 N6254
90890!#3 N6255 P3945 BLD 23 -1 FP BE Pri
90891!#3 N6256 P3946 MEMBAR
90892!#3 N6257 P3947 ST_BINIT 11 0x1800179 Int BE Pri
90893!#3 N6258 P3948 MEMBAR
90894!#3 N6259 P3949 DWST 12 0x180017a Int BE Pri
90895!#3 N6260 P3949 DWST 13 0x180017b Int BE Pri
90896!#A N6259 N6260
90897!#3 N6261 P3950 LD 17 -1 Int BE Pri
90898!#3 N6262 P3951 ST 12 0x180017c Int BE Pri
90899!#3 N6263 P3952 MEMBAR
90900!#3 N6264 P3953 BSTC 15 0x410000f3 FP BE Pri
90901!#3 N6265 P3953 BSTC 16 0x410000f4 FP BE Pri
90902!#A N6264 N6265
90903!#3 N6266 P3953 BSTC 17 0x410000f5 FP BE Pri
90904!#3 N6267 P3954 MEMBAR
90905!#3 N6268 P3955 LDD 18 -1 Int BE Pri
90906!#3 N6269 P3955 LDD 19 -1 Int BE Pri
90907!#A N6268 N6269
90908!#3 N6270 P3956 ST 18 0x180017d Int BE Pri
90909!#3 N6271 P3957 DWLD 18 -1 Int BE Pri
90910!#3 N6272 P3957 DWLD 19 -1 Int BE Pri
90911!#A N6271 N6272
90912!#3 N6273 P3958 MEMBAR
90913!#3 N6274 P3959 BLD 0 -1 FP BE Pri
90914!#3 N6275 P3959 BLD 1 -1 FP BE Pri
90915!#A N6274 N6275
90916!#3 N6276 P3959 BLD 2 -1 FP BE Pri
90917!#3 N6277 P3960 MEMBAR
90918!#3 N6278 P3961 ST_BINIT 20 0x180017e Int BE Pri
90919!#3 N6279 P3962 MEMBAR
90920!#3 N6280 P3963 LDD 23 -1 Int BE Pri
90921!#3 N6281 P3964 LDD 17 -1 Int BE Pri
90922!#3 N6282 P3965 SWAP 16 0xffffffff 0x180017f Int BE Pri
90923!#3 N6283 P3966 MEMBAR
90924!#3 N6284 P3967 BST 9 0x410000f6 FP BE Pri
90925!#3 N6285 P3967 BST 10 0x410000f7 FP BE Pri
90926!#A N6284 N6285
90927!#3 N6286 P3967 BST 11 0x410000f8 FP BE Pri
90928!#3 N6287 P3968 MEMBAR
90929!#3 N6288 P3969 LD 20 -1 Int BE Pri
90930!#3 N6289 P3969 CAS 20 -1 N6288 0x1800180 Int BE Pri
90931!#3 N6290 P3970 DWLD 2 -1 Int BE Pri
90932!#3 N6291 P3971 MEMBAR
90933!#3 N6292 P3972 BLD 3 -1 FP BE Pri
90934!#3 N6293 P3972 BLD 4 -1 FP BE Pri
90935!#A N6292 N6293
90936!#3 N6294 P3972 BLD 5 -1 FP BE Pri
90937!#3 N6295 P3973 MEMBAR
90938!#3 N6296 P3974 DWLD 0 -1 Int BE Pri
90939!#3 N6297 P3974 DWLD 1 -1 Int BE Pri
90940!#A N6296 N6297
90941!#3 N6298 P3975 SWAP 16 0xffffffff 0x1800181 Int BE Pri
90942!#3 N6299 P3976 LDD 8 -1 Int BE Pri
90943!#3 N6300 P3977 SWAP 19 0xffffffff 0x1800182 Int BE Pri
90944!#3 N6301 P3978 LD 1 -1 Int BE Pri
90945!#3 N6302 P3978 CAS 1 -1 N6301 0x1800183 Int BE Pri
90946!#3 N6303 P3979 ST_BINIT 6 0x1800184 Int BE Pri
90947!#3 N6304 P3980 MEMBAR
90948!#3 N6305 P3981 LDD 21 -1 Int BE Pri
90949!#3 N6306 P3981 LDD 22 -1 Int BE Pri
90950!#A N6305 N6306
90951!#3 N6307 P3982 MEMBAR
90952!#3 N6308 P3983 BST 0 0x410000f9 FP BE Pri
90953!#3 N6309 P3983 BST 1 0x410000fa FP BE Pri
90954!#A N6308 N6309
90955!#3 N6310 P3983 BST 2 0x410000fb FP BE Pri
90956!#3 N6311 P3984 MEMBAR
90957!#3 N6312 P3985 DWST_BINIT 11 0x1800185 Int BE Pri
90958!#3 N6313 P3986 MEMBAR
90959!#3 N6314 P3987 LDD 2 -1 Int BE Pri
90960!#3 N6315 P3988 LDD 9 -1 Int LE Pri
90961!#3 N6316 P3988 LDD 10 -1 Int LE Pri
90962!#A N6315 N6316
90963!#3 N6317 P3989 ST 23 0x1800186 Int BE Pri
90964!#3 N6318 P3990 DWST_BINIT 15 0x1800187 Int BE Pri
90965!#3 N6319 P3990 DWST_BINIT 16 0x1800188 Int BE Pri
90966!#A N6318 N6319
90967!#3 N6320 P3991 MEMBAR
90968!#3 N6321 P3992 BSTC 21 0x410000fc FP BE Pri
90969!#3 N6322 P3992 BSTC 22 0x410000fd FP BE Pri
90970!#A N6321 N6322
90971!#3 N6323 P3992 BSTC 23 0x410000fe FP BE Pri
90972!#3 N6324 P3993 MEMBAR
90973!#3 N6325 P3994 LDD 12 -1 Int BE Pri
90974!#3 N6326 P3994 LDD 13 -1 Int BE Pri
90975!#A N6325 N6326
90976!#3 N6327 P3995 LD 23 -1 Int BE Pri
90977!#3 N6328 P3996 MEMBAR
90978!#3 N6329 P3997 BSTC 21 0x410000ff FP BE Pri
90979!#3 N6330 P3997 BSTC 22 0x41000100 FP BE Pri
90980!#A N6329 N6330
90981!#3 N6331 P3997 BSTC 23 0x41000101 FP BE Pri
90982!#3 N6332 P3998 MEMBAR
90983!#3 N6333 P3999 ST_BINIT 1 0x1800189 Int BE Pri
90984!#3 N6334 P4000 MEMBAR
90985!#3 N6335 P4001 BSTC 15 0x41000102 FP BE Pri
90986!#3 N6336 P4001 BSTC 16 0x41000103 FP BE Pri
90987!#A N6335 N6336
90988!#3 N6337 P4001 BSTC 17 0x41000104 FP BE Pri
90989!#3 N6338 P4002 MEMBAR
90990!#3 N6339 P4003 DWST 9 0x180018a Int BE Pri
90991!#3 N6340 P4003 DWST 10 0x180018b Int BE Pri
90992!#A N6339 N6340
90993!#3 N6341 P4004 REPLACEMENT 12 Int BE Pri
90994!#3 N6342 P4005 MEMBAR
90995!#3 N6343 P4006 BLD 9 -1 FP BE Pri
90996!#3 N6344 P4006 BLD 10 -1 FP BE Pri
90997!#A N6343 N6344
90998!#3 N6345 P4006 BLD 11 -1 FP BE Pri
90999!#3 N6346 P4007 MEMBAR
91000!#3 N6347 P4008 LD 3 -1 Int BE Pri Loop_exit
91001!#3 N6348 P4009 MEMBAR
91002!#4 N6349 P4010 PREFETCH 22 Int LE Pri Loop_entry
91003!#4 N6350 P4011 MEMBAR
91004!#4 N6351 P4012 BLD 15 -1 FP BE Pri
91005!#4 N6352 P4012 BLD 16 -1 FP BE Pri
91006!#A N6351 N6352
91007!#4 N6353 P4012 BLD 17 -1 FP BE Pri
91008!#4 N6354 P4013 MEMBAR
91009!#4 N6355 P4014 SWAP 12 0xffffffff 0x2000001 Int BE Pri
91010!#4 N6356 P4015 DWLD 9 -1 Int LE Pri
91011!#4 N6357 P4015 DWLD 10 -1 Int LE Pri
91012!#A N6356 N6357
91013!#4 N6358 P4016 REPLACEMENT 3 Int BE Pri
91014!#4 N6359 P4017 ST 13 0x2000002 Int BE Pri
91015!#4 N6360 P4018 PREFETCH 2 Int BE Pri
91016!#4 N6361 P4019 MEMBAR
91017!#4 N6362 P4020 BSTC 3 0x41800001 FP BE Pri
91018!#4 N6363 P4020 BSTC 4 0x41800002 FP BE Pri
91019!#A N6362 N6363
91020!#4 N6364 P4020 BSTC 5 0x41800003 FP BE Pri
91021!#4 N6365 P4021 MEMBAR
91022!#4 N6366 P4022 SWAP 23 0xffffffff 0x2000003 Int BE Pri
91023!#4 N6367 P4023 MEMBAR
91024!#4 N6368 P4024 BLD 6 -1 FP BE Pri
91025!#4 N6369 P4024 BLD 7 -1 FP BE Pri
91026!#A N6368 N6369
91027!#4 N6370 P4024 BLD 8 -1 FP BE Pri
91028!#4 N6371 P4025 MEMBAR
91029!#4 N6372 P4026 BSTC 6 0x41800004 FP BE Pri
91030!#4 N6373 P4026 BSTC 7 0x41800005 FP BE Pri
91031!#A N6372 N6373
91032!#4 N6374 P4026 BSTC 8 0x41800006 FP BE Pri
91033!#4 N6375 P4027 MEMBAR
91034!#4 N6376 P4028 DWST 12 0x2000004 Int BE Pri
91035!#4 N6377 P4028 DWST 13 0x2000005 Int BE Pri
91036!#A N6376 N6377
91037!#4 N6378 P4029 DWST 17 0x2000006 Int BE Pri
91038!#4 N6379 P4030 DWLD 3 -1 Int BE Pri
91039!#4 N6380 P4030 DWLD 4 -1 Int BE Pri
91040!#A N6379 N6380
91041!#4 N6381 P4030 CASX 3 -1 N6379 0x2000007 Int BE Pri
91042!#4 N6382 P4030 CASX 4 -1 N6380 0x2000008 Int BE Pri
91043!#A N6381 N6382
91044!#4 N6383 P4031 ST_BINIT 16 0x2000009 Int BE Pri
91045!#4 N6384 P4032 MEMBAR
91046!#4 N6385 P4033 LDD 2 -1 Int BE Pri
91047!#4 N6386 P4034 DWLD 21 -1 Int BE Pri
91048!#4 N6387 P4034 DWLD 22 -1 Int BE Pri
91049!#A N6386 N6387
91050!#4 N6388 P4034 CASX 21 -1 N6386 0x200000a Int BE Pri
91051!#4 N6389 P4034 CASX 22 -1 N6387 0x200000b Int BE Pri
91052!#A N6388 N6389
91053!#4 N6390 P4035 ST 0 0x41800007 FP BE Pri
91054!#4 N6391 P4036 ST_BINIT 9 0x200000c Int LE Pri
91055!#4 N6392 P4037 MEMBAR
91056!#4 N6393 P4038 BLD 0 -1 FP BE Pri
91057!#4 N6394 P4038 BLD 1 -1 FP BE Pri
91058!#A N6393 N6394
91059!#4 N6395 P4038 BLD 2 -1 FP BE Pri
91060!#4 N6396 P4039 MEMBAR
91061!#4 N6397 P4040 ST 3 0x200000d Int BE Pri
91062!#4 N6398 P4041 MEMBAR
91063!#4 N6399 P4042 BLD 9 -1 FP BE Pri
91064!#4 N6400 P4042 BLD 10 -1 FP BE Pri
91065!#A N6399 N6400
91066!#4 N6401 P4042 BLD 11 -1 FP BE Pri
91067!#4 N6402 P4043 MEMBAR
91068!#4 N6403 P4044 PREFETCH 16 Int BE Pri
91069!#4 N6404 P4045 LD 15 -1 Int LE Pri
91070!#4 N6405 P4046 LD 9 -1 Int BE Pri
91071!#4 N6406 P4046 CAS 9 -1 N6405 0x200000e Int BE Pri
91072!#4 N6407 P4047 MEMBAR
91073!#4 N6408 P4048 BST 9 0x41800008 FP BE Pri
91074!#4 N6409 P4048 BST 10 0x41800009 FP BE Pri
91075!#A N6408 N6409
91076!#4 N6410 P4048 BST 11 0x4180000a FP BE Pri
91077!#4 N6411 P4049 MEMBAR
91078!#4 N6412 P4050 DWST 20 0x200000f Int LE Pri
91079!#4 N6413 P4051 ST_BINIT 16 0x2000010 Int BE Pri
91080!#4 N6414 P4052 MEMBAR
91081!#4 N6415 P4053 DWST 11 0x2000011 Int BE Pri
91082!#4 N6416 P4054 ST_BINIT 17 0x2000012 Int BE Pri
91083!#4 N6417 P4055 MEMBAR
91084!#4 N6418 P4056 LDD 14 -1 Int BE Pri
91085!#4 N6419 P4057 ST 6 0x2000013 Int LE Pri
91086!#4 N6420 P4058 DWST 20 0x2000014 Int BE Pri
91087!#4 N6421 P4059 MEMBAR
91088!#4 N6422 P4060 BSTC 18 0x4180000b FP BE Pri
91089!#4 N6423 P4060 BSTC 19 0x4180000c FP BE Pri
91090!#A N6422 N6423
91091!#4 N6424 P4060 BSTC 20 0x4180000d FP BE Pri
91092!#4 N6425 P4061 MEMBAR
91093!#4 N6426 P4062 ST_BINIT 5 0x2000015 Int BE Pri
91094!#4 N6427 P4063 MEMBAR
91095!#4 N6428 P4064 DWLD 0 -1 Int BE Pri
91096!#4 N6429 P4064 DWLD 1 -1 Int BE Pri
91097!#A N6428 N6429
91098!#4 N6430 P4064 CASX 0 -1 N6428 0x2000016 Int BE Pri
91099!#4 N6431 P4064 CASX 1 -1 N6429 0x2000017 Int BE Pri
91100!#A N6430 N6431
91101!#4 N6432 P4065 ST 11 0x2000018 Int BE Pri
91102!#4 N6433 P4066 LD 5 -1 Int LE Pri
91103!#4 N6434 P4067 LD 23 -1 Int LE Pri
91104!#4 N6435 P4068 LD 23 -1 Int BE Pri
91105!#4 N6436 P4069 MEMBAR
91106!#4 N6437 P4070 BST 6 0x4180000e FP BE Pri
91107!#4 N6438 P4070 BST 7 0x4180000f FP BE Pri
91108!#A N6437 N6438
91109!#4 N6439 P4070 BST 8 0x41800010 FP BE Pri
91110!#4 N6440 P4071 MEMBAR
91111!#4 N6441 P4072 DWLD 18 -1 Int BE Pri
91112!#4 N6442 P4072 DWLD 19 -1 Int BE Pri
91113!#A N6441 N6442
91114!#4 N6443 P4073 MEMBAR
91115!#4 N6444 P4074 BLD 6 -1 FP BE Pri
91116!#4 N6445 P4074 BLD 7 -1 FP BE Pri
91117!#A N6444 N6445
91118!#4 N6446 P4074 BLD 8 -1 FP BE Pri
91119!#4 N6447 P4075 MEMBAR
91120!#4 N6448 P4076 ST 16 0x2000019 Int BE Pri
91121!#4 N6449 P4077 PREFETCH 21 Int BE Pri
91122!#4 N6450 P4078 DWST 8 0x200001a Int BE Pri
91123!#4 N6451 P4079 MEMBAR
91124!#4 N6452 P4080 BLD 12 -1 FP BE Pri
91125!#4 N6453 P4080 BLD 13 -1 FP BE Pri
91126!#A N6452 N6453
91127!#4 N6454 P4080 BLD 14 -1 FP BE Pri
91128!#4 N6455 P4081 MEMBAR
91129!#4 N6456 P4082 DWST 6 0x200001b Int BE Pri
91130!#4 N6457 P4082 DWST 7 0x200001c Int BE Pri
91131!#A N6456 N6457
91132!#4 N6458 P4083 MEMBAR
91133!#4 N6459 P4084 BLD 3 -1 FP BE Pri
91134!#4 N6460 P4084 BLD 4 -1 FP BE Pri
91135!#A N6459 N6460
91136!#4 N6461 P4084 BLD 5 -1 FP BE Pri
91137!#4 N6462 P4085 MEMBAR
91138!#4 N6463 P4086 DWLD 9 -1 Int BE Pri
91139!#4 N6464 P4086 DWLD 10 -1 Int BE Pri
91140!#A N6463 N6464
91141!#4 N6465 P4086 CASX 9 -1 N6463 0x200001d Int BE Pri
91142!#4 N6466 P4086 CASX 10 -1 N6464 0x200001e Int BE Pri
91143!#A N6465 N6466
91144!#4 N6467 P4087 LD 18 -1 Int BE Pri
91145!#4 N6468 P4087 CAS 18 -1 N6467 0x200001f Int BE Pri
91146!#4 N6469 P4088 ST_BINIT 3 0x2000020 Int BE Pri
91147!#4 N6470 P4089 MEMBAR
91148!#4 N6471 P4090 BSTC 6 0x41800011 FP BE Pri
91149!#4 N6472 P4090 BSTC 7 0x41800012 FP BE Pri
91150!#A N6471 N6472
91151!#4 N6473 P4090 BSTC 8 0x41800013 FP BE Pri
91152!#4 N6474 P4091 MEMBAR
91153!#4 N6475 P4092 SWAP 6 0xffffffff 0x2000021 Int BE Pri
91154!#4 N6476 P4093 ST_BINIT 5 0x2000022 Int BE Pri
91155!#4 N6477 P4094 MEMBAR
91156!#4 N6478 P4095 REPLACEMENT 4 Int BE Pri
91157!#4 N6479 P4096 LDD 18 -1 Int BE Pri
91158!#4 N6480 P4096 LDD 19 -1 Int BE Pri
91159!#A N6479 N6480
91160!#4 N6481 P4097 LD 20 -1 Int BE Pri
91161!#4 N6482 P4097 CAS 20 -1 N6481 0x2000023 Int BE Pri
91162!#4 N6483 P4098 DWLD 8 -1,0x0 Int BE Pri
91163!#4 N6484 P4098 CASX 8 -1,0x0 N6483 0x2000024 Int BE Pri
91164!#4 N6485 P4099 LDD 18 -1 Int BE Pri
91165!#4 N6486 P4099 LDD 19 -1 Int BE Pri
91166!#A N6485 N6486
91167!#4 N6487 P4100 MEMBAR
91168!#4 N6488 P4101 BSTC 12 0x41800014 FP BE Pri
91169!#4 N6489 P4101 BSTC 13 0x41800015 FP BE Pri
91170!#A N6488 N6489
91171!#4 N6490 P4101 BSTC 14 0x41800016 FP BE Pri
91172!#4 N6491 P4102 MEMBAR
91173!#4 N6492 P4103 LDD 2 -1 Int BE Pri
91174!#4 N6493 P4104 LD 21 -1 Int BE Pri
91175!#4 N6494 P4104 CAS 21 -1 N6493 0x2000025 Int BE Pri
91176!#4 N6495 P4105 MEMBAR
91177!#4 N6496 P4106 BST 21 0x41800017 FP BE Pri
91178!#4 N6497 P4106 BST 22 0x41800018 FP BE Pri
91179!#A N6496 N6497
91180!#4 N6498 P4106 BST 23 0x41800019 FP BE Pri
91181!#4 N6499 P4107 MEMBAR
91182!#4 N6500 P4108 LD 10 -1 Int BE Pri
91183!#4 N6501 P4109 ST_BINIT 5 0x2000026 Int LE Pri
91184!#4 N6502 P4110 MEMBAR
91185!#4 N6503 P4111 BST 0 0x4180001a FP BE Pri
91186!#4 N6504 P4111 BST 1 0x4180001b FP BE Pri
91187!#A N6503 N6504
91188!#4 N6505 P4111 BST 2 0x4180001c FP BE Pri
91189!#4 N6506 P4112 MEMBAR
91190!#4 N6507 P4113 LD 4 -1 FP BE Pri
91191!#4 N6508 P4114 ST_BINIT 11 0x2000027 Int LE Pri
91192!#4 N6509 P4115 MEMBAR
91193!#4 N6510 P4116 ST 16 0x2000028 Int BE Pri
91194!#4 N6511 P4117 MEMBAR
91195!#4 N6512 P4118 BST 0 0x4180001d FP BE Pri
91196!#4 N6513 P4118 BST 1 0x4180001e FP BE Pri
91197!#A N6512 N6513
91198!#4 N6514 P4118 BST 2 0x4180001f FP BE Pri
91199!#4 N6515 P4119 MEMBAR
91200!#4 N6516 P4120 DWLD 23 -1 FP BE Pri
91201!#4 N6517 P4121 LD 7 -1 Int BE Pri
91202!#4 N6518 P4122 ST 18 0x2000029 Int BE Pri
91203!#4 N6519 P4123 LD 17 -1 FP BE Pri
91204!#4 N6520 P4124 LDD 2 -1 Int BE Pri
91205!#4 N6521 P4125 DWLD 3 -1 Int BE Pri
91206!#4 N6522 P4125 DWLD 4 -1 Int BE Pri
91207!#A N6521 N6522
91208!#4 N6523 P4125 CASX 3 -1 N6521 0x200002a Int BE Pri
91209!#4 N6524 P4125 CASX 4 -1 N6522 0x200002b Int BE Pri
91210!#A N6523 N6524
91211!#4 N6525 P4126 SWAP 4 0xffffffff 0x200002c Int BE Pri
91212!#4 N6526 P4127 MEMBAR
91213!#4 N6527 P4128 BSTC 3 0x41800020 FP BE Pri
91214!#4 N6528 P4128 BSTC 4 0x41800021 FP BE Pri
91215!#A N6527 N6528
91216!#4 N6529 P4128 BSTC 5 0x41800022 FP BE Pri
91217!#4 N6530 P4129 MEMBAR
91218!#4 N6531 P4130 ST 0 0x200002d Int BE Pri
91219!#4 N6532 P4131 LDD 18 -1 Int LE Pri
91220!#4 N6533 P4131 LDD 19 -1 Int LE Pri
91221!#A N6532 N6533
91222!#4 N6534 P4132 LDD 9 -1 Int BE Pri
91223!#4 N6535 P4132 LDD 10 -1 Int BE Pri
91224!#A N6534 N6535
91225!#4 N6536 P4133 PREFETCH 13 Int BE Pri
91226!#4 N6537 P4134 ST 19 0x200002e Int BE Pri
91227!#4 N6538 P4135 DWST 0 0x200002f Int BE Pri
91228!#4 N6539 P4135 DWST 1 0x2000030 Int BE Pri
91229!#A N6538 N6539
91230!#4 N6540 P4136 DWST 2 0x2000031 Int BE Pri
91231!#4 N6541 P4137 LD 21 -1 Int BE Pri
91232!#4 N6542 P4137 CAS 21 -1 N6541 0x2000032 Int BE Pri
91233!#4 N6543 P4138 DWLD 9 -1 Int BE Pri
91234!#4 N6544 P4138 DWLD 10 -1 Int BE Pri
91235!#A N6543 N6544
91236!#4 N6545 P4139 LD 15 -1 Int BE Pri
91237!#4 N6546 P4140 ST_BINIT 20 0x2000033 Int BE Pri
91238!#4 N6547 P4141 MEMBAR
91239!#4 N6548 P4142 PREFETCH 2 Int BE Pri
91240!#4 N6549 P4143 LDD 12 -1 Int BE Pri
91241!#4 N6550 P4143 LDD 13 -1 Int BE Pri
91242!#A N6549 N6550
91243!#4 N6551 P4144 DWLD 9 -1 FP BE Pri
91244!#4 N6552 P4144 DWLD 10 -1 FP BE Pri
91245!#A N6551 N6552
91246!#4 N6553 P4145 LD 18 -1 Int BE Pri
91247!#4 N6554 P4145 CAS 18 -1 N6553 0x2000034 Int BE Pri
91248!#4 N6555 P4146 LDD 12 -1 Int BE Pri
91249!#4 N6556 P4146 LDD 13 -1 Int BE Pri
91250!#A N6555 N6556
91251!#4 N6557 P4147 LDD 18 -1 Int BE Pri
91252!#4 N6558 P4147 LDD 19 -1 Int BE Pri
91253!#A N6557 N6558
91254!#4 N6559 P4148 DWST_BINIT 6 0x2000035 Int BE Pri
91255!#4 N6560 P4148 DWST_BINIT 7 0x2000036 Int BE Pri
91256!#A N6559 N6560
91257!#4 N6561 P4149 MEMBAR
91258!#4 N6562 P4150 BST 9 0x41800023 FP BE Pri
91259!#4 N6563 P4150 BST 10 0x41800024 FP BE Pri
91260!#A N6562 N6563
91261!#4 N6564 P4150 BST 11 0x41800025 FP BE Pri
91262!#4 N6565 P4151 MEMBAR
91263!#4 N6566 P4152 LD 20 -1 Int BE Pri
91264!#4 N6567 P4153 DWST_BINIT 21 0x2000037 Int BE Pri
91265!#4 N6568 P4153 DWST_BINIT 22 0x2000038 Int BE Pri
91266!#A N6567 N6568
91267!#4 N6569 P4154 MEMBAR
91268!#4 N6570 P4155 DWLD 3 -1 Int BE Pri
91269!#4 N6571 P4155 DWLD 4 -1 Int BE Pri
91270!#A N6570 N6571
91271!#4 N6572 P4155 CASX 3 -1 N6570 0x2000039 Int BE Pri
91272!#4 N6573 P4155 CASX 4 -1 N6571 0x200003a Int BE Pri
91273!#A N6572 N6573
91274!#4 N6574 P4156 DWST_BINIT 15 0x200003b Int BE Pri
91275!#4 N6575 P4156 DWST_BINIT 16 0x200003c Int BE Pri
91276!#A N6574 N6575
91277!#4 N6576 P4157 MEMBAR
91278!#4 N6577 P4158 PREFETCH 16 Int BE Pri
91279!#4 N6578 P4159 PREFETCH 4 Int BE Pri
91280!#4 N6579 P4160 LDD 12 -1 Int BE Pri
91281!#4 N6580 P4160 LDD 13 -1 Int BE Pri
91282!#A N6579 N6580
91283!#4 N6581 P4161 DWST_BINIT 21 0x200003d Int BE Pri
91284!#4 N6582 P4161 DWST_BINIT 22 0x200003e Int BE Pri
91285!#A N6581 N6582
91286!#4 N6583 P4162 MEMBAR
91287!#4 N6584 P4163 PREFETCH 18 Int BE Pri
91288!#4 N6585 P4164 ST 19 0x200003f Int BE Pri
91289!#4 N6586 P4165 DWST 15 0x2000040 Int BE Pri
91290!#4 N6587 P4165 DWST 16 0x2000041 Int BE Pri
91291!#A N6586 N6587
91292!#4 N6588 P4166 SWAP 23 0xffffffff 0x2000042 Int BE Pri
91293!#4 N6589 P4167 DWST_BINIT 11 0x2000043 Int BE Pri
91294!#4 N6590 P4168 MEMBAR
91295!#4 N6591 P4169 PREFETCH 7 Int BE Pri
91296!#4 N6592 P4170 LD 21 -1 Int BE Pri
91297!#4 N6593 P4171 MEMBAR
91298!#4 N6594 P4172 BST 18 0x41800026 FP BE Pri
91299!#4 N6595 P4172 BST 19 0x41800027 FP BE Pri
91300!#A N6594 N6595
91301!#4 N6596 P4172 BST 20 0x41800028 FP BE Pri
91302!#4 N6597 P4173 MEMBAR
91303!#4 N6598 P4174 LD 13 -1 FP BE Pri
91304!#4 N6599 P4175 DWLD 2 -1 Int BE Pri
91305!#4 N6600 P4176 DWST 12 0x2000044 Int BE Pri
91306!#4 N6601 P4176 DWST 13 0x2000045 Int BE Pri
91307!#A N6600 N6601
91308!#4 N6602 P4177 DWST 14 0x41800029 FP BE Pri
91309!#4 N6603 P4178 PREFETCH 22 Int BE Pri
91310!#4 N6604 P4179 LD 1 -1 Int LE Pri
91311!#4 N6605 P4180 LD 19 -1 Int BE Pri
91312!#4 N6606 P4181 REPLACEMENT 6 Int BE Pri
91313!#4 N6607 P4182 DWST_BINIT 12 0x2000046 Int BE Pri
91314!#4 N6608 P4182 DWST_BINIT 13 0x2000047 Int BE Pri
91315!#A N6607 N6608
91316!#4 N6609 P4183 MEMBAR
91317!#4 N6610 P4184 LD 22 -1 Int BE Pri
91318!#4 N6611 P4184 CAS 22 -1 N6610 0x2000048 Int BE Pri
91319!#4 N6612 P4185 SWAP 7 0xffffffff 0x2000049 Int BE Pri
91320!#4 N6613 P4186 PREFETCH 13 Int BE Pri
91321!#4 N6614 P4187 ST 23 0x200004a Int BE Pri
91322!#4 N6615 P4188 LD 15 -1 Int BE Pri
91323!#4 N6616 P4188 CAS 15 -1 N6615 0x200004b Int BE Pri
91324!#4 N6617 P4189 PREFETCH 15 Int BE Pri
91325!#4 N6618 P4190 DWLD 3 -1 Int BE Pri
91326!#4 N6619 P4190 DWLD 4 -1 Int BE Pri
91327!#A N6618 N6619
91328!#4 N6620 P4190 CASX 3 -1 N6618 0x200004c Int BE Pri
91329!#4 N6621 P4190 CASX 4 -1 N6619 0x200004d Int BE Pri
91330!#A N6620 N6621
91331!#4 N6622 P4191 DWLD 17 -1,0x0 Int BE Pri
91332!#4 N6623 P4191 CASX 17 -1,0x0 N6622 0x200004e Int BE Pri
91333!#4 N6624 P4192 MEMBAR
91334!#4 N6625 P4193 BLD 6 -1 FP BE Pri
91335!#4 N6626 P4193 BLD 7 -1 FP BE Pri
91336!#A N6625 N6626
91337!#4 N6627 P4193 BLD 8 -1 FP BE Pri
91338!#4 N6628 P4194 MEMBAR
91339!#4 N6629 P4195 DWLD 6 -1 Int BE Pri
91340!#4 N6630 P4195 DWLD 7 -1 Int BE Pri
91341!#A N6629 N6630
91342!#4 N6631 P4195 CASX 6 -1 N6629 0x200004f Int BE Pri
91343!#4 N6632 P4195 CASX 7 -1 N6630 0x2000050 Int BE Pri
91344!#A N6631 N6632
91345!#4 N6633 P4196 MEMBAR
91346!#4 N6634 P4197 BST 15 0x4180002a FP BE Pri
91347!#4 N6635 P4197 BST 16 0x4180002b FP BE Pri
91348!#A N6634 N6635
91349!#4 N6636 P4197 BST 17 0x4180002c FP BE Pri
91350!#4 N6637 P4198 MEMBAR
91351!#4 N6638 P4199 DWLD 17 -1,0x0 Int LE Pri
91352!#4 N6639 P4199 CASX 17 -1,0x0 N6638 0x2000051 Int LE Pri
91353!#4 N6640 P4200 DWST 15 0x2000052 Int BE Pri
91354!#4 N6641 P4200 DWST 16 0x2000053 Int BE Pri
91355!#A N6640 N6641
91356!#4 N6642 P4201 ST_BINIT 2 0x2000054 Int BE Pri
91357!#4 N6643 P4202 MEMBAR
91358!#4 N6644 P4203 LD 10 -1 Int BE Pri
91359!#4 N6645 P4203 CAS 10 -1 N6644 0x2000055 Int BE Pri
91360!#4 N6646 P4204 LD 22 -1 Int LE Pri
91361!#4 N6647 P4204 CAS 22 -1 N6646 0x2000056 Int LE Pri
91362!#4 N6648 P4205 DWLD 23 -1 FP BE Pri
91363!#4 N6649 P4206 ST 14 0x2000057 Int BE Pri
91364!#4 N6650 P4207 PREFETCH 12 Int BE Pri
91365!#4 N6651 P4208 DWST_BINIT 15 0x2000058 Int BE Pri
91366!#4 N6652 P4208 DWST_BINIT 16 0x2000059 Int BE Pri
91367!#A N6651 N6652
91368!#4 N6653 P4209 MEMBAR
91369!#4 N6654 P4210 BST 6 0x4180002d FP BE Pri
91370!#4 N6655 P4210 BST 7 0x4180002e FP BE Pri
91371!#A N6654 N6655
91372!#4 N6656 P4210 BST 8 0x4180002f FP BE Pri
91373!#4 N6657 P4211 MEMBAR
91374!#4 N6658 P4212 BLD 0 -1 FP BE Pri
91375!#4 N6659 P4212 BLD 1 -1 FP BE Pri
91376!#A N6658 N6659
91377!#4 N6660 P4212 BLD 2 -1 FP BE Pri
91378!#4 N6661 P4213 MEMBAR
91379!#4 N6662 P4214 SWAP 5 0xffffffff 0x200005a Int BE Pri
91380!#4 N6663 P4215 REPLACEMENT 1 Int BE Pri
91381!#4 N6664 P4216 LDD 6 -1 Int BE Pri
91382!#4 N6665 P4216 LDD 7 -1 Int BE Pri
91383!#A N6664 N6665
91384!#4 N6666 P4217 DWLD 9 -1 Int BE Pri
91385!#4 N6667 P4217 DWLD 10 -1 Int BE Pri
91386!#A N6666 N6667
91387!#4 N6668 P4218 DWLD 14 -1,0x0 Int BE Pri
91388!#4 N6669 P4218 CASX 14 -1,0x0 N6668 0x200005b Int BE Pri
91389!#4 N6670 P4219 MEMBAR
91390!#4 N6671 P4220 BSTC 18 0x41800030 FP BE Pri
91391!#4 N6672 P4220 BSTC 19 0x41800031 FP BE Pri
91392!#A N6671 N6672
91393!#4 N6673 P4220 BSTC 20 0x41800032 FP BE Pri
91394!#4 N6674 P4221 MEMBAR
91395!#4 N6675 P4222 ST_BINIT 19 0x200005c Int BE Pri
91396!#4 N6676 P4223 MEMBAR
91397!#4 N6677 P4224 DWST 9 0x200005d Int BE Pri
91398!#4 N6678 P4224 DWST 10 0x200005e Int BE Pri
91399!#A N6677 N6678
91400!#4 N6679 P4225 SWAP 12 0xffffffff 0x200005f Int BE Pri
91401!#4 N6680 P4226 DWLD 6 -1 Int BE Pri
91402!#4 N6681 P4226 DWLD 7 -1 Int BE Pri
91403!#A N6680 N6681
91404!#4 N6682 P4226 CASX 6 -1 N6680 0x2000060 Int BE Pri
91405!#4 N6683 P4226 CASX 7 -1 N6681 0x2000061 Int BE Pri
91406!#A N6682 N6683
91407!#4 N6684 P4227 MEMBAR
91408!#4 N6685 P4228 BST 18 0x41800033 FP BE Pri
91409!#4 N6686 P4228 BST 19 0x41800034 FP BE Pri
91410!#A N6685 N6686
91411!#4 N6687 P4228 BST 20 0x41800035 FP BE Pri
91412!#4 N6688 P4229 MEMBAR
91413!#4 N6689 P4230 ST 14 0x2000062 Int BE Pri
91414!#4 N6690 P4231 LD 18 -1 Int BE Pri
91415!#4 N6691 P4232 DWLD 2 -1 Int BE Pri
91416!#4 N6692 P4233 MEMBAR
91417!#4 N6693 P4234 BLD 15 -1 FP BE Pri
91418!#4 N6694 P4234 BLD 16 -1 FP BE Pri
91419!#A N6693 N6694
91420!#4 N6695 P4234 BLD 17 -1 FP BE Pri
91421!#4 N6696 P4235 MEMBAR
91422!#4 N6697 P4236 SWAP 1 0xffffffff 0x2000063 Int BE Pri
91423!#4 N6698 P4237 PREFETCH 23 Int BE Pri
91424!#4 N6699 P4238 DWLD 0 -1 Int BE Pri
91425!#4 N6700 P4238 DWLD 1 -1 Int BE Pri
91426!#A N6699 N6700
91427!#4 N6701 P4238 CASX 0 -1 N6699 0x2000064 Int BE Pri
91428!#4 N6702 P4238 CASX 1 -1 N6700 0x2000065 Int BE Pri
91429!#A N6701 N6702
91430!#4 N6703 P4239 LDD 21 -1 Int BE Pri
91431!#4 N6704 P4239 LDD 22 -1 Int BE Pri
91432!#A N6703 N6704
91433!#4 N6705 P4240 LD 13 -1 Int BE Pri
91434!#4 N6706 P4241 SWAP 22 0xffffffff 0x2000066 Int LE Pri
91435!#4 N6707 P4242 DWST_BINIT 8 0x2000067 Int BE Pri
91436!#4 N6708 P4243 MEMBAR
91437!#4 N6709 P4244 BST 3 0x41800036 FP BE Pri
91438!#4 N6710 P4244 BST 4 0x41800037 FP BE Pri
91439!#A N6709 N6710
91440!#4 N6711 P4244 BST 5 0x41800038 FP BE Pri
91441!#4 N6712 P4245 MEMBAR
91442!#4 N6713 P4246 ST 8 0x2000068 Int BE Pri
91443!#4 N6714 P4247 MEMBAR
91444!#4 N6715 P4248 BST 3 0x41800039 FP BE Pri
91445!#4 N6716 P4248 BST 4 0x4180003a FP BE Pri
91446!#A N6715 N6716
91447!#4 N6717 P4248 BST 5 0x4180003b FP BE Pri
91448!#4 N6718 P4249 MEMBAR
91449!#4 N6719 P4250 DWST_BINIT 20 0x2000069 Int BE Pri
91450!#4 N6720 P4251 MEMBAR
91451!#4 N6721 P4252 DWST 9 0x200006a Int BE Pri
91452!#4 N6722 P4252 DWST 10 0x200006b Int BE Pri
91453!#A N6721 N6722
91454!#4 N6723 P4253 PREFETCH 2 Int BE Pri
91455!#4 N6724 P4254 SWAP 13 0xffffffff 0x200006c Int BE Pri
91456!#4 N6725 P4255 PREFETCH 5 Int BE Pri
91457!#4 N6726 P4256 SWAP 0 0xffffffff 0x200006d Int BE Pri
91458!#4 N6727 P4257 LDD 23 -1 Int BE Pri
91459!#4 N6728 P4258 LDD 3 -1 Int BE Pri
91460!#4 N6729 P4258 LDD 4 -1 Int BE Pri
91461!#A N6728 N6729
91462!#4 N6730 P4259 MEMBAR
91463!#4 N6731 P4260 BLD 0 -1 FP BE Pri
91464!#4 N6732 P4260 BLD 1 -1 FP BE Pri
91465!#A N6731 N6732
91466!#4 N6733 P4260 BLD 2 -1 FP BE Pri
91467!#4 N6734 P4261 MEMBAR
91468!#4 N6735 P4262 SWAP 1 0xffffffff 0x200006e Int BE Pri
91469!#4 N6736 P4263 LD 22 -1 Int BE Pri
91470!#4 N6737 P4263 CAS 22 -1 N6736 0x200006f Int BE Pri
91471!#4 N6738 P4264 MEMBAR
91472!#4 N6739 P4265 BLD 18 -1 FP BE Pri
91473!#4 N6740 P4265 BLD 19 -1 FP BE Pri
91474!#A N6739 N6740
91475!#4 N6741 P4265 BLD 20 -1 FP BE Pri
91476!#4 N6742 P4266 MEMBAR
91477!#4 N6743 P4267 LD 13 -1 Int BE Pri
91478!#4 N6744 P4267 CAS 13 -1 N6743 0x2000070 Int BE Pri
91479!#4 N6745 P4268 DWST 11 0x2000071 Int BE Pri
91480!#4 N6746 P4269 MEMBAR
91481!#4 N6747 P4270 BSTC 3 0x4180003c FP BE Pri
91482!#4 N6748 P4270 BSTC 4 0x4180003d FP BE Pri
91483!#A N6747 N6748
91484!#4 N6749 P4270 BSTC 5 0x4180003e FP BE Pri
91485!#4 N6750 P4271 MEMBAR
91486!#4 N6751 P4272 DWLD 5 -1 Int BE Pri
91487!#4 N6752 P4273 LD 19 -1 Int BE Pri
91488!#4 N6753 P4273 CAS 19 -1 N6752 0x2000072 Int BE Pri
91489!#4 N6754 P4274 LD 21 -1 Int BE Pri
91490!#4 N6755 P4274 CAS 21 -1 N6754 0x2000073 Int BE Pri
91491!#4 N6756 P4275 ST_BINIT 16 0x2000074 Int BE Pri
91492!#4 N6757 P4276 MEMBAR
91493!#4 N6758 P4277 DWST_BINIT 5 0x2000075 Int BE Pri
91494!#4 N6759 P4278 MEMBAR
91495!#4 N6760 P4279 DWST 3 0x4180003f FP BE Pri
91496!#4 N6761 P4279 DWST 4 0x41800040 FP BE Pri
91497!#A N6760 N6761
91498!#4 N6762 P4280 LDD 0 -1 Int BE Pri
91499!#4 N6763 P4280 LDD 1 -1 Int BE Pri
91500!#A N6762 N6763
91501!#4 N6764 P4281 REPLACEMENT 5 Int BE Pri
91502!#4 N6765 P4282 DWST 6 0x2000076 Int BE Pri
91503!#4 N6766 P4282 DWST 7 0x2000077 Int BE Pri
91504!#A N6765 N6766
91505!#4 N6767 P4283 ST 11 0x2000078 Int BE Pri
91506!#4 N6768 P4284 MEMBAR
91507!#4 N6769 P4285 BST 0 0x41800041 FP BE Pri
91508!#4 N6770 P4285 BST 1 0x41800042 FP BE Pri
91509!#A N6769 N6770
91510!#4 N6771 P4285 BST 2 0x41800043 FP BE Pri
91511!#4 N6772 P4286 MEMBAR
91512!#4 N6773 P4287 DWLD 9 -1 Int BE Pri
91513!#4 N6774 P4287 DWLD 10 -1 Int BE Pri
91514!#A N6773 N6774
91515!#4 N6775 P4288 LDD 18 -1 Int BE Pri
91516!#4 N6776 P4288 LDD 19 -1 Int BE Pri
91517!#A N6775 N6776
91518!#4 N6777 P4289 PREFETCH 21 Int BE Pri
91519!#4 N6778 P4290 MEMBAR
91520!#4 N6779 P4291 BST 12 0x41800044 FP BE Pri
91521!#4 N6780 P4291 BST 13 0x41800045 FP BE Pri
91522!#A N6779 N6780
91523!#4 N6781 P4291 BST 14 0x41800046 FP BE Pri
91524!#4 N6782 P4292 MEMBAR
91525!#4 N6783 P4293 DWST 14 0x2000079 Int BE Pri
91526!#4 N6784 P4294 MEMBAR
91527!#4 N6785 P4295 BSTC 18 0x41800047 FP BE Pri
91528!#4 N6786 P4295 BSTC 19 0x41800048 FP BE Pri
91529!#A N6785 N6786
91530!#4 N6787 P4295 BSTC 20 0x41800049 FP BE Pri
91531!#4 N6788 P4296 MEMBAR
91532!#4 N6789 P4297 DWST_BINIT 12 0x200007a Int BE Pri
91533!#4 N6790 P4297 DWST_BINIT 13 0x200007b Int BE Pri
91534!#A N6789 N6790
91535!#4 N6791 P4298 MEMBAR
91536!#4 N6792 P4299 DWST 3 0x4180004a FP BE Pri
91537!#4 N6793 P4299 DWST 4 0x4180004b FP BE Pri
91538!#A N6792 N6793
91539!#4 N6794 P4300 MEMBAR
91540!#4 N6795 P4301 BST 21 0x4180004c FP BE Pri
91541!#4 N6796 P4301 BST 22 0x4180004d FP BE Pri
91542!#A N6795 N6796
91543!#4 N6797 P4301 BST 23 0x4180004e FP BE Pri
91544!#4 N6798 P4302 MEMBAR
91545!#4 N6799 P4303 DWST_BINIT 0 0x200007c Int BE Pri
91546!#4 N6800 P4303 DWST_BINIT 1 0x200007d Int BE Pri
91547!#A N6799 N6800
91548!#4 N6801 P4304 MEMBAR
91549!#4 N6802 P4305 LD 10 -1 Int BE Pri
91550!#4 N6803 P4305 CAS 10 -1 N6802 0x200007e Int BE Pri
91551!#4 N6804 P4306 LDD 12 -1 Int BE Pri
91552!#4 N6805 P4306 LDD 13 -1 Int BE Pri
91553!#A N6804 N6805
91554!#4 N6806 P4307 LDD 8 -1 Int BE Pri
91555!#4 N6807 P4308 MEMBAR
91556!#4 N6808 P4309 BSTC 0 0x4180004f FP BE Pri
91557!#4 N6809 P4309 BSTC 1 0x41800050 FP BE Pri
91558!#A N6808 N6809
91559!#4 N6810 P4309 BSTC 2 0x41800051 FP BE Pri
91560!#4 N6811 P4310 MEMBAR
91561!#4 N6812 P4311 BLD 18 -1 FP BE Pri
91562!#4 N6813 P4311 BLD 19 -1 FP BE Pri
91563!#A N6812 N6813
91564!#4 N6814 P4311 BLD 20 -1 FP BE Pri
91565!#4 N6815 P4312 MEMBAR
91566!#4 N6816 P4313 DWST 23 0x41800052 FP BE Pri
91567!#4 N6817 P4314 DWLD 21 -1 Int BE Pri
91568!#4 N6818 P4314 DWLD 22 -1 Int BE Pri
91569!#A N6817 N6818
91570!#4 N6819 P4314 CASX 21 -1 N6817 0x200007f Int BE Pri
91571!#4 N6820 P4314 CASX 22 -1 N6818 0x2000080 Int BE Pri
91572!#A N6819 N6820
91573!#4 N6821 P4315 LD 6 -1 Int BE Pri
91574!#4 N6822 P4315 CAS 6 -1 N6821 0x2000081 Int BE Pri
91575!#4 N6823 P4316 DWST_BINIT 3 0x2000082 Int BE Pri
91576!#4 N6824 P4316 DWST_BINIT 4 0x2000083 Int BE Pri
91577!#A N6823 N6824
91578!#4 N6825 P4317 MEMBAR
91579!#4 N6826 P4318 ST 18 0x2000084 Int BE Pri
91580!#4 N6827 P4319 DWLD 3 -1 Int LE Pri
91581!#4 N6828 P4319 DWLD 4 -1 Int LE Pri
91582!#A N6827 N6828
91583!#4 N6829 P4319 CASX 3 -1 N6827 0x2000085 Int LE Pri
91584!#4 N6830 P4319 CASX 4 -1 N6828 0x2000086 Int LE Pri
91585!#A N6829 N6830
91586!#4 N6831 P4320 REPLACEMENT 15 Int BE Pri
91587!#4 N6832 P4321 PREFETCH 15 Int BE Pri
91588!#4 N6833 P4322 LD 4 -1 Int BE Pri
91589!#4 N6834 P4322 CAS 4 -1 N6833 0x2000087 Int BE Pri
91590!#4 N6835 P4323 SWAP 13 0xffffffff 0x2000088 Int BE Pri
91591!#4 N6836 P4324 ST_BINIT 21 0x2000089 Int BE Pri
91592!#4 N6837 P4325 MEMBAR
91593!#4 N6838 P4326 DWLD 6 -1 Int BE Pri
91594!#4 N6839 P4326 DWLD 7 -1 Int BE Pri
91595!#A N6838 N6839
91596!#4 N6840 P4326 CASX 6 -1 N6838 0x200008a Int BE Pri
91597!#4 N6841 P4326 CASX 7 -1 N6839 0x200008b Int BE Pri
91598!#A N6840 N6841
91599!#4 N6842 P4327 ST_BINIT 0 0x200008c Int BE Pri
91600!#4 N6843 P4328 MEMBAR
91601!#4 N6844 P4329 PREFETCH 11 Int BE Pri
91602!#4 N6845 P4330 LDD 14 -1 Int BE Pri
91603!#4 N6846 P4331 DWST_BINIT 14 0x200008d Int BE Pri
91604!#4 N6847 P4332 MEMBAR
91605!#4 N6848 P4333 LD 19 -1 Int BE Pri
91606!#4 N6849 P4333 CAS 19 -1 N6848 0x200008e Int BE Pri
91607!#4 N6850 P4334 MEMBAR
91608!#4 N6851 P4335 BSTC 21 0x41800053 FP BE Pri
91609!#4 N6852 P4335 BSTC 22 0x41800054 FP BE Pri
91610!#A N6851 N6852
91611!#4 N6853 P4335 BSTC 23 0x41800055 FP BE Pri
91612!#4 N6854 P4336 MEMBAR
91613!#4 N6855 P4337 ST 5 0x200008f Int BE Pri
91614!#4 N6856 P4338 ST 8 0x41800056 FP BE Pri
91615!#4 N6857 P4339 LD 13 -1 Int BE Pri
91616!#4 N6858 P4340 PREFETCH 1 Int BE Pri
91617!#4 N6859 P4341 SWAP 6 0xffffffff 0x2000090 Int BE Pri
91618!#4 N6860 P4342 ST_BINIT 15 0x2000091 Int BE Pri
91619!#4 N6861 P4343 MEMBAR
91620!#4 N6862 P4344 BST 12 0x41800057 FP BE Pri
91621!#4 N6863 P4344 BST 13 0x41800058 FP BE Pri
91622!#A N6862 N6863
91623!#4 N6864 P4344 BST 14 0x41800059 FP BE Pri
91624!#4 N6865 P4345 MEMBAR
91625!#4 N6866 P4346 LD 13 -1 Int BE Pri
91626!#4 N6867 P4347 PREFETCH 16 Int BE Pri
91627!#4 N6868 P4348 MEMBAR
91628!#4 N6869 P4349 BST 18 0x4180005a FP BE Pri
91629!#4 N6870 P4349 BST 19 0x4180005b FP BE Pri
91630!#A N6869 N6870
91631!#4 N6871 P4349 BST 20 0x4180005c FP BE Pri
91632!#4 N6872 P4350 MEMBAR
91633!#4 N6873 P4351 PREFETCH 3 Int BE Pri
91634!#4 N6874 P4352 DWST 3 0x2000092 Int BE Pri
91635!#4 N6875 P4352 DWST 4 0x2000093 Int BE Pri
91636!#A N6874 N6875
91637!#4 N6876 P4353 PREFETCH 12 Int BE Pri
91638!#4 N6877 P4354 MEMBAR
91639!#4 N6878 P4355 BSTC 18 0x4180005d FP BE Pri
91640!#4 N6879 P4355 BSTC 19 0x4180005e FP BE Pri
91641!#A N6878 N6879
91642!#4 N6880 P4355 BSTC 20 0x4180005f FP BE Pri
91643!#4 N6881 P4356 MEMBAR
91644!#4 N6882 P4357 BLD 0 -1 FP BE Pri
91645!#4 N6883 P4357 BLD 1 -1 FP BE Pri
91646!#A N6882 N6883
91647!#4 N6884 P4357 BLD 2 -1 FP BE Pri
91648!#4 N6885 P4358 MEMBAR
91649!#4 N6886 P4359 ST 0 0x2000094 Int BE Pri
91650!#4 N6887 P4360 DWST_BINIT 11 0x2000095 Int BE Pri
91651!#4 N6888 P4361 MEMBAR
91652!#4 N6889 P4362 DWST 12 0x2000096 Int BE Pri
91653!#4 N6890 P4362 DWST 13 0x2000097 Int BE Pri
91654!#A N6889 N6890
91655!#4 N6891 P4363 LD 0 -1 Int BE Pri
91656!#4 N6892 P4363 CAS 0 -1 N6891 0x2000098 Int BE Pri
91657!#4 N6893 P4364 PREFETCH 0 Int BE Pri
91658!#4 N6894 P4365 MEMBAR
91659!#4 N6895 P4366 BSTC 3 0x41800060 FP BE Pri
91660!#4 N6896 P4366 BSTC 4 0x41800061 FP BE Pri
91661!#A N6895 N6896
91662!#4 N6897 P4366 BSTC 5 0x41800062 FP BE Pri
91663!#4 N6898 P4367 MEMBAR
91664!#4 N6899 P4368 BLD 3 -1 FP BE Pri
91665!#4 N6900 P4368 BLD 4 -1 FP BE Pri
91666!#A N6899 N6900
91667!#4 N6901 P4368 BLD 5 -1 FP BE Pri
91668!#4 N6902 P4369 MEMBAR
91669!#4 N6903 P4370 PREFETCH 2 Int BE Pri
91670!#4 N6904 P4371 ST 14 0x2000099 Int BE Pri
91671!#4 N6905 P4372 LD 9 -1 Int BE Pri
91672!#4 N6906 P4372 CAS 9 -1 N6905 0x200009a Int BE Pri
91673!#4 N6907 P4373 LD 3 -1 Int BE Pri
91674!#4 N6908 P4374 SWAP 15 0xffffffff 0x200009b Int BE Pri
91675!#4 N6909 P4375 DWLD 14 -1,0x0 Int BE Pri
91676!#4 N6910 P4375 CASX 14 -1,0x0 N6909 0x200009c Int BE Pri
91677!#4 N6911 P4376 MEMBAR
91678!#4 N6912 P4377 BST 12 0x41800063 FP BE Pri
91679!#4 N6913 P4377 BST 13 0x41800064 FP BE Pri
91680!#A N6912 N6913
91681!#4 N6914 P4377 BST 14 0x41800065 FP BE Pri
91682!#4 N6915 P4378 MEMBAR
91683!#4 N6916 P4379 DWLD 6 -1 Int BE Pri
91684!#4 N6917 P4379 DWLD 7 -1 Int BE Pri
91685!#A N6916 N6917
91686!#4 N6918 P4379 CASX 6 -1 N6916 0x200009d Int BE Pri
91687!#4 N6919 P4379 CASX 7 -1 N6917 0x200009e Int BE Pri
91688!#A N6918 N6919
91689!#4 N6920 P4380 DWST 23 0x200009f Int BE Pri
91690!#4 N6921 P4381 DWST_BINIT 12 0x20000a0 Int BE Pri
91691!#4 N6922 P4381 DWST_BINIT 13 0x20000a1 Int BE Pri
91692!#A N6921 N6922
91693!#4 N6923 P4382 MEMBAR
91694!#4 N6924 P4383 ST 2 0x20000a2 Int BE Pri
91695!#4 N6925 P4384 SWAP 20 0xffffffff 0x20000a3 Int BE Pri
91696!#4 N6926 P4385 PREFETCH 13 Int BE Pri
91697!#4 N6927 P4386 LDD 8 -1 Int BE Pri
91698!#4 N6928 P4387 LD 15 -1 Int BE Pri
91699!#4 N6929 P4387 CAS 15 -1 N6928 0x20000a4 Int BE Pri
91700!#4 N6930 P4388 MEMBAR
91701!#4 N6931 P4389 BSTC 12 0x41800066 FP BE Pri
91702!#4 N6932 P4389 BSTC 13 0x41800067 FP BE Pri
91703!#A N6931 N6932
91704!#4 N6933 P4389 BSTC 14 0x41800068 FP BE Pri
91705!#4 N6934 P4390 MEMBAR
91706!#4 N6935 P4391 REPLACEMENT 7 Int BE Pri
91707!#4 N6936 P4392 DWLD 21 -1 Int BE Pri
91708!#4 N6937 P4392 DWLD 22 -1 Int BE Pri
91709!#A N6936 N6937
91710!#4 N6938 P4392 CASX 21 -1 N6936 0x20000a5 Int BE Pri
91711!#4 N6939 P4392 CASX 22 -1 N6937 0x20000a6 Int BE Pri
91712!#A N6938 N6939
91713!#4 N6940 P4393 MEMBAR
91714!#4 N6941 P4394 BST 6 0x41800069 FP BE Pri
91715!#4 N6942 P4394 BST 7 0x4180006a FP BE Pri
91716!#A N6941 N6942
91717!#4 N6943 P4394 BST 8 0x4180006b FP BE Pri
91718!#4 N6944 P4395 MEMBAR
91719!#4 N6945 P4396 LDD 8 -1 Int LE Pri
91720!#4 N6946 P4397 LD 22 -1 Int BE Pri
91721!#4 N6947 P4398 ST_BINIT 11 0x20000a7 Int BE Pri
91722!#4 N6948 P4399 MEMBAR
91723!#4 N6949 P4400 DWST_BINIT 9 0x20000a8 Int BE Pri
91724!#4 N6950 P4400 DWST_BINIT 10 0x20000a9 Int BE Pri
91725!#A N6949 N6950
91726!#4 N6951 P4401 MEMBAR
91727!#4 N6952 P4402 REPLACEMENT 5 Int BE Pri
91728!#4 N6953 P4403 ST 6 0x20000aa Int BE Pri
91729!#4 N6954 P4404 DWST_BINIT 0 0x20000ab Int BE Pri
91730!#4 N6955 P4404 DWST_BINIT 1 0x20000ac Int BE Pri
91731!#A N6954 N6955
91732!#4 N6956 P4405 MEMBAR
91733!#4 N6957 P4406 BSTC 18 0x4180006c FP BE Pri
91734!#4 N6958 P4406 BSTC 19 0x4180006d FP BE Pri
91735!#A N6957 N6958
91736!#4 N6959 P4406 BSTC 20 0x4180006e FP BE Pri
91737!#4 N6960 P4407 MEMBAR
91738!#4 N6961 P4408 BLD 6 -1 FP BE Pri
91739!#4 N6962 P4408 BLD 7 -1 FP BE Pri
91740!#A N6961 N6962
91741!#4 N6963 P4408 BLD 8 -1 FP BE Pri
91742!#4 N6964 P4409 MEMBAR
91743!#4 N6965 P4410 DWLD 21 -1 Int BE Pri
91744!#4 N6966 P4410 DWLD 22 -1 Int BE Pri
91745!#A N6965 N6966
91746!#4 N6967 P4410 CASX 21 -1 N6965 0x20000ad Int BE Pri
91747!#4 N6968 P4410 CASX 22 -1 N6966 0x20000ae Int BE Pri
91748!#A N6967 N6968
91749!#4 N6969 P4411 ST 0 0x20000af Int BE Pri
91750!#4 N6970 P4412 SWAP 7 0xffffffff 0x20000b0 Int BE Pri
91751!#4 N6971 P4413 LDD 3 -1 Int BE Pri
91752!#4 N6972 P4413 LDD 4 -1 Int BE Pri
91753!#A N6971 N6972
91754!#4 N6973 P4414 MEMBAR
91755!#4 N6974 P4415 BST 0 0x4180006f FP BE Pri
91756!#4 N6975 P4415 BST 1 0x41800070 FP BE Pri
91757!#A N6974 N6975
91758!#4 N6976 P4415 BST 2 0x41800071 FP BE Pri
91759!#4 N6977 P4416 MEMBAR
91760!#4 N6978 P4417 DWLD 0 -1 Int BE Pri
91761!#4 N6979 P4417 DWLD 1 -1 Int BE Pri
91762!#A N6978 N6979
91763!#4 N6980 P4418 LD 11 -1 Int BE Pri
91764!#4 N6981 P4418 CAS 11 -1 N6980 0x20000b1 Int BE Pri
91765!#4 N6982 P4419 MEMBAR
91766!#4 N6983 P4420 BST 15 0x41800072 FP BE Pri
91767!#4 N6984 P4420 BST 16 0x41800073 FP BE Pri
91768!#A N6983 N6984
91769!#4 N6985 P4420 BST 17 0x41800074 FP BE Pri
91770!#4 N6986 P4421 MEMBAR
91771!#4 N6987 P4422 DWST 15 0x20000b2 Int BE Pri
91772!#4 N6988 P4422 DWST 16 0x20000b3 Int BE Pri
91773!#A N6987 N6988
91774!#4 N6989 P4423 LD 22 -1 Int BE Pri
91775!#4 N6990 P4424 DWST_BINIT 11 0x20000b4 Int BE Pri
91776!#4 N6991 P4425 MEMBAR
91777!#4 N6992 P4426 REPLACEMENT 20 Int BE Pri
91778!#4 N6993 P4427 LDD 14 -1 Int BE Pri
91779!#4 N6994 P4428 LD 22 -1 Int BE Pri
91780!#4 N6995 P4428 CAS 22 -1 N6994 0x20000b5 Int BE Pri
91781!#4 N6996 P4429 ST_BINIT 1 0x20000b6 Int BE Pri
91782!#4 N6997 P4430 MEMBAR
91783!#4 N6998 P4431 DWLD 0 -1 Int BE Pri
91784!#4 N6999 P4431 DWLD 1 -1 Int BE Pri
91785!#A N6998 N6999
91786!#4 N7000 P4431 CASX 0 -1 N6998 0x20000b7 Int BE Pri
91787!#4 N7001 P4431 CASX 1 -1 N6999 0x20000b8 Int BE Pri
91788!#A N7000 N7001
91789!#4 N7002 P4432 MEMBAR
91790!#4 N7003 P4433 BLD 9 -1 FP BE Pri
91791!#4 N7004 P4433 BLD 10 -1 FP BE Pri
91792!#A N7003 N7004
91793!#4 N7005 P4433 BLD 11 -1 FP BE Pri
91794!#4 N7006 P4434 MEMBAR
91795!#4 N7007 P4435 LD 21 -1 Int BE Pri
91796!#4 N7008 P4436 DWLD 14 -1,0x0 Int BE Pri
91797!#4 N7009 P4436 CASX 14 -1,0x0 N7008 0x20000b9 Int BE Pri
91798!#4 N7010 P4437 DWST_BINIT 0 0x20000ba Int BE Pri
91799!#4 N7011 P4437 DWST_BINIT 1 0x20000bb Int BE Pri
91800!#A N7010 N7011
91801!#4 N7012 P4438 MEMBAR
91802!#4 N7013 P4439 LD 8 -1 Int BE Pri
91803!#4 N7014 P4439 CAS 8 -1 N7013 0x20000bc Int BE Pri
91804!#4 N7015 P4440 DWLD 6 -1 Int BE Pri
91805!#4 N7016 P4440 DWLD 7 -1 Int BE Pri
91806!#A N7015 N7016
91807!#4 N7017 P4440 CASX 6 -1 N7015 0x20000bd Int BE Pri
91808!#4 N7018 P4440 CASX 7 -1 N7016 0x20000be Int BE Pri
91809!#A N7017 N7018
91810!#4 N7019 P4441 LD 12 -1 Int BE Pri
91811!#4 N7020 P4441 CAS 12 -1 N7019 0x20000bf Int BE Pri
91812!#4 N7021 P4442 LD 12 -1 Int BE Pri
91813!#4 N7022 P4443 DWLD 23 -1 Int BE Pri
91814!#4 N7023 P4444 DWLD 17 -1 Int BE Pri
91815!#4 N7024 P4445 MEMBAR
91816!#4 N7025 P4446 BST 0 0x41800075 FP BE Pri
91817!#4 N7026 P4446 BST 1 0x41800076 FP BE Pri
91818!#A N7025 N7026
91819!#4 N7027 P4446 BST 2 0x41800077 FP BE Pri
91820!#4 N7028 P4447 MEMBAR
91821!#4 N7029 P4448 LD 15 -1 Int BE Pri
91822!#4 N7030 P4449 LD 19 -1 Int LE Pri
91823!#4 N7031 P4450 PREFETCH 5 Int BE Pri
91824!#4 N7032 P4451 MEMBAR
91825!#4 N7033 P4452 BST 21 0x41800078 FP BE Pri
91826!#4 N7034 P4452 BST 22 0x41800079 FP BE Pri
91827!#A N7033 N7034
91828!#4 N7035 P4452 BST 23 0x4180007a FP BE Pri
91829!#4 N7036 P4453 MEMBAR
91830!#4 N7037 P4454 REPLACEMENT 0 Int BE Pri
91831!#4 N7038 P4455 LD 12 -1 Int BE Pri
91832!#4 N7039 P4456 SWAP 23 0xffffffff 0x20000c0 Int BE Pri
91833!#4 N7040 P4457 LD 7 -1 Int BE Pri
91834!#4 N7041 P4457 CAS 7 -1 N7040 0x20000c1 Int BE Pri
91835!#4 N7042 P4458 DWST_BINIT 3 0x20000c2 Int BE Pri
91836!#4 N7043 P4458 DWST_BINIT 4 0x20000c3 Int BE Pri
91837!#A N7042 N7043
91838!#4 N7044 P4459 MEMBAR
91839!#4 N7045 P4460 PREFETCH 22 Int BE Pri
91840!#4 N7046 P4461 LDD 9 -1 Int BE Pri
91841!#4 N7047 P4461 LDD 10 -1 Int BE Pri
91842!#A N7046 N7047
91843!#4 N7048 P4462 MEMBAR
91844!#4 N7049 P4463 BLD 12 -1 FP BE Pri
91845!#4 N7050 P4463 BLD 13 -1 FP BE Pri
91846!#A N7049 N7050
91847!#4 N7051 P4463 BLD 14 -1 FP BE Pri
91848!#4 N7052 P4464 MEMBAR
91849!#4 N7053 P4465 DWST 3 0x20000c4 Int BE Pri
91850!#4 N7054 P4465 DWST 4 0x20000c5 Int BE Pri
91851!#A N7053 N7054
91852!#4 N7055 P4466 LDD 9 -1 Int BE Pri
91853!#4 N7056 P4466 LDD 10 -1 Int BE Pri
91854!#A N7055 N7056
91855!#4 N7057 P4467 LDD 23 -1 Int BE Pri
91856!#4 N7058 P4468 SWAP 18 0xffffffff 0x20000c6 Int BE Pri
91857!#4 N7059 P4469 DWST_BINIT 18 0x20000c7 Int BE Pri
91858!#4 N7060 P4469 DWST_BINIT 19 0x20000c8 Int BE Pri
91859!#A N7059 N7060
91860!#4 N7061 P4470 MEMBAR
91861!#4 N7062 P4471 LD 21 -1 Int BE Pri
91862!#4 N7063 P4472 LD 21 -1 Int BE Pri
91863!#4 N7064 P4473 REPLACEMENT 1 Int BE Pri
91864!#4 N7065 P4474 MEMBAR
91865!#4 N7066 P4475 BST 3 0x4180007b FP BE Pri
91866!#4 N7067 P4475 BST 4 0x4180007c FP BE Pri
91867!#A N7066 N7067
91868!#4 N7068 P4475 BST 5 0x4180007d FP BE Pri
91869!#4 N7069 P4476 MEMBAR
91870!#4 N7070 P4477 PREFETCH 0 Int BE Pri
91871!#4 N7071 P4478 DWST 18 0x20000c9 Int BE Pri
91872!#4 N7072 P4478 DWST 19 0x20000ca Int BE Pri
91873!#A N7071 N7072
91874!#4 N7073 P4479 SWAP 20 0xffffffff 0x20000cb Int LE Pri
91875!#4 N7074 P4480 LDD 21 -1 Int BE Pri
91876!#4 N7075 P4480 LDD 22 -1 Int BE Pri
91877!#A N7074 N7075
91878!#4 N7076 P4481 REPLACEMENT 1 Int BE Pri
91879!#4 N7077 P4482 PREFETCH 19 Int BE Pri
91880!#4 N7078 P4483 SWAP 13 0xffffffff 0x20000cc Int BE Pri
91881!#4 N7079 P4484 SWAP 21 0xffffffff 0x20000cd Int BE Pri
91882!#4 N7080 P4485 DWST_BINIT 21 0x20000ce Int BE Pri
91883!#4 N7081 P4485 DWST_BINIT 22 0x20000cf Int BE Pri
91884!#A N7080 N7081
91885!#4 N7082 P4486 MEMBAR
91886!#4 N7083 P4487 SWAP 12 0xffffffff 0x20000d0 Int BE Pri
91887!#4 N7084 P4488 LDD 12 -1 Int BE Pri
91888!#4 N7085 P4488 LDD 13 -1 Int BE Pri
91889!#A N7084 N7085
91890!#4 N7086 P4489 MEMBAR
91891!#4 N7087 P4490 BST 18 0x4180007e FP BE Pri
91892!#4 N7088 P4490 BST 19 0x4180007f FP BE Pri
91893!#A N7087 N7088
91894!#4 N7089 P4490 BST 20 0x41800080 FP BE Pri
91895!#4 N7090 P4491 MEMBAR
91896!#4 N7091 P4492 DWLD 3 -1 Int BE Pri
91897!#4 N7092 P4492 DWLD 4 -1 Int BE Pri
91898!#A N7091 N7092
91899!#4 N7093 P4492 CASX 3 -1 N7091 0x20000d1 Int BE Pri
91900!#4 N7094 P4492 CASX 4 -1 N7092 0x20000d2 Int BE Pri
91901!#A N7093 N7094
91902!#4 N7095 P4493 PREFETCH 7 Int BE Pri
91903!#4 N7096 P4494 MEMBAR
91904!#4 N7097 P4495 BSTC 9 0x41800081 FP BE Pri
91905!#4 N7098 P4495 BSTC 10 0x41800082 FP BE Pri
91906!#A N7097 N7098
91907!#4 N7099 P4495 BSTC 11 0x41800083 FP BE Pri
91908!#4 N7100 P4496 MEMBAR
91909!#4 N7101 P4497 DWLD 18 -1 Int BE Pri
91910!#4 N7102 P4497 DWLD 19 -1 Int BE Pri
91911!#A N7101 N7102
91912!#4 N7103 P4498 DWST 9 0x20000d3 Int BE Pri
91913!#4 N7104 P4498 DWST 10 0x20000d4 Int BE Pri
91914!#A N7103 N7104
91915!#4 N7105 P4499 MEMBAR
91916!#4 N7106 P4500 BST 3 0x41800084 FP BE Pri
91917!#4 N7107 P4500 BST 4 0x41800085 FP BE Pri
91918!#A N7106 N7107
91919!#4 N7108 P4500 BST 5 0x41800086 FP BE Pri
91920!#4 N7109 P4501 MEMBAR
91921!#4 N7110 P4502 LD 17 -1 Int BE Pri
91922!#4 N7111 P4503 LDD 11 -1 Int BE Pri
91923!#4 N7112 P4504 SWAP 4 0xffffffff 0x20000d5 Int BE Pri
91924!#4 N7113 P4505 LD 0 -1 Int BE Pri
91925!#4 N7114 P4506 SWAP 14 0xffffffff 0x20000d6 Int BE Pri
91926!#4 N7115 P4507 ST 5 0x20000d7 Int LE Pri
91927!#4 N7116 P4508 DWST 14 0x41800087 FP BE Pri
91928!#4 N7117 P4509 LD 23 -1 Int BE Pri
91929!#4 N7118 P4510 REPLACEMENT 0 Int BE Pri
91930!#4 N7119 P4511 DWST_BINIT 9 0x20000d8 Int LE Pri
91931!#4 N7120 P4511 DWST_BINIT 10 0x20000d9 Int LE Pri
91932!#A N7119 N7120
91933!#4 N7121 P4512 MEMBAR
91934!#4 N7122 P4513 ST_BINIT 7 0x20000da Int BE Pri
91935!#4 N7123 P4514 MEMBAR
91936!#4 N7124 P4515 LDD 9 -1 Int LE Pri
91937!#4 N7125 P4515 LDD 10 -1 Int LE Pri
91938!#A N7124 N7125
91939!#4 N7126 P4516 DWLD 18 -1 Int BE Pri
91940!#4 N7127 P4516 DWLD 19 -1 Int BE Pri
91941!#A N7126 N7127
91942!#4 N7128 P4517 LD 5 -1 Int BE Pri
91943!#4 N7129 P4517 CAS 5 -1 N7128 0x20000db Int BE Pri
91944!#4 N7130 P4518 DWST 0 0x20000dc Int BE Pri
91945!#4 N7131 P4518 DWST 1 0x20000dd Int BE Pri
91946!#A N7130 N7131
91947!#4 N7132 P4519 LD 18 -1 Int BE Pri
91948!#4 N7133 P4520 DWST_BINIT 5 0x20000de Int BE Pri
91949!#4 N7134 P4521 MEMBAR
91950!#4 N7135 P4522 DWST 6 0x20000df Int BE Pri
91951!#4 N7136 P4522 DWST 7 0x20000e0 Int BE Pri
91952!#A N7135 N7136
91953!#4 N7137 P4523 MEMBAR
91954!#4 N7138 P4524 BSTC 15 0x41800088 FP BE Pri
91955!#4 N7139 P4524 BSTC 16 0x41800089 FP BE Pri
91956!#A N7138 N7139
91957!#4 N7140 P4524 BSTC 17 0x4180008a FP BE Pri
91958!#4 N7141 P4525 MEMBAR
91959!#4 N7142 P4526 LD 9 -1 Int BE Pri
91960!#4 N7143 P4527 MEMBAR
91961!#4 N7144 P4528 BST 3 0x4180008b FP BE Pri
91962!#4 N7145 P4528 BST 4 0x4180008c FP BE Pri
91963!#A N7144 N7145
91964!#4 N7146 P4528 BST 5 0x4180008d FP BE Pri
91965!#4 N7147 P4529 MEMBAR
91966!#4 N7148 P4530 LD 0 -1 Int BE Pri
91967!#4 N7149 P4531 MEMBAR
91968!#4 N7150 P4532 BLD 15 -1 FP BE Pri
91969!#4 N7151 P4532 BLD 16 -1 FP BE Pri
91970!#A N7150 N7151
91971!#4 N7152 P4532 BLD 17 -1 FP BE Pri
91972!#4 N7153 P4533 MEMBAR
91973!#4 N7154 P4534 DWLD 3 -1 Int BE Pri
91974!#4 N7155 P4534 DWLD 4 -1 Int BE Pri
91975!#A N7154 N7155
91976!#4 N7156 P4534 CASX 3 -1 N7154 0x20000e1 Int BE Pri
91977!#4 N7157 P4534 CASX 4 -1 N7155 0x20000e2 Int BE Pri
91978!#A N7156 N7157
91979!#4 N7158 P4535 LD 5 -1 Int BE Pri
91980!#4 N7159 P4535 CAS 5 -1 N7158 0x20000e3 Int BE Pri
91981!#4 N7160 P4536 LD 3 -1 Int BE Pri
91982!#4 N7161 P4537 ST 7 0x20000e4 Int BE Pri
91983!#4 N7162 P4538 LDD 15 -1 Int BE Pri
91984!#4 N7163 P4538 LDD 16 -1 Int BE Pri
91985!#A N7162 N7163
91986!#4 N7164 P4539 LDD 12 -1 Int LE Pri
91987!#4 N7165 P4539 LDD 13 -1 Int LE Pri
91988!#A N7164 N7165
91989!#4 N7166 P4540 MEMBAR
91990!#4 N7167 P4541 BLD 3 -1 FP BE Pri
91991!#4 N7168 P4541 BLD 4 -1 FP BE Pri
91992!#A N7167 N7168
91993!#4 N7169 P4541 BLD 5 -1 FP BE Pri
91994!#4 N7170 P4542 MEMBAR
91995!#4 N7171 P4543 DWLD 18 -1 Int BE Pri
91996!#4 N7172 P4543 DWLD 19 -1 Int BE Pri
91997!#A N7171 N7172
91998!#4 N7173 P4544 DWLD 3 -1 Int BE Pri
91999!#4 N7174 P4544 DWLD 4 -1 Int BE Pri
92000!#A N7173 N7174
92001!#4 N7175 P4544 CASX 3 -1 N7173 0x20000e5 Int BE Pri
92002!#4 N7176 P4544 CASX 4 -1 N7174 0x20000e6 Int BE Pri
92003!#A N7175 N7176
92004!#4 N7177 P4545 LD 9 -1 Int BE Pri
92005!#4 N7178 P4545 CAS 9 -1 N7177 0x20000e7 Int BE Pri
92006!#4 N7179 P4546 MEMBAR
92007!#4 N7180 P4547 BSTC 12 0x4180008e FP BE Pri
92008!#4 N7181 P4547 BSTC 13 0x4180008f FP BE Pri
92009!#A N7180 N7181
92010!#4 N7182 P4547 BSTC 14 0x41800090 FP BE Pri
92011!#4 N7183 P4548 MEMBAR
92012!#4 N7184 P4549 BLD 3 -1 FP BE Pri
92013!#4 N7185 P4549 BLD 4 -1 FP BE Pri
92014!#A N7184 N7185
92015!#4 N7186 P4549 BLD 5 -1 FP BE Pri
92016!#4 N7187 P4550 MEMBAR
92017!#4 N7188 P4551 LDD 15 -1 Int BE Pri
92018!#4 N7189 P4551 LDD 16 -1 Int BE Pri
92019!#A N7188 N7189
92020!#4 N7190 P4552 PREFETCH 2 Int BE Pri
92021!#4 N7191 P4553 MEMBAR
92022!#4 N7192 P4554 BST 6 0x41800091 FP BE Pri
92023!#4 N7193 P4554 BST 7 0x41800092 FP BE Pri
92024!#A N7192 N7193
92025!#4 N7194 P4554 BST 8 0x41800093 FP BE Pri
92026!#4 N7195 P4555 MEMBAR
92027!#4 N7196 P4556 LDD 9 -1 Int BE Pri
92028!#4 N7197 P4556 LDD 10 -1 Int BE Pri
92029!#A N7196 N7197
92030!#4 N7198 P4557 DWST_BINIT 14 0x20000e8 Int BE Pri
92031!#4 N7199 P4558 MEMBAR
92032!#4 N7200 P4559 LDD 11 -1 Int BE Pri
92033!#4 N7201 P4560 MEMBAR
92034!#4 N7202 P4561 BLD 3 -1 FP BE Pri
92035!#4 N7203 P4561 BLD 4 -1 FP BE Pri
92036!#A N7202 N7203
92037!#4 N7204 P4561 BLD 5 -1 FP BE Pri
92038!#4 N7205 P4562 MEMBAR
92039!#4 N7206 P4563 SWAP 14 0xffffffff 0x20000e9 Int BE Pri
92040!#4 N7207 P4564 MEMBAR
92041!#4 N7208 P4565 BSTC 21 0x41800094 FP BE Pri
92042!#4 N7209 P4565 BSTC 22 0x41800095 FP BE Pri
92043!#A N7208 N7209
92044!#4 N7210 P4565 BSTC 23 0x41800096 FP BE Pri
92045!#4 N7211 P4566 MEMBAR
92046!#4 N7212 P4567 LD 10 -1 Int BE Pri
92047!#4 N7213 P4567 CAS 10 -1 N7212 0x20000ea Int BE Pri
92048!#4 N7214 P4568 LD 7 -1 Int BE Pri
92049!#4 N7215 P4569 ST_BINIT 20 0x20000eb Int BE Pri
92050!#4 N7216 P4570 MEMBAR
92051!#4 N7217 P4571 ST_BINIT 19 0x20000ec Int BE Pri
92052!#4 N7218 P4572 MEMBAR
92053!#4 N7219 P4573 ST_BINIT 13 0x20000ed Int BE Pri
92054!#4 N7220 P4574 MEMBAR
92055!#4 N7221 P4575 LD 15 -1 Int BE Pri
92056!#4 N7222 P4575 CAS 15 -1 N7221 0x20000ee Int BE Pri
92057!#4 N7223 P4576 PREFETCH 7 Int BE Pri
92058!#4 N7224 P4577 LDD 6 -1 Int BE Pri
92059!#4 N7225 P4577 LDD 7 -1 Int BE Pri
92060!#A N7224 N7225
92061!#4 N7226 P4578 ST_BINIT 18 0x20000ef Int BE Pri
92062!#4 N7227 P4579 MEMBAR
92063!#4 N7228 P4580 REPLACEMENT 19 Int BE Pri
92064!#4 N7229 P4581 ST_BINIT 18 0x20000f0 Int BE Pri
92065!#4 N7230 P4582 MEMBAR
92066!#4 N7231 P4583 DWST_BINIT 11 0x20000f1 Int BE Pri
92067!#4 N7232 P4584 MEMBAR
92068!#4 N7233 P4585 BST 3 0x41800097 FP BE Pri
92069!#4 N7234 P4585 BST 4 0x41800098 FP BE Pri
92070!#A N7233 N7234
92071!#4 N7235 P4585 BST 5 0x41800099 FP BE Pri
92072!#4 N7236 P4586 MEMBAR
92073!#4 N7237 P4587 PREFETCH 4 Int BE Pri
92074!#4 N7238 P4588 DWLD 6 -1 Int LE Pri
92075!#4 N7239 P4588 DWLD 7 -1 Int LE Pri
92076!#A N7238 N7239
92077!#4 N7240 P4588 CASX 6 -1 N7238 0x20000f2 Int LE Pri
92078!#4 N7241 P4588 CASX 7 -1 N7239 0x20000f3 Int LE Pri
92079!#A N7240 N7241
92080!#4 N7242 P4589 SWAP 10 0xffffffff 0x20000f4 Int BE Pri
92081!#4 N7243 P4590 REPLACEMENT 1 Int BE Pri
92082!#4 N7244 P4591 ST 9 0x20000f5 Int BE Pri
92083!#4 N7245 P4592 MEMBAR
92084!#4 N7246 P4593 BST 9 0x4180009a FP BE Pri
92085!#4 N7247 P4593 BST 10 0x4180009b FP BE Pri
92086!#A N7246 N7247
92087!#4 N7248 P4593 BST 11 0x4180009c FP BE Pri
92088!#4 N7249 P4594 MEMBAR
92089!#4 N7250 P4595 DWST 18 0x20000f6 Int BE Pri
92090!#4 N7251 P4595 DWST 19 0x20000f7 Int BE Pri
92091!#A N7250 N7251
92092!#4 N7252 P4596 MEMBAR
92093!#4 N7253 P4597 BST 15 0x4180009d FP BE Pri
92094!#4 N7254 P4597 BST 16 0x4180009e FP BE Pri
92095!#A N7253 N7254
92096!#4 N7255 P4597 BST 17 0x4180009f FP BE Pri
92097!#4 N7256 P4598 MEMBAR
92098!#4 N7257 P4599 BLD 0 -1 FP BE Pri
92099!#4 N7258 P4599 BLD 1 -1 FP BE Pri
92100!#A N7257 N7258
92101!#4 N7259 P4599 BLD 2 -1 FP BE Pri
92102!#4 N7260 P4600 MEMBAR
92103!#4 N7261 P4601 PREFETCH 13 Int BE Pri
92104!#4 N7262 P4602 ST 6 0x20000f8 Int BE Pri
92105!#4 N7263 P4603 MEMBAR
92106!#4 N7264 P4604 BSTC 6 0x418000a0 FP BE Pri
92107!#4 N7265 P4604 BSTC 7 0x418000a1 FP BE Pri
92108!#A N7264 N7265
92109!#4 N7266 P4604 BSTC 8 0x418000a2 FP BE Pri
92110!#4 N7267 P4605 MEMBAR
92111!#4 N7268 P4606 BST 15 0x418000a3 FP BE Pri
92112!#4 N7269 P4606 BST 16 0x418000a4 FP BE Pri
92113!#A N7268 N7269
92114!#4 N7270 P4606 BST 17 0x418000a5 FP BE Pri
92115!#4 N7271 P4607 MEMBAR
92116!#4 N7272 P4608 BSTC 0 0x418000a6 FP BE Pri
92117!#4 N7273 P4608 BSTC 1 0x418000a7 FP BE Pri
92118!#A N7272 N7273
92119!#4 N7274 P4608 BSTC 2 0x418000a8 FP BE Pri
92120!#4 N7275 P4609 MEMBAR
92121!#4 N7276 P4610 ST_BINIT 7 0x20000f9 Int BE Pri
92122!#4 N7277 P4611 MEMBAR
92123!#4 N7278 P4612 DWST 20 0x20000fa Int BE Pri
92124!#4 N7279 P4613 LDD 6 -1 Int LE Pri
92125!#4 N7280 P4613 LDD 7 -1 Int LE Pri
92126!#A N7279 N7280
92127!#4 N7281 P4614 LD 8 -1 Int BE Pri
92128!#4 N7282 P4614 CAS 8 -1 N7281 0x20000fb Int BE Pri
92129!#4 N7283 P4615 LD 11 -1 Int BE Pri
92130!#4 N7284 P4615 CAS 11 -1 N7283 0x20000fc Int BE Pri
92131!#4 N7285 P4616 DWLD 2 -1 Int BE Pri
92132!#4 N7286 P4617 DWST 2 0x20000fd Int BE Pri
92133!#4 N7287 P4618 LDD 6 -1 Int BE Pri
92134!#4 N7288 P4618 LDD 7 -1 Int BE Pri
92135!#A N7287 N7288
92136!#4 N7289 P4619 ST_BINIT 6 0x20000fe Int BE Pri
92137!#4 N7290 P4620 MEMBAR
92138!#4 N7291 P4621 BSTC 15 0x418000a9 FP BE Pri
92139!#4 N7292 P4621 BSTC 16 0x418000aa FP BE Pri
92140!#A N7291 N7292
92141!#4 N7293 P4621 BSTC 17 0x418000ab FP BE Pri
92142!#4 N7294 P4622 MEMBAR
92143!#4 N7295 P4623 SWAP 11 0xffffffff 0x20000ff Int BE Pri
92144!#4 N7296 P4624 DWST_BINIT 6 0x2000100 Int BE Pri
92145!#4 N7297 P4624 DWST_BINIT 7 0x2000101 Int BE Pri
92146!#A N7296 N7297
92147!#4 N7298 P4625 MEMBAR
92148!#4 N7299 P4626 DWLD 18 -1 Int BE Pri
92149!#4 N7300 P4626 DWLD 19 -1 Int BE Pri
92150!#A N7299 N7300
92151!#4 N7301 P4626 CASX 18 -1 N7299 0x2000102 Int BE Pri
92152!#4 N7302 P4626 CASX 19 -1 N7300 0x2000103 Int BE Pri
92153!#A N7301 N7302
92154!#4 N7303 P4627 DWST_BINIT 6 0x2000104 Int BE Pri
92155!#4 N7304 P4627 DWST_BINIT 7 0x2000105 Int BE Pri
92156!#A N7303 N7304
92157!#4 N7305 P4628 MEMBAR
92158!#4 N7306 P4629 LD 4 -1 Int LE Pri
92159!#4 N7307 P4629 CAS 4 -1 N7306 0x2000106 Int LE Pri
92160!#4 N7308 P4630 LD 1 -1 Int BE Pri
92161!#4 N7309 P4631 MEMBAR
92162!#4 N7310 P4632 BLD 3 -1 FP BE Pri
92163!#4 N7311 P4632 BLD 4 -1 FP BE Pri
92164!#A N7310 N7311
92165!#4 N7312 P4632 BLD 5 -1 FP BE Pri
92166!#4 N7313 P4633 MEMBAR
92167!#4 N7314 P4634 DWST 12 0x418000ac FP BE Pri
92168!#4 N7315 P4634 DWST 13 0x418000ad FP BE Pri
92169!#A N7314 N7315
92170!#4 N7316 P4635 LDD 3 -1 Int BE Pri
92171!#4 N7317 P4635 LDD 4 -1 Int BE Pri
92172!#A N7316 N7317
92173!#4 N7318 P4636 DWLD 9 -1 FP BE Pri
92174!#4 N7319 P4636 DWLD 10 -1 FP BE Pri
92175!#A N7318 N7319
92176!#4 N7320 P4637 LD 15 -1 Int LE Pri
92177!#4 N7321 P4637 CAS 15 -1 N7320 0x2000107 Int LE Pri
92178!#4 N7322 P4638 ST_BINIT 9 0x2000108 Int BE Pri
92179!#4 N7323 P4639 MEMBAR
92180!#4 N7324 P4640 ST_BINIT 5 0x2000109 Int BE Pri
92181!#4 N7325 P4641 MEMBAR
92182!#4 N7326 P4642 BSTC 15 0x418000ae FP BE Pri
92183!#4 N7327 P4642 BSTC 16 0x418000af FP BE Pri
92184!#A N7326 N7327
92185!#4 N7328 P4642 BSTC 17 0x418000b0 FP BE Pri
92186!#4 N7329 P4643 MEMBAR
92187!#4 N7330 P4644 ST 0 0x200010a Int BE Pri
92188!#4 N7331 P4645 DWST_BINIT 0 0x200010b Int LE Pri
92189!#4 N7332 P4645 DWST_BINIT 1 0x200010c Int LE Pri
92190!#A N7331 N7332
92191!#4 N7333 P4646 MEMBAR
92192!#4 N7334 P4647 ST 3 0x200010d Int LE Pri
92193!#4 N7335 P4648 SWAP 14 0xffffffff 0x200010e Int BE Pri
92194!#4 N7336 P4649 ST_BINIT 0 0x200010f Int BE Pri
92195!#4 N7337 P4650 MEMBAR
92196!#4 N7338 P4651 PREFETCH 23 Int BE Pri
92197!#4 N7339 P4652 LD 23 -1 Int BE Pri
92198!#4 N7340 P4652 CAS 23 -1 N7339 0x2000110 Int BE Pri
92199!#4 N7341 P4653 LDD 17 -1 Int BE Pri
92200!#4 N7342 P4654 DWST_BINIT 20 0x2000111 Int BE Pri
92201!#4 N7343 P4655 MEMBAR
92202!#4 N7344 P4656 ST_BINIT 10 0x2000112 Int BE Pri
92203!#4 N7345 P4657 MEMBAR
92204!#4 N7346 P4658 DWLD 23 -1 Int BE Pri
92205!#4 N7347 P4659 DWST_BINIT 9 0x2000113 Int BE Pri
92206!#4 N7348 P4659 DWST_BINIT 10 0x2000114 Int BE Pri
92207!#A N7347 N7348
92208!#4 N7349 P4660 MEMBAR
92209!#4 N7350 P4661 BLD 12 -1 FP BE Pri
92210!#4 N7351 P4661 BLD 13 -1 FP BE Pri
92211!#A N7350 N7351
92212!#4 N7352 P4661 BLD 14 -1 FP BE Pri
92213!#4 N7353 P4662 MEMBAR
92214!#4 N7354 P4663 DWST 17 0x2000115 Int BE Pri
92215!#4 N7355 P4664 DWST 6 0x2000116 Int BE Pri
92216!#4 N7356 P4664 DWST 7 0x2000117 Int BE Pri
92217!#A N7355 N7356
92218!#4 N7357 P4665 DWLD 9 -1 Int BE Pri
92219!#4 N7358 P4665 DWLD 10 -1 Int BE Pri
92220!#A N7357 N7358
92221!#4 N7359 P4665 CASX 9 -1 N7357 0x2000118 Int BE Pri
92222!#4 N7360 P4665 CASX 10 -1 N7358 0x2000119 Int BE Pri
92223!#A N7359 N7360
92224!#4 N7361 P4666 LD 11 -1 Int BE Pri
92225!#4 N7362 P4667 LD 3 -1 Int BE Pri
92226!#4 N7363 P4667 CAS 3 -1 N7362 0x200011a Int BE Pri
92227!#4 N7364 P4668 ST 20 0x200011b Int BE Pri
92228!#4 N7365 P4669 MEMBAR
92229!#4 N7366 P4670 BSTC 3 0x418000b1 FP BE Pri
92230!#4 N7367 P4670 BSTC 4 0x418000b2 FP BE Pri
92231!#A N7366 N7367
92232!#4 N7368 P4670 BSTC 5 0x418000b3 FP BE Pri
92233!#4 N7369 P4671 MEMBAR
92234!#4 N7370 P4672 DWST 12 0x200011c Int BE Pri
92235!#4 N7371 P4672 DWST 13 0x200011d Int BE Pri
92236!#A N7370 N7371
92237!#4 N7372 P4673 LD 1 -1 Int BE Pri
92238!#4 N7373 P4674 LD 17 -1 Int BE Pri
92239!#4 N7374 P4675 DWLD 14 -1 Int BE Pri
92240!#4 N7375 P4676 LD 23 -1 Int BE Pri
92241!#4 N7376 P4676 CAS 23 -1 N7375 0x200011e Int BE Pri
92242!#4 N7377 P4677 DWST_BINIT 17 0x200011f Int BE Pri
92243!#4 N7378 P4678 MEMBAR
92244!#4 N7379 P4679 REPLACEMENT 11 Int BE Pri
92245!#4 N7380 P4680 LD 16 -1 Int BE Pri
92246!#4 N7381 P4681 DWST 2 0x2000120 Int BE Pri
92247!#4 N7382 P4682 MEMBAR
92248!#4 N7383 P4683 BSTC 21 0x418000b4 FP BE Pri
92249!#4 N7384 P4683 BSTC 22 0x418000b5 FP BE Pri
92250!#A N7383 N7384
92251!#4 N7385 P4683 BSTC 23 0x418000b6 FP BE Pri
92252!#4 N7386 P4684 MEMBAR
92253!#4 N7387 P4685 SWAP 13 0xffffffff 0x2000121 Int BE Pri
92254!#4 N7388 P4686 SWAP 9 0xffffffff 0x2000122 Int BE Pri
92255!#4 N7389 P4687 LD 12 -1 Int BE Pri
92256!#4 N7390 P4687 CAS 12 -1 N7389 0x2000123 Int BE Pri
92257!#4 N7391 P4688 MEMBAR
92258!#4 N7392 P4689 BLD 3 -1 FP BE Pri
92259!#4 N7393 P4689 BLD 4 -1 FP BE Pri
92260!#A N7392 N7393
92261!#4 N7394 P4689 BLD 5 -1 FP BE Pri
92262!#4 N7395 P4690 MEMBAR
92263!#4 N7396 P4691 ST_BINIT 21 0x2000124 Int BE Pri
92264!#4 N7397 P4692 MEMBAR
92265!#4 N7398 P4693 DWST 17 0x2000125 Int BE Pri
92266!#4 N7399 P4694 DWST 18 0x2000126 Int BE Pri
92267!#4 N7400 P4694 DWST 19 0x2000127 Int BE Pri
92268!#A N7399 N7400
92269!#4 N7401 P4695 PREFETCH 11 Int BE Pri
92270!#4 N7402 P4696 MEMBAR
92271!#4 N7403 P4697 BSTC 21 0x418000b7 FP BE Pri
92272!#4 N7404 P4697 BSTC 22 0x418000b8 FP BE Pri
92273!#A N7403 N7404
92274!#4 N7405 P4697 BSTC 23 0x418000b9 FP BE Pri
92275!#4 N7406 P4698 MEMBAR
92276!#4 N7407 P4699 ST 10 0x2000128 Int LE Pri
92277!#4 N7408 P4700 DWST_BINIT 14 0x2000129 Int BE Pri
92278!#4 N7409 P4701 MEMBAR
92279!#4 N7410 P4702 DWLD 15 -1 Int BE Pri
92280!#4 N7411 P4702 DWLD 16 -1 Int BE Pri
92281!#A N7410 N7411
92282!#4 N7412 P4702 CASX 15 -1 N7410 0x200012a Int BE Pri
92283!#4 N7413 P4702 CASX 16 -1 N7411 0x200012b Int BE Pri
92284!#A N7412 N7413
92285!#4 N7414 P4703 DWLD 21 -1 Int BE Pri
92286!#4 N7415 P4703 DWLD 22 -1 Int BE Pri
92287!#A N7414 N7415
92288!#4 N7416 P4704 DWST 18 0x200012c Int BE Pri
92289!#4 N7417 P4704 DWST 19 0x200012d Int BE Pri
92290!#A N7416 N7417
92291!#4 N7418 P4705 SWAP 12 0xffffffff 0x200012e Int BE Pri
92292!#4 N7419 P4706 REPLACEMENT 19 Int BE Pri
92293!#4 N7420 P4707 DWST 6 0x200012f Int BE Pri
92294!#4 N7421 P4707 DWST 7 0x2000130 Int BE Pri
92295!#A N7420 N7421
92296!#4 N7422 P4708 LDD 11 -1 Int BE Pri
92297!#4 N7423 P4709 DWLD 15 -1 Int BE Pri
92298!#4 N7424 P4709 DWLD 16 -1 Int BE Pri
92299!#A N7423 N7424
92300!#4 N7425 P4710 DWST_BINIT 9 0x2000131 Int LE Pri
92301!#4 N7426 P4710 DWST_BINIT 10 0x2000132 Int LE Pri
92302!#A N7425 N7426
92303!#4 N7427 P4711 MEMBAR
92304!#4 N7428 P4712 LDD 18 -1 Int BE Pri
92305!#4 N7429 P4712 LDD 19 -1 Int BE Pri
92306!#A N7428 N7429
92307!#4 N7430 P4713 LD 22 -1 Int BE Pri
92308!#4 N7431 P4713 CAS 22 -1 N7430 0x2000133 Int BE Pri
92309!#4 N7432 P4714 REPLACEMENT 0 Int BE Pri
92310!#4 N7433 P4715 MEMBAR
92311!#4 N7434 P4716 BST 18 0x418000ba FP BE Pri
92312!#4 N7435 P4716 BST 19 0x418000bb FP BE Pri
92313!#A N7434 N7435
92314!#4 N7436 P4716 BST 20 0x418000bc FP BE Pri
92315!#4 N7437 P4717 MEMBAR
92316!#4 N7438 P4718 PREFETCH 18 Int BE Pri
92317!#4 N7439 P4719 PREFETCH 13 Int BE Pri
92318!#4 N7440 P4720 DWST_BINIT 8 0x2000134 Int BE Pri
92319!#4 N7441 P4721 MEMBAR
92320!#4 N7442 P4722 DWLD 6 -1 Int BE Pri
92321!#4 N7443 P4722 DWLD 7 -1 Int BE Pri
92322!#A N7442 N7443
92323!#4 N7444 P4723 DWLD 14 -1,0x0 Int BE Pri
92324!#4 N7445 P4723 CASX 14 -1,0x0 N7444 0x2000135 Int BE Pri
92325!#4 N7446 P4724 ST 23 0x2000136 Int BE Pri
92326!#4 N7447 P4725 LD 19 -1 Int BE Pri
92327!#4 N7448 P4726 MEMBAR
92328!#4 N7449 P4727 BLD 3 -1 FP BE Pri
92329!#4 N7450 P4727 BLD 4 -1 FP BE Pri
92330!#A N7449 N7450
92331!#4 N7451 P4727 BLD 5 -1 FP BE Pri
92332!#4 N7452 P4728 MEMBAR
92333!#4 N7453 P4729 LD 5 -1 Int BE Pri
92334!#4 N7454 P4729 CAS 5 -1 N7453 0x2000137 Int BE Pri
92335!#4 N7455 P4730 LD 5 -1 Int BE Pri
92336!#4 N7456 P4730 CAS 5 -1 N7455 0x2000138 Int BE Pri
92337!#4 N7457 P4731 MEMBAR
92338!#4 N7458 P4732 BST 3 0x418000bd FP BE Pri
92339!#4 N7459 P4732 BST 4 0x418000be FP BE Pri
92340!#A N7458 N7459
92341!#4 N7460 P4732 BST 5 0x418000bf FP BE Pri
92342!#4 N7461 P4733 MEMBAR
92343!#4 N7462 P4734 LD 15 -1 Int BE Pri
92344!#4 N7463 P4735 MEMBAR
92345!#4 N7464 P4736 BST 0 0x418000c0 FP BE Pri
92346!#4 N7465 P4736 BST 1 0x418000c1 FP BE Pri
92347!#A N7464 N7465
92348!#4 N7466 P4736 BST 2 0x418000c2 FP BE Pri
92349!#4 N7467 P4737 MEMBAR
92350!#4 N7468 P4738 SWAP 6 0xffffffff 0x2000139 Int BE Pri
92351!#4 N7469 P4739 MEMBAR
92352!#4 N7470 P4740 BLD 21 -1 FP BE Pri
92353!#4 N7471 P4740 BLD 22 -1 FP BE Pri
92354!#A N7470 N7471
92355!#4 N7472 P4740 BLD 23 -1 FP BE Pri
92356!#4 N7473 P4741 MEMBAR
92357!#4 N7474 P4742 DWST 11 0x200013a Int BE Pri
92358!#4 N7475 P4743 LD 1 -1 Int BE Pri
92359!#4 N7476 P4743 CAS 1 -1 N7475 0x200013b Int BE Pri
92360!#4 N7477 P4744 MEMBAR
92361!#4 N7478 P4745 BSTC 3 0x418000c3 FP BE Pri
92362!#4 N7479 P4745 BSTC 4 0x418000c4 FP BE Pri
92363!#A N7478 N7479
92364!#4 N7480 P4745 BSTC 5 0x418000c5 FP BE Pri
92365!#4 N7481 P4746 MEMBAR
92366!#4 N7482 P4747 REPLACEMENT 0 Int BE Pri
92367!#4 N7483 P4748 SWAP 8 0xffffffff 0x200013c Int BE Pri
92368!#4 N7484 P4749 LD 12 -1 Int BE Pri
92369!#4 N7485 P4750 ST 16 0x200013d Int BE Pri
92370!#4 N7486 P4751 DWST 18 0x418000c6 FP BE Pri
92371!#4 N7487 P4751 DWST 19 0x418000c7 FP BE Pri
92372!#A N7486 N7487
92373!#4 N7488 P4752 DWLD 20 -1 Int BE Pri
92374!#4 N7489 P4753 DWLD 18 -1 Int BE Pri
92375!#4 N7490 P4753 DWLD 19 -1 Int BE Pri
92376!#A N7489 N7490
92377!#4 N7491 P4754 LD 19 -1 Int BE Pri
92378!#4 N7492 P4754 CAS 19 -1 N7491 0x200013e Int BE Pri
92379!#4 N7493 P4755 DWST_BINIT 12 0x200013f Int BE Pri
92380!#4 N7494 P4755 DWST_BINIT 13 0x2000140 Int BE Pri
92381!#A N7493 N7494
92382!#4 N7495 P4756 MEMBAR
92383!#4 N7496 P4757 LD 18 -1 Int BE Pri
92384!#4 N7497 P4758 LDD 2 -1 Int BE Pri
92385!#4 N7498 P4759 LD 5 -1 Int LE Pri
92386!#4 N7499 P4759 CAS 5 -1 N7498 0x2000141 Int LE Pri
92387!#4 N7500 P4760 LDD 14 -1 Int LE Pri
92388!#4 N7501 P4761 LD 0 -1 Int BE Pri
92389!#4 N7502 P4761 CAS 0 -1 N7501 0x2000142 Int BE Pri
92390!#4 N7503 P4762 DWLD 8 -1 Int LE Pri
92391!#4 N7504 P4763 LDD 3 -1 Int BE Pri
92392!#4 N7505 P4763 LDD 4 -1 Int BE Pri
92393!#A N7504 N7505
92394!#4 N7506 P4764 DWLD 6 -1 Int BE Pri
92395!#4 N7507 P4764 DWLD 7 -1 Int BE Pri
92396!#A N7506 N7507
92397!#4 N7508 P4764 CASX 6 -1 N7506 0x2000143 Int BE Pri
92398!#4 N7509 P4764 CASX 7 -1 N7507 0x2000144 Int BE Pri
92399!#A N7508 N7509
92400!#4 N7510 P4765 LDD 8 -1 Int BE Pri
92401!#4 N7511 P4766 DWST 12 0x418000c8 FP BE Pri
92402!#4 N7512 P4766 DWST 13 0x418000c9 FP BE Pri
92403!#A N7511 N7512
92404!#4 N7513 P4767 ST_BINIT 1 0x2000145 Int BE Pri
92405!#4 N7514 P4768 MEMBAR
92406!#4 N7515 P4769 SWAP 3 0xffffffff 0x2000146 Int BE Pri
92407!#4 N7516 P4770 ST 21 0x2000147 Int BE Pri
92408!#4 N7517 P4771 DWST_BINIT 12 0x2000148 Int BE Pri
92409!#4 N7518 P4771 DWST_BINIT 13 0x2000149 Int BE Pri
92410!#A N7517 N7518
92411!#4 N7519 P4772 MEMBAR
92412!#4 N7520 P4773 ST_BINIT 2 0x200014a Int BE Pri
92413!#4 N7521 P4774 MEMBAR
92414!#4 N7522 P4775 DWST_BINIT 18 0x200014b Int LE Pri
92415!#4 N7523 P4775 DWST_BINIT 19 0x200014c Int LE Pri
92416!#A N7522 N7523
92417!#4 N7524 P4776 MEMBAR
92418!#4 N7525 P4777 DWST_BINIT 3 0x200014d Int BE Pri
92419!#4 N7526 P4777 DWST_BINIT 4 0x200014e Int BE Pri
92420!#A N7525 N7526
92421!#4 N7527 P4778 MEMBAR
92422!#4 N7528 P4779 SWAP 1 0xffffffff 0x200014f Int BE Pri
92423!#4 N7529 P4780 LD 18 -1 Int BE Pri
92424!#4 N7530 P4780 CAS 18 -1 N7529 0x2000150 Int BE Pri
92425!#4 N7531 P4781 LDD 17 -1 Int BE Pri
92426!#4 N7532 P4782 DWST 3 0x2000151 Int BE Pri
92427!#4 N7533 P4782 DWST 4 0x2000152 Int BE Pri
92428!#A N7532 N7533
92429!#4 N7534 P4783 MEMBAR
92430!#4 N7535 P4784 BST 18 0x418000ca FP BE Pri
92431!#4 N7536 P4784 BST 19 0x418000cb FP BE Pri
92432!#A N7535 N7536
92433!#4 N7537 P4784 BST 20 0x418000cc FP BE Pri
92434!#4 N7538 P4785 MEMBAR
92435!#4 N7539 P4786 BSTC 0 0x418000cd FP BE Pri
92436!#4 N7540 P4786 BSTC 1 0x418000ce FP BE Pri
92437!#A N7539 N7540
92438!#4 N7541 P4786 BSTC 2 0x418000cf FP BE Pri
92439!#4 N7542 P4787 MEMBAR
92440!#4 N7543 P4788 DWLD 8 -1,0x0 Int LE Pri
92441!#4 N7544 P4788 CASX 8 -1,0x0 N7543 0x2000153 Int LE Pri
92442!#4 N7545 P4789 ST 4 0x418000d0 FP BE Pri
92443!#4 N7546 P4790 DWST 18 0x2000154 Int BE Pri
92444!#4 N7547 P4790 DWST 19 0x2000155 Int BE Pri
92445!#A N7546 N7547
92446!#4 N7548 P4791 REPLACEMENT 18 Int BE Pri
92447!#4 N7549 P4792 DWST_BINIT 15 0x2000156 Int BE Pri
92448!#4 N7550 P4792 DWST_BINIT 16 0x2000157 Int BE Pri
92449!#A N7549 N7550
92450!#4 N7551 P4793 MEMBAR
92451!#4 N7552 P4794 SWAP 8 0xffffffff 0x2000158 Int BE Pri
92452!#4 N7553 P4795 ST 23 0x2000159 Int BE Pri
92453!#4 N7554 P4796 LDD 3 -1 Int BE Pri
92454!#4 N7555 P4796 LDD 4 -1 Int BE Pri
92455!#A N7554 N7555
92456!#4 N7556 P4797 LDD 9 -1 Int BE Pri
92457!#4 N7557 P4797 LDD 10 -1 Int BE Pri
92458!#A N7556 N7557
92459!#4 N7558 P4798 PREFETCH 4 Int BE Pri
92460!#4 N7559 P4799 SWAP 11 0xffffffff 0x200015a Int BE Pri
92461!#4 N7560 P4800 LD 8 -1 Int BE Pri
92462!#4 N7561 P4800 CAS 8 -1 N7560 0x200015b Int BE Pri
92463!#4 N7562 P4801 ST 20 0x418000d1 FP BE Pri
92464!#4 N7563 P4802 LD 22 -1 Int BE Pri
92465!#4 N7564 P4802 CAS 22 -1 N7563 0x200015c Int BE Pri
92466!#4 N7565 P4803 ST 10 0x200015d Int BE Pri
92467!#4 N7566 P4804 DWLD 3 -1 Int BE Pri
92468!#4 N7567 P4804 DWLD 4 -1 Int BE Pri
92469!#A N7566 N7567
92470!#4 N7568 P4805 LD 7 -1 Int BE Pri
92471!#4 N7569 P4805 CAS 7 -1 N7568 0x200015e Int BE Pri
92472!#4 N7570 P4806 DWST_BINIT 12 0x200015f Int BE Pri
92473!#4 N7571 P4806 DWST_BINIT 13 0x2000160 Int BE Pri
92474!#A N7570 N7571
92475!#4 N7572 P4807 MEMBAR
92476!#4 N7573 P4808 SWAP 18 0xffffffff 0x2000161 Int BE Pri
92477!#4 N7574 P4809 ST 5 0x418000d2 FP BE Pri
92478!#4 N7575 P4810 LD 9 -1 FP BE Pri
92479!#4 N7576 P4811 MEMBAR
92480!#4 N7577 P4812 BLD 6 -1 FP BE Pri
92481!#4 N7578 P4812 BLD 7 -1 FP BE Pri
92482!#A N7577 N7578
92483!#4 N7579 P4812 BLD 8 -1 FP BE Pri
92484!#4 N7580 P4813 MEMBAR
92485!#4 N7581 P4814 ST 14 0x418000d3 FP BE Pri
92486!#4 N7582 P4815 MEMBAR
92487!#4 N7583 P4816 BLD 3 -1 FP BE Pri
92488!#4 N7584 P4816 BLD 4 -1 FP BE Pri
92489!#A N7583 N7584
92490!#4 N7585 P4816 BLD 5 -1 FP BE Pri
92491!#4 N7586 P4817 MEMBAR
92492!#4 N7587 P4818 DWST 6 0x2000162 Int LE Pri
92493!#4 N7588 P4818 DWST 7 0x2000163 Int LE Pri
92494!#A N7587 N7588
92495!#4 N7589 P4819 ST 21 0x418000d4 FP BE Pri
92496!#4 N7590 P4820 LD 6 -1 Int BE Pri
92497!#4 N7591 P4820 CAS 6 -1 N7590 0x2000164 Int BE Pri
92498!#4 N7592 P4821 LDD 17 -1 Int BE Pri
92499!#4 N7593 P4822 DWLD 8 -1 Int BE Pri
92500!#4 N7594 P4823 ST 8 0x2000165 Int BE Pri
92501!#4 N7595 P4824 LD 21 -1 Int BE Pri
92502!#4 N7596 P4825 LD 22 -1 Int BE Pri
92503!#4 N7597 P4825 CAS 22 -1 N7596 0x2000166 Int BE Pri
92504!#4 N7598 P4826 LDD 14 -1 Int BE Pri
92505!#4 N7599 P4827 DWST 15 0x2000167 Int BE Pri
92506!#4 N7600 P4827 DWST 16 0x2000168 Int BE Pri
92507!#A N7599 N7600
92508!#4 N7601 P4828 DWLD 15 -1 Int BE Pri
92509!#4 N7602 P4828 DWLD 16 -1 Int BE Pri
92510!#A N7601 N7602
92511!#4 N7603 P4829 DWST 14 0x2000169 Int BE Pri
92512!#4 N7604 P4830 DWST_BINIT 17 0x200016a Int LE Pri
92513!#4 N7605 P4831 MEMBAR
92514!#4 N7606 P4832 DWST_BINIT 9 0x200016b Int BE Pri
92515!#4 N7607 P4832 DWST_BINIT 10 0x200016c Int BE Pri
92516!#A N7606 N7607
92517!#4 N7608 P4833 MEMBAR
92518!#4 N7609 P4834 DWST 15 0x418000d5 FP BE Pri
92519!#4 N7610 P4834 DWST 16 0x418000d6 FP BE Pri
92520!#A N7609 N7610
92521!#4 N7611 P4835 DWST 20 0x200016d Int BE Pri
92522!#4 N7612 P4836 PREFETCH 20 Int BE Pri
92523!#4 N7613 P4837 REPLACEMENT 17 Int BE Pri
92524!#4 N7614 P4838 LD 5 -1 Int BE Pri
92525!#4 N7615 P4839 ST_BINIT 17 0x200016e Int BE Pri
92526!#4 N7616 P4840 MEMBAR
92527!#4 N7617 P4841 DWST 14 0x200016f Int BE Pri
92528!#4 N7618 P4842 ST 10 0x2000170 Int BE Pri
92529!#4 N7619 P4843 DWLD 18 -1 Int BE Pri
92530!#4 N7620 P4843 DWLD 19 -1 Int BE Pri
92531!#A N7619 N7620
92532!#4 N7621 P4844 ST 7 0x418000d7 FP BE Pri
92533!#4 N7622 P4845 DWLD 17 -1,0x0 Int BE Pri
92534!#4 N7623 P4845 CASX 17 -1,0x0 N7622 0x2000171 Int BE Pri
92535!#4 N7624 P4846 SWAP 2 0xffffffff 0x2000172 Int BE Pri
92536!#4 N7625 P4847 REPLACEMENT 9 Int BE Pri
92537!#4 N7626 P4848 DWST_BINIT 9 0x2000173 Int BE Pri
92538!#4 N7627 P4848 DWST_BINIT 10 0x2000174 Int BE Pri
92539!#A N7626 N7627
92540!#4 N7628 P4849 MEMBAR
92541!#4 N7629 P4850 DWST 20 0x2000175 Int BE Pri
92542!#4 N7630 P4851 ST 19 0x418000d8 FP BE Pri
92543!#4 N7631 P4852 DWST 3 0x2000176 Int BE Pri
92544!#4 N7632 P4852 DWST 4 0x2000177 Int BE Pri
92545!#A N7631 N7632
92546!#4 N7633 P4853 MEMBAR
92547!#4 N7634 P4854 BSTC 0 0x418000d9 FP BE Pri
92548!#4 N7635 P4854 BSTC 1 0x418000da FP BE Pri
92549!#A N7634 N7635
92550!#4 N7636 P4854 BSTC 2 0x418000db FP BE Pri
92551!#4 N7637 P4855 MEMBAR
92552!#4 N7638 P4856 DWLD 12 -1 Int BE Pri
92553!#4 N7639 P4856 DWLD 13 -1 Int BE Pri
92554!#A N7638 N7639
92555!#4 N7640 P4857 MEMBAR
92556!#4 N7641 P4858 BLD 3 -1 FP BE Pri
92557!#4 N7642 P4858 BLD 4 -1 FP BE Pri
92558!#A N7641 N7642
92559!#4 N7643 P4858 BLD 5 -1 FP BE Pri
92560!#4 N7644 P4859 MEMBAR
92561!#4 N7645 P4860 ST 17 0x2000178 Int BE Pri
92562!#4 N7646 P4861 LD 22 -1 Int BE Pri
92563!#4 N7647 P4861 CAS 22 -1 N7646 0x2000179 Int BE Pri
92564!#4 N7648 P4862 MEMBAR
92565!#4 N7649 P4863 BST 21 0x418000dc FP BE Pri
92566!#4 N7650 P4863 BST 22 0x418000dd FP BE Pri
92567!#A N7649 N7650
92568!#4 N7651 P4863 BST 23 0x418000de FP BE Pri
92569!#4 N7652 P4864 MEMBAR
92570!#4 N7653 P4865 SWAP 12 0xffffffff 0x200017a Int BE Pri
92571!#4 N7654 P4866 LD 4 -1 Int BE Pri
92572!#4 N7655 P4867 DWST_BINIT 15 0x200017b Int BE Pri
92573!#4 N7656 P4867 DWST_BINIT 16 0x200017c Int BE Pri
92574!#A N7655 N7656
92575!#4 N7657 P4868 MEMBAR
92576!#4 N7658 P4869 DWLD 2 -1,0x0 Int BE Pri
92577!#4 N7659 P4869 CASX 2 -1,0x0 N7658 0x200017d Int BE Pri
92578!#4 N7660 P4870 MEMBAR
92579!#4 N7661 P4871 BLD 12 -1 FP BE Pri
92580!#4 N7662 P4871 BLD 13 -1 FP BE Pri
92581!#A N7661 N7662
92582!#4 N7663 P4871 BLD 14 -1 FP BE Pri
92583!#4 N7664 P4872 MEMBAR
92584!#4 N7665 P4873 BLD 9 -1 FP BE Pri
92585!#4 N7666 P4873 BLD 10 -1 FP BE Pri
92586!#A N7665 N7666
92587!#4 N7667 P4873 BLD 11 -1 FP BE Pri
92588!#4 N7668 P4874 MEMBAR
92589!#4 N7669 P4875 PREFETCH 11 Int BE Pri
92590!#4 N7670 P4876 LDD 12 -1 Int BE Pri
92591!#4 N7671 P4876 LDD 13 -1 Int BE Pri
92592!#A N7670 N7671
92593!#4 N7672 P4877 MEMBAR
92594!#4 N7673 P4878 BST 6 0x418000df FP BE Pri
92595!#4 N7674 P4878 BST 7 0x418000e0 FP BE Pri
92596!#A N7673 N7674
92597!#4 N7675 P4878 BST 8 0x418000e1 FP BE Pri
92598!#4 N7676 P4879 MEMBAR
92599!#4 N7677 P4880 ST 14 0x200017e Int BE Pri
92600!#4 N7678 P4881 DWLD 5 -1,0x0 Int BE Pri
92601!#4 N7679 P4881 CASX 5 -1,0x0 N7678 0x200017f Int BE Pri
92602!#4 N7680 P4882 SWAP 16 0xffffffff 0x2000180 Int BE Pri
92603!#4 N7681 P4883 DWST_BINIT 6 0x2000181 Int LE Pri
92604!#4 N7682 P4883 DWST_BINIT 7 0x2000182 Int LE Pri
92605!#A N7681 N7682
92606!#4 N7683 P4884 MEMBAR
92607!#4 N7684 P4885 BSTC 6 0x418000e2 FP BE Pri
92608!#4 N7685 P4885 BSTC 7 0x418000e3 FP BE Pri
92609!#A N7684 N7685
92610!#4 N7686 P4885 BSTC 8 0x418000e4 FP BE Pri
92611!#4 N7687 P4886 MEMBAR
92612!#4 N7688 P4887 LD 17 -1 Int BE Pri
92613!#4 N7689 P4887 CAS 17 -1 N7688 0x2000183 Int BE Pri
92614!#4 N7690 P4888 ST_BINIT 22 0x2000184 Int BE Pri
92615!#4 N7691 P4889 MEMBAR
92616!#4 N7692 P4890 ST_BINIT 23 0x2000185 Int BE Pri
92617!#4 N7693 P4891 MEMBAR
92618!#4 N7694 P4892 BSTC 15 0x418000e5 FP BE Pri
92619!#4 N7695 P4892 BSTC 16 0x418000e6 FP BE Pri
92620!#A N7694 N7695
92621!#4 N7696 P4892 BSTC 17 0x418000e7 FP BE Pri
92622!#4 N7697 P4893 MEMBAR
92623!#4 N7698 P4894 SWAP 3 0xffffffff 0x2000186 Int BE Pri
92624!#4 N7699 P4895 MEMBAR
92625!#4 N7700 P4896 BST 21 0x418000e8 FP BE Pri
92626!#4 N7701 P4896 BST 22 0x418000e9 FP BE Pri
92627!#A N7700 N7701
92628!#4 N7702 P4896 BST 23 0x418000ea FP BE Pri
92629!#4 N7703 P4897 MEMBAR
92630!#4 N7704 P4898 DWLD 23 -1 Int BE Pri
92631!#4 N7705 P4899 MEMBAR
92632!#4 N7706 P4900 BST 12 0x418000eb FP BE Pri
92633!#4 N7707 P4900 BST 13 0x418000ec FP BE Pri
92634!#A N7706 N7707
92635!#4 N7708 P4900 BST 14 0x418000ed FP BE Pri
92636!#4 N7709 P4901 MEMBAR
92637!#4 N7710 P4902 DWLD 5 -1 Int BE Pri
92638!#4 N7711 P4903 SWAP 3 0xffffffff 0x2000187 Int BE Pri
92639!#4 N7712 P4904 MEMBAR
92640!#4 N7713 P4905 BST 3 0x418000ee FP BE Pri
92641!#4 N7714 P4905 BST 4 0x418000ef FP BE Pri
92642!#A N7713 N7714
92643!#4 N7715 P4905 BST 5 0x418000f0 FP BE Pri
92644!#4 N7716 P4906 MEMBAR
92645!#4 N7717 P4907 LD 17 -1 Int BE Pri
92646!#4 N7718 P4908 LD 4 -1 Int BE Pri
92647!#4 N7719 P4908 CAS 4 -1 N7718 0x2000188 Int BE Pri
92648!#4 N7720 P4909 DWST 21 0x2000189 Int BE Pri
92649!#4 N7721 P4909 DWST 22 0x200018a Int BE Pri
92650!#A N7720 N7721
92651!#4 N7722 P4910 MEMBAR
92652!#4 N7723 P4911 BST 15 0x418000f1 FP BE Pri
92653!#4 N7724 P4911 BST 16 0x418000f2 FP BE Pri
92654!#A N7723 N7724
92655!#4 N7725 P4911 BST 17 0x418000f3 FP BE Pri
92656!#4 N7726 P4912 MEMBAR
92657!#4 N7727 P4913 ST_BINIT 18 0x200018b Int BE Pri
92658!#4 N7728 P4914 MEMBAR
92659!#4 N7729 P4915 REPLACEMENT 10 Int BE Pri
92660!#4 N7730 P4916 DWLD 5 -1,0x0 Int BE Pri
92661!#4 N7731 P4916 CASX 5 -1,0x0 N7730 0x200018c Int BE Pri
92662!#4 N7732 P4917 ST 11 0x200018d Int BE Pri
92663!#4 N7733 P4918 PREFETCH 11 Int BE Pri
92664!#4 N7734 P4919 SWAP 7 0xffffffff 0x200018e Int BE Pri
92665!#4 N7735 P4920 DWST 21 0x200018f Int BE Pri
92666!#4 N7736 P4920 DWST 22 0x2000190 Int BE Pri
92667!#A N7735 N7736
92668!#4 N7737 P4921 LDD 0 -1 Int BE Pri
92669!#4 N7738 P4921 LDD 1 -1 Int BE Pri
92670!#A N7737 N7738
92671!#4 N7739 P4922 LDD 0 -1 Int BE Pri
92672!#4 N7740 P4922 LDD 1 -1 Int BE Pri
92673!#A N7739 N7740
92674!#4 N7741 P4923 ST 0 0x418000f4 FP BE Pri
92675!#4 N7742 P4924 LD 19 -1 Int BE Pri
92676!#4 N7743 P4925 SWAP 5 0xffffffff 0x2000191 Int BE Pri
92677!#4 N7744 P4926 ST 1 0x2000192 Int BE Pri
92678!#4 N7745 P4927 LD 10 -1 FP BE Pri
92679!#4 N7746 P4928 REPLACEMENT 7 Int BE Pri
92680!#4 N7747 P4929 PREFETCH 7 Int BE Pri
92681!#4 N7748 P4930 MEMBAR
92682!#4 N7749 P4931 BST 0 0x418000f5 FP BE Pri
92683!#4 N7750 P4931 BST 1 0x418000f6 FP BE Pri
92684!#A N7749 N7750
92685!#4 N7751 P4931 BST 2 0x418000f7 FP BE Pri
92686!#4 N7752 P4932 MEMBAR
92687!#4 N7753 P4933 ST 0 0x2000193 Int BE Pri
92688!#4 N7754 P4934 LD 18 -1 Int BE Pri
92689!#4 N7755 P4935 LDD 5 -1 Int BE Pri
92690!#4 N7756 P4936 ST_BINIT 6 0x2000194 Int LE Pri
92691!#4 N7757 P4937 MEMBAR
92692!#4 N7758 P4938 ST 20 0x2000195 Int BE Pri
92693!#4 N7759 P4939 PREFETCH 12 Int LE Pri
92694!#4 N7760 P4940 DWST 3 0x2000196 Int BE Pri
92695!#4 N7761 P4940 DWST 4 0x2000197 Int BE Pri
92696!#A N7760 N7761
92697!#4 N7762 P4941 DWLD 17 -1,0x0 Int BE Pri
92698!#4 N7763 P4941 CASX 17 -1,0x0 N7762 0x2000198 Int BE Pri
92699!#4 N7764 P4942 REPLACEMENT 9 Int BE Pri
92700!#4 N7765 P4943 LDD 21 -1 Int BE Pri
92701!#4 N7766 P4943 LDD 22 -1 Int BE Pri
92702!#A N7765 N7766
92703!#4 N7767 P4944 ST_BINIT 5 0x2000199 Int BE Pri
92704!#4 N7768 P4945 MEMBAR
92705!#4 N7769 P4946 BLD 9 -1 FP BE Pri
92706!#4 N7770 P4946 BLD 10 -1 FP BE Pri
92707!#A N7769 N7770
92708!#4 N7771 P4946 BLD 11 -1 FP BE Pri
92709!#4 N7772 P4947 MEMBAR
92710!#4 N7773 P4948 DWLD 21 -1 Int BE Pri
92711!#4 N7774 P4948 DWLD 22 -1 Int BE Pri
92712!#A N7773 N7774
92713!#4 N7775 P4949 SWAP 8 0xffffffff 0x200019a Int BE Pri
92714!#4 N7776 P4950 DWLD 15 -1 Int BE Pri
92715!#4 N7777 P4950 DWLD 16 -1 Int BE Pri
92716!#A N7776 N7777
92717!#4 N7778 P4951 LDD 6 -1 Int LE Pri
92718!#4 N7779 P4951 LDD 7 -1 Int LE Pri
92719!#A N7778 N7779
92720!#4 N7780 P4952 DWST_BINIT 12 0x200019b Int BE Pri
92721!#4 N7781 P4952 DWST_BINIT 13 0x200019c Int BE Pri
92722!#A N7780 N7781
92723!#4 N7782 P4953 MEMBAR
92724!#4 N7783 P4954 LDD 5 -1 Int BE Pri
92725!#4 N7784 P4955 DWST_BINIT 20 0x200019d Int BE Pri
92726!#4 N7785 P4956 MEMBAR
92727!#4 N7786 P4957 ST_BINIT 7 0x200019e Int BE Pri
92728!#4 N7787 P4958 MEMBAR
92729!#4 N7788 P4959 DWST 11 0x200019f Int BE Pri
92730!#4 N7789 P4960 SWAP 14 0xffffffff 0x20001a0 Int BE Pri
92731!#4 N7790 P4961 MEMBAR
92732!#4 N7791 P4962 BLD 9 -1 FP BE Pri
92733!#4 N7792 P4962 BLD 10 -1 FP BE Pri
92734!#A N7791 N7792
92735!#4 N7793 P4962 BLD 11 -1 FP BE Pri
92736!#4 N7794 P4963 MEMBAR
92737!#4 N7795 P4964 LD 2 -1 Int BE Pri
92738!#4 N7796 P4965 LD 0 -1 Int BE Pri
92739!#4 N7797 P4966 LDD 0 -1 Int BE Pri
92740!#4 N7798 P4966 LDD 1 -1 Int BE Pri
92741!#A N7797 N7798
92742!#4 N7799 P4967 MEMBAR
92743!#4 N7800 P4968 BSTC 9 0x418000f8 FP BE Pri
92744!#4 N7801 P4968 BSTC 10 0x418000f9 FP BE Pri
92745!#A N7800 N7801
92746!#4 N7802 P4968 BSTC 11 0x418000fa FP BE Pri
92747!#4 N7803 P4969 MEMBAR
92748!#4 N7804 P4970 BST 12 0x418000fb FP BE Pri
92749!#4 N7805 P4970 BST 13 0x418000fc FP BE Pri
92750!#A N7804 N7805
92751!#4 N7806 P4970 BST 14 0x418000fd FP BE Pri
92752!#4 N7807 P4971 MEMBAR
92753!#4 N7808 P4972 DWST_BINIT 0 0x20001a1 Int BE Pri
92754!#4 N7809 P4972 DWST_BINIT 1 0x20001a2 Int BE Pri
92755!#A N7808 N7809
92756!#4 N7810 P4973 MEMBAR
92757!#4 N7811 P4974 BSTC 3 0x418000fe FP BE Pri
92758!#4 N7812 P4974 BSTC 4 0x418000ff FP BE Pri
92759!#A N7811 N7812
92760!#4 N7813 P4974 BSTC 5 0x41800100 FP BE Pri
92761!#4 N7814 P4975 MEMBAR
92762!#4 N7815 P4976 BSTC 21 0x41800101 FP BE Pri
92763!#4 N7816 P4976 BSTC 22 0x41800102 FP BE Pri
92764!#A N7815 N7816
92765!#4 N7817 P4976 BSTC 23 0x41800103 FP BE Pri
92766!#4 N7818 P4977 MEMBAR
92767!#4 N7819 P4978 LD 12 -1 Int BE Pri
92768!#4 N7820 P4979 REPLACEMENT 18 Int BE Pri
92769!#4 N7821 P4980 ST 1 0x20001a3 Int BE Pri
92770!#4 N7822 P4981 MEMBAR
92771!#4 N7823 P4982 BLD 9 -1 FP BE Pri
92772!#4 N7824 P4982 BLD 10 -1 FP BE Pri
92773!#A N7823 N7824
92774!#4 N7825 P4982 BLD 11 -1 FP BE Pri
92775!#4 N7826 P4983 MEMBAR
92776!#4 N7827 P4984 PREFETCH 9 Int BE Pri
92777!#4 N7828 P4985 DWLD 6 -1 Int BE Pri
92778!#4 N7829 P4985 DWLD 7 -1 Int BE Pri
92779!#A N7828 N7829
92780!#4 N7830 P4985 CASX 6 -1 N7828 0x20001a4 Int BE Pri
92781!#4 N7831 P4985 CASX 7 -1 N7829 0x20001a5 Int BE Pri
92782!#A N7830 N7831
92783!#4 N7832 P4986 LD 10 -1 FP BE Pri
92784!#4 N7833 P4987 ST_BINIT 12 0x20001a6 Int BE Pri
92785!#4 N7834 P4988 MEMBAR
92786!#4 N7835 P4989 LD 14 -1 Int BE Pri
92787!#4 N7836 P4989 CAS 14 -1 N7835 0x20001a7 Int BE Pri
92788!#4 N7837 P4990 LDD 12 -1 Int BE Pri
92789!#4 N7838 P4990 LDD 13 -1 Int BE Pri
92790!#A N7837 N7838
92791!#4 N7839 P4991 SWAP 2 0xffffffff 0x20001a8 Int BE Pri
92792!#4 N7840 P4992 SWAP 8 0xffffffff 0x20001a9 Int BE Pri
92793!#4 N7841 P4993 LD 18 -1 Int BE Pri
92794!#4 N7842 P4993 CAS 18 -1 N7841 0x20001aa Int BE Pri
92795!#4 N7843 P4994 LD 3 -1 Int BE Pri
92796!#4 N7844 P4994 CAS 3 -1 N7843 0x20001ab Int BE Pri
92797!#4 N7845 P4995 ST_BINIT 2 0x20001ac Int BE Pri
92798!#4 N7846 P4996 MEMBAR
92799!#4 N7847 P4997 DWST_BINIT 0 0x20001ad Int BE Pri
92800!#4 N7848 P4997 DWST_BINIT 1 0x20001ae Int BE Pri
92801!#A N7847 N7848
92802!#4 N7849 P4998 MEMBAR
92803!#4 N7850 P4999 PREFETCH 17 Int BE Pri
92804!#4 N7851 P5000 LD 14 -1 Int BE Pri
92805!#4 N7852 P5000 CAS 14 -1 N7851 0x20001af Int BE Pri
92806!#4 N7853 P5001 MEMBAR
92807!#4 N7854 P5002 BLD 12 -1 FP BE Pri
92808!#4 N7855 P5002 BLD 13 -1 FP BE Pri
92809!#A N7854 N7855
92810!#4 N7856 P5002 BLD 14 -1 FP BE Pri
92811!#4 N7857 P5003 MEMBAR
92812!#4 N7858 P5004 LD 0 -1 Int BE Pri
92813!#4 N7859 P5005 MEMBAR
92814!#4 N7860 P5006 BLD 6 -1 FP BE Pri
92815!#4 N7861 P5006 BLD 7 -1 FP BE Pri
92816!#A N7860 N7861
92817!#4 N7862 P5006 BLD 8 -1 FP BE Pri
92818!#4 N7863 P5007 MEMBAR
92819!#4 N7864 P5008 DWST 0 0x20001b0 Int BE Pri
92820!#4 N7865 P5008 DWST 1 0x20001b1 Int BE Pri
92821!#A N7864 N7865
92822!#4 N7866 P5009 MEMBAR
92823!#4 N7867 P5010 BST 18 0x41800104 FP BE Pri
92824!#4 N7868 P5010 BST 19 0x41800105 FP BE Pri
92825!#A N7867 N7868
92826!#4 N7869 P5010 BST 20 0x41800106 FP BE Pri
92827!#4 N7870 P5011 MEMBAR
92828!#4 N7871 P5012 LD 3 -1 Int BE Pri Loop_exit
92829!#4 N7872 P5013 MEMBAR
92830!#5 N7873 P5014 ST 7 0x2800001 Int BE Pri Loop_entry
92831!#5 N7874 P5015 REPLACEMENT 5 Int BE Pri
92832!#5 N7875 P5016 SWAP 9 0xffffffff 0x2800002 Int BE Pri
92833!#5 N7876 P5017 DWLD 17 -1 Int BE Pri
92834!#5 N7877 P5018 MEMBAR
92835!#5 N7878 P5019 BST 6 0x42000001 FP BE Pri
92836!#5 N7879 P5019 BST 7 0x42000002 FP BE Pri
92837!#A N7878 N7879
92838!#5 N7880 P5019 BST 8 0x42000003 FP BE Pri
92839!#5 N7881 P5020 MEMBAR
92840!#5 N7882 P5021 SWAP 10 0xffffffff 0x2800003 Int BE Pri
92841!#5 N7883 P5022 REPLACEMENT 17 Int BE Pri
92842!#5 N7884 P5023 DWST 18 0x2800004 Int BE Pri
92843!#5 N7885 P5023 DWST 19 0x2800005 Int BE Pri
92844!#A N7884 N7885
92845!#5 N7886 P5024 DWST 9 0x2800006 Int BE Pri
92846!#5 N7887 P5024 DWST 10 0x2800007 Int BE Pri
92847!#A N7886 N7887
92848!#5 N7888 P5025 ST_BINIT 0 0x2800008 Int BE Pri
92849!#5 N7889 P5026 MEMBAR
92850!#5 N7890 P5027 LD 5 -1 Int BE Pri
92851!#5 N7891 P5027 CAS 5 -1 N7890 0x2800009 Int BE Pri
92852!#5 N7892 P5028 DWST 12 0x280000a Int BE Pri
92853!#5 N7893 P5028 DWST 13 0x280000b Int BE Pri
92854!#A N7892 N7893
92855!#5 N7894 P5029 DWST 2 0x280000c Int BE Pri
92856!#5 N7895 P5030 ST_BINIT 18 0x280000d Int BE Pri
92857!#5 N7896 P5031 MEMBAR
92858!#5 N7897 P5032 ST 9 0x280000e Int BE Pri
92859!#5 N7898 P5033 LDD 15 -1 Int BE Pri
92860!#5 N7899 P5033 LDD 16 -1 Int BE Pri
92861!#A N7898 N7899
92862!#5 N7900 P5034 ST 3 0x280000f Int BE Pri
92863!#5 N7901 P5035 ST 0 0x42000004 FP BE Pri
92864!#5 N7902 P5036 MEMBAR
92865!#5 N7903 P5037 BST 21 0x42000005 FP BE Pri
92866!#5 N7904 P5037 BST 22 0x42000006 FP BE Pri
92867!#A N7903 N7904
92868!#5 N7905 P5037 BST 23 0x42000007 FP BE Pri
92869!#5 N7906 P5038 MEMBAR
92870!#5 N7907 P5039 LDD 15 -1 Int LE Pri
92871!#5 N7908 P5039 LDD 16 -1 Int LE Pri
92872!#A N7907 N7908
92873!#5 N7909 P5040 DWST 9 0x2800010 Int BE Pri
92874!#5 N7910 P5040 DWST 10 0x2800011 Int BE Pri
92875!#A N7909 N7910
92876!#5 N7911 P5041 SWAP 7 0xffffffff 0x2800012 Int BE Pri
92877!#5 N7912 P5042 LD 6 -1 Int BE Pri
92878!#5 N7913 P5043 DWLD 3 -1 Int BE Pri
92879!#5 N7914 P5043 DWLD 4 -1 Int BE Pri
92880!#A N7913 N7914
92881!#5 N7915 P5044 MEMBAR
92882!#5 N7916 P5045 BLD 15 -1 FP BE Pri
92883!#5 N7917 P5045 BLD 16 -1 FP BE Pri
92884!#A N7916 N7917
92885!#5 N7918 P5045 BLD 17 -1 FP BE Pri
92886!#5 N7919 P5046 MEMBAR
92887!#5 N7920 P5047 REPLACEMENT 17 Int BE Pri
92888!#5 N7921 P5048 LD 17 -1 Int BE Pri
92889!#5 N7922 P5049 MEMBAR
92890!#5 N7923 P5050 BLD 12 -1 FP BE Pri
92891!#5 N7924 P5050 BLD 13 -1 FP BE Pri
92892!#A N7923 N7924
92893!#5 N7925 P5050 BLD 14 -1 FP BE Pri
92894!#5 N7926 P5051 MEMBAR
92895!#5 N7927 P5052 PREFETCH 7 Int BE Pri
92896!#5 N7928 P5053 LD 5 -1 Int BE Pri
92897!#5 N7929 P5054 ST_BINIT 1 0x2800013 Int BE Pri
92898!#5 N7930 P5055 MEMBAR
92899!#5 N7931 P5056 DWST_BINIT 17 0x2800014 Int BE Pri
92900!#5 N7932 P5057 MEMBAR
92901!#5 N7933 P5058 DWST 2 0x2800015 Int BE Pri
92902!#5 N7934 P5059 LD 18 -1 Int BE Pri
92903!#5 N7935 P5059 CAS 18 -1 N7934 0x2800016 Int BE Pri
92904!#5 N7936 P5060 DWLD 15 -1 Int BE Pri
92905!#5 N7937 P5060 DWLD 16 -1 Int BE Pri
92906!#A N7936 N7937
92907!#5 N7938 P5060 CASX 15 -1 N7936 0x2800017 Int BE Pri
92908!#5 N7939 P5060 CASX 16 -1 N7937 0x2800018 Int BE Pri
92909!#A N7938 N7939
92910!#5 N7940 P5061 PREFETCH 2 Int BE Pri
92911!#5 N7941 P5062 DWST_BINIT 0 0x2800019 Int BE Pri
92912!#5 N7942 P5062 DWST_BINIT 1 0x280001a Int BE Pri
92913!#A N7941 N7942
92914!#5 N7943 P5063 MEMBAR
92915!#5 N7944 P5064 BLD 3 -1 FP BE Pri
92916!#5 N7945 P5064 BLD 4 -1 FP BE Pri
92917!#A N7944 N7945
92918!#5 N7946 P5064 BLD 5 -1 FP BE Pri
92919!#5 N7947 P5065 MEMBAR
92920!#5 N7948 P5066 LD 18 -1 Int BE Pri
92921!#5 N7949 P5067 LDD 21 -1 Int BE Pri
92922!#5 N7950 P5067 LDD 22 -1 Int BE Pri
92923!#A N7949 N7950
92924!#5 N7951 P5068 DWST_BINIT 2 0x280001b Int BE Pri
92925!#5 N7952 P5069 MEMBAR
92926!#5 N7953 P5070 LDD 6 -1 Int BE Pri
92927!#5 N7954 P5070 LDD 7 -1 Int BE Pri
92928!#A N7953 N7954
92929!#5 N7955 P5071 ST_BINIT 15 0x280001c Int LE Pri
92930!#5 N7956 P5072 MEMBAR
92931!#5 N7957 P5073 LDD 3 -1 Int BE Pri
92932!#5 N7958 P5073 LDD 4 -1 Int BE Pri
92933!#A N7957 N7958
92934!#5 N7959 P5074 ST 15 0x280001d Int BE Pri
92935!#5 N7960 P5075 MEMBAR
92936!#5 N7961 P5076 BLD 9 -1 FP BE Pri
92937!#5 N7962 P5076 BLD 10 -1 FP BE Pri
92938!#A N7961 N7962
92939!#5 N7963 P5076 BLD 11 -1 FP BE Pri
92940!#5 N7964 P5077 MEMBAR
92941!#5 N7965 P5078 DWLD 14 -1 Int BE Pri
92942!#5 N7966 P5079 MEMBAR
92943!#5 N7967 P5080 BST 6 0x42000008 FP BE Pri
92944!#5 N7968 P5080 BST 7 0x42000009 FP BE Pri
92945!#A N7967 N7968
92946!#5 N7969 P5080 BST 8 0x4200000a FP BE Pri
92947!#5 N7970 P5081 MEMBAR
92948!#5 N7971 P5082 SWAP 23 0xffffffff 0x280001e Int BE Pri
92949!#5 N7972 P5083 LD 13 -1 Int BE Pri
92950!#5 N7973 P5083 CAS 13 -1 N7972 0x280001f Int BE Pri
92951!#5 N7974 P5084 LD 22 -1 Int BE Pri
92952!#5 N7975 P5084 CAS 22 -1 N7974 0x2800020 Int BE Pri
92953!#5 N7976 P5085 DWST_BINIT 9 0x2800021 Int LE Pri
92954!#5 N7977 P5085 DWST_BINIT 10 0x2800022 Int LE Pri
92955!#A N7976 N7977
92956!#5 N7978 P5086 MEMBAR
92957!#5 N7979 P5087 LDD 6 -1 Int BE Pri
92958!#5 N7980 P5087 LDD 7 -1 Int BE Pri
92959!#A N7979 N7980
92960!#5 N7981 P5088 ST 10 0x2800023 Int BE Pri
92961!#5 N7982 P5089 DWLD 23 -1 Int BE Pri
92962!#5 N7983 P5090 MEMBAR
92963!#5 N7984 P5091 BSTC 21 0x4200000b FP BE Pri
92964!#5 N7985 P5091 BSTC 22 0x4200000c FP BE Pri
92965!#A N7984 N7985
92966!#5 N7986 P5091 BSTC 23 0x4200000d FP BE Pri
92967!#5 N7987 P5092 MEMBAR
92968!#5 N7988 P5093 DWLD 9 -1 Int BE Pri
92969!#5 N7989 P5093 DWLD 10 -1 Int BE Pri
92970!#A N7988 N7989
92971!#5 N7990 P5093 CASX 9 -1 N7988 0x2800024 Int BE Pri
92972!#5 N7991 P5093 CASX 10 -1 N7989 0x2800025 Int BE Pri
92973!#A N7990 N7991
92974!#5 N7992 P5094 MEMBAR
92975!#5 N7993 P5095 BST 3 0x4200000e FP BE Pri
92976!#5 N7994 P5095 BST 4 0x4200000f FP BE Pri
92977!#A N7993 N7994
92978!#5 N7995 P5095 BST 5 0x42000010 FP BE Pri
92979!#5 N7996 P5096 MEMBAR
92980!#5 N7997 P5097 ST 9 0x2800026 Int BE Pri
92981!#5 N7998 P5098 REPLACEMENT 17 Int BE Pri
92982!#5 N7999 P5099 ST 13 0x2800027 Int BE Pri
92983!#5 N8000 P5100 DWST_BINIT 9 0x2800028 Int BE Pri
92984!#5 N8001 P5100 DWST_BINIT 10 0x2800029 Int BE Pri
92985!#A N8000 N8001
92986!#5 N8002 P5101 MEMBAR
92987!#5 N8003 P5102 BSTC 9 0x42000011 FP BE Pri
92988!#5 N8004 P5102 BSTC 10 0x42000012 FP BE Pri
92989!#A N8003 N8004
92990!#5 N8005 P5102 BSTC 11 0x42000013 FP BE Pri
92991!#5 N8006 P5103 MEMBAR
92992!#5 N8007 P5104 BST 0 0x42000014 FP BE Pri
92993!#5 N8008 P5104 BST 1 0x42000015 FP BE Pri
92994!#A N8007 N8008
92995!#5 N8009 P5104 BST 2 0x42000016 FP BE Pri
92996!#5 N8010 P5105 MEMBAR
92997!#5 N8011 P5106 PREFETCH 5 Int BE Pri
92998!#5 N8012 P5107 MEMBAR
92999!#5 N8013 P5108 BSTC 15 0x42000017 FP BE Pri
93000!#5 N8014 P5108 BSTC 16 0x42000018 FP BE Pri
93001!#A N8013 N8014
93002!#5 N8015 P5108 BSTC 17 0x42000019 FP BE Pri
93003!#5 N8016 P5109 MEMBAR
93004!#5 N8017 P5110 BSTC 21 0x4200001a FP BE Pri
93005!#5 N8018 P5110 BSTC 22 0x4200001b FP BE Pri
93006!#A N8017 N8018
93007!#5 N8019 P5110 BSTC 23 0x4200001c FP BE Pri
93008!#5 N8020 P5111 MEMBAR
93009!#5 N8021 P5112 LDD 3 -1 Int BE Pri
93010!#5 N8022 P5112 LDD 4 -1 Int BE Pri
93011!#A N8021 N8022
93012!#5 N8023 P5113 DWLD 18 -1 Int BE Pri
93013!#5 N8024 P5113 DWLD 19 -1 Int BE Pri
93014!#A N8023 N8024
93015!#5 N8025 P5114 DWST_BINIT 18 0x280002a Int BE Pri
93016!#5 N8026 P5114 DWST_BINIT 19 0x280002b Int BE Pri
93017!#A N8025 N8026
93018!#5 N8027 P5115 MEMBAR
93019!#5 N8028 P5116 ST 11 0x280002c Int BE Pri
93020!#5 N8029 P5117 LD 12 -1 Int BE Pri
93021!#5 N8030 P5118 LD 14 -1 Int BE Pri
93022!#5 N8031 P5119 MEMBAR
93023!#5 N8032 P5120 BSTC 12 0x4200001d FP BE Pri
93024!#5 N8033 P5120 BSTC 13 0x4200001e FP BE Pri
93025!#A N8032 N8033
93026!#5 N8034 P5120 BSTC 14 0x4200001f FP BE Pri
93027!#5 N8035 P5121 MEMBAR
93028!#5 N8036 P5122 DWST_BINIT 17 0x280002d Int BE Pri
93029!#5 N8037 P5123 MEMBAR
93030!#5 N8038 P5124 BLD 3 -1 FP BE Pri
93031!#5 N8039 P5124 BLD 4 -1 FP BE Pri
93032!#A N8038 N8039
93033!#5 N8040 P5124 BLD 5 -1 FP BE Pri
93034!#5 N8041 P5125 MEMBAR
93035!#5 N8042 P5126 BSTC 6 0x42000020 FP BE Pri
93036!#5 N8043 P5126 BSTC 7 0x42000021 FP BE Pri
93037!#A N8042 N8043
93038!#5 N8044 P5126 BSTC 8 0x42000022 FP BE Pri
93039!#5 N8045 P5127 MEMBAR
93040!#5 N8046 P5128 LD 0 -1 Int BE Pri
93041!#5 N8047 P5129 ST_BINIT 21 0x280002e Int BE Pri
93042!#5 N8048 P5130 MEMBAR
93043!#5 N8049 P5131 BST 21 0x42000023 FP BE Pri
93044!#5 N8050 P5131 BST 22 0x42000024 FP BE Pri
93045!#A N8049 N8050
93046!#5 N8051 P5131 BST 23 0x42000025 FP BE Pri
93047!#5 N8052 P5132 MEMBAR
93048!#5 N8053 P5133 DWST_BINIT 5 0x280002f Int BE Pri
93049!#5 N8054 P5134 MEMBAR
93050!#5 N8055 P5135 DWST 0 0x2800030 Int BE Pri
93051!#5 N8056 P5135 DWST 1 0x2800031 Int BE Pri
93052!#A N8055 N8056
93053!#5 N8057 P5136 LD 19 -1 FP BE Pri
93054!#5 N8058 P5137 LD 5 -1 Int BE Pri
93055!#5 N8059 P5138 LDD 17 -1 Int BE Pri
93056!#5 N8060 P5139 ST_BINIT 21 0x2800032 Int BE Pri
93057!#5 N8061 P5140 MEMBAR
93058!#5 N8062 P5141 DWST 11 0x2800033 Int LE Pri
93059!#5 N8063 P5142 ST 10 0x2800034 Int BE Pri
93060!#5 N8064 P5143 PREFETCH 17 Int BE Pri
93061!#5 N8065 P5144 DWLD 21 -1 Int BE Pri
93062!#5 N8066 P5144 DWLD 22 -1 Int BE Pri
93063!#A N8065 N8066
93064!#5 N8067 P5145 ST 11 0x2800035 Int BE Pri
93065!#5 N8068 P5146 ST_BINIT 10 0x2800036 Int BE Pri
93066!#5 N8069 P5147 MEMBAR
93067!#5 N8070 P5148 BSTC 18 0x42000026 FP BE Pri
93068!#5 N8071 P5148 BSTC 19 0x42000027 FP BE Pri
93069!#A N8070 N8071
93070!#5 N8072 P5148 BSTC 20 0x42000028 FP BE Pri
93071!#5 N8073 P5149 MEMBAR
93072!#5 N8074 P5150 SWAP 7 0xffffffff 0x2800037 Int BE Pri
93073!#5 N8075 P5151 REPLACEMENT 22 Int BE Pri
93074!#5 N8076 P5152 DWLD 6 -1 Int BE Pri
93075!#5 N8077 P5152 DWLD 7 -1 Int BE Pri
93076!#A N8076 N8077
93077!#5 N8078 P5153 MEMBAR
93078!#5 N8079 P5154 BSTC 0 0x42000029 FP BE Pri
93079!#5 N8080 P5154 BSTC 1 0x4200002a FP BE Pri
93080!#A N8079 N8080
93081!#5 N8081 P5154 BSTC 2 0x4200002b FP BE Pri
93082!#5 N8082 P5155 MEMBAR
93083!#5 N8083 P5156 LD 2 -1 Int BE Pri
93084!#5 N8084 P5157 DWLD 6 -1 Int BE Pri
93085!#5 N8085 P5157 DWLD 7 -1 Int BE Pri
93086!#A N8084 N8085
93087!#5 N8086 P5157 CASX 6 -1 N8084 0x2800038 Int BE Pri
93088!#5 N8087 P5157 CASX 7 -1 N8085 0x2800039 Int BE Pri
93089!#A N8086 N8087
93090!#5 N8088 P5158 DWST_BINIT 9 0x280003a Int BE Pri
93091!#5 N8089 P5158 DWST_BINIT 10 0x280003b Int BE Pri
93092!#A N8088 N8089
93093!#5 N8090 P5159 MEMBAR
93094!#5 N8091 P5160 DWLD 6 -1 Int BE Pri
93095!#5 N8092 P5160 DWLD 7 -1 Int BE Pri
93096!#A N8091 N8092
93097!#5 N8093 P5161 MEMBAR
93098!#5 N8094 P5162 BSTC 15 0x4200002c FP BE Pri
93099!#5 N8095 P5162 BSTC 16 0x4200002d FP BE Pri
93100!#A N8094 N8095
93101!#5 N8096 P5162 BSTC 17 0x4200002e FP BE Pri
93102!#5 N8097 P5163 MEMBAR
93103!#5 N8098 P5164 LD 4 -1 Int BE Pri
93104!#5 N8099 P5165 PREFETCH 19 Int BE Pri
93105!#5 N8100 P5166 LDD 6 -1 Int BE Pri
93106!#5 N8101 P5166 LDD 7 -1 Int BE Pri
93107!#A N8100 N8101
93108!#5 N8102 P5167 REPLACEMENT 0 Int BE Pri
93109!#5 N8103 P5168 PREFETCH 7 Int BE Pri
93110!#5 N8104 P5169 DWLD 14 -1,0x0 Int BE Pri
93111!#5 N8105 P5169 CASX 14 -1,0x0 N8104 0x280003c Int BE Pri
93112!#5 N8106 P5170 DWST_BINIT 6 0x280003d Int BE Pri
93113!#5 N8107 P5170 DWST_BINIT 7 0x280003e Int BE Pri
93114!#A N8106 N8107
93115!#5 N8108 P5171 MEMBAR
93116!#5 N8109 P5172 DWST 17 0x280003f Int BE Pri
93117!#5 N8110 P5173 DWLD 3 -1 Int BE Pri
93118!#5 N8111 P5173 DWLD 4 -1 Int BE Pri
93119!#A N8110 N8111
93120!#5 N8112 P5173 CASX 3 -1 N8110 0x2800040 Int BE Pri
93121!#5 N8113 P5173 CASX 4 -1 N8111 0x2800041 Int BE Pri
93122!#A N8112 N8113
93123!#5 N8114 P5174 DWST_BINIT 9 0x2800042 Int BE Pri
93124!#5 N8115 P5174 DWST_BINIT 10 0x2800043 Int BE Pri
93125!#A N8114 N8115
93126!#5 N8116 P5175 MEMBAR
93127!#5 N8117 P5176 ST_BINIT 22 0x2800044 Int BE Pri
93128!#5 N8118 P5177 MEMBAR
93129!#5 N8119 P5178 ST 4 0x2800045 Int BE Pri
93130!#5 N8120 P5179 MEMBAR
93131!#5 N8121 P5180 BST 9 0x4200002f FP BE Pri
93132!#5 N8122 P5180 BST 10 0x42000030 FP BE Pri
93133!#A N8121 N8122
93134!#5 N8123 P5180 BST 11 0x42000031 FP BE Pri
93135!#5 N8124 P5181 MEMBAR
93136!#5 N8125 P5182 DWST_BINIT 21 0x2800046 Int BE Pri
93137!#5 N8126 P5182 DWST_BINIT 22 0x2800047 Int BE Pri
93138!#A N8125 N8126
93139!#5 N8127 P5183 MEMBAR
93140!#5 N8128 P5184 DWST_BINIT 12 0x2800048 Int BE Pri
93141!#5 N8129 P5184 DWST_BINIT 13 0x2800049 Int BE Pri
93142!#A N8128 N8129
93143!#5 N8130 P5185 MEMBAR
93144!#5 N8131 P5186 DWLD 21 -1 Int BE Pri
93145!#5 N8132 P5186 DWLD 22 -1 Int BE Pri
93146!#A N8131 N8132
93147!#5 N8133 P5186 CASX 21 -1 N8131 0x280004a Int BE Pri
93148!#5 N8134 P5186 CASX 22 -1 N8132 0x280004b Int BE Pri
93149!#A N8133 N8134
93150!#5 N8135 P5187 DWST 9 0x280004c Int BE Pri
93151!#5 N8136 P5187 DWST 10 0x280004d Int BE Pri
93152!#A N8135 N8136
93153!#5 N8137 P5188 LD 2 -1 Int BE Pri
93154!#5 N8138 P5189 ST_BINIT 18 0x280004e Int BE Pri
93155!#5 N8139 P5190 MEMBAR
93156!#5 N8140 P5191 DWLD 6 -1 Int BE Pri
93157!#5 N8141 P5191 DWLD 7 -1 Int BE Pri
93158!#A N8140 N8141
93159!#5 N8142 P5192 PREFETCH 3 Int BE Pri
93160!#5 N8143 P5193 PREFETCH 11 Int BE Pri
93161!#5 N8144 P5194 DWST 12 0x280004f Int BE Pri
93162!#5 N8145 P5194 DWST 13 0x2800050 Int BE Pri
93163!#A N8144 N8145
93164!#5 N8146 P5195 DWST_BINIT 0 0x2800051 Int BE Pri
93165!#5 N8147 P5195 DWST_BINIT 1 0x2800052 Int BE Pri
93166!#A N8146 N8147
93167!#5 N8148 P5196 MEMBAR
93168!#5 N8149 P5197 PREFETCH 4 Int BE Pri
93169!#5 N8150 P5198 DWLD 15 -1 Int BE Pri
93170!#5 N8151 P5198 DWLD 16 -1 Int BE Pri
93171!#A N8150 N8151
93172!#5 N8152 P5198 CASX 15 -1 N8150 0x2800053 Int BE Pri
93173!#5 N8153 P5198 CASX 16 -1 N8151 0x2800054 Int BE Pri
93174!#A N8152 N8153
93175!#5 N8154 P5199 MEMBAR
93176!#5 N8155 P5200 BSTC 15 0x42000032 FP BE Pri
93177!#5 N8156 P5200 BSTC 16 0x42000033 FP BE Pri
93178!#A N8155 N8156
93179!#5 N8157 P5200 BSTC 17 0x42000034 FP BE Pri
93180!#5 N8158 P5201 MEMBAR
93181!#5 N8159 P5202 BLD 6 -1 FP BE Pri
93182!#5 N8160 P5202 BLD 7 -1 FP BE Pri
93183!#A N8159 N8160
93184!#5 N8161 P5202 BLD 8 -1 FP BE Pri
93185!#5 N8162 P5203 MEMBAR
93186!#5 N8163 P5204 DWLD 18 -1 FP BE Pri
93187!#5 N8164 P5204 DWLD 19 -1 FP BE Pri
93188!#A N8163 N8164
93189!#5 N8165 P5205 DWLD 12 -1 Int BE Pri
93190!#5 N8166 P5205 DWLD 13 -1 Int BE Pri
93191!#A N8165 N8166
93192!#5 N8167 P5206 ST_BINIT 12 0x2800055 Int BE Pri
93193!#5 N8168 P5207 MEMBAR
93194!#5 N8169 P5208 LD 3 -1 Int BE Pri
93195!#5 N8170 P5208 CAS 3 -1 N8169 0x2800056 Int BE Pri
93196!#5 N8171 P5209 PREFETCH 7 Int BE Pri
93197!#5 N8172 P5210 SWAP 8 0xffffffff 0x2800057 Int BE Pri
93198!#5 N8173 P5211 DWLD 15 -1 Int BE Pri
93199!#5 N8174 P5211 DWLD 16 -1 Int BE Pri
93200!#A N8173 N8174
93201!#5 N8175 P5211 CASX 15 -1 N8173 0x2800058 Int BE Pri
93202!#5 N8176 P5211 CASX 16 -1 N8174 0x2800059 Int BE Pri
93203!#A N8175 N8176
93204!#5 N8177 P5212 MEMBAR
93205!#5 N8178 P5213 BST 0 0x42000035 FP BE Pri
93206!#5 N8179 P5213 BST 1 0x42000036 FP BE Pri
93207!#A N8178 N8179
93208!#5 N8180 P5213 BST 2 0x42000037 FP BE Pri
93209!#5 N8181 P5214 MEMBAR
93210!#5 N8182 P5215 LD 1 -1 Int BE Pri
93211!#5 N8183 P5216 PREFETCH 2 Int BE Pri
93212!#5 N8184 P5217 DWLD 18 -1 Int BE Pri
93213!#5 N8185 P5217 DWLD 19 -1 Int BE Pri
93214!#A N8184 N8185
93215!#5 N8186 P5218 REPLACEMENT 2 Int BE Pri
93216!#5 N8187 P5219 PREFETCH 13 Int BE Pri
93217!#5 N8188 P5220 ST_BINIT 14 0x280005a Int LE Pri
93218!#5 N8189 P5221 MEMBAR
93219!#5 N8190 P5222 ST 3 0x280005b Int BE Pri
93220!#5 N8191 P5223 ST_BINIT 3 0x280005c Int BE Pri
93221!#5 N8192 P5224 MEMBAR
93222!#5 N8193 P5225 BST 12 0x42000038 FP BE Pri
93223!#5 N8194 P5225 BST 13 0x42000039 FP BE Pri
93224!#A N8193 N8194
93225!#5 N8195 P5225 BST 14 0x4200003a FP BE Pri
93226!#5 N8196 P5226 MEMBAR
93227!#5 N8197 P5227 LD 10 -1 Int BE Pri
93228!#5 N8198 P5227 CAS 10 -1 N8197 0x280005d Int BE Pri
93229!#5 N8199 P5228 DWST 8 0x280005e Int BE Pri
93230!#5 N8200 P5229 MEMBAR
93231!#5 N8201 P5230 BLD 9 -1 FP BE Pri
93232!#5 N8202 P5230 BLD 10 -1 FP BE Pri
93233!#A N8201 N8202
93234!#5 N8203 P5230 BLD 11 -1 FP BE Pri
93235!#5 N8204 P5231 MEMBAR
93236!#5 N8205 P5232 ST 2 0x280005f Int BE Pri
93237!#5 N8206 P5233 REPLACEMENT 15 Int BE Pri
93238!#5 N8207 P5234 MEMBAR
93239!#5 N8208 P5235 BLD 9 -1 FP BE Pri
93240!#5 N8209 P5235 BLD 10 -1 FP BE Pri
93241!#A N8208 N8209
93242!#5 N8210 P5235 BLD 11 -1 FP BE Pri
93243!#5 N8211 P5236 MEMBAR
93244!#5 N8212 P5237 PREFETCH 6 Int BE Pri
93245!#5 N8213 P5238 DWST 20 0x4200003b FP BE Pri
93246!#5 N8214 P5239 SWAP 9 0xffffffff 0x2800060 Int BE Pri
93247!#5 N8215 P5240 MEMBAR
93248!#5 N8216 P5241 BSTC 9 0x4200003c FP BE Pri
93249!#5 N8217 P5241 BSTC 10 0x4200003d FP BE Pri
93250!#A N8216 N8217
93251!#5 N8218 P5241 BSTC 11 0x4200003e FP BE Pri
93252!#5 N8219 P5242 MEMBAR
93253!#5 N8220 P5243 DWST 18 0x2800061 Int BE Pri
93254!#5 N8221 P5243 DWST 19 0x2800062 Int BE Pri
93255!#A N8220 N8221
93256!#5 N8222 P5244 ST 20 0x2800063 Int BE Pri
93257!#5 N8223 P5245 ST 18 0x2800064 Int BE Pri
93258!#5 N8224 P5246 LD 11 -1 Int BE Pri
93259!#5 N8225 P5247 PREFETCH 16 Int BE Pri
93260!#5 N8226 P5248 DWST_BINIT 8 0x2800065 Int BE Pri
93261!#5 N8227 P5249 MEMBAR
93262!#5 N8228 P5250 BSTC 9 0x4200003f FP BE Pri
93263!#5 N8229 P5250 BSTC 10 0x42000040 FP BE Pri
93264!#A N8228 N8229
93265!#5 N8230 P5250 BSTC 11 0x42000041 FP BE Pri
93266!#5 N8231 P5251 MEMBAR
93267!#5 N8232 P5252 DWST 21 0x42000042 FP BE Pri
93268!#5 N8233 P5252 DWST 22 0x42000043 FP BE Pri
93269!#A N8232 N8233
93270!#5 N8234 P5253 MEMBAR
93271!#5 N8235 P5254 BLD 3 -1 FP BE Pri
93272!#5 N8236 P5254 BLD 4 -1 FP BE Pri
93273!#A N8235 N8236
93274!#5 N8237 P5254 BLD 5 -1 FP BE Pri
93275!#5 N8238 P5255 MEMBAR
93276!#5 N8239 P5256 PREFETCH 14 Int BE Pri
93277!#5 N8240 P5257 MEMBAR
93278!#5 N8241 P5258 BLD 0 -1 FP BE Pri
93279!#5 N8242 P5258 BLD 1 -1 FP BE Pri
93280!#A N8241 N8242
93281!#5 N8243 P5258 BLD 2 -1 FP BE Pri
93282!#5 N8244 P5259 MEMBAR
93283!#5 N8245 P5260 SWAP 3 0xffffffff 0x2800066 Int BE Pri
93284!#5 N8246 P5261 DWST_BINIT 17 0x2800067 Int BE Pri
93285!#5 N8247 P5262 MEMBAR
93286!#5 N8248 P5263 BST 12 0x42000044 FP BE Pri
93287!#5 N8249 P5263 BST 13 0x42000045 FP BE Pri
93288!#A N8248 N8249
93289!#5 N8250 P5263 BST 14 0x42000046 FP BE Pri
93290!#5 N8251 P5264 MEMBAR
93291!#5 N8252 P5265 BST 9 0x42000047 FP BE Pri
93292!#5 N8253 P5265 BST 10 0x42000048 FP BE Pri
93293!#A N8252 N8253
93294!#5 N8254 P5265 BST 11 0x42000049 FP BE Pri
93295!#5 N8255 P5266 MEMBAR
93296!#5 N8256 P5267 LD 14 -1 Int BE Pri
93297!#5 N8257 P5267 CAS 14 -1 N8256 0x2800068 Int BE Pri
93298!#5 N8258 P5268 ST 21 0x2800069 Int BE Pri
93299!#5 N8259 P5269 MEMBAR
93300!#5 N8260 P5270 BSTC 9 0x4200004a FP BE Pri
93301!#5 N8261 P5270 BSTC 10 0x4200004b FP BE Pri
93302!#A N8260 N8261
93303!#5 N8262 P5270 BSTC 11 0x4200004c FP BE Pri
93304!#5 N8263 P5271 MEMBAR
93305!#5 N8264 P5272 REPLACEMENT 1 Int BE Pri
93306!#5 N8265 P5273 DWLD 12 -1 Int BE Pri
93307!#5 N8266 P5273 DWLD 13 -1 Int BE Pri
93308!#A N8265 N8266
93309!#5 N8267 P5274 PREFETCH 17 Int BE Pri
93310!#5 N8268 P5275 MEMBAR
93311!#5 N8269 P5276 BLD 9 -1 FP BE Pri
93312!#5 N8270 P5276 BLD 10 -1 FP BE Pri
93313!#A N8269 N8270
93314!#5 N8271 P5276 BLD 11 -1 FP BE Pri
93315!#5 N8272 P5277 MEMBAR
93316!#5 N8273 P5278 LD 8 -1 Int BE Pri
93317!#5 N8274 P5278 CAS 8 -1 N8273 0x280006a Int BE Pri
93318!#5 N8275 P5279 DWLD 15 -1 Int BE Pri
93319!#5 N8276 P5279 DWLD 16 -1 Int BE Pri
93320!#A N8275 N8276
93321!#5 N8277 P5280 DWST_BINIT 11 0x280006b Int BE Pri
93322!#5 N8278 P5281 MEMBAR
93323!#5 N8279 P5282 DWST 15 0x280006c Int BE Pri
93324!#5 N8280 P5282 DWST 16 0x280006d Int BE Pri
93325!#A N8279 N8280
93326!#5 N8281 P5283 PREFETCH 6 Int BE Pri
93327!#5 N8282 P5284 ST 4 0x280006e Int BE Pri
93328!#5 N8283 P5285 SWAP 7 0xffffffff 0x280006f Int BE Pri
93329!#5 N8284 P5286 LD 11 -1 Int BE Pri
93330!#5 N8285 P5287 DWLD 6 -1 Int BE Pri
93331!#5 N8286 P5287 DWLD 7 -1 Int BE Pri
93332!#A N8285 N8286
93333!#5 N8287 P5287 CASX 6 -1 N8285 0x2800070 Int BE Pri
93334!#5 N8288 P5287 CASX 7 -1 N8286 0x2800071 Int BE Pri
93335!#A N8287 N8288
93336!#5 N8289 P5288 MEMBAR
93337!#5 N8290 P5289 BSTC 9 0x4200004d FP BE Pri
93338!#5 N8291 P5289 BSTC 10 0x4200004e FP BE Pri
93339!#A N8290 N8291
93340!#5 N8292 P5289 BSTC 11 0x4200004f FP BE Pri
93341!#5 N8293 P5290 MEMBAR
93342!#5 N8294 P5291 BSTC 6 0x42000050 FP BE Pri
93343!#5 N8295 P5291 BSTC 7 0x42000051 FP BE Pri
93344!#A N8294 N8295
93345!#5 N8296 P5291 BSTC 8 0x42000052 FP BE Pri
93346!#5 N8297 P5292 MEMBAR
93347!#5 N8298 P5293 BST 18 0x42000053 FP BE Pri
93348!#5 N8299 P5293 BST 19 0x42000054 FP BE Pri
93349!#A N8298 N8299
93350!#5 N8300 P5293 BST 20 0x42000055 FP BE Pri
93351!#5 N8301 P5294 MEMBAR
93352!#5 N8302 P5295 ST 1 0x2800072 Int BE Pri
93353!#5 N8303 P5296 SWAP 17 0xffffffff 0x2800073 Int BE Pri
93354!#5 N8304 P5297 MEMBAR
93355!#5 N8305 P5298 BSTC 21 0x42000056 FP BE Pri
93356!#5 N8306 P5298 BSTC 22 0x42000057 FP BE Pri
93357!#A N8305 N8306
93358!#5 N8307 P5298 BSTC 23 0x42000058 FP BE Pri
93359!#5 N8308 P5299 MEMBAR
93360!#5 N8309 P5300 SWAP 22 0xffffffff 0x2800074 Int BE Pri
93361!#5 N8310 P5301 DWST 14 0x2800075 Int BE Pri
93362!#5 N8311 P5302 MEMBAR
93363!#5 N8312 P5303 BST 15 0x42000059 FP BE Pri
93364!#5 N8313 P5303 BST 16 0x4200005a FP BE Pri
93365!#A N8312 N8313
93366!#5 N8314 P5303 BST 17 0x4200005b FP BE Pri
93367!#5 N8315 P5304 MEMBAR
93368!#5 N8316 P5305 BLD 9 -1 FP BE Pri
93369!#5 N8317 P5305 BLD 10 -1 FP BE Pri
93370!#A N8316 N8317
93371!#5 N8318 P5305 BLD 11 -1 FP BE Pri
93372!#5 N8319 P5306 MEMBAR
93373!#5 N8320 P5307 DWLD 12 -1 Int BE Pri
93374!#5 N8321 P5307 DWLD 13 -1 Int BE Pri
93375!#A N8320 N8321
93376!#5 N8322 P5308 LDD 15 -1 Int BE Pri
93377!#5 N8323 P5308 LDD 16 -1 Int BE Pri
93378!#A N8322 N8323
93379!#5 N8324 P5309 DWST_BINIT 23 0x2800076 Int BE Pri
93380!#5 N8325 P5310 MEMBAR
93381!#5 N8326 P5311 BSTC 3 0x4200005c FP BE Pri
93382!#5 N8327 P5311 BSTC 4 0x4200005d FP BE Pri
93383!#A N8326 N8327
93384!#5 N8328 P5311 BSTC 5 0x4200005e FP BE Pri
93385!#5 N8329 P5312 MEMBAR
93386!#5 N8330 P5313 DWST 11 0x2800077 Int BE Pri
93387!#5 N8331 P5314 SWAP 19 0xffffffff 0x2800078 Int BE Pri
93388!#5 N8332 P5315 LDD 18 -1 Int BE Pri
93389!#5 N8333 P5315 LDD 19 -1 Int BE Pri
93390!#A N8332 N8333
93391!#5 N8334 P5316 LD 1 -1 Int BE Pri
93392!#5 N8335 P5316 CAS 1 -1 N8334 0x2800079 Int BE Pri
93393!#5 N8336 P5317 DWST_BINIT 9 0x280007a Int BE Pri
93394!#5 N8337 P5317 DWST_BINIT 10 0x280007b Int BE Pri
93395!#A N8336 N8337
93396!#5 N8338 P5318 MEMBAR
93397!#5 N8339 P5319 DWLD 23 -1 Int BE Pri
93398!#5 N8340 P5320 ST 7 0x280007c Int BE Pri
93399!#5 N8341 P5321 DWLD 20 -1 Int BE Pri
93400!#5 N8342 P5322 LD 22 -1 Int BE Pri
93401!#5 N8343 P5323 REPLACEMENT 10 Int BE Pri
93402!#5 N8344 P5324 ST_BINIT 8 0x280007d Int BE Pri
93403!#5 N8345 P5325 MEMBAR
93404!#5 N8346 P5326 DWLD 20 -1,0x0 Int BE Pri
93405!#5 N8347 P5326 CASX 20 -1,0x0 N8346 0x280007e Int BE Pri
93406!#5 N8348 P5327 LDD 6 -1 Int BE Pri
93407!#5 N8349 P5327 LDD 7 -1 Int BE Pri
93408!#A N8348 N8349
93409!#5 N8350 P5328 PREFETCH 4 Int BE Pri
93410!#5 N8351 P5329 ST 19 0x280007f Int LE Pri
93411!#5 N8352 P5330 ST_BINIT 22 0x2800080 Int BE Pri
93412!#5 N8353 P5331 MEMBAR
93413!#5 N8354 P5332 ST 10 0x2800081 Int BE Pri
93414!#5 N8355 P5333 LD 7 -1 Int BE Pri
93415!#5 N8356 P5334 SWAP 10 0xffffffff 0x2800082 Int BE Pri
93416!#5 N8357 P5335 MEMBAR
93417!#5 N8358 P5336 BST 9 0x4200005f FP BE Pri
93418!#5 N8359 P5336 BST 10 0x42000060 FP BE Pri
93419!#A N8358 N8359
93420!#5 N8360 P5336 BST 11 0x42000061 FP BE Pri
93421!#5 N8361 P5337 MEMBAR
93422!#5 N8362 P5338 DWLD 3 -1 Int BE Pri
93423!#5 N8363 P5338 DWLD 4 -1 Int BE Pri
93424!#A N8362 N8363
93425!#5 N8364 P5338 CASX 3 -1 N8362 0x2800083 Int BE Pri
93426!#5 N8365 P5338 CASX 4 -1 N8363 0x2800084 Int BE Pri
93427!#A N8364 N8365
93428!#5 N8366 P5339 ST_BINIT 2 0x2800085 Int BE Pri
93429!#5 N8367 P5340 MEMBAR
93430!#5 N8368 P5341 DWST 3 0x2800086 Int BE Pri
93431!#5 N8369 P5341 DWST 4 0x2800087 Int BE Pri
93432!#A N8368 N8369
93433!#5 N8370 P5342 LDD 9 -1 Int BE Pri
93434!#5 N8371 P5342 LDD 10 -1 Int BE Pri
93435!#A N8370 N8371
93436!#5 N8372 P5343 REPLACEMENT 13 Int BE Pri
93437!#5 N8373 P5344 LDD 0 -1 Int BE Pri
93438!#5 N8374 P5344 LDD 1 -1 Int BE Pri
93439!#A N8373 N8374
93440!#5 N8375 P5345 MEMBAR
93441!#5 N8376 P5346 BSTC 12 0x42000062 FP BE Pri
93442!#5 N8377 P5346 BSTC 13 0x42000063 FP BE Pri
93443!#A N8376 N8377
93444!#5 N8378 P5346 BSTC 14 0x42000064 FP BE Pri
93445!#5 N8379 P5347 MEMBAR
93446!#5 N8380 P5348 LDD 8 -1 Int BE Pri
93447!#5 N8381 P5349 ST 20 0x2800088 Int BE Pri
93448!#5 N8382 P5350 DWST_BINIT 21 0x2800089 Int BE Pri
93449!#5 N8383 P5350 DWST_BINIT 22 0x280008a Int BE Pri
93450!#A N8382 N8383
93451!#5 N8384 P5351 MEMBAR
93452!#5 N8385 P5352 ST_BINIT 22 0x280008b Int BE Pri
93453!#5 N8386 P5353 MEMBAR
93454!#5 N8387 P5354 PREFETCH 23 Int BE Pri
93455!#5 N8388 P5355 MEMBAR
93456!#5 N8389 P5356 BSTC 18 0x42000065 FP BE Pri
93457!#5 N8390 P5356 BSTC 19 0x42000066 FP BE Pri
93458!#A N8389 N8390
93459!#5 N8391 P5356 BSTC 20 0x42000067 FP BE Pri
93460!#5 N8392 P5357 MEMBAR
93461!#5 N8393 P5358 DWST_BINIT 21 0x280008c Int BE Pri
93462!#5 N8394 P5358 DWST_BINIT 22 0x280008d Int BE Pri
93463!#A N8393 N8394
93464!#5 N8395 P5359 MEMBAR
93465!#5 N8396 P5360 LD 2 -1 Int BE Pri
93466!#5 N8397 P5360 CAS 2 -1 N8396 0x280008e Int BE Pri
93467!#5 N8398 P5361 MEMBAR
93468!#5 N8399 P5362 BST 21 0x42000068 FP BE Pri
93469!#5 N8400 P5362 BST 22 0x42000069 FP BE Pri
93470!#A N8399 N8400
93471!#5 N8401 P5362 BST 23 0x4200006a FP BE Pri
93472!#5 N8402 P5363 MEMBAR
93473!#5 N8403 P5364 SWAP 4 0xffffffff 0x280008f Int BE Pri
93474!#5 N8404 P5365 ST_BINIT 18 0x2800090 Int BE Pri
93475!#5 N8405 P5366 MEMBAR
93476!#5 N8406 P5367 REPLACEMENT 23 Int BE Pri
93477!#5 N8407 P5368 REPLACEMENT 7 Int BE Pri
93478!#5 N8408 P5369 PREFETCH 19 Int BE Pri
93479!#5 N8409 P5370 LD 3 -1 Int BE Pri
93480!#5 N8410 P5370 CAS 3 -1 N8409 0x2800091 Int BE Pri
93481!#5 N8411 P5371 MEMBAR
93482!#5 N8412 P5372 BSTC 0 0x4200006b FP BE Pri
93483!#5 N8413 P5372 BSTC 1 0x4200006c FP BE Pri
93484!#A N8412 N8413
93485!#5 N8414 P5372 BSTC 2 0x4200006d FP BE Pri
93486!#5 N8415 P5373 MEMBAR
93487!#5 N8416 P5374 PREFETCH 2 Int BE Pri
93488!#5 N8417 P5375 ST_BINIT 22 0x2800092 Int BE Pri
93489!#5 N8418 P5376 MEMBAR
93490!#5 N8419 P5377 BLD 15 -1 FP BE Pri
93491!#5 N8420 P5377 BLD 16 -1 FP BE Pri
93492!#A N8419 N8420
93493!#5 N8421 P5377 BLD 17 -1 FP BE Pri
93494!#5 N8422 P5378 MEMBAR
93495!#5 N8423 P5379 BLD 3 -1 FP BE Pri
93496!#5 N8424 P5379 BLD 4 -1 FP BE Pri
93497!#A N8423 N8424
93498!#5 N8425 P5379 BLD 5 -1 FP BE Pri
93499!#5 N8426 P5380 MEMBAR
93500!#5 N8427 P5381 LD 15 -1 Int BE Pri
93501!#5 N8428 P5382 DWLD 12 -1 FP BE Pri
93502!#5 N8429 P5382 DWLD 13 -1 FP BE Pri
93503!#A N8428 N8429
93504!#5 N8430 P5383 LD 4 -1 Int LE Pri
93505!#5 N8431 P5383 CAS 4 -1 N8430 0x2800093 Int LE Pri
93506!#5 N8432 P5384 MEMBAR
93507!#5 N8433 P5385 BLD 18 -1 FP BE Pri
93508!#5 N8434 P5385 BLD 19 -1 FP BE Pri
93509!#A N8433 N8434
93510!#5 N8435 P5385 BLD 20 -1 FP BE Pri
93511!#5 N8436 P5386 MEMBAR
93512!#5 N8437 P5387 ST_BINIT 19 0x2800094 Int BE Pri
93513!#5 N8438 P5388 MEMBAR
93514!#5 N8439 P5389 BSTC 0 0x4200006e FP BE Pri
93515!#5 N8440 P5389 BSTC 1 0x4200006f FP BE Pri
93516!#A N8439 N8440
93517!#5 N8441 P5389 BSTC 2 0x42000070 FP BE Pri
93518!#5 N8442 P5390 MEMBAR
93519!#5 N8443 P5391 ST_BINIT 14 0x2800095 Int BE Pri
93520!#5 N8444 P5392 MEMBAR
93521!#5 N8445 P5393 SWAP 4 0xffffffff 0x2800096 Int BE Pri
93522!#5 N8446 P5394 DWLD 6 -1 Int BE Pri
93523!#5 N8447 P5394 DWLD 7 -1 Int BE Pri
93524!#A N8446 N8447
93525!#5 N8448 P5394 CASX 6 -1 N8446 0x2800097 Int BE Pri
93526!#5 N8449 P5394 CASX 7 -1 N8447 0x2800098 Int BE Pri
93527!#A N8448 N8449
93528!#5 N8450 P5395 DWST 3 0x42000071 FP BE Pri
93529!#5 N8451 P5395 DWST 4 0x42000072 FP BE Pri
93530!#A N8450 N8451
93531!#5 N8452 P5396 PREFETCH 16 Int BE Pri
93532!#5 N8453 P5397 LDD 3 -1 Int BE Pri
93533!#5 N8454 P5397 LDD 4 -1 Int BE Pri
93534!#A N8453 N8454
93535!#5 N8455 P5398 DWLD 12 -1 Int BE Pri
93536!#5 N8456 P5398 DWLD 13 -1 Int BE Pri
93537!#A N8455 N8456
93538!#5 N8457 P5398 CASX 12 -1 N8455 0x2800099 Int BE Pri
93539!#5 N8458 P5398 CASX 13 -1 N8456 0x280009a Int BE Pri
93540!#A N8457 N8458
93541!#5 N8459 P5399 LD 12 -1 Int BE Pri
93542!#5 N8460 P5400 ST 21 0x280009b Int BE Pri
93543!#5 N8461 P5401 SWAP 1 0xffffffff 0x280009c Int BE Pri
93544!#5 N8462 P5402 SWAP 19 0xffffffff 0x280009d Int BE Pri
93545!#5 N8463 P5403 ST_BINIT 2 0x280009e Int BE Pri
93546!#5 N8464 P5404 MEMBAR
93547!#5 N8465 P5405 DWLD 8 -1,0x0 Int BE Pri
93548!#5 N8466 P5405 CASX 8 -1,0x0 N8465 0x280009f Int BE Pri
93549!#5 N8467 P5406 ST 8 0x28000a0 Int BE Pri
93550!#5 N8468 P5407 SWAP 17 0xffffffff 0x28000a1 Int BE Pri
93551!#5 N8469 P5408 ST_BINIT 5 0x28000a2 Int BE Pri
93552!#5 N8470 P5409 MEMBAR
93553!#5 N8471 P5410 DWLD 3 -1 Int BE Pri
93554!#5 N8472 P5410 DWLD 4 -1 Int BE Pri
93555!#A N8471 N8472
93556!#5 N8473 P5411 LD 6 -1 Int LE Pri
93557!#5 N8474 P5412 ST_BINIT 1 0x28000a3 Int BE Pri
93558!#5 N8475 P5413 MEMBAR
93559!#5 N8476 P5414 DWLD 14 -1 FP BE Pri
93560!#5 N8477 P5415 LDD 20 -1 Int BE Pri
93561!#5 N8478 P5416 PREFETCH 10 Int BE Pri
93562!#5 N8479 P5417 LDD 8 -1 Int BE Pri
93563!#5 N8480 P5418 MEMBAR
93564!#5 N8481 P5419 BLD 21 -1 FP BE Pri
93565!#5 N8482 P5419 BLD 22 -1 FP BE Pri
93566!#A N8481 N8482
93567!#5 N8483 P5419 BLD 23 -1 FP BE Pri
93568!#5 N8484 P5420 MEMBAR
93569!#5 N8485 P5421 DWLD 15 -1 Int BE Pri
93570!#5 N8486 P5421 DWLD 16 -1 Int BE Pri
93571!#A N8485 N8486
93572!#5 N8487 P5422 SWAP 9 0xffffffff 0x28000a4 Int BE Pri
93573!#5 N8488 P5423 LDD 2 -1 Int BE Pri
93574!#5 N8489 P5424 PREFETCH 8 Int BE Pri
93575!#5 N8490 P5425 DWST_BINIT 5 0x28000a5 Int BE Pri
93576!#5 N8491 P5426 MEMBAR
93577!#5 N8492 P5427 DWST 5 0x28000a6 Int BE Pri
93578!#5 N8493 P5428 DWLD 20 -1,0x0 Int BE Pri
93579!#5 N8494 P5428 CASX 20 -1,0x0 N8493 0x28000a7 Int BE Pri
93580!#5 N8495 P5429 MEMBAR
93581!#5 N8496 P5430 BSTC 0 0x42000073 FP BE Pri
93582!#5 N8497 P5430 BSTC 1 0x42000074 FP BE Pri
93583!#A N8496 N8497
93584!#5 N8498 P5430 BSTC 2 0x42000075 FP BE Pri
93585!#5 N8499 P5431 MEMBAR
93586!#5 N8500 P5432 DWST_BINIT 11 0x28000a8 Int BE Pri
93587!#5 N8501 P5433 MEMBAR
93588!#5 N8502 P5434 LD 14 -1 Int BE Pri
93589!#5 N8503 P5435 ST_BINIT 3 0x28000a9 Int BE Pri
93590!#5 N8504 P5436 MEMBAR
93591!#5 N8505 P5437 DWST 6 0x28000aa Int BE Pri
93592!#5 N8506 P5437 DWST 7 0x28000ab Int BE Pri
93593!#A N8505 N8506
93594!#5 N8507 P5438 LDD 6 -1 Int LE Pri
93595!#5 N8508 P5438 LDD 7 -1 Int LE Pri
93596!#A N8507 N8508
93597!#5 N8509 P5439 DWLD 15 -1 Int BE Pri
93598!#5 N8510 P5439 DWLD 16 -1 Int BE Pri
93599!#A N8509 N8510
93600!#5 N8511 P5440 LDD 6 -1 Int BE Pri
93601!#5 N8512 P5440 LDD 7 -1 Int BE Pri
93602!#A N8511 N8512
93603!#5 N8513 P5441 LD 23 -1 Int BE Pri
93604!#5 N8514 P5441 CAS 23 -1 N8513 0x28000ac Int BE Pri
93605!#5 N8515 P5442 ST_BINIT 2 0x28000ad Int BE Pri
93606!#5 N8516 P5443 MEMBAR
93607!#5 N8517 P5444 ST 8 0x28000ae Int BE Pri
93608!#5 N8518 P5445 DWST 21 0x42000076 FP BE Pri
93609!#5 N8519 P5445 DWST 22 0x42000077 FP BE Pri
93610!#A N8518 N8519
93611!#5 N8520 P5446 PREFETCH 15 Int BE Pri
93612!#5 N8521 P5447 MEMBAR
93613!#5 N8522 P5448 BST 12 0x42000078 FP BE Pri
93614!#5 N8523 P5448 BST 13 0x42000079 FP BE Pri
93615!#A N8522 N8523
93616!#5 N8524 P5448 BST 14 0x4200007a FP BE Pri
93617!#5 N8525 P5449 MEMBAR
93618!#5 N8526 P5450 DWLD 6 -1 Int BE Pri
93619!#5 N8527 P5450 DWLD 7 -1 Int BE Pri
93620!#A N8526 N8527
93621!#5 N8528 P5451 ST_BINIT 21 0x28000af Int LE Pri
93622!#5 N8529 P5452 MEMBAR
93623!#5 N8530 P5453 LDD 12 -1 Int BE Pri
93624!#5 N8531 P5453 LDD 13 -1 Int BE Pri
93625!#A N8530 N8531
93626!#5 N8532 P5454 PREFETCH 19 Int BE Pri
93627!#5 N8533 P5455 DWLD 12 -1 FP BE Pri
93628!#5 N8534 P5455 DWLD 13 -1 FP BE Pri
93629!#A N8533 N8534
93630!#5 N8535 P5456 PREFETCH 14 Int BE Pri
93631!#5 N8536 P5457 LDD 20 -1 Int BE Pri
93632!#5 N8537 P5458 LD 19 -1 Int BE Pri
93633!#5 N8538 P5458 CAS 19 -1 N8537 0x28000b0 Int BE Pri
93634!#5 N8539 P5459 DWST 14 0x28000b1 Int BE Pri
93635!#5 N8540 P5460 LD 14 -1 Int BE Pri
93636!#5 N8541 P5460 CAS 14 -1 N8540 0x28000b2 Int BE Pri
93637!#5 N8542 P5461 DWST_BINIT 6 0x28000b3 Int LE Pri
93638!#5 N8543 P5461 DWST_BINIT 7 0x28000b4 Int LE Pri
93639!#A N8542 N8543
93640!#5 N8544 P5462 MEMBAR
93641!#5 N8545 P5463 ST_BINIT 5 0x28000b5 Int BE Pri
93642!#5 N8546 P5464 MEMBAR
93643!#5 N8547 P5465 LDD 21 -1 Int BE Pri
93644!#5 N8548 P5465 LDD 22 -1 Int BE Pri
93645!#A N8547 N8548
93646!#5 N8549 P5466 LD 19 -1 Int BE Pri
93647!#5 N8550 P5466 CAS 19 -1 N8549 0x28000b6 Int BE Pri
93648!#5 N8551 P5467 LD 13 -1 Int BE Pri
93649!#5 N8552 P5467 CAS 13 -1 N8551 0x28000b7 Int BE Pri
93650!#5 N8553 P5468 DWST 12 0x28000b8 Int BE Pri
93651!#5 N8554 P5468 DWST 13 0x28000b9 Int BE Pri
93652!#A N8553 N8554
93653!#5 N8555 P5469 LD 12 -1 Int BE Pri
93654!#5 N8556 P5470 PREFETCH 3 Int BE Pri
93655!#5 N8557 P5471 DWLD 17 -1,0x0 Int BE Pri
93656!#5 N8558 P5471 CASX 17 -1,0x0 N8557 0x28000ba Int BE Pri
93657!#5 N8559 P5472 SWAP 3 0xffffffff 0x28000bb Int BE Pri
93658!#5 N8560 P5473 LDD 11 -1 Int BE Pri
93659!#5 N8561 P5474 SWAP 12 0xffffffff 0x28000bc Int BE Pri
93660!#5 N8562 P5475 DWST_BINIT 18 0x28000bd Int BE Pri
93661!#5 N8563 P5475 DWST_BINIT 19 0x28000be Int BE Pri
93662!#A N8562 N8563
93663!#5 N8564 P5476 MEMBAR
93664!#5 N8565 P5477 LD 3 -1 Int BE Pri
93665!#5 N8566 P5477 CAS 3 -1 N8565 0x28000bf Int BE Pri
93666!#5 N8567 P5478 ST 20 0x28000c0 Int BE Pri
93667!#5 N8568 P5479 DWST_BINIT 20 0x28000c1 Int BE Pri
93668!#5 N8569 P5480 MEMBAR
93669!#5 N8570 P5481 ST_BINIT 22 0x28000c2 Int BE Pri
93670!#5 N8571 P5482 MEMBAR
93671!#5 N8572 P5483 BLD 6 -1 FP BE Pri
93672!#5 N8573 P5483 BLD 7 -1 FP BE Pri
93673!#A N8572 N8573
93674!#5 N8574 P5483 BLD 8 -1 FP BE Pri
93675!#5 N8575 P5484 MEMBAR
93676!#5 N8576 P5485 LD 14 -1 Int BE Pri
93677!#5 N8577 P5485 CAS 14 -1 N8576 0x28000c3 Int BE Pri
93678!#5 N8578 P5486 ST_BINIT 2 0x28000c4 Int BE Pri
93679!#5 N8579 P5487 MEMBAR
93680!#5 N8580 P5488 LDD 12 -1 Int BE Pri
93681!#5 N8581 P5488 LDD 13 -1 Int BE Pri
93682!#A N8580 N8581
93683!#5 N8582 P5489 REPLACEMENT 20 Int BE Pri
93684!#5 N8583 P5490 ST 3 0x28000c5 Int BE Pri
93685!#5 N8584 P5491 DWST 2 0x28000c6 Int BE Pri
93686!#5 N8585 P5492 MEMBAR
93687!#5 N8586 P5493 BLD 6 -1 FP BE Pri
93688!#5 N8587 P5493 BLD 7 -1 FP BE Pri
93689!#A N8586 N8587
93690!#5 N8588 P5493 BLD 8 -1 FP BE Pri
93691!#5 N8589 P5494 MEMBAR
93692!#5 N8590 P5495 SWAP 3 0xffffffff 0x28000c7 Int BE Pri
93693!#5 N8591 P5496 DWLD 5 -1,0x0 Int BE Pri
93694!#5 N8592 P5496 CASX 5 -1,0x0 N8591 0x28000c8 Int BE Pri
93695!#5 N8593 P5497 DWLD 14 -1 Int BE Pri
93696!#5 N8594 P5498 DWST_BINIT 18 0x28000c9 Int BE Pri
93697!#5 N8595 P5498 DWST_BINIT 19 0x28000ca Int BE Pri
93698!#A N8594 N8595
93699!#5 N8596 P5499 MEMBAR
93700!#5 N8597 P5500 BLD 12 -1 FP BE Pri
93701!#5 N8598 P5500 BLD 13 -1 FP BE Pri
93702!#A N8597 N8598
93703!#5 N8599 P5500 BLD 14 -1 FP BE Pri
93704!#5 N8600 P5501 MEMBAR
93705!#5 N8601 P5502 DWST_BINIT 0 0x28000cb Int BE Pri
93706!#5 N8602 P5502 DWST_BINIT 1 0x28000cc Int BE Pri
93707!#A N8601 N8602
93708!#5 N8603 P5503 MEMBAR
93709!#5 N8604 P5504 PREFETCH 22 Int BE Pri
93710!#5 N8605 P5505 ST_BINIT 15 0x28000cd Int BE Pri
93711!#5 N8606 P5506 MEMBAR
93712!#5 N8607 P5507 DWLD 2 -1,0x0 Int BE Pri
93713!#5 N8608 P5507 CASX 2 -1,0x0 N8607 0x28000ce Int BE Pri
93714!#5 N8609 P5508 MEMBAR
93715!#5 N8610 P5509 BST 12 0x4200007b FP BE Pri
93716!#5 N8611 P5509 BST 13 0x4200007c FP BE Pri
93717!#A N8610 N8611
93718!#5 N8612 P5509 BST 14 0x4200007d FP BE Pri
93719!#5 N8613 P5510 MEMBAR
93720!#5 N8614 P5511 SWAP 21 0xffffffff 0x28000cf Int BE Pri
93721!#5 N8615 P5512 LD 17 -1 Int BE Pri
93722!#5 N8616 P5512 CAS 17 -1 N8615 0x28000d0 Int BE Pri
93723!#5 N8617 P5513 ST_BINIT 11 0x28000d1 Int BE Pri
93724!#5 N8618 P5514 MEMBAR
93725!#5 N8619 P5515 LDD 0 -1 Int BE Pri
93726!#5 N8620 P5515 LDD 1 -1 Int BE Pri
93727!#A N8619 N8620
93728!#5 N8621 P5516 ST 7 0x28000d2 Int BE Pri
93729!#5 N8622 P5517 SWAP 19 0xffffffff 0x28000d3 Int BE Pri
93730!#5 N8623 P5518 MEMBAR
93731!#5 N8624 P5519 BSTC 0 0x4200007e FP BE Pri
93732!#5 N8625 P5519 BSTC 1 0x4200007f FP BE Pri
93733!#A N8624 N8625
93734!#5 N8626 P5519 BSTC 2 0x42000080 FP BE Pri
93735!#5 N8627 P5520 MEMBAR
93736!#5 N8628 P5521 ST 3 0x42000081 FP BE Pri
93737!#5 N8629 P5522 MEMBAR
93738!#5 N8630 P5523 BST 21 0x42000082 FP BE Pri
93739!#5 N8631 P5523 BST 22 0x42000083 FP BE Pri
93740!#A N8630 N8631
93741!#5 N8632 P5523 BST 23 0x42000084 FP BE Pri
93742!#5 N8633 P5524 MEMBAR
93743!#5 N8634 P5525 BST 3 0x42000085 FP BE Pri
93744!#5 N8635 P5525 BST 4 0x42000086 FP BE Pri
93745!#A N8634 N8635
93746!#5 N8636 P5525 BST 5 0x42000087 FP BE Pri
93747!#5 N8637 P5526 MEMBAR
93748!#5 N8638 P5527 LDD 9 -1 Int BE Pri
93749!#5 N8639 P5527 LDD 10 -1 Int BE Pri
93750!#A N8638 N8639
93751!#5 N8640 P5528 DWST 17 0x28000d4 Int BE Pri
93752!#5 N8641 P5529 LDD 18 -1 Int BE Pri
93753!#5 N8642 P5529 LDD 19 -1 Int BE Pri
93754!#A N8641 N8642
93755!#5 N8643 P5530 LD 8 -1 Int BE Pri
93756!#5 N8644 P5530 CAS 8 -1 N8643 0x28000d5 Int BE Pri
93757!#5 N8645 P5531 DWST 12 0x28000d6 Int BE Pri
93758!#5 N8646 P5531 DWST 13 0x28000d7 Int BE Pri
93759!#A N8645 N8646
93760!#5 N8647 P5532 SWAP 6 0xffffffff 0x28000d8 Int BE Pri
93761!#5 N8648 P5533 DWST_BINIT 5 0x28000d9 Int BE Pri
93762!#5 N8649 P5534 MEMBAR
93763!#5 N8650 P5535 SWAP 16 0xffffffff 0x28000da Int BE Pri
93764!#5 N8651 P5536 LDD 18 -1 Int BE Pri
93765!#5 N8652 P5536 LDD 19 -1 Int BE Pri
93766!#A N8651 N8652
93767!#5 N8653 P5537 PREFETCH 11 Int LE Pri
93768!#5 N8654 P5538 ST_BINIT 9 0x28000db Int BE Pri
93769!#5 N8655 P5539 MEMBAR
93770!#5 N8656 P5540 PREFETCH 9 Int BE Pri
93771!#5 N8657 P5541 SWAP 0 0xffffffff 0x28000dc Int BE Pri
93772!#5 N8658 P5542 DWLD 9 -1 Int BE Pri
93773!#5 N8659 P5542 DWLD 10 -1 Int BE Pri
93774!#A N8658 N8659
93775!#5 N8660 P5542 CASX 9 -1 N8658 0x28000dd Int BE Pri
93776!#5 N8661 P5542 CASX 10 -1 N8659 0x28000de Int BE Pri
93777!#A N8660 N8661
93778!#5 N8662 P5543 DWLD 3 -1 Int BE Pri
93779!#5 N8663 P5543 DWLD 4 -1 Int BE Pri
93780!#A N8662 N8663
93781!#5 N8664 P5543 CASX 3 -1 N8662 0x28000df Int BE Pri
93782!#5 N8665 P5543 CASX 4 -1 N8663 0x28000e0 Int BE Pri
93783!#A N8664 N8665
93784!#5 N8666 P5544 MEMBAR
93785!#5 N8667 P5545 BLD 21 -1 FP BE Pri
93786!#5 N8668 P5545 BLD 22 -1 FP BE Pri
93787!#A N8667 N8668
93788!#5 N8669 P5545 BLD 23 -1 FP BE Pri
93789!#5 N8670 P5546 MEMBAR
93790!#5 N8671 P5547 LD 17 -1 Int BE Pri
93791!#5 N8672 P5548 DWLD 15 -1 Int BE Pri
93792!#5 N8673 P5548 DWLD 16 -1 Int BE Pri
93793!#A N8672 N8673
93794!#5 N8674 P5549 MEMBAR
93795!#5 N8675 P5550 BLD 12 -1 FP BE Pri
93796!#5 N8676 P5550 BLD 13 -1 FP BE Pri
93797!#A N8675 N8676
93798!#5 N8677 P5550 BLD 14 -1 FP BE Pri
93799!#5 N8678 P5551 MEMBAR
93800!#5 N8679 P5552 SWAP 17 0xffffffff 0x28000e1 Int BE Pri
93801!#5 N8680 P5553 DWST_BINIT 9 0x28000e2 Int LE Pri
93802!#5 N8681 P5553 DWST_BINIT 10 0x28000e3 Int LE Pri
93803!#A N8680 N8681
93804!#5 N8682 P5554 MEMBAR
93805!#5 N8683 P5555 DWST_BINIT 8 0x28000e4 Int BE Pri
93806!#5 N8684 P5556 MEMBAR
93807!#5 N8685 P5557 LD 19 -1 Int BE Pri
93808!#5 N8686 P5558 DWLD 12 -1 Int BE Pri
93809!#5 N8687 P5558 DWLD 13 -1 Int BE Pri
93810!#A N8686 N8687
93811!#5 N8688 P5559 DWLD 11 -1 Int BE Pri
93812!#5 N8689 P5560 ST_BINIT 5 0x28000e5 Int BE Pri
93813!#5 N8690 P5561 MEMBAR
93814!#5 N8691 P5562 BLD 0 -1 FP BE Pri
93815!#5 N8692 P5562 BLD 1 -1 FP BE Pri
93816!#A N8691 N8692
93817!#5 N8693 P5562 BLD 2 -1 FP BE Pri
93818!#5 N8694 P5563 MEMBAR
93819!#5 N8695 P5564 ST_BINIT 2 0x28000e6 Int BE Pri
93820!#5 N8696 P5565 MEMBAR
93821!#5 N8697 P5566 DWST_BINIT 15 0x28000e7 Int BE Pri
93822!#5 N8698 P5566 DWST_BINIT 16 0x28000e8 Int BE Pri
93823!#A N8697 N8698
93824!#5 N8699 P5567 MEMBAR
93825!#5 N8700 P5568 LD 2 -1 FP BE Pri
93826!#5 N8701 P5569 ST_BINIT 22 0x28000e9 Int BE Pri
93827!#5 N8702 P5570 MEMBAR
93828!#5 N8703 P5571 SWAP 13 0xffffffff 0x28000ea Int LE Pri
93829!#5 N8704 P5572 LD 13 -1 Int LE Pri
93830!#5 N8705 P5572 CAS 13 -1 N8704 0x28000eb Int LE Pri
93831!#5 N8706 P5573 MEMBAR
93832!#5 N8707 P5574 BST 3 0x42000088 FP BE Pri
93833!#5 N8708 P5574 BST 4 0x42000089 FP BE Pri
93834!#A N8707 N8708
93835!#5 N8709 P5574 BST 5 0x4200008a FP BE Pri
93836!#5 N8710 P5575 MEMBAR
93837!#5 N8711 P5576 LD 3 -1 Int BE Pri
93838!#5 N8712 P5576 CAS 3 -1 N8711 0x28000ec Int BE Pri
93839!#5 N8713 P5577 MEMBAR
93840!#5 N8714 P5578 BSTC 18 0x4200008b FP BE Pri
93841!#5 N8715 P5578 BSTC 19 0x4200008c FP BE Pri
93842!#A N8714 N8715
93843!#5 N8716 P5578 BSTC 20 0x4200008d FP BE Pri
93844!#5 N8717 P5579 MEMBAR
93845!#5 N8718 P5580 DWST_BINIT 5 0x28000ed Int BE Pri
93846!#5 N8719 P5581 MEMBAR
93847!#5 N8720 P5582 ST_BINIT 5 0x28000ee Int BE Pri
93848!#5 N8721 P5583 MEMBAR
93849!#5 N8722 P5584 DWLD 12 -1 Int BE Pri
93850!#5 N8723 P5584 DWLD 13 -1 Int BE Pri
93851!#A N8722 N8723
93852!#5 N8724 P5585 MEMBAR
93853!#5 N8725 P5586 BSTC 0 0x4200008e FP BE Pri
93854!#5 N8726 P5586 BSTC 1 0x4200008f FP BE Pri
93855!#A N8725 N8726
93856!#5 N8727 P5586 BSTC 2 0x42000090 FP BE Pri
93857!#5 N8728 P5587 MEMBAR
93858!#5 N8729 P5588 PREFETCH 13 Int BE Pri
93859!#5 N8730 P5589 MEMBAR
93860!#5 N8731 P5590 BST 18 0x42000091 FP BE Pri
93861!#5 N8732 P5590 BST 19 0x42000092 FP BE Pri
93862!#A N8731 N8732
93863!#5 N8733 P5590 BST 20 0x42000093 FP BE Pri
93864!#5 N8734 P5591 MEMBAR
93865!#5 N8735 P5592 LD 1 -1 Int BE Pri
93866!#5 N8736 P5593 ST_BINIT 3 0x28000ef Int BE Pri
93867!#5 N8737 P5594 MEMBAR
93868!#5 N8738 P5595 LDD 9 -1 Int BE Pri
93869!#5 N8739 P5595 LDD 10 -1 Int BE Pri
93870!#A N8738 N8739
93871!#5 N8740 P5596 PREFETCH 22 Int BE Pri
93872!#5 N8741 P5597 ST 13 0x42000094 FP BE Pri
93873!#5 N8742 P5598 MEMBAR
93874!#5 N8743 P5599 BST 15 0x42000095 FP BE Pri
93875!#5 N8744 P5599 BST 16 0x42000096 FP BE Pri
93876!#A N8743 N8744
93877!#5 N8745 P5599 BST 17 0x42000097 FP BE Pri
93878!#5 N8746 P5600 MEMBAR
93879!#5 N8747 P5601 REPLACEMENT 8 Int BE Pri
93880!#5 N8748 P5602 PREFETCH 2 Int BE Pri
93881!#5 N8749 P5603 ST_BINIT 8 0x28000f0 Int BE Pri
93882!#5 N8750 P5604 MEMBAR
93883!#5 N8751 P5605 DWLD 0 -1 Int BE Pri
93884!#5 N8752 P5605 DWLD 1 -1 Int BE Pri
93885!#A N8751 N8752
93886!#5 N8753 P5605 CASX 0 -1 N8751 0x28000f1 Int BE Pri
93887!#5 N8754 P5605 CASX 1 -1 N8752 0x28000f2 Int BE Pri
93888!#A N8753 N8754
93889!#5 N8755 P5606 ST 23 0x28000f3 Int BE Pri
93890!#5 N8756 P5607 LD 13 -1 Int BE Pri
93891!#5 N8757 P5608 LD 3 -1 Int BE Pri
93892!#5 N8758 P5609 MEMBAR
93893!#5 N8759 P5610 BLD 3 -1 FP BE Pri
93894!#5 N8760 P5610 BLD 4 -1 FP BE Pri
93895!#A N8759 N8760
93896!#5 N8761 P5610 BLD 5 -1 FP BE Pri
93897!#5 N8762 P5611 MEMBAR
93898!#5 N8763 P5612 DWST 20 0x28000f4 Int BE Pri
93899!#5 N8764 P5613 DWST_BINIT 21 0x28000f5 Int BE Pri
93900!#5 N8765 P5613 DWST_BINIT 22 0x28000f6 Int BE Pri
93901!#A N8764 N8765
93902!#5 N8766 P5614 MEMBAR
93903!#5 N8767 P5615 DWLD 0 -1 Int BE Pri
93904!#5 N8768 P5615 DWLD 1 -1 Int BE Pri
93905!#A N8767 N8768
93906!#5 N8769 P5616 PREFETCH 1 Int BE Pri
93907!#5 N8770 P5617 LDD 0 -1 Int BE Pri
93908!#5 N8771 P5617 LDD 1 -1 Int BE Pri
93909!#A N8770 N8771
93910!#5 N8772 P5618 MEMBAR
93911!#5 N8773 P5619 BLD 6 -1 FP BE Pri
93912!#5 N8774 P5619 BLD 7 -1 FP BE Pri
93913!#A N8773 N8774
93914!#5 N8775 P5619 BLD 8 -1 FP BE Pri
93915!#5 N8776 P5620 MEMBAR
93916!#5 N8777 P5621 DWST_BINIT 3 0x28000f7 Int BE Pri
93917!#5 N8778 P5621 DWST_BINIT 4 0x28000f8 Int BE Pri
93918!#A N8777 N8778
93919!#5 N8779 P5622 MEMBAR
93920!#5 N8780 P5623 BST 15 0x42000098 FP BE Pri
93921!#5 N8781 P5623 BST 16 0x42000099 FP BE Pri
93922!#A N8780 N8781
93923!#5 N8782 P5623 BST 17 0x4200009a FP BE Pri
93924!#5 N8783 P5624 MEMBAR
93925!#5 N8784 P5625 DWLD 3 -1 Int BE Pri
93926!#5 N8785 P5625 DWLD 4 -1 Int BE Pri
93927!#A N8784 N8785
93928!#5 N8786 P5625 CASX 3 -1 N8784 0x28000f9 Int BE Pri
93929!#5 N8787 P5625 CASX 4 -1 N8785 0x28000fa Int BE Pri
93930!#A N8786 N8787
93931!#5 N8788 P5626 DWST_BINIT 3 0x28000fb Int BE Pri
93932!#5 N8789 P5626 DWST_BINIT 4 0x28000fc Int BE Pri
93933!#A N8788 N8789
93934!#5 N8790 P5627 MEMBAR
93935!#5 N8791 P5628 SWAP 0 0xffffffff 0x28000fd Int BE Pri
93936!#5 N8792 P5629 PREFETCH 8 Int BE Pri
93937!#5 N8793 P5630 DWLD 6 -1 Int BE Pri
93938!#5 N8794 P5630 DWLD 7 -1 Int BE Pri
93939!#A N8793 N8794
93940!#5 N8795 P5630 CASX 6 -1 N8793 0x28000fe Int BE Pri
93941!#5 N8796 P5630 CASX 7 -1 N8794 0x28000ff Int BE Pri
93942!#A N8795 N8796
93943!#5 N8797 P5631 SWAP 22 0xffffffff 0x2800100 Int BE Pri
93944!#5 N8798 P5632 PREFETCH 12 Int BE Pri
93945!#5 N8799 P5633 LD 15 -1 Int BE Pri
93946!#5 N8800 P5634 MEMBAR
93947!#5 N8801 P5635 BSTC 0 0x4200009b FP BE Pri
93948!#5 N8802 P5635 BSTC 1 0x4200009c FP BE Pri
93949!#A N8801 N8802
93950!#5 N8803 P5635 BSTC 2 0x4200009d FP BE Pri
93951!#5 N8804 P5636 MEMBAR
93952!#5 N8805 P5637 LD 14 -1 Int BE Pri
93953!#5 N8806 P5638 DWLD 3 -1 Int LE Pri
93954!#5 N8807 P5638 DWLD 4 -1 Int LE Pri
93955!#A N8806 N8807
93956!#5 N8808 P5639 MEMBAR
93957!#5 N8809 P5640 BLD 21 -1 FP BE Pri
93958!#5 N8810 P5640 BLD 22 -1 FP BE Pri
93959!#A N8809 N8810
93960!#5 N8811 P5640 BLD 23 -1 FP BE Pri
93961!#5 N8812 P5641 MEMBAR
93962!#5 N8813 P5642 ST 13 0x4200009e FP BE Pri
93963!#5 N8814 P5643 DWST 21 0x4200009f FP BE Pri
93964!#5 N8815 P5643 DWST 22 0x420000a0 FP BE Pri
93965!#A N8814 N8815
93966!#5 N8816 P5644 DWST_BINIT 0 0x2800101 Int BE Pri
93967!#5 N8817 P5644 DWST_BINIT 1 0x2800102 Int BE Pri
93968!#A N8816 N8817
93969!#5 N8818 P5645 MEMBAR
93970!#5 N8819 P5646 BLD 12 -1 FP BE Pri
93971!#5 N8820 P5646 BLD 13 -1 FP BE Pri
93972!#A N8819 N8820
93973!#5 N8821 P5646 BLD 14 -1 FP BE Pri
93974!#5 N8822 P5647 MEMBAR
93975!#5 N8823 P5648 DWST 20 0x2800103 Int BE Pri
93976!#5 N8824 P5649 LD 11 -1 Int BE Pri
93977!#5 N8825 P5649 CAS 11 -1 N8824 0x2800104 Int BE Pri
93978!#5 N8826 P5650 DWST_BINIT 17 0x2800105 Int BE Pri
93979!#5 N8827 P5651 MEMBAR
93980!#5 N8828 P5652 ST 22 0x2800106 Int BE Pri
93981!#5 N8829 P5653 ST_BINIT 18 0x2800107 Int BE Pri
93982!#5 N8830 P5654 MEMBAR
93983!#5 N8831 P5655 REPLACEMENT 4 Int BE Pri
93984!#5 N8832 P5656 REPLACEMENT 18 Int BE Pri
93985!#5 N8833 P5657 ST_BINIT 3 0x2800108 Int BE Pri
93986!#5 N8834 P5658 MEMBAR
93987!#5 N8835 P5659 BLD 3 -1 FP BE Pri
93988!#5 N8836 P5659 BLD 4 -1 FP BE Pri
93989!#A N8835 N8836
93990!#5 N8837 P5659 BLD 5 -1 FP BE Pri
93991!#5 N8838 P5660 MEMBAR
93992!#5 N8839 P5661 SWAP 11 0xffffffff 0x2800109 Int BE Pri
93993!#5 N8840 P5662 MEMBAR
93994!#5 N8841 P5663 BLD 15 -1 FP BE Pri
93995!#5 N8842 P5663 BLD 16 -1 FP BE Pri
93996!#A N8841 N8842
93997!#5 N8843 P5663 BLD 17 -1 FP BE Pri
93998!#5 N8844 P5664 MEMBAR
93999!#5 N8845 P5665 DWST 6 0x280010a Int BE Pri
94000!#5 N8846 P5665 DWST 7 0x280010b Int BE Pri
94001!#A N8845 N8846
94002!#5 N8847 P5666 LDD 0 -1 Int BE Pri
94003!#5 N8848 P5666 LDD 1 -1 Int BE Pri
94004!#A N8847 N8848
94005!#5 N8849 P5667 REPLACEMENT 9 Int BE Pri
94006!#5 N8850 P5668 LD 7 -1 FP BE Pri
94007!#5 N8851 P5669 MEMBAR
94008!#5 N8852 P5670 BLD 9 -1 FP BE Pri
94009!#5 N8853 P5670 BLD 10 -1 FP BE Pri
94010!#A N8852 N8853
94011!#5 N8854 P5670 BLD 11 -1 FP BE Pri
94012!#5 N8855 P5671 MEMBAR
94013!#5 N8856 P5672 DWST_BINIT 6 0x280010c Int BE Pri
94014!#5 N8857 P5672 DWST_BINIT 7 0x280010d Int BE Pri
94015!#A N8856 N8857
94016!#5 N8858 P5673 MEMBAR
94017!#5 N8859 P5674 DWST_BINIT 21 0x280010e Int BE Pri
94018!#5 N8860 P5674 DWST_BINIT 22 0x280010f Int BE Pri
94019!#A N8859 N8860
94020!#5 N8861 P5675 MEMBAR
94021!#5 N8862 P5676 DWLD 14 -1,0x0 Int BE Pri
94022!#5 N8863 P5676 CASX 14 -1,0x0 N8862 0x2800110 Int BE Pri
94023!#5 N8864 P5677 SWAP 21 0xffffffff 0x2800111 Int BE Pri
94024!#5 N8865 P5678 REPLACEMENT 19 Int BE Pri
94025!#5 N8866 P5679 LD 21 -1 Int LE Pri
94026!#5 N8867 P5680 DWLD 18 -1 Int BE Pri
94027!#5 N8868 P5680 DWLD 19 -1 Int BE Pri
94028!#A N8867 N8868
94029!#5 N8869 P5681 DWLD 21 -1 Int LE Pri
94030!#5 N8870 P5681 DWLD 22 -1 Int LE Pri
94031!#A N8869 N8870
94032!#5 N8871 P5681 CASX 21 -1 N8869 0x2800112 Int LE Pri
94033!#5 N8872 P5681 CASX 22 -1 N8870 0x2800113 Int LE Pri
94034!#A N8871 N8872
94035!#5 N8873 P5682 DWLD 3 -1 Int BE Pri
94036!#5 N8874 P5682 DWLD 4 -1 Int BE Pri
94037!#A N8873 N8874
94038!#5 N8875 P5682 CASX 3 -1 N8873 0x2800114 Int BE Pri
94039!#5 N8876 P5682 CASX 4 -1 N8874 0x2800115 Int BE Pri
94040!#A N8875 N8876
94041!#5 N8877 P5683 ST_BINIT 21 0x2800116 Int BE Pri
94042!#5 N8878 P5684 MEMBAR
94043!#5 N8879 P5685 LD 12 -1 Int BE Pri
94044!#5 N8880 P5686 MEMBAR
94045!#5 N8881 P5687 BST 9 0x420000a1 FP BE Pri
94046!#5 N8882 P5687 BST 10 0x420000a2 FP BE Pri
94047!#A N8881 N8882
94048!#5 N8883 P5687 BST 11 0x420000a3 FP BE Pri
94049!#5 N8884 P5688 MEMBAR
94050!#5 N8885 P5689 LD 13 -1 Int BE Pri
94051!#5 N8886 P5690 DWST 15 0x2800117 Int BE Pri
94052!#5 N8887 P5690 DWST 16 0x2800118 Int BE Pri
94053!#A N8886 N8887
94054!#5 N8888 P5691 MEMBAR
94055!#5 N8889 P5692 BLD 21 -1 FP BE Pri
94056!#5 N8890 P5692 BLD 22 -1 FP BE Pri
94057!#A N8889 N8890
94058!#5 N8891 P5692 BLD 23 -1 FP BE Pri
94059!#5 N8892 P5693 MEMBAR
94060!#5 N8893 P5694 BLD 15 -1 FP BE Pri
94061!#5 N8894 P5694 BLD 16 -1 FP BE Pri
94062!#A N8893 N8894
94063!#5 N8895 P5694 BLD 17 -1 FP BE Pri
94064!#5 N8896 P5695 MEMBAR
94065!#5 N8897 P5696 LD 6 -1 Int BE Pri
94066!#5 N8898 P5696 CAS 6 -1 N8897 0x2800119 Int BE Pri
94067!#5 N8899 P5697 DWLD 5 -1,0x0 Int BE Pri
94068!#5 N8900 P5697 CASX 5 -1,0x0 N8899 0x280011a Int BE Pri
94069!#5 N8901 P5698 MEMBAR
94070!#5 N8902 P5699 BSTC 18 0x420000a4 FP BE Pri
94071!#5 N8903 P5699 BSTC 19 0x420000a5 FP BE Pri
94072!#A N8902 N8903
94073!#5 N8904 P5699 BSTC 20 0x420000a6 FP BE Pri
94074!#5 N8905 P5700 MEMBAR
94075!#5 N8906 P5701 LDD 15 -1 Int BE Pri
94076!#5 N8907 P5701 LDD 16 -1 Int BE Pri
94077!#A N8906 N8907
94078!#5 N8908 P5702 MEMBAR
94079!#5 N8909 P5703 BST 12 0x420000a7 FP BE Pri
94080!#5 N8910 P5703 BST 13 0x420000a8 FP BE Pri
94081!#A N8909 N8910
94082!#5 N8911 P5703 BST 14 0x420000a9 FP BE Pri
94083!#5 N8912 P5704 MEMBAR
94084!#5 N8913 P5705 DWST_BINIT 8 0x280011b Int BE Pri
94085!#5 N8914 P5706 MEMBAR
94086!#5 N8915 P5707 LD 23 -1 Int BE Pri
94087!#5 N8916 P5707 CAS 23 -1 N8915 0x280011c Int BE Pri
94088!#5 N8917 P5708 MEMBAR
94089!#5 N8918 P5709 BLD 0 -1 FP BE Pri
94090!#5 N8919 P5709 BLD 1 -1 FP BE Pri
94091!#A N8918 N8919
94092!#5 N8920 P5709 BLD 2 -1 FP BE Pri
94093!#5 N8921 P5710 MEMBAR
94094!#5 N8922 P5711 BST 0 0x420000aa FP BE Pri
94095!#5 N8923 P5711 BST 1 0x420000ab FP BE Pri
94096!#A N8922 N8923
94097!#5 N8924 P5711 BST 2 0x420000ac FP BE Pri
94098!#5 N8925 P5712 MEMBAR
94099!#5 N8926 P5713 DWLD 15 -1 Int BE Pri
94100!#5 N8927 P5713 DWLD 16 -1 Int BE Pri
94101!#A N8926 N8927
94102!#5 N8928 P5713 CASX 15 -1 N8926 0x280011d Int BE Pri
94103!#5 N8929 P5713 CASX 16 -1 N8927 0x280011e Int BE Pri
94104!#A N8928 N8929
94105!#5 N8930 P5714 LD 20 -1 Int BE Pri
94106!#5 N8931 P5714 CAS 20 -1 N8930 0x280011f Int BE Pri
94107!#5 N8932 P5715 LD 4 -1 Int BE Pri
94108!#5 N8933 P5716 SWAP 7 0xffffffff 0x2800120 Int BE Pri
94109!#5 N8934 P5717 PREFETCH 8 Int BE Pri
94110!#5 N8935 P5718 MEMBAR
94111!#5 N8936 P5719 BST 9 0x420000ad FP BE Pri
94112!#5 N8937 P5719 BST 10 0x420000ae FP BE Pri
94113!#A N8936 N8937
94114!#5 N8938 P5719 BST 11 0x420000af FP BE Pri
94115!#5 N8939 P5720 MEMBAR
94116!#5 N8940 P5721 LDD 2 -1 Int BE Pri
94117!#5 N8941 P5722 ST 9 0x2800121 Int BE Pri
94118!#5 N8942 P5723 REPLACEMENT 2 Int BE Pri
94119!#5 N8943 P5724 DWST 15 0x2800122 Int BE Pri
94120!#5 N8944 P5724 DWST 16 0x2800123 Int BE Pri
94121!#A N8943 N8944
94122!#5 N8945 P5725 DWLD 5 -1,0x0 Int BE Pri
94123!#5 N8946 P5725 CASX 5 -1,0x0 N8945 0x2800124 Int BE Pri
94124!#5 N8947 P5726 ST_BINIT 12 0x2800125 Int BE Pri
94125!#5 N8948 P5727 MEMBAR
94126!#5 N8949 P5728 DWLD 6 -1 Int BE Pri
94127!#5 N8950 P5728 DWLD 7 -1 Int BE Pri
94128!#A N8949 N8950
94129!#5 N8951 P5729 DWST_BINIT 5 0x2800126 Int BE Pri
94130!#5 N8952 P5730 MEMBAR
94131!#5 N8953 P5731 PREFETCH 1 Int BE Pri
94132!#5 N8954 P5732 REPLACEMENT 9 Int BE Pri
94133!#5 N8955 P5733 ST 15 0x2800127 Int BE Pri
94134!#5 N8956 P5734 MEMBAR
94135!#5 N8957 P5735 BST 3 0x420000b0 FP BE Pri
94136!#5 N8958 P5735 BST 4 0x420000b1 FP BE Pri
94137!#A N8957 N8958
94138!#5 N8959 P5735 BST 5 0x420000b2 FP BE Pri
94139!#5 N8960 P5736 MEMBAR
94140!#5 N8961 P5737 LD 0 -1 Int BE Pri
94141!#5 N8962 P5737 CAS 0 -1 N8961 0x2800128 Int BE Pri
94142!#5 N8963 P5738 ST_BINIT 16 0x2800129 Int BE Pri
94143!#5 N8964 P5739 MEMBAR
94144!#5 N8965 P5740 BLD 15 -1 FP BE Pri
94145!#5 N8966 P5740 BLD 16 -1 FP BE Pri
94146!#A N8965 N8966
94147!#5 N8967 P5740 BLD 17 -1 FP BE Pri
94148!#5 N8968 P5741 MEMBAR
94149!#5 N8969 P5742 ST 9 0x280012a Int BE Pri
94150!#5 N8970 P5743 LD 14 -1 Int BE Pri
94151!#5 N8971 P5743 CAS 14 -1 N8970 0x280012b Int BE Pri
94152!#5 N8972 P5744 LD 11 -1 Int BE Pri
94153!#5 N8973 P5744 CAS 11 -1 N8972 0x280012c Int BE Pri
94154!#5 N8974 P5745 DWLD 2 -1,0x0 Int BE Pri
94155!#5 N8975 P5745 CASX 2 -1,0x0 N8974 0x280012d Int BE Pri
94156!#5 N8976 P5746 ST 18 0x280012e Int BE Pri
94157!#5 N8977 P5747 PREFETCH 1 Int BE Pri
94158!#5 N8978 P5748 MEMBAR
94159!#5 N8979 P5749 BSTC 0 0x420000b3 FP BE Pri
94160!#5 N8980 P5749 BSTC 1 0x420000b4 FP BE Pri
94161!#A N8979 N8980
94162!#5 N8981 P5749 BSTC 2 0x420000b5 FP BE Pri
94163!#5 N8982 P5750 MEMBAR
94164!#5 N8983 P5751 DWLD 2 -1 Int BE Pri
94165!#5 N8984 P5752 MEMBAR
94166!#5 N8985 P5753 BSTC 21 0x420000b6 FP BE Pri
94167!#5 N8986 P5753 BSTC 22 0x420000b7 FP BE Pri
94168!#A N8985 N8986
94169!#5 N8987 P5753 BSTC 23 0x420000b8 FP BE Pri
94170!#5 N8988 P5754 MEMBAR
94171!#5 N8989 P5755 DWLD 23 -1,0x0 Int BE Pri
94172!#5 N8990 P5755 CASX 23 -1,0x0 N8989 0x280012f Int BE Pri
94173!#5 N8991 P5756 DWLD 15 -1 Int BE Pri
94174!#5 N8992 P5756 DWLD 16 -1 Int BE Pri
94175!#A N8991 N8992
94176!#5 N8993 P5756 CASX 15 -1 N8991 0x2800130 Int BE Pri
94177!#5 N8994 P5756 CASX 16 -1 N8992 0x2800131 Int BE Pri
94178!#A N8993 N8994
94179!#5 N8995 P5757 ST_BINIT 22 0x2800132 Int BE Pri
94180!#5 N8996 P5758 MEMBAR
94181!#5 N8997 P5759 DWLD 6 -1 Int BE Pri
94182!#5 N8998 P5759 DWLD 7 -1 Int BE Pri
94183!#A N8997 N8998
94184!#5 N8999 P5759 CASX 6 -1 N8997 0x2800133 Int BE Pri
94185!#5 N9000 P5759 CASX 7 -1 N8998 0x2800134 Int BE Pri
94186!#A N8999 N9000
94187!#5 N9001 P5760 DWLD 9 -1 Int BE Pri
94188!#5 N9002 P5760 DWLD 10 -1 Int BE Pri
94189!#A N9001 N9002
94190!#5 N9003 P5761 DWLD 0 -1 Int BE Pri
94191!#5 N9004 P5761 DWLD 1 -1 Int BE Pri
94192!#A N9003 N9004
94193!#5 N9005 P5762 LD 13 -1 Int BE Pri
94194!#5 N9006 P5763 MEMBAR
94195!#5 N9007 P5764 BST 6 0x420000b9 FP BE Pri
94196!#5 N9008 P5764 BST 7 0x420000ba FP BE Pri
94197!#A N9007 N9008
94198!#5 N9009 P5764 BST 8 0x420000bb FP BE Pri
94199!#5 N9010 P5765 MEMBAR
94200!#5 N9011 P5766 BLD 3 -1 FP BE Pri
94201!#5 N9012 P5766 BLD 4 -1 FP BE Pri
94202!#A N9011 N9012
94203!#5 N9013 P5766 BLD 5 -1 FP BE Pri
94204!#5 N9014 P5767 MEMBAR
94205!#5 N9015 P5768 LD 20 -1 Int BE Pri
94206!#5 N9016 P5769 DWST_BINIT 18 0x2800135 Int BE Pri
94207!#5 N9017 P5769 DWST_BINIT 19 0x2800136 Int BE Pri
94208!#A N9016 N9017
94209!#5 N9018 P5770 MEMBAR
94210!#5 N9019 P5771 SWAP 16 0xffffffff 0x2800137 Int BE Pri
94211!#5 N9020 P5772 SWAP 22 0xffffffff 0x2800138 Int BE Pri
94212!#5 N9021 P5773 ST 16 0x2800139 Int BE Pri
94213!#5 N9022 P5774 DWST_BINIT 18 0x280013a Int BE Pri
94214!#5 N9023 P5774 DWST_BINIT 19 0x280013b Int BE Pri
94215!#A N9022 N9023
94216!#5 N9024 P5775 MEMBAR
94217!#5 N9025 P5776 LDD 15 -1 Int BE Pri
94218!#5 N9026 P5776 LDD 16 -1 Int BE Pri
94219!#A N9025 N9026
94220!#5 N9027 P5777 DWST 2 0x420000bc FP BE Pri
94221!#5 N9028 P5778 DWST_BINIT 3 0x280013c Int BE Pri
94222!#5 N9029 P5778 DWST_BINIT 4 0x280013d Int BE Pri
94223!#A N9028 N9029
94224!#5 N9030 P5779 MEMBAR
94225!#5 N9031 P5780 LDD 6 -1 Int BE Pri
94226!#5 N9032 P5780 LDD 7 -1 Int BE Pri
94227!#A N9031 N9032
94228!#5 N9033 P5781 LD 2 -1 Int BE Pri
94229!#5 N9034 P5782 ST 0 0x280013e Int LE Pri
94230!#5 N9035 P5783 MEMBAR
94231!#5 N9036 P5784 BSTC 21 0x420000bd FP BE Pri
94232!#5 N9037 P5784 BSTC 22 0x420000be FP BE Pri
94233!#A N9036 N9037
94234!#5 N9038 P5784 BSTC 23 0x420000bf FP BE Pri
94235!#5 N9039 P5785 MEMBAR
94236!#5 N9040 P5786 ST_BINIT 2 0x280013f Int BE Pri
94237!#5 N9041 P5787 MEMBAR
94238!#5 N9042 P5788 LD 14 -1 Int BE Pri
94239!#5 N9043 P5788 CAS 14 -1 N9042 0x2800140 Int BE Pri
94240!#5 N9044 P5789 MEMBAR
94241!#5 N9045 P5790 BLD 15 -1 FP BE Pri
94242!#5 N9046 P5790 BLD 16 -1 FP BE Pri
94243!#A N9045 N9046
94244!#5 N9047 P5790 BLD 17 -1 FP BE Pri
94245!#5 N9048 P5791 MEMBAR
94246!#5 N9049 P5792 DWST 3 0x2800141 Int BE Pri
94247!#5 N9050 P5792 DWST 4 0x2800142 Int BE Pri
94248!#A N9049 N9050
94249!#5 N9051 P5793 MEMBAR
94250!#5 N9052 P5794 BSTC 0 0x420000c0 FP BE Pri
94251!#5 N9053 P5794 BSTC 1 0x420000c1 FP BE Pri
94252!#A N9052 N9053
94253!#5 N9054 P5794 BSTC 2 0x420000c2 FP BE Pri
94254!#5 N9055 P5795 MEMBAR
94255!#5 N9056 P5796 DWLD 11 -1,0x0 Int BE Pri
94256!#5 N9057 P5796 CASX 11 -1,0x0 N9056 0x2800143 Int BE Pri
94257!#5 N9058 P5797 SWAP 15 0xffffffff 0x2800144 Int BE Pri
94258!#5 N9059 P5798 ST_BINIT 22 0x2800145 Int BE Pri
94259!#5 N9060 P5799 MEMBAR
94260!#5 N9061 P5800 LD 7 -1 Int BE Pri
94261!#5 N9062 P5800 CAS 7 -1 N9061 0x2800146 Int BE Pri
94262!#5 N9063 P5801 DWST_BINIT 0 0x2800147 Int BE Pri
94263!#5 N9064 P5801 DWST_BINIT 1 0x2800148 Int BE Pri
94264!#A N9063 N9064
94265!#5 N9065 P5802 MEMBAR
94266!#5 N9066 P5803 LD 17 -1 Int BE Pri
94267!#5 N9067 P5803 CAS 17 -1 N9066 0x2800149 Int BE Pri
94268!#5 N9068 P5804 MEMBAR
94269!#5 N9069 P5805 BSTC 12 0x420000c3 FP BE Pri
94270!#5 N9070 P5805 BSTC 13 0x420000c4 FP BE Pri
94271!#A N9069 N9070
94272!#5 N9071 P5805 BSTC 14 0x420000c5 FP BE Pri
94273!#5 N9072 P5806 MEMBAR
94274!#5 N9073 P5807 DWST_BINIT 5 0x280014a Int BE Pri
94275!#5 N9074 P5808 MEMBAR
94276!#5 N9075 P5809 ST_BINIT 21 0x280014b Int BE Pri
94277!#5 N9076 P5810 MEMBAR
94278!#5 N9077 P5811 REPLACEMENT 2 Int BE Pri
94279!#5 N9078 P5812 LD 8 -1 Int BE Pri
94280!#5 N9079 P5812 CAS 8 -1 N9078 0x280014c Int BE Pri
94281!#5 N9080 P5813 LD 14 -1 Int BE Pri
94282!#5 N9081 P5814 ST 17 0x280014d Int BE Pri
94283!#5 N9082 P5815 MEMBAR
94284!#5 N9083 P5816 BST 6 0x420000c6 FP BE Pri
94285!#5 N9084 P5816 BST 7 0x420000c7 FP BE Pri
94286!#A N9083 N9084
94287!#5 N9085 P5816 BST 8 0x420000c8 FP BE Pri
94288!#5 N9086 P5817 MEMBAR
94289!#5 N9087 P5818 BST 18 0x420000c9 FP BE Pri
94290!#5 N9088 P5818 BST 19 0x420000ca FP BE Pri
94291!#A N9087 N9088
94292!#5 N9089 P5818 BST 20 0x420000cb FP BE Pri
94293!#5 N9090 P5819 MEMBAR
94294!#5 N9091 P5820 SWAP 9 0xffffffff 0x280014e Int BE Pri
94295!#5 N9092 P5821 DWLD 12 -1 Int BE Pri
94296!#5 N9093 P5821 DWLD 13 -1 Int BE Pri
94297!#A N9092 N9093
94298!#5 N9094 P5821 CASX 12 -1 N9092 0x280014f Int BE Pri
94299!#5 N9095 P5821 CASX 13 -1 N9093 0x2800150 Int BE Pri
94300!#A N9094 N9095
94301!#5 N9096 P5822 ST 7 0x2800151 Int BE Pri
94302!#5 N9097 P5823 REPLACEMENT 3 Int BE Pri
94303!#5 N9098 P5824 LDD 3 -1 Int BE Pri
94304!#5 N9099 P5824 LDD 4 -1 Int BE Pri
94305!#A N9098 N9099
94306!#5 N9100 P5825 MEMBAR
94307!#5 N9101 P5826 BLD 12 -1 FP BE Pri
94308!#5 N9102 P5826 BLD 13 -1 FP BE Pri
94309!#A N9101 N9102
94310!#5 N9103 P5826 BLD 14 -1 FP BE Pri
94311!#5 N9104 P5827 MEMBAR
94312!#5 N9105 P5828 ST_BINIT 8 0x2800152 Int BE Pri
94313!#5 N9106 P5829 MEMBAR
94314!#5 N9107 P5830 REPLACEMENT 9 Int BE Pri
94315!#5 N9108 P5831 ST_BINIT 6 0x2800153 Int BE Pri
94316!#5 N9109 P5832 MEMBAR
94317!#5 N9110 P5833 REPLACEMENT 10 Int BE Pri
94318!#5 N9111 P5834 SWAP 17 0xffffffff 0x2800154 Int BE Pri
94319!#5 N9112 P5835 MEMBAR
94320!#5 N9113 P5836 BST 0 0x420000cc FP BE Pri
94321!#5 N9114 P5836 BST 1 0x420000cd FP BE Pri
94322!#A N9113 N9114
94323!#5 N9115 P5836 BST 2 0x420000ce FP BE Pri
94324!#5 N9116 P5837 MEMBAR
94325!#5 N9117 P5838 DWLD 0 -1 Int LE Pri
94326!#5 N9118 P5838 DWLD 1 -1 Int LE Pri
94327!#A N9117 N9118
94328!#5 N9119 P5839 ST 8 0x2800155 Int BE Pri
94329!#5 N9120 P5840 ST 17 0x2800156 Int BE Pri
94330!#5 N9121 P5841 DWLD 3 -1 Int BE Pri
94331!#5 N9122 P5841 DWLD 4 -1 Int BE Pri
94332!#A N9121 N9122
94333!#5 N9123 P5841 CASX 3 -1 N9121 0x2800157 Int BE Pri
94334!#5 N9124 P5841 CASX 4 -1 N9122 0x2800158 Int BE Pri
94335!#A N9123 N9124
94336!#5 N9125 P5842 DWLD 17 -1,0x0 Int LE Pri
94337!#5 N9126 P5842 CASX 17 -1,0x0 N9125 0x2800159 Int LE Pri
94338!#5 N9127 P5843 MEMBAR
94339!#5 N9128 P5844 BST 18 0x420000cf FP BE Pri
94340!#5 N9129 P5844 BST 19 0x420000d0 FP BE Pri
94341!#A N9128 N9129
94342!#5 N9130 P5844 BST 20 0x420000d1 FP BE Pri
94343!#5 N9131 P5845 MEMBAR
94344!#5 N9132 P5846 PREFETCH 11 Int BE Pri
94345!#5 N9133 P5847 MEMBAR
94346!#5 N9134 P5848 BSTC 0 0x420000d2 FP BE Pri
94347!#5 N9135 P5848 BSTC 1 0x420000d3 FP BE Pri
94348!#A N9134 N9135
94349!#5 N9136 P5848 BSTC 2 0x420000d4 FP BE Pri
94350!#5 N9137 P5849 MEMBAR
94351!#5 N9138 P5850 PREFETCH 18 Int BE Pri
94352!#5 N9139 P5851 LD 21 -1 Int BE Pri
94353!#5 N9140 P5851 CAS 21 -1 N9139 0x280015a Int BE Pri
94354!#5 N9141 P5852 ST 7 0x280015b Int BE Pri
94355!#5 N9142 P5853 MEMBAR
94356!#5 N9143 P5854 BSTC 0 0x420000d5 FP BE Pri
94357!#5 N9144 P5854 BSTC 1 0x420000d6 FP BE Pri
94358!#A N9143 N9144
94359!#5 N9145 P5854 BSTC 2 0x420000d7 FP BE Pri
94360!#5 N9146 P5855 MEMBAR
94361!#5 N9147 P5856 BLD 18 -1 FP BE Pri
94362!#5 N9148 P5856 BLD 19 -1 FP BE Pri
94363!#A N9147 N9148
94364!#5 N9149 P5856 BLD 20 -1 FP BE Pri
94365!#5 N9150 P5857 MEMBAR
94366!#5 N9151 P5858 DWLD 6 -1 Int BE Pri
94367!#5 N9152 P5858 DWLD 7 -1 Int BE Pri
94368!#A N9151 N9152
94369!#5 N9153 P5858 CASX 6 -1 N9151 0x280015c Int BE Pri
94370!#5 N9154 P5858 CASX 7 -1 N9152 0x280015d Int BE Pri
94371!#A N9153 N9154
94372!#5 N9155 P5859 LD 16 -1 Int BE Pri
94373!#5 N9156 P5860 LDD 9 -1 Int LE Pri
94374!#5 N9157 P5860 LDD 10 -1 Int LE Pri
94375!#A N9156 N9157
94376!#5 N9158 P5861 REPLACEMENT 17 Int BE Pri
94377!#5 N9159 P5862 REPLACEMENT 16 Int BE Pri
94378!#5 N9160 P5863 ST 17 0x280015e Int BE Pri
94379!#5 N9161 P5864 PREFETCH 14 Int BE Pri
94380!#5 N9162 P5865 SWAP 13 0xffffffff 0x280015f Int BE Pri
94381!#5 N9163 P5866 PREFETCH 11 Int BE Pri
94382!#5 N9164 P5867 DWST 18 0x2800160 Int BE Pri
94383!#5 N9165 P5867 DWST 19 0x2800161 Int BE Pri
94384!#A N9164 N9165
94385!#5 N9166 P5868 PREFETCH 17 Int BE Pri
94386!#5 N9167 P5869 ST_BINIT 0 0x2800162 Int BE Pri
94387!#5 N9168 P5870 MEMBAR
94388!#5 N9169 P5871 BSTC 15 0x420000d8 FP BE Pri
94389!#5 N9170 P5871 BSTC 16 0x420000d9 FP BE Pri
94390!#A N9169 N9170
94391!#5 N9171 P5871 BSTC 17 0x420000da FP BE Pri
94392!#5 N9172 P5872 MEMBAR
94393!#5 N9173 P5873 DWST 5 0x2800163 Int BE Pri
94394!#5 N9174 P5874 SWAP 1 0xffffffff 0x2800164 Int BE Pri
94395!#5 N9175 P5875 ST_BINIT 22 0x2800165 Int BE Pri
94396!#5 N9176 P5876 MEMBAR
94397!#5 N9177 P5877 ST 5 0x2800166 Int BE Pri
94398!#5 N9178 P5878 MEMBAR
94399!#5 N9179 P5879 BLD 18 -1 FP BE Pri
94400!#5 N9180 P5879 BLD 19 -1 FP BE Pri
94401!#A N9179 N9180
94402!#5 N9181 P5879 BLD 20 -1 FP BE Pri
94403!#5 N9182 P5880 MEMBAR
94404!#5 N9183 P5881 BSTC 3 0x420000db FP BE Pri
94405!#5 N9184 P5881 BSTC 4 0x420000dc FP BE Pri
94406!#A N9183 N9184
94407!#5 N9185 P5881 BSTC 5 0x420000dd FP BE Pri
94408!#5 N9186 P5882 MEMBAR
94409!#5 N9187 P5883 BLD 18 -1 FP BE Pri
94410!#5 N9188 P5883 BLD 19 -1 FP BE Pri
94411!#A N9187 N9188
94412!#5 N9189 P5883 BLD 20 -1 FP BE Pri
94413!#5 N9190 P5884 MEMBAR
94414!#5 N9191 P5885 LD 13 -1 Int BE Pri
94415!#5 N9192 P5885 CAS 13 -1 N9191 0x2800167 Int BE Pri
94416!#5 N9193 P5886 LDD 15 -1 Int BE Pri
94417!#5 N9194 P5886 LDD 16 -1 Int BE Pri
94418!#A N9193 N9194
94419!#5 N9195 P5887 LDD 8 -1 Int BE Pri
94420!#5 N9196 P5888 MEMBAR
94421!#5 N9197 P5889 BST 3 0x420000de FP BE Pri
94422!#5 N9198 P5889 BST 4 0x420000df FP BE Pri
94423!#A N9197 N9198
94424!#5 N9199 P5889 BST 5 0x420000e0 FP BE Pri
94425!#5 N9200 P5890 MEMBAR
94426!#5 N9201 P5891 DWST_BINIT 5 0x2800168 Int BE Pri
94427!#5 N9202 P5892 MEMBAR
94428!#5 N9203 P5893 PREFETCH 15 Int BE Pri
94429!#5 N9204 P5894 LD 21 -1 Int BE Pri
94430!#5 N9205 P5894 CAS 21 -1 N9204 0x2800169 Int BE Pri
94431!#5 N9206 P5895 ST 1 0x280016a Int LE Pri
94432!#5 N9207 P5896 MEMBAR
94433!#5 N9208 P5897 BST 0 0x420000e1 FP BE Pri
94434!#5 N9209 P5897 BST 1 0x420000e2 FP BE Pri
94435!#A N9208 N9209
94436!#5 N9210 P5897 BST 2 0x420000e3 FP BE Pri
94437!#5 N9211 P5898 MEMBAR
94438!#5 N9212 P5899 ST 4 0x280016b Int BE Pri
94439!#5 N9213 P5900 LD 17 -1 Int BE Pri
94440!#5 N9214 P5900 CAS 17 -1 N9213 0x280016c Int BE Pri
94441!#5 N9215 P5901 DWST 17 0x280016d Int BE Pri
94442!#5 N9216 P5902 DWLD 14 -1 Int BE Pri
94443!#5 N9217 P5903 LD 21 -1 Int BE Pri
94444!#5 N9218 P5904 SWAP 4 0xffffffff 0x280016e Int BE Pri
94445!#5 N9219 P5905 SWAP 4 0xffffffff 0x280016f Int BE Pri
94446!#5 N9220 P5906 MEMBAR
94447!#5 N9221 P5907 BLD 15 -1 FP BE Pri
94448!#5 N9222 P5907 BLD 16 -1 FP BE Pri
94449!#A N9221 N9222
94450!#5 N9223 P5907 BLD 17 -1 FP BE Pri
94451!#5 N9224 P5908 MEMBAR
94452!#5 N9225 P5909 BST 3 0x420000e4 FP BE Pri
94453!#5 N9226 P5909 BST 4 0x420000e5 FP BE Pri
94454!#A N9225 N9226
94455!#5 N9227 P5909 BST 5 0x420000e6 FP BE Pri
94456!#5 N9228 P5910 MEMBAR
94457!#5 N9229 P5911 DWLD 21 -1 Int BE Pri
94458!#5 N9230 P5911 DWLD 22 -1 Int BE Pri
94459!#A N9229 N9230
94460!#5 N9231 P5911 CASX 21 -1 N9229 0x2800170 Int BE Pri
94461!#5 N9232 P5911 CASX 22 -1 N9230 0x2800171 Int BE Pri
94462!#A N9231 N9232
94463!#5 N9233 P5912 ST 13 0x2800172 Int BE Pri
94464!#5 N9234 P5913 MEMBAR
94465!#5 N9235 P5914 BSTC 3 0x420000e7 FP BE Pri
94466!#5 N9236 P5914 BSTC 4 0x420000e8 FP BE Pri
94467!#A N9235 N9236
94468!#5 N9237 P5914 BSTC 5 0x420000e9 FP BE Pri
94469!#5 N9238 P5915 MEMBAR
94470!#5 N9239 P5916 LD 21 -1 Int BE Pri
94471!#5 N9240 P5917 DWST_BINIT 14 0x2800173 Int BE Pri
94472!#5 N9241 P5918 MEMBAR
94473!#5 N9242 P5919 ST 0 0x2800174 Int BE Pri
94474!#5 N9243 P5920 PREFETCH 4 Int BE Pri
94475!#5 N9244 P5921 PREFETCH 3 Int BE Pri
94476!#5 N9245 P5922 LD 20 -1 Int BE Pri
94477!#5 N9246 P5922 CAS 20 -1 N9245 0x2800175 Int BE Pri
94478!#5 N9247 P5923 SWAP 2 0xffffffff 0x2800176 Int BE Pri
94479!#5 N9248 P5924 SWAP 15 0xffffffff 0x2800177 Int BE Pri
94480!#5 N9249 P5925 DWST 17 0x2800178 Int BE Pri
94481!#5 N9250 P5926 ST 17 0x420000ea FP BE Pri
94482!#5 N9251 P5927 MEMBAR
94483!#5 N9252 P5928 BLD 12 -1 FP BE Pri
94484!#5 N9253 P5928 BLD 13 -1 FP BE Pri
94485!#A N9252 N9253
94486!#5 N9254 P5928 BLD 14 -1 FP BE Pri
94487!#5 N9255 P5929 MEMBAR
94488!#5 N9256 P5930 ST_BINIT 21 0x2800179 Int BE Pri
94489!#5 N9257 P5931 MEMBAR
94490!#5 N9258 P5932 BSTC 12 0x420000eb FP BE Pri
94491!#5 N9259 P5932 BSTC 13 0x420000ec FP BE Pri
94492!#A N9258 N9259
94493!#5 N9260 P5932 BSTC 14 0x420000ed FP BE Pri
94494!#5 N9261 P5933 MEMBAR
94495!#5 N9262 P5934 DWLD 21 -1 Int BE Pri
94496!#5 N9263 P5934 DWLD 22 -1 Int BE Pri
94497!#A N9262 N9263
94498!#5 N9264 P5934 CASX 21 -1 N9262 0x280017a Int BE Pri
94499!#5 N9265 P5934 CASX 22 -1 N9263 0x280017b Int BE Pri
94500!#A N9264 N9265
94501!#5 N9266 P5935 PREFETCH 8 Int BE Pri
94502!#5 N9267 P5936 ST_BINIT 10 0x280017c Int BE Pri
94503!#5 N9268 P5937 MEMBAR
94504!#5 N9269 P5938 ST 20 0x280017d Int BE Pri
94505!#5 N9270 P5939 DWLD 15 -1 FP BE Pri
94506!#5 N9271 P5939 DWLD 16 -1 FP BE Pri
94507!#A N9270 N9271
94508!#5 N9272 P5940 SWAP 13 0xffffffff 0x280017e Int BE Pri
94509!#5 N9273 P5941 ST 10 0x280017f Int BE Pri
94510!#5 N9274 P5942 MEMBAR
94511!#5 N9275 P5943 BSTC 6 0x420000ee FP BE Pri
94512!#5 N9276 P5943 BSTC 7 0x420000ef FP BE Pri
94513!#A N9275 N9276
94514!#5 N9277 P5943 BSTC 8 0x420000f0 FP BE Pri
94515!#5 N9278 P5944 MEMBAR
94516!#5 N9279 P5945 LDD 0 -1 Int BE Pri
94517!#5 N9280 P5945 LDD 1 -1 Int BE Pri
94518!#A N9279 N9280
94519!#5 N9281 P5946 ST_BINIT 17 0x2800180 Int BE Pri
94520!#5 N9282 P5947 MEMBAR
94521!#5 N9283 P5948 DWST 5 0x2800181 Int BE Pri
94522!#5 N9284 P5949 DWST 3 0x2800182 Int LE Pri
94523!#5 N9285 P5949 DWST 4 0x2800183 Int LE Pri
94524!#A N9284 N9285
94525!#5 N9286 P5950 SWAP 14 0xffffffff 0x2800184 Int BE Pri
94526!#5 N9287 P5951 MEMBAR
94527!#5 N9288 P5952 BST 21 0x420000f1 FP BE Pri
94528!#5 N9289 P5952 BST 22 0x420000f2 FP BE Pri
94529!#A N9288 N9289
94530!#5 N9290 P5952 BST 23 0x420000f3 FP BE Pri
94531!#5 N9291 P5953 MEMBAR
94532!#5 N9292 P5954 BSTC 18 0x420000f4 FP BE Pri
94533!#5 N9293 P5954 BSTC 19 0x420000f5 FP BE Pri
94534!#A N9292 N9293
94535!#5 N9294 P5954 BSTC 20 0x420000f6 FP BE Pri
94536!#5 N9295 P5955 MEMBAR
94537!#5 N9296 P5956 PREFETCH 18 Int BE Pri
94538!#5 N9297 P5957 DWLD 23 -1,0x0 Int BE Pri
94539!#5 N9298 P5957 CASX 23 -1,0x0 N9297 0x2800185 Int BE Pri
94540!#5 N9299 P5958 REPLACEMENT 22 Int BE Pri
94541!#5 N9300 P5959 PREFETCH 17 Int BE Pri
94542!#5 N9301 P5960 DWLD 14 -1,0x0 Int BE Pri
94543!#5 N9302 P5960 CASX 14 -1,0x0 N9301 0x2800186 Int BE Pri
94544!#5 N9303 P5961 LD 2 -1 Int BE Pri
94545!#5 N9304 P5962 DWLD 8 -1,0x0 Int BE Pri
94546!#5 N9305 P5962 CASX 8 -1,0x0 N9304 0x2800187 Int BE Pri
94547!#5 N9306 P5963 MEMBAR
94548!#5 N9307 P5964 BSTC 21 0x420000f7 FP BE Pri
94549!#5 N9308 P5964 BSTC 22 0x420000f8 FP BE Pri
94550!#A N9307 N9308
94551!#5 N9309 P5964 BSTC 23 0x420000f9 FP BE Pri
94552!#5 N9310 P5965 MEMBAR
94553!#5 N9311 P5966 DWST_BINIT 12 0x2800188 Int BE Pri
94554!#5 N9312 P5966 DWST_BINIT 13 0x2800189 Int BE Pri
94555!#A N9311 N9312
94556!#5 N9313 P5967 MEMBAR
94557!#5 N9314 P5968 LD 3 -1 Int BE Pri
94558!#5 N9315 P5968 CAS 3 -1 N9314 0x280018a Int BE Pri
94559!#5 N9316 P5969 MEMBAR
94560!#5 N9317 P5970 BLD 6 -1 FP BE Pri
94561!#5 N9318 P5970 BLD 7 -1 FP BE Pri
94562!#A N9317 N9318
94563!#5 N9319 P5970 BLD 8 -1 FP BE Pri
94564!#5 N9320 P5971 MEMBAR
94565!#5 N9321 P5972 DWLD 20 -1 Int BE Pri
94566!#5 N9322 P5973 DWST_BINIT 0 0x280018b Int BE Pri
94567!#5 N9323 P5973 DWST_BINIT 1 0x280018c Int BE Pri
94568!#A N9322 N9323
94569!#5 N9324 P5974 MEMBAR
94570!#5 N9325 P5975 DWLD 2 -1 Int BE Pri
94571!#5 N9326 P5976 REPLACEMENT 12 Int BE Pri
94572!#5 N9327 P5977 LDD 18 -1 Int BE Pri
94573!#5 N9328 P5977 LDD 19 -1 Int BE Pri
94574!#A N9327 N9328
94575!#5 N9329 P5978 ST_BINIT 1 0x280018d Int BE Pri
94576!#5 N9330 P5979 MEMBAR
94577!#5 N9331 P5980 LDD 14 -1 Int BE Pri
94578!#5 N9332 P5981 SWAP 12 0xffffffff 0x280018e Int BE Pri
94579!#5 N9333 P5982 ST 23 0x280018f Int BE Pri
94580!#5 N9334 P5983 DWLD 0 -1 Int BE Pri
94581!#5 N9335 P5983 DWLD 1 -1 Int BE Pri
94582!#A N9334 N9335
94583!#5 N9336 P5983 CASX 0 -1 N9334 0x2800190 Int BE Pri
94584!#5 N9337 P5983 CASX 1 -1 N9335 0x2800191 Int BE Pri
94585!#A N9336 N9337
94586!#5 N9338 P5984 MEMBAR
94587!#5 N9339 P5985 BLD 12 -1 FP BE Pri
94588!#5 N9340 P5985 BLD 13 -1 FP BE Pri
94589!#A N9339 N9340
94590!#5 N9341 P5985 BLD 14 -1 FP BE Pri
94591!#5 N9342 P5986 MEMBAR
94592!#5 N9343 P5987 DWLD 0 -1 Int LE Pri
94593!#5 N9344 P5987 DWLD 1 -1 Int LE Pri
94594!#A N9343 N9344
94595!#5 N9345 P5988 ST_BINIT 7 0x2800192 Int LE Pri
94596!#5 N9346 P5989 MEMBAR
94597!#5 N9347 P5990 DWST_BINIT 21 0x2800193 Int BE Pri
94598!#5 N9348 P5990 DWST_BINIT 22 0x2800194 Int BE Pri
94599!#A N9347 N9348
94600!#5 N9349 P5991 MEMBAR
94601!#5 N9350 P5992 LD 21 -1 Int BE Pri
94602!#5 N9351 P5992 CAS 21 -1 N9350 0x2800195 Int BE Pri
94603!#5 N9352 P5993 MEMBAR
94604!#5 N9353 P5994 BST 15 0x420000fa FP BE Pri
94605!#5 N9354 P5994 BST 16 0x420000fb FP BE Pri
94606!#A N9353 N9354
94607!#5 N9355 P5994 BST 17 0x420000fc FP BE Pri
94608!#5 N9356 P5995 MEMBAR
94609!#5 N9357 P5996 BST 3 0x420000fd FP BE Pri
94610!#5 N9358 P5996 BST 4 0x420000fe FP BE Pri
94611!#A N9357 N9358
94612!#5 N9359 P5996 BST 5 0x420000ff FP BE Pri
94613!#5 N9360 P5997 MEMBAR
94614!#5 N9361 P5998 LD 14 -1 Int BE Pri
94615!#5 N9362 P5998 CAS 14 -1 N9361 0x2800196 Int BE Pri
94616!#5 N9363 P5999 LD 22 -1 Int BE Pri
94617!#5 N9364 P6000 ST 19 0x2800197 Int BE Pri
94618!#5 N9365 P6001 ST_BINIT 14 0x2800198 Int BE Pri
94619!#5 N9366 P6002 MEMBAR
94620!#5 N9367 P6003 DWLD 17 -1,0x0 Int BE Pri
94621!#5 N9368 P6003 CASX 17 -1,0x0 N9367 0x2800199 Int BE Pri
94622!#5 N9369 P6004 DWST_BINIT 3 0x280019a Int LE Pri
94623!#5 N9370 P6004 DWST_BINIT 4 0x280019b Int LE Pri
94624!#A N9369 N9370
94625!#5 N9371 P6005 MEMBAR
94626!#5 N9372 P6006 LD 1 -1 FP BE Pri
94627!#5 N9373 P6007 PREFETCH 11 Int BE Pri
94628!#5 N9374 P6008 ST_BINIT 20 0x280019c Int BE Pri
94629!#5 N9375 P6009 MEMBAR
94630!#5 N9376 P6010 DWLD 3 -1 Int BE Pri
94631!#5 N9377 P6010 DWLD 4 -1 Int BE Pri
94632!#A N9376 N9377
94633!#5 N9378 P6011 MEMBAR
94634!#5 N9379 P6012 BST 15 0x42000100 FP BE Pri
94635!#5 N9380 P6012 BST 16 0x42000101 FP BE Pri
94636!#A N9379 N9380
94637!#5 N9381 P6012 BST 17 0x42000102 FP BE Pri
94638!#5 N9382 P6013 MEMBAR
94639!#5 N9383 P6014 MEMBAR
94640!#6 N9384 P6015 LD 6 -1 Int BE Pri Loop_entry
94641!#6 N9385 P6015 CAS 6 -1 N9384 0x3000001 Int BE Pri Loop_entry
94642!#6 N9386 P6016 LDD 3 -1 Int BE Pri
94643!#6 N9387 P6016 LDD 4 -1 Int BE Pri
94644!#A N9386 N9387
94645!#6 N9388 P6017 DWST 17 0x3000002 Int BE Pri
94646!#6 N9389 P6018 SWAP 10 0xffffffff 0x3000003 Int LE Pri
94647!#6 N9390 P6019 DWST 3 0x3000004 Int BE Pri
94648!#6 N9391 P6019 DWST 4 0x3000005 Int BE Pri
94649!#A N9390 N9391
94650!#6 N9392 P6020 DWLD 3 -1 Int BE Pri
94651!#6 N9393 P6020 DWLD 4 -1 Int BE Pri
94652!#A N9392 N9393
94653!#6 N9394 P6020 CASX 3 -1 N9392 0x3000006 Int BE Pri
94654!#6 N9395 P6020 CASX 4 -1 N9393 0x3000007 Int BE Pri
94655!#A N9394 N9395
94656!#6 N9396 P6021 LD 11 -1 FP BE Pri
94657!#6 N9397 P6022 PREFETCH 0 Int BE Pri
94658!#6 N9398 P6023 DWLD 15 -1 Int LE Pri
94659!#6 N9399 P6023 DWLD 16 -1 Int LE Pri
94660!#A N9398 N9399
94661!#6 N9400 P6024 LD 16 -1 Int BE Pri
94662!#6 N9401 P6025 LDD 3 -1 Int BE Pri
94663!#6 N9402 P6025 LDD 4 -1 Int BE Pri
94664!#A N9401 N9402
94665!#6 N9403 P6026 REPLACEMENT 17 Int BE Pri
94666!#6 N9404 P6027 LDD 6 -1 Int BE Pri
94667!#6 N9405 P6027 LDD 7 -1 Int BE Pri
94668!#A N9404 N9405
94669!#6 N9406 P6028 MEMBAR
94670!#6 N9407 P6029 BST 6 0x42800001 FP BE Pri
94671!#6 N9408 P6029 BST 7 0x42800002 FP BE Pri
94672!#A N9407 N9408
94673!#6 N9409 P6029 BST 8 0x42800003 FP BE Pri
94674!#6 N9410 P6030 MEMBAR
94675!#6 N9411 P6031 ST_BINIT 17 0x3000008 Int BE Pri
94676!#6 N9412 P6032 MEMBAR
94677!#6 N9413 P6033 BST 18 0x42800004 FP BE Pri
94678!#6 N9414 P6033 BST 19 0x42800005 FP BE Pri
94679!#A N9413 N9414
94680!#6 N9415 P6033 BST 20 0x42800006 FP BE Pri
94681!#6 N9416 P6034 MEMBAR
94682!#6 N9417 P6035 DWST_BINIT 6 0x3000009 Int BE Pri
94683!#6 N9418 P6035 DWST_BINIT 7 0x300000a Int BE Pri
94684!#A N9417 N9418
94685!#6 N9419 P6036 MEMBAR
94686!#6 N9420 P6037 SWAP 8 0xffffffff 0x300000b Int BE Pri
94687!#6 N9421 P6038 SWAP 0 0xffffffff 0x300000c Int BE Pri
94688!#6 N9422 P6039 ST_BINIT 4 0x300000d Int BE Pri
94689!#6 N9423 P6040 MEMBAR
94690!#6 N9424 P6041 BSTC 6 0x42800007 FP BE Pri
94691!#6 N9425 P6041 BSTC 7 0x42800008 FP BE Pri
94692!#A N9424 N9425
94693!#6 N9426 P6041 BSTC 8 0x42800009 FP BE Pri
94694!#6 N9427 P6042 MEMBAR
94695!#6 N9428 P6043 ST_BINIT 16 0x300000e Int BE Pri
94696!#6 N9429 P6044 MEMBAR
94697!#6 N9430 P6045 LD 2 -1 Int BE Pri
94698!#6 N9431 P6046 SWAP 3 0xffffffff 0x300000f Int BE Pri
94699!#6 N9432 P6047 LDD 8 -1 Int BE Pri
94700!#6 N9433 P6048 ST 13 0x3000010 Int BE Pri
94701!#6 N9434 P6049 DWST_BINIT 3 0x3000011 Int BE Pri
94702!#6 N9435 P6049 DWST_BINIT 4 0x3000012 Int BE Pri
94703!#A N9434 N9435
94704!#6 N9436 P6050 MEMBAR
94705!#6 N9437 P6051 SWAP 14 0xffffffff 0x3000013 Int BE Pri
94706!#6 N9438 P6052 MEMBAR
94707!#6 N9439 P6053 BLD 0 -1 FP BE Pri
94708!#6 N9440 P6053 BLD 1 -1 FP BE Pri
94709!#A N9439 N9440
94710!#6 N9441 P6053 BLD 2 -1 FP BE Pri
94711!#6 N9442 P6054 MEMBAR
94712!#6 N9443 P6055 LDD 8 -1 Int LE Pri
94713!#6 N9444 P6056 ST 18 0x3000014 Int LE Pri
94714!#6 N9445 P6057 SWAP 12 0xffffffff 0x3000015 Int BE Pri
94715!#6 N9446 P6058 SWAP 19 0xffffffff 0x3000016 Int BE Pri
94716!#6 N9447 P6059 SWAP 3 0xffffffff 0x3000017 Int BE Pri
94717!#6 N9448 P6060 ST_BINIT 17 0x3000018 Int BE Pri
94718!#6 N9449 P6061 MEMBAR
94719!#6 N9450 P6062 BLD 0 -1 FP BE Pri
94720!#6 N9451 P6062 BLD 1 -1 FP BE Pri
94721!#A N9450 N9451
94722!#6 N9452 P6062 BLD 2 -1 FP BE Pri
94723!#6 N9453 P6063 MEMBAR
94724!#6 N9454 P6064 LD 1 -1 Int BE Pri
94725!#6 N9455 P6065 LDD 14 -1 Int BE Pri
94726!#6 N9456 P6066 DWLD 0 -1 Int BE Pri
94727!#6 N9457 P6066 DWLD 1 -1 Int BE Pri
94728!#A N9456 N9457
94729!#6 N9458 P6067 DWST 2 0x3000019 Int LE Pri
94730!#6 N9459 P6068 MEMBAR
94731!#6 N9460 P6069 BSTC 3 0x4280000a FP BE Pri
94732!#6 N9461 P6069 BSTC 4 0x4280000b FP BE Pri
94733!#A N9460 N9461
94734!#6 N9462 P6069 BSTC 5 0x4280000c FP BE Pri
94735!#6 N9463 P6070 MEMBAR
94736!#6 N9464 P6071 DWST 14 0x300001a Int BE Pri
94737!#6 N9465 P6072 DWST 2 0x300001b Int BE Pri
94738!#6 N9466 P6073 DWST_BINIT 21 0x300001c Int BE Pri
94739!#6 N9467 P6073 DWST_BINIT 22 0x300001d Int BE Pri
94740!#A N9466 N9467
94741!#6 N9468 P6074 MEMBAR
94742!#6 N9469 P6075 ST_BINIT 22 0x300001e Int BE Pri
94743!#6 N9470 P6076 MEMBAR
94744!#6 N9471 P6077 PREFETCH 5 Int BE Pri
94745!#6 N9472 P6078 MEMBAR
94746!#6 N9473 P6079 BLD 12 -1 FP BE Pri
94747!#6 N9474 P6079 BLD 13 -1 FP BE Pri
94748!#A N9473 N9474
94749!#6 N9475 P6079 BLD 14 -1 FP BE Pri
94750!#6 N9476 P6080 MEMBAR
94751!#6 N9477 P6081 ST_BINIT 22 0x300001f Int BE Pri
94752!#6 N9478 P6082 MEMBAR
94753!#6 N9479 P6083 DWLD 12 -1 Int BE Pri
94754!#6 N9480 P6083 DWLD 13 -1 Int BE Pri
94755!#A N9479 N9480
94756!#6 N9481 P6084 ST 21 0x3000020 Int LE Pri
94757!#6 N9482 P6085 MEMBAR
94758!#6 N9483 P6086 BLD 9 -1 FP BE Pri
94759!#6 N9484 P6086 BLD 10 -1 FP BE Pri
94760!#A N9483 N9484
94761!#6 N9485 P6086 BLD 11 -1 FP BE Pri
94762!#6 N9486 P6087 MEMBAR
94763!#6 N9487 P6088 DWST_BINIT 17 0x3000021 Int BE Pri
94764!#6 N9488 P6089 MEMBAR
94765!#6 N9489 P6090 ST 23 0x4280000d FP BE Pri
94766!#6 N9490 P6091 REPLACEMENT 9 Int BE Pri
94767!#6 N9491 P6092 MEMBAR
94768!#6 N9492 P6093 BLD 15 -1 FP BE Pri
94769!#6 N9493 P6093 BLD 16 -1 FP BE Pri
94770!#A N9492 N9493
94771!#6 N9494 P6093 BLD 17 -1 FP BE Pri
94772!#6 N9495 P6094 MEMBAR
94773!#6 N9496 P6095 PREFETCH 21 Int BE Pri
94774!#6 N9497 P6096 SWAP 14 0xffffffff 0x3000022 Int BE Pri
94775!#6 N9498 P6097 LD 9 -1 FP BE Pri
94776!#6 N9499 P6098 ST_BINIT 8 0x3000023 Int BE Pri
94777!#6 N9500 P6099 MEMBAR
94778!#6 N9501 P6100 DWST_BINIT 0 0x3000024 Int BE Pri
94779!#6 N9502 P6100 DWST_BINIT 1 0x3000025 Int BE Pri
94780!#A N9501 N9502
94781!#6 N9503 P6101 MEMBAR
94782!#6 N9504 P6102 LD 11 -1 Int BE Pri
94783!#6 N9505 P6103 LDD 21 -1 Int BE Pri
94784!#6 N9506 P6103 LDD 22 -1 Int BE Pri
94785!#A N9505 N9506
94786!#6 N9507 P6104 SWAP 12 0xffffffff 0x3000026 Int BE Pri
94787!#6 N9508 P6105 DWST 2 0x3000027 Int BE Pri
94788!#6 N9509 P6106 MEMBAR
94789!#6 N9510 P6107 BST 6 0x4280000e FP BE Pri
94790!#6 N9511 P6107 BST 7 0x4280000f FP BE Pri
94791!#A N9510 N9511
94792!#6 N9512 P6107 BST 8 0x42800010 FP BE Pri
94793!#6 N9513 P6108 MEMBAR
94794!#6 N9514 P6109 BLD 12 -1 FP BE Pri
94795!#6 N9515 P6109 BLD 13 -1 FP BE Pri
94796!#A N9514 N9515
94797!#6 N9516 P6109 BLD 14 -1 FP BE Pri
94798!#6 N9517 P6110 MEMBAR
94799!#6 N9518 P6111 DWST 18 0x3000028 Int BE Pri
94800!#6 N9519 P6111 DWST 19 0x3000029 Int BE Pri
94801!#A N9518 N9519
94802!#6 N9520 P6112 DWST 3 0x300002a Int BE Pri
94803!#6 N9521 P6112 DWST 4 0x300002b Int BE Pri
94804!#A N9520 N9521
94805!#6 N9522 P6113 SWAP 8 0xffffffff 0x300002c Int BE Pri
94806!#6 N9523 P6114 DWST_BINIT 14 0x300002d Int BE Pri
94807!#6 N9524 P6115 MEMBAR
94808!#6 N9525 P6116 DWST_BINIT 20 0x300002e Int BE Pri
94809!#6 N9526 P6117 MEMBAR
94810!#6 N9527 P6118 BST 6 0x42800011 FP BE Pri
94811!#6 N9528 P6118 BST 7 0x42800012 FP BE Pri
94812!#A N9527 N9528
94813!#6 N9529 P6118 BST 8 0x42800013 FP BE Pri
94814!#6 N9530 P6119 MEMBAR
94815!#6 N9531 P6120 DWLD 6 -1 Int BE Pri
94816!#6 N9532 P6120 DWLD 7 -1 Int BE Pri
94817!#A N9531 N9532
94818!#6 N9533 P6121 DWST_BINIT 3 0x300002f Int BE Pri
94819!#6 N9534 P6121 DWST_BINIT 4 0x3000030 Int BE Pri
94820!#A N9533 N9534
94821!#6 N9535 P6122 MEMBAR
94822!#6 N9536 P6123 ST_BINIT 0 0x3000031 Int BE Pri
94823!#6 N9537 P6124 MEMBAR
94824!#6 N9538 P6125 LDD 6 -1 Int BE Pri
94825!#6 N9539 P6125 LDD 7 -1 Int BE Pri
94826!#A N9538 N9539
94827!#6 N9540 P6126 MEMBAR
94828!#6 N9541 P6127 BSTC 9 0x42800014 FP BE Pri
94829!#6 N9542 P6127 BSTC 10 0x42800015 FP BE Pri
94830!#A N9541 N9542
94831!#6 N9543 P6127 BSTC 11 0x42800016 FP BE Pri
94832!#6 N9544 P6128 MEMBAR
94833!#6 N9545 P6129 LDD 3 -1 Int BE Pri
94834!#6 N9546 P6129 LDD 4 -1 Int BE Pri
94835!#A N9545 N9546
94836!#6 N9547 P6130 MEMBAR
94837!#6 N9548 P6131 BST 21 0x42800017 FP BE Pri
94838!#6 N9549 P6131 BST 22 0x42800018 FP BE Pri
94839!#A N9548 N9549
94840!#6 N9550 P6131 BST 23 0x42800019 FP BE Pri
94841!#6 N9551 P6132 MEMBAR
94842!#6 N9552 P6133 LD 18 -1 Int BE Pri
94843!#6 N9553 P6133 CAS 18 -1 N9552 0x3000032 Int BE Pri
94844!#6 N9554 P6134 ST_BINIT 2 0x3000033 Int BE Pri
94845!#6 N9555 P6135 MEMBAR
94846!#6 N9556 P6136 LD 13 -1 Int BE Pri
94847!#6 N9557 P6136 CAS 13 -1 N9556 0x3000034 Int BE Pri
94848!#6 N9558 P6137 LDD 0 -1 Int BE Pri
94849!#6 N9559 P6137 LDD 1 -1 Int BE Pri
94850!#A N9558 N9559
94851!#6 N9560 P6138 DWST 23 0x3000035 Int LE Pri
94852!#6 N9561 P6139 DWST 0 0x3000036 Int BE Pri
94853!#6 N9562 P6139 DWST 1 0x3000037 Int BE Pri
94854!#A N9561 N9562
94855!#6 N9563 P6140 DWST_BINIT 0 0x3000038 Int BE Pri
94856!#6 N9564 P6140 DWST_BINIT 1 0x3000039 Int BE Pri
94857!#A N9563 N9564
94858!#6 N9565 P6141 MEMBAR
94859!#6 N9566 P6142 BLD 3 -1 FP BE Pri
94860!#6 N9567 P6142 BLD 4 -1 FP BE Pri
94861!#A N9566 N9567
94862!#6 N9568 P6142 BLD 5 -1 FP BE Pri
94863!#6 N9569 P6143 MEMBAR
94864!#6 N9570 P6144 DWST_BINIT 15 0x300003a Int BE Pri
94865!#6 N9571 P6144 DWST_BINIT 16 0x300003b Int BE Pri
94866!#A N9570 N9571
94867!#6 N9572 P6145 MEMBAR
94868!#6 N9573 P6146 PREFETCH 16 Int BE Pri
94869!#6 N9574 P6147 MEMBAR
94870!#6 N9575 P6148 BSTC 12 0x4280001a FP BE Pri
94871!#6 N9576 P6148 BSTC 13 0x4280001b FP BE Pri
94872!#A N9575 N9576
94873!#6 N9577 P6148 BSTC 14 0x4280001c FP BE Pri
94874!#6 N9578 P6149 MEMBAR
94875!#6 N9579 P6150 DWLD 11 -1,0x0 Int BE Pri
94876!#6 N9580 P6150 CASX 11 -1,0x0 N9579 0x300003c Int BE Pri
94877!#6 N9581 P6151 LD 16 -1 Int BE Pri
94878!#6 N9582 P6151 CAS 16 -1 N9581 0x300003d Int BE Pri
94879!#6 N9583 P6152 ST_BINIT 7 0x300003e Int BE Pri
94880!#6 N9584 P6153 MEMBAR
94881!#6 N9585 P6154 LD 14 -1 Int BE Pri
94882!#6 N9586 P6155 DWST 12 0x300003f Int BE Pri
94883!#6 N9587 P6155 DWST 13 0x3000040 Int BE Pri
94884!#A N9586 N9587
94885!#6 N9588 P6156 MEMBAR
94886!#6 N9589 P6157 BSTC 6 0x4280001d FP BE Pri
94887!#6 N9590 P6157 BSTC 7 0x4280001e FP BE Pri
94888!#A N9589 N9590
94889!#6 N9591 P6157 BSTC 8 0x4280001f FP BE Pri
94890!#6 N9592 P6158 MEMBAR
94891!#6 N9593 P6159 LDD 3 -1 Int BE Pri
94892!#6 N9594 P6159 LDD 4 -1 Int BE Pri
94893!#A N9593 N9594
94894!#6 N9595 P6160 MEMBAR
94895!#6 N9596 P6161 BST 18 0x42800020 FP BE Pri
94896!#6 N9597 P6161 BST 19 0x42800021 FP BE Pri
94897!#A N9596 N9597
94898!#6 N9598 P6161 BST 20 0x42800022 FP BE Pri
94899!#6 N9599 P6162 MEMBAR
94900!#6 N9600 P6163 DWLD 0 -1 Int BE Pri
94901!#6 N9601 P6163 DWLD 1 -1 Int BE Pri
94902!#A N9600 N9601
94903!#6 N9602 P6163 CASX 0 -1 N9600 0x3000041 Int BE Pri
94904!#6 N9603 P6163 CASX 1 -1 N9601 0x3000042 Int BE Pri
94905!#A N9602 N9603
94906!#6 N9604 P6164 DWST_BINIT 9 0x3000043 Int BE Pri
94907!#6 N9605 P6164 DWST_BINIT 10 0x3000044 Int BE Pri
94908!#A N9604 N9605
94909!#6 N9606 P6165 MEMBAR
94910!#6 N9607 P6166 PREFETCH 22 Int BE Pri
94911!#6 N9608 P6167 MEMBAR
94912!#6 N9609 P6168 BST 12 0x42800023 FP BE Pri
94913!#6 N9610 P6168 BST 13 0x42800024 FP BE Pri
94914!#A N9609 N9610
94915!#6 N9611 P6168 BST 14 0x42800025 FP BE Pri
94916!#6 N9612 P6169 MEMBAR
94917!#6 N9613 P6170 ST 0 0x3000045 Int BE Pri
94918!#6 N9614 P6171 MEMBAR
94919!#6 N9615 P6172 BLD 3 -1 FP BE Pri
94920!#6 N9616 P6172 BLD 4 -1 FP BE Pri
94921!#A N9615 N9616
94922!#6 N9617 P6172 BLD 5 -1 FP BE Pri
94923!#6 N9618 P6173 MEMBAR
94924!#6 N9619 P6174 LD 16 -1 Int BE Pri
94925!#6 N9620 P6174 CAS 16 -1 N9619 0x3000046 Int BE Pri
94926!#6 N9621 P6175 DWLD 8 -1,0x0 Int BE Pri
94927!#6 N9622 P6175 CASX 8 -1,0x0 N9621 0x3000047 Int BE Pri
94928!#6 N9623 P6176 REPLACEMENT 6 Int BE Pri
94929!#6 N9624 P6177 MEMBAR
94930!#6 N9625 P6178 BSTC 12 0x42800026 FP BE Pri
94931!#6 N9626 P6178 BSTC 13 0x42800027 FP BE Pri
94932!#A N9625 N9626
94933!#6 N9627 P6178 BSTC 14 0x42800028 FP BE Pri
94934!#6 N9628 P6179 MEMBAR
94935!#6 N9629 P6180 BLD 6 -1 FP BE Pri
94936!#6 N9630 P6180 BLD 7 -1 FP BE Pri
94937!#A N9629 N9630
94938!#6 N9631 P6180 BLD 8 -1 FP BE Pri
94939!#6 N9632 P6181 MEMBAR
94940!#6 N9633 P6182 DWST_BINIT 15 0x3000048 Int BE Pri
94941!#6 N9634 P6182 DWST_BINIT 16 0x3000049 Int BE Pri
94942!#A N9633 N9634
94943!#6 N9635 P6183 MEMBAR
94944!#6 N9636 P6184 DWLD 3 -1 Int BE Pri
94945!#6 N9637 P6184 DWLD 4 -1 Int BE Pri
94946!#A N9636 N9637
94947!#6 N9638 P6185 PREFETCH 9 Int BE Pri
94948!#6 N9639 P6186 PREFETCH 10 Int BE Pri
94949!#6 N9640 P6187 ST 17 0x300004a Int BE Pri
94950!#6 N9641 P6188 MEMBAR
94951!#6 N9642 P6189 BST 12 0x42800029 FP BE Pri
94952!#6 N9643 P6189 BST 13 0x4280002a FP BE Pri
94953!#A N9642 N9643
94954!#6 N9644 P6189 BST 14 0x4280002b FP BE Pri
94955!#6 N9645 P6190 MEMBAR
94956!#6 N9646 P6191 SWAP 6 0xffffffff 0x300004b Int BE Pri
94957!#6 N9647 P6192 SWAP 3 0xffffffff 0x300004c Int BE Pri
94958!#6 N9648 P6193 LD 11 -1 Int BE Pri
94959!#6 N9649 P6193 CAS 11 -1 N9648 0x300004d Int BE Pri
94960!#6 N9650 P6194 ST_BINIT 7 0x300004e Int BE Pri
94961!#6 N9651 P6195 MEMBAR
94962!#6 N9652 P6196 BSTC 15 0x4280002c FP BE Pri
94963!#6 N9653 P6196 BSTC 16 0x4280002d FP BE Pri
94964!#A N9652 N9653
94965!#6 N9654 P6196 BSTC 17 0x4280002e FP BE Pri
94966!#6 N9655 P6197 MEMBAR
94967!#6 N9656 P6198 LDD 12 -1 Int BE Pri
94968!#6 N9657 P6198 LDD 13 -1 Int BE Pri
94969!#A N9656 N9657
94970!#6 N9658 P6199 DWLD 12 -1 Int BE Pri
94971!#6 N9659 P6199 DWLD 13 -1 Int BE Pri
94972!#A N9658 N9659
94973!#6 N9660 P6199 CASX 12 -1 N9658 0x300004f Int BE Pri
94974!#6 N9661 P6199 CASX 13 -1 N9659 0x3000050 Int BE Pri
94975!#A N9660 N9661
94976!#6 N9662 P6200 REPLACEMENT 23 Int BE Pri
94977!#6 N9663 P6201 ST 7 0x3000051 Int BE Pri
94978!#6 N9664 P6202 ST 9 0x3000052 Int BE Pri
94979!#6 N9665 P6203 PREFETCH 16 Int BE Pri
94980!#6 N9666 P6204 LD 1 -1 Int BE Pri
94981!#6 N9667 P6204 CAS 1 -1 N9666 0x3000053 Int BE Pri
94982!#6 N9668 P6205 ST_BINIT 2 0x3000054 Int BE Pri
94983!#6 N9669 P6206 MEMBAR
94984!#6 N9670 P6207 ST 4 0x3000055 Int BE Pri
94985!#6 N9671 P6208 MEMBAR
94986!#6 N9672 P6209 BSTC 0 0x4280002f FP BE Pri
94987!#6 N9673 P6209 BSTC 1 0x42800030 FP BE Pri
94988!#A N9672 N9673
94989!#6 N9674 P6209 BSTC 2 0x42800031 FP BE Pri
94990!#6 N9675 P6210 MEMBAR
94991!#6 N9676 P6211 SWAP 22 0xffffffff 0x3000056 Int BE Pri
94992!#6 N9677 P6212 MEMBAR
94993!#6 N9678 P6213 BSTC 15 0x42800032 FP BE Pri
94994!#6 N9679 P6213 BSTC 16 0x42800033 FP BE Pri
94995!#A N9678 N9679
94996!#6 N9680 P6213 BSTC 17 0x42800034 FP BE Pri
94997!#6 N9681 P6214 MEMBAR
94998!#6 N9682 P6215 DWST 12 0x3000057 Int BE Pri
94999!#6 N9683 P6215 DWST 13 0x3000058 Int BE Pri
95000!#A N9682 N9683
95001!#6 N9684 P6216 MEMBAR
95002!#6 N9685 P6217 BST 21 0x42800035 FP BE Pri
95003!#6 N9686 P6217 BST 22 0x42800036 FP BE Pri
95004!#A N9685 N9686
95005!#6 N9687 P6217 BST 23 0x42800037 FP BE Pri
95006!#6 N9688 P6218 MEMBAR
95007!#6 N9689 P6219 PREFETCH 17 Int BE Pri
95008!#6 N9690 P6220 MEMBAR
95009!#6 N9691 P6221 BST 3 0x42800038 FP BE Pri
95010!#6 N9692 P6221 BST 4 0x42800039 FP BE Pri
95011!#A N9691 N9692
95012!#6 N9693 P6221 BST 5 0x4280003a FP BE Pri
95013!#6 N9694 P6222 MEMBAR
95014!#6 N9695 P6223 REPLACEMENT 14 Int BE Pri
95015!#6 N9696 P6224 DWST_BINIT 0 0x3000059 Int BE Pri
95016!#6 N9697 P6224 DWST_BINIT 1 0x300005a Int BE Pri
95017!#A N9696 N9697
95018!#6 N9698 P6225 MEMBAR
95019!#6 N9699 P6226 BLD 12 -1 FP BE Pri
95020!#6 N9700 P6226 BLD 13 -1 FP BE Pri
95021!#A N9699 N9700
95022!#6 N9701 P6226 BLD 14 -1 FP BE Pri
95023!#6 N9702 P6227 MEMBAR
95024!#6 N9703 P6228 LD 22 -1 Int BE Pri
95025!#6 N9704 P6228 CAS 22 -1 N9703 0x300005b Int BE Pri
95026!#6 N9705 P6229 PREFETCH 5 Int BE Pri
95027!#6 N9706 P6230 MEMBAR
95028!#6 N9707 P6231 BSTC 0 0x4280003b FP BE Pri
95029!#6 N9708 P6231 BSTC 1 0x4280003c FP BE Pri
95030!#A N9707 N9708
95031!#6 N9709 P6231 BSTC 2 0x4280003d FP BE Pri
95032!#6 N9710 P6232 MEMBAR
95033!#6 N9711 P6233 LD 1 -1 Int BE Pri
95034!#6 N9712 P6234 LDD 15 -1 Int BE Pri
95035!#6 N9713 P6234 LDD 16 -1 Int BE Pri
95036!#A N9712 N9713
95037!#6 N9714 P6235 LD 12 -1 Int BE Pri
95038!#6 N9715 P6236 DWLD 15 -1 Int BE Pri
95039!#6 N9716 P6236 DWLD 16 -1 Int BE Pri
95040!#A N9715 N9716
95041!#6 N9717 P6237 LD 9 -1 FP BE Pri
95042!#6 N9718 P6238 DWLD 5 -1 Int BE Pri
95043!#6 N9719 P6239 ST_BINIT 13 0x300005c Int BE Pri
95044!#6 N9720 P6240 MEMBAR
95045!#6 N9721 P6241 BLD 12 -1 FP BE Pri
95046!#6 N9722 P6241 BLD 13 -1 FP BE Pri
95047!#A N9721 N9722
95048!#6 N9723 P6241 BLD 14 -1 FP BE Pri
95049!#6 N9724 P6242 MEMBAR
95050!#6 N9725 P6243 DWST_BINIT 18 0x300005d Int BE Pri
95051!#6 N9726 P6243 DWST_BINIT 19 0x300005e Int BE Pri
95052!#A N9725 N9726
95053!#6 N9727 P6244 MEMBAR
95054!#6 N9728 P6245 DWST_BINIT 17 0x300005f Int BE Pri
95055!#6 N9729 P6246 MEMBAR
95056!#6 N9730 P6247 LD 0 -1 Int BE Pri
95057!#6 N9731 P6247 CAS 0 -1 N9730 0x3000060 Int BE Pri
95058!#6 N9732 P6248 LD 2 -1 Int BE Pri
95059!#6 N9733 P6249 LD 18 -1 Int LE Pri
95060!#6 N9734 P6249 CAS 18 -1 N9733 0x3000061 Int LE Pri
95061!#6 N9735 P6250 ST 1 0x4280003e FP BE Pri
95062!#6 N9736 P6251 MEMBAR
95063!#6 N9737 P6252 BLD 12 -1 FP BE Pri
95064!#6 N9738 P6252 BLD 13 -1 FP BE Pri
95065!#A N9737 N9738
95066!#6 N9739 P6252 BLD 14 -1 FP BE Pri
95067!#6 N9740 P6253 MEMBAR
95068!#6 N9741 P6254 DWST_BINIT 8 0x3000062 Int BE Pri
95069!#6 N9742 P6255 MEMBAR
95070!#6 N9743 P6256 SWAP 6 0xffffffff 0x3000063 Int BE Pri
95071!#6 N9744 P6257 MEMBAR
95072!#6 N9745 P6258 BSTC 6 0x4280003f FP BE Pri
95073!#6 N9746 P6258 BSTC 7 0x42800040 FP BE Pri
95074!#A N9745 N9746
95075!#6 N9747 P6258 BSTC 8 0x42800041 FP BE Pri
95076!#6 N9748 P6259 MEMBAR
95077!#6 N9749 P6260 BLD 3 -1 FP BE Pri
95078!#6 N9750 P6260 BLD 4 -1 FP BE Pri
95079!#A N9749 N9750
95080!#6 N9751 P6260 BLD 5 -1 FP BE Pri
95081!#6 N9752 P6261 MEMBAR
95082!#6 N9753 P6262 BLD 15 -1 FP BE Pri
95083!#6 N9754 P6262 BLD 16 -1 FP BE Pri
95084!#A N9753 N9754
95085!#6 N9755 P6262 BLD 17 -1 FP BE Pri
95086!#6 N9756 P6263 MEMBAR
95087!#6 N9757 P6264 ST_BINIT 20 0x3000064 Int BE Pri
95088!#6 N9758 P6265 MEMBAR
95089!#6 N9759 P6266 ST_BINIT 0 0x3000065 Int BE Pri
95090!#6 N9760 P6267 MEMBAR
95091!#6 N9761 P6268 ST_BINIT 10 0x3000066 Int BE Pri
95092!#6 N9762 P6269 MEMBAR
95093!#6 N9763 P6270 DWLD 17 -1 Int BE Pri
95094!#6 N9764 P6271 PREFETCH 11 Int BE Pri
95095!#6 N9765 P6272 LD 7 -1 Int BE Pri
95096!#6 N9766 P6272 CAS 7 -1 N9765 0x3000067 Int BE Pri
95097!#6 N9767 P6273 MEMBAR
95098!#6 N9768 P6274 BSTC 12 0x42800042 FP BE Pri
95099!#6 N9769 P6274 BSTC 13 0x42800043 FP BE Pri
95100!#A N9768 N9769
95101!#6 N9770 P6274 BSTC 14 0x42800044 FP BE Pri
95102!#6 N9771 P6275 MEMBAR
95103!#6 N9772 P6276 LD 4 -1 Int BE Pri
95104!#6 N9773 P6276 CAS 4 -1 N9772 0x3000068 Int BE Pri
95105!#6 N9774 P6277 MEMBAR
95106!#6 N9775 P6278 BSTC 12 0x42800045 FP BE Pri
95107!#6 N9776 P6278 BSTC 13 0x42800046 FP BE Pri
95108!#A N9775 N9776
95109!#6 N9777 P6278 BSTC 14 0x42800047 FP BE Pri
95110!#6 N9778 P6279 MEMBAR
95111!#6 N9779 P6280 BST 3 0x42800048 FP BE Pri
95112!#6 N9780 P6280 BST 4 0x42800049 FP BE Pri
95113!#A N9779 N9780
95114!#6 N9781 P6280 BST 5 0x4280004a FP BE Pri
95115!#6 N9782 P6281 MEMBAR
95116!#6 N9783 P6282 LDD 12 -1 Int BE Pri
95117!#6 N9784 P6282 LDD 13 -1 Int BE Pri
95118!#A N9783 N9784
95119!#6 N9785 P6283 MEMBAR
95120!#6 N9786 P6284 BSTC 6 0x4280004b FP BE Pri
95121!#6 N9787 P6284 BSTC 7 0x4280004c FP BE Pri
95122!#A N9786 N9787
95123!#6 N9788 P6284 BSTC 8 0x4280004d FP BE Pri
95124!#6 N9789 P6285 MEMBAR
95125!#6 N9790 P6286 DWLD 6 -1 Int BE Pri
95126!#6 N9791 P6286 DWLD 7 -1 Int BE Pri
95127!#A N9790 N9791
95128!#6 N9792 P6287 DWLD 9 -1 FP BE Pri
95129!#6 N9793 P6287 DWLD 10 -1 FP BE Pri
95130!#A N9792 N9793
95131!#6 N9794 P6288 SWAP 7 0xffffffff 0x3000069 Int BE Pri
95132!#6 N9795 P6289 LD 18 -1 Int LE Pri
95133!#6 N9796 P6289 CAS 18 -1 N9795 0x300006a Int LE Pri
95134!#6 N9797 P6290 DWLD 8 -1 FP BE Pri
95135!#6 N9798 P6291 PREFETCH 13 Int BE Pri
95136!#6 N9799 P6292 MEMBAR
95137!#6 N9800 P6293 BSTC 12 0x4280004e FP BE Pri
95138!#6 N9801 P6293 BSTC 13 0x4280004f FP BE Pri
95139!#A N9800 N9801
95140!#6 N9802 P6293 BSTC 14 0x42800050 FP BE Pri
95141!#6 N9803 P6294 MEMBAR
95142!#6 N9804 P6295 ST 7 0x300006b Int BE Pri
95143!#6 N9805 P6296 LDD 8 -1 Int BE Pri
95144!#6 N9806 P6297 MEMBAR
95145!#6 N9807 P6298 BSTC 3 0x42800051 FP BE Pri
95146!#6 N9808 P6298 BSTC 4 0x42800052 FP BE Pri
95147!#A N9807 N9808
95148!#6 N9809 P6298 BSTC 5 0x42800053 FP BE Pri
95149!#6 N9810 P6299 MEMBAR
95150!#6 N9811 P6300 BSTC 9 0x42800054 FP BE Pri
95151!#6 N9812 P6300 BSTC 10 0x42800055 FP BE Pri
95152!#A N9811 N9812
95153!#6 N9813 P6300 BSTC 11 0x42800056 FP BE Pri
95154!#6 N9814 P6301 MEMBAR
95155!#6 N9815 P6302 DWST 15 0x300006c Int BE Pri
95156!#6 N9816 P6302 DWST 16 0x300006d Int BE Pri
95157!#A N9815 N9816
95158!#6 N9817 P6303 DWST_BINIT 15 0x300006e Int BE Pri
95159!#6 N9818 P6303 DWST_BINIT 16 0x300006f Int BE Pri
95160!#A N9817 N9818
95161!#6 N9819 P6304 MEMBAR
95162!#6 N9820 P6305 DWST 9 0x3000070 Int BE Pri
95163!#6 N9821 P6305 DWST 10 0x3000071 Int BE Pri
95164!#A N9820 N9821
95165!#6 N9822 P6306 SWAP 6 0xffffffff 0x3000072 Int BE Pri
95166!#6 N9823 P6307 DWST_BINIT 2 0x3000073 Int LE Pri
95167!#6 N9824 P6308 MEMBAR
95168!#6 N9825 P6309 SWAP 3 0xffffffff 0x3000074 Int BE Pri
95169!#6 N9826 P6310 MEMBAR
95170!#6 N9827 P6311 BSTC 3 0x42800057 FP BE Pri
95171!#6 N9828 P6311 BSTC 4 0x42800058 FP BE Pri
95172!#A N9827 N9828
95173!#6 N9829 P6311 BSTC 5 0x42800059 FP BE Pri
95174!#6 N9830 P6312 MEMBAR
95175!#6 N9831 P6313 LD 12 -1 Int BE Pri
95176!#6 N9832 P6314 DWLD 14 -1 FP BE Pri
95177!#6 N9833 P6315 DWLD 12 -1 Int BE Pri
95178!#6 N9834 P6315 DWLD 13 -1 Int BE Pri
95179!#A N9833 N9834
95180!#6 N9835 P6316 ST 1 0x3000075 Int LE Pri
95181!#6 N9836 P6317 ST 9 0x3000076 Int BE Pri
95182!#6 N9837 P6318 PREFETCH 9 Int BE Pri
95183!#6 N9838 P6319 MEMBAR
95184!#6 N9839 P6320 BST 12 0x4280005a FP BE Pri
95185!#6 N9840 P6320 BST 13 0x4280005b FP BE Pri
95186!#A N9839 N9840
95187!#6 N9841 P6320 BST 14 0x4280005c FP BE Pri
95188!#6 N9842 P6321 MEMBAR
95189!#6 N9843 P6322 BLD 21 -1 FP BE Pri
95190!#6 N9844 P6322 BLD 22 -1 FP BE Pri
95191!#A N9843 N9844
95192!#6 N9845 P6322 BLD 23 -1 FP BE Pri
95193!#6 N9846 P6323 MEMBAR
95194!#6 N9847 P6324 BST 21 0x4280005d FP BE Pri
95195!#6 N9848 P6324 BST 22 0x4280005e FP BE Pri
95196!#A N9847 N9848
95197!#6 N9849 P6324 BST 23 0x4280005f FP BE Pri
95198!#6 N9850 P6325 MEMBAR
95199!#6 N9851 P6326 LD 0 -1 Int BE Pri
95200!#6 N9852 P6326 CAS 0 -1 N9851 0x3000077 Int BE Pri
95201!#6 N9853 P6327 DWLD 8 -1,0x0 Int BE Pri
95202!#6 N9854 P6327 CASX 8 -1,0x0 N9853 0x3000078 Int BE Pri
95203!#6 N9855 P6328 MEMBAR
95204!#6 N9856 P6329 BST 9 0x42800060 FP BE Pri
95205!#6 N9857 P6329 BST 10 0x42800061 FP BE Pri
95206!#A N9856 N9857
95207!#6 N9858 P6329 BST 11 0x42800062 FP BE Pri
95208!#6 N9859 P6330 MEMBAR
95209!#6 N9860 P6331 DWST_BINIT 12 0x3000079 Int BE Pri
95210!#6 N9861 P6331 DWST_BINIT 13 0x300007a Int BE Pri
95211!#A N9860 N9861
95212!#6 N9862 P6332 MEMBAR
95213!#6 N9863 P6333 LDD 6 -1 Int BE Pri
95214!#6 N9864 P6333 LDD 7 -1 Int BE Pri
95215!#A N9863 N9864
95216!#6 N9865 P6334 DWLD 6 -1 Int BE Pri
95217!#6 N9866 P6334 DWLD 7 -1 Int BE Pri
95218!#A N9865 N9866
95219!#6 N9867 P6335 LDD 15 -1 Int BE Pri
95220!#6 N9868 P6335 LDD 16 -1 Int BE Pri
95221!#A N9867 N9868
95222!#6 N9869 P6336 MEMBAR
95223!#6 N9870 P6337 BSTC 18 0x42800063 FP BE Pri
95224!#6 N9871 P6337 BSTC 19 0x42800064 FP BE Pri
95225!#A N9870 N9871
95226!#6 N9872 P6337 BSTC 20 0x42800065 FP BE Pri
95227!#6 N9873 P6338 MEMBAR
95228!#6 N9874 P6339 DWST 12 0x300007b Int BE Pri
95229!#6 N9875 P6339 DWST 13 0x300007c Int BE Pri
95230!#A N9874 N9875
95231!#6 N9876 P6340 LD 22 -1 Int BE Pri
95232!#6 N9877 P6341 LD 14 -1 Int BE Pri
95233!#6 N9878 P6341 CAS 14 -1 N9877 0x300007d Int BE Pri
95234!#6 N9879 P6342 REPLACEMENT 3 Int BE Pri
95235!#6 N9880 P6343 LD 19 -1 Int BE Pri
95236!#6 N9881 P6343 CAS 19 -1 N9880 0x300007e Int BE Pri
95237!#6 N9882 P6344 MEMBAR
95238!#6 N9883 P6345 BSTC 9 0x42800066 FP BE Pri
95239!#6 N9884 P6345 BSTC 10 0x42800067 FP BE Pri
95240!#A N9883 N9884
95241!#6 N9885 P6345 BSTC 11 0x42800068 FP BE Pri
95242!#6 N9886 P6346 MEMBAR
95243!#6 N9887 P6347 ST_BINIT 11 0x300007f Int LE Pri
95244!#6 N9888 P6348 MEMBAR
95245!#6 N9889 P6349 DWST_BINIT 0 0x3000080 Int BE Pri
95246!#6 N9890 P6349 DWST_BINIT 1 0x3000081 Int BE Pri
95247!#A N9889 N9890
95248!#6 N9891 P6350 MEMBAR
95249!#6 N9892 P6351 LD 16 -1 Int BE Pri
95250!#6 N9893 P6351 CAS 16 -1 N9892 0x3000082 Int BE Pri
95251!#6 N9894 P6352 DWST_BINIT 6 0x3000083 Int BE Pri
95252!#6 N9895 P6352 DWST_BINIT 7 0x3000084 Int BE Pri
95253!#A N9894 N9895
95254!#6 N9896 P6353 MEMBAR
95255!#6 N9897 P6354 DWST 0 0x3000085 Int BE Pri
95256!#6 N9898 P6354 DWST 1 0x3000086 Int BE Pri
95257!#A N9897 N9898
95258!#6 N9899 P6355 MEMBAR
95259!#6 N9900 P6356 BLD 21 -1 FP BE Pri
95260!#6 N9901 P6356 BLD 22 -1 FP BE Pri
95261!#A N9900 N9901
95262!#6 N9902 P6356 BLD 23 -1 FP BE Pri
95263!#6 N9903 P6357 MEMBAR
95264!#6 N9904 P6358 REPLACEMENT 3 Int BE Pri
95265!#6 N9905 P6359 ST 5 0x3000087 Int BE Pri
95266!#6 N9906 P6360 DWLD 23 -1 Int BE Pri
95267!#6 N9907 P6361 MEMBAR
95268!#6 N9908 P6362 BLD 6 -1 FP BE Pri
95269!#6 N9909 P6362 BLD 7 -1 FP BE Pri
95270!#A N9908 N9909
95271!#6 N9910 P6362 BLD 8 -1 FP BE Pri
95272!#6 N9911 P6363 MEMBAR
95273!#6 N9912 P6364 DWST_BINIT 17 0x3000088 Int BE Pri
95274!#6 N9913 P6365 MEMBAR
95275!#6 N9914 P6366 LD 13 -1 Int BE Pri
95276!#6 N9915 P6367 LD 15 -1 Int BE Pri
95277!#6 N9916 P6368 LD 17 -1 Int BE Pri
95278!#6 N9917 P6368 CAS 17 -1 N9916 0x3000089 Int BE Pri
95279!#6 N9918 P6369 PREFETCH 20 Int BE Pri
95280!#6 N9919 P6370 MEMBAR
95281!#6 N9920 P6371 BSTC 9 0x42800069 FP BE Pri
95282!#6 N9921 P6371 BSTC 10 0x4280006a FP BE Pri
95283!#A N9920 N9921
95284!#6 N9922 P6371 BSTC 11 0x4280006b FP BE Pri
95285!#6 N9923 P6372 MEMBAR
95286!#6 N9924 P6373 PREFETCH 8 Int BE Pri
95287!#6 N9925 P6374 SWAP 23 0xffffffff 0x300008a Int BE Pri
95288!#6 N9926 P6375 PREFETCH 22 Int BE Pri
95289!#6 N9927 P6376 MEMBAR
95290!#6 N9928 P6377 BLD 9 -1 FP BE Pri
95291!#6 N9929 P6377 BLD 10 -1 FP BE Pri
95292!#A N9928 N9929
95293!#6 N9930 P6377 BLD 11 -1 FP BE Pri
95294!#6 N9931 P6378 MEMBAR
95295!#6 N9932 P6379 BSTC 21 0x4280006c FP BE Pri
95296!#6 N9933 P6379 BSTC 22 0x4280006d FP BE Pri
95297!#A N9932 N9933
95298!#6 N9934 P6379 BSTC 23 0x4280006e FP BE Pri
95299!#6 N9935 P6380 MEMBAR
95300!#6 N9936 P6381 BST 21 0x4280006f FP BE Pri
95301!#6 N9937 P6381 BST 22 0x42800070 FP BE Pri
95302!#A N9936 N9937
95303!#6 N9938 P6381 BST 23 0x42800071 FP BE Pri
95304!#6 N9939 P6382 MEMBAR
95305!#6 N9940 P6383 DWST_BINIT 6 0x300008b Int BE Pri
95306!#6 N9941 P6383 DWST_BINIT 7 0x300008c Int BE Pri
95307!#A N9940 N9941
95308!#6 N9942 P6384 MEMBAR
95309!#6 N9943 P6385 LD 1 -1 Int BE Pri
95310!#6 N9944 P6385 CAS 1 -1 N9943 0x300008d Int BE Pri
95311!#6 N9945 P6386 PREFETCH 18 Int BE Pri
95312!#6 N9946 P6387 LD 11 -1 Int BE Pri
95313!#6 N9947 P6387 CAS 11 -1 N9946 0x300008e Int BE Pri
95314!#6 N9948 P6388 DWLD 3 -1 Int BE Pri
95315!#6 N9949 P6388 DWLD 4 -1 Int BE Pri
95316!#A N9948 N9949
95317!#6 N9950 P6389 PREFETCH 4 Int BE Pri
95318!#6 N9951 P6390 DWLD 9 -1 Int BE Pri
95319!#6 N9952 P6390 DWLD 10 -1 Int BE Pri
95320!#A N9951 N9952
95321!#6 N9953 P6391 DWLD 18 -1 Int BE Pri
95322!#6 N9954 P6391 DWLD 19 -1 Int BE Pri
95323!#A N9953 N9954
95324!#6 N9955 P6392 MEMBAR
95325!#6 N9956 P6393 BST 0 0x42800072 FP BE Pri
95326!#6 N9957 P6393 BST 1 0x42800073 FP BE Pri
95327!#A N9956 N9957
95328!#6 N9958 P6393 BST 2 0x42800074 FP BE Pri
95329!#6 N9959 P6394 MEMBAR
95330!#6 N9960 P6395 PREFETCH 15 Int BE Pri
95331!#6 N9961 P6396 LD 5 -1 Int BE Pri
95332!#6 N9962 P6396 CAS 5 -1 N9961 0x300008f Int BE Pri
95333!#6 N9963 P6397 MEMBAR
95334!#6 N9964 P6398 BLD 18 -1 FP BE Pri
95335!#6 N9965 P6398 BLD 19 -1 FP BE Pri
95336!#A N9964 N9965
95337!#6 N9966 P6398 BLD 20 -1 FP BE Pri
95338!#6 N9967 P6399 MEMBAR
95339!#6 N9968 P6400 SWAP 11 0xffffffff 0x3000090 Int BE Pri
95340!#6 N9969 P6401 MEMBAR
95341!#6 N9970 P6402 BST 3 0x42800075 FP BE Pri
95342!#6 N9971 P6402 BST 4 0x42800076 FP BE Pri
95343!#A N9970 N9971
95344!#6 N9972 P6402 BST 5 0x42800077 FP BE Pri
95345!#6 N9973 P6403 MEMBAR
95346!#6 N9974 P6404 BLD 15 -1 FP BE Pri
95347!#6 N9975 P6404 BLD 16 -1 FP BE Pri
95348!#A N9974 N9975
95349!#6 N9976 P6404 BLD 17 -1 FP BE Pri
95350!#6 N9977 P6405 MEMBAR
95351!#6 N9978 P6406 DWST 5 0x3000091 Int BE Pri
95352!#6 N9979 P6407 LDD 15 -1 Int BE Pri
95353!#6 N9980 P6407 LDD 16 -1 Int BE Pri
95354!#A N9979 N9980
95355!#6 N9981 P6408 LD 23 -1 Int BE Pri
95356!#6 N9982 P6409 MEMBAR
95357!#6 N9983 P6410 BST 0 0x42800078 FP BE Pri
95358!#6 N9984 P6410 BST 1 0x42800079 FP BE Pri
95359!#A N9983 N9984
95360!#6 N9985 P6410 BST 2 0x4280007a FP BE Pri
95361!#6 N9986 P6411 MEMBAR
95362!#6 N9987 P6412 LD 0 -1 Int BE Pri
95363!#6 N9988 P6412 CAS 0 -1 N9987 0x3000092 Int BE Pri
95364!#6 N9989 P6413 LD 5 -1 Int BE Pri
95365!#6 N9990 P6414 ST_BINIT 15 0x3000093 Int BE Pri
95366!#6 N9991 P6415 MEMBAR
95367!#6 N9992 P6416 DWST 2 0x4280007b FP BE Pri
95368!#6 N9993 P6417 DWLD 8 -1 Int BE Pri
95369!#6 N9994 P6418 MEMBAR
95370!#6 N9995 P6419 BSTC 15 0x4280007c FP BE Pri
95371!#6 N9996 P6419 BSTC 16 0x4280007d FP BE Pri
95372!#A N9995 N9996
95373!#6 N9997 P6419 BSTC 17 0x4280007e FP BE Pri
95374!#6 N9998 P6420 MEMBAR
95375!#6 N9999 P6421 REPLACEMENT 15 Int BE Pri
95376!#6 N10000 P6422 DWST_BINIT 12 0x3000094 Int BE Pri
95377!#6 N10001 P6422 DWST_BINIT 13 0x3000095 Int BE Pri
95378!#A N10000 N10001
95379!#6 N10002 P6423 MEMBAR
95380!#6 N10003 P6424 ST 18 0x3000096 Int BE Pri
95381!#6 N10004 P6425 SWAP 23 0xffffffff 0x3000097 Int BE Pri
95382!#6 N10005 P6426 LD 13 -1 Int BE Pri
95383!#6 N10006 P6427 LD 23 -1 Int BE Pri
95384!#6 N10007 P6428 LD 8 -1 Int BE Pri
95385!#6 N10008 P6428 CAS 8 -1 N10007 0x3000098 Int BE Pri
95386!#6 N10009 P6429 DWST 18 0x4280007f FP BE Pri
95387!#6 N10010 P6429 DWST 19 0x42800080 FP BE Pri
95388!#A N10009 N10010
95389!#6 N10011 P6430 DWLD 15 -1 Int BE Pri
95390!#6 N10012 P6430 DWLD 16 -1 Int BE Pri
95391!#A N10011 N10012
95392!#6 N10013 P6430 CASX 15 -1 N10011 0x3000099 Int BE Pri
95393!#6 N10014 P6430 CASX 16 -1 N10012 0x300009a Int BE Pri
95394!#A N10013 N10014
95395!#6 N10015 P6431 ST 2 0x300009b Int BE Pri
95396!#6 N10016 P6432 LD 5 -1 Int BE Pri
95397!#6 N10017 P6433 LDD 3 -1 Int BE Pri
95398!#6 N10018 P6433 LDD 4 -1 Int BE Pri
95399!#A N10017 N10018
95400!#6 N10019 P6434 ST_BINIT 22 0x300009c Int BE Pri
95401!#6 N10020 P6435 MEMBAR
95402!#6 N10021 P6436 LD 8 -1 Int BE Pri
95403!#6 N10022 P6436 CAS 8 -1 N10021 0x300009d Int BE Pri
95404!#6 N10023 P6437 DWLD 21 -1 FP BE Pri
95405!#6 N10024 P6437 DWLD 22 -1 FP BE Pri
95406!#A N10023 N10024
95407!#6 N10025 P6438 SWAP 16 0xffffffff 0x300009e Int BE Pri
95408!#6 N10026 P6439 LD 5 -1 Int BE Pri
95409!#6 N10027 P6440 LD 6 -1 Int BE Pri
95410!#6 N10028 P6441 LDD 21 -1 Int BE Pri
95411!#6 N10029 P6441 LDD 22 -1 Int BE Pri
95412!#A N10028 N10029
95413!#6 N10030 P6442 LDD 0 -1 Int BE Pri
95414!#6 N10031 P6442 LDD 1 -1 Int BE Pri
95415!#A N10030 N10031
95416!#6 N10032 P6443 DWST 18 0x300009f Int BE Pri
95417!#6 N10033 P6443 DWST 19 0x30000a0 Int BE Pri
95418!#A N10032 N10033
95419!#6 N10034 P6444 DWLD 21 -1 Int BE Pri
95420!#6 N10035 P6444 DWLD 22 -1 Int BE Pri
95421!#A N10034 N10035
95422!#6 N10036 P6445 MEMBAR
95423!#6 N10037 P6446 BST 9 0x42800081 FP BE Pri
95424!#6 N10038 P6446 BST 10 0x42800082 FP BE Pri
95425!#A N10037 N10038
95426!#6 N10039 P6446 BST 11 0x42800083 FP BE Pri
95427!#6 N10040 P6447 MEMBAR
95428!#6 N10041 P6448 BLD 21 -1 FP BE Pri
95429!#6 N10042 P6448 BLD 22 -1 FP BE Pri
95430!#A N10041 N10042
95431!#6 N10043 P6448 BLD 23 -1 FP BE Pri
95432!#6 N10044 P6449 MEMBAR
95433!#6 N10045 P6450 BLD 18 -1 FP BE Pri
95434!#6 N10046 P6450 BLD 19 -1 FP BE Pri
95435!#A N10045 N10046
95436!#6 N10047 P6450 BLD 20 -1 FP BE Pri
95437!#6 N10048 P6451 MEMBAR
95438!#6 N10049 P6452 LDD 18 -1 Int BE Pri
95439!#6 N10050 P6452 LDD 19 -1 Int BE Pri
95440!#A N10049 N10050
95441!#6 N10051 P6453 MEMBAR
95442!#6 N10052 P6454 BLD 12 -1 FP BE Pri
95443!#6 N10053 P6454 BLD 13 -1 FP BE Pri
95444!#A N10052 N10053
95445!#6 N10054 P6454 BLD 14 -1 FP BE Pri
95446!#6 N10055 P6455 MEMBAR
95447!#6 N10056 P6456 BSTC 0 0x42800084 FP BE Pri
95448!#6 N10057 P6456 BSTC 1 0x42800085 FP BE Pri
95449!#A N10056 N10057
95450!#6 N10058 P6456 BSTC 2 0x42800086 FP BE Pri
95451!#6 N10059 P6457 MEMBAR
95452!#6 N10060 P6458 BST 9 0x42800087 FP BE Pri
95453!#6 N10061 P6458 BST 10 0x42800088 FP BE Pri
95454!#A N10060 N10061
95455!#6 N10062 P6458 BST 11 0x42800089 FP BE Pri
95456!#6 N10063 P6459 MEMBAR
95457!#6 N10064 P6460 ST 6 0x30000a1 Int BE Pri
95458!#6 N10065 P6461 DWLD 6 -1 Int BE Pri
95459!#6 N10066 P6461 DWLD 7 -1 Int BE Pri
95460!#A N10065 N10066
95461!#6 N10067 P6461 CASX 6 -1 N10065 0x30000a2 Int BE Pri
95462!#6 N10068 P6461 CASX 7 -1 N10066 0x30000a3 Int BE Pri
95463!#A N10067 N10068
95464!#6 N10069 P6462 LDD 9 -1 Int BE Pri
95465!#6 N10070 P6462 LDD 10 -1 Int BE Pri
95466!#A N10069 N10070
95467!#6 N10071 P6463 SWAP 19 0xffffffff 0x30000a4 Int BE Pri
95468!#6 N10072 P6464 REPLACEMENT 23 Int BE Pri
95469!#6 N10073 P6465 PREFETCH 19 Int BE Pri
95470!#6 N10074 P6466 ST_BINIT 16 0x30000a5 Int BE Pri
95471!#6 N10075 P6467 MEMBAR
95472!#6 N10076 P6468 LD 10 -1 Int BE Pri
95473!#6 N10077 P6468 CAS 10 -1 N10076 0x30000a6 Int BE Pri
95474!#6 N10078 P6469 DWST_BINIT 9 0x30000a7 Int BE Pri
95475!#6 N10079 P6469 DWST_BINIT 10 0x30000a8 Int BE Pri
95476!#A N10078 N10079
95477!#6 N10080 P6470 MEMBAR
95478!#6 N10081 P6471 DWST 3 0x30000a9 Int BE Pri
95479!#6 N10082 P6471 DWST 4 0x30000aa Int BE Pri
95480!#A N10081 N10082
95481!#6 N10083 P6472 PREFETCH 18 Int BE Pri
95482!#6 N10084 P6473 DWST 15 0x30000ab Int BE Pri
95483!#6 N10085 P6473 DWST 16 0x30000ac Int BE Pri
95484!#A N10084 N10085
95485!#6 N10086 P6474 DWST_BINIT 0 0x30000ad Int LE Pri
95486!#6 N10087 P6474 DWST_BINIT 1 0x30000ae Int LE Pri
95487!#A N10086 N10087
95488!#6 N10088 P6475 MEMBAR
95489!#6 N10089 P6476 DWLD 2 -1,0x0 Int BE Pri
95490!#6 N10090 P6476 CASX 2 -1,0x0 N10089 0x30000af Int BE Pri
95491!#6 N10091 P6477 DWST 5 0x4280008a FP BE Pri
95492!#6 N10092 P6478 DWLD 0 -1 Int BE Pri
95493!#6 N10093 P6478 DWLD 1 -1 Int BE Pri
95494!#A N10092 N10093
95495!#6 N10094 P6478 CASX 0 -1 N10092 0x30000b0 Int BE Pri
95496!#6 N10095 P6478 CASX 1 -1 N10093 0x30000b1 Int BE Pri
95497!#A N10094 N10095
95498!#6 N10096 P6479 DWLD 3 -1 Int BE Pri
95499!#6 N10097 P6479 DWLD 4 -1 Int BE Pri
95500!#A N10096 N10097
95501!#6 N10098 P6479 CASX 3 -1 N10096 0x30000b2 Int BE Pri
95502!#6 N10099 P6479 CASX 4 -1 N10097 0x30000b3 Int BE Pri
95503!#A N10098 N10099
95504!#6 N10100 P6480 MEMBAR
95505!#6 N10101 P6481 BSTC 12 0x4280008b FP BE Pri
95506!#6 N10102 P6481 BSTC 13 0x4280008c FP BE Pri
95507!#A N10101 N10102
95508!#6 N10103 P6481 BSTC 14 0x4280008d FP BE Pri
95509!#6 N10104 P6482 MEMBAR
95510!#6 N10105 P6483 ST_BINIT 17 0x30000b4 Int BE Pri
95511!#6 N10106 P6484 MEMBAR
95512!#6 N10107 P6485 LD 9 -1 Int BE Pri
95513!#6 N10108 P6486 MEMBAR
95514!#6 N10109 P6487 BSTC 0 0x4280008e FP BE Pri
95515!#6 N10110 P6487 BSTC 1 0x4280008f FP BE Pri
95516!#A N10109 N10110
95517!#6 N10111 P6487 BSTC 2 0x42800090 FP BE Pri
95518!#6 N10112 P6488 MEMBAR
95519!#6 N10113 P6489 LD 6 -1 Int BE Pri
95520!#6 N10114 P6490 ST_BINIT 9 0x30000b5 Int BE Pri
95521!#6 N10115 P6491 MEMBAR
95522!#6 N10116 P6492 ST 13 0x30000b6 Int BE Pri
95523!#6 N10117 P6493 DWLD 17 -1 Int BE Pri
95524!#6 N10118 P6494 ST_BINIT 17 0x30000b7 Int BE Pri
95525!#6 N10119 P6495 MEMBAR
95526!#6 N10120 P6496 BSTC 3 0x42800091 FP BE Pri
95527!#6 N10121 P6496 BSTC 4 0x42800092 FP BE Pri
95528!#A N10120 N10121
95529!#6 N10122 P6496 BSTC 5 0x42800093 FP BE Pri
95530!#6 N10123 P6497 MEMBAR
95531!#6 N10124 P6498 DWST 12 0x30000b8 Int BE Pri
95532!#6 N10125 P6498 DWST 13 0x30000b9 Int BE Pri
95533!#A N10124 N10125
95534!#6 N10126 P6499 LD 20 -1 Int BE Pri
95535!#6 N10127 P6499 CAS 20 -1 N10126 0x30000ba Int BE Pri
95536!#6 N10128 P6500 ST_BINIT 5 0x30000bb Int BE Pri
95537!#6 N10129 P6501 MEMBAR
95538!#6 N10130 P6502 BST 0 0x42800094 FP BE Pri
95539!#6 N10131 P6502 BST 1 0x42800095 FP BE Pri
95540!#A N10130 N10131
95541!#6 N10132 P6502 BST 2 0x42800096 FP BE Pri
95542!#6 N10133 P6503 MEMBAR
95543!#6 N10134 P6504 LD 23 -1 Int LE Pri
95544!#6 N10135 P6505 ST_BINIT 17 0x30000bc Int BE Pri
95545!#6 N10136 P6506 MEMBAR
95546!#6 N10137 P6507 BST 6 0x42800097 FP BE Pri
95547!#6 N10138 P6507 BST 7 0x42800098 FP BE Pri
95548!#A N10137 N10138
95549!#6 N10139 P6507 BST 8 0x42800099 FP BE Pri
95550!#6 N10140 P6508 MEMBAR
95551!#6 N10141 P6509 ST 19 0x30000bd Int BE Pri
95552!#6 N10142 P6510 MEMBAR
95553!#6 N10143 P6511 BST 9 0x4280009a FP BE Pri
95554!#6 N10144 P6511 BST 10 0x4280009b FP BE Pri
95555!#A N10143 N10144
95556!#6 N10145 P6511 BST 11 0x4280009c FP BE Pri
95557!#6 N10146 P6512 MEMBAR
95558!#6 N10147 P6513 LD 1 -1 Int BE Pri
95559!#6 N10148 P6514 LD 3 -1 Int BE Pri
95560!#6 N10149 P6515 DWST_BINIT 12 0x30000be Int BE Pri
95561!#6 N10150 P6515 DWST_BINIT 13 0x30000bf Int BE Pri
95562!#A N10149 N10150
95563!#6 N10151 P6516 MEMBAR
95564!#6 N10152 P6517 LDD 11 -1 Int BE Pri
95565!#6 N10153 P6518 DWLD 21 -1 Int BE Pri
95566!#6 N10154 P6518 DWLD 22 -1 Int BE Pri
95567!#A N10153 N10154
95568!#6 N10155 P6518 CASX 21 -1 N10153 0x30000c0 Int BE Pri
95569!#6 N10156 P6518 CASX 22 -1 N10154 0x30000c1 Int BE Pri
95570!#A N10155 N10156
95571!#6 N10157 P6519 PREFETCH 3 Int BE Pri
95572!#6 N10158 P6520 LD 10 -1 Int BE Pri
95573!#6 N10159 P6521 DWST 12 0x30000c2 Int BE Pri
95574!#6 N10160 P6521 DWST 13 0x30000c3 Int BE Pri
95575!#A N10159 N10160
95576!#6 N10161 P6522 DWST 0 0x30000c4 Int BE Pri
95577!#6 N10162 P6522 DWST 1 0x30000c5 Int BE Pri
95578!#A N10161 N10162
95579!#6 N10163 P6523 LD 0 -1 Int BE Pri
95580!#6 N10164 P6523 CAS 0 -1 N10163 0x30000c6 Int BE Pri
95581!#6 N10165 P6524 DWST_BINIT 14 0x30000c7 Int BE Pri
95582!#6 N10166 P6525 MEMBAR
95583!#6 N10167 P6526 SWAP 16 0xffffffff 0x30000c8 Int BE Pri
95584!#6 N10168 P6527 PREFETCH 11 Int LE Pri
95585!#6 N10169 P6528 LD 5 -1 Int BE Pri
95586!#6 N10170 P6528 CAS 5 -1 N10169 0x30000c9 Int BE Pri
95587!#6 N10171 P6529 DWLD 12 -1 Int BE Pri
95588!#6 N10172 P6529 DWLD 13 -1 Int BE Pri
95589!#A N10171 N10172
95590!#6 N10173 P6529 CASX 12 -1 N10171 0x30000ca Int BE Pri
95591!#6 N10174 P6529 CASX 13 -1 N10172 0x30000cb Int BE Pri
95592!#A N10173 N10174
95593!#6 N10175 P6530 PREFETCH 0 Int BE Pri
95594!#6 N10176 P6531 MEMBAR
95595!#6 N10177 P6532 BLD 18 -1 FP BE Pri
95596!#6 N10178 P6532 BLD 19 -1 FP BE Pri
95597!#A N10177 N10178
95598!#6 N10179 P6532 BLD 20 -1 FP BE Pri
95599!#6 N10180 P6533 MEMBAR
95600!#6 N10181 P6534 LDD 11 -1 Int BE Pri
95601!#6 N10182 P6535 MEMBAR
95602!#6 N10183 P6536 BLD 3 -1 FP BE Pri
95603!#6 N10184 P6536 BLD 4 -1 FP BE Pri
95604!#A N10183 N10184
95605!#6 N10185 P6536 BLD 5 -1 FP BE Pri
95606!#6 N10186 P6537 MEMBAR
95607!#6 N10187 P6538 DWST_BINIT 9 0x30000cc Int BE Pri
95608!#6 N10188 P6538 DWST_BINIT 10 0x30000cd Int BE Pri
95609!#A N10187 N10188
95610!#6 N10189 P6539 MEMBAR
95611!#6 N10190 P6540 ST 19 0x30000ce Int BE Pri
95612!#6 N10191 P6541 ST 0 0x30000cf Int BE Pri
95613!#6 N10192 P6542 PREFETCH 7 Int BE Pri
95614!#6 N10193 P6543 PREFETCH 23 Int BE Pri
95615!#6 N10194 P6544 DWST 23 0x30000d0 Int BE Pri
95616!#6 N10195 P6545 MEMBAR
95617!#6 N10196 P6546 BLD 9 -1 FP BE Pri
95618!#6 N10197 P6546 BLD 10 -1 FP BE Pri
95619!#A N10196 N10197
95620!#6 N10198 P6546 BLD 11 -1 FP BE Pri
95621!#6 N10199 P6547 MEMBAR
95622!#6 N10200 P6548 BLD 15 -1 FP BE Pri
95623!#6 N10201 P6548 BLD 16 -1 FP BE Pri
95624!#A N10200 N10201
95625!#6 N10202 P6548 BLD 17 -1 FP BE Pri
95626!#6 N10203 P6549 MEMBAR
95627!#6 N10204 P6550 DWST_BINIT 6 0x30000d1 Int BE Pri
95628!#6 N10205 P6550 DWST_BINIT 7 0x30000d2 Int BE Pri
95629!#A N10204 N10205
95630!#6 N10206 P6551 MEMBAR
95631!#6 N10207 P6552 PREFETCH 8 Int BE Pri
95632!#6 N10208 P6553 PREFETCH 8 Int BE Pri
95633!#6 N10209 P6554 REPLACEMENT 4 Int BE Pri
95634!#6 N10210 P6555 LDD 18 -1 Int BE Pri
95635!#6 N10211 P6555 LDD 19 -1 Int BE Pri
95636!#A N10210 N10211
95637!#6 N10212 P6556 ST_BINIT 2 0x30000d3 Int BE Pri
95638!#6 N10213 P6557 MEMBAR
95639!#6 N10214 P6558 BSTC 9 0x4280009d FP BE Pri
95640!#6 N10215 P6558 BSTC 10 0x4280009e FP BE Pri
95641!#A N10214 N10215
95642!#6 N10216 P6558 BSTC 11 0x4280009f FP BE Pri
95643!#6 N10217 P6559 MEMBAR
95644!#6 N10218 P6560 LDD 15 -1 Int BE Pri
95645!#6 N10219 P6560 LDD 16 -1 Int BE Pri
95646!#A N10218 N10219
95647!#6 N10220 P6561 LD 11 -1 Int BE Pri
95648!#6 N10221 P6562 DWST_BINIT 9 0x30000d4 Int BE Pri
95649!#6 N10222 P6562 DWST_BINIT 10 0x30000d5 Int BE Pri
95650!#A N10221 N10222
95651!#6 N10223 P6563 MEMBAR
95652!#6 N10224 P6564 BSTC 18 0x428000a0 FP BE Pri
95653!#6 N10225 P6564 BSTC 19 0x428000a1 FP BE Pri
95654!#A N10224 N10225
95655!#6 N10226 P6564 BSTC 20 0x428000a2 FP BE Pri
95656!#6 N10227 P6565 MEMBAR
95657!#6 N10228 P6566 ST 15 0x30000d6 Int BE Pri
95658!#6 N10229 P6567 MEMBAR
95659!#6 N10230 P6568 BSTC 12 0x428000a3 FP BE Pri
95660!#6 N10231 P6568 BSTC 13 0x428000a4 FP BE Pri
95661!#A N10230 N10231
95662!#6 N10232 P6568 BSTC 14 0x428000a5 FP BE Pri
95663!#6 N10233 P6569 MEMBAR
95664!#6 N10234 P6570 PREFETCH 8 Int BE Pri
95665!#6 N10235 P6571 PREFETCH 10 Int BE Pri
95666!#6 N10236 P6572 LD 23 -1 Int BE Pri
95667!#6 N10237 P6572 CAS 23 -1 N10236 0x30000d7 Int BE Pri
95668!#6 N10238 P6573 ST 18 0x30000d8 Int BE Pri
95669!#6 N10239 P6574 ST_BINIT 15 0x30000d9 Int BE Pri
95670!#6 N10240 P6575 MEMBAR
95671!#6 N10241 P6576 BLD 15 -1 FP BE Pri
95672!#6 N10242 P6576 BLD 16 -1 FP BE Pri
95673!#A N10241 N10242
95674!#6 N10243 P6576 BLD 17 -1 FP BE Pri
95675!#6 N10244 P6577 MEMBAR
95676!#6 N10245 P6578 DWST 21 0x30000da Int BE Pri
95677!#6 N10246 P6578 DWST 22 0x30000db Int BE Pri
95678!#A N10245 N10246
95679!#6 N10247 P6579 ST_BINIT 3 0x30000dc Int BE Pri
95680!#6 N10248 P6580 MEMBAR
95681!#6 N10249 P6581 DWLD 18 -1 Int BE Pri
95682!#6 N10250 P6581 DWLD 19 -1 Int BE Pri
95683!#A N10249 N10250
95684!#6 N10251 P6581 CASX 18 -1 N10249 0x30000dd Int BE Pri
95685!#6 N10252 P6581 CASX 19 -1 N10250 0x30000de Int BE Pri
95686!#A N10251 N10252
95687!#6 N10253 P6582 MEMBAR
95688!#6 N10254 P6583 BSTC 12 0x428000a6 FP BE Pri
95689!#6 N10255 P6583 BSTC 13 0x428000a7 FP BE Pri
95690!#A N10254 N10255
95691!#6 N10256 P6583 BSTC 14 0x428000a8 FP BE Pri
95692!#6 N10257 P6584 MEMBAR
95693!#6 N10258 P6585 PREFETCH 23 Int BE Pri
95694!#6 N10259 P6586 DWST_BINIT 23 0x30000df Int BE Pri
95695!#6 N10260 P6587 MEMBAR
95696!#6 N10261 P6588 REPLACEMENT 22 Int BE Pri
95697!#6 N10262 P6589 DWLD 15 -1 Int BE Pri
95698!#6 N10263 P6589 DWLD 16 -1 Int BE Pri
95699!#A N10262 N10263
95700!#6 N10264 P6589 CASX 15 -1 N10262 0x30000e0 Int BE Pri
95701!#6 N10265 P6589 CASX 16 -1 N10263 0x30000e1 Int BE Pri
95702!#A N10264 N10265
95703!#6 N10266 P6590 LDD 21 -1 Int BE Pri
95704!#6 N10267 P6590 LDD 22 -1 Int BE Pri
95705!#A N10266 N10267
95706!#6 N10268 P6591 ST 16 0x30000e2 Int BE Pri
95707!#6 N10269 P6592 LDD 20 -1 Int BE Pri
95708!#6 N10270 P6593 LD 12 -1 Int BE Pri
95709!#6 N10271 P6594 SWAP 11 0xffffffff 0x30000e3 Int BE Pri
95710!#6 N10272 P6595 MEMBAR
95711!#6 N10273 P6596 BSTC 3 0x428000a9 FP BE Pri
95712!#6 N10274 P6596 BSTC 4 0x428000aa FP BE Pri
95713!#A N10273 N10274
95714!#6 N10275 P6596 BSTC 5 0x428000ab FP BE Pri
95715!#6 N10276 P6597 MEMBAR
95716!#6 N10277 P6598 PREFETCH 8 Int BE Pri
95717!#6 N10278 P6599 LDD 8 -1 Int BE Pri
95718!#6 N10279 P6600 DWLD 15 -1 Int BE Pri
95719!#6 N10280 P6600 DWLD 16 -1 Int BE Pri
95720!#A N10279 N10280
95721!#6 N10281 P6601 DWLD 20 -1,0x0 Int BE Pri
95722!#6 N10282 P6601 CASX 20 -1,0x0 N10281 0x30000e4 Int BE Pri
95723!#6 N10283 P6602 ST 11 0x30000e5 Int BE Pri
95724!#6 N10284 P6603 DWST_BINIT 0 0x30000e6 Int BE Pri
95725!#6 N10285 P6603 DWST_BINIT 1 0x30000e7 Int BE Pri
95726!#A N10284 N10285
95727!#6 N10286 P6604 MEMBAR
95728!#6 N10287 P6605 LD 4 -1 Int BE Pri
95729!#6 N10288 P6605 CAS 4 -1 N10287 0x30000e8 Int BE Pri
95730!#6 N10289 P6606 DWLD 6 -1 Int BE Pri
95731!#6 N10290 P6606 DWLD 7 -1 Int BE Pri
95732!#A N10289 N10290
95733!#6 N10291 P6606 CASX 6 -1 N10289 0x30000e9 Int BE Pri
95734!#6 N10292 P6606 CASX 7 -1 N10290 0x30000ea Int BE Pri
95735!#A N10291 N10292
95736!#6 N10293 P6607 REPLACEMENT 11 Int BE Pri
95737!#6 N10294 P6608 DWLD 0 -1 Int BE Pri
95738!#6 N10295 P6608 DWLD 1 -1 Int BE Pri
95739!#A N10294 N10295
95740!#6 N10296 P6608 CASX 0 -1 N10294 0x30000eb Int BE Pri
95741!#6 N10297 P6608 CASX 1 -1 N10295 0x30000ec Int BE Pri
95742!#A N10296 N10297
95743!#6 N10298 P6609 DWLD 2 -1 Int BE Pri
95744!#6 N10299 P6610 LD 2 -1 Int BE Pri
95745!#6 N10300 P6610 CAS 2 -1 N10299 0x30000ed Int BE Pri
95746!#6 N10301 P6611 DWST_BINIT 21 0x30000ee Int BE Pri
95747!#6 N10302 P6611 DWST_BINIT 22 0x30000ef Int BE Pri
95748!#A N10301 N10302
95749!#6 N10303 P6612 MEMBAR
95750!#6 N10304 P6613 BLD 15 -1 FP BE Pri
95751!#6 N10305 P6613 BLD 16 -1 FP BE Pri
95752!#A N10304 N10305
95753!#6 N10306 P6613 BLD 17 -1 FP BE Pri
95754!#6 N10307 P6614 MEMBAR
95755!#6 N10308 P6615 LDD 9 -1 Int BE Pri
95756!#6 N10309 P6615 LDD 10 -1 Int BE Pri
95757!#A N10308 N10309
95758!#6 N10310 P6616 DWLD 3 -1 Int BE Pri
95759!#6 N10311 P6616 DWLD 4 -1 Int BE Pri
95760!#A N10310 N10311
95761!#6 N10312 P6617 DWLD 11 -1 Int BE Pri
95762!#6 N10313 P6618 MEMBAR
95763!#6 N10314 P6619 BLD 18 -1 FP BE Pri
95764!#6 N10315 P6619 BLD 19 -1 FP BE Pri
95765!#A N10314 N10315
95766!#6 N10316 P6619 BLD 20 -1 FP BE Pri
95767!#6 N10317 P6620 MEMBAR
95768!#6 N10318 P6621 ST 8 0x30000f0 Int BE Pri
95769!#6 N10319 P6622 DWST_BINIT 5 0x30000f1 Int BE Pri
95770!#6 N10320 P6623 MEMBAR
95771!#6 N10321 P6624 LD 14 -1 Int BE Pri
95772!#6 N10322 P6624 CAS 14 -1 N10321 0x30000f2 Int BE Pri
95773!#6 N10323 P6625 SWAP 12 0xffffffff 0x30000f3 Int LE Pri
95774!#6 N10324 P6626 ST 22 0x30000f4 Int BE Pri
95775!#6 N10325 P6627 LDD 8 -1 Int BE Pri
95776!#6 N10326 P6628 LDD 0 -1 Int LE Pri
95777!#6 N10327 P6628 LDD 1 -1 Int LE Pri
95778!#A N10326 N10327
95779!#6 N10328 P6629 MEMBAR
95780!#6 N10329 P6630 BSTC 18 0x428000ac FP BE Pri
95781!#6 N10330 P6630 BSTC 19 0x428000ad FP BE Pri
95782!#A N10329 N10330
95783!#6 N10331 P6630 BSTC 20 0x428000ae FP BE Pri
95784!#6 N10332 P6631 MEMBAR
95785!#6 N10333 P6632 BSTC 21 0x428000af FP BE Pri
95786!#6 N10334 P6632 BSTC 22 0x428000b0 FP BE Pri
95787!#A N10333 N10334
95788!#6 N10335 P6632 BSTC 23 0x428000b1 FP BE Pri
95789!#6 N10336 P6633 MEMBAR
95790!#6 N10337 P6634 PREFETCH 18 Int BE Pri
95791!#6 N10338 P6635 ST 9 0x30000f5 Int BE Pri
95792!#6 N10339 P6636 SWAP 10 0xffffffff 0x30000f6 Int BE Pri
95793!#6 N10340 P6637 MEMBAR
95794!#6 N10341 P6638 BSTC 0 0x428000b2 FP BE Pri
95795!#6 N10342 P6638 BSTC 1 0x428000b3 FP BE Pri
95796!#A N10341 N10342
95797!#6 N10343 P6638 BSTC 2 0x428000b4 FP BE Pri
95798!#6 N10344 P6639 MEMBAR
95799!#6 N10345 P6640 ST_BINIT 6 0x30000f7 Int BE Pri
95800!#6 N10346 P6641 MEMBAR
95801!#6 N10347 P6642 LD 21 -1 Int BE Pri
95802!#6 N10348 P6643 DWLD 17 -1 Int BE Pri
95803!#6 N10349 P6644 PREFETCH 9 Int BE Pri
95804!#6 N10350 P6645 DWLD 23 -1,0x0 Int LE Pri
95805!#6 N10351 P6645 CASX 23 -1,0x0 N10350 0x30000f8 Int LE Pri
95806!#6 N10352 P6646 LD 23 -1 Int BE Pri
95807!#6 N10353 P6646 CAS 23 -1 N10352 0x30000f9 Int BE Pri
95808!#6 N10354 P6647 PREFETCH 20 Int BE Pri
95809!#6 N10355 P6648 MEMBAR
95810!#6 N10356 P6649 BSTC 15 0x428000b5 FP BE Pri
95811!#6 N10357 P6649 BSTC 16 0x428000b6 FP BE Pri
95812!#A N10356 N10357
95813!#6 N10358 P6649 BSTC 17 0x428000b7 FP BE Pri
95814!#6 N10359 P6650 MEMBAR
95815!#6 N10360 P6651 BLD 12 -1 FP BE Pri
95816!#6 N10361 P6651 BLD 13 -1 FP BE Pri
95817!#A N10360 N10361
95818!#6 N10362 P6651 BLD 14 -1 FP BE Pri
95819!#6 N10363 P6652 MEMBAR
95820!#6 N10364 P6653 BSTC 15 0x428000b8 FP BE Pri
95821!#6 N10365 P6653 BSTC 16 0x428000b9 FP BE Pri
95822!#A N10364 N10365
95823!#6 N10366 P6653 BSTC 17 0x428000ba FP BE Pri
95824!#6 N10367 P6654 MEMBAR
95825!#6 N10368 P6655 ST_BINIT 9 0x30000fa Int BE Pri
95826!#6 N10369 P6656 MEMBAR
95827!#6 N10370 P6657 DWLD 14 -1,0x0 Int LE Pri
95828!#6 N10371 P6657 CASX 14 -1,0x0 N10370 0x30000fb Int LE Pri
95829!#6 N10372 P6658 PREFETCH 18 Int BE Pri
95830!#6 N10373 P6659 DWST 9 0x30000fc Int BE Pri
95831!#6 N10374 P6659 DWST 10 0x30000fd Int BE Pri
95832!#A N10373 N10374
95833!#6 N10375 P6660 MEMBAR
95834!#6 N10376 P6661 BSTC 18 0x428000bb FP BE Pri
95835!#6 N10377 P6661 BSTC 19 0x428000bc FP BE Pri
95836!#A N10376 N10377
95837!#6 N10378 P6661 BSTC 20 0x428000bd FP BE Pri
95838!#6 N10379 P6662 MEMBAR
95839!#6 N10380 P6663 LDD 3 -1 Int BE Pri
95840!#6 N10381 P6663 LDD 4 -1 Int BE Pri
95841!#A N10380 N10381
95842!#6 N10382 P6664 MEMBAR
95843!#6 N10383 P6665 BST 0 0x428000be FP BE Pri
95844!#6 N10384 P6665 BST 1 0x428000bf FP BE Pri
95845!#A N10383 N10384
95846!#6 N10385 P6665 BST 2 0x428000c0 FP BE Pri
95847!#6 N10386 P6666 MEMBAR
95848!#6 N10387 P6667 SWAP 19 0xffffffff 0x30000fe Int BE Pri
95849!#6 N10388 P6668 LDD 3 -1 Int BE Pri
95850!#6 N10389 P6668 LDD 4 -1 Int BE Pri
95851!#A N10388 N10389
95852!#6 N10390 P6669 DWST_BINIT 9 0x30000ff Int BE Pri
95853!#6 N10391 P6669 DWST_BINIT 10 0x3000100 Int BE Pri
95854!#A N10390 N10391
95855!#6 N10392 P6670 MEMBAR
95856!#6 N10393 P6671 DWLD 23 -1 Int BE Pri
95857!#6 N10394 P6672 DWLD 21 -1 Int BE Pri
95858!#6 N10395 P6672 DWLD 22 -1 Int BE Pri
95859!#A N10394 N10395
95860!#6 N10396 P6673 PREFETCH 20 Int BE Pri
95861!#6 N10397 P6674 LD 7 -1 Int BE Pri
95862!#6 N10398 P6675 DWST_BINIT 18 0x3000101 Int BE Pri
95863!#6 N10399 P6675 DWST_BINIT 19 0x3000102 Int BE Pri
95864!#A N10398 N10399
95865!#6 N10400 P6676 MEMBAR
95866!#6 N10401 P6677 SWAP 12 0xffffffff 0x3000103 Int BE Pri
95867!#6 N10402 P6678 SWAP 19 0xffffffff 0x3000104 Int BE Pri
95868!#6 N10403 P6679 DWLD 6 -1 Int BE Pri
95869!#6 N10404 P6679 DWLD 7 -1 Int BE Pri
95870!#A N10403 N10404
95871!#6 N10405 P6680 DWST_BINIT 8 0x3000105 Int BE Pri
95872!#6 N10406 P6681 MEMBAR
95873!#6 N10407 P6682 DWLD 12 -1 Int LE Pri
95874!#6 N10408 P6682 DWLD 13 -1 Int LE Pri
95875!#A N10407 N10408
95876!#6 N10409 P6682 CASX 12 -1 N10407 0x3000106 Int LE Pri
95877!#6 N10410 P6682 CASX 13 -1 N10408 0x3000107 Int LE Pri
95878!#A N10409 N10410
95879!#6 N10411 P6683 ST 13 0x3000108 Int BE Pri
95880!#6 N10412 P6684 ST_BINIT 6 0x3000109 Int BE Pri
95881!#6 N10413 P6685 MEMBAR
95882!#6 N10414 P6686 ST_BINIT 3 0x300010a Int BE Pri
95883!#6 N10415 P6687 MEMBAR
95884!#6 N10416 P6688 DWLD 15 -1 Int BE Pri
95885!#6 N10417 P6688 DWLD 16 -1 Int BE Pri
95886!#A N10416 N10417
95887!#6 N10418 P6688 CASX 15 -1 N10416 0x300010b Int BE Pri
95888!#6 N10419 P6688 CASX 16 -1 N10417 0x300010c Int BE Pri
95889!#A N10418 N10419
95890!#6 N10420 P6689 LDD 23 -1 Int BE Pri
95891!#6 N10421 P6690 ST_BINIT 4 0x300010d Int BE Pri
95892!#6 N10422 P6691 MEMBAR
95893!#6 N10423 P6692 SWAP 6 0xffffffff 0x300010e Int BE Pri
95894!#6 N10424 P6693 DWST_BINIT 23 0x300010f Int BE Pri
95895!#6 N10425 P6694 MEMBAR
95896!#6 N10426 P6695 PREFETCH 7 Int BE Pri
95897!#6 N10427 P6696 LDD 6 -1 Int BE Pri
95898!#6 N10428 P6696 LDD 7 -1 Int BE Pri
95899!#A N10427 N10428
95900!#6 N10429 P6697 LDD 3 -1 Int BE Pri
95901!#6 N10430 P6697 LDD 4 -1 Int BE Pri
95902!#A N10429 N10430
95903!#6 N10431 P6698 LD 16 -1 Int BE Pri
95904!#6 N10432 P6698 CAS 16 -1 N10431 0x3000110 Int BE Pri
95905!#6 N10433 P6699 LD 8 -1 Int BE Pri
95906!#6 N10434 P6699 CAS 8 -1 N10433 0x3000111 Int BE Pri
95907!#6 N10435 P6700 REPLACEMENT 10 Int BE Pri
95908!#6 N10436 P6701 MEMBAR
95909!#6 N10437 P6702 BST 6 0x428000c1 FP BE Pri
95910!#6 N10438 P6702 BST 7 0x428000c2 FP BE Pri
95911!#A N10437 N10438
95912!#6 N10439 P6702 BST 8 0x428000c3 FP BE Pri
95913!#6 N10440 P6703 MEMBAR
95914!#6 N10441 P6704 BLD 9 -1 FP BE Pri
95915!#6 N10442 P6704 BLD 10 -1 FP BE Pri
95916!#A N10441 N10442
95917!#6 N10443 P6704 BLD 11 -1 FP BE Pri
95918!#6 N10444 P6705 MEMBAR
95919!#6 N10445 P6706 LD 4 -1 Int BE Pri
95920!#6 N10446 P6707 MEMBAR
95921!#6 N10447 P6708 BST 9 0x428000c4 FP BE Pri
95922!#6 N10448 P6708 BST 10 0x428000c5 FP BE Pri
95923!#A N10447 N10448
95924!#6 N10449 P6708 BST 11 0x428000c6 FP BE Pri
95925!#6 N10450 P6709 MEMBAR
95926!#6 N10451 P6710 LD 4 -1 Int BE Pri
95927!#6 N10452 P6710 CAS 4 -1 N10451 0x3000112 Int BE Pri
95928!#6 N10453 P6711 LD 18 -1 Int BE Pri
95929!#6 N10454 P6712 SWAP 13 0xffffffff 0x3000113 Int BE Pri
95930!#6 N10455 P6713 DWLD 17 -1 Int BE Pri
95931!#6 N10456 P6714 ST 22 0x3000114 Int BE Pri
95932!#6 N10457 P6715 MEMBAR
95933!#6 N10458 P6716 BST 0 0x428000c7 FP BE Pri
95934!#6 N10459 P6716 BST 1 0x428000c8 FP BE Pri
95935!#A N10458 N10459
95936!#6 N10460 P6716 BST 2 0x428000c9 FP BE Pri
95937!#6 N10461 P6717 MEMBAR
95938!#6 N10462 P6718 BST 18 0x428000ca FP BE Pri
95939!#6 N10463 P6718 BST 19 0x428000cb FP BE Pri
95940!#A N10462 N10463
95941!#6 N10464 P6718 BST 20 0x428000cc FP BE Pri
95942!#6 N10465 P6719 MEMBAR
95943!#6 N10466 P6720 BST 0 0x428000cd FP BE Pri
95944!#6 N10467 P6720 BST 1 0x428000ce FP BE Pri
95945!#A N10466 N10467
95946!#6 N10468 P6720 BST 2 0x428000cf FP BE Pri
95947!#6 N10469 P6721 MEMBAR
95948!#6 N10470 P6722 DWST_BINIT 3 0x3000115 Int BE Pri
95949!#6 N10471 P6722 DWST_BINIT 4 0x3000116 Int BE Pri
95950!#A N10470 N10471
95951!#6 N10472 P6723 MEMBAR
95952!#6 N10473 P6724 LD 15 -1 Int BE Pri
95953!#6 N10474 P6724 CAS 15 -1 N10473 0x3000117 Int BE Pri
95954!#6 N10475 P6725 ST_BINIT 21 0x3000118 Int BE Pri
95955!#6 N10476 P6726 MEMBAR
95956!#6 N10477 P6727 REPLACEMENT 11 Int BE Pri
95957!#6 N10478 P6728 LDD 21 -1 Int BE Pri
95958!#6 N10479 P6728 LDD 22 -1 Int BE Pri
95959!#A N10478 N10479
95960!#6 N10480 P6729 ST 18 0x3000119 Int BE Pri
95961!#6 N10481 P6730 LD 22 -1 Int BE Pri
95962!#6 N10482 P6731 PREFETCH 1 Int BE Pri
95963!#6 N10483 P6732 LD 4 -1 Int BE Pri
95964!#6 N10484 P6733 LDD 12 -1 Int BE Pri
95965!#6 N10485 P6733 LDD 13 -1 Int BE Pri
95966!#A N10484 N10485
95967!#6 N10486 P6734 MEMBAR
95968!#6 N10487 P6735 BSTC 6 0x428000d0 FP BE Pri
95969!#6 N10488 P6735 BSTC 7 0x428000d1 FP BE Pri
95970!#A N10487 N10488
95971!#6 N10489 P6735 BSTC 8 0x428000d2 FP BE Pri
95972!#6 N10490 P6736 MEMBAR
95973!#6 N10491 P6737 SWAP 10 0xffffffff 0x300011a Int BE Pri
95974!#6 N10492 P6738 LD 23 -1 Int LE Pri
95975!#6 N10493 P6738 CAS 23 -1 N10492 0x300011b Int LE Pri
95976!#6 N10494 P6739 LDD 18 -1 Int BE Pri
95977!#6 N10495 P6739 LDD 19 -1 Int BE Pri
95978!#A N10494 N10495
95979!#6 N10496 P6740 SWAP 15 0xffffffff 0x300011c Int BE Pri
95980!#6 N10497 P6741 LDD 6 -1 Int BE Pri
95981!#6 N10498 P6741 LDD 7 -1 Int BE Pri
95982!#A N10497 N10498
95983!#6 N10499 P6742 DWST 9 0x300011d Int BE Pri
95984!#6 N10500 P6742 DWST 10 0x300011e Int BE Pri
95985!#A N10499 N10500
95986!#6 N10501 P6743 MEMBAR
95987!#6 N10502 P6744 BST 0 0x428000d3 FP BE Pri
95988!#6 N10503 P6744 BST 1 0x428000d4 FP BE Pri
95989!#A N10502 N10503
95990!#6 N10504 P6744 BST 2 0x428000d5 FP BE Pri
95991!#6 N10505 P6745 MEMBAR
95992!#6 N10506 P6746 LDD 3 -1 Int BE Pri
95993!#6 N10507 P6746 LDD 4 -1 Int BE Pri
95994!#A N10506 N10507
95995!#6 N10508 P6747 LDD 2 -1 Int BE Pri
95996!#6 N10509 P6748 PREFETCH 21 Int BE Pri
95997!#6 N10510 P6749 DWLD 18 -1 Int BE Pri
95998!#6 N10511 P6749 DWLD 19 -1 Int BE Pri
95999!#A N10510 N10511
96000!#6 N10512 P6750 PREFETCH 5 Int BE Pri
96001!#6 N10513 P6751 DWST_BINIT 20 0x300011f Int BE Pri
96002!#6 N10514 P6752 MEMBAR
96003!#6 N10515 P6753 PREFETCH 19 Int BE Pri
96004!#6 N10516 P6754 SWAP 15 0xffffffff 0x3000120 Int BE Pri
96005!#6 N10517 P6755 MEMBAR
96006!#6 N10518 P6756 BST 21 0x428000d6 FP BE Pri
96007!#6 N10519 P6756 BST 22 0x428000d7 FP BE Pri
96008!#A N10518 N10519
96009!#6 N10520 P6756 BST 23 0x428000d8 FP BE Pri
96010!#6 N10521 P6757 MEMBAR
96011!#6 N10522 P6758 LD 0 -1 Int BE Pri
96012!#6 N10523 P6758 CAS 0 -1 N10522 0x3000121 Int BE Pri
96013!#6 N10524 P6759 LD 0 -1 Int BE Pri
96014!#6 N10525 P6760 PREFETCH 15 Int BE Pri
96015!#6 N10526 P6761 MEMBAR
96016!#6 N10527 P6762 BLD 9 -1 FP BE Pri
96017!#6 N10528 P6762 BLD 10 -1 FP BE Pri
96018!#A N10527 N10528
96019!#6 N10529 P6762 BLD 11 -1 FP BE Pri
96020!#6 N10530 P6763 MEMBAR
96021!#6 N10531 P6764 BSTC 6 0x428000d9 FP BE Pri
96022!#6 N10532 P6764 BSTC 7 0x428000da FP BE Pri
96023!#A N10531 N10532
96024!#6 N10533 P6764 BSTC 8 0x428000db FP BE Pri
96025!#6 N10534 P6765 MEMBAR
96026!#6 N10535 P6766 ST_BINIT 5 0x3000122 Int BE Pri
96027!#6 N10536 P6767 MEMBAR
96028!#6 N10537 P6768 REPLACEMENT 6 Int BE Pri
96029!#6 N10538 P6769 ST_BINIT 19 0x3000123 Int BE Pri
96030!#6 N10539 P6770 MEMBAR
96031!#6 N10540 P6771 LDD 11 -1 Int BE Pri
96032!#6 N10541 P6772 MEMBAR
96033!#6 N10542 P6773 BLD 3 -1 FP BE Pri
96034!#6 N10543 P6773 BLD 4 -1 FP BE Pri
96035!#A N10542 N10543
96036!#6 N10544 P6773 BLD 5 -1 FP BE Pri
96037!#6 N10545 P6774 MEMBAR
96038!#6 N10546 P6775 LD 6 -1 Int BE Pri
96039!#6 N10547 P6775 CAS 6 -1 N10546 0x3000124 Int BE Pri
96040!#6 N10548 P6776 DWLD 8 -1 Int BE Pri
96041!#6 N10549 P6777 ST 6 0x3000125 Int BE Pri
96042!#6 N10550 P6778 MEMBAR
96043!#6 N10551 P6779 BLD 9 -1 FP BE Pri
96044!#6 N10552 P6779 BLD 10 -1 FP BE Pri
96045!#A N10551 N10552
96046!#6 N10553 P6779 BLD 11 -1 FP BE Pri
96047!#6 N10554 P6780 MEMBAR
96048!#6 N10555 P6781 LDD 2 -1 Int BE Pri
96049!#6 N10556 P6782 MEMBAR
96050!#6 N10557 P6783 BSTC 6 0x428000dc FP BE Pri
96051!#6 N10558 P6783 BSTC 7 0x428000dd FP BE Pri
96052!#A N10557 N10558
96053!#6 N10559 P6783 BSTC 8 0x428000de FP BE Pri
96054!#6 N10560 P6784 MEMBAR
96055!#6 N10561 P6785 REPLACEMENT 20 Int BE Pri
96056!#6 N10562 P6786 SWAP 17 0xffffffff 0x3000126 Int BE Pri
96057!#6 N10563 P6787 LD 3 -1 Int LE Pri
96058!#6 N10564 P6788 LD 17 -1 Int BE Pri
96059!#6 N10565 P6788 CAS 17 -1 N10564 0x3000127 Int BE Pri
96060!#6 N10566 P6789 MEMBAR
96061!#6 N10567 P6790 BLD 18 -1 FP BE Pri
96062!#6 N10568 P6790 BLD 19 -1 FP BE Pri
96063!#A N10567 N10568
96064!#6 N10569 P6790 BLD 20 -1 FP BE Pri
96065!#6 N10570 P6791 MEMBAR
96066!#6 N10571 P6792 BLD 6 -1 FP BE Pri
96067!#6 N10572 P6792 BLD 7 -1 FP BE Pri
96068!#A N10571 N10572
96069!#6 N10573 P6792 BLD 8 -1 FP BE Pri
96070!#6 N10574 P6793 MEMBAR
96071!#6 N10575 P6794 BST 6 0x428000df FP BE Pri
96072!#6 N10576 P6794 BST 7 0x428000e0 FP BE Pri
96073!#A N10575 N10576
96074!#6 N10577 P6794 BST 8 0x428000e1 FP BE Pri
96075!#6 N10578 P6795 MEMBAR
96076!#6 N10579 P6796 LD 8 -1 Int BE Pri
96077!#6 N10580 P6797 MEMBAR
96078!#6 N10581 P6798 BSTC 18 0x428000e2 FP BE Pri
96079!#6 N10582 P6798 BSTC 19 0x428000e3 FP BE Pri
96080!#A N10581 N10582
96081!#6 N10583 P6798 BSTC 20 0x428000e4 FP BE Pri
96082!#6 N10584 P6799 MEMBAR
96083!#6 N10585 P6800 DWLD 17 -1 Int BE Pri
96084!#6 N10586 P6801 DWLD 12 -1 FP BE Pri
96085!#6 N10587 P6801 DWLD 13 -1 FP BE Pri
96086!#A N10586 N10587
96087!#6 N10588 P6802 PREFETCH 11 Int BE Pri
96088!#6 N10589 P6803 PREFETCH 6 Int BE Pri
96089!#6 N10590 P6804 DWST_BINIT 18 0x3000128 Int BE Pri
96090!#6 N10591 P6804 DWST_BINIT 19 0x3000129 Int BE Pri
96091!#A N10590 N10591
96092!#6 N10592 P6805 MEMBAR
96093!#6 N10593 P6806 ST_BINIT 17 0x300012a Int BE Pri
96094!#6 N10594 P6807 MEMBAR
96095!#6 N10595 P6808 DWST 17 0x300012b Int BE Pri
96096!#6 N10596 P6809 LD 17 -1 Int BE Pri
96097!#6 N10597 P6810 DWST_BINIT 5 0x300012c Int BE Pri
96098!#6 N10598 P6811 MEMBAR
96099!#6 N10599 P6812 LD 17 -1 Int BE Pri
96100!#6 N10600 P6812 CAS 17 -1 N10599 0x300012d Int BE Pri
96101!#6 N10601 P6813 DWST_BINIT 0 0x300012e Int BE Pri
96102!#6 N10602 P6813 DWST_BINIT 1 0x300012f Int BE Pri
96103!#A N10601 N10602
96104!#6 N10603 P6814 MEMBAR
96105!#6 N10604 P6815 BLD 12 -1 FP BE Pri
96106!#6 N10605 P6815 BLD 13 -1 FP BE Pri
96107!#A N10604 N10605
96108!#6 N10606 P6815 BLD 14 -1 FP BE Pri
96109!#6 N10607 P6816 MEMBAR
96110!#6 N10608 P6817 DWLD 17 -1 Int BE Pri
96111!#6 N10609 P6818 DWST 11 0x3000130 Int BE Pri
96112!#6 N10610 P6819 SWAP 21 0xffffffff 0x3000131 Int BE Pri
96113!#6 N10611 P6820 DWST 9 0x3000132 Int BE Pri
96114!#6 N10612 P6820 DWST 10 0x3000133 Int BE Pri
96115!#A N10611 N10612
96116!#6 N10613 P6821 LDD 11 -1 Int BE Pri
96117!#6 N10614 P6822 LD 1 -1 Int BE Pri
96118!#6 N10615 P6822 CAS 1 -1 N10614 0x3000134 Int BE Pri
96119!#6 N10616 P6823 SWAP 4 0xffffffff 0x3000135 Int BE Pri
96120!#6 N10617 P6824 LD 22 -1 Int BE Pri
96121!#6 N10618 P6825 DWLD 0 -1 Int BE Pri
96122!#6 N10619 P6825 DWLD 1 -1 Int BE Pri
96123!#A N10618 N10619
96124!#6 N10620 P6825 CASX 0 -1 N10618 0x3000136 Int BE Pri
96125!#6 N10621 P6825 CASX 1 -1 N10619 0x3000137 Int BE Pri
96126!#A N10620 N10621
96127!#6 N10622 P6826 DWLD 8 -1 Int BE Pri
96128!#6 N10623 P6827 DWLD 0 -1 Int LE Pri
96129!#6 N10624 P6827 DWLD 1 -1 Int LE Pri
96130!#A N10623 N10624
96131!#6 N10625 P6827 CASX 0 -1 N10623 0x3000138 Int LE Pri
96132!#6 N10626 P6827 CASX 1 -1 N10624 0x3000139 Int LE Pri
96133!#A N10625 N10626
96134!#6 N10627 P6828 SWAP 0 0xffffffff 0x300013a Int BE Pri
96135!#6 N10628 P6829 LDD 15 -1 Int LE Pri
96136!#6 N10629 P6829 LDD 16 -1 Int LE Pri
96137!#A N10628 N10629
96138!#6 N10630 P6830 LD 0 -1 Int BE Pri
96139!#6 N10631 P6831 ST 17 0x300013b Int BE Pri
96140!#6 N10632 P6832 ST 1 0x300013c Int BE Pri
96141!#6 N10633 P6833 DWLD 0 -1 FP BE Pri
96142!#6 N10634 P6833 DWLD 1 -1 FP BE Pri
96143!#A N10633 N10634
96144!#6 N10635 P6834 ST_BINIT 15 0x300013d Int LE Pri
96145!#6 N10636 P6835 MEMBAR
96146!#6 N10637 P6836 DWLD 9 -1 Int BE Pri
96147!#6 N10638 P6836 DWLD 10 -1 Int BE Pri
96148!#A N10637 N10638
96149!#6 N10639 P6836 CASX 9 -1 N10637 0x300013e Int BE Pri
96150!#6 N10640 P6836 CASX 10 -1 N10638 0x300013f Int BE Pri
96151!#A N10639 N10640
96152!#6 N10641 P6837 MEMBAR
96153!#6 N10642 P6838 BSTC 3 0x428000e5 FP BE Pri
96154!#6 N10643 P6838 BSTC 4 0x428000e6 FP BE Pri
96155!#A N10642 N10643
96156!#6 N10644 P6838 BSTC 5 0x428000e7 FP BE Pri
96157!#6 N10645 P6839 MEMBAR
96158!#6 N10646 P6840 LD 8 -1 Int LE Pri
96159!#6 N10647 P6841 MEMBAR
96160!#6 N10648 P6842 BSTC 21 0x428000e8 FP BE Pri
96161!#6 N10649 P6842 BSTC 22 0x428000e9 FP BE Pri
96162!#A N10648 N10649
96163!#6 N10650 P6842 BSTC 23 0x428000ea FP BE Pri
96164!#6 N10651 P6843 MEMBAR
96165!#6 N10652 P6844 PREFETCH 9 Int BE Pri
96166!#6 N10653 P6845 DWLD 8 -1 Int BE Pri
96167!#6 N10654 P6846 ST 8 0x3000140 Int BE Pri
96168!#6 N10655 P6847 MEMBAR
96169!#6 N10656 P6848 BSTC 0 0x428000eb FP BE Pri
96170!#6 N10657 P6848 BSTC 1 0x428000ec FP BE Pri
96171!#A N10656 N10657
96172!#6 N10658 P6848 BSTC 2 0x428000ed FP BE Pri
96173!#6 N10659 P6849 MEMBAR
96174!#6 N10660 P6850 LD 19 -1 Int BE Pri
96175!#6 N10661 P6850 CAS 19 -1 N10660 0x3000141 Int BE Pri
96176!#6 N10662 P6851 DWST_BINIT 0 0x3000142 Int BE Pri
96177!#6 N10663 P6851 DWST_BINIT 1 0x3000143 Int BE Pri
96178!#A N10662 N10663
96179!#6 N10664 P6852 MEMBAR
96180!#6 N10665 P6853 PREFETCH 14 Int BE Pri
96181!#6 N10666 P6854 PREFETCH 22 Int BE Pri
96182!#6 N10667 P6855 MEMBAR
96183!#6 N10668 P6856 BSTC 12 0x428000ee FP BE Pri
96184!#6 N10669 P6856 BSTC 13 0x428000ef FP BE Pri
96185!#A N10668 N10669
96186!#6 N10670 P6856 BSTC 14 0x428000f0 FP BE Pri
96187!#6 N10671 P6857 MEMBAR
96188!#6 N10672 P6858 DWST 2 0x3000144 Int BE Pri
96189!#6 N10673 P6859 ST 18 0x3000145 Int BE Pri
96190!#6 N10674 P6860 ST_BINIT 9 0x3000146 Int BE Pri
96191!#6 N10675 P6861 MEMBAR
96192!#6 N10676 P6862 DWST 21 0x3000147 Int BE Pri
96193!#6 N10677 P6862 DWST 22 0x3000148 Int BE Pri
96194!#A N10676 N10677
96195!#6 N10678 P6863 DWST 8 0x3000149 Int BE Pri
96196!#6 N10679 P6864 DWLD 9 -1 Int BE Pri
96197!#6 N10680 P6864 DWLD 10 -1 Int BE Pri
96198!#A N10679 N10680
96199!#6 N10681 P6864 CASX 9 -1 N10679 0x300014a Int BE Pri
96200!#6 N10682 P6864 CASX 10 -1 N10680 0x300014b Int BE Pri
96201!#A N10681 N10682
96202!#6 N10683 P6865 DWLD 11 -1,0x0 Int BE Pri
96203!#6 N10684 P6865 CASX 11 -1,0x0 N10683 0x300014c Int BE Pri
96204!#6 N10685 P6866 SWAP 2 0xffffffff 0x300014d Int BE Pri
96205!#6 N10686 P6867 DWLD 23 -1,0x0 Int BE Pri
96206!#6 N10687 P6867 CASX 23 -1,0x0 N10686 0x300014e Int BE Pri
96207!#6 N10688 P6868 SWAP 7 0xffffffff 0x300014f Int BE Pri
96208!#6 N10689 P6869 ST 15 0x3000150 Int BE Pri
96209!#6 N10690 P6870 ST 13 0x428000f1 FP BE Pri
96210!#6 N10691 P6871 DWST_BINIT 15 0x3000151 Int BE Pri
96211!#6 N10692 P6871 DWST_BINIT 16 0x3000152 Int BE Pri
96212!#A N10691 N10692
96213!#6 N10693 P6872 MEMBAR
96214!#6 N10694 P6873 DWLD 12 -1 Int BE Pri
96215!#6 N10695 P6873 DWLD 13 -1 Int BE Pri
96216!#A N10694 N10695
96217!#6 N10696 P6874 SWAP 4 0xffffffff 0x3000153 Int BE Pri
96218!#6 N10697 P6875 DWLD 17 -1,0x0 Int BE Pri
96219!#6 N10698 P6875 CASX 17 -1,0x0 N10697 0x3000154 Int BE Pri
96220!#6 N10699 P6876 REPLACEMENT 18 Int BE Pri
96221!#6 N10700 P6877 MEMBAR
96222!#6 N10701 P6878 BST 18 0x428000f2 FP BE Pri
96223!#6 N10702 P6878 BST 19 0x428000f3 FP BE Pri
96224!#A N10701 N10702
96225!#6 N10703 P6878 BST 20 0x428000f4 FP BE Pri
96226!#6 N10704 P6879 MEMBAR
96227!#6 N10705 P6880 BSTC 21 0x428000f5 FP BE Pri
96228!#6 N10706 P6880 BSTC 22 0x428000f6 FP BE Pri
96229!#A N10705 N10706
96230!#6 N10707 P6880 BSTC 23 0x428000f7 FP BE Pri
96231!#6 N10708 P6881 MEMBAR
96232!#6 N10709 P6882 PREFETCH 0 Int BE Pri
96233!#6 N10710 P6883 DWST 15 0x3000155 Int BE Pri
96234!#6 N10711 P6883 DWST 16 0x3000156 Int BE Pri
96235!#A N10710 N10711
96236!#6 N10712 P6884 ST 12 0x3000157 Int BE Pri
96237!#6 N10713 P6885 REPLACEMENT 10 Int BE Pri
96238!#6 N10714 P6886 MEMBAR
96239!#6 N10715 P6887 BLD 21 -1 FP BE Pri
96240!#6 N10716 P6887 BLD 22 -1 FP BE Pri
96241!#A N10715 N10716
96242!#6 N10717 P6887 BLD 23 -1 FP BE Pri
96243!#6 N10718 P6888 MEMBAR
96244!#6 N10719 P6889 DWST 21 0x3000158 Int BE Pri
96245!#6 N10720 P6889 DWST 22 0x3000159 Int BE Pri
96246!#A N10719 N10720
96247!#6 N10721 P6890 DWLD 0 -1 Int BE Pri
96248!#6 N10722 P6890 DWLD 1 -1 Int BE Pri
96249!#A N10721 N10722
96250!#6 N10723 P6891 ST 23 0x300015a Int BE Pri
96251!#6 N10724 P6892 MEMBAR
96252!#6 N10725 P6893 BST 3 0x428000f8 FP BE Pri
96253!#6 N10726 P6893 BST 4 0x428000f9 FP BE Pri
96254!#A N10725 N10726
96255!#6 N10727 P6893 BST 5 0x428000fa FP BE Pri
96256!#6 N10728 P6894 MEMBAR
96257!#6 N10729 P6895 LD 8 -1 Int BE Pri
96258!#6 N10730 P6895 CAS 8 -1 N10729 0x300015b Int BE Pri
96259!#6 N10731 P6896 DWST_BINIT 6 0x300015c Int BE Pri
96260!#6 N10732 P6896 DWST_BINIT 7 0x300015d Int BE Pri
96261!#A N10731 N10732
96262!#6 N10733 P6897 MEMBAR
96263!#6 N10734 P6898 DWST_BINIT 12 0x300015e Int BE Pri
96264!#6 N10735 P6898 DWST_BINIT 13 0x300015f Int BE Pri
96265!#A N10734 N10735
96266!#6 N10736 P6899 MEMBAR
96267!#6 N10737 P6900 LD 18 -1 Int BE Pri
96268!#6 N10738 P6900 CAS 18 -1 N10737 0x3000160 Int BE Pri
96269!#6 N10739 P6901 PREFETCH 7 Int BE Pri
96270!#6 N10740 P6902 LD 13 -1 Int BE Pri
96271!#6 N10741 P6902 CAS 13 -1 N10740 0x3000161 Int BE Pri
96272!#6 N10742 P6903 REPLACEMENT 0 Int BE Pri
96273!#6 N10743 P6904 ST_BINIT 12 0x3000162 Int BE Pri
96274!#6 N10744 P6905 MEMBAR
96275!#6 N10745 P6906 LD 22 -1 FP BE Pri
96276!#6 N10746 P6907 DWLD 15 -1 Int BE Pri
96277!#6 N10747 P6907 DWLD 16 -1 Int BE Pri
96278!#A N10746 N10747
96279!#6 N10748 P6907 CASX 15 -1 N10746 0x3000163 Int BE Pri
96280!#6 N10749 P6907 CASX 16 -1 N10747 0x3000164 Int BE Pri
96281!#A N10748 N10749
96282!#6 N10750 P6908 MEMBAR
96283!#6 N10751 P6909 BST 15 0x428000fb FP BE Pri
96284!#6 N10752 P6909 BST 16 0x428000fc FP BE Pri
96285!#A N10751 N10752
96286!#6 N10753 P6909 BST 17 0x428000fd FP BE Pri
96287!#6 N10754 P6910 MEMBAR
96288!#6 N10755 P6911 ST 10 0x3000165 Int BE Pri
96289!#6 N10756 P6912 DWST_BINIT 21 0x3000166 Int BE Pri
96290!#6 N10757 P6912 DWST_BINIT 22 0x3000167 Int BE Pri
96291!#A N10756 N10757
96292!#6 N10758 P6913 MEMBAR
96293!#6 N10759 P6914 DWST_BINIT 9 0x3000168 Int BE Pri
96294!#6 N10760 P6914 DWST_BINIT 10 0x3000169 Int BE Pri
96295!#A N10759 N10760
96296!#6 N10761 P6915 MEMBAR
96297!#6 N10762 P6916 BST 9 0x428000fe FP BE Pri
96298!#6 N10763 P6916 BST 10 0x428000ff FP BE Pri
96299!#A N10762 N10763
96300!#6 N10764 P6916 BST 11 0x42800100 FP BE Pri
96301!#6 N10765 P6917 MEMBAR
96302!#6 N10766 P6918 DWLD 9 -1 Int BE Pri
96303!#6 N10767 P6918 DWLD 10 -1 Int BE Pri
96304!#A N10766 N10767
96305!#6 N10768 P6918 CASX 9 -1 N10766 0x300016a Int BE Pri
96306!#6 N10769 P6918 CASX 10 -1 N10767 0x300016b Int BE Pri
96307!#A N10768 N10769
96308!#6 N10770 P6919 MEMBAR
96309!#6 N10771 P6920 BSTC 6 0x42800101 FP BE Pri
96310!#6 N10772 P6920 BSTC 7 0x42800102 FP BE Pri
96311!#A N10771 N10772
96312!#6 N10773 P6920 BSTC 8 0x42800103 FP BE Pri
96313!#6 N10774 P6921 MEMBAR
96314!#6 N10775 P6922 LDD 0 -1 Int BE Pri
96315!#6 N10776 P6922 LDD 1 -1 Int BE Pri
96316!#A N10775 N10776
96317!#6 N10777 P6923 MEMBAR
96318!#6 N10778 P6924 BST 18 0x42800104 FP BE Pri
96319!#6 N10779 P6924 BST 19 0x42800105 FP BE Pri
96320!#A N10778 N10779
96321!#6 N10780 P6924 BST 20 0x42800106 FP BE Pri
96322!#6 N10781 P6925 MEMBAR
96323!#6 N10782 P6926 LDD 23 -1 Int BE Pri
96324!#6 N10783 P6927 LDD 9 -1 Int BE Pri
96325!#6 N10784 P6927 LDD 10 -1 Int BE Pri
96326!#A N10783 N10784
96327!#6 N10785 P6928 MEMBAR
96328!#6 N10786 P6929 BST 3 0x42800107 FP BE Pri
96329!#6 N10787 P6929 BST 4 0x42800108 FP BE Pri
96330!#A N10786 N10787
96331!#6 N10788 P6929 BST 5 0x42800109 FP BE Pri
96332!#6 N10789 P6930 MEMBAR
96333!#6 N10790 P6931 DWLD 21 -1 Int BE Pri
96334!#6 N10791 P6931 DWLD 22 -1 Int BE Pri
96335!#A N10790 N10791
96336!#6 N10792 P6932 ST 23 0x300016c Int BE Pri
96337!#6 N10793 P6933 MEMBAR
96338!#6 N10794 P6934 BST 12 0x4280010a FP BE Pri
96339!#6 N10795 P6934 BST 13 0x4280010b FP BE Pri
96340!#A N10794 N10795
96341!#6 N10796 P6934 BST 14 0x4280010c FP BE Pri
96342!#6 N10797 P6935 MEMBAR
96343!#6 N10798 P6936 ST 9 0x300016d Int BE Pri
96344!#6 N10799 P6937 DWST_BINIT 15 0x300016e Int BE Pri
96345!#6 N10800 P6937 DWST_BINIT 16 0x300016f Int BE Pri
96346!#A N10799 N10800
96347!#6 N10801 P6938 MEMBAR
96348!#6 N10802 P6939 LD 8 -1 Int BE Pri
96349!#6 N10803 P6939 CAS 8 -1 N10802 0x3000170 Int BE Pri
96350!#6 N10804 P6940 MEMBAR
96351!#6 N10805 P6941 BST 6 0x4280010d FP BE Pri
96352!#6 N10806 P6941 BST 7 0x4280010e FP BE Pri
96353!#A N10805 N10806
96354!#6 N10807 P6941 BST 8 0x4280010f FP BE Pri
96355!#6 N10808 P6942 MEMBAR
96356!#6 N10809 P6943 SWAP 20 0xffffffff 0x3000171 Int BE Pri
96357!#6 N10810 P6944 ST_BINIT 4 0x3000172 Int BE Pri
96358!#6 N10811 P6945 MEMBAR
96359!#6 N10812 P6946 DWST_BINIT 9 0x3000173 Int BE Pri
96360!#6 N10813 P6946 DWST_BINIT 10 0x3000174 Int BE Pri
96361!#A N10812 N10813
96362!#6 N10814 P6947 MEMBAR
96363!#6 N10815 P6948 DWLD 3 -1 Int BE Pri
96364!#6 N10816 P6948 DWLD 4 -1 Int BE Pri
96365!#A N10815 N10816
96366!#6 N10817 P6948 CASX 3 -1 N10815 0x3000175 Int BE Pri
96367!#6 N10818 P6948 CASX 4 -1 N10816 0x3000176 Int BE Pri
96368!#A N10817 N10818
96369!#6 N10819 P6949 LDD 18 -1 Int BE Pri
96370!#6 N10820 P6949 LDD 19 -1 Int BE Pri
96371!#A N10819 N10820
96372!#6 N10821 P6950 DWLD 5 -1,0x0 Int BE Pri
96373!#6 N10822 P6950 CASX 5 -1,0x0 N10821 0x3000177 Int BE Pri
96374!#6 N10823 P6951 ST_BINIT 16 0x3000178 Int BE Pri
96375!#6 N10824 P6952 MEMBAR
96376!#6 N10825 P6953 BLD 21 -1 FP BE Pri
96377!#6 N10826 P6953 BLD 22 -1 FP BE Pri
96378!#A N10825 N10826
96379!#6 N10827 P6953 BLD 23 -1 FP BE Pri
96380!#6 N10828 P6954 MEMBAR
96381!#6 N10829 P6955 PREFETCH 2 Int BE Pri
96382!#6 N10830 P6956 DWLD 6 -1 Int BE Pri
96383!#6 N10831 P6956 DWLD 7 -1 Int BE Pri
96384!#A N10830 N10831
96385!#6 N10832 P6956 CASX 6 -1 N10830 0x3000179 Int BE Pri
96386!#6 N10833 P6956 CASX 7 -1 N10831 0x300017a Int BE Pri
96387!#A N10832 N10833
96388!#6 N10834 P6957 LDD 8 -1 Int BE Pri
96389!#6 N10835 P6958 ST 18 0x300017b Int BE Pri
96390!#6 N10836 P6959 ST_BINIT 13 0x300017c Int BE Pri
96391!#6 N10837 P6960 MEMBAR
96392!#6 N10838 P6961 PREFETCH 21 Int BE Pri
96393!#6 N10839 P6962 MEMBAR
96394!#6 N10840 P6963 BLD 9 -1 FP BE Pri
96395!#6 N10841 P6963 BLD 10 -1 FP BE Pri
96396!#A N10840 N10841
96397!#6 N10842 P6963 BLD 11 -1 FP BE Pri
96398!#6 N10843 P6964 MEMBAR
96399!#6 N10844 P6965 LD 6 -1 Int BE Pri
96400!#6 N10845 P6966 MEMBAR
96401!#6 N10846 P6967 BLD 6 -1 FP BE Pri
96402!#6 N10847 P6967 BLD 7 -1 FP BE Pri
96403!#A N10846 N10847
96404!#6 N10848 P6967 BLD 8 -1 FP BE Pri
96405!#6 N10849 P6968 MEMBAR
96406!#6 N10850 P6969 DWST_BINIT 12 0x300017d Int LE Pri
96407!#6 N10851 P6969 DWST_BINIT 13 0x300017e Int LE Pri
96408!#A N10850 N10851
96409!#6 N10852 P6970 MEMBAR
96410!#6 N10853 P6971 DWST_BINIT 9 0x300017f Int BE Pri
96411!#6 N10854 P6971 DWST_BINIT 10 0x3000180 Int BE Pri
96412!#A N10853 N10854
96413!#6 N10855 P6972 MEMBAR
96414!#6 N10856 P6973 BSTC 18 0x42800110 FP BE Pri
96415!#6 N10857 P6973 BSTC 19 0x42800111 FP BE Pri
96416!#A N10856 N10857
96417!#6 N10858 P6973 BSTC 20 0x42800112 FP BE Pri
96418!#6 N10859 P6974 MEMBAR
96419!#6 N10860 P6975 DWLD 18 -1 Int BE Pri
96420!#6 N10861 P6975 DWLD 19 -1 Int BE Pri
96421!#A N10860 N10861
96422!#6 N10862 P6975 CASX 18 -1 N10860 0x3000181 Int BE Pri
96423!#6 N10863 P6975 CASX 19 -1 N10861 0x3000182 Int BE Pri
96424!#A N10862 N10863
96425!#6 N10864 P6976 MEMBAR
96426!#6 N10865 P6977 BST 15 0x42800113 FP BE Pri
96427!#6 N10866 P6977 BST 16 0x42800114 FP BE Pri
96428!#A N10865 N10866
96429!#6 N10867 P6977 BST 17 0x42800115 FP BE Pri
96430!#6 N10868 P6978 MEMBAR
96431!#6 N10869 P6979 ST 21 0x3000183 Int BE Pri
96432!#6 N10870 P6980 DWLD 21 -1 Int BE Pri
96433!#6 N10871 P6980 DWLD 22 -1 Int BE Pri
96434!#A N10870 N10871
96435!#6 N10872 P6980 CASX 21 -1 N10870 0x3000184 Int BE Pri
96436!#6 N10873 P6980 CASX 22 -1 N10871 0x3000185 Int BE Pri
96437!#A N10872 N10873
96438!#6 N10874 P6981 MEMBAR
96439!#6 N10875 P6982 BLD 9 -1 FP BE Pri
96440!#6 N10876 P6982 BLD 10 -1 FP BE Pri
96441!#A N10875 N10876
96442!#6 N10877 P6982 BLD 11 -1 FP BE Pri
96443!#6 N10878 P6983 MEMBAR
96444!#6 N10879 P6984 DWLD 5 -1,0x0 Int BE Pri
96445!#6 N10880 P6984 CASX 5 -1,0x0 N10879 0x3000186 Int BE Pri
96446!#6 N10881 P6985 REPLACEMENT 6 Int BE Pri
96447!#6 N10882 P6986 DWLD 12 -1 Int BE Pri
96448!#6 N10883 P6986 DWLD 13 -1 Int BE Pri
96449!#A N10882 N10883
96450!#6 N10884 P6986 CASX 12 -1 N10882 0x3000187 Int BE Pri
96451!#6 N10885 P6986 CASX 13 -1 N10883 0x3000188 Int BE Pri
96452!#A N10884 N10885
96453!#6 N10886 P6987 LD 14 -1 Int BE Pri
96454!#6 N10887 P6988 DWLD 15 -1 Int BE Pri
96455!#6 N10888 P6988 DWLD 16 -1 Int BE Pri
96456!#A N10887 N10888
96457!#6 N10889 P6988 CASX 15 -1 N10887 0x3000189 Int BE Pri
96458!#6 N10890 P6988 CASX 16 -1 N10888 0x300018a Int BE Pri
96459!#A N10889 N10890
96460!#6 N10891 P6989 DWLD 8 -1,0x0 Int BE Pri
96461!#6 N10892 P6989 CASX 8 -1,0x0 N10891 0x300018b Int BE Pri
96462!#6 N10893 P6990 DWLD 3 -1 Int BE Pri
96463!#6 N10894 P6990 DWLD 4 -1 Int BE Pri
96464!#A N10893 N10894
96465!#6 N10895 P6990 CASX 3 -1 N10893 0x300018c Int BE Pri
96466!#6 N10896 P6990 CASX 4 -1 N10894 0x300018d Int BE Pri
96467!#A N10895 N10896
96468!#6 N10897 P6991 DWLD 15 -1 Int BE Pri
96469!#6 N10898 P6991 DWLD 16 -1 Int BE Pri
96470!#A N10897 N10898
96471!#6 N10899 P6991 CASX 15 -1 N10897 0x300018e Int BE Pri
96472!#6 N10900 P6991 CASX 16 -1 N10898 0x300018f Int BE Pri
96473!#A N10899 N10900
96474!#6 N10901 P6992 DWST_BINIT 21 0x3000190 Int BE Pri
96475!#6 N10902 P6992 DWST_BINIT 22 0x3000191 Int BE Pri
96476!#A N10901 N10902
96477!#6 N10903 P6993 MEMBAR
96478!#6 N10904 P6994 PREFETCH 14 Int BE Pri
96479!#6 N10905 P6995 SWAP 19 0xffffffff 0x3000192 Int BE Pri
96480!#6 N10906 P6996 MEMBAR
96481!#6 N10907 P6997 BLD 3 -1 FP BE Pri
96482!#6 N10908 P6997 BLD 4 -1 FP BE Pri
96483!#A N10907 N10908
96484!#6 N10909 P6997 BLD 5 -1 FP BE Pri
96485!#6 N10910 P6998 MEMBAR
96486!#6 N10911 P6999 DWST_BINIT 3 0x3000193 Int BE Pri
96487!#6 N10912 P6999 DWST_BINIT 4 0x3000194 Int BE Pri
96488!#A N10911 N10912
96489!#6 N10913 P7000 MEMBAR
96490!#6 N10914 P7001 BST 3 0x42800116 FP BE Pri
96491!#6 N10915 P7001 BST 4 0x42800117 FP BE Pri
96492!#A N10914 N10915
96493!#6 N10916 P7001 BST 5 0x42800118 FP BE Pri
96494!#6 N10917 P7002 MEMBAR
96495!#6 N10918 P7003 BLD 18 -1 FP BE Pri
96496!#6 N10919 P7003 BLD 19 -1 FP BE Pri
96497!#A N10918 N10919
96498!#6 N10920 P7003 BLD 20 -1 FP BE Pri
96499!#6 N10921 P7004 MEMBAR
96500!#6 N10922 P7005 LDD 9 -1 Int BE Pri
96501!#6 N10923 P7005 LDD 10 -1 Int BE Pri
96502!#A N10922 N10923
96503!#6 N10924 P7006 SWAP 12 0xffffffff 0x3000195 Int BE Pri
96504!#6 N10925 P7007 ST_BINIT 17 0x3000196 Int BE Pri
96505!#6 N10926 P7008 MEMBAR
96506!#6 N10927 P7009 ST_BINIT 2 0x3000197 Int BE Pri
96507!#6 N10928 P7010 MEMBAR
96508!#6 N10929 P7011 DWST_BINIT 0 0x3000198 Int BE Pri
96509!#6 N10930 P7011 DWST_BINIT 1 0x3000199 Int BE Pri
96510!#A N10929 N10930
96511!#6 N10931 P7012 MEMBAR
96512!#6 N10932 P7013 BSTC 9 0x42800119 FP BE Pri
96513!#6 N10933 P7013 BSTC 10 0x4280011a FP BE Pri
96514!#A N10932 N10933
96515!#6 N10934 P7013 BSTC 11 0x4280011b FP BE Pri
96516!#6 N10935 P7014 MEMBAR
96517!#6 N10936 P7015 MEMBAR
96518!#7 N10937 P7016 DWLD 21 -1 Int BE Pri Loop_entry
96519!#7 N10938 P7016 DWLD 22 -1 Int BE Pri Loop_entry
96520!#A N10937 N10938
96521!#7 N10939 P7016 CASX 21 -1 N10937 0x3800001 Int BE Pri Loop_entry
96522!#7 N10940 P7016 CASX 22 -1 N10938 0x3800002 Int BE Pri Loop_entry
96523!#A N10939 N10940
96524!#7 N10941 P7017 DWST 5 0x3800003 Int BE Pri
96525!#7 N10942 P7018 PREFETCH 7 Int BE Pri
96526!#7 N10943 P7019 DWLD 3 -1 Int BE Pri
96527!#7 N10944 P7019 DWLD 4 -1 Int BE Pri
96528!#A N10943 N10944
96529!#7 N10945 P7019 CASX 3 -1 N10943 0x3800004 Int BE Pri
96530!#7 N10946 P7019 CASX 4 -1 N10944 0x3800005 Int BE Pri
96531!#A N10945 N10946
96532!#7 N10947 P7020 MEMBAR
96533!#7 N10948 P7021 BST 12 0x43000001 FP BE Pri
96534!#7 N10949 P7021 BST 13 0x43000002 FP BE Pri
96535!#A N10948 N10949
96536!#7 N10950 P7021 BST 14 0x43000003 FP BE Pri
96537!#7 N10951 P7022 MEMBAR
96538!#7 N10952 P7023 SWAP 7 0xffffffff 0x3800006 Int BE Pri
96539!#7 N10953 P7024 PREFETCH 7 Int BE Pri
96540!#7 N10954 P7025 DWLD 11 -1 Int BE Pri
96541!#7 N10955 P7026 LD 16 -1 Int BE Pri
96542!#7 N10956 P7027 MEMBAR
96543!#7 N10957 P7028 BSTC 12 0x43000004 FP BE Pri
96544!#7 N10958 P7028 BSTC 13 0x43000005 FP BE Pri
96545!#A N10957 N10958
96546!#7 N10959 P7028 BSTC 14 0x43000006 FP BE Pri
96547!#7 N10960 P7029 MEMBAR
96548!#7 N10961 P7030 LD 11 -1 Int BE Pri
96549!#7 N10962 P7030 CAS 11 -1 N10961 0x3800007 Int BE Pri
96550!#7 N10963 P7031 SWAP 21 0xffffffff 0x3800008 Int BE Pri
96551!#7 N10964 P7032 ST_BINIT 22 0x3800009 Int BE Pri
96552!#7 N10965 P7033 MEMBAR
96553!#7 N10966 P7034 SWAP 15 0xffffffff 0x380000a Int BE Pri
96554!#7 N10967 P7035 LDD 2 -1 Int BE Pri
96555!#7 N10968 P7036 DWLD 2 -1 Int BE Pri
96556!#7 N10969 P7037 ST_BINIT 14 0x380000b Int BE Pri
96557!#7 N10970 P7038 MEMBAR
96558!#7 N10971 P7039 BLD 12 -1 FP BE Pri
96559!#7 N10972 P7039 BLD 13 -1 FP BE Pri
96560!#A N10971 N10972
96561!#7 N10973 P7039 BLD 14 -1 FP BE Pri
96562!#7 N10974 P7040 MEMBAR
96563!#7 N10975 P7041 BST 6 0x43000007 FP BE Pri
96564!#7 N10976 P7041 BST 7 0x43000008 FP BE Pri
96565!#A N10975 N10976
96566!#7 N10977 P7041 BST 8 0x43000009 FP BE Pri
96567!#7 N10978 P7042 MEMBAR
96568!#7 N10979 P7043 DWLD 23 -1 FP BE Pri
96569!#7 N10980 P7044 MEMBAR
96570!#7 N10981 P7045 BST 3 0x4300000a FP BE Pri
96571!#7 N10982 P7045 BST 4 0x4300000b FP BE Pri
96572!#A N10981 N10982
96573!#7 N10983 P7045 BST 5 0x4300000c FP BE Pri
96574!#7 N10984 P7046 MEMBAR
96575!#7 N10985 P7047 ST_BINIT 5 0x380000c Int BE Pri
96576!#7 N10986 P7048 MEMBAR
96577!#7 N10987 P7049 DWLD 21 -1 Int BE Pri
96578!#7 N10988 P7049 DWLD 22 -1 Int BE Pri
96579!#A N10987 N10988
96580!#7 N10989 P7050 LD 2 -1 Int BE Pri
96581!#7 N10990 P7050 CAS 2 -1 N10989 0x380000d Int BE Pri
96582!#7 N10991 P7051 MEMBAR
96583!#7 N10992 P7052 BLD 15 -1 FP BE Pri
96584!#7 N10993 P7052 BLD 16 -1 FP BE Pri
96585!#A N10992 N10993
96586!#7 N10994 P7052 BLD 17 -1 FP BE Pri
96587!#7 N10995 P7053 MEMBAR
96588!#7 N10996 P7054 BST 12 0x4300000d FP BE Pri
96589!#7 N10997 P7054 BST 13 0x4300000e FP BE Pri
96590!#A N10996 N10997
96591!#7 N10998 P7054 BST 14 0x4300000f FP BE Pri
96592!#7 N10999 P7055 MEMBAR
96593!#7 N11000 P7056 ST 15 0x380000e Int LE Pri
96594!#7 N11001 P7057 DWST_BINIT 6 0x380000f Int BE Pri
96595!#7 N11002 P7057 DWST_BINIT 7 0x3800010 Int BE Pri
96596!#A N11001 N11002
96597!#7 N11003 P7058 MEMBAR
96598!#7 N11004 P7059 ST_BINIT 21 0x3800011 Int BE Pri
96599!#7 N11005 P7060 MEMBAR
96600!#7 N11006 P7061 DWST 6 0x3800012 Int LE Pri
96601!#7 N11007 P7061 DWST 7 0x3800013 Int LE Pri
96602!#A N11006 N11007
96603!#7 N11008 P7062 LD 6 -1 Int BE Pri
96604!#7 N11009 P7062 CAS 6 -1 N11008 0x3800014 Int BE Pri
96605!#7 N11010 P7063 SWAP 22 0xffffffff 0x3800015 Int BE Pri
96606!#7 N11011 P7064 DWST_BINIT 18 0x3800016 Int BE Pri
96607!#7 N11012 P7064 DWST_BINIT 19 0x3800017 Int BE Pri
96608!#A N11011 N11012
96609!#7 N11013 P7065 MEMBAR
96610!#7 N11014 P7066 LD 2 -1 Int BE Pri
96611!#7 N11015 P7067 LD 15 -1 Int BE Pri
96612!#7 N11016 P7067 CAS 15 -1 N11015 0x3800018 Int BE Pri
96613!#7 N11017 P7068 REPLACEMENT 21 Int BE Pri
96614!#7 N11018 P7069 DWLD 8 -1 Int BE Pri
96615!#7 N11019 P7070 PREFETCH 21 Int BE Pri
96616!#7 N11020 P7071 SWAP 7 0xffffffff 0x3800019 Int BE Pri
96617!#7 N11021 P7072 DWST 18 0x380001a Int BE Pri
96618!#7 N11022 P7072 DWST 19 0x380001b Int BE Pri
96619!#A N11021 N11022
96620!#7 N11023 P7073 ST_BINIT 0 0x380001c Int BE Pri
96621!#7 N11024 P7074 MEMBAR
96622!#7 N11025 P7075 ST 21 0x380001d Int LE Pri
96623!#7 N11026 P7076 ST 4 0x380001e Int BE Pri
96624!#7 N11027 P7077 LD 18 -1 Int BE Pri
96625!#7 N11028 P7077 CAS 18 -1 N11027 0x380001f Int BE Pri
96626!#7 N11029 P7078 DWLD 20 -1,0x0 Int BE Pri
96627!#7 N11030 P7078 CASX 20 -1,0x0 N11029 0x3800020 Int BE Pri
96628!#7 N11031 P7079 DWST 3 0x3800021 Int BE Pri
96629!#7 N11032 P7079 DWST 4 0x3800022 Int BE Pri
96630!#A N11031 N11032
96631!#7 N11033 P7080 DWLD 6 -1 Int LE Pri
96632!#7 N11034 P7080 DWLD 7 -1 Int LE Pri
96633!#A N11033 N11034
96634!#7 N11035 P7081 DWLD 3 -1 Int BE Pri
96635!#7 N11036 P7081 DWLD 4 -1 Int BE Pri
96636!#A N11035 N11036
96637!#7 N11037 P7081 CASX 3 -1 N11035 0x3800023 Int BE Pri
96638!#7 N11038 P7081 CASX 4 -1 N11036 0x3800024 Int BE Pri
96639!#A N11037 N11038
96640!#7 N11039 P7082 MEMBAR
96641!#7 N11040 P7083 BSTC 3 0x43000010 FP BE Pri
96642!#7 N11041 P7083 BSTC 4 0x43000011 FP BE Pri
96643!#A N11040 N11041
96644!#7 N11042 P7083 BSTC 5 0x43000012 FP BE Pri
96645!#7 N11043 P7084 MEMBAR
96646!#7 N11044 P7085 PREFETCH 5 Int BE Pri
96647!#7 N11045 P7086 SWAP 13 0xffffffff 0x3800025 Int BE Pri
96648!#7 N11046 P7087 SWAP 2 0xffffffff 0x3800026 Int BE Pri
96649!#7 N11047 P7088 MEMBAR
96650!#7 N11048 P7089 BLD 12 -1 FP BE Pri
96651!#7 N11049 P7089 BLD 13 -1 FP BE Pri
96652!#A N11048 N11049
96653!#7 N11050 P7089 BLD 14 -1 FP BE Pri
96654!#7 N11051 P7090 MEMBAR
96655!#7 N11052 P7091 SWAP 18 0xffffffff 0x3800027 Int BE Pri
96656!#7 N11053 P7092 DWST_BINIT 18 0x3800028 Int BE Pri
96657!#7 N11054 P7092 DWST_BINIT 19 0x3800029 Int BE Pri
96658!#A N11053 N11054
96659!#7 N11055 P7093 MEMBAR
96660!#7 N11056 P7094 PREFETCH 19 Int BE Pri
96661!#7 N11057 P7095 PREFETCH 11 Int BE Pri
96662!#7 N11058 P7096 MEMBAR
96663!#7 N11059 P7097 BLD 0 -1 FP BE Pri
96664!#7 N11060 P7097 BLD 1 -1 FP BE Pri
96665!#A N11059 N11060
96666!#7 N11061 P7097 BLD 2 -1 FP BE Pri
96667!#7 N11062 P7098 MEMBAR
96668!#7 N11063 P7099 ST_BINIT 14 0x380002a Int BE Pri
96669!#7 N11064 P7100 MEMBAR
96670!#7 N11065 P7101 DWST 15 0x380002b Int BE Pri
96671!#7 N11066 P7101 DWST 16 0x380002c Int BE Pri
96672!#A N11065 N11066
96673!#7 N11067 P7102 LD 3 -1 Int BE Pri
96674!#7 N11068 P7102 CAS 3 -1 N11067 0x380002d Int BE Pri
96675!#7 N11069 P7103 MEMBAR
96676!#7 N11070 P7104 BST 6 0x43000013 FP BE Pri
96677!#7 N11071 P7104 BST 7 0x43000014 FP BE Pri
96678!#A N11070 N11071
96679!#7 N11072 P7104 BST 8 0x43000015 FP BE Pri
96680!#7 N11073 P7105 MEMBAR
96681!#7 N11074 P7106 SWAP 13 0xffffffff 0x380002e Int BE Pri
96682!#7 N11075 P7107 REPLACEMENT 2 Int BE Pri
96683!#7 N11076 P7108 MEMBAR
96684!#7 N11077 P7109 BSTC 9 0x43000016 FP BE Pri
96685!#7 N11078 P7109 BSTC 10 0x43000017 FP BE Pri
96686!#A N11077 N11078
96687!#7 N11079 P7109 BSTC 11 0x43000018 FP BE Pri
96688!#7 N11080 P7110 MEMBAR
96689!#7 N11081 P7111 LDD 21 -1 Int BE Pri
96690!#7 N11082 P7111 LDD 22 -1 Int BE Pri
96691!#A N11081 N11082
96692!#7 N11083 P7112 REPLACEMENT 19 Int BE Pri
96693!#7 N11084 P7113 DWST 23 0x380002f Int BE Pri
96694!#7 N11085 P7114 DWLD 12 -1 Int LE Pri
96695!#7 N11086 P7114 DWLD 13 -1 Int LE Pri
96696!#A N11085 N11086
96697!#7 N11087 P7114 CASX 12 -1 N11085 0x3800030 Int LE Pri
96698!#7 N11088 P7114 CASX 13 -1 N11086 0x3800031 Int LE Pri
96699!#A N11087 N11088
96700!#7 N11089 P7115 ST 23 0x3800032 Int BE Pri
96701!#7 N11090 P7116 PREFETCH 7 Int BE Pri
96702!#7 N11091 P7117 LD 6 -1 Int BE Pri
96703!#7 N11092 P7118 SWAP 20 0xffffffff 0x3800033 Int BE Pri
96704!#7 N11093 P7119 MEMBAR
96705!#7 N11094 P7120 BSTC 21 0x43000019 FP BE Pri
96706!#7 N11095 P7120 BSTC 22 0x4300001a FP BE Pri
96707!#A N11094 N11095
96708!#7 N11096 P7120 BSTC 23 0x4300001b FP BE Pri
96709!#7 N11097 P7121 MEMBAR
96710!#7 N11098 P7122 DWST 9 0x3800034 Int BE Pri
96711!#7 N11099 P7122 DWST 10 0x3800035 Int BE Pri
96712!#A N11098 N11099
96713!#7 N11100 P7123 DWST 5 0x3800036 Int BE Pri
96714!#7 N11101 P7124 REPLACEMENT 13 Int BE Pri
96715!#7 N11102 P7125 MEMBAR
96716!#7 N11103 P7126 BST 18 0x4300001c FP BE Pri
96717!#7 N11104 P7126 BST 19 0x4300001d FP BE Pri
96718!#A N11103 N11104
96719!#7 N11105 P7126 BST 20 0x4300001e FP BE Pri
96720!#7 N11106 P7127 MEMBAR
96721!#7 N11107 P7128 PREFETCH 17 Int BE Pri
96722!#7 N11108 P7129 DWST_BINIT 23 0x3800037 Int BE Pri
96723!#7 N11109 P7130 MEMBAR
96724!#7 N11110 P7131 ST_BINIT 7 0x3800038 Int BE Pri
96725!#7 N11111 P7132 MEMBAR
96726!#7 N11112 P7133 BLD 21 -1 FP BE Pri
96727!#7 N11113 P7133 BLD 22 -1 FP BE Pri
96728!#A N11112 N11113
96729!#7 N11114 P7133 BLD 23 -1 FP BE Pri
96730!#7 N11115 P7134 MEMBAR
96731!#7 N11116 P7135 DWST 9 0x3800039 Int BE Pri
96732!#7 N11117 P7135 DWST 10 0x380003a Int BE Pri
96733!#A N11116 N11117
96734!#7 N11118 P7136 LD 23 -1 Int BE Pri
96735!#7 N11119 P7136 CAS 23 -1 N11118 0x380003b Int BE Pri
96736!#7 N11120 P7137 DWLD 3 -1 Int BE Pri
96737!#7 N11121 P7137 DWLD 4 -1 Int BE Pri
96738!#A N11120 N11121
96739!#7 N11122 P7138 LD 5 -1 Int BE Pri
96740!#7 N11123 P7139 LD 10 -1 Int BE Pri
96741!#7 N11124 P7139 CAS 10 -1 N11123 0x380003c Int BE Pri
96742!#7 N11125 P7140 LD 1 -1 Int BE Pri
96743!#7 N11126 P7140 CAS 1 -1 N11125 0x380003d Int BE Pri
96744!#7 N11127 P7141 DWST_BINIT 6 0x380003e Int BE Pri
96745!#7 N11128 P7141 DWST_BINIT 7 0x380003f Int BE Pri
96746!#A N11127 N11128
96747!#7 N11129 P7142 MEMBAR
96748!#7 N11130 P7143 ST_BINIT 4 0x3800040 Int BE Pri
96749!#7 N11131 P7144 MEMBAR
96750!#7 N11132 P7145 PREFETCH 15 Int BE Pri
96751!#7 N11133 P7146 ST 10 0x3800041 Int BE Pri
96752!#7 N11134 P7147 SWAP 14 0xffffffff 0x3800042 Int BE Pri
96753!#7 N11135 P7148 DWLD 15 -1 Int BE Pri
96754!#7 N11136 P7148 DWLD 16 -1 Int BE Pri
96755!#A N11135 N11136
96756!#7 N11137 P7148 CASX 15 -1 N11135 0x3800043 Int BE Pri
96757!#7 N11138 P7148 CASX 16 -1 N11136 0x3800044 Int BE Pri
96758!#A N11137 N11138
96759!#7 N11139 P7149 LD 22 -1 Int BE Pri
96760!#7 N11140 P7150 MEMBAR
96761!#7 N11141 P7151 BSTC 18 0x4300001f FP BE Pri
96762!#7 N11142 P7151 BSTC 19 0x43000020 FP BE Pri
96763!#A N11141 N11142
96764!#7 N11143 P7151 BSTC 20 0x43000021 FP BE Pri
96765!#7 N11144 P7152 MEMBAR
96766!#7 N11145 P7153 REPLACEMENT 9 Int BE Pri
96767!#7 N11146 P7154 LD 22 -1 Int BE Pri
96768!#7 N11147 P7154 CAS 22 -1 N11146 0x3800045 Int BE Pri
96769!#7 N11148 P7155 MEMBAR
96770!#7 N11149 P7156 BLD 6 -1 FP BE Pri
96771!#7 N11150 P7156 BLD 7 -1 FP BE Pri
96772!#A N11149 N11150
96773!#7 N11151 P7156 BLD 8 -1 FP BE Pri
96774!#7 N11152 P7157 MEMBAR
96775!#7 N11153 P7158 SWAP 22 0xffffffff 0x3800046 Int BE Pri
96776!#7 N11154 P7159 SWAP 16 0xffffffff 0x3800047 Int BE Pri
96777!#7 N11155 P7160 LDD 15 -1 Int BE Pri
96778!#7 N11156 P7160 LDD 16 -1 Int BE Pri
96779!#A N11155 N11156
96780!#7 N11157 P7161 DWLD 3 -1 Int BE Pri
96781!#7 N11158 P7161 DWLD 4 -1 Int BE Pri
96782!#A N11157 N11158
96783!#7 N11159 P7162 LD 5 -1 Int BE Pri
96784!#7 N11160 P7162 CAS 5 -1 N11159 0x3800048 Int BE Pri
96785!#7 N11161 P7163 SWAP 21 0xffffffff 0x3800049 Int BE Pri
96786!#7 N11162 P7164 DWST_BINIT 6 0x380004a Int BE Pri
96787!#7 N11163 P7164 DWST_BINIT 7 0x380004b Int BE Pri
96788!#A N11162 N11163
96789!#7 N11164 P7165 MEMBAR
96790!#7 N11165 P7166 BSTC 12 0x43000022 FP BE Pri
96791!#7 N11166 P7166 BSTC 13 0x43000023 FP BE Pri
96792!#A N11165 N11166
96793!#7 N11167 P7166 BSTC 14 0x43000024 FP BE Pri
96794!#7 N11168 P7167 MEMBAR
96795!#7 N11169 P7168 BSTC 3 0x43000025 FP BE Pri
96796!#7 N11170 P7168 BSTC 4 0x43000026 FP BE Pri
96797!#A N11169 N11170
96798!#7 N11171 P7168 BSTC 5 0x43000027 FP BE Pri
96799!#7 N11172 P7169 MEMBAR
96800!#7 N11173 P7170 DWLD 2 -1 Int BE Pri
96801!#7 N11174 P7171 DWLD 18 -1 Int BE Pri
96802!#7 N11175 P7171 DWLD 19 -1 Int BE Pri
96803!#A N11174 N11175
96804!#7 N11176 P7171 CASX 18 -1 N11174 0x380004c Int BE Pri
96805!#7 N11177 P7171 CASX 19 -1 N11175 0x380004d Int BE Pri
96806!#A N11176 N11177
96807!#7 N11178 P7172 DWLD 12 -1 Int BE Pri
96808!#7 N11179 P7172 DWLD 13 -1 Int BE Pri
96809!#A N11178 N11179
96810!#7 N11180 P7172 CASX 12 -1 N11178 0x380004e Int BE Pri
96811!#7 N11181 P7172 CASX 13 -1 N11179 0x380004f Int BE Pri
96812!#A N11180 N11181
96813!#7 N11182 P7173 LD 18 -1 Int BE Pri
96814!#7 N11183 P7173 CAS 18 -1 N11182 0x3800050 Int BE Pri
96815!#7 N11184 P7174 MEMBAR
96816!#7 N11185 P7175 BST 15 0x43000028 FP BE Pri
96817!#7 N11186 P7175 BST 16 0x43000029 FP BE Pri
96818!#A N11185 N11186
96819!#7 N11187 P7175 BST 17 0x4300002a FP BE Pri
96820!#7 N11188 P7176 MEMBAR
96821!#7 N11189 P7177 REPLACEMENT 9 Int BE Pri
96822!#7 N11190 P7178 MEMBAR
96823!#7 N11191 P7179 BST 12 0x4300002b FP BE Pri
96824!#7 N11192 P7179 BST 13 0x4300002c FP BE Pri
96825!#A N11191 N11192
96826!#7 N11193 P7179 BST 14 0x4300002d FP BE Pri
96827!#7 N11194 P7180 MEMBAR
96828!#7 N11195 P7181 BST 3 0x4300002e FP BE Pri
96829!#7 N11196 P7181 BST 4 0x4300002f FP BE Pri
96830!#A N11195 N11196
96831!#7 N11197 P7181 BST 5 0x43000030 FP BE Pri
96832!#7 N11198 P7182 MEMBAR
96833!#7 N11199 P7183 BSTC 9 0x43000031 FP BE Pri
96834!#7 N11200 P7183 BSTC 10 0x43000032 FP BE Pri
96835!#A N11199 N11200
96836!#7 N11201 P7183 BSTC 11 0x43000033 FP BE Pri
96837!#7 N11202 P7184 MEMBAR
96838!#7 N11203 P7185 LDD 8 -1 Int BE Pri
96839!#7 N11204 P7186 DWST 0 0x3800051 Int BE Pri
96840!#7 N11205 P7186 DWST 1 0x3800052 Int BE Pri
96841!#A N11204 N11205
96842!#7 N11206 P7187 MEMBAR
96843!#7 N11207 P7188 BST 12 0x43000034 FP BE Pri
96844!#7 N11208 P7188 BST 13 0x43000035 FP BE Pri
96845!#A N11207 N11208
96846!#7 N11209 P7188 BST 14 0x43000036 FP BE Pri
96847!#7 N11210 P7189 MEMBAR
96848!#7 N11211 P7190 ST_BINIT 9 0x3800053 Int BE Pri
96849!#7 N11212 P7191 MEMBAR
96850!#7 N11213 P7192 LD 15 -1 Int BE Pri
96851!#7 N11214 P7193 MEMBAR
96852!#7 N11215 P7194 BSTC 3 0x43000037 FP BE Pri
96853!#7 N11216 P7194 BSTC 4 0x43000038 FP BE Pri
96854!#A N11215 N11216
96855!#7 N11217 P7194 BSTC 5 0x43000039 FP BE Pri
96856!#7 N11218 P7195 MEMBAR
96857!#7 N11219 P7196 LD 4 -1 Int BE Pri
96858!#7 N11220 P7197 MEMBAR
96859!#7 N11221 P7198 BST 18 0x4300003a FP BE Pri
96860!#7 N11222 P7198 BST 19 0x4300003b FP BE Pri
96861!#A N11221 N11222
96862!#7 N11223 P7198 BST 20 0x4300003c FP BE Pri
96863!#7 N11224 P7199 MEMBAR
96864!#7 N11225 P7200 LD 3 -1 Int BE Pri
96865!#7 N11226 P7201 MEMBAR
96866!#7 N11227 P7202 BST 6 0x4300003d FP BE Pri
96867!#7 N11228 P7202 BST 7 0x4300003e FP BE Pri
96868!#A N11227 N11228
96869!#7 N11229 P7202 BST 8 0x4300003f FP BE Pri
96870!#7 N11230 P7203 MEMBAR
96871!#7 N11231 P7204 REPLACEMENT 18 Int BE Pri
96872!#7 N11232 P7205 DWST 20 0x3800054 Int BE Pri
96873!#7 N11233 P7206 PREFETCH 18 Int BE Pri
96874!#7 N11234 P7207 MEMBAR
96875!#7 N11235 P7208 BSTC 18 0x43000040 FP BE Pri
96876!#7 N11236 P7208 BSTC 19 0x43000041 FP BE Pri
96877!#A N11235 N11236
96878!#7 N11237 P7208 BSTC 20 0x43000042 FP BE Pri
96879!#7 N11238 P7209 MEMBAR
96880!#7 N11239 P7210 DWST 18 0x3800055 Int BE Pri
96881!#7 N11240 P7210 DWST 19 0x3800056 Int BE Pri
96882!#A N11239 N11240
96883!#7 N11241 P7211 MEMBAR
96884!#7 N11242 P7212 BST 15 0x43000043 FP BE Pri
96885!#7 N11243 P7212 BST 16 0x43000044 FP BE Pri
96886!#A N11242 N11243
96887!#7 N11244 P7212 BST 17 0x43000045 FP BE Pri
96888!#7 N11245 P7213 MEMBAR
96889!#7 N11246 P7214 PREFETCH 8 Int LE Pri
96890!#7 N11247 P7215 LD 19 -1 Int BE Pri
96891!#7 N11248 P7216 LD 19 -1 Int BE Pri
96892!#7 N11249 P7216 CAS 19 -1 N11248 0x3800057 Int BE Pri
96893!#7 N11250 P7217 ST 10 0x3800058 Int BE Pri
96894!#7 N11251 P7218 LD 7 -1 Int BE Pri
96895!#7 N11252 P7218 CAS 7 -1 N11251 0x3800059 Int BE Pri
96896!#7 N11253 P7219 DWLD 6 -1 Int BE Pri
96897!#7 N11254 P7219 DWLD 7 -1 Int BE Pri
96898!#A N11253 N11254
96899!#7 N11255 P7219 CASX 6 -1 N11253 0x380005a Int BE Pri
96900!#7 N11256 P7219 CASX 7 -1 N11254 0x380005b Int BE Pri
96901!#A N11255 N11256
96902!#7 N11257 P7220 ST_BINIT 15 0x380005c Int BE Pri
96903!#7 N11258 P7221 MEMBAR
96904!#7 N11259 P7222 SWAP 4 0xffffffff 0x380005d Int BE Pri
96905!#7 N11260 P7223 LD 18 -1 Int BE Pri
96906!#7 N11261 P7223 CAS 18 -1 N11260 0x380005e Int BE Pri
96907!#7 N11262 P7224 LDD 23 -1 Int BE Pri
96908!#7 N11263 P7225 DWLD 14 -1 Int BE Pri
96909!#7 N11264 P7226 SWAP 10 0xffffffff 0x380005f Int BE Pri
96910!#7 N11265 P7227 SWAP 13 0xffffffff 0x3800060 Int BE Pri
96911!#7 N11266 P7228 MEMBAR
96912!#7 N11267 P7229 BST 3 0x43000046 FP BE Pri
96913!#7 N11268 P7229 BST 4 0x43000047 FP BE Pri
96914!#A N11267 N11268
96915!#7 N11269 P7229 BST 5 0x43000048 FP BE Pri
96916!#7 N11270 P7230 MEMBAR
96917!#7 N11271 P7231 ST 14 0x3800061 Int LE Pri
96918!#7 N11272 P7232 MEMBAR
96919!#7 N11273 P7233 BSTC 3 0x43000049 FP BE Pri
96920!#7 N11274 P7233 BSTC 4 0x4300004a FP BE Pri
96921!#A N11273 N11274
96922!#7 N11275 P7233 BSTC 5 0x4300004b FP BE Pri
96923!#7 N11276 P7234 MEMBAR
96924!#7 N11277 P7235 ST_BINIT 16 0x3800062 Int BE Pri
96925!#7 N11278 P7236 MEMBAR
96926!#7 N11279 P7237 ST 13 0x3800063 Int BE Pri
96927!#7 N11280 P7238 MEMBAR
96928!#7 N11281 P7239 BSTC 9 0x4300004c FP BE Pri
96929!#7 N11282 P7239 BSTC 10 0x4300004d FP BE Pri
96930!#A N11281 N11282
96931!#7 N11283 P7239 BSTC 11 0x4300004e FP BE Pri
96932!#7 N11284 P7240 MEMBAR
96933!#7 N11285 P7241 BST 15 0x4300004f FP BE Pri
96934!#7 N11286 P7241 BST 16 0x43000050 FP BE Pri
96935!#A N11285 N11286
96936!#7 N11287 P7241 BST 17 0x43000051 FP BE Pri
96937!#7 N11288 P7242 MEMBAR
96938!#7 N11289 P7243 DWST_BINIT 9 0x3800064 Int BE Pri
96939!#7 N11290 P7243 DWST_BINIT 10 0x3800065 Int BE Pri
96940!#A N11289 N11290
96941!#7 N11291 P7244 MEMBAR
96942!#7 N11292 P7245 LD 20 -1 Int BE Pri
96943!#7 N11293 P7245 CAS 20 -1 N11292 0x3800066 Int BE Pri
96944!#7 N11294 P7246 PREFETCH 9 Int BE Pri
96945!#7 N11295 P7247 DWLD 18 -1 Int BE Pri
96946!#7 N11296 P7247 DWLD 19 -1 Int BE Pri
96947!#A N11295 N11296
96948!#7 N11297 P7247 CASX 18 -1 N11295 0x3800067 Int BE Pri
96949!#7 N11298 P7247 CASX 19 -1 N11296 0x3800068 Int BE Pri
96950!#A N11297 N11298
96951!#7 N11299 P7248 DWST_BINIT 14 0x3800069 Int LE Pri
96952!#7 N11300 P7249 MEMBAR
96953!#7 N11301 P7250 DWLD 12 -1 Int BE Pri
96954!#7 N11302 P7250 DWLD 13 -1 Int BE Pri
96955!#A N11301 N11302
96956!#7 N11303 P7250 CASX 12 -1 N11301 0x380006a Int BE Pri
96957!#7 N11304 P7250 CASX 13 -1 N11302 0x380006b Int BE Pri
96958!#A N11303 N11304
96959!#7 N11305 P7251 LD 16 -1 Int BE Pri
96960!#7 N11306 P7252 LD 22 -1 Int BE Pri
96961!#7 N11307 P7252 CAS 22 -1 N11306 0x380006c Int BE Pri
96962!#7 N11308 P7253 REPLACEMENT 0 Int BE Pri
96963!#7 N11309 P7254 ST_BINIT 2 0x380006d Int BE Pri
96964!#7 N11310 P7255 MEMBAR
96965!#7 N11311 P7256 LDD 11 -1 Int BE Pri
96966!#7 N11312 P7257 DWLD 15 -1 Int BE Pri
96967!#7 N11313 P7257 DWLD 16 -1 Int BE Pri
96968!#A N11312 N11313
96969!#7 N11314 P7258 PREFETCH 19 Int BE Pri
96970!#7 N11315 P7259 ST 2 0x380006e Int BE Pri
96971!#7 N11316 P7260 DWST 9 0x43000052 FP BE Pri
96972!#7 N11317 P7260 DWST 10 0x43000053 FP BE Pri
96973!#A N11316 N11317
96974!#7 N11318 P7261 MEMBAR
96975!#7 N11319 P7262 BSTC 18 0x43000054 FP BE Pri
96976!#7 N11320 P7262 BSTC 19 0x43000055 FP BE Pri
96977!#A N11319 N11320
96978!#7 N11321 P7262 BSTC 20 0x43000056 FP BE Pri
96979!#7 N11322 P7263 MEMBAR
96980!#7 N11323 P7264 DWLD 6 -1 Int BE Pri
96981!#7 N11324 P7264 DWLD 7 -1 Int BE Pri
96982!#A N11323 N11324
96983!#7 N11325 P7264 CASX 6 -1 N11323 0x380006f Int BE Pri
96984!#7 N11326 P7264 CASX 7 -1 N11324 0x3800070 Int BE Pri
96985!#A N11325 N11326
96986!#7 N11327 P7265 DWST 5 0x3800071 Int BE Pri
96987!#7 N11328 P7266 MEMBAR
96988!#7 N11329 P7267 BSTC 15 0x43000057 FP BE Pri
96989!#7 N11330 P7267 BSTC 16 0x43000058 FP BE Pri
96990!#A N11329 N11330
96991!#7 N11331 P7267 BSTC 17 0x43000059 FP BE Pri
96992!#7 N11332 P7268 MEMBAR
96993!#7 N11333 P7269 LD 12 -1 Int BE Pri
96994!#7 N11334 P7270 DWLD 9 -1 Int BE Pri
96995!#7 N11335 P7270 DWLD 10 -1 Int BE Pri
96996!#A N11334 N11335
96997!#7 N11336 P7271 REPLACEMENT 12 Int BE Pri
96998!#7 N11337 P7272 MEMBAR
96999!#7 N11338 P7273 BLD 15 -1 FP BE Pri
97000!#7 N11339 P7273 BLD 16 -1 FP BE Pri
97001!#A N11338 N11339
97002!#7 N11340 P7273 BLD 17 -1 FP BE Pri
97003!#7 N11341 P7274 MEMBAR
97004!#7 N11342 P7275 LD 16 -1 Int LE Pri
97005!#7 N11343 P7276 DWST 0 0x3800072 Int BE Pri
97006!#7 N11344 P7276 DWST 1 0x3800073 Int BE Pri
97007!#A N11343 N11344
97008!#7 N11345 P7277 DWST_BINIT 5 0x3800074 Int BE Pri
97009!#7 N11346 P7278 MEMBAR
97010!#7 N11347 P7279 DWLD 21 -1 Int BE Pri
97011!#7 N11348 P7279 DWLD 22 -1 Int BE Pri
97012!#A N11347 N11348
97013!#7 N11349 P7280 DWST_BINIT 6 0x3800075 Int BE Pri
97014!#7 N11350 P7280 DWST_BINIT 7 0x3800076 Int BE Pri
97015!#A N11349 N11350
97016!#7 N11351 P7281 MEMBAR
97017!#7 N11352 P7282 DWST_BINIT 21 0x3800077 Int BE Pri
97018!#7 N11353 P7282 DWST_BINIT 22 0x3800078 Int BE Pri
97019!#A N11352 N11353
97020!#7 N11354 P7283 MEMBAR
97021!#7 N11355 P7284 ST_BINIT 9 0x3800079 Int BE Pri
97022!#7 N11356 P7285 MEMBAR
97023!#7 N11357 P7286 DWLD 23 -1,0x0 Int BE Pri
97024!#7 N11358 P7286 CASX 23 -1,0x0 N11357 0x380007a Int BE Pri
97025!#7 N11359 P7287 DWLD 14 -1,0x0 Int BE Pri
97026!#7 N11360 P7287 CASX 14 -1,0x0 N11359 0x380007b Int BE Pri
97027!#7 N11361 P7288 MEMBAR
97028!#7 N11362 P7289 BLD 6 -1 FP BE Pri
97029!#7 N11363 P7289 BLD 7 -1 FP BE Pri
97030!#A N11362 N11363
97031!#7 N11364 P7289 BLD 8 -1 FP BE Pri
97032!#7 N11365 P7290 MEMBAR
97033!#7 N11366 P7291 BSTC 0 0x4300005a FP BE Pri
97034!#7 N11367 P7291 BSTC 1 0x4300005b FP BE Pri
97035!#A N11366 N11367
97036!#7 N11368 P7291 BSTC 2 0x4300005c FP BE Pri
97037!#7 N11369 P7292 MEMBAR
97038!#7 N11370 P7293 LDD 17 -1 Int BE Pri
97039!#7 N11371 P7294 DWLD 14 -1 Int BE Pri
97040!#7 N11372 P7295 DWST 21 0x380007c Int BE Pri
97041!#7 N11373 P7295 DWST 22 0x380007d Int BE Pri
97042!#A N11372 N11373
97043!#7 N11374 P7296 SWAP 22 0xffffffff 0x380007e Int BE Pri
97044!#7 N11375 P7297 SWAP 22 0xffffffff 0x380007f Int BE Pri
97045!#7 N11376 P7298 LD 8 -1 Int BE Pri
97046!#7 N11377 P7298 CAS 8 -1 N11376 0x3800080 Int BE Pri
97047!#7 N11378 P7299 DWLD 5 -1,0x0 Int BE Pri
97048!#7 N11379 P7299 CASX 5 -1,0x0 N11378 0x3800081 Int BE Pri
97049!#7 N11380 P7300 MEMBAR
97050!#7 N11381 P7301 BLD 0 -1 FP BE Pri
97051!#7 N11382 P7301 BLD 1 -1 FP BE Pri
97052!#A N11381 N11382
97053!#7 N11383 P7301 BLD 2 -1 FP BE Pri
97054!#7 N11384 P7302 MEMBAR
97055!#7 N11385 P7303 DWST_BINIT 20 0x3800082 Int LE Pri
97056!#7 N11386 P7304 MEMBAR
97057!#7 N11387 P7305 PREFETCH 10 Int BE Pri
97058!#7 N11388 P7306 ST 13 0x3800083 Int BE Pri
97059!#7 N11389 P7307 MEMBAR
97060!#7 N11390 P7308 BLD 12 -1 FP BE Pri
97061!#7 N11391 P7308 BLD 13 -1 FP BE Pri
97062!#A N11390 N11391
97063!#7 N11392 P7308 BLD 14 -1 FP BE Pri
97064!#7 N11393 P7309 MEMBAR
97065!#7 N11394 P7310 DWST 6 0x3800084 Int BE Pri
97066!#7 N11395 P7310 DWST 7 0x3800085 Int BE Pri
97067!#A N11394 N11395
97068!#7 N11396 P7311 LDD 9 -1 Int BE Pri
97069!#7 N11397 P7311 LDD 10 -1 Int BE Pri
97070!#A N11396 N11397
97071!#7 N11398 P7312 DWLD 12 -1 Int BE Pri
97072!#7 N11399 P7312 DWLD 13 -1 Int BE Pri
97073!#A N11398 N11399
97074!#7 N11400 P7313 LDD 18 -1 Int BE Pri
97075!#7 N11401 P7313 LDD 19 -1 Int BE Pri
97076!#A N11400 N11401
97077!#7 N11402 P7314 LD 19 -1 Int BE Pri
97078!#7 N11403 P7315 ST_BINIT 17 0x3800086 Int BE Pri
97079!#7 N11404 P7316 MEMBAR
97080!#7 N11405 P7317 BLD 0 -1 FP BE Pri
97081!#7 N11406 P7317 BLD 1 -1 FP BE Pri
97082!#A N11405 N11406
97083!#7 N11407 P7317 BLD 2 -1 FP BE Pri
97084!#7 N11408 P7318 MEMBAR
97085!#7 N11409 P7319 REPLACEMENT 14 Int BE Pri
97086!#7 N11410 P7320 DWST_BINIT 6 0x3800087 Int BE Pri
97087!#7 N11411 P7320 DWST_BINIT 7 0x3800088 Int BE Pri
97088!#A N11410 N11411
97089!#7 N11412 P7321 MEMBAR
97090!#7 N11413 P7322 ST 5 0x3800089 Int BE Pri
97091!#7 N11414 P7323 ST 6 0x380008a Int LE Pri
97092!#7 N11415 P7324 LD 5 -1 Int BE Pri
97093!#7 N11416 P7324 CAS 5 -1 N11415 0x380008b Int BE Pri
97094!#7 N11417 P7325 LD 14 -1 Int BE Pri
97095!#7 N11418 P7325 CAS 14 -1 N11417 0x380008c Int BE Pri
97096!#7 N11419 P7326 MEMBAR
97097!#7 N11420 P7327 BLD 15 -1 FP BE Pri
97098!#7 N11421 P7327 BLD 16 -1 FP BE Pri
97099!#A N11420 N11421
97100!#7 N11422 P7327 BLD 17 -1 FP BE Pri
97101!#7 N11423 P7328 MEMBAR
97102!#7 N11424 P7329 REPLACEMENT 9 Int BE Pri
97103!#7 N11425 P7330 MEMBAR
97104!#7 N11426 P7331 BLD 21 -1 FP BE Pri
97105!#7 N11427 P7331 BLD 22 -1 FP BE Pri
97106!#A N11426 N11427
97107!#7 N11428 P7331 BLD 23 -1 FP BE Pri
97108!#7 N11429 P7332 MEMBAR
97109!#7 N11430 P7333 PREFETCH 20 Int BE Pri
97110!#7 N11431 P7334 ST 3 0x380008d Int BE Pri
97111!#7 N11432 P7335 REPLACEMENT 23 Int BE Pri
97112!#7 N11433 P7336 LD 6 -1 Int LE Pri
97113!#7 N11434 P7336 CAS 6 -1 N11433 0x380008e Int LE Pri
97114!#7 N11435 P7337 ST_BINIT 21 0x380008f Int BE Pri
97115!#7 N11436 P7338 MEMBAR
97116!#7 N11437 P7339 ST 15 0x3800090 Int BE Pri
97117!#7 N11438 P7340 MEMBAR
97118!#7 N11439 P7341 BLD 21 -1 FP BE Pri
97119!#7 N11440 P7341 BLD 22 -1 FP BE Pri
97120!#A N11439 N11440
97121!#7 N11441 P7341 BLD 23 -1 FP BE Pri
97122!#7 N11442 P7342 MEMBAR
97123!#7 N11443 P7343 BLD 6 -1 FP BE Pri
97124!#7 N11444 P7343 BLD 7 -1 FP BE Pri
97125!#A N11443 N11444
97126!#7 N11445 P7343 BLD 8 -1 FP BE Pri
97127!#7 N11446 P7344 MEMBAR
97128!#7 N11447 P7345 DWST 21 0x3800091 Int BE Pri
97129!#7 N11448 P7345 DWST 22 0x3800092 Int BE Pri
97130!#A N11447 N11448
97131!#7 N11449 P7346 ST 15 0x3800093 Int BE Pri
97132!#7 N11450 P7347 MEMBAR
97133!#7 N11451 P7348 BSTC 21 0x4300005d FP BE Pri
97134!#7 N11452 P7348 BSTC 22 0x4300005e FP BE Pri
97135!#A N11451 N11452
97136!#7 N11453 P7348 BSTC 23 0x4300005f FP BE Pri
97137!#7 N11454 P7349 MEMBAR
97138!#7 N11455 P7350 PREFETCH 8 Int BE Pri
97139!#7 N11456 P7351 PREFETCH 7 Int BE Pri
97140!#7 N11457 P7352 DWST_BINIT 9 0x3800094 Int BE Pri
97141!#7 N11458 P7352 DWST_BINIT 10 0x3800095 Int BE Pri
97142!#A N11457 N11458
97143!#7 N11459 P7353 MEMBAR
97144!#7 N11460 P7354 LD 9 -1 Int BE Pri
97145!#7 N11461 P7355 LD 0 -1 Int BE Pri
97146!#7 N11462 P7356 DWST 20 0x3800096 Int BE Pri
97147!#7 N11463 P7357 SWAP 7 0xffffffff 0x3800097 Int BE Pri
97148!#7 N11464 P7358 MEMBAR
97149!#7 N11465 P7359 BST 0 0x43000060 FP BE Pri
97150!#7 N11466 P7359 BST 1 0x43000061 FP BE Pri
97151!#A N11465 N11466
97152!#7 N11467 P7359 BST 2 0x43000062 FP BE Pri
97153!#7 N11468 P7360 MEMBAR
97154!#7 N11469 P7361 BSTC 3 0x43000063 FP BE Pri
97155!#7 N11470 P7361 BSTC 4 0x43000064 FP BE Pri
97156!#A N11469 N11470
97157!#7 N11471 P7361 BSTC 5 0x43000065 FP BE Pri
97158!#7 N11472 P7362 MEMBAR
97159!#7 N11473 P7363 PREFETCH 18 Int BE Pri
97160!#7 N11474 P7364 LD 17 -1 Int BE Pri
97161!#7 N11475 P7365 LDD 12 -1 Int BE Pri
97162!#7 N11476 P7365 LDD 13 -1 Int BE Pri
97163!#A N11475 N11476
97164!#7 N11477 P7366 MEMBAR
97165!#7 N11478 P7367 BLD 12 -1 FP BE Pri
97166!#7 N11479 P7367 BLD 13 -1 FP BE Pri
97167!#A N11478 N11479
97168!#7 N11480 P7367 BLD 14 -1 FP BE Pri
97169!#7 N11481 P7368 MEMBAR
97170!#7 N11482 P7369 SWAP 19 0xffffffff 0x3800098 Int BE Pri
97171!#7 N11483 P7370 SWAP 15 0xffffffff 0x3800099 Int BE Pri
97172!#7 N11484 P7371 ST 16 0x380009a Int BE Pri
97173!#7 N11485 P7372 ST 3 0x380009b Int BE Pri
97174!#7 N11486 P7373 ST_BINIT 1 0x380009c Int BE Pri
97175!#7 N11487 P7374 MEMBAR
97176!#7 N11488 P7375 BSTC 21 0x43000066 FP BE Pri
97177!#7 N11489 P7375 BSTC 22 0x43000067 FP BE Pri
97178!#A N11488 N11489
97179!#7 N11490 P7375 BSTC 23 0x43000068 FP BE Pri
97180!#7 N11491 P7376 MEMBAR
97181!#7 N11492 P7377 LD 10 -1 Int BE Pri
97182!#7 N11493 P7377 CAS 10 -1 N11492 0x380009d Int BE Pri
97183!#7 N11494 P7378 MEMBAR
97184!#7 N11495 P7379 BST 21 0x43000069 FP BE Pri
97185!#7 N11496 P7379 BST 22 0x4300006a FP BE Pri
97186!#A N11495 N11496
97187!#7 N11497 P7379 BST 23 0x4300006b FP BE Pri
97188!#7 N11498 P7380 MEMBAR
97189!#7 N11499 P7381 SWAP 21 0xffffffff 0x380009e Int BE Pri
97190!#7 N11500 P7382 MEMBAR
97191!#7 N11501 P7383 BLD 9 -1 FP BE Pri
97192!#7 N11502 P7383 BLD 10 -1 FP BE Pri
97193!#A N11501 N11502
97194!#7 N11503 P7383 BLD 11 -1 FP BE Pri
97195!#7 N11504 P7384 MEMBAR
97196!#7 N11505 P7385 BSTC 9 0x4300006c FP BE Pri
97197!#7 N11506 P7385 BSTC 10 0x4300006d FP BE Pri
97198!#A N11505 N11506
97199!#7 N11507 P7385 BSTC 11 0x4300006e FP BE Pri
97200!#7 N11508 P7386 MEMBAR
97201!#7 N11509 P7387 DWST 8 0x380009f Int BE Pri
97202!#7 N11510 P7388 MEMBAR
97203!#7 N11511 P7389 BST 12 0x4300006f FP BE Pri
97204!#7 N11512 P7389 BST 13 0x43000070 FP BE Pri
97205!#A N11511 N11512
97206!#7 N11513 P7389 BST 14 0x43000071 FP BE Pri
97207!#7 N11514 P7390 MEMBAR
97208!#7 N11515 P7391 DWLD 23 -1 Int BE Pri
97209!#7 N11516 P7392 LDD 3 -1 Int BE Pri
97210!#7 N11517 P7392 LDD 4 -1 Int BE Pri
97211!#A N11516 N11517
97212!#7 N11518 P7393 ST 5 0x38000a0 Int BE Pri
97213!#7 N11519 P7394 DWLD 9 -1 Int BE Pri
97214!#7 N11520 P7394 DWLD 10 -1 Int BE Pri
97215!#A N11519 N11520
97216!#7 N11521 P7395 LD 6 -1 Int BE Pri
97217!#7 N11522 P7396 ST_BINIT 23 0x38000a1 Int BE Pri
97218!#7 N11523 P7397 MEMBAR
97219!#7 N11524 P7398 ST 6 0x38000a2 Int BE Pri
97220!#7 N11525 P7399 DWLD 9 -1 Int BE Pri
97221!#7 N11526 P7399 DWLD 10 -1 Int BE Pri
97222!#A N11525 N11526
97223!#7 N11527 P7399 CASX 9 -1 N11525 0x38000a3 Int BE Pri
97224!#7 N11528 P7399 CASX 10 -1 N11526 0x38000a4 Int BE Pri
97225!#A N11527 N11528
97226!#7 N11529 P7400 DWST 18 0x38000a5 Int BE Pri
97227!#7 N11530 P7400 DWST 19 0x38000a6 Int BE Pri
97228!#A N11529 N11530
97229!#7 N11531 P7401 LD 0 -1 Int BE Pri
97230!#7 N11532 P7401 CAS 0 -1 N11531 0x38000a7 Int BE Pri
97231!#7 N11533 P7402 DWLD 15 -1 Int BE Pri
97232!#7 N11534 P7402 DWLD 16 -1 Int BE Pri
97233!#A N11533 N11534
97234!#7 N11535 P7402 CASX 15 -1 N11533 0x38000a8 Int BE Pri
97235!#7 N11536 P7402 CASX 16 -1 N11534 0x38000a9 Int BE Pri
97236!#A N11535 N11536
97237!#7 N11537 P7403 ST_BINIT 6 0x38000aa Int BE Pri
97238!#7 N11538 P7404 MEMBAR
97239!#7 N11539 P7405 LDD 2 -1 Int BE Pri
97240!#7 N11540 P7406 ST_BINIT 11 0x38000ab Int BE Pri
97241!#7 N11541 P7407 MEMBAR
97242!#7 N11542 P7408 BST 3 0x43000072 FP BE Pri
97243!#7 N11543 P7408 BST 4 0x43000073 FP BE Pri
97244!#A N11542 N11543
97245!#7 N11544 P7408 BST 5 0x43000074 FP BE Pri
97246!#7 N11545 P7409 MEMBAR
97247!#7 N11546 P7410 BST 0 0x43000075 FP BE Pri
97248!#7 N11547 P7410 BST 1 0x43000076 FP BE Pri
97249!#A N11546 N11547
97250!#7 N11548 P7410 BST 2 0x43000077 FP BE Pri
97251!#7 N11549 P7411 MEMBAR
97252!#7 N11550 P7412 DWST 15 0x38000ac Int BE Pri
97253!#7 N11551 P7412 DWST 16 0x38000ad Int BE Pri
97254!#A N11550 N11551
97255!#7 N11552 P7413 PREFETCH 14 Int BE Pri
97256!#7 N11553 P7414 PREFETCH 10 Int LE Pri
97257!#7 N11554 P7415 LD 20 -1 Int BE Pri
97258!#7 N11555 P7415 CAS 20 -1 N11554 0x38000ae Int BE Pri
97259!#7 N11556 P7416 LD 20 -1 Int BE Pri
97260!#7 N11557 P7417 MEMBAR
97261!#7 N11558 P7418 BLD 21 -1 FP BE Pri
97262!#7 N11559 P7418 BLD 22 -1 FP BE Pri
97263!#A N11558 N11559
97264!#7 N11560 P7418 BLD 23 -1 FP BE Pri
97265!#7 N11561 P7419 MEMBAR
97266!#7 N11562 P7420 DWLD 0 -1 Int BE Pri
97267!#7 N11563 P7420 DWLD 1 -1 Int BE Pri
97268!#A N11562 N11563
97269!#7 N11564 P7421 DWLD 5 -1 FP BE Pri
97270!#7 N11565 P7422 DWLD 0 -1 Int BE Pri
97271!#7 N11566 P7422 DWLD 1 -1 Int BE Pri
97272!#A N11565 N11566
97273!#7 N11567 P7423 DWST_BINIT 12 0x38000af Int BE Pri
97274!#7 N11568 P7423 DWST_BINIT 13 0x38000b0 Int BE Pri
97275!#A N11567 N11568
97276!#7 N11569 P7424 MEMBAR
97277!#7 N11570 P7425 LDD 18 -1 Int BE Pri
97278!#7 N11571 P7425 LDD 19 -1 Int BE Pri
97279!#A N11570 N11571
97280!#7 N11572 P7426 LDD 3 -1 Int BE Pri
97281!#7 N11573 P7426 LDD 4 -1 Int BE Pri
97282!#A N11572 N11573
97283!#7 N11574 P7427 SWAP 18 0xffffffff 0x38000b1 Int BE Pri
97284!#7 N11575 P7428 SWAP 7 0xffffffff 0x38000b2 Int BE Pri
97285!#7 N11576 P7429 MEMBAR
97286!#7 N11577 P7430 BLD 3 -1 FP BE Pri
97287!#7 N11578 P7430 BLD 4 -1 FP BE Pri
97288!#A N11577 N11578
97289!#7 N11579 P7430 BLD 5 -1 FP BE Pri
97290!#7 N11580 P7431 MEMBAR
97291!#7 N11581 P7432 BSTC 6 0x43000078 FP BE Pri
97292!#7 N11582 P7432 BSTC 7 0x43000079 FP BE Pri
97293!#A N11581 N11582
97294!#7 N11583 P7432 BSTC 8 0x4300007a FP BE Pri
97295!#7 N11584 P7433 MEMBAR
97296!#7 N11585 P7434 LD 13 -1 Int BE Pri
97297!#7 N11586 P7435 SWAP 9 0xffffffff 0x38000b3 Int BE Pri
97298!#7 N11587 P7436 MEMBAR
97299!#7 N11588 P7437 BSTC 18 0x4300007b FP BE Pri
97300!#7 N11589 P7437 BSTC 19 0x4300007c FP BE Pri
97301!#A N11588 N11589
97302!#7 N11590 P7437 BSTC 20 0x4300007d FP BE Pri
97303!#7 N11591 P7438 MEMBAR
97304!#7 N11592 P7439 LDD 21 -1 Int BE Pri
97305!#7 N11593 P7439 LDD 22 -1 Int BE Pri
97306!#A N11592 N11593
97307!#7 N11594 P7440 LDD 23 -1 Int BE Pri
97308!#7 N11595 P7441 DWLD 20 -1,0x0 Int BE Pri
97309!#7 N11596 P7441 CASX 20 -1,0x0 N11595 0x38000b4 Int BE Pri
97310!#7 N11597 P7442 MEMBAR
97311!#7 N11598 P7443 BSTC 15 0x4300007e FP BE Pri
97312!#7 N11599 P7443 BSTC 16 0x4300007f FP BE Pri
97313!#A N11598 N11599
97314!#7 N11600 P7443 BSTC 17 0x43000080 FP BE Pri
97315!#7 N11601 P7444 MEMBAR
97316!#7 N11602 P7445 PREFETCH 9 Int BE Pri
97317!#7 N11603 P7446 MEMBAR
97318!#7 N11604 P7447 BST 3 0x43000081 FP BE Pri
97319!#7 N11605 P7447 BST 4 0x43000082 FP BE Pri
97320!#A N11604 N11605
97321!#7 N11606 P7447 BST 5 0x43000083 FP BE Pri
97322!#7 N11607 P7448 MEMBAR
97323!#7 N11608 P7449 ST 1 0x38000b5 Int BE Pri
97324!#7 N11609 P7450 LDD 3 -1 Int BE Pri
97325!#7 N11610 P7450 LDD 4 -1 Int BE Pri
97326!#A N11609 N11610
97327!#7 N11611 P7451 LD 21 -1 Int BE Pri
97328!#7 N11612 P7451 CAS 21 -1 N11611 0x38000b6 Int BE Pri
97329!#7 N11613 P7452 SWAP 17 0xffffffff 0x38000b7 Int BE Pri
97330!#7 N11614 P7453 DWST 6 0x38000b8 Int BE Pri
97331!#7 N11615 P7453 DWST 7 0x38000b9 Int BE Pri
97332!#A N11614 N11615
97333!#7 N11616 P7454 LD 10 -1 Int BE Pri
97334!#7 N11617 P7455 REPLACEMENT 20 Int BE Pri
97335!#7 N11618 P7456 PREFETCH 16 Int BE Pri
97336!#7 N11619 P7457 DWLD 20 -1,0x0 Int BE Pri
97337!#7 N11620 P7457 CASX 20 -1,0x0 N11619 0x38000ba Int BE Pri
97338!#7 N11621 P7458 MEMBAR
97339!#7 N11622 P7459 BST 9 0x43000084 FP BE Pri
97340!#7 N11623 P7459 BST 10 0x43000085 FP BE Pri
97341!#A N11622 N11623
97342!#7 N11624 P7459 BST 11 0x43000086 FP BE Pri
97343!#7 N11625 P7460 MEMBAR
97344!#7 N11626 P7461 LDD 15 -1 Int BE Pri
97345!#7 N11627 P7461 LDD 16 -1 Int BE Pri
97346!#A N11626 N11627
97347!#7 N11628 P7462 DWLD 5 -1,0x0 Int BE Pri
97348!#7 N11629 P7462 CASX 5 -1,0x0 N11628 0x38000bb Int BE Pri
97349!#7 N11630 P7463 ST 3 0x38000bc Int BE Pri
97350!#7 N11631 P7464 LD 23 -1 Int BE Pri
97351!#7 N11632 P7465 LDD 9 -1 Int BE Pri
97352!#7 N11633 P7465 LDD 10 -1 Int BE Pri
97353!#A N11632 N11633
97354!#7 N11634 P7466 DWLD 0 -1 Int BE Pri
97355!#7 N11635 P7466 DWLD 1 -1 Int BE Pri
97356!#A N11634 N11635
97357!#7 N11636 P7466 CASX 0 -1 N11634 0x38000bd Int BE Pri
97358!#7 N11637 P7466 CASX 1 -1 N11635 0x38000be Int BE Pri
97359!#A N11636 N11637
97360!#7 N11638 P7467 MEMBAR
97361!#7 N11639 P7468 BSTC 3 0x43000087 FP BE Pri
97362!#7 N11640 P7468 BSTC 4 0x43000088 FP BE Pri
97363!#A N11639 N11640
97364!#7 N11641 P7468 BSTC 5 0x43000089 FP BE Pri
97365!#7 N11642 P7469 MEMBAR
97366!#7 N11643 P7470 LDD 12 -1 Int BE Pri
97367!#7 N11644 P7470 LDD 13 -1 Int BE Pri
97368!#A N11643 N11644
97369!#7 N11645 P7471 LDD 3 -1 Int BE Pri
97370!#7 N11646 P7471 LDD 4 -1 Int BE Pri
97371!#A N11645 N11646
97372!#7 N11647 P7472 LDD 15 -1 Int BE Pri
97373!#7 N11648 P7472 LDD 16 -1 Int BE Pri
97374!#A N11647 N11648
97375!#7 N11649 P7473 SWAP 11 0xffffffff 0x38000bf Int BE Pri
97376!#7 N11650 P7474 LD 21 -1 Int BE Pri
97377!#7 N11651 P7475 REPLACEMENT 16 Int BE Pri
97378!#7 N11652 P7476 LDD 18 -1 Int BE Pri
97379!#7 N11653 P7476 LDD 19 -1 Int BE Pri
97380!#A N11652 N11653
97381!#7 N11654 P7477 ST_BINIT 0 0x38000c0 Int LE Pri
97382!#7 N11655 P7478 MEMBAR
97383!#7 N11656 P7479 ST_BINIT 2 0x38000c1 Int BE Pri
97384!#7 N11657 P7480 MEMBAR
97385!#7 N11658 P7481 PREFETCH 18 Int BE Pri
97386!#7 N11659 P7482 SWAP 22 0xffffffff 0x38000c2 Int BE Pri
97387!#7 N11660 P7483 DWST 23 0x38000c3 Int BE Pri
97388!#7 N11661 P7484 LD 5 -1 Int BE Pri
97389!#7 N11662 P7485 REPLACEMENT 20 Int BE Pri
97390!#7 N11663 P7486 DWLD 21 -1 Int BE Pri
97391!#7 N11664 P7486 DWLD 22 -1 Int BE Pri
97392!#A N11663 N11664
97393!#7 N11665 P7486 CASX 21 -1 N11663 0x38000c4 Int BE Pri
97394!#7 N11666 P7486 CASX 22 -1 N11664 0x38000c5 Int BE Pri
97395!#A N11665 N11666
97396!#7 N11667 P7487 DWLD 5 -1 Int BE Pri
97397!#7 N11668 P7488 LDD 9 -1 Int BE Pri
97398!#7 N11669 P7488 LDD 10 -1 Int BE Pri
97399!#A N11668 N11669
97400!#7 N11670 P7489 LD 1 -1 Int BE Pri
97401!#7 N11671 P7490 DWLD 6 -1 Int BE Pri
97402!#7 N11672 P7490 DWLD 7 -1 Int BE Pri
97403!#A N11671 N11672
97404!#7 N11673 P7491 DWST 12 0x4300008a FP BE Pri
97405!#7 N11674 P7491 DWST 13 0x4300008b FP BE Pri
97406!#A N11673 N11674
97407!#7 N11675 P7492 MEMBAR
97408!#7 N11676 P7493 BST 12 0x4300008c FP BE Pri
97409!#7 N11677 P7493 BST 13 0x4300008d FP BE Pri
97410!#A N11676 N11677
97411!#7 N11678 P7493 BST 14 0x4300008e FP BE Pri
97412!#7 N11679 P7494 MEMBAR
97413!#7 N11680 P7495 DWST 6 0x38000c6 Int BE Pri
97414!#7 N11681 P7495 DWST 7 0x38000c7 Int BE Pri
97415!#A N11680 N11681
97416!#7 N11682 P7496 REPLACEMENT 15 Int BE Pri
97417!#7 N11683 P7497 DWST_BINIT 2 0x38000c8 Int BE Pri
97418!#7 N11684 P7498 MEMBAR
97419!#7 N11685 P7499 LD 15 -1 Int BE Pri
97420!#7 N11686 P7500 SWAP 21 0xffffffff 0x38000c9 Int BE Pri
97421!#7 N11687 P7501 PREFETCH 22 Int BE Pri
97422!#7 N11688 P7502 LDD 15 -1 Int BE Pri
97423!#7 N11689 P7502 LDD 16 -1 Int BE Pri
97424!#A N11688 N11689
97425!#7 N11690 P7503 PREFETCH 21 Int BE Pri
97426!#7 N11691 P7504 SWAP 5 0xffffffff 0x38000ca Int BE Pri
97427!#7 N11692 P7505 MEMBAR
97428!#7 N11693 P7506 BST 18 0x4300008f FP BE Pri
97429!#7 N11694 P7506 BST 19 0x43000090 FP BE Pri
97430!#A N11693 N11694
97431!#7 N11695 P7506 BST 20 0x43000091 FP BE Pri
97432!#7 N11696 P7507 MEMBAR
97433!#7 N11697 P7508 DWST_BINIT 15 0x38000cb Int BE Pri
97434!#7 N11698 P7508 DWST_BINIT 16 0x38000cc Int BE Pri
97435!#A N11697 N11698
97436!#7 N11699 P7509 MEMBAR
97437!#7 N11700 P7510 DWLD 3 -1 FP BE Pri
97438!#7 N11701 P7510 DWLD 4 -1 FP BE Pri
97439!#A N11700 N11701
97440!#7 N11702 P7511 DWST 6 0x38000cd Int BE Pri
97441!#7 N11703 P7511 DWST 7 0x38000ce Int BE Pri
97442!#A N11702 N11703
97443!#7 N11704 P7512 DWST 6 0x38000cf Int BE Pri
97444!#7 N11705 P7512 DWST 7 0x38000d0 Int BE Pri
97445!#A N11704 N11705
97446!#7 N11706 P7513 DWST 21 0x38000d1 Int LE Pri
97447!#7 N11707 P7513 DWST 22 0x38000d2 Int LE Pri
97448!#A N11706 N11707
97449!#7 N11708 P7514 MEMBAR
97450!#7 N11709 P7515 BLD 0 -1 FP BE Pri
97451!#7 N11710 P7515 BLD 1 -1 FP BE Pri
97452!#A N11709 N11710
97453!#7 N11711 P7515 BLD 2 -1 FP BE Pri
97454!#7 N11712 P7516 MEMBAR
97455!#7 N11713 P7517 DWST_BINIT 15 0x38000d3 Int BE Pri
97456!#7 N11714 P7517 DWST_BINIT 16 0x38000d4 Int BE Pri
97457!#A N11713 N11714
97458!#7 N11715 P7518 MEMBAR
97459!#7 N11716 P7519 DWST 15 0x38000d5 Int BE Pri
97460!#7 N11717 P7519 DWST 16 0x38000d6 Int BE Pri
97461!#A N11716 N11717
97462!#7 N11718 P7520 PREFETCH 6 Int BE Pri
97463!#7 N11719 P7521 MEMBAR
97464!#7 N11720 P7522 BST 12 0x43000092 FP BE Pri
97465!#7 N11721 P7522 BST 13 0x43000093 FP BE Pri
97466!#A N11720 N11721
97467!#7 N11722 P7522 BST 14 0x43000094 FP BE Pri
97468!#7 N11723 P7523 MEMBAR
97469!#7 N11724 P7524 ST 11 0x38000d7 Int BE Pri
97470!#7 N11725 P7525 MEMBAR
97471!#7 N11726 P7526 BSTC 12 0x43000095 FP BE Pri
97472!#7 N11727 P7526 BSTC 13 0x43000096 FP BE Pri
97473!#A N11726 N11727
97474!#7 N11728 P7526 BSTC 14 0x43000097 FP BE Pri
97475!#7 N11729 P7527 MEMBAR
97476!#7 N11730 P7528 DWLD 23 -1 Int BE Pri
97477!#7 N11731 P7529 DWLD 14 -1 Int BE Pri
97478!#7 N11732 P7530 DWLD 3 -1 Int BE Pri
97479!#7 N11733 P7530 DWLD 4 -1 Int BE Pri
97480!#A N11732 N11733
97481!#7 N11734 P7530 CASX 3 -1 N11732 0x38000d8 Int BE Pri
97482!#7 N11735 P7530 CASX 4 -1 N11733 0x38000d9 Int BE Pri
97483!#A N11734 N11735
97484!#7 N11736 P7531 LD 20 -1 FP BE Pri
97485!#7 N11737 P7532 DWLD 21 -1 Int BE Pri
97486!#7 N11738 P7532 DWLD 22 -1 Int BE Pri
97487!#A N11737 N11738
97488!#7 N11739 P7533 LD 1 -1 Int BE Pri
97489!#7 N11740 P7533 CAS 1 -1 N11739 0x38000da Int BE Pri
97490!#7 N11741 P7534 REPLACEMENT 5 Int BE Pri
97491!#7 N11742 P7535 SWAP 21 0xffffffff 0x38000db Int BE Pri
97492!#7 N11743 P7536 DWST_BINIT 11 0x38000dc Int BE Pri
97493!#7 N11744 P7537 MEMBAR
97494!#7 N11745 P7538 LD 18 -1 Int BE Pri
97495!#7 N11746 P7538 CAS 18 -1 N11745 0x38000dd Int BE Pri
97496!#7 N11747 P7539 MEMBAR
97497!#7 N11748 P7540 BSTC 21 0x43000098 FP BE Pri
97498!#7 N11749 P7540 BSTC 22 0x43000099 FP BE Pri
97499!#A N11748 N11749
97500!#7 N11750 P7540 BSTC 23 0x4300009a FP BE Pri
97501!#7 N11751 P7541 MEMBAR
97502!#7 N11752 P7542 DWLD 9 -1 Int BE Pri
97503!#7 N11753 P7542 DWLD 10 -1 Int BE Pri
97504!#A N11752 N11753
97505!#7 N11754 P7543 DWLD 11 -1,0x0 Int BE Pri
97506!#7 N11755 P7543 CASX 11 -1,0x0 N11754 0x38000de Int BE Pri
97507!#7 N11756 P7544 MEMBAR
97508!#7 N11757 P7545 BSTC 3 0x4300009b FP BE Pri
97509!#7 N11758 P7545 BSTC 4 0x4300009c FP BE Pri
97510!#A N11757 N11758
97511!#7 N11759 P7545 BSTC 5 0x4300009d FP BE Pri
97512!#7 N11760 P7546 MEMBAR
97513!#7 N11761 P7547 PREFETCH 7 Int BE Pri
97514!#7 N11762 P7548 DWST_BINIT 14 0x38000df Int BE Pri
97515!#7 N11763 P7549 MEMBAR
97516!#7 N11764 P7550 REPLACEMENT 0 Int BE Pri
97517!#7 N11765 P7551 DWLD 17 -1 FP BE Pri
97518!#7 N11766 P7552 LD 23 -1 Int BE Pri
97519!#7 N11767 P7552 CAS 23 -1 N11766 0x38000e0 Int BE Pri
97520!#7 N11768 P7553 PREFETCH 15 Int BE Pri
97521!#7 N11769 P7554 PREFETCH 8 Int BE Pri
97522!#7 N11770 P7555 DWLD 18 -1 Int BE Pri
97523!#7 N11771 P7555 DWLD 19 -1 Int BE Pri
97524!#A N11770 N11771
97525!#7 N11772 P7556 MEMBAR
97526!#7 N11773 P7557 BLD 12 -1 FP BE Pri
97527!#7 N11774 P7557 BLD 13 -1 FP BE Pri
97528!#A N11773 N11774
97529!#7 N11775 P7557 BLD 14 -1 FP BE Pri
97530!#7 N11776 P7558 MEMBAR
97531!#7 N11777 P7559 ST 14 0x38000e1 Int BE Pri
97532!#7 N11778 P7560 DWST 6 0x4300009e FP BE Pri
97533!#7 N11779 P7560 DWST 7 0x4300009f FP BE Pri
97534!#A N11778 N11779
97535!#7 N11780 P7561 SWAP 8 0xffffffff 0x38000e2 Int BE Pri
97536!#7 N11781 P7562 SWAP 15 0xffffffff 0x38000e3 Int BE Pri
97537!#7 N11782 P7563 DWLD 3 -1 Int BE Pri
97538!#7 N11783 P7563 DWLD 4 -1 Int BE Pri
97539!#A N11782 N11783
97540!#7 N11784 P7563 CASX 3 -1 N11782 0x38000e4 Int BE Pri
97541!#7 N11785 P7563 CASX 4 -1 N11783 0x38000e5 Int BE Pri
97542!#A N11784 N11785
97543!#7 N11786 P7564 SWAP 2 0xffffffff 0x38000e6 Int BE Pri
97544!#7 N11787 P7565 MEMBAR
97545!#7 N11788 P7566 BST 3 0x430000a0 FP BE Pri
97546!#7 N11789 P7566 BST 4 0x430000a1 FP BE Pri
97547!#A N11788 N11789
97548!#7 N11790 P7566 BST 5 0x430000a2 FP BE Pri
97549!#7 N11791 P7567 MEMBAR
97550!#7 N11792 P7568 DWLD 12 -1 Int BE Pri
97551!#7 N11793 P7568 DWLD 13 -1 Int BE Pri
97552!#A N11792 N11793
97553!#7 N11794 P7569 MEMBAR
97554!#7 N11795 P7570 BLD 18 -1 FP BE Pri
97555!#7 N11796 P7570 BLD 19 -1 FP BE Pri
97556!#A N11795 N11796
97557!#7 N11797 P7570 BLD 20 -1 FP BE Pri
97558!#7 N11798 P7571 MEMBAR
97559!#7 N11799 P7572 DWST_BINIT 21 0x38000e7 Int BE Pri
97560!#7 N11800 P7572 DWST_BINIT 22 0x38000e8 Int BE Pri
97561!#A N11799 N11800
97562!#7 N11801 P7573 MEMBAR
97563!#7 N11802 P7574 BST 15 0x430000a3 FP BE Pri
97564!#7 N11803 P7574 BST 16 0x430000a4 FP BE Pri
97565!#A N11802 N11803
97566!#7 N11804 P7574 BST 17 0x430000a5 FP BE Pri
97567!#7 N11805 P7575 MEMBAR
97568!#7 N11806 P7576 ST 1 0x38000e9 Int BE Pri
97569!#7 N11807 P7577 LD 1 -1 Int BE Pri
97570!#7 N11808 P7577 CAS 1 -1 N11807 0x38000ea Int BE Pri
97571!#7 N11809 P7578 LDD 3 -1 Int BE Pri
97572!#7 N11810 P7578 LDD 4 -1 Int BE Pri
97573!#A N11809 N11810
97574!#7 N11811 P7579 LDD 3 -1 Int BE Pri
97575!#7 N11812 P7579 LDD 4 -1 Int BE Pri
97576!#A N11811 N11812
97577!#7 N11813 P7580 LD 8 -1 Int BE Pri
97578!#7 N11814 P7581 DWST_BINIT 21 0x38000eb Int BE Pri
97579!#7 N11815 P7581 DWST_BINIT 22 0x38000ec Int BE Pri
97580!#A N11814 N11815
97581!#7 N11816 P7582 MEMBAR
97582!#7 N11817 P7583 REPLACEMENT 11 Int BE Pri
97583!#7 N11818 P7584 LDD 2 -1 Int BE Pri
97584!#7 N11819 P7585 REPLACEMENT 23 Int BE Pri
97585!#7 N11820 P7586 DWST 8 0x38000ed Int BE Pri
97586!#7 N11821 P7587 ST_BINIT 13 0x38000ee Int BE Pri
97587!#7 N11822 P7588 MEMBAR
97588!#7 N11823 P7589 PREFETCH 14 Int BE Pri
97589!#7 N11824 P7590 ST 16 0x38000ef Int BE Pri
97590!#7 N11825 P7591 DWST_BINIT 3 0x38000f0 Int BE Pri
97591!#7 N11826 P7591 DWST_BINIT 4 0x38000f1 Int BE Pri
97592!#A N11825 N11826
97593!#7 N11827 P7592 MEMBAR
97594!#7 N11828 P7593 DWLD 18 -1 Int BE Pri
97595!#7 N11829 P7593 DWLD 19 -1 Int BE Pri
97596!#A N11828 N11829
97597!#7 N11830 P7594 ST_BINIT 2 0x38000f2 Int BE Pri
97598!#7 N11831 P7595 MEMBAR
97599!#7 N11832 P7596 LD 17 -1 Int BE Pri
97600!#7 N11833 P7596 CAS 17 -1 N11832 0x38000f3 Int BE Pri
97601!#7 N11834 P7597 DWLD 6 -1 Int BE Pri
97602!#7 N11835 P7597 DWLD 7 -1 Int BE Pri
97603!#A N11834 N11835
97604!#7 N11836 P7598 LD 21 -1 Int BE Pri
97605!#7 N11837 P7599 REPLACEMENT 0 Int BE Pri
97606!#7 N11838 P7600 ST 10 0x38000f4 Int BE Pri
97607!#7 N11839 P7601 LD 20 -1 Int BE Pri
97608!#7 N11840 P7602 DWST_BINIT 9 0x38000f5 Int BE Pri
97609!#7 N11841 P7602 DWST_BINIT 10 0x38000f6 Int BE Pri
97610!#A N11840 N11841
97611!#7 N11842 P7603 MEMBAR
97612!#7 N11843 P7604 LDD 12 -1 Int LE Pri
97613!#7 N11844 P7604 LDD 13 -1 Int LE Pri
97614!#A N11843 N11844
97615!#7 N11845 P7605 PREFETCH 12 Int BE Pri
97616!#7 N11846 P7606 PREFETCH 7 Int BE Pri
97617!#7 N11847 P7607 MEMBAR
97618!#7 N11848 P7608 BSTC 6 0x430000a6 FP BE Pri
97619!#7 N11849 P7608 BSTC 7 0x430000a7 FP BE Pri
97620!#A N11848 N11849
97621!#7 N11850 P7608 BSTC 8 0x430000a8 FP BE Pri
97622!#7 N11851 P7609 MEMBAR
97623!#7 N11852 P7610 SWAP 21 0xffffffff 0x38000f7 Int BE Pri
97624!#7 N11853 P7611 PREFETCH 22 Int BE Pri
97625!#7 N11854 P7612 SWAP 6 0xffffffff 0x38000f8 Int BE Pri
97626!#7 N11855 P7613 MEMBAR
97627!#7 N11856 P7614 BSTC 21 0x430000a9 FP BE Pri
97628!#7 N11857 P7614 BSTC 22 0x430000aa FP BE Pri
97629!#A N11856 N11857
97630!#7 N11858 P7614 BSTC 23 0x430000ab FP BE Pri
97631!#7 N11859 P7615 MEMBAR
97632!#7 N11860 P7616 DWST 12 0x38000f9 Int BE Pri
97633!#7 N11861 P7616 DWST 13 0x38000fa Int BE Pri
97634!#A N11860 N11861
97635!#7 N11862 P7617 MEMBAR
97636!#7 N11863 P7618 BLD 9 -1 FP BE Pri
97637!#7 N11864 P7618 BLD 10 -1 FP BE Pri
97638!#A N11863 N11864
97639!#7 N11865 P7618 BLD 11 -1 FP BE Pri
97640!#7 N11866 P7619 MEMBAR
97641!#7 N11867 P7620 DWLD 17 -1,0x0 Int BE Pri
97642!#7 N11868 P7620 CASX 17 -1,0x0 N11867 0x38000fb Int BE Pri
97643!#7 N11869 P7621 DWST 11 0x38000fc Int BE Pri
97644!#7 N11870 P7622 ST 17 0x38000fd Int BE Pri
97645!#7 N11871 P7623 MEMBAR
97646!#7 N11872 P7624 BSTC 3 0x430000ac FP BE Pri
97647!#7 N11873 P7624 BSTC 4 0x430000ad FP BE Pri
97648!#A N11872 N11873
97649!#7 N11874 P7624 BSTC 5 0x430000ae FP BE Pri
97650!#7 N11875 P7625 MEMBAR
97651!#7 N11876 P7626 DWLD 9 -1 Int BE Pri
97652!#7 N11877 P7626 DWLD 10 -1 Int BE Pri
97653!#A N11876 N11877
97654!#7 N11878 P7626 CASX 9 -1 N11876 0x38000fe Int BE Pri
97655!#7 N11879 P7626 CASX 10 -1 N11877 0x38000ff Int BE Pri
97656!#A N11878 N11879
97657!#7 N11880 P7627 MEMBAR
97658!#7 N11881 P7628 BSTC 9 0x430000af FP BE Pri
97659!#7 N11882 P7628 BSTC 10 0x430000b0 FP BE Pri
97660!#A N11881 N11882
97661!#7 N11883 P7628 BSTC 11 0x430000b1 FP BE Pri
97662!#7 N11884 P7629 MEMBAR
97663!#7 N11885 P7630 LD 16 -1 Int BE Pri
97664!#7 N11886 P7631 MEMBAR
97665!#7 N11887 P7632 BLD 6 -1 FP BE Pri
97666!#7 N11888 P7632 BLD 7 -1 FP BE Pri
97667!#A N11887 N11888
97668!#7 N11889 P7632 BLD 8 -1 FP BE Pri
97669!#7 N11890 P7633 MEMBAR
97670!#7 N11891 P7634 SWAP 1 0xffffffff 0x3800100 Int BE Pri
97671!#7 N11892 P7635 MEMBAR
97672!#7 N11893 P7636 BSTC 0 0x430000b2 FP BE Pri
97673!#7 N11894 P7636 BSTC 1 0x430000b3 FP BE Pri
97674!#A N11893 N11894
97675!#7 N11895 P7636 BSTC 2 0x430000b4 FP BE Pri
97676!#7 N11896 P7637 MEMBAR
97677!#7 N11897 P7638 DWLD 6 -1 Int BE Pri
97678!#7 N11898 P7638 DWLD 7 -1 Int BE Pri
97679!#A N11897 N11898
97680!#7 N11899 P7639 DWLD 15 -1 Int BE Pri
97681!#7 N11900 P7639 DWLD 16 -1 Int BE Pri
97682!#A N11899 N11900
97683!#7 N11901 P7639 CASX 15 -1 N11899 0x3800101 Int BE Pri
97684!#7 N11902 P7639 CASX 16 -1 N11900 0x3800102 Int BE Pri
97685!#A N11901 N11902
97686!#7 N11903 P7640 DWLD 3 -1 Int BE Pri
97687!#7 N11904 P7640 DWLD 4 -1 Int BE Pri
97688!#A N11903 N11904
97689!#7 N11905 P7640 CASX 3 -1 N11903 0x3800103 Int BE Pri
97690!#7 N11906 P7640 CASX 4 -1 N11904 0x3800104 Int BE Pri
97691!#A N11905 N11906
97692!#7 N11907 P7641 LDD 8 -1 Int BE Pri
97693!#7 N11908 P7642 DWLD 14 -1 Int BE Pri
97694!#7 N11909 P7643 LD 7 -1 Int BE Pri
97695!#7 N11910 P7643 CAS 7 -1 N11909 0x3800105 Int BE Pri
97696!#7 N11911 P7644 SWAP 12 0xffffffff 0x3800106 Int BE Pri
97697!#7 N11912 P7645 REPLACEMENT 11 Int BE Pri
97698!#7 N11913 P7646 SWAP 19 0xffffffff 0x3800107 Int BE Pri
97699!#7 N11914 P7647 LDD 8 -1 Int BE Pri
97700!#7 N11915 P7648 ST 15 0x3800108 Int BE Pri
97701!#7 N11916 P7649 DWLD 21 -1 FP BE Pri
97702!#7 N11917 P7649 DWLD 22 -1 FP BE Pri
97703!#A N11916 N11917
97704!#7 N11918 P7650 PREFETCH 21 Int BE Pri
97705!#7 N11919 P7651 DWST 8 0x3800109 Int BE Pri
97706!#7 N11920 P7652 PREFETCH 21 Int BE Pri
97707!#7 N11921 P7653 MEMBAR
97708!#7 N11922 P7654 BSTC 15 0x430000b5 FP BE Pri
97709!#7 N11923 P7654 BSTC 16 0x430000b6 FP BE Pri
97710!#A N11922 N11923
97711!#7 N11924 P7654 BSTC 17 0x430000b7 FP BE Pri
97712!#7 N11925 P7655 MEMBAR
97713!#7 N11926 P7656 REPLACEMENT 16 Int BE Pri
97714!#7 N11927 P7657 MEMBAR
97715!#7 N11928 P7658 BLD 0 -1 FP BE Pri
97716!#7 N11929 P7658 BLD 1 -1 FP BE Pri
97717!#A N11928 N11929
97718!#7 N11930 P7658 BLD 2 -1 FP BE Pri
97719!#7 N11931 P7659 MEMBAR
97720!#7 N11932 P7660 BSTC 15 0x430000b8 FP BE Pri
97721!#7 N11933 P7660 BSTC 16 0x430000b9 FP BE Pri
97722!#A N11932 N11933
97723!#7 N11934 P7660 BSTC 17 0x430000ba FP BE Pri
97724!#7 N11935 P7661 MEMBAR
97725!#7 N11936 P7662 SWAP 6 0xffffffff 0x380010a Int BE Pri
97726!#7 N11937 P7663 SWAP 5 0xffffffff 0x380010b Int BE Pri
97727!#7 N11938 P7664 DWST 6 0x380010c Int BE Pri
97728!#7 N11939 P7664 DWST 7 0x380010d Int BE Pri
97729!#A N11938 N11939
97730!#7 N11940 P7665 DWST_BINIT 17 0x380010e Int BE Pri
97731!#7 N11941 P7666 MEMBAR
97732!#7 N11942 P7667 LD 23 -1 Int BE Pri
97733!#7 N11943 P7667 CAS 23 -1 N11942 0x380010f Int BE Pri
97734!#7 N11944 P7668 REPLACEMENT 6 Int BE Pri
97735!#7 N11945 P7669 DWST_BINIT 6 0x3800110 Int BE Pri
97736!#7 N11946 P7669 DWST_BINIT 7 0x3800111 Int BE Pri
97737!#A N11945 N11946
97738!#7 N11947 P7670 MEMBAR
97739!#7 N11948 P7671 BLD 0 -1 FP BE Pri
97740!#7 N11949 P7671 BLD 1 -1 FP BE Pri
97741!#A N11948 N11949
97742!#7 N11950 P7671 BLD 2 -1 FP BE Pri
97743!#7 N11951 P7672 MEMBAR
97744!#7 N11952 P7673 DWST_BINIT 23 0x3800112 Int BE Pri
97745!#7 N11953 P7674 MEMBAR
97746!#7 N11954 P7675 LD 21 -1 Int BE Pri
97747!#7 N11955 P7676 DWLD 0 -1 Int BE Pri
97748!#7 N11956 P7676 DWLD 1 -1 Int BE Pri
97749!#A N11955 N11956
97750!#7 N11957 P7677 ST 17 0x3800113 Int BE Pri
97751!#7 N11958 P7678 LD 23 -1 Int BE Pri
97752!#7 N11959 P7678 CAS 23 -1 N11958 0x3800114 Int BE Pri
97753!#7 N11960 P7679 PREFETCH 21 Int BE Pri
97754!#7 N11961 P7680 DWST 21 0x3800115 Int BE Pri
97755!#7 N11962 P7680 DWST 22 0x3800116 Int BE Pri
97756!#A N11961 N11962
97757!#7 N11963 P7681 LDD 6 -1 Int BE Pri
97758!#7 N11964 P7681 LDD 7 -1 Int BE Pri
97759!#A N11963 N11964
97760!#7 N11965 P7682 MEMBAR
97761!#7 N11966 P7683 BSTC 0 0x430000bb FP BE Pri
97762!#7 N11967 P7683 BSTC 1 0x430000bc FP BE Pri
97763!#A N11966 N11967
97764!#7 N11968 P7683 BSTC 2 0x430000bd FP BE Pri
97765!#7 N11969 P7684 MEMBAR
97766!#7 N11970 P7685 DWST 9 0x3800117 Int BE Pri
97767!#7 N11971 P7685 DWST 10 0x3800118 Int BE Pri
97768!#A N11970 N11971
97769!#7 N11972 P7686 PREFETCH 19 Int LE Pri
97770!#7 N11973 P7687 SWAP 3 0xffffffff 0x3800119 Int BE Pri
97771!#7 N11974 P7688 PREFETCH 20 Int BE Pri
97772!#7 N11975 P7689 DWST_BINIT 0 0x380011a Int BE Pri
97773!#7 N11976 P7689 DWST_BINIT 1 0x380011b Int BE Pri
97774!#A N11975 N11976
97775!#7 N11977 P7690 MEMBAR
97776!#7 N11978 P7691 ST_BINIT 7 0x380011c Int BE Pri
97777!#7 N11979 P7692 MEMBAR
97778!#7 N11980 P7693 DWST_BINIT 15 0x380011d Int BE Pri
97779!#7 N11981 P7693 DWST_BINIT 16 0x380011e Int BE Pri
97780!#A N11980 N11981
97781!#7 N11982 P7694 MEMBAR
97782!#7 N11983 P7695 DWST_BINIT 12 0x380011f Int BE Pri
97783!#7 N11984 P7695 DWST_BINIT 13 0x3800120 Int BE Pri
97784!#A N11983 N11984
97785!#7 N11985 P7696 MEMBAR
97786!#7 N11986 P7697 DWLD 21 -1 Int BE Pri
97787!#7 N11987 P7697 DWLD 22 -1 Int BE Pri
97788!#A N11986 N11987
97789!#7 N11988 P7697 CASX 21 -1 N11986 0x3800121 Int BE Pri
97790!#7 N11989 P7697 CASX 22 -1 N11987 0x3800122 Int BE Pri
97791!#A N11988 N11989
97792!#7 N11990 P7698 ST_BINIT 18 0x3800123 Int BE Pri
97793!#7 N11991 P7699 MEMBAR
97794!#7 N11992 P7700 DWST 15 0x3800124 Int BE Pri
97795!#7 N11993 P7700 DWST 16 0x3800125 Int BE Pri
97796!#A N11992 N11993
97797!#7 N11994 P7701 ST 19 0x3800126 Int BE Pri
97798!#7 N11995 P7702 LD 1 -1 Int BE Pri
97799!#7 N11996 P7702 CAS 1 -1 N11995 0x3800127 Int BE Pri
97800!#7 N11997 P7703 MEMBAR
97801!#7 N11998 P7704 BSTC 6 0x430000be FP BE Pri
97802!#7 N11999 P7704 BSTC 7 0x430000bf FP BE Pri
97803!#A N11998 N11999
97804!#7 N12000 P7704 BSTC 8 0x430000c0 FP BE Pri
97805!#7 N12001 P7705 MEMBAR
97806!#7 N12002 P7706 SWAP 6 0xffffffff 0x3800128 Int BE Pri
97807!#7 N12003 P7707 ST 10 0x3800129 Int BE Pri
97808!#7 N12004 P7708 MEMBAR
97809!#7 N12005 P7709 BSTC 9 0x430000c1 FP BE Pri
97810!#7 N12006 P7709 BSTC 10 0x430000c2 FP BE Pri
97811!#A N12005 N12006
97812!#7 N12007 P7709 BSTC 11 0x430000c3 FP BE Pri
97813!#7 N12008 P7710 MEMBAR
97814!#7 N12009 P7711 DWLD 9 -1 Int BE Pri
97815!#7 N12010 P7711 DWLD 10 -1 Int BE Pri
97816!#A N12009 N12010
97817!#7 N12011 P7712 MEMBAR
97818!#7 N12012 P7713 BST 9 0x430000c4 FP BE Pri
97819!#7 N12013 P7713 BST 10 0x430000c5 FP BE Pri
97820!#A N12012 N12013
97821!#7 N12014 P7713 BST 11 0x430000c6 FP BE Pri
97822!#7 N12015 P7714 MEMBAR
97823!#7 N12016 P7715 BLD 21 -1 FP BE Pri
97824!#7 N12017 P7715 BLD 22 -1 FP BE Pri
97825!#A N12016 N12017
97826!#7 N12018 P7715 BLD 23 -1 FP BE Pri
97827!#7 N12019 P7716 MEMBAR
97828!#7 N12020 P7717 SWAP 11 0xffffffff 0x380012a Int BE Pri
97829!#7 N12021 P7718 ST_BINIT 22 0x380012b Int BE Pri
97830!#7 N12022 P7719 MEMBAR
97831!#7 N12023 P7720 BLD 9 -1 FP BE Pri
97832!#7 N12024 P7720 BLD 10 -1 FP BE Pri
97833!#A N12023 N12024
97834!#7 N12025 P7720 BLD 11 -1 FP BE Pri
97835!#7 N12026 P7721 MEMBAR
97836!#7 N12027 P7722 BLD 9 -1 FP BE Pri
97837!#7 N12028 P7722 BLD 10 -1 FP BE Pri
97838!#A N12027 N12028
97839!#7 N12029 P7722 BLD 11 -1 FP BE Pri
97840!#7 N12030 P7723 MEMBAR
97841!#7 N12031 P7724 DWST 18 0x380012c Int BE Pri
97842!#7 N12032 P7724 DWST 19 0x380012d Int BE Pri
97843!#A N12031 N12032
97844!#7 N12033 P7725 DWST_BINIT 12 0x380012e Int LE Pri
97845!#7 N12034 P7725 DWST_BINIT 13 0x380012f Int LE Pri
97846!#A N12033 N12034
97847!#7 N12035 P7726 MEMBAR
97848!#7 N12036 P7727 LDD 21 -1 Int BE Pri
97849!#7 N12037 P7727 LDD 22 -1 Int BE Pri
97850!#A N12036 N12037
97851!#7 N12038 P7728 DWLD 12 -1 Int BE Pri
97852!#7 N12039 P7728 DWLD 13 -1 Int BE Pri
97853!#A N12038 N12039
97854!#7 N12040 P7728 CASX 12 -1 N12038 0x3800130 Int BE Pri
97855!#7 N12041 P7728 CASX 13 -1 N12039 0x3800131 Int BE Pri
97856!#A N12040 N12041
97857!#7 N12042 P7729 MEMBAR
97858!#7 N12043 P7730 BSTC 21 0x430000c7 FP BE Pri
97859!#7 N12044 P7730 BSTC 22 0x430000c8 FP BE Pri
97860!#A N12043 N12044
97861!#7 N12045 P7730 BSTC 23 0x430000c9 FP BE Pri
97862!#7 N12046 P7731 MEMBAR
97863!#7 N12047 P7732 DWLD 9 -1 Int BE Pri
97864!#7 N12048 P7732 DWLD 10 -1 Int BE Pri
97865!#A N12047 N12048
97866!#7 N12049 P7732 CASX 9 -1 N12047 0x3800132 Int BE Pri
97867!#7 N12050 P7732 CASX 10 -1 N12048 0x3800133 Int BE Pri
97868!#A N12049 N12050
97869!#7 N12051 P7733 DWLD 21 -1 Int BE Pri
97870!#7 N12052 P7733 DWLD 22 -1 Int BE Pri
97871!#A N12051 N12052
97872!#7 N12053 P7733 CASX 21 -1 N12051 0x3800134 Int BE Pri
97873!#7 N12054 P7733 CASX 22 -1 N12052 0x3800135 Int BE Pri
97874!#A N12053 N12054
97875!#7 N12055 P7734 SWAP 0 0xffffffff 0x3800136 Int BE Pri
97876!#7 N12056 P7735 MEMBAR
97877!#7 N12057 P7736 BST 21 0x430000ca FP BE Pri
97878!#7 N12058 P7736 BST 22 0x430000cb FP BE Pri
97879!#A N12057 N12058
97880!#7 N12059 P7736 BST 23 0x430000cc FP BE Pri
97881!#7 N12060 P7737 MEMBAR
97882!#7 N12061 P7738 ST 1 0x3800137 Int BE Pri
97883!#7 N12062 P7739 LDD 18 -1 Int BE Pri
97884!#7 N12063 P7739 LDD 19 -1 Int BE Pri
97885!#A N12062 N12063
97886!#7 N12064 P7740 DWST 17 0x3800138 Int BE Pri
97887!#7 N12065 P7741 MEMBAR
97888!#7 N12066 P7742 BST 9 0x430000cd FP BE Pri
97889!#7 N12067 P7742 BST 10 0x430000ce FP BE Pri
97890!#A N12066 N12067
97891!#7 N12068 P7742 BST 11 0x430000cf FP BE Pri
97892!#7 N12069 P7743 MEMBAR
97893!#7 N12070 P7744 LD 14 -1 Int BE Pri
97894!#7 N12071 P7745 SWAP 13 0xffffffff 0x3800139 Int BE Pri
97895!#7 N12072 P7746 LD 7 -1 Int BE Pri
97896!#7 N12073 P7746 CAS 7 -1 N12072 0x380013a Int BE Pri
97897!#7 N12074 P7747 DWST 20 0x380013b Int BE Pri
97898!#7 N12075 P7748 DWLD 6 -1 Int BE Pri
97899!#7 N12076 P7748 DWLD 7 -1 Int BE Pri
97900!#A N12075 N12076
97901!#7 N12077 P7748 CASX 6 -1 N12075 0x380013c Int BE Pri
97902!#7 N12078 P7748 CASX 7 -1 N12076 0x380013d Int BE Pri
97903!#A N12077 N12078
97904!#7 N12079 P7749 PREFETCH 3 Int BE Pri
97905!#7 N12080 P7750 DWST_BINIT 23 0x380013e Int BE Pri
97906!#7 N12081 P7751 MEMBAR
97907!#7 N12082 P7752 BSTC 9 0x430000d0 FP BE Pri
97908!#7 N12083 P7752 BSTC 10 0x430000d1 FP BE Pri
97909!#A N12082 N12083
97910!#7 N12084 P7752 BSTC 11 0x430000d2 FP BE Pri
97911!#7 N12085 P7753 MEMBAR
97912!#7 N12086 P7754 DWLD 20 -1,0x0 Int BE Pri
97913!#7 N12087 P7754 CASX 20 -1,0x0 N12086 0x380013f Int BE Pri
97914!#7 N12088 P7755 LD 12 -1 Int BE Pri
97915!#7 N12089 P7755 CAS 12 -1 N12088 0x3800140 Int BE Pri
97916!#7 N12090 P7756 SWAP 17 0xffffffff 0x3800141 Int BE Pri
97917!#7 N12091 P7757 MEMBAR
97918!#7 N12092 P7758 BLD 3 -1 FP BE Pri
97919!#7 N12093 P7758 BLD 4 -1 FP BE Pri
97920!#A N12092 N12093
97921!#7 N12094 P7758 BLD 5 -1 FP BE Pri
97922!#7 N12095 P7759 MEMBAR
97923!#7 N12096 P7760 LD 12 -1 Int BE Pri
97924!#7 N12097 P7761 DWLD 5 -1 Int BE Pri
97925!#7 N12098 P7762 ST 9 0x3800142 Int BE Pri
97926!#7 N12099 P7763 ST 13 0x3800143 Int BE Pri
97927!#7 N12100 P7764 DWST 8 0x3800144 Int BE Pri
97928!#7 N12101 P7765 REPLACEMENT 11 Int BE Pri
97929!#7 N12102 P7766 PREFETCH 12 Int BE Pri
97930!#7 N12103 P7767 DWLD 3 -1 Int BE Pri
97931!#7 N12104 P7767 DWLD 4 -1 Int BE Pri
97932!#A N12103 N12104
97933!#7 N12105 P7767 CASX 3 -1 N12103 0x3800145 Int BE Pri
97934!#7 N12106 P7767 CASX 4 -1 N12104 0x3800146 Int BE Pri
97935!#A N12105 N12106
97936!#7 N12107 P7768 MEMBAR
97937!#7 N12108 P7769 BSTC 9 0x430000d3 FP BE Pri
97938!#7 N12109 P7769 BSTC 10 0x430000d4 FP BE Pri
97939!#A N12108 N12109
97940!#7 N12110 P7769 BSTC 11 0x430000d5 FP BE Pri
97941!#7 N12111 P7770 MEMBAR
97942!#7 N12112 P7771 ST_BINIT 6 0x3800147 Int BE Pri
97943!#7 N12113 P7772 MEMBAR
97944!#7 N12114 P7773 LD 9 -1 Int BE Pri
97945!#7 N12115 P7774 LD 4 -1 Int BE Pri
97946!#7 N12116 P7775 PREFETCH 14 Int BE Pri
97947!#7 N12117 P7776 LD 6 -1 Int BE Pri
97948!#7 N12118 P7776 CAS 6 -1 N12117 0x3800148 Int BE Pri
97949!#7 N12119 P7777 MEMBAR
97950!#7 N12120 P7778 BST 3 0x430000d6 FP BE Pri
97951!#7 N12121 P7778 BST 4 0x430000d7 FP BE Pri
97952!#A N12120 N12121
97953!#7 N12122 P7778 BST 5 0x430000d8 FP BE Pri
97954!#7 N12123 P7779 MEMBAR
97955!#7 N12124 P7780 LDD 21 -1 Int BE Pri
97956!#7 N12125 P7780 LDD 22 -1 Int BE Pri
97957!#A N12124 N12125
97958!#7 N12126 P7781 MEMBAR
97959!#7 N12127 P7782 BLD 0 -1 FP BE Pri
97960!#7 N12128 P7782 BLD 1 -1 FP BE Pri
97961!#A N12127 N12128
97962!#7 N12129 P7782 BLD 2 -1 FP BE Pri
97963!#7 N12130 P7783 MEMBAR
97964!#7 N12131 P7784 LD 21 -1 Int BE Pri
97965!#7 N12132 P7784 CAS 21 -1 N12131 0x3800149 Int BE Pri
97966!#7 N12133 P7785 DWST_BINIT 5 0x380014a Int BE Pri
97967!#7 N12134 P7786 MEMBAR
97968!#7 N12135 P7787 LD 22 -1 Int BE Pri
97969!#7 N12136 P7788 SWAP 21 0xffffffff 0x380014b Int BE Pri
97970!#7 N12137 P7789 MEMBAR
97971!#7 N12138 P7790 BST 9 0x430000d9 FP BE Pri
97972!#7 N12139 P7790 BST 10 0x430000da FP BE Pri
97973!#A N12138 N12139
97974!#7 N12140 P7790 BST 11 0x430000db FP BE Pri
97975!#7 N12141 P7791 MEMBAR
97976!#7 N12142 P7792 DWST_BINIT 9 0x380014c Int BE Pri
97977!#7 N12143 P7792 DWST_BINIT 10 0x380014d Int BE Pri
97978!#A N12142 N12143
97979!#7 N12144 P7793 MEMBAR
97980!#7 N12145 P7794 DWLD 14 -1,0x0 Int BE Pri
97981!#7 N12146 P7794 CASX 14 -1,0x0 N12145 0x380014e Int BE Pri
97982!#7 N12147 P7795 MEMBAR
97983!#7 N12148 P7796 BLD 21 -1 FP BE Pri
97984!#7 N12149 P7796 BLD 22 -1 FP BE Pri
97985!#A N12148 N12149
97986!#7 N12150 P7796 BLD 23 -1 FP BE Pri
97987!#7 N12151 P7797 MEMBAR
97988!#7 N12152 P7798 PREFETCH 22 Int BE Pri
97989!#7 N12153 P7799 MEMBAR
97990!#7 N12154 P7800 BSTC 21 0x430000dc FP BE Pri
97991!#7 N12155 P7800 BSTC 22 0x430000dd FP BE Pri
97992!#A N12154 N12155
97993!#7 N12156 P7800 BSTC 23 0x430000de FP BE Pri
97994!#7 N12157 P7801 MEMBAR
97995!#7 N12158 P7802 PREFETCH 4 Int BE Pri
97996!#7 N12159 P7803 MEMBAR
97997!#7 N12160 P7804 BSTC 3 0x430000df FP BE Pri
97998!#7 N12161 P7804 BSTC 4 0x430000e0 FP BE Pri
97999!#A N12160 N12161
98000!#7 N12162 P7804 BSTC 5 0x430000e1 FP BE Pri
98001!#7 N12163 P7805 MEMBAR
98002!#7 N12164 P7806 ST_BINIT 19 0x380014f Int LE Pri
98003!#7 N12165 P7807 MEMBAR
98004!#7 N12166 P7808 SWAP 5 0xffffffff 0x3800150 Int BE Pri
98005!#7 N12167 P7809 MEMBAR
98006!#7 N12168 P7810 BST 21 0x430000e2 FP BE Pri
98007!#7 N12169 P7810 BST 22 0x430000e3 FP BE Pri
98008!#A N12168 N12169
98009!#7 N12170 P7810 BST 23 0x430000e4 FP BE Pri
98010!#7 N12171 P7811 MEMBAR
98011!#7 N12172 P7812 LD 22 -1 Int BE Pri
98012!#7 N12173 P7813 SWAP 14 0xffffffff 0x3800151 Int BE Pri
98013!#7 N12174 P7814 MEMBAR
98014!#7 N12175 P7815 BST 21 0x430000e5 FP BE Pri
98015!#7 N12176 P7815 BST 22 0x430000e6 FP BE Pri
98016!#A N12175 N12176
98017!#7 N12177 P7815 BST 23 0x430000e7 FP BE Pri
98018!#7 N12178 P7816 MEMBAR
98019!#7 N12179 P7817 LDD 9 -1 Int BE Pri
98020!#7 N12180 P7817 LDD 10 -1 Int BE Pri
98021!#A N12179 N12180
98022!#7 N12181 P7818 DWLD 15 -1 Int BE Pri
98023!#7 N12182 P7818 DWLD 16 -1 Int BE Pri
98024!#A N12181 N12182
98025!#7 N12183 P7818 CASX 15 -1 N12181 0x3800152 Int BE Pri
98026!#7 N12184 P7818 CASX 16 -1 N12182 0x3800153 Int BE Pri
98027!#A N12183 N12184
98028!#7 N12185 P7819 MEMBAR
98029!#7 N12186 P7820 BST 6 0x430000e8 FP BE Pri
98030!#7 N12187 P7820 BST 7 0x430000e9 FP BE Pri
98031!#A N12186 N12187
98032!#7 N12188 P7820 BST 8 0x430000ea FP BE Pri
98033!#7 N12189 P7821 MEMBAR
98034!#7 N12190 P7822 REPLACEMENT 10 Int BE Pri
98035!#7 N12191 P7823 SWAP 10 0xffffffff 0x3800154 Int BE Pri
98036!#7 N12192 P7824 MEMBAR
98037!#7 N12193 P7825 BSTC 6 0x430000eb FP BE Pri
98038!#7 N12194 P7825 BSTC 7 0x430000ec FP BE Pri
98039!#A N12193 N12194
98040!#7 N12195 P7825 BSTC 8 0x430000ed FP BE Pri
98041!#7 N12196 P7826 MEMBAR
98042!#7 N12197 P7827 BST 18 0x430000ee FP BE Pri
98043!#7 N12198 P7827 BST 19 0x430000ef FP BE Pri
98044!#A N12197 N12198
98045!#7 N12199 P7827 BST 20 0x430000f0 FP BE Pri
98046!#7 N12200 P7828 MEMBAR
98047!#7 N12201 P7829 DWST_BINIT 9 0x3800155 Int BE Pri
98048!#7 N12202 P7829 DWST_BINIT 10 0x3800156 Int BE Pri
98049!#A N12201 N12202
98050!#7 N12203 P7830 MEMBAR
98051!#7 N12204 P7831 SWAP 13 0xffffffff 0x3800157 Int LE Pri
98052!#7 N12205 P7832 DWLD 3 -1 Int BE Pri
98053!#7 N12206 P7832 DWLD 4 -1 Int BE Pri
98054!#A N12205 N12206
98055!#7 N12207 P7832 CASX 3 -1 N12205 0x3800158 Int BE Pri
98056!#7 N12208 P7832 CASX 4 -1 N12206 0x3800159 Int BE Pri
98057!#A N12207 N12208
98058!#7 N12209 P7833 DWLD 17 -1 FP BE Pri
98059!#7 N12210 P7834 PREFETCH 10 Int BE Pri
98060!#7 N12211 P7835 PREFETCH 5 Int LE Pri
98061!#7 N12212 P7836 DWLD 2 -1 Int BE Pri
98062!#7 N12213 P7837 MEMBAR
98063!#7 N12214 P7838 BSTC 18 0x430000f1 FP BE Pri
98064!#7 N12215 P7838 BSTC 19 0x430000f2 FP BE Pri
98065!#A N12214 N12215
98066!#7 N12216 P7838 BSTC 20 0x430000f3 FP BE Pri
98067!#7 N12217 P7839 MEMBAR
98068!#7 N12218 P7840 DWST 18 0x430000f4 FP BE Pri
98069!#7 N12219 P7840 DWST 19 0x430000f5 FP BE Pri
98070!#A N12218 N12219
98071!#7 N12220 P7841 DWST_BINIT 20 0x380015a Int BE Pri
98072!#7 N12221 P7842 MEMBAR
98073!#7 N12222 P7843 DWST_BINIT 18 0x380015b Int BE Pri
98074!#7 N12223 P7843 DWST_BINIT 19 0x380015c Int BE Pri
98075!#A N12222 N12223
98076!#7 N12224 P7844 MEMBAR
98077!#7 N12225 P7845 SWAP 9 0xffffffff 0x380015d Int BE Pri
98078!#7 N12226 P7846 MEMBAR
98079!#7 N12227 P7847 BST 15 0x430000f6 FP BE Pri
98080!#7 N12228 P7847 BST 16 0x430000f7 FP BE Pri
98081!#A N12227 N12228
98082!#7 N12229 P7847 BST 17 0x430000f8 FP BE Pri
98083!#7 N12230 P7848 MEMBAR
98084!#7 N12231 P7849 LD 11 -1 Int BE Pri
98085!#7 N12232 P7850 MEMBAR
98086!#7 N12233 P7851 BST 9 0x430000f9 FP BE Pri
98087!#7 N12234 P7851 BST 10 0x430000fa FP BE Pri
98088!#A N12233 N12234
98089!#7 N12235 P7851 BST 11 0x430000fb FP BE Pri
98090!#7 N12236 P7852 MEMBAR
98091!#7 N12237 P7853 DWLD 2 -1,0x0 Int BE Pri
98092!#7 N12238 P7853 CASX 2 -1,0x0 N12237 0x380015e Int BE Pri
98093!#7 N12239 P7854 PREFETCH 6 Int BE Pri
98094!#7 N12240 P7855 PREFETCH 7 Int BE Pri
98095!#7 N12241 P7856 MEMBAR
98096!#7 N12242 P7857 BSTC 6 0x430000fc FP BE Pri
98097!#7 N12243 P7857 BSTC 7 0x430000fd FP BE Pri
98098!#A N12242 N12243
98099!#7 N12244 P7857 BSTC 8 0x430000fe FP BE Pri
98100!#7 N12245 P7858 MEMBAR
98101!#7 N12246 P7859 LD 5 -1 Int BE Pri
98102!#7 N12247 P7859 CAS 5 -1 N12246 0x380015f Int BE Pri
98103!#7 N12248 P7860 LD 9 -1 Int BE Pri
98104!#7 N12249 P7860 CAS 9 -1 N12248 0x3800160 Int BE Pri
98105!#7 N12250 P7861 SWAP 18 0xffffffff 0x3800161 Int BE Pri
98106!#7 N12251 P7862 DWLD 0 -1 Int BE Pri
98107!#7 N12252 P7862 DWLD 1 -1 Int BE Pri
98108!#A N12251 N12252
98109!#7 N12253 P7863 ST 5 0x3800162 Int BE Pri
98110!#7 N12254 P7864 DWST_BINIT 15 0x3800163 Int BE Pri
98111!#7 N12255 P7864 DWST_BINIT 16 0x3800164 Int BE Pri
98112!#A N12254 N12255
98113!#7 N12256 P7865 MEMBAR
98114!#7 N12257 P7866 DWLD 3 -1 Int BE Pri
98115!#7 N12258 P7866 DWLD 4 -1 Int BE Pri
98116!#A N12257 N12258
98117!#7 N12259 P7867 MEMBAR
98118!#7 N12260 P7868 BST 21 0x430000ff FP BE Pri
98119!#7 N12261 P7868 BST 22 0x43000100 FP BE Pri
98120!#A N12260 N12261
98121!#7 N12262 P7868 BST 23 0x43000101 FP BE Pri
98122!#7 N12263 P7869 MEMBAR
98123!#7 N12264 P7870 DWST 11 0x3800165 Int BE Pri
98124!#7 N12265 P7871 DWLD 14 -1,0x0 Int BE Pri
98125!#7 N12266 P7871 CASX 14 -1,0x0 N12265 0x3800166 Int BE Pri
98126!#7 N12267 P7872 LD 21 -1 Int BE Pri
98127!#7 N12268 P7873 DWST_BINIT 6 0x3800167 Int BE Pri
98128!#7 N12269 P7873 DWST_BINIT 7 0x3800168 Int BE Pri
98129!#A N12268 N12269
98130!#7 N12270 P7874 MEMBAR
98131!#7 N12271 P7875 BST 3 0x43000102 FP BE Pri
98132!#7 N12272 P7875 BST 4 0x43000103 FP BE Pri
98133!#A N12271 N12272
98134!#7 N12273 P7875 BST 5 0x43000104 FP BE Pri
98135!#7 N12274 P7876 MEMBAR
98136!#7 N12275 P7877 ST_BINIT 7 0x3800169 Int BE Pri
98137!#7 N12276 P7878 MEMBAR
98138!#7 N12277 P7879 LDD 20 -1 Int BE Pri
98139!#7 N12278 P7880 DWST_BINIT 18 0x380016a Int BE Pri
98140!#7 N12279 P7880 DWST_BINIT 19 0x380016b Int BE Pri
98141!#A N12278 N12279
98142!#7 N12280 P7881 MEMBAR
98143!#7 N12281 P7882 DWLD 3 -1 Int BE Pri
98144!#7 N12282 P7882 DWLD 4 -1 Int BE Pri
98145!#A N12281 N12282
98146!#7 N12283 P7883 REPLACEMENT 9 Int BE Pri
98147!#7 N12284 P7884 LDD 6 -1 Int BE Pri
98148!#7 N12285 P7884 LDD 7 -1 Int BE Pri
98149!#A N12284 N12285
98150!#7 N12286 P7885 PREFETCH 18 Int BE Pri
98151!#7 N12287 P7886 SWAP 22 0xffffffff 0x380016c Int BE Pri
98152!#7 N12288 P7887 DWST 0 0x380016d Int BE Pri
98153!#7 N12289 P7887 DWST 1 0x380016e Int BE Pri
98154!#A N12288 N12289
98155!#7 N12290 P7888 DWST 3 0x43000105 FP BE Pri
98156!#7 N12291 P7888 DWST 4 0x43000106 FP BE Pri
98157!#A N12290 N12291
98158!#7 N12292 P7889 DWLD 6 -1 Int BE Pri
98159!#7 N12293 P7889 DWLD 7 -1 Int BE Pri
98160!#A N12292 N12293
98161!#7 N12294 P7889 CASX 6 -1 N12292 0x380016f Int BE Pri
98162!#7 N12295 P7889 CASX 7 -1 N12293 0x3800170 Int BE Pri
98163!#A N12294 N12295
98164!#7 N12296 P7890 MEMBAR
98165!#7 N12297 P7891 BST 3 0x43000107 FP BE Pri
98166!#7 N12298 P7891 BST 4 0x43000108 FP BE Pri
98167!#A N12297 N12298
98168!#7 N12299 P7891 BST 5 0x43000109 FP BE Pri
98169!#7 N12300 P7892 MEMBAR
98170!#7 N12301 P7893 ST 4 0x3800171 Int LE Pri
98171!#7 N12302 P7894 ST 15 0x3800172 Int BE Pri
98172!#7 N12303 P7895 MEMBAR
98173!#7 N12304 P7896 BLD 3 -1 FP BE Pri
98174!#7 N12305 P7896 BLD 4 -1 FP BE Pri
98175!#A N12304 N12305
98176!#7 N12306 P7896 BLD 5 -1 FP BE Pri
98177!#7 N12307 P7897 MEMBAR
98178!#7 N12308 P7898 DWST 18 0x3800173 Int BE Pri
98179!#7 N12309 P7898 DWST 19 0x3800174 Int BE Pri
98180!#A N12308 N12309
98181!#7 N12310 P7899 REPLACEMENT 16 Int BE Pri
98182!#7 N12311 P7900 ST_BINIT 19 0x3800175 Int BE Pri
98183!#7 N12312 P7901 MEMBAR
98184!#7 N12313 P7902 LD 18 -1 Int BE Pri
98185!#7 N12314 P7903 DWLD 8 -1,0x0 Int BE Pri
98186!#7 N12315 P7903 CASX 8 -1,0x0 N12314 0x3800176 Int BE Pri
98187!#7 N12316 P7904 DWLD 18 -1 Int BE Pri
98188!#7 N12317 P7904 DWLD 19 -1 Int BE Pri
98189!#A N12316 N12317
98190!#7 N12318 P7904 CASX 18 -1 N12316 0x3800177 Int BE Pri
98191!#7 N12319 P7904 CASX 19 -1 N12317 0x3800178 Int BE Pri
98192!#A N12318 N12319
98193!#7 N12320 P7905 DWLD 21 -1 Int BE Pri
98194!#7 N12321 P7905 DWLD 22 -1 Int BE Pri
98195!#A N12320 N12321
98196!#7 N12322 P7906 LDD 6 -1 Int BE Pri
98197!#7 N12323 P7906 LDD 7 -1 Int BE Pri
98198!#A N12322 N12323
98199!#7 N12324 P7907 LDD 15 -1 Int BE Pri
98200!#7 N12325 P7907 LDD 16 -1 Int BE Pri
98201!#A N12324 N12325
98202!#7 N12326 P7908 REPLACEMENT 16 Int BE Pri
98203!#7 N12327 P7909 DWLD 2 -1,0x0 Int BE Pri
98204!#7 N12328 P7909 CASX 2 -1,0x0 N12327 0x3800179 Int BE Pri
98205!#7 N12329 P7910 ST 2 0x380017a Int BE Pri
98206!#7 N12330 P7911 MEMBAR
98207!#7 N12331 P7912 BST 6 0x4300010a FP BE Pri
98208!#7 N12332 P7912 BST 7 0x4300010b FP BE Pri
98209!#A N12331 N12332
98210!#7 N12333 P7912 BST 8 0x4300010c FP BE Pri
98211!#7 N12334 P7913 MEMBAR
98212!#7 N12335 P7914 BST 12 0x4300010d FP BE Pri
98213!#7 N12336 P7914 BST 13 0x4300010e FP BE Pri
98214!#A N12335 N12336
98215!#7 N12337 P7914 BST 14 0x4300010f FP BE Pri
98216!#7 N12338 P7915 MEMBAR
98217!#7 N12339 P7916 ST 7 0x380017b Int BE Pri
98218!#7 N12340 P7917 DWST_BINIT 17 0x380017c Int BE Pri
98219!#7 N12341 P7918 MEMBAR
98220!#7 N12342 P7919 DWLD 15 -1 FP BE Pri
98221!#7 N12343 P7919 DWLD 16 -1 FP BE Pri
98222!#A N12342 N12343
98223!#7 N12344 P7920 SWAP 1 0xffffffff 0x380017d Int BE Pri
98224!#7 N12345 P7921 MEMBAR
98225!#7 N12346 P7922 BLD 6 -1 FP BE Pri
98226!#7 N12347 P7922 BLD 7 -1 FP BE Pri
98227!#A N12346 N12347
98228!#7 N12348 P7922 BLD 8 -1 FP BE Pri
98229!#7 N12349 P7923 MEMBAR
98230!#7 N12350 P7924 LD 17 -1 Int BE Pri
98231!#7 N12351 P7925 DWLD 15 -1 Int BE Pri
98232!#7 N12352 P7925 DWLD 16 -1 Int BE Pri
98233!#A N12351 N12352
98234!#7 N12353 P7926 DWLD 21 -1 Int BE Pri
98235!#7 N12354 P7926 DWLD 22 -1 Int BE Pri
98236!#A N12353 N12354
98237!#7 N12355 P7926 CASX 21 -1 N12353 0x380017e Int BE Pri
98238!#7 N12356 P7926 CASX 22 -1 N12354 0x380017f Int BE Pri
98239!#A N12355 N12356
98240!#7 N12357 P7927 LDD 0 -1 Int BE Pri
98241!#7 N12358 P7927 LDD 1 -1 Int BE Pri
98242!#A N12357 N12358
98243!#7 N12359 P7928 DWST 15 0x43000110 FP BE Pri
98244!#7 N12360 P7928 DWST 16 0x43000111 FP BE Pri
98245!#A N12359 N12360
98246!#7 N12361 P7929 LDD 20 -1 Int BE Pri
98247!#7 N12362 P7930 ST 20 0x3800180 Int BE Pri
98248!#7 N12363 P7931 DWST_BINIT 18 0x3800181 Int BE Pri
98249!#7 N12364 P7931 DWST_BINIT 19 0x3800182 Int BE Pri
98250!#A N12363 N12364
98251!#7 N12365 P7932 MEMBAR
98252!#7 N12366 P7933 DWST_BINIT 14 0x3800183 Int BE Pri
98253!#7 N12367 P7934 MEMBAR
98254!#7 N12368 P7935 REPLACEMENT 23 Int BE Pri
98255!#7 N12369 P7936 SWAP 0 0xffffffff 0x3800184 Int BE Pri
98256!#7 N12370 P7937 DWLD 11 -1,0x0 Int BE Pri
98257!#7 N12371 P7937 CASX 11 -1,0x0 N12370 0x3800185 Int BE Pri
98258!#7 N12372 P7938 ST_BINIT 8 0x3800186 Int BE Pri
98259!#7 N12373 P7939 MEMBAR
98260!#7 N12374 P7940 BST 3 0x43000112 FP BE Pri
98261!#7 N12375 P7940 BST 4 0x43000113 FP BE Pri
98262!#A N12374 N12375
98263!#7 N12376 P7940 BST 5 0x43000114 FP BE Pri
98264!#7 N12377 P7941 MEMBAR
98265!#7 N12378 P7942 DWLD 17 -1 Int BE Pri
98266!#7 N12379 P7943 LD 3 -1 Int BE Pri
98267!#7 N12380 P7943 CAS 3 -1 N12379 0x3800187 Int BE Pri
98268!#7 N12381 P7944 SWAP 4 0xffffffff 0x3800188 Int BE Pri
98269!#7 N12382 P7945 DWST_BINIT 14 0x3800189 Int BE Pri
98270!#7 N12383 P7946 MEMBAR
98271!#7 N12384 P7947 BLD 18 -1 FP BE Pri
98272!#7 N12385 P7947 BLD 19 -1 FP BE Pri
98273!#A N12384 N12385
98274!#7 N12386 P7947 BLD 20 -1 FP BE Pri
98275!#7 N12387 P7948 MEMBAR
98276!#7 N12388 P7949 DWST_BINIT 18 0x380018a Int BE Pri
98277!#7 N12389 P7949 DWST_BINIT 19 0x380018b Int BE Pri
98278!#A N12388 N12389
98279!#7 N12390 P7950 MEMBAR
98280!#7 N12391 P7951 SWAP 18 0xffffffff 0x380018c Int BE Pri
98281!#7 N12392 P7952 LDD 18 -1 Int BE Pri
98282!#7 N12393 P7952 LDD 19 -1 Int BE Pri
98283!#A N12392 N12393
98284!#7 N12394 P7953 MEMBAR
98285!#7 N12395 P7954 BSTC 21 0x43000115 FP BE Pri
98286!#7 N12396 P7954 BSTC 22 0x43000116 FP BE Pri
98287!#A N12395 N12396
98288!#7 N12397 P7954 BSTC 23 0x43000117 FP BE Pri
98289!#7 N12398 P7955 MEMBAR
98290!#7 N12399 P7956 ST 4 0x380018d Int BE Pri
98291!#7 N12400 P7957 LD 15 -1 Int BE Pri
98292!#7 N12401 P7958 MEMBAR
98293!#7 N12402 P7959 BLD 18 -1 FP BE Pri
98294!#7 N12403 P7959 BLD 19 -1 FP BE Pri
98295!#A N12402 N12403
98296!#7 N12404 P7959 BLD 20 -1 FP BE Pri
98297!#7 N12405 P7960 MEMBAR
98298!#7 N12406 P7961 BSTC 6 0x43000118 FP BE Pri
98299!#7 N12407 P7961 BSTC 7 0x43000119 FP BE Pri
98300!#A N12406 N12407
98301!#7 N12408 P7961 BSTC 8 0x4300011a FP BE Pri
98302!#7 N12409 P7962 MEMBAR
98303!#7 N12410 P7963 BSTC 12 0x4300011b FP BE Pri
98304!#7 N12411 P7963 BSTC 13 0x4300011c FP BE Pri
98305!#A N12410 N12411
98306!#7 N12412 P7963 BSTC 14 0x4300011d FP BE Pri
98307!#7 N12413 P7964 MEMBAR
98308!#7 N12414 P7965 SWAP 22 0xffffffff 0x380018e Int BE Pri
98309!#7 N12415 P7966 SWAP 18 0xffffffff 0x380018f Int BE Pri
98310!#7 N12416 P7967 MEMBAR
98311!#7 N12417 P7968 BSTC 21 0x4300011e FP BE Pri
98312!#7 N12418 P7968 BSTC 22 0x4300011f FP BE Pri
98313!#A N12417 N12418
98314!#7 N12419 P7968 BSTC 23 0x43000120 FP BE Pri
98315!#7 N12420 P7969 MEMBAR
98316!#7 N12421 P7970 DWST 17 0x3800190 Int BE Pri
98317!#7 N12422 P7971 LD 11 -1 FP BE Pri
98318!#7 N12423 P7972 DWST_BINIT 0 0x3800191 Int LE Pri
98319!#7 N12424 P7972 DWST_BINIT 1 0x3800192 Int LE Pri
98320!#A N12423 N12424
98321!#7 N12425 P7973 MEMBAR
98322!#7 N12426 P7974 DWST 3 0x3800193 Int LE Pri
98323!#7 N12427 P7974 DWST 4 0x3800194 Int LE Pri
98324!#A N12426 N12427
98325!#7 N12428 P7975 DWST 18 0x3800195 Int BE Pri
98326!#7 N12429 P7975 DWST 19 0x3800196 Int BE Pri
98327!#A N12428 N12429
98328!#7 N12430 P7976 DWLD 0 -1 Int BE Pri
98329!#7 N12431 P7976 DWLD 1 -1 Int BE Pri
98330!#A N12430 N12431
98331!#7 N12432 P7977 MEMBAR
98332!#7 N12433 P7978 BLD 6 -1 FP BE Pri
98333!#7 N12434 P7978 BLD 7 -1 FP BE Pri
98334!#A N12433 N12434
98335!#7 N12435 P7978 BLD 8 -1 FP BE Pri
98336!#7 N12436 P7979 MEMBAR
98337!#7 N12437 P7980 BST 15 0x43000121 FP BE Pri
98338!#7 N12438 P7980 BST 16 0x43000122 FP BE Pri
98339!#A N12437 N12438
98340!#7 N12439 P7980 BST 17 0x43000123 FP BE Pri
98341!#7 N12440 P7981 MEMBAR
98342!#7 N12441 P7982 DWST_BINIT 17 0x3800197 Int BE Pri
98343!#7 N12442 P7983 MEMBAR
98344!#7 N12443 P7984 LD 6 -1 Int BE Pri
98345!#7 N12444 P7985 MEMBAR
98346!#7 N12445 P7986 BSTC 6 0x43000124 FP BE Pri
98347!#7 N12446 P7986 BSTC 7 0x43000125 FP BE Pri
98348!#A N12445 N12446
98349!#7 N12447 P7986 BSTC 8 0x43000126 FP BE Pri
98350!#7 N12448 P7987 MEMBAR
98351!#7 N12449 P7988 PREFETCH 14 Int BE Pri
98352!#7 N12450 P7989 ST_BINIT 20 0x3800198 Int BE Pri
98353!#7 N12451 P7990 MEMBAR
98354!#7 N12452 P7991 BST 18 0x43000127 FP BE Pri
98355!#7 N12453 P7991 BST 19 0x43000128 FP BE Pri
98356!#A N12452 N12453
98357!#7 N12454 P7991 BST 20 0x43000129 FP BE Pri
98358!#7 N12455 P7992 MEMBAR
98359!#7 N12456 P7993 BST 3 0x4300012a FP BE Pri
98360!#7 N12457 P7993 BST 4 0x4300012b FP BE Pri
98361!#A N12456 N12457
98362!#7 N12458 P7993 BST 5 0x4300012c FP BE Pri
98363!#7 N12459 P7994 MEMBAR
98364!#7 N12460 P7995 LDD 23 -1 Int BE Pri
98365!#7 N12461 P7996 LD 9 -1 Int BE Pri
98366!#7 N12462 P7997 LD 19 -1 Int BE Pri
98367!#7 N12463 P7997 CAS 19 -1 N12462 0x3800199 Int BE Pri
98368!#7 N12464 P7998 MEMBAR
98369!#7 N12465 P7999 BLD 12 -1 FP BE Pri
98370!#7 N12466 P7999 BLD 13 -1 FP BE Pri
98371!#A N12465 N12466
98372!#7 N12467 P7999 BLD 14 -1 FP BE Pri
98373!#7 N12468 P8000 MEMBAR
98374!#7 N12469 P8001 BLD 0 -1 FP BE Pri
98375!#7 N12470 P8001 BLD 1 -1 FP BE Pri
98376!#A N12469 N12470
98377!#7 N12471 P8001 BLD 2 -1 FP BE Pri
98378!#7 N12472 P8002 MEMBAR
98379!#7 N12473 P8003 SWAP 16 0xffffffff 0x380019a Int BE Pri
98380!#7 N12474 P8004 DWLD 11 -1 Int BE Pri
98381!#7 N12475 P8005 DWLD 21 -1 Int BE Pri
98382!#7 N12476 P8005 DWLD 22 -1 Int BE Pri
98383!#A N12475 N12476
98384!#7 N12477 P8005 CASX 21 -1 N12475 0x380019b Int BE Pri
98385!#7 N12478 P8005 CASX 22 -1 N12476 0x380019c Int BE Pri
98386!#A N12477 N12478
98387!#7 N12479 P8006 DWST 11 0x380019d Int BE Pri
98388!#7 N12480 P8007 MEMBAR
98389!#7 N12481 P8008 BLD 9 -1 FP BE Pri
98390!#7 N12482 P8008 BLD 10 -1 FP BE Pri
98391!#A N12481 N12482
98392!#7 N12483 P8008 BLD 11 -1 FP BE Pri
98393!#7 N12484 P8009 MEMBAR
98394!#7 N12485 P8010 DWST 15 0x380019e Int BE Pri
98395!#7 N12486 P8010 DWST 16 0x380019f Int BE Pri
98396!#A N12485 N12486
98397!#7 N12487 P8011 LD 7 -1 Int BE Pri
98398!#7 N12488 P8012 LD 2 -1 Int BE Pri
98399!#7 N12489 P8013 SWAP 15 0xffffffff 0x38001a0 Int BE Pri
98400!#7 N12490 P8014 MEMBAR
98401!#7 N12491 P8015 BSTC 21 0x4300012d FP BE Pri
98402!#7 N12492 P8015 BSTC 22 0x4300012e FP BE Pri
98403!#A N12491 N12492
98404!#7 N12493 P8015 BSTC 23 0x4300012f FP BE Pri
98405!#7 N12494 P8016 MEMBAR
98406!#7 N12495 P8017 LD 3 -1 Int BE Pri Loop_exit
98407!#7 N12496 P8018 MEMBAR
Full OpenSPARC design & verification tarball including full HDL.