[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / ifu / diag / err_ittp_diag.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: err_ittp_diag.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MY_HP_TEXT_PA     0x1050000000
#define MY_HP_DATA_PA     0x1050001000

#define ASI_PRIMARY_CONTEXT_0   0x21
#define ASI_ITLB_DATA_IN_REG    0x54
#define ASI_DMMU_TAG_ACCESS     0x58
#define ASI_DTLB_DATA_IN_REG    0x5c
#define ASI_DMMU_SFAR           0x58

			
#define MY_USER_TEXT_VA000      0x7a000000
#define MY_USER_TEXT_RA000      0x7b000000
#define MY_USER_TEXT_PA000      0x107b000000
#define MY_USER_TEXT_VA001      0x7a010000
#define MY_USER_TEXT_RA001      0x7b010000
#define MY_USER_TEXT_PA001      0x107b010000

#define MY_USER_DATA_VA000      0x6a000000
#define MY_USER_DATA_RA000      0x6b000000
#define MY_USER_DATA_PA000      0x106b000000
#define MY_USER_DATA_VA001      0x6a010000
#define MY_USER_DATA_RA001      0x6b010000
#define MY_USER_DATA_PA001      0x106b010000

#define MAIN_PAGE_HV_ALSO
!! enable error detcetion. Disable error injection.
#define H_HT0_Mem_Address_Not_Aligned_0x34
#define My_HT0_Mem_Address_Not_Aligned_0x34 \
  	add %g0, CERER_VA, %g3;	\
  	stxa %o2, [%g3]ASI_CERER; \
  	stxa %g0, [%g0]ASI_ERR_INJ; \
        done;nop;nop;nop;nop

#define H_HT0_Data_Access_MMU_Error_0x72
#define SUN_H_HT0_Data_Access_MMU_Error_0x72 \
	ba DATA_ACCESS_ERROR_HANDLER; \
        nop;nop;nop;nop;nop;nop;nop

#define H_HT0_Instruction_Access_MMU_Error_0x71
#define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \
	ba INST_ACCESS_MMU_ERROR_HANDLER; \
        nop;nop;nop;nop;nop;nop;nop

#define  ERR_INJ_IMTU 1
#define CERER_ITTP 1
#define CETER_PSCCE 0
#define CETER_DE 0
#define CETER_DHCCE 0
#include "hboot.s"

/************************************************************************
   Test case:	
 ************************************************************************/

.text
.global main
!! Enable err_injection and err_detection. The pg to which we are jumping 
!! is a tLB miss, it will be loaded in TLB with err injected and then
!! on the TLB lookup error will be seen. When we first lookup the pg, it is
!! a TLB miss. The err_hanlder clears error detection but err_injection is
!!on so pg is reloaded with parity err.
main:		/* test begin */
  ta    T_CHANGE_HPRIV

  !! Enable error injection
  setx ERR_INJ_REG_DATA, %l0, %l1
  stxa %l1, [%g0]ASI_ERR_INJ

  setx CERER_DATA, %l0, %o2

  ta T_CHANGE_NONHPRIV	
  mov %g0, %i0
  setx user_code_begin_000, %g1, %l4
  jmp  %l4
  nop
  EXIT_BAD
  nop
	

/************************************************************************
   Test case data start
 ************************************************************************/
.data
.global user_data_start
user_data_start:
.word 0xD6B3479D
.word 0xDB28926C

!#***********************************************************************
	
SECTION .My_User_Section_4v000 TEXT_VA=MY_USER_TEXT_VA000, DATA_VA=MY_USER_DATA_VA000
attr_text {
	Name = .My_User_Section_4v000,
	part_0_ctx_nonzero_tsb_config_2,
	VA = MY_USER_TEXT_VA000,
	RA = MY_USER_TEXT_RA000,
	PA = ra2pa(MY_USER_TEXT_RA000, 0),
	TTE_Context = PCONTEXT,
	TTE_V       = 1,
	TTE_NFO     = 0,
	TTE_L       = 0,
	TTE_Soft    = 0,
	TTE_IE      = 0,
	TTE_E       = 0,
	TTE_CP      = 1,
	TTE_CV      = 0,
	TTE_P       = 0,
	TTE_EP      = 1,
	TTE_W       = 0,
	TTE_SW1     = 0,
	TTE_SW0     = 0,
	TTE_RSVD1   = 0,
	TTE_Size    = 0,
	}

!! Take mis aligned trap. The trap handler enables err_detection and 
!! clears err_injection. On return from trap handler, mmu_err trap is
!! taken for label TH0_done. The pg is reloaded with no err.
.text
.global user_code_begin_000
user_code_begin_000:
	cmp     %i0, 0x1
	bne     FAIL
	mov 	%g0, %i0
	setx user_data_begin_000, %g1, %l3
	setx TH0_DONE, %g1, %l4
	ld [%l3+1], %g1  !cause mem_addr_not_aligned trap
TH0_DONE:
	cmp     %i0, 0x1
	bne     FAIL
  	setx user_code_begin_001, %g1, %l4
  	jmp  %l4
  	mov %g0, %i0

FAIL:	EXIT_BAD
	nop

attr_data {
	Name = .My_User_Section_4v000,
	part_0_ctx_nonzero_tsb_config_1,
	VA = MY_USER_DATA_VA000,
	RA = MY_USER_DATA_RA000,
	PA = ra2pa(MY_USER_DATA_RA000, 0),
	TTE_Context = PCONTEXT,
	TTE_V       = 1,
	TTE_NFO     = 0,
	TTE_L       = 0,
	TTE_Soft    = 0,
	TTE_IE      = 0,
	TTE_E       = 0,
	TTE_CP      = 1,
	TTE_CV      = 0,
	TTE_P       = 0,
	TTE_EP      = 0,
	TTE_W       = 1,
	TTE_SW1     = 0,
	TTE_SW0     = 0,
	TTE_RSVD1   = 0,
	TTE_Size    = 0,
	}
.data
.global user_data_begin_000
user_data_begin_000:
	.word 0x6c7e
	.word 0x2fbf
	.word 0x2c83
	.word 0x11ab0

SECTION .My_User_Section_4v001 TEXT_VA=MY_USER_TEXT_VA001, DATA_VA=MY_USER_DATA_VA001
attr_text {
        Name = .My_User_Section_4v001,
        part_0_ctx_nonzero_tsb_config_2,
        VA = MY_USER_TEXT_VA001,
        RA = MY_USER_TEXT_RA001,
 PA = ra2pa(MY_USER_TEXT_RA001, 0),
        TTE_Context = PCONTEXT,
        TTE_V       = 1,
        TTE_NFO     = 0,
        TTE_L       = 0,
        TTE_Soft    = 0,
        TTE_IE      = 0,
        TTE_E       = 0,
        TTE_CP      = 1,
        TTE_CV      = 0,
        TTE_P       = 0,
        TTE_EP      = 1,
        TTE_W       = 0,
        TTE_SW1     = 0,
        TTE_SW0     = 0,
        TTE_RSVD1   = 0,
        TTE_Size    = 0,
        }
attr_text {
NAME = .My_User_Section_4v001,
  hypervisor
}

!! Chk if there is an err in the delay slot and delay slot is annulled
!! then err is not reported.
!! pg _001 has no error. Lable TGT0 represents the first inst. of
!! next_page and TGT1 represents the 2nd inst.
!! There are two iterations, in the first iteration inst in delay slot is
!! executed and causes pg to be loaded with err in tlb. Alignment trap
!! is taken that causes err_detection to be enabled. On return from
!!trap handler the delay slot inst has an err but it is not reported as
!! the delay slot os annulled.
.text
.global user_code_begin_001
.skip 8124
user_code_begin_001:
	mov %g0, %i1 	! to control branch execution
  	ta   T_CHANGE_HPRIV
  	!! Enable error injection
  	stxa %l1, [%g0]ASI_ERR_INJ
  	ta T_CHANGE_NONHPRIV	
        setx TGT1, %g1, %l4
	setx user_data_begin_000, %g1, %l3
GO_BACK: brz,a  %i1, TGT1	!! load entry in ITLB
TGT0:	add %g0, %g7, %g5  !! dummy inst
TGT1:	add %g0, 1, %i1
	brz,a  %i0, GO_BACK
	ld [%l3+1], %g1  !cause mem_addr_not_aligned trap
	cmp %i0, 1
	bnz FAIL
	nop
	EXIT_GOOD
	nop

FAIL:   EXIT_BAD
        nop

attr_data {
        Name = .My_User_Section_4v001,
        part_0_ctx_nonzero_tsb_config_1,
        VA = MY_USER_DATA_VA001,
        RA = MY_USER_DATA_RA001,
 PA = ra2pa(MY_USER_DATA_RA001, 0),
        TTE_Context = PCONTEXT,
        TTE_V       = 1,
        TTE_NFO     = 0,
        TTE_L       = 0,
        TTE_Soft    = 0,
        TTE_IE      = 0,
        TTE_E       = 0,
        TTE_CP      = 1,
        TTE_CV      = 0,
        TTE_P       = 0,
        TTE_EP      = 0,
        TTE_W       = 1,
        TTE_SW1     = 0,
        TTE_SW0     = 0,
        TTE_RSVD1   = 0,
        TTE_Size    = 0,
        }
attr_data {
NAME = .My_User_Section_4v001,
  hypervisor
}

.data
.global user_data_begin_001
user_data_begin_001:
        .word 0x10731
        .word 0xd027
        .word 0x1350e
        .word 0x10e9d

.global DATA_ACCESS_ERROR_HANDLER
.global INST_ACCESS_ERROR_HANDLER

SECTION .HTRAPS
.text
DATA_ACCESS_ERROR_HANDLER:
        add %g0, SFSR_VA, %g5		!
	ldxa 	[%g5]ASI_DSFSR, %o1	!
	cmp	%o1, 0x1
	bne 	FAIL
        add     %g0, SFAR_VA, %g6	!!g6 has sfar va
	ldxa 	[%g6]ASI_SFAR, %o1	
	cmp 	%o1, %l3
	bne 	FAIL
	//issue demap pg
	xor 	%o1, 0x1fff, %o1
	stxa    %g0, [%o1] ASI_DMMU_DEMAP
	//disable errors
  	add %g0, CERER_VA, %g3	
  	stxa %g0, [%g3]ASI_CERER
        add %g0, 1, %i0		!
        retry
	nop


INST_ACCESS_MMU_ERROR_HANDLER:
        add 	%g0, SFSR_VA, %g5		!
	ldxa 	[%g5]ASI_ISFSR, %o1	!
	cmp	%o1, ISFSR_ITTP  
	bne 	FAIL
	stxa 	%g0, [%g5]ASI_ISFSR
        add     %g0, SFAR_VA, %g6	!!g6 has sfar va
	rdpr 	%tpc, %o1
	cmp 	%o1, %l4  		!! cmp pc matches the expected pc
	bne 	FAIL
	!issue demap pg
	srlx 	%o1, 0xd, %o1
	sllx 	%o1, 0xd, %o1
	stxa    %g0, [%o1] ASI_IMMU_DEMAP
	!disable errors
  	add %g0, CERER_VA, %g3	
  	stxa %g0, [%g3]ASI_CERER
        add %g0, 1, %i0		!
	retry

FAIL: EXIT_BAD
	nop
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: err_ittp_diag.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MY_HP_TEXT_PA 0x1050000000
	39	#define MY_HP_DATA_PA 0x1050001000
	40
	41	#define ASI_PRIMARY_CONTEXT_0 0x21
	42	#define ASI_ITLB_DATA_IN_REG 0x54
	43	#define ASI_DMMU_TAG_ACCESS 0x58
	44	#define ASI_DTLB_DATA_IN_REG 0x5c
	45	#define ASI_DMMU_SFAR 0x58
	46
	47
	48	#define MY_USER_TEXT_VA000 0x7a000000
	49	#define MY_USER_TEXT_RA000 0x7b000000
	50	#define MY_USER_TEXT_PA000 0x107b000000
	51	#define MY_USER_TEXT_VA001 0x7a010000
	52	#define MY_USER_TEXT_RA001 0x7b010000
	53	#define MY_USER_TEXT_PA001 0x107b010000
	54
	55	#define MY_USER_DATA_VA000 0x6a000000
	56	#define MY_USER_DATA_RA000 0x6b000000
	57	#define MY_USER_DATA_PA000 0x106b000000
	58	#define MY_USER_DATA_VA001 0x6a010000
	59	#define MY_USER_DATA_RA001 0x6b010000
	60	#define MY_USER_DATA_PA001 0x106b010000
	61
	62	#define MAIN_PAGE_HV_ALSO
	63	!! enable error detcetion. Disable error injection.
	64	#define H_HT0_Mem_Address_Not_Aligned_0x34
65	#define My_HT0_Mem_Address_Not_Aligned_0x34 \
66	add %g0, CERER_VA, %g3; \
67	stxa %o2, [%g3]ASI_CERER; \
68	stxa %g0, [%g0]ASI_ERR_INJ; \
69	done;nop;nop;nop;nop
70
71	#define H_HT0_Data_Access_MMU_Error_0x72
72	#define SUN_H_HT0_Data_Access_MMU_Error_0x72 \
73	ba DATA_ACCESS_ERROR_HANDLER; \
74	nop;nop;nop;nop;nop;nop;nop
75
76	#define H_HT0_Instruction_Access_MMU_Error_0x71
77	#define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \
78	ba INST_ACCESS_MMU_ERROR_HANDLER; \
79	nop;nop;nop;nop;nop;nop;nop
80
81	#define ERR_INJ_IMTU 1
82	#define CERER_ITTP 1
83	#define CETER_PSCCE 0
84	#define CETER_DE 0
85	#define CETER_DHCCE 0
86	#include "hboot.s"
87
88	/************************************************************************
89	Test case:
90	************************************************************************/
91
92	.text
93	.global main
94	!! Enable err_injection and err_detection. The pg to which we are jumping
95	!! is a tLB miss, it will be loaded in TLB with err injected and then
96	!! on the TLB lookup error will be seen. When we first lookup the pg, it is
97	!! a TLB miss. The err_hanlder clears error detection but err_injection is
98	!!on so pg is reloaded with parity err.
99	main: /* test begin */
100	ta T_CHANGE_HPRIV
101
102	!! Enable error injection
103	setx ERR_INJ_REG_DATA, %l0, %l1
104	stxa %l1, [%g0]ASI_ERR_INJ
105
106	setx CERER_DATA, %l0, %o2
107
108	ta T_CHANGE_NONHPRIV
109	mov %g0, %i0
110	setx user_code_begin_000, %g1, %l4
111	jmp %l4
112	nop
113	EXIT_BAD
114	nop
115
116
117
118	/************************************************************************
119	Test case data start
120	************************************************************************/
121	.data
122	.global user_data_start
123	user_data_start:
124	.word 0xD6B3479D
125	.word 0xDB28926C
126
127	!#***********************************************************************
128
129	SECTION .My_User_Section_4v000 TEXT_VA=MY_USER_TEXT_VA000, DATA_VA=MY_USER_DATA_VA000
130	attr_text {
131	Name = .My_User_Section_4v000,
132	part_0_ctx_nonzero_tsb_config_2,
133	VA = MY_USER_TEXT_VA000,
134	RA = MY_USER_TEXT_RA000,
135	PA = ra2pa(MY_USER_TEXT_RA000, 0),
136	TTE_Context = PCONTEXT,
137	TTE_V = 1,
138	TTE_NFO = 0,
139	TTE_L = 0,
140	TTE_Soft = 0,
141	TTE_IE = 0,
142	TTE_E = 0,
143	TTE_CP = 1,
144	TTE_CV = 0,
145	TTE_P = 0,
146	TTE_EP = 1,
147	TTE_W = 0,
148	TTE_SW1 = 0,
149	TTE_SW0 = 0,
150	TTE_RSVD1 = 0,
151	TTE_Size = 0,
152	}
153
154	!! Take mis aligned trap. The trap handler enables err_detection and
155	!! clears err_injection. On return from trap handler, mmu_err trap is
156	!! taken for label TH0_done. The pg is reloaded with no err.
157	.text
158	.global user_code_begin_000
159	user_code_begin_000:
160	cmp %i0, 0x1
161	bne FAIL
162	mov %g0, %i0
163	setx user_data_begin_000, %g1, %l3
164	setx TH0_DONE, %g1, %l4
165	ld [%l3+1], %g1 !cause mem_addr_not_aligned trap
166	TH0_DONE:
167	cmp %i0, 0x1
168	bne FAIL
169	setx user_code_begin_001, %g1, %l4
170	jmp %l4
171	mov %g0, %i0
172
173	FAIL: EXIT_BAD
174	nop
175
176	attr_data {
177	Name = .My_User_Section_4v000,
178	part_0_ctx_nonzero_tsb_config_1,
179	VA = MY_USER_DATA_VA000,
180	RA = MY_USER_DATA_RA000,
181	PA = ra2pa(MY_USER_DATA_RA000, 0),
182	TTE_Context = PCONTEXT,
183	TTE_V = 1,
184	TTE_NFO = 0,
185	TTE_L = 0,
186	TTE_Soft = 0,
187	TTE_IE = 0,
188	TTE_E = 0,
189	TTE_CP = 1,
190	TTE_CV = 0,
191	TTE_P = 0,
192	TTE_EP = 0,
193	TTE_W = 1,
194	TTE_SW1 = 0,
195	TTE_SW0 = 0,
196	TTE_RSVD1 = 0,
197	TTE_Size = 0,
198	}
199	.data
200	.global user_data_begin_000
201	user_data_begin_000:
202	.word 0x6c7e
203	.word 0x2fbf
204	.word 0x2c83
205	.word 0x11ab0
206
207	SECTION .My_User_Section_4v001 TEXT_VA=MY_USER_TEXT_VA001, DATA_VA=MY_USER_DATA_VA001
208	attr_text {
209	Name = .My_User_Section_4v001,
210	part_0_ctx_nonzero_tsb_config_2,
211	VA = MY_USER_TEXT_VA001,
212	RA = MY_USER_TEXT_RA001,
213	PA = ra2pa(MY_USER_TEXT_RA001, 0),
214	TTE_Context = PCONTEXT,
215	TTE_V = 1,
216	TTE_NFO = 0,
217	TTE_L = 0,
218	TTE_Soft = 0,
219	TTE_IE = 0,
220	TTE_E = 0,
221	TTE_CP = 1,
222	TTE_CV = 0,
223	TTE_P = 0,
224	TTE_EP = 1,
225	TTE_W = 0,
226	TTE_SW1 = 0,
227	TTE_SW0 = 0,
228	TTE_RSVD1 = 0,
229	TTE_Size = 0,
230	}
231	attr_text {
232	NAME = .My_User_Section_4v001,
233	hypervisor
234	}
235
236	!! Chk if there is an err in the delay slot and delay slot is annulled
237	!! then err is not reported.
238	!! pg _001 has no error. Lable TGT0 represents the first inst. of
239	!! next_page and TGT1 represents the 2nd inst.
240	!! There are two iterations, in the first iteration inst in delay slot is
241	!! executed and causes pg to be loaded with err in tlb. Alignment trap
242	!! is taken that causes err_detection to be enabled. On return from
243	!!trap handler the delay slot inst has an err but it is not reported as
244	!! the delay slot os annulled.
245	.text
246	.global user_code_begin_001
247	.skip 8124
248	user_code_begin_001:
249	mov %g0, %i1 ! to control branch execution
250	ta T_CHANGE_HPRIV
251	!! Enable error injection
252	stxa %l1, [%g0]ASI_ERR_INJ
253	ta T_CHANGE_NONHPRIV
254	setx TGT1, %g1, %l4
255	setx user_data_begin_000, %g1, %l3
256	GO_BACK: brz,a %i1, TGT1 !! load entry in ITLB
257	TGT0: add %g0, %g7, %g5 !! dummy inst
258	TGT1: add %g0, 1, %i1
259	brz,a %i0, GO_BACK
260	ld [%l3+1], %g1 !cause mem_addr_not_aligned trap
261	cmp %i0, 1
262	bnz FAIL
263	nop
264	EXIT_GOOD
265	nop
266
267	FAIL: EXIT_BAD
268	nop
269
270	attr_data {
271	Name = .My_User_Section_4v001,
272	part_0_ctx_nonzero_tsb_config_1,
273	VA = MY_USER_DATA_VA001,
274	RA = MY_USER_DATA_RA001,
275	PA = ra2pa(MY_USER_DATA_RA001, 0),
276	TTE_Context = PCONTEXT,
277	TTE_V = 1,
278	TTE_NFO = 0,
279	TTE_L = 0,
280	TTE_Soft = 0,
281	TTE_IE = 0,
282	TTE_E = 0,
283	TTE_CP = 1,
284	TTE_CV = 0,
285	TTE_P = 0,
286	TTE_EP = 0,
287	TTE_W = 1,
288	TTE_SW1 = 0,
289	TTE_SW0 = 0,
290	TTE_RSVD1 = 0,
291	TTE_Size = 0,
292	}
293	attr_data {
294	NAME = .My_User_Section_4v001,
295	hypervisor
296	}
297
298	.data
299	.global user_data_begin_001
300	user_data_begin_001:
301	.word 0x10731
302	.word 0xd027
303	.word 0x1350e
304	.word 0x10e9d
305
306	.global DATA_ACCESS_ERROR_HANDLER
307	.global INST_ACCESS_ERROR_HANDLER
308
309	SECTION .HTRAPS
310	.text
311	DATA_ACCESS_ERROR_HANDLER:
312	add %g0, SFSR_VA, %g5 !
313	ldxa [%g5]ASI_DSFSR, %o1 !
314	cmp %o1, 0x1
315	bne FAIL
316	add %g0, SFAR_VA, %g6 !!g6 has sfar va
317	ldxa [%g6]ASI_SFAR, %o1
318	cmp %o1, %l3
319	bne FAIL
320	//issue demap pg
321	xor %o1, 0x1fff, %o1
322	stxa %g0, [%o1] ASI_DMMU_DEMAP
323	//disable errors
324	add %g0, CERER_VA, %g3
325	stxa %g0, [%g3]ASI_CERER
326	add %g0, 1, %i0 !
327	retry
328	nop
329
330
331	INST_ACCESS_MMU_ERROR_HANDLER:
332	add %g0, SFSR_VA, %g5 !
333	ldxa [%g5]ASI_ISFSR, %o1 !
334	cmp %o1, ISFSR_ITTP
335	bne FAIL
336	stxa %g0, [%g5]ASI_ISFSR
337	add %g0, SFAR_VA, %g6 !!g6 has sfar va
338	rdpr %tpc, %o1
339	cmp %o1, %l4 !! cmp pc matches the expected pc
340	bne FAIL
341	!issue demap pg
342	srlx %o1, 0xd, %o1
343	sllx %o1, 0xd, %o1
344	stxa %g0, [%o1] ASI_IMMU_DEMAP
345	!disable errors
346	add %g0, CERER_VA, %g3
347	stxa %g0, [%g3]ASI_CERER
348	add %g0, 1, %i0 !
349	retry
350
351	FAIL: EXIT_BAD
352	nop