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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: err_fc_dcdp_dcl2u_diag.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MY_HP_TEXT_PA 0x1050000000 | |
39 | #define MY_HP_DATA_PA 0x1050001000 | |
40 | ||
41 | #define ASI_PRIMARY_CONTEXT_0 0x21 | |
42 | #define ASI_ITLB_DATA_IN_REG 0x54 | |
43 | #define ASI_DMMU_TAG_ACCESS 0x58 | |
44 | #define ASI_DTLB_DATA_IN_REG 0x5c | |
45 | #define ASI_DMMU_SFAR 0x58 | |
46 | ||
47 | ||
48 | #define MY_USER_TEXT_VA000 0x7a000000 | |
49 | #define MY_USER_TEXT_RA000 0x7b000000 | |
50 | #define MY_USER_TEXT_PA000 0x107b000000 | |
51 | #define MY_USER_TEXT_VA001 0x7a010000 | |
52 | #define MY_USER_TEXT_RA001 0x7b010000 | |
53 | #define MY_USER_TEXT_PA001 0x107b010000 | |
54 | #define MY_USER_TEXT_VA002 0x7a020000 | |
55 | #define MY_USER_TEXT_RA002 0x7b020000 | |
56 | #define MY_USER_TEXT_PA002 0x107b020000 | |
57 | #define MY_USER_TEXT_VA003 0x7a030000 | |
58 | #define MY_USER_TEXT_RA003 0x7b030000 | |
59 | #define MY_USER_TEXT_PA003 0x107b030000 | |
60 | #define MY_USER_TEXT_VA004 0x7a040000 | |
61 | #define MY_USER_TEXT_RA004 0x7b040000 | |
62 | #define MY_USER_TEXT_PA004 0x107b040000 | |
63 | #define MY_USER_TEXT_VA005 0x7a050000 | |
64 | #define MY_USER_TEXT_RA005 0x7b050000 | |
65 | #define MY_USER_TEXT_PA005 0x107b050000 | |
66 | #define MY_USER_TEXT_VA006 0x7a060000 | |
67 | #define MY_USER_TEXT_RA006 0x7b060000 | |
68 | #define MY_USER_TEXT_PA006 0x107b060000 | |
69 | #define MY_USER_TEXT_VA007 0x7a070000 | |
70 | #define MY_USER_TEXT_RA007 0x7b070000 | |
71 | #define MY_USER_TEXT_PA007 0x107b070000 | |
72 | #define MY_USER_TEXT_VA008 0x7a080000 | |
73 | #define MY_USER_TEXT_RA008 0x7b080000 | |
74 | #define MY_USER_TEXT_PA008 0x107b080000 | |
75 | #define MY_USER_TEXT_VA009 0x7a090000 | |
76 | #define MY_USER_TEXT_RA009 0x7b090000 | |
77 | #define MY_USER_TEXT_PA009 0x107b090000 | |
78 | #define MY_USER_TEXT_VA010 0x7a0a0000 | |
79 | #define MY_USER_TEXT_RA010 0x7b0a0000 | |
80 | #define MY_USER_TEXT_PA010 0x107b0a0000 | |
81 | #define MY_USER_TEXT_VA011 0x7a0b0000 | |
82 | #define MY_USER_TEXT_RA011 0x7b0b0000 | |
83 | #define MY_USER_TEXT_PA011 0x107b0b0000 | |
84 | #define MY_USER_TEXT_VA012 0x7a0c0000 | |
85 | #define MY_USER_TEXT_RA012 0x7b0c0000 | |
86 | #define MY_USER_TEXT_PA012 0x107b0c0000 | |
87 | #define MY_USER_TEXT_VA013 0x7a0d0000 | |
88 | #define MY_USER_TEXT_RA013 0x7b0d0000 | |
89 | #define MY_USER_TEXT_PA013 0x107b0d0000 | |
90 | ||
91 | #define MY_USER_DATA_VA000 0x6a002000 | |
92 | #define MY_USER_DATA_RA000 0x6b002000 | |
93 | #define MY_USER_DATA_PA000 0x106b002000 | |
94 | #define MY_USER_DATA_VA001 0x6a004000 | |
95 | #define MY_USER_DATA_RA001 0x6b004000 | |
96 | #define MY_USER_DATA_PA001 0x106b004000 | |
97 | #define MY_USER_DATA_VA002 0x6a086000 | |
98 | #define MY_USER_DATA_RA002 0x6b086000 | |
99 | #define MY_USER_DATA_PA002 0x106b086000 | |
100 | #define MY_USER_DATA_VA003 0x6a0c8000 | |
101 | #define MY_USER_DATA_RA003 0x6b0c8000 | |
102 | #define MY_USER_DATA_PA003 0x106b0c8000 | |
103 | #define MY_USER_DATA_VA004 0x6a10a000 | |
104 | #define MY_USER_DATA_RA004 0x6b10a000 | |
105 | #define MY_USER_DATA_PA004 0x106b10a000 | |
106 | #define MY_USER_DATA_VA005 0x6a14c000 | |
107 | #define MY_USER_DATA_RA005 0x6b14c000 | |
108 | #define MY_USER_DATA_PA005 0x106b14c000 | |
109 | #define MY_USER_DATA_VA006 0x6a18e000 | |
110 | #define MY_USER_DATA_RA006 0x6b18e000 | |
111 | #define MY_USER_DATA_PA006 0x106b18e000 | |
112 | #define MY_USER_DATA_VA007 0x6a1e0000 | |
113 | #define MY_USER_DATA_RA007 0x6b1e0000 | |
114 | #define MY_USER_DATA_PA007 0x106b1e0000 | |
115 | #define MY_USER_DATA_VA008 0x6a080000 | |
116 | #define MY_USER_DATA_RA008 0x6b080000 | |
117 | #define MY_USER_DATA_PA008 0x106b080000 | |
118 | #define MY_USER_DATA_VA009 0x6a090000 | |
119 | #define MY_USER_DATA_RA009 0x6b090000 | |
120 | #define MY_USER_DATA_PA009 0x106b090000 | |
121 | #define MY_USER_DATA_VA010 0x6a0a0000 | |
122 | #define MY_nc_DATA_RA010 0xb06b0a0000 | |
123 | #define MY_nc_DATA_PA010 0xc06b0a0000 | |
124 | #define MY_USER_DATA_VA011 0x6a0b0000 | |
125 | #define MY_nc_DATA_RA011 0xb06b0b0000 | |
126 | #define MY_nc_DATA_PA011 0xc06b0b0000 | |
127 | #define MY_USER_DATA_VA012 0x6a0c0000 | |
128 | #define MY_nc_DATA_RA012 0xb06b0c0000 | |
129 | #define MY_nc_DATA_PA012 0xc06b0c0000 | |
130 | #define MY_USER_DATA_VA013 0x6a0d0000 | |
131 | #define MY_nc_DATA_RA013 0xb06b0d0000 | |
132 | #define MY_nc_DATA_PA013 0xc06b0d0000 | |
133 | ||
134 | #define IMDU_ERR_EN 0xa0000000 | |
135 | #define IMTU_ERR_EN 0x90000000 | |
136 | #define DMDU_ERR_EN 0x88000000 | |
137 | #define DMTU_ERR_EN 0x84000000 | |
138 | #define IRCU_ERR_EN 0x82000000 | |
139 | #define FRCU_ERR_EN 0x81000000 | |
140 | #define SCAU_ERR_EN 0x80800000 | |
141 | #define TCCU_ERR_EN 0x80400000 | |
142 | #define TSAU_ERR_EN 0x80200000 | |
143 | #define MRAU_ERR_EN 0x80100000 | |
144 | #define STAU_ERR_EN 0x80080000 | |
145 | #define STDU_ERR_EN 0x80020000 | |
146 | ||
147 | #define ASI_DESR 0x4c | |
148 | #define ASI_DFESR 0x4c | |
149 | #define DFESR_VA 0x8 | |
150 | #define ASI_DSFSR 0x58 | |
151 | #define ASI_ISFSR 0x50 | |
152 | #define SFSR_VA 0x18 | |
153 | #define ASI_SFAR 0x58 | |
154 | #define SFAR_VA 0x20 | |
155 | #define ASI_ERR_INJ 0x43 | |
156 | #define ASI_CETER 0x4C | |
157 | #define CETER_VA 0x18 | |
158 | #define ASI_CERER 0x4C | |
159 | #define CERER_VA 0x10 | |
160 | ||
161 | #define CETER_ALL 0x7000_0000_0000_0000 | |
162 | #define DCDP_ERR_TYPE 0x8 | |
163 | ||
164 | #define MAIN_PAGE_HV_ALSO | |
165 | ||
166 | #define H_HT0_Data_access_error_0x32 DATA_ACCESS_ERROR_HANDLER | |
167 | ||
168 | #define H_HT0_Hw_Corrected_Error_0x63 | |
169 | #define SUN_H_HT0_Hw_Corrected_Error_0x63 \ | |
170 | ba HW_CORR_ERROR_HANDLER; \ | |
171 | nop;nop;nop;nop;nop;nop;nop | |
172 | ||
173 | #include "hboot.s" | |
174 | ||
175 | /************************************************************************ | |
176 | Test case: | |
177 | ************************************************************************/ | |
178 | #define TEST_DATA0 0x5555555555555555 | |
179 | #define TEST_DATA1 0x1122334455667788 | |
180 | #define TEST_DATA2 0xaabbccddeeff0011 | |
181 | #define TEST_DATA3 0x123456789abcdeff | |
182 | #define TEST_DATA4 0xff123456789abcde | |
183 | #define TEST_DATA5 0x1f2f3f4e5d6a7b8c | |
184 | #define TEST_DATA6 0xe1d2f3b5a8e3a8a9 | |
185 | #define TEST_DATA7 0x1a2b3c4d5e6f2346 | |
186 | #define ALL_F 0Xffffffffffffffff | |
187 | ||
188 | .text | |
189 | .global main | |
190 | ||
191 | main: /* test begin */ | |
192 | ta T_CHANGE_HPRIV | |
193 | ||
194 | setx 0x0000008000000800, %l0, %o2 !! enable DCDP errs and l2c errors | |
195 | add %g0, CERER_VA, %g3 !!g3 has cerer va | |
196 | ||
197 | stxa %o2, [%g3]ASI_CERER | |
198 | ||
199 | !! set CETER.all | |
200 | mov 7, %o2 | |
201 | sllx %o2, 60, %o2 | |
202 | add %g0, CETER_VA, %g3 | |
203 | stxa %o2, [%g3]ASI_CETER | |
204 | ||
205 | !! Put cache in direct mapped mode | |
206 | add %g0, 0x10, %g1 | |
207 | or %g0, 0x2, %g2 | |
208 | stxa %g2, [%g1]ASI_DIAG | |
209 | ||
210 | !! set NCEEN in l2 err enable reg | |
211 | set_nccen_l2: | |
212 | mov 0xaa, %g1 | |
213 | sllx %g1, 32, %g1 | |
214 | mov 0x2, %g2 | |
215 | stx %g2, [%g1] | |
216 | stx %g2, [%g1+0x40] | |
217 | stx %g2, [%g1+0x80] | |
218 | stx %g2, [%g1+0xc0] | |
219 | stx %g2, [%g1+0x100] | |
220 | stx %g2, [%g1+0x140] | |
221 | stx %g2, [%g1+0x180] | |
222 | stx %g2, [%g1+0x1c0] | |
223 | ||
224 | !! put l2$ banks in direct mapped mode | |
225 | l2cache_dm: | |
226 | mov 0xa9, %g1 | |
227 | sllx %g1, 32, %g1 | |
228 | mov 0x2, %g2 | |
229 | stx %g2, [%g1] | |
230 | stx %g2, [%g1+0x40] | |
231 | stx %g2, [%g1+0x80] | |
232 | stx %g2, [%g1+0xc0] | |
233 | stx %g2, [%g1+0x100] | |
234 | stx %g2, [%g1+0x140] | |
235 | stx %g2, [%g1+0x180] | |
236 | stx %g2, [%g1+0x1c0] | |
237 | ||
238 | setx 0x3ffff8, %g1, %l3 !! mask to capture the lower 22 bits of the PA | |
239 | mov 8, %l4 !! no. of iterations for each thread | |
240 | ||
241 | !!ta T_CHANGE_NONHPRIV | |
242 | ||
243 | setx user_code_begin_000, %g1, %g2 | |
244 | jmp %g2 | |
245 | nop | |
246 | EXIT_BAD | |
247 | ||
248 | ||
249 | FAIL: | |
250 | EXIT_BAD | |
251 | nop | |
252 | ||
253 | ||
254 | /************************************************************************ | |
255 | Test case data start | |
256 | ************************************************************************/ | |
257 | .data | |
258 | .global user_data_start | |
259 | user_data_start: | |
260 | .word 0x12345678 | |
261 | .word 0x9a9b9c9d | |
262 | .word 0x00000000 | |
263 | .word 0xffffffff | |
264 | ||
265 | !#*********************************************************************** | |
266 | ||
267 | SECTION .My_User_Section_4v000 TEXT_VA=MY_USER_TEXT_VA000, DATA_VA=MY_USER_DATA_VA000 | |
268 | attr_text { | |
269 | Name = .My_User_Section_4v000, | |
270 | part_0_ctx_nonzero_tsb_config_2, | |
271 | VA = MY_USER_TEXT_VA000, | |
272 | RA = MY_USER_TEXT_RA000, | |
273 | PA = ra2pa(MY_USER_TEXT_RA000, 0), | |
274 | TTE_Context = PCONTEXT, | |
275 | TTE_V = 1, | |
276 | TTE_NFO = 0, | |
277 | TTE_L = 0, | |
278 | TTE_Soft = 0, | |
279 | TTE_IE = 0, | |
280 | TTE_E = 0, | |
281 | TTE_CP = 1, | |
282 | TTE_CV = 0, | |
283 | TTE_P = 0, | |
284 | TTE_EP = 1, | |
285 | TTE_W = 0, | |
286 | TTE_SW1 = 0, | |
287 | TTE_SW0 = 0, | |
288 | TTE_RSVD1 = 0, | |
289 | TTE_Size = 0, | |
290 | } | |
291 | attr_text { | |
292 | NAME = .My_User_Section_4v000, | |
293 | hypervisor | |
294 | } | |
295 | .text | |
296 | .global user_code_begin_000 | |
297 | user_code_begin_000: | |
298 | setx user_data_begin_000, %g1, %l1 | |
299 | add %l1, 0x200, %l2 | |
300 | setx TEST_DATA0, %g1, %g3 | |
301 | setx ALL_F, %g1, %g4 | |
302 | ||
303 | store_to_l2_th0: | |
304 | mov %g0, %i0 | |
305 | mov %g0, %i1 | |
306 | xor %g3, %g4, %g3 | |
307 | stxa %g3, [%l1]0x10 | |
308 | membar #Sync | |
309 | !!add %l2, 0x10, %l2 | |
310 | !!ldxa [%l2]0x10, %l5 | |
311 | prefetch [%l2], 0x18 !!add a prefetch ice so that the above store is committed before the | |
312 | !!diagnostic read executes | |
313 | ||
314 | diag_read_l2_th0: | |
315 | mov 0xa0, %g2 | |
316 | sllx %g2, 32, %g2 | |
317 | and %l3, %l1, %g1 | |
318 | add %g2, %g1, %g2 | |
319 | ldx [%g2], %g5 | |
320 | ||
321 | inj_ue_th0: | |
322 | xor %g5, 0x5, %g5 | |
323 | stx %g5, [%g2] | |
324 | membar #Sync | |
325 | ||
326 | ld_in_l1_th0: | |
327 | ldxa [%l1]0x10, %l5 !! shd see data_acc_err, put line in cache with bad parity | |
328 | brz %i0, FAIL | |
329 | mov %g0, %i0 | |
330 | ldxa [%l1]0x10, %l5 !! Do a ld, shd see both data_acc and hw_corrected err | |
331 | brz %i0, FAIL | |
332 | brz %i1, FAIL | |
333 | add %l2, 0x40, %l2 | |
334 | dec %l4 | |
335 | brnz %l4, store_to_l2_th0 | |
336 | add %l1, 0x40, %l1 | |
337 | ||
338 | EXIT_GOOD | |
339 | nop | |
340 | ||
341 | FAIL: | |
342 | EXIT_BAD | |
343 | ||
344 | attr_data { | |
345 | Name = .My_User_Section_4v000, | |
346 | part_0_ctx_nonzero_tsb_config_1, | |
347 | VA = MY_USER_DATA_VA000, | |
348 | RA = MY_USER_DATA_RA000, | |
349 | PA = ra2pa(MY_USER_DATA_RA000, 0), | |
350 | TTE_Context = PCONTEXT, | |
351 | TTE_V = 1, | |
352 | TTE_NFO = 0, | |
353 | TTE_L = 0, | |
354 | TTE_Soft = 0, | |
355 | TTE_IE = 0, | |
356 | TTE_E = 0, | |
357 | TTE_CP = 1, | |
358 | TTE_CV = 0, | |
359 | TTE_P = 0, | |
360 | TTE_EP = 0, | |
361 | TTE_W = 1, | |
362 | TTE_SW1 = 0, | |
363 | TTE_SW0 = 0, | |
364 | TTE_RSVD1 = 0, | |
365 | TTE_Size = 0, | |
366 | } | |
367 | attr_data { | |
368 | NAME = .My_User_Section_4v000, | |
369 | hypervisor | |
370 | } | |
371 | .data | |
372 | .global user_data_begin_000 | |
373 | user_data_begin_000: | |
374 | .xword 0xe0066361bd9fcb86 | |
375 | .xword 0xea22901c101f6f52 | |
376 | .xword 0x806faa2171350467 | |
377 | .xword 0xff54f2cd06a0d342 | |
378 | .xword 0x566bff718cddb905 | |
379 | .xword 0x6d367bc4d165d37a | |
380 | .xword 0x5efc42b18f920522 | |
381 | .xword 0x584c92dec4bc66de | |
382 | ||
383 | .xword 0xed9efe0d05896ce1 | |
384 | .xword 0xf9d45b94972117c8 | |
385 | .xword 0xd0c647618c9e43f3 | |
386 | .xword 0xfe04ead3b77c2d11 | |
387 | .xword 0x06d2d7f29e76397c | |
388 | .xword 0x234c366110eddd38 | |
389 | .xword 0xa80656d4288044bc | |
390 | .xword 0x0f59d0e1ac35dbd4 | |
391 | ||
392 | .xword 0x0f59d0e1ac35dbd4 | |
393 | .xword 0x0f59d0e1ac35dbd4 | |
394 | .xword 0x057c893bc8fc1e7e | |
395 | .xword 0xcfb9e3a29c786cc0 | |
396 | .xword 0x7257becb4609969e | |
397 | .xword 0x4b1896677e83abae | |
398 | .xword 0xc2e35a285574f037 | |
399 | .xword 0x2e42eb5835020e2e | |
400 | ||
401 | .xword 0x90775b99929f43cc | |
402 | .xword 0x9fac4ae85a4ecd4e | |
403 | .xword 0x057c893bc8fc1e7e | |
404 | .xword 0xcfb9e3a29c786cc0 | |
405 | .xword 0x7257becb4609969e | |
406 | .xword 0x4b1896677e83abae | |
407 | .xword 0xc2e35a285574f037 | |
408 | .xword 0x2e42eb5835020e2e | |
409 | ||
410 | .xword 0x90775b99929f43cc | |
411 | .xword 0x9fac4ae85a4ecd4e | |
412 | .xword 0x057c893bc8fc1e7e | |
413 | .xword 0xcfb9e3a29c786cc0 | |
414 | .xword 0x7257becb4609969e | |
415 | .xword 0x4b1896677e83abae | |
416 | .xword 0xc2e35a285574f037 | |
417 | .xword 0x2e42eb5835020e2e | |
418 | ||
419 | .xword 0x90775b99929f43cc | |
420 | .xword 0x9fac4ae85a4ecd4e | |
421 | .xword 0xfa474991f13e3460 | |
422 | .xword 0x1446415baecf3609 | |
423 | .xword 0xe3215e901114ad4b | |
424 | .xword 0xf91d897e92d1ee95 | |
425 | .xword 0x33458a48805d888b | |
426 | .xword 0x7f5a3ddb7d8e3c23 | |
427 | ||
428 | ||
429 | .xword 0xaa80311fb1e17e79 | |
430 | .xword 0x0f59d0e1ac35dbd4 | |
431 | .xword 0x057c893bc8fc1e7e | |
432 | .xword 0xcfb9e3a29c786cc0 | |
433 | .xword 0x7257becb4609969e | |
434 | .xword 0x4b1896677e83abae | |
435 | .xword 0xc2e35a285574f037 | |
436 | .xword 0x2e42eb5835020e2e | |
437 | ||
438 | .xword 0x90775b99929f43cc | |
439 | .xword 0x9fac4ae85a4ecd4e | |
440 | .xword 0x12e763fbd8e2970d | |
441 | .xword 0x7320217fab3eae0e | |
442 | .xword 0x38683cebedefb5af | |
443 | .xword 0xea22901c101f6f52 | |
444 | .xword 0x806faa2171350467 | |
445 | .xword 0xff54f2cd06a0d342 | |
446 | ||
447 | .xword 0x566bff718cddb905 | |
448 | .xword 0x6d367bc4d165d37a | |
449 | .xword 0x5efc42b18f920522 | |
450 | .xword 0x584c92dec4bc66de | |
451 | .xword 0xed9efe0d05896ce1 | |
452 | .xword 0xf9d45b94972117c8 | |
453 | .xword 0xd0c647618c9e43f3 | |
454 | .xword 0xfe04ead3b77c2d11 | |
455 | ||
456 | .xword 0x057c893bc8fc1e7e | |
457 | .xword 0x90775b99929f43cc | |
458 | .xword 0x9fac4ae85a4ecd4e | |
459 | .xword 0xfa474991f13e3460 | |
460 | .xword 0x1446415baecf3609 | |
461 | .xword 0xe3215e901114ad4b | |
462 | .xword 0xf91d897e92d1ee95 | |
463 | .xword 0x33458a48805d888b | |
464 | .xword 0x7f5a3ddb7d8e3c23 | |
465 | ||
466 | ||
467 | .xword 0xaa80311fb1e17e79 | |
468 | .xword 0x0f59d0e1ac35dbd4 | |
469 | .xword 0x057c893bc8fc1e7e | |
470 | .xword 0xcfb9e3a29c786cc0 | |
471 | .xword 0x7257becb4609969e | |
472 | .xword 0x4b1896677e83abae | |
473 | .xword 0xc2e35a285574f037 | |
474 | .xword 0x2e42eb5835020e2e | |
475 | ||
476 | .xword 0x90775b99929f43cc | |
477 | .xword 0x9fac4ae85a4ecd4e | |
478 | .xword 0x12e763fbd8e2970d | |
479 | .xword 0x7320217fab3eae0e | |
480 | .xword 0x38683cebedefb5af | |
481 | ||
482 | ||
483 | .global DATA_ACCESS_ERROR_HANDLER | |
484 | .global INST_ACCESS_ERROR_HANDLER | |
485 | .global MEM_ADDR_HANDLER | |
486 | ||
487 | SECTION .HTRAPS | |
488 | .text | |
489 | DATA_ACCESS_ERROR_HANDLER: | |
490 | add %g0, SFSR_VA, %g5 ! | |
491 | ldxa [%g5]ASI_DSFSR, %o1 ! | |
492 | cmp %o1, 0x1 | |
493 | bne FAIL | |
494 | stxa %g0, [%g5]ASI_DSFSR | |
495 | add %g0, 1, %i0 ! | |
496 | done | |
497 | nop | |
498 | ||
499 | INST_ACCESS_ERROR_HANDLER: | |
500 | add %g0, SFSR_VA, %g5 ! | |
501 | !!ldxa [%g5]ASI_ISFSR, %o1 ! | |
502 | !!cmp %o1, 0x1 | |
503 | !!bne FAIL | |
504 | add %g0, SFAR_VA, %g6 !!g6 has sfar va | |
505 | ldxa [%g6]ASI_SFAR, %o1 | |
506 | !!brnz %o1, FAIL | |
507 | rdpr %tpc, %o1 | |
508 | cmp %o1, %l4 !! cmp pc matches the expected pc | |
509 | bne FAIL | |
510 | !!issue demap pg | |
511 | srlx %o1, 0xd, %o1 | |
512 | sllx %o1, 0xd, %o1 | |
513 | stxa %g0, [%o1] ASI_IMMU_DEMAP | |
514 | add %g0, 1, %i0 ! | |
515 | retry | |
516 | MEM_ADDR_HANDLER: | |
517 | !!read the four D$ entries and inject errors | |
518 | !!D$ entry 0 | |
519 | sll %i3, 1, %g1 | |
520 | mov %g0, %g2 | |
521 | cmp %l4, 7 | |
522 | bg,a .+8 | |
523 | or %g0, 0x8, %g2 | |
524 | and %l4, 0x7, %g3 | |
525 | sll %g1, %g3, %g4 | |
526 | ||
527 | setx cache_index_data, %g5, %g6 | |
528 | ||
529 | DC_ENTRY0: | |
530 | ldx [%g6], %o1 | |
531 | stxa %o1, [%g0+%i1]ASI_DC_TAG | |
532 | ldx [%g6 +0x8], %o2 | |
533 | add %g4, %g2, %i5 | |
534 | !! inject err in way0 | |
535 | cmp %l0, 0 | |
536 | bz,a .+8 | |
537 | stxa %o2, [%i5+%i1]ASI_DC_DATA !! store data with parity err | |
538 | cmp %l0, 4 | |
539 | bz,a .+8 | |
540 | stxa %o2, [%i5+%i1]ASI_DC_DATA !! store data with parity err | |
541 | ||
542 | DC_ENTRY1: | |
543 | ||
544 | !!D$ entry 1 | |
545 | ldx [%g6 + 0x10], %o1 | |
546 | stxa %o1, [%i2 + %i1]ASI_DC_TAG | |
547 | ldx [%g6 + 0x18], %o2 | |
548 | !! inject err in way1 | |
549 | add %g4, %g2, %i5 | |
550 | add %i2, %i5, %i5 | |
551 | cmp %l0, 1 | |
552 | bz,a .+8 | |
553 | stxa %o2, [%i5+%i1]ASI_DC_DATA !! store data with parity err | |
554 | cmp %l0, 4 | |
555 | bz,a .+8 | |
556 | stxa %o2, [%i5+%i1]ASI_DC_DATA !! store data with parity err | |
557 | ||
558 | DC_ENTRY2: | |
559 | ||
560 | !!D$ entry 2 | |
561 | ldx [%g6 + 0x20], %o1 | |
562 | stxa %o1, [%i3 + %i1]ASI_DC_TAG | |
563 | ldx [%g6 + 0x28], %o2 | |
564 | add %g4, %g2, %i5 | |
565 | add %i3, %i5, %i5 | |
566 | !! inject err in way2 | |
567 | cmp %l0, 2 | |
568 | bz,a .+8 | |
569 | stxa %o2, [%i5+%i1]ASI_DC_DATA !! store data with parity err | |
570 | cmp %l0, 4 | |
571 | bz,a .+8 | |
572 | stxa %o2, [%i5+%i1]ASI_DC_DATA !! store data with parity err | |
573 | ||
574 | DC_ENTRY3: | |
575 | ||
576 | !!D$ entry 3 | |
577 | ldx [%g6 + 0x30], %o1 | |
578 | stxa %o1, [%i4 + %i1]ASI_DC_TAG | |
579 | ldx [%g6 + 0x38], %o2 | |
580 | ||
581 | add %g4, %g2, %i5 | |
582 | add %i4, %i5, %i5 | |
583 | !! inject err in way3 | |
584 | cmp %l0, 3 | |
585 | bge,a .+8 | |
586 | stxa %o2, [%i5+%i1]ASI_DC_DATA !! store data with parity err | |
587 | nop | |
588 | done | |
589 | ||
590 | HW_CORR_ERROR_HANDLER: | |
591 | RD_DESR: | |
592 | ldxa [%g0]0x4c, %o1 !! read the DESR | |
593 | mov 1, %i1 | |
594 | done | |
595 | nop | |
596 | CHL_ERRT: | |
597 | srlx %o1, 56, %o2 !! chk the err_type | |
598 | and %o2, 0x1F, %o0 | |
599 | cmp %o0, DCDP_ERR_TYPE | |
600 | bne FAIL | |
601 | CHK_S_M_BIT: | |
602 | srlx %o2, 5, %o2 !! chk s and M bit clear | |
603 | and %o2, 3, %o0 | |
604 | cmp %o0, 0 | |
605 | bne FAIL | |
606 | CHK_F_BIT: | |
607 | ||
608 | srlx %o2, 2, %o0 !! chk F bit set | |
609 | cmp %o0, 1 | |
610 | bne FAIL | |
611 | CHK_WAY: | |
612 | srlx %i1, 4, %o0 !! get the index from i1 | |
613 | and %o1, 0x3f, %o2 !! get the index | |
614 | cmp %o2, %o0 | |
615 | bne FAIL | |
616 | sra %o1, 7, %o2 !! get the way | |
617 | subcc %l0, %o2, %o0 !! in case of err in all ways, way 0 is reported. | |
618 | bz .+16 | |
619 | cmp %o0, %l0 | |
620 | bnz FAIL | |
621 | nop | |
622 | RD_DTAG0: | |
623 | mov %g0, %o2 | |
624 | ldxa [%g0+%i1]ASI_DC_TAG, %o1 | |
625 | and %o1, 0x3, %i6 | |
626 | cmp %i6, 3 | |
627 | bz,a .+8 | |
628 | add %o2, 1, %o2 | |
629 | ||
630 | RD_DTAG1: | |
631 | ldxa [%i2+%i1]ASI_DC_TAG, %o1 | |
632 | and %o1, 0x3, %i6 | |
633 | cmp %i6, 3 | |
634 | bz,a .+8 | |
635 | add %o2, 1, %o2 | |
636 | ||
637 | RD_DTAG2: | |
638 | ldxa [%i3+%i1]ASI_DC_TAG, %o1 | |
639 | and %o1, 0x3, %i6 | |
640 | cmp %i6, 3 | |
641 | bz,a .+8 | |
642 | add %o2, 1, %o2 | |
643 | ||
644 | RD_DTAG3: | |
645 | ldxa [%i4+%i1]ASI_DC_TAG, %o1 | |
646 | and %o1, 0x3, %i6 | |
647 | cmp %i6, 3 | |
648 | bz,a .+8 | |
649 | add %o2, 1, %o2 | |
650 | ||
651 | cmp %l6, %o2 !! make sure no. of valid ways equal expected data | |
652 | bne FAIL | |
653 | add %g0, 1, %i0 | |
654 | retry | |
655 | ||
656 | INVALID_ASI_HANDLER: | |
657 | done | |
658 | nop | |
659 | ||
660 | DAE_NFO_PG_HANDLER: | |
661 | setx cache_index_data, %g1, %g4 | |
662 | sll %i3, 1, %g1 | |
663 | mov %g0, %g2 | |
664 | ||
665 | ST_WAY0: | |
666 | ldxa [%g0+%i1]ASI_DC_TAG, %o1 | |
667 | sllx %o1, 1, %o1 !! move tag parity into bit 32 | |
668 | srl %o1, 1, %o1 !! make upper 32 bits 0 | |
669 | stx %o1, [%g4] | |
670 | add %g1, %g2, %i5 | |
671 | ldxa [%i5+%i1]ASI_DC_DATA, %o2 | |
672 | stx %o2, [%g4 + 0x8] | |
673 | ||
674 | srl %o1, 2, %o1 | |
675 | sllx %o1, 11, %o1 | |
676 | ||
677 | ST_WAY1: | |
678 | ldxa [%i2 + %i1]ASI_DC_TAG, %o1 | |
679 | sllx %o1, 1, %o1 !! move tag parity into bit 32 | |
680 | srl %o1, 1, %o1 !! make upper 32 bits 0 | |
681 | stx %o1, [%g4 + 0x10] | |
682 | add %g1, %g2, %i5 | |
683 | add %i2, %i5, %i5 | |
684 | ldxa [%i5 + %i1]ASI_DC_DATA, %o2 | |
685 | stx %o2, [%g4 + 0x18] | |
686 | ||
687 | srl %o1, 2, %o1 | |
688 | sllx %o1, 11, %o1 | |
689 | ||
690 | ST_WAY2: | |
691 | ldxa [%i3 + %i1]ASI_DC_TAG, %o1 | |
692 | sllx %o1, 1, %o1 !! move tag parity into bit 32 | |
693 | srl %o1, 1, %o1 !! make upper 32 bits 0 | |
694 | stx %o1, [%g4 + 0x20] | |
695 | add %g1, %g2, %i5 | |
696 | add %i3, %i5, %i5 | |
697 | ldxa [%i5 + %i1]ASI_DC_DATA, %o2 | |
698 | stx %o2, [%g4 + 0x28] | |
699 | ||
700 | srl %o1, 2, %o1 | |
701 | sllx %o1, 11, %o1 | |
702 | ||
703 | ST_WAY3: | |
704 | ldxa [%i4 + %i1]ASI_DC_TAG, %o1 | |
705 | sllx %o1, 1, %o1 !! move tag parity into bit 32 | |
706 | srl %o1, 1, %o1 !! make upper 32 bits 0 | |
707 | stx %o1, [%g4 + 0x30] | |
708 | add %g1, %g2, %i5 | |
709 | add %i4, %i5, %i5 | |
710 | ldxa [%i5 + %i1]ASI_DC_DATA, %o2 | |
711 | stx %o2, [%g4 + 0x38] | |
712 | ||
713 | srl %o1, 2, %o1 | |
714 | sllx %o1, 11, %o1 | |
715 | ||
716 | done | |
717 | nop | |
718 | ||
719 | FAIL: EXIT_BAD | |
720 | nop | |
721 | ||
722 | .data | |
723 | .align 64 | |
724 | cache_index_data: | |
725 | .xword 0 | |
726 | .xword 0 | |
727 | .xword 0 | |
728 | .xword 0 | |
729 | .xword 0 | |
730 | .xword 0 | |
731 | .xword 0 | |
732 | .xword 0 | |
733 | .xword 0 | |
734 | .xword 0 | |
735 | .xword 0 | |
736 | .xword 0 | |
737 | .xword 0 | |
738 | ||
739 | ||
740 | ||
741 |