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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / lsu / diag / err_sbdlu_fc_diag.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: err_sbdlu_fc_diag.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MY_HP_TEXT_PA 0x1050000000
39#define MY_HP_DATA_PA 0x1050001000
40
41#define ASI_PRIMARY_CONTEXT_0 0x21
42#define ASI_ITLB_DATA_IN_REG 0x54
43#define ASI_DMMU_TAG_ACCESS 0x58
44#define ASI_DTLB_DATA_IN_REG 0x5c
45#define ASI_DMMU_SFAR 0x58
46
47
48#define MY_USER_TEXT_VA000 0x7a000000
49#define MY_USER_TEXT_RA000 0x7b000000
50#define MY_USER_TEXT_PA000 0x107b000000
51#define MY_USER_TEXT_VA001 0x7a010000
52#define MY_USER_TEXT_RA001 0x7b010000
53#define MY_USER_TEXT_PA001 0x107b010000
54#define MY_USER_TEXT_VA002 0x7a020000
55#define MY_USER_TEXT_RA002 0x7b020000
56#define MY_USER_TEXT_PA002 0x107b020000
57#define MY_USER_TEXT_VA003 0x7a030000
58#define MY_USER_TEXT_RA003 0x7b030000
59#define MY_USER_TEXT_PA003 0x107b030000
60#define MY_USER_TEXT_VA004 0x7a040000
61#define MY_USER_TEXT_RA004 0x7b040000
62#define MY_USER_TEXT_PA004 0x107b040000
63#define MY_USER_TEXT_VA005 0x7a050000
64#define MY_USER_TEXT_RA005 0x7b050000
65#define MY_USER_TEXT_PA005 0x107b050000
66#define MY_USER_TEXT_VA006 0x7a060000
67#define MY_USER_TEXT_RA006 0x7b060000
68#define MY_USER_TEXT_PA006 0x107b060000
69#define MY_USER_TEXT_VA007 0x7a070000
70#define MY_USER_TEXT_RA007 0x7b070000
71#define MY_USER_TEXT_PA007 0x107b070000
72#define MY_USER_TEXT_VA008 0x7a080000
73#define MY_USER_TEXT_RA008 0x7b080000
74#define MY_USER_TEXT_PA008 0x107b080000
75
76#define MY_USER_DATA_VA000 0x6a000000
77#define MY_USER_DATA_RA000 0x6b000000
78#define MY_USER_DATA_PA000 0x106b000000
79#define MY_USER_DATA_VA001 0x6a010000
80#define MY_USER_DATA_RA001 0x6b010000
81#define MY_USER_DATA_PA001 0x106b010000
82#define MY_nc_DATA_RA001 0xb06b0a0000
83#define MY_nc_DATA_PA001 0xc06b0a0000
84#define MY_USER_DATA_VA002 0x6a020000
85#define MY_USER_DATA_RA002 0x6b020000
86#define MY_USER_DATA_PA002 0x106b020000
87#define MY_USER_DATA_VA003 0x6a030000
88#define MY_USER_DATA_RA003 0x6b030000
89#define MY_USER_DATA_PA003 0x106b030000
90#define MY_USER_DATA_VA004 0x6a040000
91#define MY_USER_DATA_RA004 0x6b040000
92#define MY_USER_DATA_PA004 0x106b040000
93#define MY_USER_DATA_VA005 0x6a050000
94#define MY_USER_DATA_RA005 0x6b050000
95#define MY_USER_DATA_PA005 0x106b050000
96#define MY_USER_DATA_VA006 0x6a060000
97#define MY_USER_DATA_RA006 0x6b060000
98#define MY_USER_DATA_PA006 0x106b060000
99#define MY_USER_DATA_VA007 0x6a070000
100#define MY_USER_DATA_RA007 0x6b070000
101#define MY_USER_DATA_PA007 0x106b070000
102#define MY_USER_DATA_VA008 0x6a080000
103#define MY_USER_DATA_RA008 0x6b080000
104#define MY_USER_DATA_PA008 0x106b080000
105#define MY_USER_DATA_VA009 0x6a090000
106#define MY_USER_DATA_RA009 0x6b090000
107#define MY_USER_DATA_PA009 0x106b090000
108
109#define IMDU_ERR_EN 0xa0000000
110#define IMTU_ERR_EN 0x90000000
111#define DMDU_ERR_EN 0x88000000
112#define DMTU_ERR_EN 0x84000000
113#define IRCU_ERR_EN 0x82000000
114#define FRCU_ERR_EN 0x81000000
115#define SCAU_ERR_EN 0x80800000
116#define TCCU_ERR_EN 0x80400000
117#define TSAU_ERR_EN 0x80200000
118#define MRAU_ERR_EN 0x80100000
119#define STAU_ERR_EN 0x80080000
120#define STDU_ERR_EN 0x80020000
121
122#define ASI_DESR 0x4c
123#define ASI_DFESR 0x4c
124#define DFESR_VA 0x8
125#define ASI_DSFSR 0x58
126#define ASI_ISFSR 0x50
127#define SFSR_VA 0x18
128#define ASI_SFAR 0x58
129#define SFAR_VA 0x20
130#define ASI_ERR_INJ 0x43
131#define ASI_CETER 0x4C
132#define CETER_VA 0x18
133#define ASI_CERER 0x4C
134#define CERER_VA 0x10
135
136#define CERER_SBDPC 0x400
137#define CETER_DHCCE 0x1000000000000000
138#define CETER_DE 0x2000000000000000
139#define CETER_PSCCE 0x4000000000000000
140#define DCVP_ERR_TYPE 0x5
141#define SBDPC_ERR_TYPE 0x5
142#define SBDPU_ERR_TYPE 0x6
143#define HPRIV 0x5
144#define PRIV 0x3
145#define USER 0x0
146#define DCL2ND_ERR_TYPE 0x2
147#define CETER_ALL 0x7000000000000000
148
149
150#define MAIN_PAGE_HV_ALSO
151#define H_HT0_Mem_Address_Not_Aligned_0x34
152#define My_HT0_Mem_Address_Not_Aligned_0x34 \
153 ba MEM_ADDR_HANDLER; \
154 nop;nop;nop;nop;nop;nop;nop
155
156
157#define H_HT0_Data_Access_MMU_Error_0x72
158#define SUN_H_HT0_Data_Access_MMU_Error_0x72 \
159 ba DATA_ACCESS_ERROR_HANDLER; \
160 nop;nop;nop;nop;nop;nop;nop
161
162#define H_HT0_Instruction_Access_MMU_Error_0x71
163#define SUN_H_HT0_Instruction_Access_MMU_Error_0x71 \
164 ba INST_ACCESS_ERROR_HANDLER; \
165 nop;nop;nop;nop;nop;nop;nop
166
167#define H_HT0_Hw_Corrected_Error_0x63
168#define SUN_H_HT0_Hw_Corrected_Error_0x63 \
169 ba HW_CORR_ERROR_HANDLER; \
170 nop;nop;nop;nop;nop;nop;nop
171
172#define H_HT0_DAE_invalid_asi_0x14
173#define SUN_H_HT0_DAE_invalid_asi_0x14 \
174 ba INVALID_ASI_HANDLER; \
175 nop;nop;nop;nop;nop;nop;nop
176
177!! turn off cerer.dcvp
178#define H_HT0_DAE_nc_page_0x16
179#define SUN_H_HT0_DAE_nc_page_0x16 \
180 add %g0, CERER_VA, %g3;\
181 stxa %g0, [%g3]ASI_CERER;\
182 done;nop;nop;nop;nop;nop
183
184!! turn on cerer.dcvp
185#define H_HT0_Privileged_Action_0x37
186#define My_HT0_Privileged_Action_0x37 \
187 set 0x04000, %g1; \
188 add %g0, CERER_VA, %g3;\
189 stxa %g1, [%g3]ASI_CERER;\
190 done;nop;nop;nop;nop
191
192#define H_HT0_Stdf_Mem_Address_Not_Aligned_0x36
193#define My_HT0_Stdf_Mem_Address_Not_Aligned_0x36 \
194 set STDU_ERR_EN, %g1;\
195 or %g1, %l3, %g1 ;\
196 cmp %i3, 1; \
197 be,a .+12; \
198 stxa %g1, [%g0]ASI_ERR_INJ ;\
199 stxa %g0, [%g0]ASI_ERR_INJ ;\
200 done
201
202#define H_HT0_Data_access_error_0x32
203#define SUN_H_HT0_Data_access_error_0x32 \
204 ba DATA_ACCESS_ERROR_HANDLER; \
205 nop;nop;nop;nop;nop;nop;nop
206
207#define H_HT0_Sw_Recoverable_Error_0x40
208#define SUN_H_HT0_Sw_Recoverable_Error_0x40 \
209 ba RECOVERABLE_ERR_HANDLER; \
210 nop;nop;nop;nop;nop;nop;nop
211
212
213#define H_HT0_Internal_Processor_Error_0x29
214#define SUN_H_HT0_Internal_Processor_Error_0x29 \
215 ba INT_PROC_ERR_HANDLER; \
216 nop;nop;nop;nop;nop;nop;nop
217
218#include "hboot.s"
219
220/************************************************************************
221 Test case:
222 ************************************************************************/
223
224.text
225.global main
226
227main: /* test begin */
228 ta T_CHANGE_HPRIV
229
230 !! set CERER.SBDPU
231 setx 0x1f000000200, %g1, %o2 !! enable sbdpu, sbdlu errs
232 add %g0, CERER_VA, %g3 !!g3 has cerer va
233
234 stxa %o2, [%g3]ASI_CERER
235
236 !! set all bits in the ceter
237 setx CETER_ALL, %l0, %o2
238 add %g0, CETER_VA, %g3
239 stxa %o2, [%g3]ASI_CETER
240
241!!set nceen to enable nd detection
242 !! set NCEEN in l2 err enable reg
243set_nccen_l2:
244 mov 0xaa, %g1
245 sllx %g1, 32, %g1
246 mov 0x2, %g2
247 stx %g2, [%g1]
248 stx %g2, [%g1+0x40]
249 stx %g2, [%g1+0x80]
250 stx %g2, [%g1+0xc0]
251 stx %g2, [%g1+0x100]
252 stx %g2, [%g1+0x140]
253 stx %g2, [%g1+0x180]
254 stx %g2, [%g1+0x1c0]
255
256 ta T_CHANGE_NONHPRIV
257
258 setx user_code_begin_000, %g2, %g3
259 !setx user_code_begin_001, %g2, %g3
260 jmp %g3
261 nop
262 EXIT_BAD
263
264
265/************************************************************************
266 Test case data start
267 ************************************************************************/
268.data
269.global user_data_start
270user_data_start:
271.word 0x12345678
272.word 0x9a9b9c9d
273.word 0x00000000
274.word 0xffffffff
275
276!#***********************************************************************
277
278SECTION .My_User_Section_4v000 TEXT_VA=MY_USER_TEXT_VA000, DATA_VA=MY_USER_DATA_VA000
279attr_text {
280 Name = .My_User_Section_4v000,
281 part_0_ctx_nonzero_tsb_config_2,
282 VA = MY_USER_TEXT_VA000,
283 RA = MY_USER_TEXT_RA000,
284 PA = ra2pa(MY_USER_TEXT_RA000, 0),
285 TTE_Context = PCONTEXT,
286 TTE_V = 1,
287 TTE_NFO = 0,
288 TTE_L = 0,
289 TTE_Soft = 0,
290 TTE_IE = 0,
291 TTE_E = 0,
292 TTE_CP = 1,
293 TTE_CV = 0,
294 TTE_P = 0,
295 TTE_EP = 1,
296 TTE_W = 0,
297 TTE_SW1 = 0,
298 TTE_SW0 = 0,
299 TTE_RSVD1 = 0,
300 TTE_Size = 0,
301 }
302attr_text {
303NAME = .My_User_Section_4v000,
304 hypervisor
305}
306!! STb has only 7 bits of ecc. So, Flipping bit 7 of
307!! the ecc mask has no effect and is not changed.
308!! Try all possible 2 bit combinations of errors in ecc bits.
309!! combinations of bits tried:70 (70 means bits 7 and 0 are asserted together)
310!! With bit 0 = 1: 60, 50, 40, 30, 20, 10 => 7 cases
311!! With bit 1 = 1: 61, 51, 41, 31, 21 => 6 cases
312!! With bit 2 = 1: 62, 52, 42, 32 => 5 cases
313!! With bit 3 = 1: 63, 53, 43 => 4 cases
314!! With bit 4 = 1: 64, 54 => 3 cases
315!! With bit 5 = 1: 65 => 2 cases
316
317.text
318.global user_code_begin_000
319user_code_begin_000:
320 mov %g0, %l2 !! stb expected index is in l2
321 mov %g0, %i4 !! don't need to clear the err in the sw trap handler
322 add %g0, 3, %l3
323 add %g0, 1, %i3 !! enable err_injection
324 add %g0, USER, %i6
325
326 std %d0, [%l4 + 0x4] !stdf_not_aligned
327 ldxa [%l4]0xE4, %g1 !! invalid asi trap to set to stb ptr to 0
328
329 setx user_data_begin_000, %g1, %l4
330 setx user_data_begin_001, %g1, %l5
331
332 ldx [%l4], %o4 !pg lookup
333 ldx [%l5], %o5 !pg lookup
334!!IPE and SWE trap on an stb ue
335!! generate a stb ue error which causes both an sbdlu and sbdpu.
336!! the ld which causes sbdlu is a hit in the L1$ so we don't see a dae when
337!!ld is replayed.
338CASE0:
339 mov %g0, %i0 !! ipe tracker due to sbdlu
340 mov %g0, %i1 !! swe tracker due to sbdpu
341 mov %g0, %i2 !!dae tracker
342 !add %l4, 0x10, %l4
343 !add %l5, 0x10, %l5
344
345 stx %o5, [%l4] !! UE
346 ldx [%l4], %o4 !! ld is a hit in the cache so no data_acc_err trap
347 !! on retry from sw_recoverable_err handler
348 add %o5, 0x100, %o5
349 brz %i0, FAIL
350 brz %i1, FAIL
351 brnz %i2, FAIL
352 nop
353
354!!IPE, SWE, and DAE trap on an stb ue
355!! generate a stb ue error which causes both an sbdlu and sbdpu.
356!! the ld which causes sbdlu is a miss in the L1$ so we see a dae when
357!!ld is replayed.
358
359CASE1:
360 add %g0, 3, %l3
361 add %g0, 1, %i3 !! enable err_injection
362 add %g0, USER, %i6
363
364 std %d0, [%l4 + 0x4] !stdf_not_aligned
365 ldxa [%l4]0xE4, %g1 !! invalid asi trap to set to stb ptr to 0
366
367 setx user_data_begin_000, %g1, %l4
368 setx user_data_begin_001, %g1, %l5
369
370 mov %g0, %i0 !! ipe tracker
371 mov %g0, %i1 !! swe tracker
372 mov %g0, %i2 !!dae tracker
373
374 stx %o5, [%l4 + 0x10] !!ue
375 ldx [%l4 + 0x10], %o4 !! ld is a cache miss in the cache so data_acc_err trap
376 !! on retry from sw_recoverable_err handler
377 brz %i0, FAIL
378 brz %i1, FAIL
379 brz %i2, FAIL
380 nop
381
382!!SWE, and DAE trap on an stb ue
383!!These case has 4 back to back stores all of which get ues.
384!!There are loads to these stores later on and all of them get daes
385CASE2:
386 add %g0, 3, %l3
387 add %g0, 1, %i3 !! enable err_injection
388 add %g0, USER, %i6
389
390 std %d0, [%l4 + 0x4] !stdf_not_aligned
391 ldxa [%l4]0xE4, %g1 !! invalid asi trap to set to stb ptr to 0
392
393 setx user_data_begin_000, %g1, %l4
394 setx user_data_begin_001, %g1, %l5
395
396 mov %g0, %i0 !! ipe tracker
397 mov %g0, %i1 !! swe tracker
398 mov %g0, %i2 !!dae tracker
399
400 stx %o5, [%l4 + 0x20] !!ue
401 stx %o5, [%l4 + 0x30] !!ue
402 stx %o5, [%l4 + 0x40] !!ue
403 stx %o5, [%l4 + 0x50] !!ue
404
405 ldx [%l4 + 0x60], %o4 !!
406 ldx [%l4 + 0x70], %o4 !!
407
408 brz %i1, FAIL
409 mov %g0, %i1
410
411 ldx [%l4 + 0x20], %o1 !!
412 brz %i2, FAIL
413 mov %g0, %i2
414 ldx [%l4 + 0x30], %o2 !!
415 brz %i2, FAIL
416 mov %g0, %i2
417 ldx [%l4 + 0x40], %o3 !!
418 brz %i2, FAIL
419 mov %g0, %i2
420 ldx [%l4 + 0x50], %o4 !!
421 brz %i2, FAIL
422 mov %g0, %i2
423
424!!SWE trap on an stb ue
425!!These case has 4 back to back stores all of which get ues.
426!!In the swe trap handler the stores are rewritten which clears the err
427!!in L2$.
428!!There are loads to these stores later on and none of them shd get dae
429!!as the err has been cleared in L2$.
430
431CASE3:
432 add %g0, 3, %l3
433 add %g0, 1, %i3 !! enable err_injection
434 mov 1, %i4 !! clear the err in the sw_trap_handler
435
436 std %d0, [%l4 + 0x4] !stdf_not_aligned
437 ldxa [%l4]0xE4, %g1 !! invalid asi trap to set to stb ptr to 0
438
439 setx user_data_begin_000, %g1, %l4
440
441 mov %g0, %i0 !! ipe tracker
442 mov %g0, %i1 !! swe tracker
443 mov %g0, %i2 !!dae tracker
444
445 add %o4, 0x1fff, %o1
446 xor %o4, %o1, %o2
447 and %o2, %o5, %o3
448 xor %l4, %o5, %o4
449
450 stx %o1, [%l4 + 0x60] !!hit in L1$
451 stx %o2, [%l4 + 0x70] !!hit in L1$
452 stx %o3, [%l4 + 0x90] !!miss in L1$
453 stx %o4, [%l4 + 0xa0] !!miss in L1$
454
455 ldx [%l5 + 0x30], %o5 !!
456 ldx [%l5 + 0x40], %o5 !!
457 ldx [%l5 + 0x50], %o5 !!
458
459 brz %i1, FAIL
460 mov %g0, %i1
461
462 ldx [%l4 + 0x60], %g1
463 brnz %i2, FAIL
464 cmp %g1, %o1
465 bne FAIL
466 ldx [%l4 + 0x70], %g2
467 brnz %i2, FAIL
468 cmp %g2, %o2
469 bne FAIL
470 ldx [%l4 + 0x90], %g3
471 brnz %i2, FAIL
472 cmp %g3, %o3
473 bne FAIL
474 ldx [%l4 + 0xa0], %g4
475 brnz %i2, FAIL
476 cmp %g4, %o4
477 bne FAIL
478
479 EXIT_GOOD
480 nop
481
482FAIL:
483 EXIT_BAD
484
485attr_data {
486 Name = .My_User_Section_4v000,
487 part_0_ctx_nonzero_tsb_config_1,
488 VA = MY_USER_DATA_VA000,
489 RA = MY_USER_DATA_RA000,
490 PA = ra2pa(MY_USER_DATA_RA000, 0),
491 TTE_Context = PCONTEXT,
492 TTE_V = 1,
493 TTE_NFO = 0,
494 TTE_L = 0,
495 TTE_Soft = 0,
496 TTE_IE = 0,
497 TTE_E = 0,
498 TTE_CP = 1,
499 TTE_CV = 0,
500 TTE_P = 0,
501 TTE_EP = 0,
502 TTE_W = 1,
503 TTE_SW1 = 0,
504 TTE_SW0 = 0,
505 TTE_RSVD1 = 0,
506 TTE_Size = 0,
507 }
508attr_data {
509NAME = .My_User_Section_4v000,
510 hypervisor
511}
512.data
513.global user_data_begin_000
514user_data_begin_000:
515.xword 0xe0066361bd9fcb86
516.xword 0xea22901c101f6f52
517.xword 0x806faa2171350467
518.xword 0xff54f2cd06a0d342
519.xword 0x566bff718cddb905
520.xword 0x6d367bc4d165d37a
521.xword 0x5efc42b18f920522
522.xword 0x584c92dec4bc66de
523.xword 0xed9efe0d05896ce1
524.xword 0xf9d45b94972117c8
525.xword 0xd0c647618c9e43f3
526.xword 0xfe04ead3b77c2d11
527.xword 0x06d2d7f29e76397c
528.xword 0x234c366110eddd38
529.xword 0xa80656d4288044bc
530.xword 0x12e763fbd8e2970d
531.xword 0x7320217fab3eae0e
532.xword 0x38683cebedefb5af
533.xword 0xefc4e1f1b35853fc
534.xword 0xe790a0c1689eb683
535.xword 0x88c650f170c41710
536.xword 0x614126cf9fc8dca3
537.xword 0x4be2f60911e465ce
538.xword 0x4e22352a0c29c95c
539.xword 0xf18efdf01ce79e24
540.xword 0x294aaa56144d7cf1
541.xword 0xe0066361bd9fcb86
542.xword 0xea22901c101f6f52
543.xword 0x806faa2171350467
544.xword 0xff54f2cd06a0d342
545.xword 0x566bff718cddb905
546.xword 0x6d367bc4d165d37a
547.xword 0x5efc42b18f920522
548.xword 0x584c92dec4bc66de
549.xword 0xefc4e1f1b35853fc
550.xword 0xe790a0c1689eb683
551.xword 0x88c650f170c41710
552.xword 0x614126cf9fc8dca3
553.xword 0x5efc42b18f920522
554.xword 0x584c92dec4bc66de
555.xword 0xed9efe0d05896ce1
556.xword 0xf9d45b94972117c8
557.xword 0xd0c647618c9e43f3
558.xword 0xfe04ead3b77c2d11
559.xword 0x06d2d7f29e76397c
560.xword 0x234c366110eddd38
561.xword 0xa80656d4288044bc
562.xword 0x12e763fbd8e2970d
563.xword 0x7320217fab3eae0e
564.xword 0x38683cebedefb5af
565.xword 0xefc4e1f1b35853fc
566.xword 0xe790a0c1689eb683
567.xword 0x88c650f170c41710
568
569
570SECTION .My_User_Section_4v001 TEXT_VA=MY_USER_TEXT_VA001, DATA_VA=MY_USER_DATA_VA001
571attr_text {
572 Name = .My_User_Section_4v001,
573 part_0_ctx_nonzero_tsb_config_2,
574 VA = MY_USER_TEXT_VA001,
575 RA = MY_USER_TEXT_RA001,
576 PA = ra2pa(MY_USER_TEXT_RA001, 0),
577 TTE_Context = PCONTEXT,
578 TTE_V = 1,
579 TTE_NFO = 0,
580 TTE_L = 0,
581 TTE_Soft = 0,
582 TTE_IE = 0,
583 TTE_E = 0,
584 TTE_CP = 1,
585 TTE_CV = 0,
586 TTE_P = 0,
587 TTE_EP = 1,
588 TTE_W = 0,
589 TTE_SW1 = 0,
590 TTE_SW0 = 0,
591 TTE_RSVD1 = 0,
592 TTE_Size = 0,
593 }
594attr_text {
595NAME = .My_User_Section_4v001,
596 hypervisor
597}
598! Check, if CETER.DE is clear then no trap is taken.
599! After that once CETER.DE is set, trap will be taken.
600
601.text
602.global user_code_begin_001
603user_code_begin_001:
604 EXIT_GOOD
605 nop
606
607attr_data {
608 Name = .My_User_Section_4v001,
609 part_0_ctx_nonzero_tsb_config_1,
610 VA = MY_USER_DATA_VA001,
611 RA = MY_USER_DATA_RA001,
612 PA = ra2pa(MY_USER_DATA_RA001, 0),
613 TTE_Context = PCONTEXT,
614 TTE_V = 1,
615 TTE_NFO = 0,
616 TTE_L = 0,
617 TTE_Soft = 0,
618 TTE_IE = 0,
619 TTE_E = 0,
620 TTE_CP = 1,
621 TTE_CV = 1,
622 TTE_P = 0,
623 TTE_EP = 0,
624 TTE_W = 1,
625 TTE_SW1 = 0,
626 TTE_SW0 = 0,
627 TTE_RSVD1 = 0,
628 TTE_Size = 0,
629 }
630attr_data {
631NAME = .My_User_Section_4v001,
632 hypervisor
633}
634.data
635.global user_data_begin_001
636user_data_begin_001:
637.xword 0xfa474991f13e3460
638.xword 0x1446415baecf3609
639.xword 0xe3215e901114ad4b
640.xword 0xf91d897e92d1ee95
641.xword 0x33458a48805d888b
642.xword 0x7f5a3ddb7d8e3c23
643.xword 0xaa80311fb1e17e79
644.xword 0x0f59d0e1ac35dbd4
645.xword 0x057c893bc8fc1e7e
646.xword 0xcfb9e3a29c786cc0
647.xword 0x7257becb4609969e
648.xword 0x4b1896677e83abae
649.xword 0xc2e35a285574f037
650.xword 0x2e42eb5835020e2e
651.xword 0x90775b99929f43cc
652.xword 0xd0c647618c9e43f3
653.xword 0xfe04ead3b77c2d11
654.xword 0x06d2d7f29e76397c
655.xword 0x234c366110eddd38
656.xword 0xa80656d4288044bc
657.xword 0x12e763fbd8e2970d
658.xword 0x7320217fab3eae0e
659.xword 0x38683cebedefb5af
660.xword 0xefc4e1f1b35853fc
661.xword 0xe790a0c1689eb683
662.xword 0x9fac4ae85a4ecd4e
663
664 .word 0x10731
665 .word 0xd027
666 .word 0x1350e
667 .word 0x10e9d
668
669
670
671.global DATA_ACCESS_ERROR_HANDLER
672.global INST_ACCESS_ERROR_HANDLER
673.global MEM_ADDR_HANDLER
674.global RECOVERABLE_ERR_HANDLER
675.global INT_PROC_ERR_HANDLER
676
677SECTION .HTRAPS
678.text
679DATA_ACCESS_ERROR_HANDLER:
680 add %g0, SFSR_VA, %g5 !
681 ldxa [%g5]ASI_DSFSR, %o1 !
682 stxa %g0, [%g5]ASI_DSFSR ! clear the err
683 add %g0, 1, %i2
684 done
685 nop
686
687INST_ACCESS_ERROR_HANDLER:
688 add %g0, SFSR_VA, %g5 !
689 !!ldxa [%g5]ASI_ISFSR, %o1 !
690 !!cmp %o1, 0x1
691 !!bne FAIL
692 add %g0, SFAR_VA, %g6 !!g6 has sfar va
693 ldxa [%g6]ASI_SFAR, %o1
694 !!brnz %o1, FAIL
695 rdpr %tpc, %o1
696 cmp %o1, %l4 !! cmp pc matches the expected pc
697 bne FAIL
698 !!issue demap pg
699 srlx %o1, 0xd, %o1
700 sllx %o1, 0xd, %o1
701 stxa %g0, [%o1] ASI_IMMU_DEMAP
702 add %g0, 1, %i0 !
703 retry
704
705MEM_ADDR_HANDLER:
706 done
707 nop
708
709HW_CORR_ERROR_HANDLER:
710 ldxa [%g0]0x4c, %g1 !! read the DESR
711 ldxa [%g0]0x4c, %g2 !! g2 shd be 0.
712 retry
713 nop
714
715INVALID_ASI_HANDLER:
716 set STDU_ERR_EN, %g1
717 or %g1, %l3, %g1
718
719 add %g0, 0x100, %g3 !! read the stb ptr
720 ldxa [%g3]ASI_STB_ACCESS, %g2
721 !srlx %g2, 3, %g2
722 brz %g2, DONE
723 cmp %g2, 1
724 be STORES_7
725 cmp %g2, 2
726 be STORES_6
727 cmp %g2, 3
728 be STORES_5
729 cmp %g2, 4
730 be STORES_4
731 cmp %g2, 5
732 be STORES_3
733 cmp %g2, 6
734 be STORES_2
735 cmp %g2, 7
736 be,a DONE
737STORES_7:
738 stxa %g1, [%g0]ASI_ERR_INJ ! no err injected on wr to err inj
739STORES_6:
740 stxa %g1, [%g0]ASI_ERR_INJ ! no err injected on wr to err inj
741STORES_5:
742 stxa %g1, [%g0]ASI_ERR_INJ ! no err injected on wr to err inj
743STORES_4:
744 stxa %g1, [%g0]ASI_ERR_INJ ! no err injected on wr to err inj
745STORES_3:
746 stxa %g1, [%g0]ASI_ERR_INJ ! no err injected on wr to err inj
747STORES_2:
748 stxa %g1, [%g0]ASI_ERR_INJ ! no err injected on wr to err inj
749 stxa %g1, [%g0]ASI_ERR_INJ ! no err injected on wr to err inj
750
751DONE:
752 done
753 nop
754
755RECOVERABLE_ERR_HANDLER:
756stxa %g0, [%g0]ASI_ERR_INJ !! turn off err injection
757 ldxa [%g0]0x4c, %g1 !! read the DESR
758 ldxa [%g0]0x4c, %g2 !! g2 shd be 0.
759CHK_ERRT:
760 srlx %g1, 56, %g2 !! chk the err_type
761 and %g2, 0x1F, %g3
762 cmp %g3, SBDPU_ERR_TYPE
763 !bne FAIL
764CHK_S_BIT:
765 srlx %g2, 5, %g2 !! chk s bit
766 and %g2, 1, %g3
767 cmp %g3, 1
768 !bne FAIL
769CHK_F_BIT:
770 srlx %g2, 2, %g3 !! chk F bit set
771 cmp %g3, 1
772 !bne FAIL
773CHK_WAY:
774 and %g1, 0x7, %g2 !! SB index
775 cmp %g2, %l2
776 !bne FAIL
777 nop
778
779 brz %i4, RET !!if i4 is 1 then clear the err in the trap handler.
780 nop
781CLR_ERR:
782 mov %l4, %l5
783 add %l5, 0x60, %l5
784 stxa %o1, [%l5]0x10
785 add %l5, 0x10, %l5
786 stxa %o2, [%l5]0x10
787 add %l5, 0x20, %l5
788 stxa %o3, [%l5]0x10
789 add %l5, 0x10, %l5
790 stxa %o4, [%l5]0x10
791 membar #Sync
792RET: add %g0, 1, %i1
793 retry
794
795
796INT_PROC_ERR_HANDLER:
797CHK_ERR_TYP:
798 stxa %g0, [%g0]ASI_ERR_INJ
799 add %g0, SFSR_VA, %g1
800 ldxa [%g1]ASI_DSFSR, %g2 !! read the DSFSR
801 stxa %g0, [%g1]ASI_DSFSR !! clear the dsfsr
802 and %g2, 0xF, %g2
803 !cmp %g2, SBDLC_ERR_TYPE
804 !bne FAIL
805CHK_INDEX:
806 add %g0, SFAR_VA, %g1
807 ldxa [%g1]ASI_SFAR, %g2 !! read the DSFAR
808 and %g2, 0x7, %g2
809 !cmp %g2, %l2
810 !bne FAIL
811 nop
812
813 membar #Sync
814 add %g0, 1, %i0
815 retry
816
817FAIL: EXIT_BAD
818 nop
819
820.data
821
822
823
824
Full OpenSPARC design & verification tarball including full HDL.