[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / pmu / diag / ovBitTest.pal

# 1 "pmu_sl4_mask_n2.pal" 

:#define MAIN_PAGE_NUCLEUS_ALSO
:#define MAIN_PAGE_HV_ALSO
:#define DMMU_SKIP_IF_NO_TTE
 
:#include "hboot.s"

:


:.text
:.global main

:main:		


:! Thread 0 Start

:!main_t0:

:	setx	0x0000000080040030, %i0, %l0 ! Write    value
:       setx    0x0000000080040030, %i0, %l1 ! Expected value
:       setx    0x0000000000000000, %i0, %l2
:       setx    0x0000000000000000, %i0, %l3 ! Second expected value
:       setx    0x8000000080040030, %i0, %l4 ! Should update Ov0, but not Ov1
:       setx    0x0000000000040030, %i0, %l5 ! Expected value
:       setx    0x4000000080000030, %i0, %l6 ! Should update Ov1, but not Ov0
:       setx    0x0000000080000030, %i0, %l7 ! Expectd Value
:       setx    0xC000000080040030, %i0, %i5 ! Should update neither
:       setx    0x0000000000000030, %i0, %i6 ! Expected Value
:       setx    0xC000000000000000, %i0, %i3 ! Make sure a write doesn't off them
:       setx    0x0000000080040000, %i0, %i4 ! Expected Value
:       setx    0xFFFFFFFFFFFFFFFF, %i0, %g3 ! make sure it doesn't affect bits
:       setx    0x000000007FFBFFFF, %i0, %g4 ! Expected

:	! Execute Main Diag ..
:	ta T_CHANGE_HPRIV            ! Should cause Watchdog_reset trap
	

:!Count_ITLB_References:	
	
:	wr 	%l0, %g0, %pcr 	 !  Write the PCR and overflow bits
:       rd      %pcr, %i0        !
:	xor 	%l1, %i0, %i1    !  see if the expected read, compares
:                                !  compares to the actual read
:       brnz    %i1, fail
:       rd      %pcr, %i2       ! Read it again to make sure the OV bits
:                                ! were not cleared
:       xor     %i2,  %l1, %i1
:       brnz    %i1,  fail

:       wr      %i3, %g0, %pcr   !  Now try to clear it with the 63,62 on
:       rd      %pcr, %i0        !  Read it back, they should still be set
:       xor     %i4,  %i0, %i1   
:       brnz    %i1, fail

:	wr 	%l2, %g0, %pcr 	 !  Write the PCR and clear the overflow bits
:       wr      %g3, %g0, %pcr   !  Now try to write all bits with the 63,62 on
:       rd      %pcr, %i0        !  Read it back, they should still be set
:       xor     %g4,  %i0, %i1   
:       brnz    %i1, fail


:	wr 	%l2, %g0, %pcr 	 !  Write the PCR and clear the overflow bits
:       rd      %pcr, %i0        !
:	xor 	%31, %i0, %i1    !  see if the expected read, compares
:                                !  compares to the actual read       
:       brnz    %i1, fail
:       rd      %pcr, %i2       ! Read it again to make sure the OV bits
:                                ! were not cleared
:       ! Testing Ov1 Off, Ov0 on
:	wr 	%l2, %g0, %pcr 	 !  Clear the PCR
:	wr 	%l4, %g0, %pcr 	 !  Write the PCR and overflow bits
:       rd      %pcr, %i0        !
:	xor 	%l5, %i0, %i1    !  see if the expected read, compares
:                                !  compares to the actual read
:       brnz    %i1, fail

:       ! Testing Ov0 Off, Ov1 on
:	wr 	%l2, %g0, %pcr 	 !  Clear the PCR
:	wr 	%l6, %g0, %pcr 	 !  Write the PCR and overflow bits
:       rd      %pcr, %i0        !
:	xor 	%l7, %i0, %i1    !  see if the expected read, compares
:                                !  compares to the actual read
:       brnz    %i1, fail

:       ! Testing both off
:	wr 	%l2, %g0, %pcr 	 !  Clear the PCR
:	wr 	%i5, %g0, %pcr 	 !  Write the PCR and overflow bits
:       rd      %pcr, %i0        !
:	xor 	%i6, %i0, %i1    !  see if the expected read, compares
:                                !  compares to the actual read
:       brnz    %i1, fail

:     nop
:     nop
:     nop
:     nop
:     nop
:     EXIT_GOOD
:     nop
:     nop
:     nop
:     nop

                          	
:fail:
:	EXIT_BAD
Commit	Line	Data
86530b38 AT	1	# 1 "pmu_sl4_mask_n2.pal"
	2
	3	:#define MAIN_PAGE_NUCLEUS_ALSO
	4	:#define MAIN_PAGE_HV_ALSO
	5	:#define DMMU_SKIP_IF_NO_TTE
	6
	7	:#include "hboot.s"
	8
	9	:
	10
	11
	12
	13	:.text
	14	:.global main
	15
	16	:main:
	17
	18
	19	:! Thread 0 Start
	20
	21	:!main_t0:
	22
	23	: setx 0x0000000080040030, %i0, %l0 ! Write value
	24	: setx 0x0000000080040030, %i0, %l1 ! Expected value
	25	: setx 0x0000000000000000, %i0, %l2
	26	: setx 0x0000000000000000, %i0, %l3 ! Second expected value
	27	: setx 0x8000000080040030, %i0, %l4 ! Should update Ov0, but not Ov1
	28	: setx 0x0000000000040030, %i0, %l5 ! Expected value
	29	: setx 0x4000000080000030, %i0, %l6 ! Should update Ov1, but not Ov0
	30	: setx 0x0000000080000030, %i0, %l7 ! Expectd Value
	31	: setx 0xC000000080040030, %i0, %i5 ! Should update neither
	32	: setx 0x0000000000000030, %i0, %i6 ! Expected Value
	33	: setx 0xC000000000000000, %i0, %i3 ! Make sure a write doesn't off them
	34	: setx 0x0000000080040000, %i0, %i4 ! Expected Value
	35	: setx 0xFFFFFFFFFFFFFFFF, %i0, %g3 ! make sure it doesn't affect bits
	36	: setx 0x000000007FFBFFFF, %i0, %g4 ! Expected
	37
	38	: ! Execute Main Diag ..
	39	: ta T_CHANGE_HPRIV ! Should cause Watchdog_reset trap
	40
	41
	42	:!Count_ITLB_References:
	43
	44	: wr %l0, %g0, %pcr ! Write the PCR and overflow bits
	45	: rd %pcr, %i0 !
	46	: xor %l1, %i0, %i1 ! see if the expected read, compares
	47	: ! compares to the actual read
	48	: brnz %i1, fail
	49	: rd %pcr, %i2 ! Read it again to make sure the OV bits
	50	: ! were not cleared
	51	: xor %i2, %l1, %i1
	52	: brnz %i1, fail
	53
	54	: wr %i3, %g0, %pcr ! Now try to clear it with the 63,62 on
	55	: rd %pcr, %i0 ! Read it back, they should still be set
	56	: xor %i4, %i0, %i1
	57	: brnz %i1, fail
	58
	59	: wr %l2, %g0, %pcr ! Write the PCR and clear the overflow bits
	60	: wr %g3, %g0, %pcr ! Now try to write all bits with the 63,62 on
	61	: rd %pcr, %i0 ! Read it back, they should still be set
	62	: xor %g4, %i0, %i1
	63	: brnz %i1, fail
	64
65
66	: wr %l2, %g0, %pcr ! Write the PCR and clear the overflow bits
67	: rd %pcr, %i0 !
68	: xor %31, %i0, %i1 ! see if the expected read, compares
69	: ! compares to the actual read
70	: brnz %i1, fail
71	: rd %pcr, %i2 ! Read it again to make sure the OV bits
72	: ! were not cleared
73	: ! Testing Ov1 Off, Ov0 on
74	: wr %l2, %g0, %pcr ! Clear the PCR
75	: wr %l4, %g0, %pcr ! Write the PCR and overflow bits
76	: rd %pcr, %i0 !
77	: xor %l5, %i0, %i1 ! see if the expected read, compares
78	: ! compares to the actual read
79	: brnz %i1, fail
80
81	: ! Testing Ov0 Off, Ov1 on
82	: wr %l2, %g0, %pcr ! Clear the PCR
83	: wr %l6, %g0, %pcr ! Write the PCR and overflow bits
84	: rd %pcr, %i0 !
85	: xor %l7, %i0, %i1 ! see if the expected read, compares
86	: ! compares to the actual read
87	: brnz %i1, fail
88
89	: ! Testing both off
90	: wr %l2, %g0, %pcr ! Clear the PCR
91	: wr %i5, %g0, %pcr ! Write the PCR and overflow bits
92	: rd %pcr, %i0 !
93	: xor %i6, %i0, %i1 ! see if the expected read, compares
94	: ! compares to the actual read
95	: brnz %i1, fail
96
97	: nop
98	: nop
99	: nop
100	: nop
101	: nop
102	: EXIT_GOOD
103	: nop
104	: nop
105	: nop
106	: nop
107
108
109	:fail:
110	: EXIT_BAD
111
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114