[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / pmu / diag / pmu_ccx_sel5_0x01_thAll.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: pmu_ccx_sel5_0x01_thAll.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define PIC_COUNT 1

#define MAX_THREAD_TIMEOUT 0x1fff
#define MAIN_PAGE_HV_ALSO
#define NO_TRAPCHECK
#define H_HT0_Control_Word_Queue_Interrupt_0x3c
#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
  wr %g0, 0x40, %asi; \
  ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %i5; \
  stxa %i5, [%g0 + ASI_SPU_CWQ_CSR] %asi; \
  ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %i5; \
  and %i5, 0x10, %i5; \
  brnz %i5, FAIL; \
  nop; \
  ba CHECK_PIC_COUNT; \
  nop;nop;

#include "hboot.s"

.text
.global main

main:       

   and %g0,0,%i6
   
   setx 0x0000deadbeefbad0, %l5, %l4

   !# Switch to hpriv mode
   ta T_CHANGE_HPRIV
   !# Check to make sure pic is zero
   !#rd  %pic,   %g4
   !#cmp %g0,    %g4
   !#bne,pn  %icc,   fail
   !#nop
   wr  %g0, %g0, %pic !zero out pic

   !# Setup PCR Register
   set 0x000000002809C048, %g2
   wr  %g2, %g0, %pcr
   wr  %g0, %g0, %pic !zero out pic

   !Get TID
   ta T_RD_THID
   mov %o1, %l6
   nop

   cmp %l6, 0
   be thread_0
   nop

   cmp %l6, 1
   be thread_other
   nop

   !all other threads execute the same code
   cmp %l6, 2
   be thread_other
   nop

   cmp %l6, 3
   be thread_other
   nop

   cmp %l6, 4
   be thread_other
   nop

   cmp %l6, 5
   be thread_other
   nop

   cmp %l6, 6
   be thread_other
   nop

   cmp %l6, 7
   be thread_other
   nop

   ba fail

thread_0:
   !# setup ASI register to point to SPU
   wr %g0, 0x40, %asi

InitialCW_0:

   !# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
   ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
   and %l1, 0xf, %l2
   cmp %g0, %l2
   bne,pn %xcc, fail
   nop

   !# allocate control word queue (e.g., setup head/tail/first/last registers)
   setx CWQ_BASE, %g1, %l6

   !# write base addr to first, head, and tail ptr
   !# first store to first
   stxa    %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
   !# Mask off upper 16 bits
   setx 0x0000ffffffffffff, %l5, %l0
   and %l0, %l6, %l2
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   !# then to head
   stxa    %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   !# then to tail
   stxa    %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   !# then end of CWQ region to LAST
   setx CWQ_LAST, %g1, %l5
   stxa    %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
   !# Mask off upper 16 bits
   and %l0, %l5, %l2
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   membar #Sync

   ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
   add %l2, 512, %l2
   stxa    %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   !# Kick off the CWQ operation by writing to the CWQ_CSR
   !# Set the enabled bit and reset the other bits
   or      %g0, 0x1, %g1
   stxa    %g1,    [%g0 + ASI_SPU_CWQ_CSR] %asi
   !# Make sure all these stores get to memory before we start

   !# Try CWQ_SYNC operation...
   ldxa    [%g0 + 0x30] %asi, %l1

   and	%l1, 0x6, %l1
   brnz	%l1, fail			!# test for unexpected protocal error
   nop

   ldxa    [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
   ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1

   setx 10, %g1, %l2
   or %g0, %g0, %g3   

check_results_0:
   setx    results, %g1, %l5
   ldx     [%l5 + %g3], %l1
   add     %g3, 0x8, %g3   !# i++
   addcc   %l2, -1, %l2
   bgt     check_results_0
   nop

   or %g0, 0x8, %i0    
   or %g0, %g0, %g3   

check_sfas_0:
   setx    fas_result, %g1, %l5
   ldx     [%l5 + %g3], %l1
   add     %g3, 0x8, %g3   !# i++
   addcc   %i0, -1, %i0
   bgt     check_sfas_0 
   nop

!disable SPU before next operation
   stxa    %g0,    [%g0 + ASI_SPU_CWQ_CSR] %asi
   nop

   EXIT_GOOD

thread_other:
   !wait for interrupt and then exit

wait_for_int:
   cmp %i6,1
   bne wait_for_int
   nop

   EXIT_GOOD

fail:
   EXIT_BAD

.data
user_data_start:
scratch_area:

! first 8 addresses are for counters, last is for done bit
.align 16
thread_scratch_area:
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000

.align 16
msg1:
.xword 0x0030fdc05d599221
.xword 0x10f3279537ce239f
.xword 0x350192ee57e49864
.xword 0xe6b13af6031ce21d
.xword 0xc04ca56d80506fa8
.xword 0xb3c6d051fbad26e0
.xword 0xb260907945f0428a
.xword 0xa59182341647b4c2
.xword 0xab9b60838da8f032
.xword 0x97149144f33acd56
.align 16
key:
.xword 0x95f1a4e75e3d7de9
.xword 0x54d350ef97fc6332
.xword 0x8bf6a691fb59ffa6
.xword 0xd0a8142e351cffdc
.xword 0xa110d949b459ff24
.xword 0x40e7b7e36e436a93

.align 16
iv:
.xword 0x8afbb3c3013d7e7a
.xword 0x1980dd67b1386a71
.xword 0x4cb849ad9f511439
.xword 0x5af08a49a51e2b9d
.xword 0x879b4a63cc59cd74
.xword 0xb847c25ebf5b1795

.align 16
results:
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF

.align 16
fas_result:
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF

!# CWQ data area, set aside 512 CW's worth
!# 512*8*8 = 32KB
.align 32*1024
CWQ_BASE:
.xword 0xC1610B02000A0000
.xword msg1
.xword key
.xword iv
.xword fas_result
.xword 0
.xword 0
.xword results

.xword 0xC1610B22000A0040
.xword msg1
.xword key
.xword iv
.xword fas_result
.xword 0
.xword 0
.xword results

.xword 0xC1610B42000A0035
.xword msg1
.xword key
.xword iv
.xword fas_result
.xword 0
.xword 0
.xword results

.xword 0xC1610B62000A0005
.xword msg1
.xword key
.xword iv
.xword fas_result
.xword 0
.xword 0
.xword results

.xword 0xC1610B82000A0035
.xword msg1
.xword key
.xword iv
.xword fas_result
.xword 0
.xword 0
.xword results

.xword 0xC1610BA2000A0025
.xword msg1
.xword key
.xword iv
.xword fas_result
.xword 0
.xword 0
.xword results

.xword 0xC1610BC2000A0015
.xword msg1
.xword key
.xword iv
.xword fas_result
.xword 0
.xword 0
.xword results

.xword 0xC1610BE2000A0005
.xword msg1
.xword key
.xword iv
.xword fas_result
.xword 0
.xword 0
.xword results

.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
CWQ_LAST:
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAAA

.end

.global CHECK_PIC_COUNT
SECTION .HTRAPS
.text
CHECK_PIC_COUNT:
  rd  %pic,   %g4
  mov %g4, %i7
  srlx %g4, 32, %g4
  brz %g4, FAIL 
  nop

check_pic0_isZero_0:
  setx 0x00000000ffffffff, %l5, %l0
  and %i7, %l0, %i7
  brnz %i7, FAIL 
  nop

  !increment interrupt counter
  add %i6,1,%i6

  retry
  nop

FAIL: EXIT_BAD
nop

#if 0
#endif
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: pmu_ccx_sel5_0x01_thAll.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define PIC_COUNT 1
	39
	40	#define MAX_THREAD_TIMEOUT 0x1fff
	41	#define MAIN_PAGE_HV_ALSO
	42	#define NO_TRAPCHECK
	43	#define H_HT0_Control_Word_Queue_Interrupt_0x3c
	44	#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
	45	wr %g0, 0x40, %asi; \
	46	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %i5; \
	47	stxa %i5, [%g0 + ASI_SPU_CWQ_CSR] %asi; \
	48	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %i5; \
	49	and %i5, 0x10, %i5; \
	50	brnz %i5, FAIL; \
	51	nop; \
	52	ba CHECK_PIC_COUNT; \
	53	nop;nop;
	54
	55	#include "hboot.s"
	56
	57	.text
	58	.global main
	59
	60	main:
	61
	62	and %g0,0,%i6
	63
	64	setx 0x0000deadbeefbad0, %l5, %l4
65
66	!# Switch to hpriv mode
67	ta T_CHANGE_HPRIV
68	!# Check to make sure pic is zero
69	!#rd %pic, %g4
70	!#cmp %g0, %g4
71	!#bne,pn %icc, fail
72	!#nop
73	wr %g0, %g0, %pic !zero out pic
74
75	!# Setup PCR Register
76	set 0x000000002809C048, %g2
77	wr %g2, %g0, %pcr
78	wr %g0, %g0, %pic !zero out pic
79
80	!Get TID
81	ta T_RD_THID
82	mov %o1, %l6
83	nop
84
85	cmp %l6, 0
86	be thread_0
87	nop
88
89	cmp %l6, 1
90	be thread_other
91	nop
92
93	!all other threads execute the same code
94	cmp %l6, 2
95	be thread_other
96	nop
97
98	cmp %l6, 3
99	be thread_other
100	nop
101
102	cmp %l6, 4
103	be thread_other
104	nop
105
106	cmp %l6, 5
107	be thread_other
108	nop
109
110	cmp %l6, 6
111	be thread_other
112	nop
113
114	cmp %l6, 7
115	be thread_other
116	nop
117
118	ba fail
119
120	thread_0:
121	!# setup ASI register to point to SPU
122	wr %g0, 0x40, %asi
123
124	InitialCW_0:
125
126	!# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
127	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
128	and %l1, 0xf, %l2
129	cmp %g0, %l2
130	bne,pn %xcc, fail
131	nop
132
133	!# allocate control word queue (e.g., setup head/tail/first/last registers)
134	setx CWQ_BASE, %g1, %l6
135
136	!# write base addr to first, head, and tail ptr
137	!# first store to first
138	stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
139	ldxa [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
140	!# Mask off upper 16 bits
141	setx 0x0000ffffffffffff, %l5, %l0
142	and %l0, %l6, %l2
143	cmp %l1, %l2
144	bne,pn %xcc, fail
145	nop
146
147	!# then to head
148	stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
149	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
150	cmp %l1, %l2
151	bne,pn %xcc, fail
152	nop
153
154	!# then to tail
155	stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
156	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
157	cmp %l1, %l2
158	bne,pn %xcc, fail
159	nop
160
161	!# then end of CWQ region to LAST
162	setx CWQ_LAST, %g1, %l5
163	stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
164	ldxa [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
165	!# Mask off upper 16 bits
166	and %l0, %l5, %l2
167	cmp %l1, %l2
168	bne,pn %xcc, fail
169	nop
170
171	membar #Sync
172
173	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
174	add %l2, 512, %l2
175	stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
176	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
177	cmp %l1, %l2
178	bne,pn %xcc, fail
179	nop
180
181	!# Kick off the CWQ operation by writing to the CWQ_CSR
182	!# Set the enabled bit and reset the other bits
183	or %g0, 0x1, %g1
184	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
185	!# Make sure all these stores get to memory before we start
186
187	!# Try CWQ_SYNC operation...
188	ldxa [%g0 + 0x30] %asi, %l1
189
190	and %l1, 0x6, %l1
191	brnz %l1, fail !# test for unexpected protocal error
192	nop
193
194	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
195	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
196
197	setx 10, %g1, %l2
198	or %g0, %g0, %g3
199
200	check_results_0:
201	setx results, %g1, %l5
202	ldx [%l5 + %g3], %l1
203	add %g3, 0x8, %g3 !# i++
204	addcc %l2, -1, %l2
205	bgt check_results_0
206	nop
207
208	or %g0, 0x8, %i0
209	or %g0, %g0, %g3
210
211	check_sfas_0:
212	setx fas_result, %g1, %l5
213	ldx [%l5 + %g3], %l1
214	add %g3, 0x8, %g3 !# i++
215	addcc %i0, -1, %i0
216	bgt check_sfas_0
217	nop
218
219	!disable SPU before next operation
220	stxa %g0, [%g0 + ASI_SPU_CWQ_CSR] %asi
221	nop
222
223	EXIT_GOOD
224
225	thread_other:
226	!wait for interrupt and then exit
227
228	wait_for_int:
229	cmp %i6,1
230	bne wait_for_int
231	nop
232
233	EXIT_GOOD
234
235	fail:
236	EXIT_BAD
237
238	.data
239	user_data_start:
240	scratch_area:
241
242	! first 8 addresses are for counters, last is for done bit
243	.align 16
244	thread_scratch_area:
245	.xword 0x0000000000000000
246	.xword 0x0000000000000000
247	.xword 0x0000000000000000
248	.xword 0x0000000000000000
249	.xword 0x0000000000000000
250	.xword 0x0000000000000000
251	.xword 0x0000000000000000
252	.xword 0x0000000000000000
253	.xword 0x0000000000000000
254
255	.align 16
256	msg1:
257	.xword 0x0030fdc05d599221
258	.xword 0x10f3279537ce239f
259	.xword 0x350192ee57e49864
260	.xword 0xe6b13af6031ce21d
261	.xword 0xc04ca56d80506fa8
262	.xword 0xb3c6d051fbad26e0
263	.xword 0xb260907945f0428a
264	.xword 0xa59182341647b4c2
265	.xword 0xab9b60838da8f032
266	.xword 0x97149144f33acd56
267	.align 16
268	key:
269	.xword 0x95f1a4e75e3d7de9
270	.xword 0x54d350ef97fc6332
271	.xword 0x8bf6a691fb59ffa6
272	.xword 0xd0a8142e351cffdc
273	.xword 0xa110d949b459ff24
274	.xword 0x40e7b7e36e436a93
275
276	.align 16
277	iv:
278	.xword 0x8afbb3c3013d7e7a
279	.xword 0x1980dd67b1386a71
280	.xword 0x4cb849ad9f511439
281	.xword 0x5af08a49a51e2b9d
282	.xword 0x879b4a63cc59cd74
283	.xword 0xb847c25ebf5b1795
284
285	.align 16
286	results:
287	.xword 0xDEADBEEFDEADBEEF
288	.xword 0xDEADBEEFDEADBEEF
289	.xword 0xDEADBEEFDEADBEEF
290	.xword 0xDEADBEEFDEADBEEF
291	.xword 0xDEADBEEFDEADBEEF
292	.xword 0xDEADBEEFDEADBEEF
293	.xword 0xDEADBEEFDEADBEEF
294	.xword 0xDEADBEEFDEADBEEF
295	.xword 0xDEADBEEFDEADBEEF
296	.xword 0xDEADBEEFDEADBEEF
297	.xword 0xDEADBEEFDEADBEEF
298	.xword 0xDEADBEEFDEADBEEF
299	.xword 0xDEADBEEFDEADBEEF
300	.xword 0xDEADBEEFDEADBEEF
301
302	.align 16
303	fas_result:
304	.xword 0xDEADBEEFDEADBEEF
305	.xword 0xDEADBEEFDEADBEEF
306	.xword 0xDEADBEEFDEADBEEF
307	.xword 0xDEADBEEFDEADBEEF
308	.xword 0xDEADBEEFDEADBEEF
309	.xword 0xDEADBEEFDEADBEEF
310	.xword 0xDEADBEEFDEADBEEF
311	.xword 0xDEADBEEFDEADBEEF
312
313	!# CWQ data area, set aside 512 CW's worth
314	!# 51288 = 32KB
315	.align 32*1024
316	CWQ_BASE:
317	.xword 0xC1610B02000A0000
318	.xword msg1
319	.xword key
320	.xword iv
321	.xword fas_result
322	.xword 0
323	.xword 0
324	.xword results
325
326	.xword 0xC1610B22000A0040
327	.xword msg1
328	.xword key
329	.xword iv
330	.xword fas_result
331	.xword 0
332	.xword 0
333	.xword results
334
335	.xword 0xC1610B42000A0035
336	.xword msg1
337	.xword key
338	.xword iv
339	.xword fas_result
340	.xword 0
341	.xword 0
342	.xword results
343
344	.xword 0xC1610B62000A0005
345	.xword msg1
346	.xword key
347	.xword iv
348	.xword fas_result
349	.xword 0
350	.xword 0
351	.xword results
352
353	.xword 0xC1610B82000A0035
354	.xword msg1
355	.xword key
356	.xword iv
357	.xword fas_result
358	.xword 0
359	.xword 0
360	.xword results
361
362	.xword 0xC1610BA2000A0025
363	.xword msg1
364	.xword key
365	.xword iv
366	.xword fas_result
367	.xword 0
368	.xword 0
369	.xword results
370
371	.xword 0xC1610BC2000A0015
372	.xword msg1
373	.xword key
374	.xword iv
375	.xword fas_result
376	.xword 0
377	.xword 0
378	.xword results
379
380	.xword 0xC1610BE2000A0005
381	.xword msg1
382	.xword key
383	.xword iv
384	.xword fas_result
385	.xword 0
386	.xword 0
387	.xword results
388
389	.xword 0xAAAAAAAAAAAAAAAA
390	.xword 0xAAAAAAAAAAAAAAAA
391	.xword 0xAAAAAAAAAAAAAAAA
392	.xword 0xAAAAAAAAAAAAAAAA
393	.xword 0xAAAAAAAAAAAAAAAA
394	.xword 0xAAAAAAAAAAAAAAAA
395	.xword 0xAAAAAAAAAAAAAAAA
396	.xword 0xAAAAAAAAAAAAAAAA
397	CWQ_LAST:
398	.xword 0xAAAAAAAAAAAAAAAA
399	.xword 0xAAAAAAAAAAAAAAAA
400	.xword 0xAAAAAAAAAAAAAAAA
401	.xword 0xAAAAAAAAAAAAAAAA
402	.xword 0xAAAAAAAAAAAAAAAA
403	.xword 0xAAAAAAAAAAAAAAAA
404	.xword 0xAAAAAAAAAAAAAAAA
405	.xword 0xAAAAAAAAAAAAAAAA
406
407	.end
408
409	.global CHECK_PIC_COUNT
410	SECTION .HTRAPS
411	.text
412	CHECK_PIC_COUNT:
413	rd %pic, %g4
414	mov %g4, %i7
415	srlx %g4, 32, %g4
416	brz %g4, FAIL
417	nop
418
419	check_pic0_isZero_0:
420	setx 0x00000000ffffffff, %l5, %l0
421	and %i7, %l0, %i7
422	brnz %i7, FAIL
423	nop
424
425	!increment interrupt counter
426	add %i6,1,%i6
427
428	retry
429	nop
430
431	FAIL: EXIT_BAD
432	nop
433
434	#if 0
435	#endif