[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / pmu / diag / pmu_ccx_sel5_0x02_th0.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: pmu_ccx_sel5_0x02_th0.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define PIC_COUNT  0x2
#define MAIN_PAGE_HV_ALSO
#define NO_TRAPCHECK
#define H_HT0_Control_Word_Queue_Interrupt_0x3c
#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
  %g0, 0x40, %asi; \
  ldxa [%g0 + ASI_SPU_CWQ_CSR]%asi, %i5; \
  stxa %i5, [%g0 + ASI_SPU_CWQ_CSR]%asi; \
  add %i6, 1, %i6; \
  retry;nop;nop;nop;
#include "hboot.s"

.text
.global main

main:       

thread_0:

   setx 0x0000deadbeefbad0, %l5, %l4

   !# Switch to hpriv mode
   ta T_CHANGE_HPRIV
   !# Check to make sure pic is zero
!#   rd  %pic,   %g4
!#   cmp %g0,    %g4
!#   bne,pn  %icc,   fail
!#   nop

  !# Setup PCR Register
  set 0x0000000020414088, %g2
  wr  %g2, %g0, %pcr

   !# reset pic after pcr written as boot code counts instructions
   wr %g0, %g0, %pic	

   !# init interrupt trap counter
   add %g0, 0, %i6

   !# setup ASI register to point to SPU
   wr %g0, 0x40, %asi

InitialCW_0:

   !# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
   ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
   and %l1, 0xf, %l2
   cmp %g0, %l2
   bne,pn %xcc, fail
   nop

   !# allocate control word queue (e.g., setup head/tail/first/last registers)
   setx CWQ_BASE, %g1, %l6

   !# write base addr to first, head, and tail ptr
   !# first store to first
   stxa    %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
   !# Mask off upper 16 bits
   setx 0x0000ffffffffffff, %l5, %l0
   and %l0, %l6, %l2
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   !# then to head
   stxa    %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   !# then to tail
   stxa    %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   !# then end of CWQ region to LAST
   setx CWQ_LAST, %g1, %l5
   stxa    %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
   !# Mask off upper 16 bits
   and %l0, %l5, %l2
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   setx 0x5555deadbeefbad5, %l5, %l4

    add %l6, 0x0, %l6
   !# set  CWQ data
   setx 0xC1600901000A0035, %l1, %l2			!# CWQ Control Word
   mov %l2, %i7					    !# save initial CW

   !# write CWQ entry (%l6 points to CWQ)
   stx  %l2, [%l6 + 0x0]

   !# source address
   setx msg1, %g1, %l2
   stx %l2, [%l6 + 0x8]

   !# Authentication Key Address (40-bit)
   setx key, %g1, %l2
   stx %l2, [%l6 + 0x10]

   !# set IV
   setx iv, %g1, %o2
   stx     %o2, [%l6 + 0x18]

   !# Final Authentication State Address (40-bit)
   setx fas_result, %g1, %o2
   stx     %o2, [%l6 + 0x20]

   !# Encryption Key Address (40-bit)
   stx %g0, [%l6+0x28]

   !# Encryption Initialization Vector Address (40-bit)
   stx %g0, [%l6+0x30]

   !# Destination Address (40-bit)
   setx    results, %g1, %o3
   stx %o3, [%l6 + 0x38]

   setx 0x6666deadbeefbad6, %l5, %l4

   membar #Sync

   ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
   add %l2, 64, %l2
   stxa    %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
   ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
   cmp %l1, %l2
   bne,pn %xcc,    fail
   nop

   !# Kick off the CWQ operation by writing to the CWQ_CSR
   !# Set the enabled bit and reset the other bits
   or      %g0, 0x1, %g1
   stxa    %g1,    [%g0 + ASI_SPU_CWQ_CSR] %asi
   !# Make sure all these stores get to memory before we start

   !# Try CWQ_SYNC operation...
   ldxa    [%g0 + 0x30] %asi, %l1

   and	%l1, 0x6, %l1 
   brnz	%l1, fail			!# test for unexpected protocal error
   nop

   ldxa    [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
   ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1

check_pic_th_0:
    rd  %pic,   %g4
    mov %g4, %i7
    cmp     %g4, PIC_COUNT
    bne,pn  %icc, fail
    nop

check_pic1_isZero_0:
    setx 0xffffffff00000000, %l5, %l0
    and %i7, %l0, %i7
    cmp     %i7, 0x0
    bne,pn  %icc, fail
    nop


   setx 10, %g1, %l2
   or %g0, %g0, %g3   

check_results_0:
   setx    results, %g1, %l5
   ldx     [%l5 + %g3], %l1
   add     %g3, 0x8, %g3   !# i++
   addcc   %l2, -1, %l2
   bgt     check_results_0
   nop

   or %g0, 0x8, %i0    
   or %g0, %g0, %g3   

check_sfas_0:
   setx    fas_result, %g1, %l5
   ldx     [%l5 + %g3], %l1
   add     %g3, 0x8, %g3   !# i++
   addcc   %i0, -1, %i0
   bgt     check_sfas_0 
   nop

!disable SPU before next operation
   stxa    %g0,    [%g0 + ASI_SPU_CWQ_CSR] %asi
   nop

   EXIT_GOOD


fail:
   EXIT_BAD

.data
user_data_start:
scratch_area:

! first 8 addresses are for counters, last is for done bit
.align 16
thread_scratch_area:
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000
.xword 0x0000000000000000

.align 16
msg1:
.xword 0x0030fdc05d599221
.xword 0x10f3279537ce239f
.xword 0x350192ee57e49864
.xword 0xe6b13af6031ce21d
.xword 0xc04ca56d80506fa8
.xword 0xb3c6d051fbad26e0
.xword 0xb260907945f0428a
.xword 0xa59182341647b4c2
.xword 0xab9b60838da8f032
.xword 0x97149144f33acd56
.align 16
key:
.xword 0x95f1a4e75e3d7de9
.xword 0x54d350ef97fc6332
.xword 0x8bf6a691fb59ffa6
.xword 0xd0a8142e351cffdc
.xword 0xa110d949b459ff24
.xword 0x40e7b7e36e436a93

.align 16
iv:
.xword 0x8afbb3c3013d7e7a
.xword 0x1980dd67b1386a71
.xword 0x4cb849ad9f511439
.xword 0x5af08a49a51e2b9d
.xword 0x879b4a63cc59cd74
.xword 0xb847c25ebf5b1795

.align 16
results:
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF

.align 16
fas_result:
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF

!# CWQ data area, set aside 512 CW's worth
!# 512*8*8 = 32KB
.align 32*1024
CWQ_BASE:
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
CWQ_LAST:
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA

.end

#if 0
#endif
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: pmu_ccx_sel5_0x02_th0.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define PIC_COUNT 0x2
	39	#define MAIN_PAGE_HV_ALSO
	40	#define NO_TRAPCHECK
	41	#define H_HT0_Control_Word_Queue_Interrupt_0x3c
	42	#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
	43	%g0, 0x40, %asi; \
	44	ldxa [%g0 + ASI_SPU_CWQ_CSR]%asi, %i5; \
	45	stxa %i5, [%g0 + ASI_SPU_CWQ_CSR]%asi; \
	46	add %i6, 1, %i6; \
	47	retry;nop;nop;nop;
	48	#include "hboot.s"
	49
	50	.text
	51	.global main
	52
	53	main:
	54
	55	thread_0:
	56
	57	setx 0x0000deadbeefbad0, %l5, %l4
	58
	59	!# Switch to hpriv mode
	60	ta T_CHANGE_HPRIV
	61	!# Check to make sure pic is zero
	62	!# rd %pic, %g4
	63	!# cmp %g0, %g4
	64	!# bne,pn %icc, fail
65	!# nop
66
67	!# Setup PCR Register
68	set 0x0000000020414088, %g2
69	wr %g2, %g0, %pcr
70
71	!# reset pic after pcr written as boot code counts instructions
72	wr %g0, %g0, %pic
73
74	!# init interrupt trap counter
75	add %g0, 0, %i6
76
77	!# setup ASI register to point to SPU
78	wr %g0, 0x40, %asi
79
80	InitialCW_0:
81
82	!# Make sure CWQ is currently disabled, not busy, not terminated, no protocol error; else fail
83	ldxa [%g0 + ASI_SPU_CWQ_CSR] %asi, %l1
84	and %l1, 0xf, %l2
85	cmp %g0, %l2
86	bne,pn %xcc, fail
87	nop
88
89	!# allocate control word queue (e.g., setup head/tail/first/last registers)
90	setx CWQ_BASE, %g1, %l6
91
92	!# write base addr to first, head, and tail ptr
93	!# first store to first
94	stxa %l6, [%g0 + ASI_SPU_CWQ_FIRST] %asi
95	ldxa [%g0 + ASI_SPU_CWQ_FIRST] %asi, %l1
96	!# Mask off upper 16 bits
97	setx 0x0000ffffffffffff, %l5, %l0
98	and %l0, %l6, %l2
99	cmp %l1, %l2
100	bne,pn %xcc, fail
101	nop
102
103	!# then to head
104	stxa %l6, [%g0 + ASI_SPU_CWQ_HEAD] %asi
105	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
106	cmp %l1, %l2
107	bne,pn %xcc, fail
108	nop
109
110	!# then to tail
111	stxa %l6, [%g0 + ASI_SPU_CWQ_TAIL] %asi
112	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
113	cmp %l1, %l2
114	bne,pn %xcc, fail
115	nop
116
117	!# then end of CWQ region to LAST
118	setx CWQ_LAST, %g1, %l5
119	stxa %l5, [%g0 + ASI_SPU_CWQ_LAST] %asi
120	ldxa [%g0 + ASI_SPU_CWQ_LAST] %asi, %l1
121	!# Mask off upper 16 bits
122	and %l0, %l5, %l2
123	cmp %l1, %l2
124	bne,pn %xcc, fail
125	nop
126
127	setx 0x5555deadbeefbad5, %l5, %l4
128
129	add %l6, 0x0, %l6
130	!# set CWQ data
131	setx 0xC1600901000A0035, %l1, %l2 !# CWQ Control Word
132	mov %l2, %i7 !# save initial CW
133
134	!# write CWQ entry (%l6 points to CWQ)
135	stx %l2, [%l6 + 0x0]
136
137	!# source address
138	setx msg1, %g1, %l2
139	stx %l2, [%l6 + 0x8]
140
141	!# Authentication Key Address (40-bit)
142	setx key, %g1, %l2
143	stx %l2, [%l6 + 0x10]
144
145	!# set IV
146	setx iv, %g1, %o2
147	stx %o2, [%l6 + 0x18]
148
149	!# Final Authentication State Address (40-bit)
150	setx fas_result, %g1, %o2
151	stx %o2, [%l6 + 0x20]
152
153	!# Encryption Key Address (40-bit)
154	stx %g0, [%l6+0x28]
155
156	!# Encryption Initialization Vector Address (40-bit)
157	stx %g0, [%l6+0x30]
158
159	!# Destination Address (40-bit)
160	setx results, %g1, %o3
161	stx %o3, [%l6 + 0x38]
162
163	setx 0x6666deadbeefbad6, %l5, %l4
164
165	membar #Sync
166
167	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l2
168	add %l2, 64, %l2
169	stxa %l2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
170	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
171	cmp %l1, %l2
172	bne,pn %xcc, fail
173	nop
174
175	!# Kick off the CWQ operation by writing to the CWQ_CSR
176	!# Set the enabled bit and reset the other bits
177	or %g0, 0x1, %g1
178	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
179	!# Make sure all these stores get to memory before we start
180
181	!# Try CWQ_SYNC operation...
182	ldxa [%g0 + 0x30] %asi, %l1
183
184	and %l1, 0x6, %l1
185	brnz %l1, fail !# test for unexpected protocal error
186	nop
187
188	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %l1
189	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %l1
190
191	check_pic_th_0:
192	rd %pic, %g4
193	mov %g4, %i7
194	cmp %g4, PIC_COUNT
195	bne,pn %icc, fail
196	nop
197
198	check_pic1_isZero_0:
199	setx 0xffffffff00000000, %l5, %l0
200	and %i7, %l0, %i7
201	cmp %i7, 0x0
202	bne,pn %icc, fail
203	nop
204
205
206	setx 10, %g1, %l2
207	or %g0, %g0, %g3
208
209	check_results_0:
210	setx results, %g1, %l5
211	ldx [%l5 + %g3], %l1
212	add %g3, 0x8, %g3 !# i++
213	addcc %l2, -1, %l2
214	bgt check_results_0
215	nop
216
217	or %g0, 0x8, %i0
218	or %g0, %g0, %g3
219
220	check_sfas_0:
221	setx fas_result, %g1, %l5
222	ldx [%l5 + %g3], %l1
223	add %g3, 0x8, %g3 !# i++
224	addcc %i0, -1, %i0
225	bgt check_sfas_0
226	nop
227
228	!disable SPU before next operation
229	stxa %g0, [%g0 + ASI_SPU_CWQ_CSR] %asi
230	nop
231
232	EXIT_GOOD
233
234
235	fail:
236	EXIT_BAD
237
238	.data
239	user_data_start:
240	scratch_area:
241
242	! first 8 addresses are for counters, last is for done bit
243	.align 16
244	thread_scratch_area:
245	.xword 0x0000000000000000
246	.xword 0x0000000000000000
247	.xword 0x0000000000000000
248	.xword 0x0000000000000000
249	.xword 0x0000000000000000
250	.xword 0x0000000000000000
251	.xword 0x0000000000000000
252	.xword 0x0000000000000000
253	.xword 0x0000000000000000
254
255	.align 16
256	msg1:
257	.xword 0x0030fdc05d599221
258	.xword 0x10f3279537ce239f
259	.xword 0x350192ee57e49864
260	.xword 0xe6b13af6031ce21d
261	.xword 0xc04ca56d80506fa8
262	.xword 0xb3c6d051fbad26e0
263	.xword 0xb260907945f0428a
264	.xword 0xa59182341647b4c2
265	.xword 0xab9b60838da8f032
266	.xword 0x97149144f33acd56
267	.align 16
268	key:
269	.xword 0x95f1a4e75e3d7de9
270	.xword 0x54d350ef97fc6332
271	.xword 0x8bf6a691fb59ffa6
272	.xword 0xd0a8142e351cffdc
273	.xword 0xa110d949b459ff24
274	.xword 0x40e7b7e36e436a93
275
276	.align 16
277	iv:
278	.xword 0x8afbb3c3013d7e7a
279	.xword 0x1980dd67b1386a71
280	.xword 0x4cb849ad9f511439
281	.xword 0x5af08a49a51e2b9d
282	.xword 0x879b4a63cc59cd74
283	.xword 0xb847c25ebf5b1795
284
285	.align 16
286	results:
287	.xword 0xDEADBEEFDEADBEEF
288	.xword 0xDEADBEEFDEADBEEF
289	.xword 0xDEADBEEFDEADBEEF
290	.xword 0xDEADBEEFDEADBEEF
291	.xword 0xDEADBEEFDEADBEEF
292	.xword 0xDEADBEEFDEADBEEF
293	.xword 0xDEADBEEFDEADBEEF
294	.xword 0xDEADBEEFDEADBEEF
295	.xword 0xDEADBEEFDEADBEEF
296	.xword 0xDEADBEEFDEADBEEF
297	.xword 0xDEADBEEFDEADBEEF
298	.xword 0xDEADBEEFDEADBEEF
299	.xword 0xDEADBEEFDEADBEEF
300	.xword 0xDEADBEEFDEADBEEF
301
302	.align 16
303	fas_result:
304	.xword 0xDEADBEEFDEADBEEF
305	.xword 0xDEADBEEFDEADBEEF
306	.xword 0xDEADBEEFDEADBEEF
307	.xword 0xDEADBEEFDEADBEEF
308	.xword 0xDEADBEEFDEADBEEF
309	.xword 0xDEADBEEFDEADBEEF
310	.xword 0xDEADBEEFDEADBEEF
311	.xword 0xDEADBEEFDEADBEEF
312
313	!# CWQ data area, set aside 512 CW's worth
314	!# 51288 = 32KB
315	.align 32*1024
316	CWQ_BASE:
317	.xword 0xAAAAAAAAAAAAAAA
318	.xword 0xAAAAAAAAAAAAAAA
319	.xword 0xAAAAAAAAAAAAAAA
320	.xword 0xAAAAAAAAAAAAAAA
321	.xword 0xAAAAAAAAAAAAAAA
322	.xword 0xAAAAAAAAAAAAAAA
323	.xword 0xAAAAAAAAAAAAAAA
324	.xword 0xAAAAAAAAAAAAAAA
325	.xword 0xAAAAAAAAAAAAAAA
326	.xword 0xAAAAAAAAAAAAAAA
327	.xword 0xAAAAAAAAAAAAAAA
328	.xword 0xAAAAAAAAAAAAAAA
329	.xword 0xAAAAAAAAAAAAAAA
330	.xword 0xAAAAAAAAAAAAAAA
331	.xword 0xAAAAAAAAAAAAAAA
332	.xword 0xAAAAAAAAAAAAAAA
333	CWQ_LAST:
334	.xword 0xAAAAAAAAAAAAAAA
335	.xword 0xAAAAAAAAAAAAAAA
336	.xword 0xAAAAAAAAAAAAAAA
337	.xword 0xAAAAAAAAAAAAAAA
338	.xword 0xAAAAAAAAAAAAAAA
339	.xword 0xAAAAAAAAAAAAAAA
340	.xword 0xAAAAAAAAAAAAAAA
341	.xword 0xAAAAAAAAAAAAAAA
342
343	.end
344
345	#if 0
346	#endif