[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / tlu / diag / tlu_halt_cwqint.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tlu_halt_cwqint.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Control_Word_Queue_Interrupt_0x3c
#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
   mov 0x20, %g1 ;\
   stxa %g0 ,[%g1]0x40 ;\
   retry
    

#define MAIN_PAGE_HV_ALSO

#include "hboot.s"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:		/* test begin */


    ta T_CHANGE_HPRIV

    ! If MT, then park all threads based on park_mask
    ! Unpark the next thread when finished with this one..
    ! %l1 contains is_mt, %l2 contains address of is_mt
    ! %l3 contains park_mask, %l4 contains address of park_mask
    ! % l5 is mutex address 

setup_for_mt: ! {{{
    setx is_mt, %g1, %l2
    add %l2, 8, %l4
    add %l4, 8, %l5
    ldx [%l5], %g1
    ldstub [%l5], %g1 
get_mutex:
    ldx [%l5], %g2
    brnz,a %g1, get_mutex
    ldstub [%l5], %g1 

check_is_mt_set:
    ldx [%l2], %l1
    brnz %l1, continue
    mov 0x58, %g3
is_mt_not_set:
    ldxa [%g3]0x41, %l1
    popc %l1, %l1
    dec %l1
    brz %l1, continue
    nop
is_mt_and_first:
    mov 0x50, %g3
    stxa %g0, [%g3] 0x41  ! Park all threads
    mov 50, %g1
wait:
    brnz,a %g1, wait
    dec %g1

    stx %l1, [%l2]        ! Set the MT flag
    mov 1, %g1
    stx %g0, [%l5]  ! release mutex
    stxa %g1, [%g3] 0x41  ! Start with T0
    
continue:
    stx %g0, [%l5]  ! release mutex

! }}}

test1:
    wrpr %g0, 0x0, %pstate  ! disable IE


    wr %g0, 0x40, %asi    
    stxa    %g0,    [%g0 + ASI_SPU_CWQ_CSR] %asi
    !# allocate control word queue (e.g., setup head/tail/first/last registers)
    set CWQ_BASE, %g6

    !# write base addr to first, head, and tail ptr
    !# first store to first
    stxa    %g6, [%g0 + ASI_SPU_CWQ_FIRST] %asi	!# first store to first

    stxa    %g6, [%g0 + ASI_SPU_CWQ_HEAD] %asi	!# then to head
    stxa    %g6, [%g0 + ASI_SPU_CWQ_TAIL] %asi	!# then to tail
    setx CWQ_LAST, %g1, %g5				!# then end of CWQ region to LAST
    stxa    %g5, [%g0 + ASI_SPU_CWQ_LAST] %asi

    !# set  CWQ control word ([39:37] is strand ID ..)
#ifdef INJECT_ERR
    best_set_reg(0x20600000, %g1, %g2)		!#		Control Word
#else
    best_set_reg(0x20610000, %g1, %g2)		!#		Control Word
#endif
    ldxa [%g0]0x63, %g1  ! get my TID for interrupt steering ..
    sllx %g1, 5, %g1
    or %g2, %g1, %g2
    sllx %g2, 32, %g2

    !# write CWQ entry (%g6 points to CWQ)
    stx  %g2, [%g6 + 0x0]

    setx msg, %g1, %g2
    stx %g2, [%g6 + 0x8]	!# source address

    stx %g0, [%g6 + 0x10]	!# Authentication Key  Address (40-bit)
    stx %g0, [%g6 + 0x18]	!# Authentication IV   Address (40-bit)
    stx %g0, [%g6 + 0x20]	!# Authentication FSAS Address (40-bit)
    stx %g0, [%g6 + 0x28]	!# Encryption Key Address (40-bit)
    stx %g0, [%g6 + 0x30]	!# Encryption Initialization Vector Address (40-bit)

    setx    results, %g1, %o3
    stx %o3, [%g6 + 0x38]	!# Destination Address (40-bit)

    membar #Sync

    ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %g2
    add %g2, 0x40, %g2
    stxa    %g2, [%g0 + ASI_SPU_CWQ_TAIL] %asi

    !# Kick off the CWQ operation by writing to the CWQ_CSR
    !# Set the enabled bit and reset the other bits
    or      %g0, 0x1, %g1
    stxa    %g1,    [%g0 + ASI_SPU_CWQ_CSR] %asi
#ifdef INJECT_ERR
! $EV trig_pc_d(1, @VA(.MAIN.test1)) -> errCpxPkt(*,2,1, *, *, 1)
#endif


    mov 100, %g1
wait_for_int:
    brnz,a %g1, wait_for_int
    dec %g1

halt1:
    wrhpr %g0, 0x0, %halt
    ldxa [%g0]0x4c, %g0  ! clear DESR

test2:
    mov 0x20, %g1 
    stxa %g0 ,[%g1]0x40 
    wrpr %g0, 2, %pstate    ! Enable IE


    !# set  CWQ control word ([39:37] is strand ID ..)
#ifdef INJECT_ERR
    best_set_reg(0x20600000, %g1, %g2)		!#		Control Word
#else
    best_set_reg(0x20610000, %g1, %g2)		!#		Control Word
#endif
    ldxa [%g0]0x63, %g1  ! get my TID for interrupt steering ..
    sllx %g1, 5, %g1
    or %g2, %g1, %g2
    sllx %g2, 32, %g2
    stx  %g2, [%g6 + 0x0]
    membar #Sync
    ldxa    [%g0 + ASI_SPU_CWQ_HEAD] %asi, %g2
    sub %g2, 0x40, %g2
    stxa    %g2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
    or      %g0, 0x1, %g1
    stxa    %g1,    [%g0 + ASI_SPU_CWQ_CSR] %asi
#ifdef INJECT_ERR
! $EV trig_pc_d(1, @VA(.MAIN.test2)) -> errCpxPkt(*,2,1, *, *, 1)
#endif

halt2:
    wrhpr %g0, 0x0, %halt
    ldxa [%g0]0x4c, %g0  ! clear DESR
    nop
    nop
    nop

    ! Finish if not MT
    brz %l1, done_thread
    nop

    ! If MT, shift mask, unpark next thread and finish
    ldx [%l4], %l3
    sllx %l3, 1, %l3
    mov 0x60, %g1
    stxa %l3, [%g1]0x41
    stx %l3, [%l4]
    nop

	
/*******************************************************
 * Exit code
 *******************************************************/

done_thread:
    nop
	ta		T_GOOD_TRAP
    nop

/************************************************************************
   Test case data start
 ************************************************************************/
.data
is_mt :
.xword 0x0
park_mask:
.xword 0x1
mutex:
.xword 0

SECTION .CWQ_DATA DATA_VA =0x4000
attr_data {
    Name = .CWQ_DATA 
    hypervisor
}

.data
.align 16
.global msg
msg:
.xword 0xad32fa52374cc6ba
.xword 0x4cbf52280549003a

.align 16
.global results
results:
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
!# CWQ data area 
.align 64
.global CWQ_BASE
CWQ_BASE:
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.global CWQ_LAST
.align 64
CWQ_LAST:
.word 0x0
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: tlu_halt_cwqint.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Control_Word_Queue_Interrupt_0x3c
	39	#define My_HT0_Control_Word_Queue_Interrupt_0x3c \
	40	mov 0x20, %g1 ;\
	41	stxa %g0 ,[%g1]0x40 ;\
	42	retry
	43
	44
	45	#define MAIN_PAGE_HV_ALSO
	46
	47	#include "hboot.s"
	48
	49	/************************************************************************
	50	Test case code start
	51	************************************************************************/
	52
	53	.text
	54	.global main
	55
	56	main: /* test begin */
	57
	58
	59	ta T_CHANGE_HPRIV
	60
	61	! If MT, then park all threads based on park_mask
	62	! Unpark the next thread when finished with this one..
	63	! %l1 contains is_mt, %l2 contains address of is_mt
	64	! %l3 contains park_mask, %l4 contains address of park_mask
65	! % l5 is mutex address
66
67	setup_for_mt: ! {{{
68	setx is_mt, %g1, %l2
69	add %l2, 8, %l4
70	add %l4, 8, %l5
71	ldx [%l5], %g1
72	ldstub [%l5], %g1
73	get_mutex:
74	ldx [%l5], %g2
75	brnz,a %g1, get_mutex
76	ldstub [%l5], %g1
77
78	check_is_mt_set:
79	ldx [%l2], %l1
80	brnz %l1, continue
81	mov 0x58, %g3
82	is_mt_not_set:
83	ldxa [%g3]0x41, %l1
84	popc %l1, %l1
85	dec %l1
86	brz %l1, continue
87	nop
88	is_mt_and_first:
89	mov 0x50, %g3
90	stxa %g0, [%g3] 0x41 ! Park all threads
91	mov 50, %g1
92	wait:
93	brnz,a %g1, wait
94	dec %g1
95
96	stx %l1, [%l2] ! Set the MT flag
97	mov 1, %g1
98	stx %g0, [%l5] ! release mutex
99	stxa %g1, [%g3] 0x41 ! Start with T0
100
101	continue:
102	stx %g0, [%l5] ! release mutex
103
104	! }}}
105
106	test1:
107	wrpr %g0, 0x0, %pstate ! disable IE
108
109
110	wr %g0, 0x40, %asi
111	stxa %g0, [%g0 + ASI_SPU_CWQ_CSR] %asi
112	!# allocate control word queue (e.g., setup head/tail/first/last registers)
113	set CWQ_BASE, %g6
114
115	!# write base addr to first, head, and tail ptr
116	!# first store to first
117	stxa %g6, [%g0 + ASI_SPU_CWQ_FIRST] %asi !# first store to first
118
119	stxa %g6, [%g0 + ASI_SPU_CWQ_HEAD] %asi !# then to head
120	stxa %g6, [%g0 + ASI_SPU_CWQ_TAIL] %asi !# then to tail
121	setx CWQ_LAST, %g1, %g5 !# then end of CWQ region to LAST
122	stxa %g5, [%g0 + ASI_SPU_CWQ_LAST] %asi
123
124	!# set CWQ control word ([39:37] is strand ID ..)
125	#ifdef INJECT_ERR
126	best_set_reg(0x20600000, %g1, %g2) !# Control Word
127	#else
128	best_set_reg(0x20610000, %g1, %g2) !# Control Word
129	#endif
130	ldxa [%g0]0x63, %g1 ! get my TID for interrupt steering ..
131	sllx %g1, 5, %g1
132	or %g2, %g1, %g2
133	sllx %g2, 32, %g2
134
135	!# write CWQ entry (%g6 points to CWQ)
136	stx %g2, [%g6 + 0x0]
137
138	setx msg, %g1, %g2
139	stx %g2, [%g6 + 0x8] !# source address
140
141	stx %g0, [%g6 + 0x10] !# Authentication Key Address (40-bit)
142	stx %g0, [%g6 + 0x18] !# Authentication IV Address (40-bit)
143	stx %g0, [%g6 + 0x20] !# Authentication FSAS Address (40-bit)
144	stx %g0, [%g6 + 0x28] !# Encryption Key Address (40-bit)
145	stx %g0, [%g6 + 0x30] !# Encryption Initialization Vector Address (40-bit)
146
147	setx results, %g1, %o3
148	stx %o3, [%g6 + 0x38] !# Destination Address (40-bit)
149
150	membar #Sync
151
152	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %g2
153	add %g2, 0x40, %g2
154	stxa %g2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
155
156	!# Kick off the CWQ operation by writing to the CWQ_CSR
157	!# Set the enabled bit and reset the other bits
158	or %g0, 0x1, %g1
159	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
160	#ifdef INJECT_ERR
161	! $EV trig_pc_d(1, @VA(.MAIN.test1)) -> errCpxPkt(,2,1, , *, 1)
162	#endif
163
164
165	mov 100, %g1
166	wait_for_int:
167	brnz,a %g1, wait_for_int
168	dec %g1
169
170	halt1:
171	wrhpr %g0, 0x0, %halt
172	ldxa [%g0]0x4c, %g0 ! clear DESR
173
174	test2:
175	mov 0x20, %g1
176	stxa %g0 ,[%g1]0x40
177	wrpr %g0, 2, %pstate ! Enable IE
178
179
180	!# set CWQ control word ([39:37] is strand ID ..)
181	#ifdef INJECT_ERR
182	best_set_reg(0x20600000, %g1, %g2) !# Control Word
183	#else
184	best_set_reg(0x20610000, %g1, %g2) !# Control Word
185	#endif
186	ldxa [%g0]0x63, %g1 ! get my TID for interrupt steering ..
187	sllx %g1, 5, %g1
188	or %g2, %g1, %g2
189	sllx %g2, 32, %g2
190	stx %g2, [%g6 + 0x0]
191	membar #Sync
192	ldxa [%g0 + ASI_SPU_CWQ_HEAD] %asi, %g2
193	sub %g2, 0x40, %g2
194	stxa %g2, [%g0 + ASI_SPU_CWQ_HEAD] %asi
195	or %g0, 0x1, %g1
196	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
197	#ifdef INJECT_ERR
198	! $EV trig_pc_d(1, @VA(.MAIN.test2)) -> errCpxPkt(,2,1, , *, 1)
199	#endif
200
201	halt2:
202	wrhpr %g0, 0x0, %halt
203	ldxa [%g0]0x4c, %g0 ! clear DESR
204	nop
205	nop
206	nop
207
208	! Finish if not MT
209	brz %l1, done_thread
210	nop
211
212	! If MT, shift mask, unpark next thread and finish
213	ldx [%l4], %l3
214	sllx %l3, 1, %l3
215	mov 0x60, %g1
216	stxa %l3, [%g1]0x41
217	stx %l3, [%l4]
218	nop
219
220
221	/*******************************************************
222	* Exit code
223	*******************************************************/
224
225	done_thread:
226	nop
227	ta T_GOOD_TRAP
228	nop
229
230	/************************************************************************
231	Test case data start
232	************************************************************************/
233	.data
234	is_mt :
235	.xword 0x0
236	park_mask:
237	.xword 0x1
238	mutex:
239	.xword 0
240
241	SECTION .CWQ_DATA DATA_VA =0x4000
242	attr_data {
243	Name = .CWQ_DATA
244	hypervisor
245	}
246
247	.data
248	.align 16
249	.global msg
250	msg:
251	.xword 0xad32fa52374cc6ba
252	.xword 0x4cbf52280549003a
253
254	.align 16
255	.global results
256	results:
257	.xword 0xDEADBEEFDEADBEEF
258	.xword 0xDEADBEEFDEADBEEF
259	!# CWQ data area
260	.align 64
261	.global CWQ_BASE
262	CWQ_BASE:
263	.xword 0xAAAAAAAAAAAAAAA
264	.xword 0xAAAAAAAAAAAAAAA
265	.xword 0xAAAAAAAAAAAAAAA
266	.xword 0xAAAAAAAAAAAAAAA
267	.xword 0xAAAAAAAAAAAAAAA
268	.xword 0xAAAAAAAAAAAAAAA
269	.xword 0xAAAAAAAAAAAAAAA
270	.xword 0xAAAAAAAAAAAAAAA
271	.xword 0xAAAAAAAAAAAAAAA
272	.xword 0xAAAAAAAAAAAAAAA
273	.xword 0xAAAAAAAAAAAAAAA
274	.xword 0xAAAAAAAAAAAAAAA
275	.xword 0xAAAAAAAAAAAAAAA
276	.xword 0xAAAAAAAAAAAAAAA
277	.xword 0xAAAAAAAAAAAAAAA
278	.xword 0xAAAAAAAAAAAAAAA
279	.xword 0xAAAAAAAAAAAAAAA
280	.xword 0xAAAAAAAAAAAAAAA
281	.xword 0xAAAAAAAAAAAAAAA
282	.xword 0xAAAAAAAAAAAAAAA
283	.xword 0xAAAAAAAAAAAAAAA
284	.xword 0xAAAAAAAAAAAAAAA
285	.xword 0xAAAAAAAAAAAAAAA
286	.xword 0xAAAAAAAAAAAAAAA
287	.global CWQ_LAST
288	.align 64
289	CWQ_LAST:
290	.word 0x0
291