[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / tlu / diag / tlu_halt_cwqmodint_cancel.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: tlu_halt_cwqmodint_cancel.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"

/************************************************************************
   Test case code start
 ************************************************************************/

.text
.global main

main:		/* test begin */


    ta T_CHANGE_HPRIV

    ! If MT, then park all threads based on park_mask
    ! Unpark the next thread when finished with this one..
    ! %l1 contains is_mt, %l2 contains address of is_mt
    ! %l3 contains park_mask, %l4 contains address of park_mask
    ! % l5 is mutex address 

setup_for_mt: ! {{{
    setx is_mt, %g1, %l2
    add %l2, 8, %l4
    add %l4, 8, %l5
    ldx [%l5], %g1
    ldstub [%l5], %g1 
get_mutex:
    ldx [%l5], %g2
    brnz,a %g1, get_mutex
    ldstub [%l5], %g1 

check_is_mt_set:
    ldx [%l2], %l1
    brnz %l1, continue
    mov 0x58, %g3
is_mt_not_set:
    ldxa [%g3]0x41, %l1
    popc %l1, %l1
    dec %l1
    brz %l1, continue
    nop
is_mt_and_first:
    mov 0x50, %g3
    stxa %g0, [%g3] 0x41  ! Park all threads
    mov 50, %g1
wait:
    brnz,a %g1, wait
    dec %g1

    stx %l1, [%l2]        ! Set the MT flag
    mov 1, %g1
    stx %g0, [%l5]  ! release mutex
    stxa %g1, [%g3] 0x41  ! Start with T0
    
continue:
    stx %g0, [%l5]  ! release mutex

! }}}

test1:
    wrpr %g0, 0x0, %pstate  ! disable IE


setup_for_cwq_int:

    wr %g0, 0x40, %asi    
    stxa    %g0,    [%g0 + ASI_SPU_CWQ_CSR] %asi
    !# allocate control word queue (e.g., setup head/tail/first/last registers)
    set CWQ_BASE, %g6

    !# write base addr to first, head, and tail ptr
    !# first store to first
    stxa    %g6, [%g0 + ASI_SPU_CWQ_FIRST] %asi	!# first store to first

    stxa    %g6, [%g0 + ASI_SPU_CWQ_HEAD] %asi	!# then to head
    stxa    %g6, [%g0 + ASI_SPU_CWQ_TAIL] %asi	!# then to tail
    setx CWQ_LAST, %g1, %g5				!# then end of CWQ region to LAST
    stxa    %g5, [%g0 + ASI_SPU_CWQ_LAST] %asi

    !# set  CWQ control word ([39:37] is strand ID ..)
    best_set_reg(0x20610000, %g1, %g2)		!#		Control Word
    ldxa [%g0]0x63, %g1  ! get my TID for interrupt steering ..
    sllx %g1, 5, %g1
    or %g2, %g1, %g2
    sllx %g2, 32, %g2

    !# write CWQ entry (%g6 points to CWQ)
    stx  %g2, [%g6 + 0x0]

    setx msg, %g1, %g2
    stx %g2, [%g6 + 0x8]	!# source address

    stx %g0, [%g6 + 0x10]	!# Authentication Key  Address (40-bit)
    stx %g0, [%g6 + 0x18]	!# Authentication IV   Address (40-bit)
    stx %g0, [%g6 + 0x20]	!# Authentication FSAS Address (40-bit)
    stx %g0, [%g6 + 0x28]	!# Encryption Key Address (40-bit)
    stx %g0, [%g6 + 0x30]	!# Encryption Initialization Vector Address (40-bit)

    setx    results, %g1, %o3
    stx %o3, [%g6 + 0x38]	!# Destination Address (40-bit)

    membar #Sync

    ldxa    [%g0 + ASI_SPU_CWQ_TAIL] %asi, %g2
    add %g2, 0x40, %g2
    stxa    %g2, [%g0 + ASI_SPU_CWQ_TAIL] %asi

    !# Kick off the CWQ operation by writing to the CWQ_CSR
    !# Set the enabled bit and reset the other bits
    or      %g0, 0x1, %g1
    stxa    %g1,    [%g0 + ASI_SPU_CWQ_CSR] %asi


setup_for_modint:

	!# 21:0 == 00 0010 0000 0000 0011 1111
	!# 20:18 TID == 0..7
	!#    17 cause interrupt
	!# 12:08 modular addition (1001)
	!# 12:08 load MA mem      (0000)
	!# 07:00 length = 63

    wr %g0, 0x40, %asi
	setx	0x2003f, %g1, %g3
    ldxa [%g0]0x63, %g1  ! get my TID for interrupt steering ..
    sllx %g1, 18, %g1
    or %g3, %g1, %g3
	stxa	%g3, [%g0 + 0x80] %asi


    mov 100, %g1
wait_for_int:
    brnz,a %g1, wait_for_int
    dec %g1

halt1:
    rdhpr %halt, %g7

    wrpr %g0, 0x2, %pstate  ! enable  IE

    ! Finish if not MT
    brz %l1, done_thread
    nop

    ! If MT, shift mask, unpark next thread and finish
    ldx [%l4], %l3
    sllx %l3, 1, %l3
    mov 0x60, %g1
    stxa %l3, [%g1]0x41
    stx %l3, [%l4]
    nop

	
/*******************************************************
 * Exit code
 *******************************************************/

done_thread:
    nop
	ta		T_GOOD_TRAP
    nop

/************************************************************************
   Test case data start
 ************************************************************************/
.data
is_mt :
.xword 0x0
park_mask:
.xword 0x1
mutex:
.xword 0

SECTION .CWQ_DATA DATA_VA =0x4000
attr_data {
    Name = .CWQ_DATA 
    hypervisor
}

.data
.align 16
.global msg
msg:
.xword 0xad32fa52374cc6ba
.xword 0x4cbf52280549003a

.align 16
.global results
results:
.xword 0xDEADBEEFDEADBEEF
.xword 0xDEADBEEFDEADBEEF
!# CWQ data area 
.align 64
.global CWQ_BASE
CWQ_BASE:
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.xword 0xAAAAAAAAAAAAAAA
.global CWQ_LAST
.align 64
CWQ_LAST:
.word 0x0
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: tlu_halt_cwqmodint_cancel.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40	#include "hboot.s"
	41
	42	/************************************************************************
	43	Test case code start
	44	************************************************************************/
	45
	46	.text
	47	.global main
	48
	49	main: /* test begin */
	50
	51
	52	ta T_CHANGE_HPRIV
	53
	54	! If MT, then park all threads based on park_mask
	55	! Unpark the next thread when finished with this one..
	56	! %l1 contains is_mt, %l2 contains address of is_mt
	57	! %l3 contains park_mask, %l4 contains address of park_mask
	58	! % l5 is mutex address
	59
	60	setup_for_mt: ! {{{
	61	setx is_mt, %g1, %l2
	62	add %l2, 8, %l4
	63	add %l4, 8, %l5
	64	ldx [%l5], %g1
65	ldstub [%l5], %g1
66	get_mutex:
67	ldx [%l5], %g2
68	brnz,a %g1, get_mutex
69	ldstub [%l5], %g1
70
71	check_is_mt_set:
72	ldx [%l2], %l1
73	brnz %l1, continue
74	mov 0x58, %g3
75	is_mt_not_set:
76	ldxa [%g3]0x41, %l1
77	popc %l1, %l1
78	dec %l1
79	brz %l1, continue
80	nop
81	is_mt_and_first:
82	mov 0x50, %g3
83	stxa %g0, [%g3] 0x41 ! Park all threads
84	mov 50, %g1
85	wait:
86	brnz,a %g1, wait
87	dec %g1
88
89	stx %l1, [%l2] ! Set the MT flag
90	mov 1, %g1
91	stx %g0, [%l5] ! release mutex
92	stxa %g1, [%g3] 0x41 ! Start with T0
93
94	continue:
95	stx %g0, [%l5] ! release mutex
96
97	! }}}
98
99	test1:
100	wrpr %g0, 0x0, %pstate ! disable IE
101
102
103	setup_for_cwq_int:
104
105	wr %g0, 0x40, %asi
106	stxa %g0, [%g0 + ASI_SPU_CWQ_CSR] %asi
107	!# allocate control word queue (e.g., setup head/tail/first/last registers)
108	set CWQ_BASE, %g6
109
110	!# write base addr to first, head, and tail ptr
111	!# first store to first
112	stxa %g6, [%g0 + ASI_SPU_CWQ_FIRST] %asi !# first store to first
113
114	stxa %g6, [%g0 + ASI_SPU_CWQ_HEAD] %asi !# then to head
115	stxa %g6, [%g0 + ASI_SPU_CWQ_TAIL] %asi !# then to tail
116	setx CWQ_LAST, %g1, %g5 !# then end of CWQ region to LAST
117	stxa %g5, [%g0 + ASI_SPU_CWQ_LAST] %asi
118
119	!# set CWQ control word ([39:37] is strand ID ..)
120	best_set_reg(0x20610000, %g1, %g2) !# Control Word
121	ldxa [%g0]0x63, %g1 ! get my TID for interrupt steering ..
122	sllx %g1, 5, %g1
123	or %g2, %g1, %g2
124	sllx %g2, 32, %g2
125
126	!# write CWQ entry (%g6 points to CWQ)
127	stx %g2, [%g6 + 0x0]
128
129	setx msg, %g1, %g2
130	stx %g2, [%g6 + 0x8] !# source address
131
132	stx %g0, [%g6 + 0x10] !# Authentication Key Address (40-bit)
133	stx %g0, [%g6 + 0x18] !# Authentication IV Address (40-bit)
134	stx %g0, [%g6 + 0x20] !# Authentication FSAS Address (40-bit)
135	stx %g0, [%g6 + 0x28] !# Encryption Key Address (40-bit)
136	stx %g0, [%g6 + 0x30] !# Encryption Initialization Vector Address (40-bit)
137
138	setx results, %g1, %o3
139	stx %o3, [%g6 + 0x38] !# Destination Address (40-bit)
140
141	membar #Sync
142
143	ldxa [%g0 + ASI_SPU_CWQ_TAIL] %asi, %g2
144	add %g2, 0x40, %g2
145	stxa %g2, [%g0 + ASI_SPU_CWQ_TAIL] %asi
146
147	!# Kick off the CWQ operation by writing to the CWQ_CSR
148	!# Set the enabled bit and reset the other bits
149	or %g0, 0x1, %g1
150	stxa %g1, [%g0 + ASI_SPU_CWQ_CSR] %asi
151
152
153	setup_for_modint:
154
155	!# 21:0 == 00 0010 0000 0000 0011 1111
156	!# 20:18 TID == 0..7
157	!# 17 cause interrupt
158	!# 12:08 modular addition (1001)
159	!# 12:08 load MA mem (0000)
160	!# 07:00 length = 63
161
162	wr %g0, 0x40, %asi
163	setx 0x2003f, %g1, %g3
164	ldxa [%g0]0x63, %g1 ! get my TID for interrupt steering ..
165	sllx %g1, 18, %g1
166	or %g3, %g1, %g3
167	stxa %g3, [%g0 + 0x80] %asi
168
169
170	mov 100, %g1
171	wait_for_int:
172	brnz,a %g1, wait_for_int
173	dec %g1
174
175	halt1:
176	rdhpr %halt, %g7
177
178	wrpr %g0, 0x2, %pstate ! enable IE
179
180	! Finish if not MT
181	brz %l1, done_thread
182	nop
183
184	! If MT, shift mask, unpark next thread and finish
185	ldx [%l4], %l3
186	sllx %l3, 1, %l3
187	mov 0x60, %g1
188	stxa %l3, [%g1]0x41
189	stx %l3, [%l4]
190	nop
191
192
193	/*******************************************************
194	* Exit code
195	*******************************************************/
196
197	done_thread:
198	nop
199	ta T_GOOD_TRAP
200	nop
201
202	/************************************************************************
203	Test case data start
204	************************************************************************/
205	.data
206	is_mt :
207	.xword 0x0
208	park_mask:
209	.xword 0x1
210	mutex:
211	.xword 0
212
213	SECTION .CWQ_DATA DATA_VA =0x4000
214	attr_data {
215	Name = .CWQ_DATA
216	hypervisor
217	}
218
219	.data
220	.align 16
221	.global msg
222	msg:
223	.xword 0xad32fa52374cc6ba
224	.xword 0x4cbf52280549003a
225
226	.align 16
227	.global results
228	results:
229	.xword 0xDEADBEEFDEADBEEF
230	.xword 0xDEADBEEFDEADBEEF
231	!# CWQ data area
232	.align 64
233	.global CWQ_BASE
234	CWQ_BASE:
235	.xword 0xAAAAAAAAAAAAAAA
236	.xword 0xAAAAAAAAAAAAAAA
237	.xword 0xAAAAAAAAAAAAAAA
238	.xword 0xAAAAAAAAAAAAAAA
239	.xword 0xAAAAAAAAAAAAAAA
240	.xword 0xAAAAAAAAAAAAAAA
241	.xword 0xAAAAAAAAAAAAAAA
242	.xword 0xAAAAAAAAAAAAAAA
243	.xword 0xAAAAAAAAAAAAAAA
244	.xword 0xAAAAAAAAAAAAAAA
245	.xword 0xAAAAAAAAAAAAAAA
246	.xword 0xAAAAAAAAAAAAAAA
247	.xword 0xAAAAAAAAAAAAAAA
248	.xword 0xAAAAAAAAAAAAAAA
249	.xword 0xAAAAAAAAAAAAAAA
250	.xword 0xAAAAAAAAAAAAAAA
251	.xword 0xAAAAAAAAAAAAAAA
252	.xword 0xAAAAAAAAAAAAAAA
253	.xword 0xAAAAAAAAAAAAAAA
254	.xword 0xAAAAAAAAAAAAAAA
255	.xword 0xAAAAAAAAAAAAAAA
256	.xword 0xAAAAAAAAAAAAAAA
257	.xword 0xAAAAAAAAAAAAAAA
258	.xword 0xAAAAAAAAAAAAAAA
259	.global CWQ_LAST
260	.align 64
261	CWQ_LAST:
262	.word 0x0
263