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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / uarch / tlu / diag / tlu_rand01_ind_01.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: tlu_rand01_ind_01.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define TRAP_SECT_HV_ALSO
39#define DMMU_SKIP_IF_NO_TTE
40#define IMMU_SKIP_IF_NO_TTE
41
42#define MAIN_PAGE_NUCLEUS_ALSO
43#define MAIN_PAGE_HV_ALSO
44
45#define H_T1_Trap_Instruction_0
46#define My_T1_Trap_Instruction_0 \
47 save; \
48 restore; \
49 done ;\
50 nop; nop; nop; nop; nop
51#define H_T1_Trap_Instruction_1
52#define My_T1_Trap_Instruction_1 \
53 save ;\
54 restore ;\
55 done ;\
56 nop; nop; nop; nop; nop
57#define H_T1_Trap_Instruction_2
58#define My_T1_Trap_Instruction_2 \
59 save ;\
60 restore ;\
61 done ;\
62 nop; nop; nop; nop; nop
63#define H_T1_Trap_Instruction_3
64#define My_T1_Trap_Instruction_3 \
65 save ;\
66 restore ;\
67 done ;\
68 nop; nop; nop; nop; nop
69#define H_T1_Trap_Instruction_4
70#define My_T1_Trap_Instruction_4 \
71 save ;\
72 restore ;\
73 done ;\
74 nop; nop; nop; nop; nop
75#define H_T1_Trap_Instruction_5
76#define My_T1_Trap_Instruction_5 \
77 save ;\
78 restore ;\
79 done ;\
80 nop; nop; nop; nop; nop
81
82#define H_HT0_Trap_Instruction_0
83#define My_HT0_Trap_Instruction_0 \
84 save; \
85 restore; \
86 done ;\
87 nop; nop; nop; nop; nop
88#define H_HT0_Trap_Instruction_1
89#define My_HT0_Trap_Instruction_1 \
90 save ;\
91 restore ;\
92 done ;\
93 nop; nop; nop; nop; nop
94#define H_HT0_Trap_Instruction_2
95#define My_HT0_Trap_Instruction_2 \
96 save ;\
97 restore ;\
98 done ;\
99 nop; nop; nop; nop; nop
100#define H_HT0_Trap_Instruction_3
101#define My_HT0_Trap_Instruction_3 \
102 save ;\
103 restore ;\
104 done ;\
105 nop; nop; nop; nop; nop
106#define H_HT0_Trap_Instruction_4
107#define My_HT0_Trap_Instruction_4 \
108 save ;\
109 restore ;\
110 done ;\
111 nop; nop; nop; nop; nop
112#define H_HT0_Trap_Instruction_5
113#define My_HT0_Trap_Instruction_5 \
114 save ;\
115 restore ;\
116 done ;\
117 nop; nop; nop; nop; nop
118#define H_HT0_Mem_Address_Not_Aligned_0x34
119#define My_HT0_Mem_Address_Not_Aligned_0x34 \
120 save ;\
121 restore ;\
122 done ;\
123 nop; nop; nop; nop; nop
124#define H_HT0_Illegal_instruction_0x10
125#define My_HT0_Illegal_instruction_0x10 \
126 save; \
127 restore; \
128 done; \
129 nop; nop; nop; nop; nop
130#define H_HT0_DAE_so_page_0x30
131#define My_HT0_DAE_so_page_0x30 \
132 save; \
133 restore;\
134 done; \
135 nop; nop; nop; nop; nop
136#define H_HT0_DAE_invalid_asi_0x14
137#define SUN_H_HT0_DAE_invalid_asi_0x14 \
138 save; \
139 restore;\
140 done; \
141 nop; nop; nop; nop; nop
142#define H_HT0_DAE_privilege_violation_0x15
143#define SUN_H_HT0_DAE_privilege_violation_0x15 \
144 save; \
145 restore;\
146 done; \
147 nop; nop; nop; nop; nop
148#define H_HT0_Privileged_Action_0x37
149#define My_HT0_Privileged_Action_0x37 \
150 save; \
151 restore;\
152 done; \
153 nop; nop; nop; nop; nop
154#define H_HT0_Lddf_Mem_Address_Not_Aligned_0x35
155#define My_HT0_Lddf_Mem_Address_Not_Aligned_0x35 \
156 save; \
157 restore;\
158 done; \
159 nop; nop; nop; nop; nop
160#define H_HT0_Fp_exception_other_0x22
161#define My_HT0_Fp_exception_other_0x22 \
162 save; \
163 restore;\
164 done; \
165 nop; nop; nop; nop; nop
166
167#define H_HT0_mem_real_range_0x2d
168#define SUN_H_HT0_mem_real_range_0x2d \
169 done;nop
170
171#define H_HT0_mem_address_range_0x2e
172#define SUN_H_HT0_mem_address_range_0x2e \
173 done;nop
174
175#define H_HT0_Instruction_address_range_0x0d
176#define SUN_H_HT0_Instruction_address_range_0x0d \
177 done;nop
178
179#include "hboot.s"
180.text
181.global main
182main:
183
184 !Start with TL 1
185 ta T_CHANGE_TO_TL1
186
187 ! Set up ld/st area per thread
188 ta T_RD_THID
189 mov %o1, %l6
190 umul %l6, 256, %l7
191 setx user_data_start, %g1, %g3
192 add %l7, %g3, %l7
193
194! Register init code
195
196 setx 0xc2bca5a1ead703f1, %g1, %g0
197 setx 0x7aeb2ca91ca302ef, %g1, %g1
198 setx 0xb327ef60281e9f0a, %g1, %g2
199 setx 0xce52f1d1b3a66741, %g1, %g3
200 setx 0xbaac0317a97b9bc9, %g1, %g4
201 setx 0x6980494fa6ee5461, %g1, %g5
202 setx 0x499680aec3b59630, %g1, %g6
203 setx 0x43949fddcb47f4a3, %g1, %g7
204 setx 0xcf996c4f2dbf20c3, %g1, %r16
205 setx 0x304610e7585a5cd0, %g1, %r17
206 setx 0x58b8bdea91825422, %g1, %r18
207 setx 0xa0c5db68c0cad4e0, %g1, %r19
208 setx 0xeda6a7a11c5d55f0, %g1, %r20
209 setx 0x876a47f9526be42a, %g1, %r21
210 setx 0x99e28a6435151c33, %g1, %r22
211 setx 0xf4ee33d89aec1ac4, %g1, %r23
212 setx 0x7d6164af63960b7c, %g1, %r24
213 setx 0x17dde98fc47b6aba, %g1, %r25
214 setx 0x9ad6887bf8f5d0e3, %g1, %r26
215 setx 0xc3ab8d70ffe20ff6, %g1, %r27
216 setx 0xc02e5ba84a025f8c, %g1, %r28
217 setx 0x7c508ded2790fc1d, %g1, %r29
218 setx 0x10c4ce668aa92ea9, %g1, %r30
219 setx 0xe381667f64296dc7, %g1, %r31
220 save
221 setx 0x8be43a4b8d8da77e, %g1, %r16
222 setx 0xf29ce5455dea14ca, %g1, %r17
223 setx 0x1976792221dd0074, %g1, %r18
224 setx 0x21090022c04b73aa, %g1, %r19
225 setx 0x0c801b9e7e2c1019, %g1, %r20
226 setx 0xe877730e1027522e, %g1, %r21
227 setx 0x8b25a1d422789004, %g1, %r22
228 setx 0x02e9928777690a27, %g1, %r23
229 setx 0x6953ec3beb0eb030, %g1, %r24
230 setx 0xa33238ea211a835e, %g1, %r25
231 setx 0xc7faa196654c584c, %g1, %r26
232 setx 0x6c1719d27f4445fd, %g1, %r27
233 setx 0xbdeb1a2e59876deb, %g1, %r28
234 setx 0xe6c1086711adb70c, %g1, %r29
235 setx 0xa2b8c0c7bb8b5353, %g1, %r30
236 setx 0xe1d4ebe583f86944, %g1, %r31
237 save
238 setx 0x256f6bdb827594a0, %g1, %r16
239 setx 0xba4dfeccb29d0286, %g1, %r17
240 setx 0xd948057971a00356, %g1, %r18
241 setx 0x82c4dc861be665e7, %g1, %r19
242 setx 0x5de694a67332f62e, %g1, %r20
243 setx 0x4cd867e2f0309b59, %g1, %r21
244 setx 0x8f2a8c6a43bd8522, %g1, %r22
245 setx 0x7e7bf981b60bd31d, %g1, %r23
246 setx 0xdd9d80c99418ec76, %g1, %r24
247 setx 0x640930dfd3c1eeb7, %g1, %r25
248 setx 0xd9e1c58011ae4bfd, %g1, %r26
249 setx 0xbf3b6710996e57ac, %g1, %r27
250 setx 0x32530f37814e089e, %g1, %r28
251 setx 0xe28ce2e28e1facbb, %g1, %r29
252 setx 0xad1a23fc138a5e57, %g1, %r30
253 setx 0x03a5ba207bab7b5f, %g1, %r31
254 restore
255 restore
256 mov 0x35, %r30
257 .word 0x83504000 ! 3: RDPR_TNPC rdpr %tnpc, %r1
258 .word 0x36700001 ! 12: BPGE <illegal instruction>
259 .word 0x26800001 ! 19: BL bl,a <label_0x1>
260 .word 0x99d02033 ! 34: Tcc_I tgu icc_or_xcc, %r0 + 51
261 .word 0x9050800f ! 45: UMUL_R umul %r2, %r15, %r8
262 .word 0x8a81e001 ! 46: ADDcc_I addcc %r7, 0x0001, %r5
263 .word 0x3e800001 ! 57: BVC bvc,a <label_0x1>
264 .word 0x9fd02035 ! 60: Tcc_I tvc icc_or_xcc, %r0 + 53
265 .word 0x85d02030 ! 85: Tcc_I tle icc_or_xcc, %r0 + 48
266 .word 0x9150c000 ! 86: RDPR_TT rdpr %tt, %r8
267 .word 0x24800001 ! 87: BLE ble,a <label_0x1>
268 .word 0xd0d02001 ! 88: LDSHA_I ldsha [%r0, + 0x0001] %asi, %r8
269 .word 0x22700001 ! 93: BPE <illegal instruction>
270 .word 0xd0c80291 ! 94: LDSBA_R ldsba [%r0, %r17] 0x14, %r8
271 .word 0x9e510001 ! 103: UMUL_R umul %r4, %r1, %r15
272 mov 0x30, %r30
273 .word 0x9bd0001e ! 104: Tcc_R tcc icc_or_xcc, %r0 + %r30
274 ta T_CHANGE_NONPRIV ! macro
275 ta T_CHANGE_NONHPRIV ! macro
276 .word 0xd8782001 ! 111: SWAP_I swap %r12, [%r0 + 0x0001]
277 mov 0x35, %r30
278 .word 0x9bd0001e ! 116: Tcc_R tcc icc_or_xcc, %r0 + %r30
279 mov 0x31, %r30
280 .word 0x8fd0001e ! 123: Tcc_R tvs icc_or_xcc, %r0 + %r30
281 .word 0x3c800001 ! 134: BPOS bpos,a <label_0x1>
282 .word 0x2c800001 ! 139: BNEG bneg,a <label_0x1>
283 .word 0xd847c000 ! 140: LDSW_R ldsw [%r31 + %r0], %r12
284 .word 0x2a800001 ! 145: BCS bcs,a <label_0x1>
285 .word 0x836ba001 ! 154: SDIVX_I sdivx %r14, 0x0001, %r1
286 .word 0x2c800001 ! 157: BNEG bneg,a <label_0x1>
287 mov 0x35, %r30
288 .word 0x81d0001e ! 166: Tcc_R tn icc_or_xcc, %r0 + %r30
289 .word 0x38800001 ! 185: BGU bgu,a <label_0x1>
290 .word 0xc207c000 ! 208: LDUW_R lduw [%r31 + %r0], %r1
291 .word 0xc20fc000 ! 211: LDUB_R ldub [%r31 + %r0], %r1
292 .word 0xc25fe001 ! 212: LDX_I ldx [%r31 + 0x0001], %r1
293 .word 0x87802004 ! 229: WRASI_I wr %r0, 0x0004, %asi
294 mov 0x30, %r30
295 .word 0x97d0001e ! 238: Tcc_R tge icc_or_xcc, %r0 + %r30
296 mov 0x34, %r30
297 .word 0x81d0001e ! 267: Tcc_R tn icc_or_xcc, %r0 + %r30
298 mov 0x31, %r30
299 .word 0x97d0001e ! 268: Tcc_R tge icc_or_xcc, %r0 + %r30
300 .word 0x90684009 ! 271: UDIVX_R udivx %r1, %r9, %r8
301 .word 0x87d02032 ! 280: Tcc_I tl icc_or_xcc, %r0 + 50
302 .word 0x87802054 ! 289: WRASI_I wr %r0, 0x0054, %asi
303 .word 0xd007e001 ! 294: LDUW_I lduw [%r31 + 0x0001], %r8
304 mov 0x30, %r30
305 .word 0x9fd0001e ! 295: Tcc_R tvc icc_or_xcc, %r0 + %r30
306 mov 0x34, %r30
307 .word 0x99d0001e ! 296: Tcc_R tgu icc_or_xcc, %r0 + %r30
308 mov 0x34, %r30
309 .word 0x97d0001e ! 301: Tcc_R tge icc_or_xcc, %r0 + %r30
310 .word 0x9d69e001 ! 304: SDIVX_I sdivx %r7, 0x0001, %r14
311 ta T_CHANGE_NONPRIV ! macro
312 .word 0x8bd02034 ! 340: Tcc_I tcs icc_or_xcc, %r0 + 52
313 .word 0xd4796001 ! 353: SWAP_I swap %r10, [%r5 + 0x0001]
314 mov 0x35, %r30
315 .word 0x97d0001e ! 358: Tcc_R tge icc_or_xcc, %r0 + %r30
316 .word 0x946ae001 ! 359: UDIVX_I udivx %r11, 0x0001, %r10
317 .word 0x3c700001 ! 366: BPPOS <illegal instruction>
318 .word 0x3c700001 ! 367: BPPOS <illegal instruction>
319 mov 0x31, %r30
320 .word 0x97d0001e ! 372: Tcc_R tge icc_or_xcc, %r0 + %r30
321 mov 0x34, %r30
322 .word 0x83d0001e ! 377: Tcc_R te icc_or_xcc, %r0 + %r30
323 .word 0x26800001 ! 406: BL bl,a <label_0x1>
324 .word 0x8dd02031 ! 407: Tcc_I tneg icc_or_xcc, %r0 + 49
325 .word 0xc6f90029 ! 414: SWAPA_R swapa %r3, [%r4 + %r9] 0x01
326 .word 0xc607e001 ! 429: LDUW_I lduw [%r31 + 0x0001], %r3
327 .word 0xc657e001 ! 434: LDSH_I ldsh [%r31 + 0x0001], %r3
328 mov 0x35, %r30
329 .word 0x8fd0001e ! 439: Tcc_R tvs icc_or_xcc, %r0 + %r30
330 .word 0xc6882001 ! 450: LDUBA_I lduba [%r0, + 0x0001] %asi, %r3
331 .word 0x8dd02030 ! 455: Tcc_I tneg icc_or_xcc, %r0 + 48
332 .word 0x81d02034 ! 474: Tcc_I tn icc_or_xcc, %r0 + 52
333 ta T_CHANGE_HPRIV ! macro
334 .word 0x87d02035 ! 488: Tcc_I tl icc_or_xcc, %r0 + 53
335 .word 0x2e700001 ! 489: BPVS <illegal instruction>
336 .word 0x9fd02031 ! 496: Tcc_I tvc icc_or_xcc, %r0 + 49
337 .word 0x20800001 ! 507: BN bn,a <label_0x1>
338 .word 0x94d1e001 ! 508: UMULcc_I umulcc %r7, 0x0001, %r10
339 .word 0x91d02034 ! 509: Tcc_I ta icc_or_xcc, %r0 + 52
340 .word 0x92682001 ! 510: UDIVX_I udivx %r0, 0x0001, %r9
341 .word 0x97d02032 ! 513: Tcc_I tge icc_or_xcc, %r0 + 50
342 .word 0x9fd02033 ! 514: Tcc_I tvc icc_or_xcc, %r0 + 51
343 .word 0x87802004 ! 529: WRASI_I wr %r0, 0x0004, %asi
344 mov 0x33, %r30
345 .word 0x9bd0001e ! 532: Tcc_R tcc icc_or_xcc, %r0 + %r30
346 .word 0x94d26001 ! 533: UMULcc_I umulcc %r9, 0x0001, %r10
347 .word 0x87a009e0 ! 536: FDIVq dis not found
348
349 .word 0x87802016 ! 539: WRASI_I wr %r0, 0x0016, %asi
350 .word 0xc6c02001 ! 544: LDSWA_I ldswa [%r0, + 0x0001] %asi, %r3
351 mov 0x30, %r30
352 .word 0x95d0001e ! 563: Tcc_R tg icc_or_xcc, %r0 + %r30
353 ta T_CHANGE_HPRIV ! macro
354 .word 0x20800001 ! 571: BN bn,a <label_0x1>
355 mov 0x33, %r30
356 .word 0x89d0001e ! 572: Tcc_R tleu icc_or_xcc, %r0 + %r30
357 .word 0x3c800001 ! 579: BPOS bpos,a <label_0x1>
358 .word 0x97d02031 ! 586: Tcc_I tge icc_or_xcc, %r0 + 49
359 .word 0xc60fc000 ! 597: LDUB_R ldub [%r31 + %r0], %r3
360 .word 0xc6d82001 ! 598: LDXA_I ldxa [%r0, + 0x0001] %asi, %r3
361 .word 0xc6882001 ! 601: LDUBA_I lduba [%r0, + 0x0001] %asi, %r3
362 .word 0x36700001 ! 606: BPGE <illegal instruction>
363 .word 0x88828009 ! 609: ADDcc_R addcc %r10, %r9, %r4
364 .word 0x24800001 ! 614: BLE ble,a <label_0x1>
365 .word 0x3a800001 ! 615: BCC bcc,a <label_0x1>
366 .word 0x89d02030 ! 618: Tcc_I tleu icc_or_xcc, %r0 + 48
367 .word 0x92002001 ! 621: ADD_I add %r0, 0x0001, %r9
368 .word 0x30700001 ! 622: BPA <illegal instruction>
369 .word 0x85d02035 ! 631: Tcc_I tle icc_or_xcc, %r0 + 53
370 .word 0xd247c000 ! 638: LDSW_R ldsw [%r31 + %r0], %r9
371 .word 0x97d02030 ! 643: Tcc_I tge icc_or_xcc, %r0 + 48
372 .word 0xd25fe001 ! 666: LDX_I ldx [%r31 + 0x0001], %r9
373 mov 0x33, %r30
374 .word 0x8bd0001e ! 675: Tcc_R tcs icc_or_xcc, %r0 + %r30
375 mov 0x33, %r30
376 .word 0x87d0001e ! 690: Tcc_R tl icc_or_xcc, %r0 + %r30
377 .word 0xd24fc000 ! 695: LDSB_R ldsb [%r31 + %r0], %r9
378 .word 0xd25fc000 ! 698: LDX_R ldx [%r31 + %r0], %r9
379 .word 0x24800001 ! 701: BLE ble,a <label_0x1>
380 .word 0x89d02031 ! 704: Tcc_I tleu icc_or_xcc, %r0 + 49
381 .word 0x87802004 ! 717: WRASI_I wr %r0, 0x0004, %asi
382 mov 0x32, %r30
383 .word 0x81d0001e ! 718: Tcc_R tn icc_or_xcc, %r0 + %r30
384 ta T_CHANGE_NONPRIV ! macro
385 .word 0x8202a001 ! 780: ADD_I add %r10, 0x0001, %r1
386 .word 0x26800001 ! 817: BL bl,a <label_0x1>
387 .word 0x8dd02031 ! 818: Tcc_I tneg icc_or_xcc, %r0 + 49
388 .word 0x2a800001 ! 819: BCS bcs,a <label_0x1>
389 .word 0x93500000 ! 820: RDPR_TPC rdpr %tpc, %r9
390 mov 0x30, %r30
391 .word 0x85d0001e ! 835: Tcc_R tle icc_or_xcc, %r0 + %r30
392 mov 0x31, %r30
393 .word 0x8fd0001e ! 846: Tcc_R tvs icc_or_xcc, %r0 + %r30
394 .word 0x99d02033 ! 847: Tcc_I tgu icc_or_xcc, %r0 + 51
395 .word 0xd2d02001 ! 848: LDSHA_I ldsha [%r0, + 0x0001] %asi, %r9
396 .word 0xd247e001 ! 851: LDSW_I ldsw [%r31 + 0x0001], %r9
397 .word 0x944b0009 ! 852: MULX_R mulx %r12, %r9, %r10
398 .word 0x89d02035 ! 853: Tcc_I tleu icc_or_xcc, %r0 + 53
399 .word 0x24700001 ! 856: BPLE <illegal instruction>
400 .word 0x8e782001 ! 863: SDIV_I sdiv %r0, 0x0001, %r7
401 .word 0x9c4be001 ! 884: MULX_I mulx %r15, 0x0001, %r14
402 .word 0x87802010 ! 889: WRASI_I wr %r0, 0x0010, %asi
403 .word 0x2c800001 ! 890: BNEG bneg,a <label_0x1>
404 .word 0x9ba149ca ! 901: FDIVd fdivd %f36, %f10, %f44
405 .word 0xda57c000 ! 906: LDSH_R ldsh [%r31 + %r0], %r13
406 .word 0xda57c000 ! 927: LDSH_R ldsh [%r31 + %r0], %r13
407 .word 0x8e79e001 ! 932: SDIV_I sdiv %r7, 0x0001, %r7
408 .word 0xce4fe001 ! 939: LDSB_I ldsb [%r31 + 0x0001], %r7
409 .word 0xce0fc000 ! 950: LDUB_R ldub [%r31 + %r0], %r7
410 mov 0x30, %r30
411 .word 0x8fd0001e ! 959: Tcc_R tvs icc_or_xcc, %r0 + %r30
412 .word 0x82d16001 ! 962: UMULcc_I umulcc %r5, 0x0001, %r1
413 mov 0x31, %r30
414 .word 0x85d0001e ! 973: Tcc_R tle icc_or_xcc, %r0 + %r30
415 .word 0x87802054 ! 980: WRASI_I wr %r0, 0x0054, %asi
416 .word 0x3e700001 ! 995: BPVC <illegal instruction>
417
418
419.data
420user_data_start:
421 .xword 0x249615e83e8f6650
422 .xword 0x881f5923f8466c52
423 .xword 0x04461c361e9ed943
424 .xword 0xe86a0cd7b842e088
425 .xword 0x9f9c38affec93dda
426 .xword 0x150f2df8fbb816b7
427 .xword 0xb5573066003687c3
428 .xword 0xf791216fe8757a24
429 .xword 0x0a9b78fe1a0e768d
430 .xword 0xfa6df29b0cb5f22b
431 .xword 0x606e7090d404079c
432 .xword 0x8d42a31be36e06ae
433 .xword 0x6b0204e7a1422697
434 .xword 0x4d0ca9ade5b65648
435 .xword 0x0451f55c1ba24929
436 .xword 0xa05f431f777d2fa2
437
438
439.text
440 ta T_GOOD_TRAP
441.data
442 .xword 0x0
443
444#if 0
445!!# /*
446!!# output of /import/bw/tools/local/indra-release/indra,1.4.11/bin/ijpp (indrajal preprocessor) - Thu Mar 25 09:21:39 2004
447!!# */
448!!#
449!!# %%section c_declarations
450!!#
451!!#
452!!#
453!!# %%
454!!# %%section control
455!!#
456!!# %%
457!!# %%section init
458!!# {
459!!#
460!!#
461!!# IJ_bind_thread_group("diag.j", 22, th0, 0x01);
462!!#
463!!# // Random 64 bits //
464!!# IJ_set_rvar("diag.j", 25, Rv_rand_64,"64'hrrrrrrrr_rrrrrrrr");
465!!#
466!!# // Register usage - use 0-28 //
467!!# // R31 is memory pointer
468!!# // R30 is trap number register
469!!# //
470!!# IJ_set_ropr_fld("diag.j", 31, ijdefault, Ft_Rs1, "5'b0rrrr");
471!!# IJ_set_ropr_fld("diag.j", 32, ijdefault, Ft_Rs2, "5'b0rrrr");
472!!# IJ_set_ropr_fld("diag.j", 33, ijdefault, Ft_Rd, "5'b0rrrr");
473!!#
474!!# // Load/Store pointer = r31
475!!# IJ_set_ropr_fld("diag.j", 36, Ro_ldst_ptr, Ft_Rs1, "{31}");
476!!#
477!!# // ASI register values
478!!# IJ_set_ropr_fld("diag.j", 39, Ro_wrasi_i, Ft_Rs1, "{0x0}");
479!!# IJ_set_ropr_fld("diag.j", 40, Ro_wrasi_i, Ft_Simm13, "{0x4, 0x10, 0x14, 0x16, 0x45, 0x54}");
480!!#
481!!# // General Ldst ASIs to use .. 50% should be illegal ..
482!!# IJ_set_ropr_fld("diag.j", 43, Ro_nontrap_ldasi, Ft_Imm_Asi, "{0x12,0x14, 0x53..0x64}");
483!!# IJ_set_ropr_fld("diag.j", 44, Ro_nontrap_ldasi, Ft_Rs1, "{0x0}");
484!!# IJ_set_ropr_fld("diag.j", 45, Ro_nontrap_ldasi, Ft_Rs2, "{0x31}");
485!!# IJ_set_ropr_fld("diag.j", 46, Ro_nontrap_ldasi, Ft_Simm13, "{0x0}, 6'brr0000");
486!!#
487!!# // General Ldst alignment to use .. 50% should be illegal ..
488!!# IJ_set_ropr_fld("diag.j", 49, Ro_nontrap_ld, Fm_align_Simm13, "{0x0, 0x7}");
489!!# IJ_set_ropr_fld("diag.j", 50, Ro_nontrap_ld, Ft_Rs1, "{31}");
490!!# IJ_set_ropr_fld("diag.j", 51, Ro_nontrap_ld, Ft_Rs2, "{0}");
491!!#
492!!# // Trap ASI operands
493!!# IJ_set_ropr_fld("diag.j", 54, Ro_traps_asi, Ft_Imm_Asi, "{0x25, 0x72..0x74}");
494!!# IJ_set_ropr_fld("diag.j", 55, Ro_traps_asi, Ft_Rs1, "{0}");
495!!# IJ_set_ropr_fld("diag.j", 56, Ro_trap_ldasi, Ft_Simm13, "{0}");
496!!#
497!!# // Trap #s to use
498!!# IJ_set_ropr_fld("diag.j", 59, Ro_traps_i, Ft_Sw_Trap, "{0x30..0x35 }");
499!!# IJ_set_ropr_fld("diag.j", 60, Ro_traps_i, Ft_Rs1, "{0}");
500!!# IJ_set_ropr_fld("diag.j", 61, Ro_traps_i, Ft_Cond_f2, "{0x0 .. 0xf}");
501!!# IJ_set_ropr_fld("diag.j", 62, Ro_traps_r, Ft_Rs1, "{0}");
502!!# IJ_set_ropr_fld("diag.j", 63, Ro_traps_r, Ft_Rs2, "{30}");
503!!# IJ_set_ropr_fld("diag.j", 64, Ro_traps_r, Ft_Cond_f2, "{0x0 .. 0xf}");
504!!# IJ_set_ropr_fld("diag.j", 65, Ro_traps_r, Ft_Simm13, "{0x30..0x35}");
505!!# IJ_set_rvar("diag.j", 66, Rv_init_trap, "{0x30..0x35}");
506!!#
507!!# // Weights
508!!# IJ_set_rvar("diag.j", 69, wt_high, "{6}");
509!!# IJ_set_rvar("diag.j", 70, wt_med, "{3}");
510!!# IJ_set_rvar("diag.j", 71, wt_low, "{1}");
511!!#
512!!# // Initialize registers ..
513!!# IJ_init_regs_by_setx ("diag.j", 74, th0, 3, 2, Rv_rand_64);
514!!#
515!!# }
516!!#
517!!# %%
518!!# %%section finish
519!!# {
520!!#
521!!#
522!!# int i;
523!!# IJ_printf ("diag.j", 79, th0,"\n\n.data\nuser_data_start:\n");
524!!# for (i = 0; i < 16; i++) {
525!!# IJ_printf ("diag.j", 81, th0,"\t.xword\t0x%016llrx\n", Rv_rand_64);
526!!# }
527!!#
528!!# }
529!!#
530!!# %%
531!!# %%section map
532!!#
533!!# %%
534!!# %%section grammar
535!!#
536!!#
537!!# block: inst | block inst
538!!# {
539!!# IJ_generate ("diag.j", 225, th0, $2);
540!!# };
541!!#
542!!# inst: trap_asr %rvar wt_low
543!!# | trap_asi %rvar wt_low
544!!# | tcc %rvar wt_high
545!!# | ldst_excp %rvar wt_med
546!!# | ldstasi_excp %rvar wt_med
547!!# | change_mode %rvar wt_low
548!!# | alu %rvar wt_med
549!!# | br %rvar wt_med
550!!# | wrasi %rvar wt_low
551!!# ;
552!!#
553!!# change_mode :
554!!# tCHANGE_NONPRIV
555!!# | tCHANGE_PRIV
556!!# | tCHANGE_NONHPRIV
557!!# | tCHANGE_HPRIV
558!!# ;
559!!#
560!!# trap_asr :
561!!# tRDPR_TPC
562!!# | tRDPR_TSTATE
563!!# | tRDPR_TT
564!!# | tRDPR_TNPC
565!!# | tRDPR_TBA
566!!# | tRDPR_TL
567!!# | tRDHPR_HTBA
568!!# | tRDHPR_HPSTATE
569!!# ;
570!!#
571!!# trap_asi : mTRAP_ASI
572!!# asi_load_r %ropr Ro_traps_asi |
573!!# asi_load_i %ropr Ro_traps_asi
574!!# ;
575!!#
576!!# wrasi : tWRASI_I %ropr Ro_wrasi_i
577!!#
578!!# reg_tcc : tTcc_R %ropr Ro_traps_r
579!!# {
580!!# IJ_printf("diag.j", 268, th0, "\tmov 0x%rx, %%r30\n", Rv_init_trap);
581!!# }
582!!# ;
583!!#
584!!# tcc :
585!!# tTcc_I %ropr Ro_traps_i
586!!# | reg_tcc
587!!#
588!!# ;
589!!#
590!!# ldst_excp : mLDST_EXCP
591!!# ldds %ropr Ro_nontrap_ld |
592!!# load_r %ropr Ro_nontrap_ld |
593!!# load_i %ropr Ro_nontrap_ld
594!!#
595!!# ;
596!!#
597!!# ldstasi_excp : mLDSTASI_EXCP
598!!# asi_load_r %ropr Ro_nontrap_ldasi |
599!!# asi_load_r %ropr Ro_nontrap_ldasi
600!!# ;
601!!#
602!!# ldds: tLDD_R | tLDD_I | tLDDA_I | tLDDA_R
603!!# ;
604!!#
605!!# stds: tSTDA_R | tSTDA_I | tSTD_R | tSTD_I
606!!# ;
607!!#
608!!# load_r: tLDSB_R | tLDSH_R | tLDSW_R | tLDUB_R | tLDUH_R | tLDUW_R | tLDX_R
609!!# ;
610!!#
611!!# load_i: tLDSB_I | tLDSH_I | tLDSW_I | tLDUB_I | tLDUH_I | tLDUW_I | tLDX_I
612!!# ;
613!!#
614!!# asi_load_i: tLDSBA_I | tLDSHA_I | tLDSWA_I | tLDUBA_I | tLDUHA_I | tLDUWA_I
615!!# | tLDXA_I
616!!# ;
617!!#
618!!# asi_load_r:tLDSBA_R | tLDSHA_R | tLDSWA_R | tLDUBA_R | tLDUHA_R | tLDUWA_R
619!!# | tLDXA_R
620!!# ;
621!!#
622!!# asi_store_i: tSTBA_I | tSTHA_I | tSTWA_I | tSTXA_I
623!!# ;
624!!#
625!!# asi_store_r: tSTBA_R | tSTHA_R | tSTWA_R | tSTXA_R
626!!# ;
627!!#
628!!# alu :
629!!# tADD_I | tADDcc_R | tADDcc_I | tADDCcc_I |
630!!# tMULX_R | tMULX_I | tUMUL_R | tUMULcc_R | tUMULcc_I |
631!!# tSMULcc_R | tSDIV_I | tSDIV_R | tSDIVX_R | tSDIVX_I | tUDIVX_R |
632!!# tUDIVX_I | tFDIVs | tFDIVd | tFDIVq | tSWAP_I | tSWAPA_R | tCASA_I
633!!# ;
634!!#
635!!# br : tBA | tBN | tBNE | tBE | tBG | tBLE | tBGE | tBL | tBGU | tBLEU |
636!!# tBCC | tBCS | tBPOS | tBNEG | tBVC | tBVS | tBPA | tBPN | tBPNE |
637!!# tBPE | tBPG | tBPLE | tBPGE | tBPL | tBPGU | tBPLEU | tBPCC | tBPCS |
638!!# tBPPOS | tBPNEG | tBPVC | tBPVS
639!!# ;
640!!#
641!!#
642!!#
643!!#
644!!# %%
645!!# %%section cbfunc
646!!#
647!!# %%
648!!# %%section stat
649!!#
650!!# %%
651#endif
Full OpenSPARC design & verification tarball including full HDL.