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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / cmp8.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cmp8.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef SYSNAME
36#define SYSNAME cmp8
37#define sys(x) cmp8_ ## x
38#define CMP
39#define CMP8
40#define ALL_THREADS 64
41#endif
42
43
44////////////////////////////////////////////////////////////////////////////////////////////
45//
46// added this group of tests for OpenSparc T2 (called cmp8_mini_T2)
47//
48////////////////////////////////////////////////////////////////////////////////////////////
49
50
51
52<sys(mini_T2) sys=cmp8>
53<runargs -sys=cmp8 -tg_seed=1 >
54<runargs -sas -vcs_run_args=+show_delta>
55
56
57// has 7 tests that should pass
58
59<cmp8_lsu_share name=cmp8_lsu_share>
60<runargs -vcs_run_args=+thread=all -midas_args=-allow_tsb_conflicts>
61st_blk st_blk.s
62ldst_sync ldst_sync.s
63</runargs>
64
65</cmp8_lsu_share>
66
67
68<cmp8_lsu_fast name=cmp8_lsu_fast>
69lsu_casa_std_pst0 lsu_casa_std_pst0.s -vcs_run_args=+thread=all
70
71</cmp8_lsu_fast>
72
73<cmp8_mpgen name=cmp8_mpgen>
74<runargs -vcs_run_args=+EIGHT_CORE_DTM2_TESTER>
75<runargs -sas_run_args=-DTSO_CHECKER>
76<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>
77
78mpgen_tso_one_bank mpgen_tso_one_bank.s
79mpgen_dynamic_pwr_mgmt mpgen_dynamic_pwr_mgmt.s
80</runargs>
81</runargs>
82</runargs>
83
84</cmp8_mpgen>
85
86<cmp8_lsu_special name=cmp8_lsu_special>
87<runargs -fast_boot -midas_args=-allow_tsb_conflicts -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+show_load -vcs_run_args=+show_delta -finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -vcs_run_args=+8_FBDIMMS -midas_args=-DL2_REG_PROG -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2cpx_errmon_off>
88
89block_load_store niagara2_bldst.s
90
91</runargs>
92</cmp8_lsu_special>
93
94<cmp8_tlu name=cmp8_tlu>
95<runargs -rtl_timeout=20000 -vcs_run_args=+skt_timeout=20000 -vcs_run_args=+th_timeout=50000>
96tlu_fcrand05_ind_14 tlu_fcrand05_ind_14.s
97</runargs>
98</cmp8_tlu>
99
100
101
102</runargs>
103</runargs>
104</sys(mini_T2)>
105
106
107////////////////////////////////////////////////////////////////////////////////////////////////////
108
109
110////////////////////////////////////////////////////////////////////////////////////////////
111//
112// added this group of tests for OpenSparc T2 (called cmp8_all_T2)
113//
114////////////////////////////////////////////////////////////////////////////////////////////
115
116
117
118
119<sys(all_T2) sys=cmp8>
120<runargs -sys=cmp8 -tg_seed=1>
121<runargs -nosas -vcs_run_args=+show_delta>
122
123
124
125<core_qualify name=core_qualify>
126// Always run with TSO_CHECKER enabled
127<runargs -sas_run_args=-DTSO_CHECKER>
128
129
130// --- tsotool diags // {{{
131<runargs -fast_boot -midas_args=-allow_tsb_conflicts -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+show_load -vcs_run_args=+show_delta -finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -vcs_run_args=+8_FBDIMMS -midas_args=-DL2_REG_PROG -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2cpx_errmon_off>
132n2_8t-fullraw n2_8t-fullraw.s
133n2_8t-bstld n2_8t-bstld.s
134niagara2_bldst niagara2_bldst.s
135n2_64t_ldcasxa_8bank n2_64t_ldcasxa_8bank.s
136</runargs>
137// --- tsotool diags // }}}
138
139//---ccx diag real 64 threads {{{
140<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -midas_args=-DPORTABLE_CORE -vcs_run_args=+l2esr_mon_off -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+8_FBDIMMS -vcs_run_args=+l2cpx_errmon_off>
141#if(!defined FC8 && !defined CMP8)
142n2_st_atomic_8t8b n2_st_atomic_8t8b.s
143#endif
144</runargs>
145//---ccx diag real 64 threads }}}
146
147
148//---MPGen diags {{{
149<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>
150mpgen_dynamic_caches mpgen_dynamic_caches.s
151mpgen_dynamic_pwr_mgmt mpgen_dynamic_pwr_mgmt.s
152mpgen_tso_one_bank mpgen_tso_one_bank.s
153mpgen_tso_all_banks mpgen_tso_all_banks.s
154mpgen_tso_ba_all_banks mpgen_tso_ba_all_banks.s
155mpgen_tso_atomic_one_bank mpgen_tso_atomic_one_bank.s
156mpgen_tso_atomic_all_banks mpgen_tso_atomic_all_banks.s
157
158#if(!defined FC && !defined CMP8)
159mpgen_semi_full_isa_1 mpgen_semi_full_isa_1.s
160mpgen_semi_full_isa_2 mpgen_semi_full_isa_2.s
161mpgen_semi_full_isa_3 mpgen_semi_full_isa_3.s
162mpgen_ldst_mix mpgen_ldst_mix.s
163mpgen_ldst_all_l2_banks mpgen_ldst_all_l2_banks.s
164mpgen_ldst_int_no_asi mpgen_ldst_int_no_asi.s
165mpgen_tso_ba_one_bank mpgen_tso_ba_one_bank.s
166mpgen_tso_atomic_asi_one_bank mpgen_tso_atomic_asi_one_bank.s
167mpgen_tso_atomic_asi_all_banks mpgen_tso_atomic_asi_all_banks.s
168#endif
169
170</runargs>
171//---MPGen diags }}}
172
173//---TLU_RAND5 diags {{{
174<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+l2cpx_errmon_off>
175tlu_fcrand05_ind_14 tlu_fcrand05_ind_14.s
176// fcrand05_rand_38 fcrand05_rand_38.s -midas_args=-DMULTIPASS=1
177
178#if(!defined FC && !defined CMP8 )
179fcrand05_rand_4 fcrand05_rand_4.s -midas_args=-DMULTIPASS=1
180fcrand05_rand_37 fcrand05_rand_37.s -midas_args=-DMULTIPASS=1
181fcrand05_rand_43 fcrand05_rand_43.s -midas_args=-DMULTIPASS=1
182fcrand05_rand_88 fcrand05_rand_88.s -midas_args=-DMULTIPASS=1
183#endif
184
185</runargs>
186//---TLU_RAND5 diags }}}
187
188</runargs>
189</core_qualify>
190
191<lsu_fast name=lsu_fast>
192
193 dcache_diag_test_0 dcache_diag_test_0.s -nosas -vcs_run_args=+gchkr_off
194 lsu_dcache_diagnostic lsu_dcache_diagnostic.s -nosas -vcs_run_args=+gchkr_off
195
196
197 <runargs -midas_args=-allow_tsb_conflicts>
198
199 lsu_ie_01 lsu_ie_01.s
200 lsu_ie_02 lsu_ie_02.s
201 lsu_ie_03 lsu_ie_03.s
202 lsu_ie_04 lsu_ie_04.s
203 lsu_ie_05 lsu_ie_05.s
204 lsu_ie_06 lsu_ie_06.s
205 lsu_ie_07 lsu_ie_07.s
206 lsu_ie_08 lsu_ie_08.s
207 lsu_ie_09 lsu_ie_09.s
208 lsu_ie_10 lsu_ie_10.s
209 lsu_hang_cwp lsu_hang_cwp.s -vcs_run_args=+thread=all -vcs_run_args=+th_timeout=8000 -tg_seed=1
210
211#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
212 lsu_casa_std_pst0 lsu_casa_std_pst0.s
213 lsu_casa_std_pst1 lsu_casa_std_pst1.s
214 lsu_casa_std_pst2 lsu_casa_std_pst2.s
215 lsu_casa_std_pst3 lsu_casa_std_pst3.s
216 lsu_casa_std_pst4 lsu_casa_std_pst4.s
217 lsu_casa_std_pst5 lsu_casa_std_pst5.s
218 lsu_casa_std_pst6 lsu_casa_std_pst6.s
219 lsu_casa_std_pst7 lsu_casa_std_pst7.s
220 lsu_casa_std_pst8 lsu_casa_std_pst8.s
221 lsu_casa_std_pst9 lsu_casa_std_pst9.s
222#endif
223
224 </runargs>
225</lsu_fast>
226#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
227<lsu_long name=lsu_long>
228
229 <runargs -vcs_run_args=+thread=all -sas -midas_args=-allow_tsb_conflicts>
230
231 n2_lsu_arb_hitl1_1.j_652649_rand_0 n2_lsu_arb_hitl1_1.j_652649_rand_0.s -midas_args=-allow_tsb_conflicts
232
233 </runargs>
234</lsu_long>
235#endif
236<lsu_share name=lsu_share>
237
238 <runargs -vcs_run_args=+thread=all -sas -midas_args=-allow_tsb_conflicts>
239
240 ldst_sync_fc0 ldst_sync_fc0.s -vcs_run_args=+hash_on
241 ldst_sync_fc1 ldst_sync_fc1.s -vcs_run_args=+hash_on
242 ldst_sync_fc2 ldst_sync_fc2.s
243 ldst_sync_fc3 ldst_sync_fc3.s
244#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
245 ldst_sync_fc4 ldst_sync_fc4.s -vcs_run_args=+hash_on
246 ldst_sync_fc5 ldst_sync_fc5.s -vcs_run_args=+hash_on
247 ldst_sync_fc6 ldst_sync_fc6.s
248 ldst_sync_fc9 ldst_sync_fc9.s
249 ldst_sync_fc10 ldst_sync_fc10.s -vcs_run_args=+inval_rate=300 -vcs_run_args=+hash_on
250 ldst_sync_fc11 ldst_sync_fc11.s -vcs_run_args=+inval_rate=300 -vcs_run_args=+hash_on
251 ldst_sync_fc13 ldst_sync_fc13.s -vcs_run_args=+inval_rate=400
252 ldst_sync_fc15 ldst_sync_fc15.s -vcs_run_args=+inval_rate=400
253 ldst_sync_fc16 ldst_sync_fc16.s -vcs_run_args=+inval_rate=500
254 ldst_sync_fc17 ldst_sync_fc17.s -vcs_run_args=+inval_rate=500
255 ldst_sync_fc18 ldst_sync_fc18.s -vcs_run_args=+inval_rate=500
256 ldst_sync_fc19 ldst_sync_fc19.s -vcs_run_args=+inval_rate=500
257
258 ifu_basic_ld ifu_basic_ld.s
259 ldst_sync ldst_sync.s
260 st_blk st_blk.s
261 ld_blk ld_blk.s
262 ldst_sync_ldd ldst_sync_ldd.s
263
264#endif
265 </runargs>
266</lsu_share>
267<lsu_asi name=lsu_asi>
268
269<runargs -vcs_run_args=-max_cycle=100000>
270#if (defined SPC || defined CMP1)
271 n2_lsu_asi_ring_01 n2_lsu_asi_ring_01.s -vcs_run_args=+thread=all
272 n2_lsu_asi_ring_02 n2_lsu_asi_ring_02.s -vcs_run_args=+thread=all
273 n2_lsu_asi_ring_03 n2_lsu_asi_ring_03.s -vcs_run_args=+thread=all
274#endif
275</runargs>
276</lsu_asi>
277<lsu_ras name=lsu_ras>
278
279<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off -vcs_run_args=+noDebugModes>
280#ifdef SPC
281 err_dttp_diag err_dttp_diag.s -vcs_run_args=+thread=03
282 err_dtdp_diag err_dtdp_diag.s -vcs_run_args=+thread=03
283
284
285 err_sbdpu_diag_0 err_sbdpu_diag.s
286 err_sbdpu_diag_1 err_sbdpu_diag.s -vcs_run_args=+thread=02
287 err_sbdpu_diag_2 err_sbdpu_diag.s -vcs_run_args=+thread=04
288 err_sbdpu_diag_3 err_sbdpu_diag.s -vcs_run_args=+thread=08
289 err_sbdpu_diag_4 err_sbdpu_diag.s -vcs_run_args=+thread=10
290 err_sbdpu_diag_5 err_sbdpu_diag.s -vcs_run_args=+thread=20
291 err_sbdpu_diag_6 err_sbdpu_diag.s -vcs_run_args=+thread=40
292 err_sbdpu_diag_7 err_sbdpu_diag.s -vcs_run_args=+thread=80
293
294
295</runargs>
296
297
298<runargs -sas -vcs_run_args=+thread=all -midas_args=-DINC_ERR_TRAPS -vcs_run_args=+noDebugModes>
299#endif
300</runargs>
301</lsu_ras>
302
303#if(defined SPC || defined FC1 || defined CCM1 || defined CMP1)
304<blimp name=blimp>
305
306<runargs -midas_args=-allow_tsb_conflicts>
307//---------------------------
308// 1 thread
309<runargs -vcs_run_args=+thread=01>
310 // #90279 tlu assertion
311 blimp_rand1_st_2865865 blimp_rand1_st_2865865.s
312 // #90867 - 8t diag fails ST
313 blimp_rand1_8t_3148963 blimp_rand1_8t_3148963.s
314</runargs>
315
316//---------------------------
317// 2 thread
318<runargs -vcs_run_args=+thread=11>
319 // #102229 TLU redirect with error injection
320 blimp_rand1_8t_11_7812675 blimp_rand1.knobs_7812675.s -tg_seed=1411795610 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_ic_on -midas_args=-DINC_ERR_TRAPS
321</runargs>
322
323//---------------------------
324// 4 thread
325<runargs -vcs_run_args=+thread=0f>
326</runargs>
327
328
329//---------------------------
330// 8 thread
331<runargs -vcs_run_args=+thread=ff>
332 // #90696 PC miscmp on trap
333 blimp_rand1_8t_3033526 blimp_rand1_8t_3033526.s
334 // #93441
335 blimp_rand1_8t_4240359 blimp_rand1_8t_4240359.s
336 // #94081
337 blimp_rand1_8t_4527139 blimp_rand1_8t_4527139.s
338 // #94079
339 blimp_rand4_8t_4528891 blimp_rand4_8t_4528891.s
340 // #98363
341 blimp_rand5_8t_6471004 blimp_rand5_8t_6471004.s
342 // #100870 - 2 traps taken at once
343 blimp_rand3.knobs_7246351 blimp_rand3.knobs_7246351.s -vcs_run_args=+random_ccx_gnt -vcs_run_args=+min_ccx_gnt_delay=2 -vcs_run_args=+max_ccx_gnt_delay=10 -vcs_run_args=+TIMEOUT=10000 -max_cycle=+4000000 -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_irf_on -vcs_run_args=+err_irf_freq=45 -midas_args=-DINC_ERR_TRAPS -vcs_run_args=+thread=ff -tg_seed=1344387010
344</runargs>
345
346
347</runargs>
348</blimp>
349#endif
350
351
352<runargs -vcs_run_args=+noredwdrkill>
353<tlu_long name=tlu_long>
354
355#if (! defined FC)
356<runargs -vcs_run_args=+thread=all>
357#endif
358
359#if (defined FC)
360<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
361#endif
362
363
364 tlu_rand01_ind_02 tlu_rand01_ind_02.s
365
366 tlu_rand02_ind_07 tlu_rand02_ind_07.s
367
368 tlu_rand02_ind_08 tlu_rand02_ind_08.s
369 tlu_rand02_ind_09 tlu_rand02_ind_09.s
370 tlu_rand02_ind_10 tlu_rand02_ind_10.s
371
372
373 tlu_rand03_ind_03 tlu_rand03_ind_03.s
374 tlu_rand03_ind_04 tlu_rand03_ind_04.s
375 tlu_rand03_ind_07 tlu_rand03_ind_07.s
376 tlu_rand03_ind_08 tlu_rand03_ind_08.s
377 tlu_rand03_ind_05 tlu_rand03_ind_05.s
378 tlu_rand03_ind_06 tlu_rand03_ind_06.s
379 tlu_rand03_ind_09 tlu_rand03_ind_09.s
380
381#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
382 tlu_rand04_ind_02 tlu_rand04_ind_02.s
383 tlu_rand04_ind_03 tlu_rand04_ind_03.s
384 tlu_rand04_ind_04 tlu_rand04_ind_04.s
385
386 tlu_rand04_ind_19 tlu_rand04_ind_19.s
387 tlu_rand04_ind_21 tlu_rand04_ind_21.s
388 tlu_rand04_ind_22 tlu_rand04_ind_22.s
389
390// TLU rand5 diags use user events
391#if (defined SPC)
392</runargs>
393
394<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off>
395 err_tcc_hstick_diag err_tcc_hstick_diag.s -vcs_run_args=+thread=01
396 err_tcc_hstick_diag_1 err_tcc_hstick_diag.s -vcs_run_args=+thread=02
397 err_tcc_hstick_diag_2 err_tcc_hstick_diag.s -vcs_run_args=+thread=04
398 err_tcc_hstick_diag_3 err_tcc_hstick_diag.s -vcs_run_args=+thread=08
399 err_tcc_hstick_diag_4 err_tcc_hstick_diag.s -vcs_run_args=+thread=10
400 err_tcc_hstick_diag_5 err_tcc_hstick_diag.s -vcs_run_args=+thread=20
401 err_tcc_hstick_diag_6 err_tcc_hstick_diag.s -vcs_run_args=+thread=40
402 err_tcc_hstick_diag_7 err_tcc_hstick_diag.s -vcs_run_args=+thread=80
403
404
405 err_inj_mondo_diag err_inj_mondo_diag.s -vcs_run_args=+thread=01
406 err_inj_mondo_diag_1 err_inj_mondo_diag.s -vcs_run_args=+thread=02
407 err_inj_mondo_diag_2 err_inj_mondo_diag.s -vcs_run_args=+thread=04
408 err_inj_mondo_diag_3 err_inj_mondo_diag.s -vcs_run_args=+thread=08
409 err_inj_mondo_diag_4 err_inj_mondo_diag.s -vcs_run_args=+thread=10
410 err_inj_mondo_diag_5 err_inj_mondo_diag.s -vcs_run_args=+thread=20
411 err_inj_mondo_diag_6 err_inj_mondo_diag.s -vcs_run_args=+thread=40
412 err_inj_mondo_diag_7 err_inj_mondo_diag.s -vcs_run_args=+thread=80
413
414 err_tsa_diag err_tsa_diag.s -vcs_run_args=+thread=01
415 err_tsa_diag_1 err_tsa_diag.s -vcs_run_args=+thread=02
416 err_tsa_diag_2 err_tsa_diag.s -vcs_run_args=+thread=04
417 err_tsa_diag_3 err_tsa_diag.s -vcs_run_args=+thread=08
418 err_tsa_diag_4 err_tsa_diag.s -vcs_run_args=+thread=10
419 err_tsa_diag_5 err_tsa_diag.s -vcs_run_args=+thread=20
420 err_tsa_diag_6 err_tsa_diag.s -vcs_run_args=+thread=40
421 err_tsa_diag_7 err_tsa_diag.s -vcs_run_args=+thread=80
422
423
424 err_stick_cmpr_cycle err_stick_cmpr_cycle.s -vcs_run_args=+thread=01
425 err_stick_cmpr_cycle_1 err_stick_cmpr_cycle.s -vcs_run_args=+thread=02
426 err_stick_cmpr_cycle_2 err_stick_cmpr_cycle.s -vcs_run_args=+thread=04
427 err_stick_cmpr_cycle_3 err_stick_cmpr_cycle.s -vcs_run_args=+thread=08
428 err_stick_cmpr_cycle_4 err_stick_cmpr_cycle.s -vcs_run_args=+thread=10
429 err_stick_cmpr_cycle_5 err_stick_cmpr_cycle.s -vcs_run_args=+thread=20
430 err_stick_cmpr_cycle_6 err_stick_cmpr_cycle.s -vcs_run_args=+thread=40
431 err_stick_cmpr_cycle_7 err_stick_cmpr_cycle.s -vcs_run_args=+thread=80
432
433
434 err_tick_cmpr_cycle_c1_n2 err_tick_cmpr_cycle_c1_n2.s -vcs_run_args=+thread=01
435
436
437</runargs>
438
439
440#if (! defined FC)
441<runargs -vcs_run_args=+thread=all>
442#endif
443
444#if (defined FC)
445<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
446#endif
447
448#endif
449 tlu_rand05_ind_10_11_8 tlu_rand05_ind_10_11_8.s
450#if (defined SPC || defined CMP1 || defined CMP1L2X )
451 tlu_swtraps tlu_swtraps.pal
452#endif
453#endif
454</runargs>
455</tlu_long>
456<tlu_fast name=tlu_fast>
457
458#if (! defined FC)
459<runargs -vcs_run_args=+thread=all>
460#endif
461
462#if (defined FC)
463<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
464#endif
465
466 tlu_allintvec1 tlu_allintvec1.s
467 tlu_allintvec2 tlu_allintvec2.s
468
469 tlu_simulint tlu_simulint.s -vcs_run_args=+err_chkrs_off
470#if (defined SPC)
471
472 tlu_rand01_ind_01 tlu_rand01_ind_01.s
473 tlu_rand01_ind_04 tlu_rand01_ind_04.s
474
475 tlu_rand02_ind_03 tlu_rand02_ind_03.s
476 tlu_rand02_ind_05 tlu_rand02_ind_05.s
477
478#endif
479 tlu_rand04_ind_01 tlu_rand04_ind_01.s
480#if (defined SPC || defined CMP1 || defined CMP1L2X || defined CCM1 || defined FC1 )
481
482// tlu_rand05_ind_01_05_2 tlu_rand05_ind_01_05_2.s
483 tlu_rand05_ind_01_13_1 tlu_rand05_ind_01_13_1.s
484// tlu_rand05_ind_01_15_3 tlu_rand05_ind_01_15_3.s
485// tlu_rand05_ind_01_27_4 tlu_rand05_ind_01_27_4.s
486// tlu_rand05_ind_02_08_4 tlu_rand05_ind_02_08_4.s
487// tlu_rand05_ind_03_01_1 tlu_rand05_ind_03_01_1.s
488 tlu_rand05_ind_39 tlu_rand05_ind_39.s
489 tlu_rand01_ind_09 tlu_rand01_ind_09.s
490
491// tlu_rand05_ind_39_1 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=1
492// tlu_rand05_ind_39_2 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=2
493// tlu_rand05_ind_39_3 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=3
494// tlu_rand05_ind_39_4 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=4
495// tlu_rand05_ind_39_5 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=5
496// tlu_rand05_ind_39_6 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=6
497// tlu_rand05_ind_39_7 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=7
498#endif
499
500</runargs>
501
502// SingleThread ONLY
503
504
505 tlu_rand01_ind_11 tlu_rand01_ind_11.s
506
507 tlu_rand02_ind_02 tlu_rand02_ind_02.s
508#if( !defined FC)
509 tlu_rand03_ind_02 tlu_rand03_ind_02.s
510 tlu_rand04_ind_02 tlu_rand04_ind_02.s
511
512 tlu_rand04_ind_14 tlu_rand04_ind_14.s
513 tlu_rand04_ind_15 tlu_rand04_ind_15.s
514 tlu_rand04_ind_21 tlu_rand04_ind_21.s
515
516 tlu_rand03_ind_05 tlu_rand03_ind_05.s
517 tlu_rand03_ind_06 tlu_rand03_ind_06.s
518 tlu_rand03_ind_09 tlu_rand03_ind_09.s
519 tlu_rand04_ind_03 tlu_rand04_ind_03.s
520 tlu_rand04_ind_04 tlu_rand04_ind_04.s
521 tlu_rand04_ind_06 tlu_rand04_ind_06.s
522 tlu_rand04_ind_07 tlu_rand04_ind_07.s
523 tlu_rand04_ind_16 tlu_rand04_ind_16.s
524 tlu_rand04_ind_19 tlu_rand04_ind_19.s
525 tlu_rand04_ind_20 tlu_rand04_ind_20.s
526 tlu_rand04_ind_22 tlu_rand04_ind_22.s
527 tlu_rand04_ind_08 tlu_rand04_ind_08.s
528
529 tlu_rand04_ind_11 tlu_rand04_ind_11.s -midas_args=-DCMP_THREAD_START=0xe7 -finish_mask=e7
530#endif
531
532
533#if (defined SPC || defined CMP)
534
535
536#if(! defined CMP1)
537// tlu_iaw_range_1 tlu_iaw_range.s -vcs_run_args=+thread=11
538// tlu_iaw_range_2 tlu_iaw_range.s -vcs_run_args=+thread=22
539// tlu_iaw_range_3 tlu_iaw_range.s -vcs_run_args=+thread=44
540// tlu_iaw_range_4 tlu_iaw_range.s -vcs_run_args=+thread=88
541#endif
542
543#endif
544 tlu_107450 tlu_107450.s
545 tlu_107450_mt tlu_107450_mt.s
546</tlu_fast>
547
548<tlu_disrupting name=tlu_disrupting>
549#if (defined SPC || defined CMP)
550 tlu_rand05_ind_08 tlu_rand05_ind_08.s
551 tlu_rand05_ind_10 tlu_rand05_ind_10.s
552 tlu_rand05_ind_11 tlu_rand05_ind_11.s
553 tlu_rand05_ind_12 tlu_rand05_ind_12.s
554 tlu_rand05_ind_15 tlu_rand05_ind_15.s
555 tlu_rand05_ind_16 tlu_rand05_ind_16.s
556#endif
557#if (defined SPC || defined CMP)
558 tlu_rand05_ind_01 tlu_rand05_ind_01.s
559 tlu_rand05_ind_02 tlu_rand05_ind_02.s
560 tlu_rand05_ind_03 tlu_rand05_ind_03.s
561 tlu_rand05_ind_04 tlu_rand05_ind_04.s
562 tlu_rand05_ind_06 tlu_rand05_ind_06.s
563 tlu_rand05_ind_07 tlu_rand05_ind_07.s
564
565 tlu_rand05_ind_01_mt tlu_rand05_ind_01.s -vcs_run_args=+thread=all
566
567 // tlu_rand05_ind_23 tlu_rand05_ind_23.s -vcs_run_args=+thread=ff
568
569// isa3_1215ivtrap2 isa3_1215ivtrap2.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
570#endif
571#if (!defined FC)
572
573// isa3_1215ivtrap isa3_1215ivtrap.s -vcs_run_args=+thread=all
574 isa3_intlevel_121503 isa3_intlevel_121503.s -vcs_run_args=+thread=all
575 isa3_mondo_121503 isa3_mondo_121503.s -vcs_run_args=+thread=all
576
577
578 isa3_1215hsysmatrap isa3_1215hsysmatrap.s -vcs_run_args=+thread=all
579// isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -vcs_run_args=+thread=1
580// isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -vcs_run_args=+thread=ff
581
582#endif
583</tlu_disrupting>
584
585
586<tlu_halt name=tlu_halt>
587
588 err_dcdp_halt err_dcdp_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
589// err_tcc_hstick_halt err_tcc_hstick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
590 err_tcc_stick_halt err_tcc_stick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
591 err_tcc_tick_halt err_tcc_tick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
592 tlu_halt_hstmatch tlu_halt_hstmatch.s -vcs_run_args=+thread=all
593// tlu_halt_intvec tlu_halt_intvec.s -vcs_run_args=+thread=all
594// tlu_halt_modint tlu_halt_modint.s -vcs_run_args=+thread=all
595// tlu_halt_cwqint tlu_halt_cwqint.s -vcs_run_args=+thread=all
596// tlu_halt_park tlu_halt_park.s -vcs_run_args=+thread=all
597 tlu_halt_stickint tlu_halt_stickint.s -vcs_run_args=+thread=all
598 tlu_halt_tickint tlu_halt_tickint.s -vcs_run_args=+thread=all
599// tlu_halt_xir tlu_halt_xir.s -vcs_run_args=+thread=all
600
601</tlu_halt>
602
603</runargs>
604
605<mmu_core name=mmu_core>
606
607
608#if (!defined FC)
609<runargs -sas -vcs_run_args=+thread=01>
610#endif
611
612#if (defined FC)
613<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=1 >
614#endif
615
616 mmu_st_unsupport_psize mmu_st_unsupport_psize.s
617 mmu_st_h2p mmu_st_h2p.s
618#ifdef SPC
619 mmu_st_tsb_va_hole mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
620 mmu_st_tsb_va_hole_1 mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
621#endif
622 mmu_st_ext_ra mmu_st_ext_ra.s
623 mmu_use_bit_test mmu_tag_read_use_bit_test.s
624 mmu_st_hwtw_enable mmu_st_hwtw_enable.s
625</runargs>
626
627#if (!defined FC)
628<runargs -sas -vcs_run_args=+thread=all>
629#endif
630
631#if (defined FC)
632<runargs -sas -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
633#endif
634
635 mmu_mt_ranotpa_0 mmu_mt_ranotpa_0.s
636 mmu_mt_no_hboot_hwtw_0 mmu_mt_no_hboot_hwtw_0.s
637 mmu_mt_no_hboot_hwtw_0a mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
638 mmu_mt_ep_0 mmu_mt_ep_0.s
639 mmu_mt_psize_1 mmu_mt_psize_1.s
640 mmu_mt_realrange_0 mmu_mt_realrange_0.s
641 mmu_mt_realrange_1 mmu_mt_realrange_1.s
642 mmu_mt_hwtw_demap mmu_mt_hwtw_demap.s
643 mmu_mt_tsb_ptr_0 mmu_mt_tsb_ptr_0.s
644 mmu_mt_tsb_ptr_1 mmu_mt_tsb_ptr_1.s
645#if (!defined FC)
646 mmu_mt_htba mmu_mt_htba.s -vcs_run_args=+thread=ff
647#endif
648#if (defined FC)
649 mmu_mt_htba mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=ff -finish_mask=all
650#endif
651 mmu_mt_real_0 mmu_mt_real_0.s
652 mmu_mt_real_1 mmu_mt_real_1.s
653 mmu_mt_bypass_use_ctx_0 mmu_mt_bypass_use_ctx_0.s
654 mmu_mt_write_tsb_0 mmu_mt_write_tsb_0.s
655 mmu_mt_rr_0 mmu_mt_rr_0.s
656 mmu_mt_demap_page mmu_mt_demap_page.s
657 mmu_mt_demap_page_1 mmu_mt_demap_page_1.s
658
659</runargs>
660
661#ifdef SPC
662
663<runargs -sas -vcs_run_args=+thread=07 -vcs_run_args=+err_chkrs_off>
664 mmu_mt_mhit_0 mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
665</runargs>
666
667<runargs -sas -vcs_run_args=+thread=13>
668 mmu_mt_mhit_1 mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
669</runargs>
670
671<runargs -sas -vcs_run_args=+thread=21 -vcs_run_args=+err_chkrs_off>
672 mmu_st_mhit_2 mmu_st_mhit_2.s -vcs_run_args=+err_sync_on
673</runargs>
674
675#endif
676
677#if (!defined FC)
678<runargs -sas -vcs_run_args=+thread=03>
679#endif
680#if (defined FC)
681<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -finish_mask=3 >
682#endif
683
684 mmu_mt_use_ctx0 mmu_mt_use_ctx0.s
685 mmu_mt_use_ctx1 mmu_mt_use_ctx1.s
686 mmu_mt_rtrans_0 mmu_mt_rtrans_0.s
687
688</runargs>
689
690#if (!defined FC)
691<runargs -sas -vcs_run_args=+thread=1f>
692#endif
693#if (defined FC)
694<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -finish_mask=1f >
695#endif
696
697 mmu_mt_asi_cp mmu_mt_asi_cp.s
698
699</runargs>
700
701
702#if (!defined FC)
703<runargs -sas -vcs_run_args=+thread=01 -midas_args=-DTSB_SEARCH_BURST>
704#endif
705#if (defined FC)
706<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -midas_args=-DTSB_SEARCH_BURST -finish_mask=1 >
707#endif
708
709 mmu_st_unsupport_psize_burst mmu_st_unsupport_psize.s
710 mmu_st_h2p_burst mmu_st_h2p.s
711#ifdef SPC
712 mmu_st_tsb_va_hole_burst mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
713 mmu_st_tsb_va_hole_1_burst mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
714 mmu_st_ext_ra_burst mmu_st_ext_ra.s
715#endif
716
717</runargs>
718
719#if (!defined FC)
720<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_BURST>
721#endif
722#if (defined FC)
723<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_BURST -finish_mask=all >
724#endif
725
726// mmu_mt_ranotpa_0_burst mmu_mt_ranotpa_0.s
727// mmu_mt_no_hboot_hwtw_0_burst mmu_mt_no_hboot_hwtw_0.s
728// mmu_mt_no_hboot_hwtw_0a_burst mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
729// mmu_mt_ep_0_burst mmu_mt_ep_0.s
730 mmu_mt_psize_1_burst mmu_mt_psize_1.s
731// mmu_mt_realrange_0_burst mmu_mt_realrange_0.s
732// mmu_mt_realrange_1_burst mmu_mt_realrange_1.s
733 mmu_mt_hwtw_demap_burst mmu_mt_hwtw_demap.s
734 mmu_mt_tsb_ptr_0_burst mmu_mt_tsb_ptr_0.s
735 mmu_mt_tsb_ptr_1_burst mmu_mt_tsb_ptr_1.s
736
737#if (!defined FC)
738 mmu_mt_htba_burst mmu_mt_htba.s -vcs_run_args=+thread=ff
739#endif
740#if (defined FC)
741 mmu_mt_htba_burst mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
742#endif
743
744 mmu_mt_real_0_burst mmu_mt_real_0.s
745 mmu_mt_real_1_burst mmu_mt_real_1.s
746 mmu_mt_bypass_use_ctx_0_burst mmu_mt_bypass_use_ctx_0.s
747 mmu_mt_write_tsb_0_burst mmu_mt_write_tsb_0.s
748 mmu_mt_rr_0_burst mmu_mt_rr_0.s
749 mmu_mt_demap_page_burst mmu_mt_demap_page.s
750 mmu_mt_demap_page_1_burst mmu_mt_demap_page_1.s
751
752</runargs>
753
754#ifdef SPC
755
756<runargs -sas -vcs_run_args=+thread=07 -midas_args=-DTSB_SEARCH_BURST -vcs_run_args=+err_chkrs_off>
757 mmu_mt_mhit_0_burst mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
758</runargs>
759
760#if (!defined FC)
761<runargs -sas -vcs_run_args=+thread=13 -midas_args=-DTSB_SEARCH_BURST>
762#endif
763#if (defined FC)
764<runargs -sas -midas_args=-DCMP_THREAD_START=0x13 -midas_args=-DTSB_SEARCH_BURST -finish_mask=13 >
765#endif
766 mmu_mt_mhit_1_burst mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
767</runargs>
768
769#endif
770
771#if (!defined FC)
772<runargs -sas -vcs_run_args=+thread=03 -midas_args=-DTSB_SEARCH_BURST>
773#endif
774#if (defined FC)
775<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -midas_args=-DTSB_SEARCH_BURST -finish_mask=3 >
776#endif
777
778 mmu_mt_use_ctx0_burst mmu_mt_use_ctx0.s
779 mmu_mt_use_ctx1_burst mmu_mt_use_ctx1.s
780 mmu_mt_rtrans_0_burst mmu_mt_rtrans_0.s
781
782</runargs>
783
784#if (!defined FC)
785<runargs -sas -vcs_run_args=+thread=1f -midas_args=-DTSB_SEARCH_BURST>
786#endif
787#if (defined FC)
788<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -midas_args=-DTSB_SEARCH_BURST -finish_mask=1f >
789#endif
790
791 mmu_mt_asi_cp_burst mmu_mt_asi_cp.s
792
793</runargs>
794
795
796#if (!defined FC)
797<runargs -sas -vcs_run_args=+thread=01 -midas_args=-DTSB_SEARCH_PREDICTION>
798#endif
799#if (defined FC)
800<runargs -sas -midas_args=-DCMP_THREAD_START=0x01 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=1 >
801#endif
802
803 mmu_st_unsupport_psize_prediction mmu_st_unsupport_psize.s
804 mmu_st_h2p_prediction mmu_st_h2p.s
805#ifdef SPC
806 mmu_st_tsb_va_hole_prediction mmu_st_tsb_va_hole.s -midas_args=-DCUSTOM_TRAP_0X9
807 mmu_st_tsb_va_hole_1_prediction mmu_st_tsb_va_hole_1.s -midas_args=-DCUSTOM_TRAP_0X9
808 mmu_st_ext_ra_prediction mmu_st_ext_ra.s
809#endif
810
811</runargs>
812
813#if (!defined FC)
814<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_PREDICTION>
815#endif
816#if (defined FC)
817<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=all >
818#endif
819
820 mmu_mt_ranotpa_0_prediction mmu_mt_ranotpa_0.s
821 mmu_mt_no_hboot_hwtw_0_prediction mmu_mt_no_hboot_hwtw_0.s
822 mmu_mt_no_hboot_hwtw_0a_prediction mmu_mt_no_hboot_hwtw_0.s -midas_args=-DNOHWTW
823 mmu_mt_ep_0_prediction mmu_mt_ep_0.s
824 mmu_mt_psize_1_prediction mmu_mt_psize_1.s
825 mmu_mt_realrange_0_prediction mmu_mt_realrange_0.s
826 mmu_mt_realrange_1_prediction mmu_mt_realrange_1.s
827 mmu_mt_hwtw_demap_prediction mmu_mt_hwtw_demap.s
828 mmu_mt_tsb_ptr_0_prediction mmu_mt_tsb_ptr_0.s
829 mmu_mt_tsb_ptr_1_prediction mmu_mt_tsb_ptr_1.s
830#if (!defined FC)
831 mmu_mt_htba_prediction mmu_mt_htba.s -vcs_run_args=+thread=ff
832#endif
833#if (defined FC)
834 mmu_mt_htba_prediction mmu_mt_htba.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
835#endif
836 mmu_mt_real_0_prediction mmu_mt_real_0.s
837// mmu_mt_real_1_prediction mmu_mt_real_1.s
838 mmu_mt_bypass_use_ctx_0_prediction mmu_mt_bypass_use_ctx_0.s
839 mmu_mt_write_tsb_0_prediction mmu_mt_write_tsb_0.s
840 mmu_mt_rr_0_prediction mmu_mt_rr_0.s
841 mmu_mt_demap_page_prediction mmu_mt_demap_page.s
842 mmu_mt_demap_page_1_prediction mmu_mt_demap_page_1.s
843
844</runargs>
845
846#ifdef SPC
847
848#if (!defined FC)
849<runargs -sas -vcs_run_args=+thread=07 -midas_args=-DTSB_SEARCH_PREDICTION -vcs_run_args=+err_chkrs_off>
850#endif
851#if (defined FC)
852<runargs -sas -midas_args=-DCMP_THREAD_START=0x07 -midas_args=-DTSB_SEARCH_PREDICTION -vcs_run_args=+err_chkrs_off -finish_mask=7 >
853#endif
854
855 mmu_mt_mhit_0_prediction mmu_mt_mhit_0.s -vcs_run_args=+err_sync_on
856</runargs>
857
858#if (!defined FC)
859<runargs -sas -vcs_run_args=+thread=13 -midas_args=-DTSB_SEARCH_PREDICTION>
860#endif
861#if (defined FC)
862<runargs -sas -midas_args=-DCMP_THREAD_START=0x13 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=13 >
863#endif
864
865 mmu_mt_mhit_1_prediction mmu_mt_mhit_1.s -vcs_run_args=+err_sync_on
866</runargs>
867
868#endif
869
870#if (!defined FC)
871<runargs -sas -vcs_run_args=+thread=03 -midas_args=-DTSB_SEARCH_PREDICTION>
872#endif
873#if (defined FC)
874<runargs -sas -midas_args=-DCMP_THREAD_START=0x03 -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=3 >
875#endif
876
877 mmu_mt_use_ctx0_prediction mmu_mt_use_ctx0.s
878 mmu_mt_use_ctx1_prediction mmu_mt_use_ctx1.s
879 mmu_mt_rtrans_0_prediction mmu_mt_rtrans_0.s
880
881</runargs>
882
883#if (!defined FC)
884<runargs -sas -vcs_run_args=+thread=1f -midas_args=-DTSB_SEARCH_PREDICTION>
885#endif
886#if (defined FC)
887<runargs -sas -midas_args=-DCMP_THREAD_START=0x1f -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=1f >
888#endif
889
890 mmu_mt_asi_cp_prediction mmu_mt_asi_cp.s
891
892</runargs>
893
894#ifdef SPC
895
896<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off>
897 err_sca_diag err_sca_diag.s
898 err_scau_diag err_scau_diag.s
899 err_mra_diag err_mra_diag.s
900</runargs>
901
902#endif
903
904
905#if (!defined FC)
906<runargs -sas -vcs_run_args=+thread=all -midas_args=-DTSB_SEARCH_PREDICTION>
907#endif
908#if (defined FC)
909<runargs -sas -midas_args=-DCMP_THREAD_START=all -midas_args=-DTSB_SEARCH_PREDICTION -finish_mask=all >
910#endif
911
912 mmu_mt_real_1_prediction mmu_mt_real_1.s
913</runargs>
914</mmu_core>
915
916
917<mmu_tlb_sync name=mmu_tlb_sync>
918
919 mmu_tag_read_use_bit_test mmu_tag_read_use_bit_test.s
920</mmu_tlb_sync>
921<mmu_cmp_test name=mmu_cmp_test>
922
923
924#if (!defined FC)
925<runargs -midas_args=-DMMU247 -vcs_run_args=+thread=all -midas_args=-DENABLE_ITTM_DTTM -midas_args=-DPORTABLE_CORE>
926#endif
927#if (defined FC)
928<runargs -midas_args=-DMMU247 -midas_args=-DCMP_THREAD_START=all -midas_args=-DENABLE_ITTM_DTTM -midas_args=-DPORTABLE_CORE -finish_mask=all >
929#endif
930
931// mmu_cmp_test_0 mmu_cmp_test_0.s
932// mmu_cmp_test_1 mmu_cmp_test_1.s
933 mmu_cmp_test_2 mmu_cmp_test_2.s
934 mmu_cmp_test_3 mmu_cmp_test_3.s
935// mmu_cmp_test_4 mmu_cmp_test_4.s
936</runargs>
937</mmu_cmp_test>
938
939#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
940<kaos_st name=kaos_st>
941
942<runargs -midas_args=-allow_tsb_conflicts>
943 kaos_01_07_2004_1 kaos_01_07_2004_1.s
944 kaos_02_03_04_18 kaos_02_03_04_18.s
945 kaos_02_05_2004_20 kaos_02_05_2004_20.s
946 kaos_02_05_2004_91 kaos_02_05_2004_91.s
947 kaos_02_06_2004_11 kaos_02_06_2004_11.s
948 kaos_02_06_2004_135 kaos_02_06_2004_135.s
949 kaos_02_06_2004_152 kaos_02_06_2004_152.s
950 kaos_02_06_2004_71 kaos_02_06_2004_71.s
951 kaos_27_1_2004_0_11 kaos_27_1_2004_0_11.s
952 kaos_27_1_2004_0_13 kaos_27_1_2004_0_13.s
953 kaos_27_1_2004_0_22 kaos_27_1_2004_0_22.s
954 kaos_27_1_2004_0_42 kaos_27_1_2004_0_42.s
955 kaos_27_1_2004_0_49 kaos_27_1_2004_0_49.s
956 v9_kao_02_10_04_19 v9_kao_02_10_04_19.s
957 v9_kao_02_11_04_31 v9_kao_02_11_04_31.s
958 v9_kao_02_14_04_101 v9_kao_02_14_04_101.s
959 v9_kao_02_14_04_103 v9_kao_02_14_04_103.s
960 v9_kao_02_14_04_112 v9_kao_02_14_04_112.s
961 ifu_kao_02_18_04_109 ifu_kao_02_18_04_109.s
962
963</runargs>
964</kaos_st>
965<kaos_2t name=kaos_2t>
966<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=03 -midas_args=-DNOHWTW>
967 kaos_01_06_2004_1 kaos_01_06_2004_1.s
968 //v9_2th_kao_02_20_04_88 v9_2th_kao_02_20_04_88.s
969 v9_2th_kao_02_20_04_125 v9_2th_kao_02_20_04_125.s
970 v9_2th_kao_02_20_04_131 v9_2th_kao_02_20_04_131.s
971 v9_2th_kao_02_20_04_219 v9_2th_kao_02_20_04_219.s
972 v9_2th_kao_02_20_04_434 v9_2th_kao_02_20_04_434.s
973 v9_2th_kao_02_20_04_71 v9_2th_kao_02_20_04_71.s
974
975</runargs>
976</kaos_2t>
977
978<kaos_4t name=kaos_4t>
979<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=0f -midas_args=-DNOHWTW>
980 v9_4th_kao_02_25_04_4 v9_4th_kao_02_25_04_4.s
981 //v9_kao_4th_02_23_04_0 v9_kao_4th_02_23_04_0.s
982 v9_kao_4th_02_27_04_2 v9_kao_4th_02_27_04_2.s
983 v9_kao_4th_02_27_04_199 v9_kao_4th_02_27_04_199.s
984 v9_kao_4th_02_27_04_34 v9_kao_4th_02_27_04_34.s
985 v9_kao_4th_03_04_04_100 v9_kao_4th_03_04_04_100.s
986 v9_kao_4th_02_27_04_199 v9_kao_4th_02_27_04_199.s
987 v9_4th_kaos_03_05_04_500 v9_4th_kaos_03_05_04_500.s
988 v9_4th_kaos_03_05_04_105 v9_4th_kaos_03_05_04_105.s
989 v9_4th_kaos_03_05_04_130 v9_4th_kaos_03_05_04_130.s
990 v9_4th_kaos_03_05_04_101 v9_4th_kaos_03_05_04_101.s
991 v9_4th_kaos_03_05_04_153 v9_4th_kaos_03_05_04_153.s
992 v9_4th_kaos_03_05_04_501 v9_4th_kaos_03_05_04_501.s
993
994</runargs>
995</kaos_4t>
996
997
998<kaos_8t name=kaos_8t>
999<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=all>
1000
1001 v9_8th_sp_kaos_03_11_04_0 v9_8th_sp_kaos_03_11_04_0.s
1002 v9_8th_sp_kaos_03_11_04_15 v9_8th_sp_kaos_03_11_04_15.s
1003 v9_8th_kaos_03_16_04_0 v9_8th_kaos_03_16_04_0.s
1004 ifu_8th_sp_kaos_03_10_04_1 ifu_8th_sp_kaos_03_10_04_1.s
1005 v9_8th_kaos_02_08_04_20 v9_8th_kaos_02_08_04_20.s
1006 v9_8th_sp_kaos_03_11_04_17 v9_8th_sp_kaos_03_11_04_17.s
1007 v9_8th_kaos_03_17_04_133 v9_8th_kaos_03_17_04_133.s
1008 v9_8th_kaos_03_17_04_0 v9_8th_kaos_03_17_04_0.s
1009#if (defined CMP1 || defined SPC)
1010 v9_8th_kaos_03_23_04_14 v9_8th_kaos_03_23_04_14.s
1011#endif
1012 v9_8th_kaos_03_17_04_10 v9_8th_kaos_03_17_04_10.s
1013 v9_8th_kaos_02_08_04_20 v9_8th_kaos_02_08_04_20.s
1014 v9_8th_kaos_03_14_04_396 v9_8th_kaos_03_14_04_396.s
1015 isa_8th_kaos_03_30_04_101 isa_8th_kaos_03_30_04_101.s
1016
1017 v9_8th_kaos_03_01_04_102 v9_8th_kaos_03_01_04_102.s
1018 v9_8th_kao_03_01_04_0 v9_8th_kao_03_01_04_0.s
1019 v9_8th_kaos_02_08_04_0 v9_8th_kaos_02_08_04_0.s
1020</runargs>
1021</kaos_8t>
1022#endif
1023
1024<kaos_tlb name=kaos_tlb>
1025
1026<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=all>
1027
1028 // These diags require TLB Sync
1029 // Add these back into kaos_8t once CMP has TLB Sync
1030 v9_8th_kaos_03_01_04_102 v9_8th_kaos_03_01_04_102.s
1031 v9_8th_kao_03_01_04_0 v9_8th_kao_03_01_04_0.s
1032 v9_8th_kaos_02_08_04_0 v9_8th_kaos_02_08_04_0.s
1033
1034</runargs>
1035</kaos_tlb>
1036
1037
1038<isa2_mt name=isa2_mt>
1039#if (!defined FC)
1040<runargs -vcs_run_args=+thread=all>
1041#endif
1042#if (defined FC)
1043<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
1044#endif
1045isa2_raw_fc_2 isa2_raw_fc_2.s
1046isa2_all_fail_fc_3 isa2_all_fail_fc_3.s
1047spc_isa2mt_fail_fc_9 spc_isa2mt_fail_fc_9.s
1048spc_isa2mt_fail_fc_7 spc_isa2mt_fail_fc_7.s
1049spc_isa2mt_fail_fc_11 spc_isa2mt_fail_fc_11.s
1050
1051isa2_basic_fc0 isa2_basic_fc0.s
1052isa2_basic_fc1 isa2_basic_fc1.s
1053isa2_basic_fc2 isa2_basic_fc2.s
1054isa2_basic_fc3 isa2_basic_fc3.s
1055isa2_basic_fc4 isa2_basic_fc4.s
1056isa2_basic_fc5 isa2_basic_fc5.s
1057isa2_basic_fc6 isa2_basic_fc6.s
1058isa2_basic_fc7 isa2_basic_fc7.s
1059isa2_basic_fc8 isa2_basic_fc8.s
1060isa2_basic_fc9 isa2_basic_fc9.s
1061isa2_basic_fc10 isa2_basic_fc10.s
1062isa2_basic_fc11 isa2_basic_fc11.s
1063isa2_basic_fc12 isa2_basic_fc12.s
1064isa2_basic_fc13 isa2_basic_fc13.s
1065isa2_basic_fc14 isa2_basic_fc14.s
1066isa2_basic_fc15 isa2_basic_fc15.s
1067isa2_basic_fc16 isa2_basic_fc16.s
1068isa2_basic_fc17 isa2_basic_fc17.s
1069isa2_basic_fc18 isa2_basic_fc18.s
1070isa2_basic_fc19 isa2_basic_fc19.s
1071isa2_basic_fc20 isa2_basic_fc20.s
1072isa2_basic_fc21 isa2_basic_fc21.s
1073isa2_basic_fc22 isa2_basic_fc22.s
1074isa2_basic_fc23 isa2_basic_fc23.s
1075isa2_basic_fc24 isa2_basic_fc24.s
1076isa2_basic_fc25 isa2_basic_fc25.s
1077isa2_basic_fc26 isa2_basic_fc26.s
1078isa2_basic_fc27 isa2_basic_fc27.s
1079isa2_basic_fc28 isa2_basic_fc28.s
1080isa2_basic_fc29 isa2_basic_fc29.s
1081
1082</runargs>
1083</isa2_mt>
1084<isa3_saverestore name=isa3_saverestore>
1085
1086 isa3_saverestore_fc0 isa3_saverestore_fc0.s
1087 isa3_saverestore_fc1 isa3_saverestore_fc1.s
1088 isa3_saverestore_fc2 isa3_saverestore_fc2.s
1089 isa3_saverestore_fc3 isa3_saverestore_fc3.s
1090 isa3_saverestore_fc4 isa3_saverestore_fc4.s
1091</isa3_saverestore>
1092
1093<isa3_mt name=isa3_mt>
1094
1095#if (!defined FC)
1096<runargs -vcs_run_args=+thread=all>
1097#endif
1098#if (defined FC)
1099<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
1100#endif
1101
1102 isa3_basic3_f0 isa3_basic3_f0.s
1103 isa3_basic3_f1 isa3_basic3_f1.s
1104 isa3_basic3_f2 isa3_basic3_f2.s
1105 isa3_basic3_f3 isa3_basic3_f3.s
1106 isa3_basic3_f5 isa3_basic3_f5.s
1107 isa3_basic3_f6 isa3_basic3_f6.s
1108 isa3_basic3_f7 isa3_basic3_f7.s
1109 isa3_basic3_f8 isa3_basic3_f8.s
1110 isa3_basic3_f10 isa3_basic3_f10.s
1111 isa3_basic3_f11 isa3_basic3_f11.s
1112 isa3_basic3_f12 isa3_basic3_f12.s
1113 isa3_basic3_f13 isa3_basic3_f13.s
1114 isa3_basic3_f14 isa3_basic3_f14.s
1115 isa3_basic3_f15 isa3_basic3_f15.s
1116 isa3_basic3_f16 isa3_basic3_f16.s
1117 isa3_basic3_f17 isa3_basic3_f17.s
1118 isa3_basic3_f18 isa3_basic3_f18.s
1119 isa3_basic3_f19 isa3_basic3_f19.s
1120 isa3_window3_f0 isa3_window3_f0.s
1121 isa3_window3_f1 isa3_window3_f1.s
1122 isa3_window3_f2 isa3_window3_f2.s
1123 isa3_window3_f3 isa3_window3_f3.s
1124 isa3_window3_f4 isa3_window3_f4.s
1125 isa3_window3_f5 isa3_window3_f5.s
1126 isa3_window3_f6 isa3_window3_f6.s
1127 isa3_window3_f7 isa3_window3_f7.s
1128 isa3_window3_f8 isa3_window3_f8.s
1129 isa3_window3_f9 isa3_window3_f9.s
1130 isa3_window3_f10 isa3_window3_f10.s
1131 isa3_window3_f11 isa3_window3_f11.s
1132 isa3_window3_f12 isa3_window3_f12.s
1133 isa3_window3_f13 isa3_window3_f13.s
1134 isa3_window3_f14 isa3_window3_f14.s
1135 isa3_window3_f15 isa3_window3_f15.s
1136 isa3_window3_f16 isa3_window3_f16.s
1137 isa3_window3_f17 isa3_window3_f17.s
1138 isa3_window3_f18 isa3_window3_f18.s
1139 isa3_window3_f19 isa3_window3_f19.s
1140 isa3_fsr3_f1 isa3_fsr3_f1.s
1141 isa3_fsr3_f2 isa3_fsr3_f2.s
1142 isa3_fsr3_f3 isa3_fsr3_f3.s
1143 isa3_fsr3_f4 isa3_fsr3_f4.s
1144 isa3_fsr3_f5 isa3_fsr3_f5.s
1145 isa3_fsr3_f6 isa3_fsr3_f6.s
1146 isa3_fsr3_f8 isa3_fsr3_f8.s
1147 isa3_fsr3_f9 isa3_fsr3_f9.s
1148 isa3_fsr3_f10 isa3_fsr3_f10.s
1149 isa3_fsr3_f11 isa3_fsr3_f11.s
1150 isa3_fsr3_f12 isa3_fsr3_f12.s
1151 isa3_fsr3_f13 isa3_fsr3_f13.s
1152 isa3_fsr3_f14 isa3_fsr3_f14.s
1153 isa3_fsr3_f15 isa3_fsr3_f15.s
1154 isa3_fsr3_f16 isa3_fsr3_f16.s
1155 isa3_fsr3_f17 isa3_fsr3_f17.s
1156 isa3_fsr3_f18 isa3_fsr3_f18.s
1157
1158isa3_asr_pr_hpr_f1 isa3_asr_pr_hpr_f1.s
1159isa3_asr_pr_hpr_f2 isa3_asr_pr_hpr_f2.s
1160isa3_asr_pr_hpr_f3 isa3_asr_pr_hpr_f3.s
1161isa3_asr_pr_hpr_f4 isa3_asr_pr_hpr_f4.s
1162isa3_asr_pr_hpr_f5 isa3_asr_pr_hpr_f5.s
1163isa3_asr_pr_hpr_f6 isa3_asr_pr_hpr_f6.s
1164isa3_asr_pr_hpr_f7 isa3_asr_pr_hpr_f7.s
1165
1166#if (!defined NO_IDTLB)
1167#if (!defined FC)
1168<runargs -vcs_run_args=+thread=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
1169#endif
1170#if (defined FC)
1171<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
1172#endif
1173
1174 isa3_basic_idtlb1 isa3_basic_idtlb1.s
1175 isa3_basic_idtlb1_nohw isa3_basic_idtlb1.s -midas_args=-DNOHWTW
1176 isa3_basic_idtlb2 isa3_basic_idtlb2.s
1177 isa3_basic_idtlb3 isa3_basic_idtlb3.s
1178 isa3_basic_idtlb4 isa3_basic_idtlb4.s
1179 isa3_basic_idtlb4_nohw isa3_basic_idtlb4.s -midas_args=-DNOHWTW
1180 isa3_basic_idtlb5 isa3_basic_idtlb5.s
1181 isa3_basic_idtlb6 isa3_basic_idtlb6.s
1182 isa3_basic_dtlb1 isa3_basic_dtlb1.s
1183 isa3_basic_idtlb6_nohw isa3_basic_idtlb6.s -midas_args=-DNOHWTW
1184 isa3_basic_dtlb1_nohw isa3_basic_dtlb1.s -midas_args=-DNOHWTW
1185</runargs>
1186#endif
1187
1188isa3_mmu_f1 isa3_mmu_f1.s
1189isa3_mmu_f2 isa3_mmu_f2.s
1190isa3_scratchpad_f1 isa3_scratchpad_f1.s
1191isa3_scratchpad_f2 isa3_scratchpad_f2.s
1192isa3_mmu_21_52_f1 isa3_mmu_21_52_f1.s
1193
1194isa3_mmu_htw_4v_phy isa3_mmu_htw_0.s -vcs_run_args=+thread=all
1195isa3_mmu_htw_4v_real isa3_mmu_htw_3.s -vcs_run_args=+thread=all
1196
1197
1198 isa3_flushw_fc0 isa3_flushw_fc0.s
1199 isa3_basic0_f0 isa3_basic0_f0.s
1200 isa3_fsr0_f0 isa3_fsr0_f0.s
1201 isa3_window0_f0 isa3_window0_f0.s
1202
1203 spc2_hboot_test spc2_hboot_test.s
1204 spc_shutdown spc_shutdown.s
1205
1206</runargs>
1207</isa3_mt>
1208
1209<isa3_st name=isa3_st>
1210 isa3_basic3_f0 isa3_basic3_f0.s
1211 isa3_basic3_f1 isa3_basic3_f1.s
1212 isa3_basic3_f2 isa3_basic3_f2.s
1213 isa3_basic3_f3 isa3_basic3_f3.s
1214 isa3_basic3_f5 isa3_basic3_f5.s
1215 isa3_basic3_f6 isa3_basic3_f6.s
1216 isa3_basic3_f7 isa3_basic3_f7.s
1217 isa3_basic3_f8 isa3_basic3_f8.s
1218 isa3_basic3_f10 isa3_basic3_f10.s
1219 isa3_basic3_f11 isa3_basic3_f11.s
1220 isa3_basic3_f12 isa3_basic3_f12.s
1221 isa3_basic3_f13 isa3_basic3_f13.s
1222 isa3_basic3_f14 isa3_basic3_f14.s
1223 isa3_basic3_f15 isa3_basic3_f15.s
1224 isa3_basic3_f16 isa3_basic3_f16.s
1225 isa3_basic3_f17 isa3_basic3_f17.s
1226 isa3_basic3_f18 isa3_basic3_f18.s
1227 isa3_basic3_f19 isa3_basic3_f19.s
1228 isa3_window3_f0 isa3_window3_f0.s
1229 isa3_window3_f1 isa3_window3_f1.s
1230 isa3_window3_f2 isa3_window3_f2.s
1231 isa3_window3_f3 isa3_window3_f3.s
1232 isa3_window3_f4 isa3_window3_f4.s
1233 isa3_window3_f5 isa3_window3_f5.s
1234 isa3_window3_f6 isa3_window3_f6.s
1235 isa3_window3_f7 isa3_window3_f7.s
1236 isa3_window3_f8 isa3_window3_f8.s
1237 isa3_window3_f9 isa3_window3_f9.s
1238 isa3_window3_f10 isa3_window3_f10.s
1239 isa3_window3_f11 isa3_window3_f11.s
1240 isa3_window3_f12 isa3_window3_f12.s
1241 isa3_window3_f13 isa3_window3_f13.s
1242 isa3_window3_f14 isa3_window3_f14.s
1243 isa3_window3_f15 isa3_window3_f15.s
1244 isa3_window3_f16 isa3_window3_f16.s
1245 isa3_window3_f17 isa3_window3_f17.s
1246 isa3_window3_f18 isa3_window3_f18.s
1247 isa3_window3_f19 isa3_window3_f19.s
1248 isa3_fsr3_f1 isa3_fsr3_f1.s
1249 isa3_fsr3_f2 isa3_fsr3_f2.s
1250 isa3_fsr3_f3 isa3_fsr3_f3.s
1251 isa3_fsr3_f4 isa3_fsr3_f4.s
1252 isa3_fsr3_f5 isa3_fsr3_f5.s
1253 isa3_fsr3_f6 isa3_fsr3_f6.s
1254 isa3_fsr3_f8 isa3_fsr3_f8.s
1255 isa3_fsr3_f9 isa3_fsr3_f9.s
1256 isa3_fsr3_f10 isa3_fsr3_f10.s
1257 isa3_fsr3_f11 isa3_fsr3_f11.s
1258 isa3_fsr3_f12 isa3_fsr3_f12.s
1259 isa3_fsr3_f13 isa3_fsr3_f13.s
1260 isa3_fsr3_f14 isa3_fsr3_f14.s
1261 isa3_fsr3_f15 isa3_fsr3_f15.s
1262 isa3_fsr3_f16 isa3_fsr3_f16.s
1263 isa3_fsr3_f17 isa3_fsr3_f17.s
1264 isa3_fsr3_f18 isa3_fsr3_f18.s
1265
1266isa3_asr_pr_hpr_f1 isa3_asr_pr_hpr_f1.s
1267isa3_asr_pr_hpr_f2 isa3_asr_pr_hpr_f2.s
1268isa3_asr_pr_hpr_f3 isa3_asr_pr_hpr_f3.s
1269isa3_asr_pr_hpr_f4 isa3_asr_pr_hpr_f4.s
1270isa3_asr_pr_hpr_f5 isa3_asr_pr_hpr_f5.s
1271isa3_asr_pr_hpr_f6 isa3_asr_pr_hpr_f6.s
1272isa3_asr_pr_hpr_f7 isa3_asr_pr_hpr_f7.s
1273
1274#define NO_IDTLB
1275#if (!defined NO_IDTLB)
1276
1277
1278#if (!defined FC)
1279<runargs -vcs_run_args=+thread=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
1280#endif
1281#if (defined FC)
1282<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all -midas_args=-DTHREAD_COUNT=ALL_THREADS>
1283#endif
1284
1285 isa3_basic_idtlb1 isa3_basic_idtlb1.s
1286 isa3_basic_idtlb1_nohw isa3_basic_idtlb1.s -midas_args=-DNOHWTW
1287 isa3_basic_idtlb2 isa3_basic_idtlb2.s
1288 isa3_basic_idtlb3 isa3_basic_idtlb3.s
1289 isa3_basic_idtlb4 isa3_basic_idtlb4.s
1290 isa3_basic_idtlb4_nohw isa3_basic_idtlb4.s -midas_args=-DNOHWTW
1291 isa3_basic_idtlb5 isa3_basic_idtlb5.s
1292 isa3_basic_idtlb6 isa3_basic_idtlb6.s
1293 isa3_basic_dtlb1 isa3_basic_dtlb1.s
1294 isa3_basic_idtlb6_nohw isa3_basic_idtlb6.s -midas_args=-DNOHWTW
1295 isa3_basic_dtlb1_nohw isa3_basic_dtlb1.s -midas_args=-DNOHWTW
1296</runargs>
1297#endif
1298
1299isa3_mmu_f1 isa3_mmu_f1.s
1300isa3_mmu_f2 isa3_mmu_f2.s
1301isa3_scratchpad_f1 isa3_scratchpad_f1.s
1302isa3_scratchpad_f2 isa3_scratchpad_f2.s
1303isa3_mmu_21_52_f1 isa3_mmu_21_52_f1.s
1304
1305isa3_mmu_htw_4v_phy isa3_mmu_htw_0.s -vcs_run_args=+thread=all
1306isa3_mmu_htw_4v_real isa3_mmu_htw_3.s -vcs_run_args=+thread=all
1307
1308#undef NO_IDTLB
1309 isa3_flushw_fc0 isa3_flushw_fc0.s
1310 isa3_basic0_f0 isa3_basic0_f0.s
1311 isa3_fsr0_f0 isa3_fsr0_f0.s
1312 isa3_window0_f0 isa3_window0_f0.s
1313</isa3_st>
1314
1315<isa_1215 name=isa_1215>
1316
1317 isa3_va_watchpoint isa3_va_watchpoint.s
1318 isa3_pa_watchpoint isa3_pa_watchpoint.s
1319 isa3_1215htraps1 isa3_1215htraps1.s
1320 isa3_privileged_action isa3_privileged_action.s
1321 isa3_fdacc_protection isa3_fdacc_protection.s
1322 spc_trans_test0 spc_trans_test0.s
1323 isa3_align_trap isa3_align_trap.s
1324 isa3_core_id isa3_core_id.s -nosas
1325 isa3_fp_disable_1215_0x20 isa3_fp_disable_1215_0x20.s -sas
1326 isa3_fp_excIeee_1215_0x21 isa3_fp_excIeee_1215_0x21.s -sas
1327 isa3_fp_excOther_1215_0x22 isa3_fp_excOther_1215_0x22.s -sas
1328 isa3_int_div0_1215_0x28 isa3_int_div0_1215_0x28.s -sas
1329// isa3_mod_arith_int_1215_0x3d isa3_mod_arith_int_1215_0x3d.s -nosas
1330 isa3_1215hsysmatrap isa3_1215hsysmatrap.s
1331 traps_34_35_36 traps_34_35_36.s
1332 traps_save_restore traps_save_restore.s
1333#if (defined CMP1 || defined SPC)
1334// isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -vcs_run_args=+thread=1
1335// isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -vcs_run_args=+thread=ff
1336// isa3_1215ivtrap isa3_1215ivtrap.s -vcs_run_args=+thread=ff
1337#endif
1338 isa3_trap_0x30 isa3_trap_0x30.s
1339 isa3_trap_0x3e isa3_trap_0x3e.s
1340 isa3_trap_0x3f isa3_trap_0x3f.s
1341 isa3_trap_0x8 isa3_trap_0x8.s
1342
1343 isa3_mt_hwtw1 isa3_mt_hwtw1.s -vcs_run_args=+thread=all
1344
1345#if (defined SPC)
1346 isa3_xir_121503 isa3_xir_121503.s -vcs_run_args=+thread=all -vcs_run_args=+intr_en=all -vcs_run_args=+intr_vect=3 -vcs_run_args=+intr_type=1 -vcs_run_args=+intr_wait=3000 -vcs_run_args=+intr_delay=100 -vcs_run_args=+lsu_mon_off
1347#endif
1348 isa3_intlevel_121503 isa3_intlevel_121503.s -vcs_run_args=+thread=all
1349 isa3_mondo_121503 isa3_mondo_121503.s -vcs_run_args=+thread=all
1350 tsotool_1t_75971 tsotool_1t_75971.s -midas_args=-allow_tsb_conflicts
1351</isa_1215>
1352#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
1353<pmu name=pmu>
1354
1355<runargs -nosas -midas_args=-DNOPMUENABLE>
1356 isa3_pmu_e2_t1 isa3_pmu_e2_t1.s
1357 isa3_pmu_imiss_idle isa3_pmu_imiss_idle.s
1358 isa3_pmu_int15 isa3_pmu_int15.s
1359 isa3_pmu_cpu_ldst isa3_pmu_cpu_ldst.s
1360 isa3_pmu_dmiss_idle isa3_pmu_dmiss_idle.s
1361 isa3_pmu_other isa3_pmu_other.s
1362
1363<runargs -vcs_run_args=+TIMEOUT=500000 -vcs_run_args=+skt_timeout=500000 -max_cycle=+5000000 -rtl_timeout=5000000>
1364
1365//CPU loads to CCX
1366pmu_ccx_sel5_0x04_thAll pmu_ccx_sel5_0x04_thAll.s -vcs_run_args=+thread=ff
1367
1368//CPU stores to CCX
1369pmu_ccx_sel5_0x10_thAll pmu_ccx_sel5_0x10_thAll.s -vcs_run_args=+thread=ff
1370
1371</runargs> // timeout
1372</runargs> // -nosas
1373
1374//TLB Misses
1375 itlbMiss0 itlbSl3.pal -vcs_run_args=+thread=01
1376 itlbMiss1 itlbSl3.pal -vcs_run_args=+thread=02
1377 itlbMiss2 itlbSl3.pal -vcs_run_args=+thread=04
1378 itlbMiss3 itlbSl3.pal -vcs_run_args=+thread=08
1379 itlbMiss4 itlbSl3.pal -vcs_run_args=+thread=10
1380 itlbMiss5 itlbSl3.pal -vcs_run_args=+thread=20
1381 itlbMiss6 itlbSl3.pal -vcs_run_args=+thread=40
1382 itlbMiss7 itlbSl3.pal -vcs_run_args=+thread=80
1383
1384 dtlbMiss0 dtlbSl3.pal -vcs_run_args=+thread=01
1385 dtlbMiss1 dtlbSl3.pal -vcs_run_args=+thread=02
1386 dtlbMiss2 dtlbSl3.pal -vcs_run_args=+thread=04
1387 dtlbMiss3 dtlbSl3.pal -vcs_run_args=+thread=08
1388 dtlbMiss4 dtlbSl3.pal -vcs_run_args=+thread=10
1389 dtlbMiss5 dtlbSl3.pal -vcs_run_args=+thread=20
1390 dtlbMiss6 dtlbSl3.pal -vcs_run_args=+thread=40
1391 dtlbMiss7 dtlbSl3.pal -vcs_run_args=+thread=80
1392
1393 itlbMissLoOv0 itlbSl3OvL.pal -vcs_run_args=+thread=01
1394 itlbMissLoOv1 itlbSl3OvL.pal -vcs_run_args=+thread=02
1395 itlbMissLoOv2 itlbSl3OvL.pal -vcs_run_args=+thread=04
1396 itlbMissLoOv3 itlbSl3OvL.pal -vcs_run_args=+thread=08
1397 itlbMissLoOv4 itlbSl3OvL.pal -vcs_run_args=+thread=10
1398 itlbMissLoOv5 itlbSl3OvL.pal -vcs_run_args=+thread=20
1399 itlbMissLoOv6 itlbSl3OvL.pal -vcs_run_args=+thread=40
1400 itlbMissLoOv7 itlbSl3OvL.pal -vcs_run_args=+thread=80
1401
1402 itlbMissHiOv0 itlbSl3OvH.pal -vcs_run_args=+thread=01
1403 itlbMissHiOv1 itlbSl3OvH.pal -vcs_run_args=+thread=02
1404 itlbMissHiOv2 itlbSl3OvH.pal -vcs_run_args=+thread=04
1405 itlbMissHiOv3 itlbSl3OvH.pal -vcs_run_args=+thread=08
1406 itlbMissHiOv4 itlbSl3OvH.pal -vcs_run_args=+thread=10
1407 itlbMissHiOv5 itlbSl3OvH.pal -vcs_run_args=+thread=20
1408 itlbMissHiOv6 itlbSl3OvH.pal -vcs_run_args=+thread=40
1409 itlbMissHiOv7 itlbSl3OvH.pal -vcs_run_args=+thread=80
1410
1411 dtlbMissLoOv0 dtlbSl3OvL.pal -vcs_run_args=+thread=01
1412 dtlbMissLoOv1 dtlbSl3OvL.pal -vcs_run_args=+thread=02
1413 dtlbMissLoOv2 dtlbSl3OvL.pal -vcs_run_args=+thread=04
1414 dtlbMissLoOv3 dtlbSl3OvL.pal -vcs_run_args=+thread=08
1415 dtlbMissLoOv4 dtlbSl3OvL.pal -vcs_run_args=+thread=10
1416 dtlbMissLoOv5 dtlbSl3OvL.pal -vcs_run_args=+thread=20
1417 dtlbMissLoOv6 dtlbSl3OvL.pal -vcs_run_args=+thread=40
1418 dtlbMissLoOv7 dtlbSl3OvL.pal -vcs_run_args=+thread=80
1419
1420 dtlbMissHiOv0 dtlbSl3OvH.pal -vcs_run_args=+thread=01
1421 dtlbMissHiOv1 dtlbSl3OvH.pal -vcs_run_args=+thread=02
1422 dtlbMissHiOv2 dtlbSl3OvH.pal -vcs_run_args=+thread=04
1423 dtlbMissHiOv3 dtlbSl3OvH.pal -vcs_run_args=+thread=08
1424 dtlbMissHiOv4 dtlbSl3OvH.pal -vcs_run_args=+thread=10
1425 dtlbMissHiOv5 dtlbSl3OvH.pal -vcs_run_args=+thread=20
1426 dtlbMissHiOv6 dtlbSl3OvH.pal -vcs_run_args=+thread=40
1427 dtlbMissHiOv7 dtlbSl3OvH.pal -vcs_run_args=+thread=80
1428
1429//Cache misses
1430// icacheMiss0 icacheMissSl3.s -vcs_run_args=+thread=01
1431 icacheMiss1 icacheMissSl3.s -vcs_run_args=+thread=02
1432 icacheMiss2 icacheMissSl3.s -vcs_run_args=+thread=04
1433 icacheMiss3 icacheMissSl3.s -vcs_run_args=+thread=08
1434 icacheMiss4 icacheMissSl3.s -vcs_run_args=+thread=10
1435 icacheMiss5 icacheMissSl3.s -vcs_run_args=+thread=20
1436 icacheMiss6 icacheMissSl3.s -vcs_run_args=+thread=40
1437// icacheMiss7 icacheMissSl3.s -vcs_run_args=+thread=80
1438
1439 dcacheMiss0 dcacheMissSl3.s -vcs_run_args=+thread=01
1440 dcacheMiss1 dcacheMissSl3.s -vcs_run_args=+thread=02
1441 dcacheMiss2 dcacheMissSl3.s -vcs_run_args=+thread=04
1442 dcacheMiss3 dcacheMissSl3.s -vcs_run_args=+thread=08
1443 dcacheMiss4 dcacheMissSl3.s -vcs_run_args=+thread=10
1444 dcacheMiss5 dcacheMissSl3.s -vcs_run_args=+thread=20
1445 dcacheMiss6 dcacheMissSl3.s -vcs_run_args=+thread=40
1446 dcacheMiss7 dcacheMissSl3.s -vcs_run_args=+thread=80
1447
1448 dcacheOvH0 dcacheOvH.s -vcs_run_args=+thread=01
1449 dcacheOvH1 dcacheOvH.s -vcs_run_args=+thread=02
1450 dcacheOvH2 dcacheOvH.s -vcs_run_args=+thread=04
1451 dcacheOvH3 dcacheOvH.s -vcs_run_args=+thread=08
1452 dcacheOvH4 dcacheOvH.s -vcs_run_args=+thread=10
1453 dcacheOvH5 dcacheOvH.s -vcs_run_args=+thread=20
1454 dcacheOvH6 dcacheOvH.s -vcs_run_args=+thread=40
1455 dcacheOvH7 dcacheOvH.s -vcs_run_args=+thread=80
1456
1457 dcacheOvL0 dcacheOvL.s -vcs_run_args=+thread=01
1458 dcacheOvL1 dcacheOvL.s -vcs_run_args=+thread=02
1459 dcacheOvL2 dcacheOvL.s -vcs_run_args=+thread=04
1460 dcacheOvL3 dcacheOvL.s -vcs_run_args=+thread=08
1461 dcacheOvL4 dcacheOvL.s -vcs_run_args=+thread=10
1462 dcacheOvL5 dcacheOvL.s -vcs_run_args=+thread=20
1463 dcacheOvL6 dcacheOvL.s -vcs_run_args=+thread=40
1464 dcacheOvL7 dcacheOvL.s -vcs_run_args=+thread=80
1465
1466#ifdef SPC
1467 dcacheMissL20 dcacheL2MissSl3.s -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1 -nosas
1468 dcacheMissL21 dcacheL2MissSl3.s -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
1469 dcacheMissL22 dcacheL2MissSl3.s -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
1470 dcacheMissL23 dcacheL2MissSl3.s -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
1471 dcacheMissL24 dcacheL2MissSl3.s -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
1472 dcacheMissL25 dcacheL2MissSl3.s -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
1473 dcacheMissL26 dcacheL2MissSl3.s -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
1474 dcacheMissL27 dcacheL2MissSl3.s -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
1475
1476
1477 icMiss0 icMissL2Miss.pal -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1
1478 icMiss1 icMissL2Miss.pal -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
1479 icMiss2 icMissL2Miss.pal -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
1480 icMiss3 icMissL2Miss.pal -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
1481 icMiss4 icMissL2Miss.pal -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
1482 icMiss5 icMissL2Miss.pal -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
1483 icMiss6 icMissL2Miss.pal -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
1484 icMiss7 icMissL2Miss.pal -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
1485#endif
1486
1487 pmuAtomic pmuAtomic.s -vcs_run_args=+thread=all
1488
1489 pmuOverflowBit ovBitTest.pal -vcs_run_args=+thread=all
1490
1491#ifdef SPC
1492//SL 4 test
1493 serviceLevel4 pmu_sl4_mask_n2.pal -vcs_run_args=+l2miss_type=1 -nosas
1494#endif
1495</pmu>
1496#endif
1497#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
1498<fgu_traps name=fgu_traps>
1499
1500fgu_ieee_traps_01 fgu_ieee_traps_01.s
1501fgu_ieee_traps_02 fgu_ieee_traps_02.s
1502fgu_ieee_traps_03 fgu_ieee_traps_03.s
1503fgu_ieee_traps_04 fgu_ieee_traps_04.s
1504fgu_ieee_traps_05 fgu_ieee_traps_05.s
1505fgu_ieee_traps_06 fgu_ieee_traps_06.s
1506fgu_ieee_traps_07 fgu_ieee_traps_07.s
1507fgu_ieee_traps_08 fgu_ieee_traps_08.s
1508fgu_ieee_traps_09 fgu_ieee_traps_09.s
1509fgu_ieee_traps_10 fgu_ieee_traps_10.s
1510fgu_idiv_traps_01 fgu_idiv_traps_01.s
1511fgu_idiv_traps_02 fgu_idiv_traps_02.s
1512fgu_idiv_traps_03 fgu_idiv_traps_03.s
1513fgu_idiv_traps_04 fgu_idiv_traps_04.s
1514fgu_idiv_traps_05 fgu_idiv_traps_05.s
1515fgu_idiv_traps_06 fgu_idiv_traps_06.s
1516fgu_idiv_traps_07 fgu_idiv_traps_07.s
1517fgu_idiv_traps_08 fgu_idiv_traps_08.s
1518fgu_idiv_traps_09 fgu_idiv_traps_09.s
1519fgu_idiv_traps_10 fgu_idiv_traps_10.s
1520fgu_siam_traps_21 fgu_siam_traps_21.s
1521fgu_stfsr_traps_22 fgu_stfsr_traps_22.s
1522fgu_stxfsr_traps_23 fgu_stxfsr_traps_23.s
1523fgu_ieee_traps_24 fgu_ieee_traps_24.s
1524fgu_ieee_traps_25 fgu_ieee_traps_25.s
1525fgu_ieee_traps_26 fgu_ieee_traps_26.s
1526fgu_ieee_traps_27 fgu_ieee_traps_27.s
1527fgu_ieee_traps_28 fgu_ieee_traps_28.s
1528fgu_ieee_traps_29 fgu_ieee_traps_29.s
1529fgu_ieee_traps_30 fgu_ieee_traps_30.s
1530
1531</fgu_traps>
1532#endif
1533#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
1534<runargs -vcs_run_args=+thread=01>
1535<exu_ported name=exu_ported>
1536
1537exu_add_n2 exu_add_n2.s
1538exu_irf_global_n2 exu_irf_global_n2.s
1539exu_irf_local_n2 exu_irf_local_n2.s
1540exu_logical_n2 exu_logical_n2.s
1541exu_move_n2 exu_move_n2.s
1542exu_muldiv_n2 exu_muldiv_n2.s
1543exu_shift_n2 exu_shift_n2.s
1544exu_sub_n2 exu_sub_n2.s
1545
1546exu_win_traps_n2 exu_win_traps_n2.s
1547
1548fp_addsub0_n2 fp_addsub0_n2.s
1549fp_fadd_norm_sv_n2 fp_fadd_norm_sv_n2.s
1550fp_fdiv_man_sv_n2 fp_fdiv_man_sv_n2.s
1551fp_fprs0_n2 fp_fprs0_n2.s
1552fp_ieee_flags_n2 fp_ieee_flags_n2.s
1553fp_movixcc0_n2 fp_movixcc0_n2.s
1554fp_movixcc1_n2 fp_movixcc1_n2.s
1555fp_movixcc2_n2 fp_movixcc2_n2.s
1556fp_muldiv0_a_n2 fp_muldiv0_a_n2.s
1557fp_muldiv0_n2 fp_muldiv0_n2.s
1558fp_sticky_bits_n2 fp_sticky_bits_n2.s
1559
1560
1561ffu_blkst_stall_n2 ffu_blkst_stall_n2.s
1562ffu_faligndata_n2 ffu_faligndata_n2.s
1563ffu_fpaddsub_n2 ffu_fpaddsub_n2.s
1564ffu_fplogic_n2 ffu_fplogic_n2.s
1565ffu_fpreg_rw_n2 ffu_fpreg_rw_n2.s
1566ffu_fsr_gsr_n2 ffu_fsr_gsr_n2.s
1567ffu_fsr_tem_n2 ffu_fsr_tem_n2.s
1568ffu_siam_n2 ffu_siam_n2.s
1569</exu_ported>
1570</runargs>
1571#endif
1572
1573<isa1_st name=isa1_st>
1574
1575 isa1_noldst_fc_0513 isa1_noldst_fc_0513.s
1576 lsu_align_raw lsu_align_raw.s
1577 lsu_storeraw_fc_0 lsu_storeraw_fc_0.s
1578 spc_basic_isa2_fc_0 spc_basic_isa2_fc_0.s
1579 spc_mul_ldst spc_mul_ldst.s
1580 spc_asi spc_asi.s
1581 spc_flush0 spc_flush0.s
1582 ldst_atomic ldst_atomic.s
1583</isa1_st>
1584<isa1_mt name=isa1_mt>
1585
1586
1587#if (!defined FC)
1588<runargs -vcs_run_args=+thread=all>
1589#endif
1590#if (defined FC)
1591<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
1592#endif
1593
1594 biccgen biccgen.s
1595 bpccgen bpccgen.s
1596 bprgen bprgen.s
1597 ifu_basic_bicc ifu_basic_bicc.s
1598 ifu_basic_br1 ifu_basic_br1.s
1599 ifu_basic_br2 ifu_basic_br2.s
1600 ifu_basic_br ifu_basic_br.s
1601 ifu_basic_ex1 ifu_basic_ex1.s
1602 ifu_basic_ex_raw ifu_basic_ex_raw.s
1603 ifu_basic_mov ifu_basic_mov.s
1604 ifu_basic_branch ifu_basic_branch.s
1605 lsu_cpqfill lsu_cpqfill.s
1606// spc_pmu_asr spc_pmu_asr.s
1607 spc_tlu_rml_asr spc_tlu_rml_asr.s
1608</runargs>
1609</isa1_mt>
1610<isa1_nospec name=isa1_nospec>
1611
1612<runargs -midas_args=-DNOSPEC_EN>
1613 ifu_basic_x ifu_basic_x.s
1614 ifu_basic_branch ifu_basic_branch.s
1615 biccgen biccgen.s
1616 bpccgen bpccgen.s
1617 bprgen bprgen.s
1618 isa1_noldst_fc_0513 isa1_noldst_fc_0513.s
1619 spc_basic_isa2_fc_0 spc_basic_isa2_fc_0.s
1620</runargs>
1621</isa1_nospec>
1622
1623
1624</runargs>
1625</runargs>
1626</sys(all_T2)>
1627
1628////////////////////////////////////////////////////////////////////////////////////////////////////
1629
1630
1631#ifdef CMP
1632#undef ALL_THREADS
1633#undef CMP8
1634#undef CMP
1635#undef sys
1636#undef SYSNAME
1637#endif
1638
1639
Full OpenSPARC design & verification tarball including full HDL.