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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / cmp / cmp_8core.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cmp_8core.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<sys(cmp8) name=sys(cmp8)>
36<sys(all)>
37<sys(daily)>
38
39
40<runargs -sas -vcs_run -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000 -vcs_run_args=+8_FBDIMMS >
41
42#if (!defined FC)
43n2_all_th_ldst_th64_force n2_all_th_ldst.s -vcs_run_args=+thread=ffffffffffffffff
44#endif
45#if (defined FC)
46n2_all_th_ldst_th64_force n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
47#endif
48
49n2_all_th_ldst_th0_1_9 n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0x203 -finish_mask=0x203
50n2_all_th_ldst_th64 n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
51
52// different core combinations
53n2_all_th_ldst_core_0_2_8th n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xff00ff -finish_mask=0xff00ff
54n2_all_th_ldst_core_0_1_2_4_8th n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xff00ffffff -finish_mask=ff00ffffff
55n2_all_th_ldst_core_0_1_2_3_4_8th n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffffff -finish_mask=ffffffffff
56
57n2_mcu_0_all_fbdimm_rkhi_mcu0_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU0 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
58n2_mcu_0_all_fbdimm_rkhi_mcu1_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU1 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
59n2_mcu_0_all_fbdimm_rkhi_mcu2_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU2 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
60n2_mcu_0_all_fbdimm_rkhi_mcu3_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU3 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
61
62n2_mcu_0_all_fbdimm_rkhi_mcu0_L2off_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU0 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
63n2_mcu_0_all_fbdimm_rkhi_mcu1_L2off_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU1 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
64n2_mcu_0_all_fbdimm_rkhi_mcu2_L2off_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU2 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
65n2_mcu_0_all_fbdimm_rkhi_mcu3_L2off_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU3 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
66
67</runargs>
68
69////////////////////////////////////////////////////////////////////////////
70// CMT diags, 8 core
71
72<runargs -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DTHREAD_COUNT=64>
73
74cmp_park_all_w1c_w1s cmp_park_all_w1c_w1s.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
75
76cmp_master_park_unpark_all_rw cmp_master_park_unpark_all_rw.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
77
78cmp_master_park_unpark_all_w1s_w1c cmp_master_park_unpark_all_w1s_w1c.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
79
80cmp_park_all_rw cmp_park_all_rw.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
81
82</runargs>
83
84
85<runargs -sas -vcs_run -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+l2cpx_errmon_off>
86
87ncu_park_unpark_by_running_rw ncu_park_unpark_by_running_rw.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
88
89ncu_park_unpark_multiple_times ncu_park_unpark_multiple_times.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
90
91ncu_park_by_running_rw1c ncu_park_by_running_rw1c.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000 -sas_run_args=-DPLI_DEBUG=2 -sas_run_args=-DPLI_LOG=./pli.log
92
93ncu_unpark_by_running_rw1s ncu_unpark_by_running_rw1s.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
94
95ncu_force_unpark_thr1 ncu_force_unpark_thr1.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
96
97ncu_force_unpark_thr2 ncu_force_unpark_thr2.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
98
99ncu_core_id ncu_core_id.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
100
101ncu_xir ncu_xir.s -finish_mask=0x0006060000060607 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff
102
103ncu_xir_allth ncu_xir_allth.s -finish_mask=0xffffffffffffffff -midas_args=-DPART_0_BASE=0x200000000
104
105ncu_pcx_pkts_allth ncu_pcx_pkts_allth.s -finish_mask=0xffffffffffffffff -midas_args=-DPART_0_BASE=0x200000000
106
107ncu_ssi_mt ncu_ssi_mt.s -finish_mask=0x0040000000000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot
108
109ncu_ssi_ifill_ack_nack_1 ncu_ssi_ifill_ack_nack.s -finish_mask=0x00000000000000ff -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x00000000000000ff
110
111ncu_ssi_ifill_ack_nack_2 ncu_ssi_ifill_ack_nack.s -finish_mask=0x000000000000ff00 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x000000000000ff00
112
113ncu_ssi_ifill_ack_nack_3 ncu_ssi_ifill_ack_nack.s -finish_mask=0x0000000000ff0000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x0000000000ff0000
114
115ncu_ssi_ifill_ack_nack_4 ncu_ssi_ifill_ack_nack.s -finish_mask=0x00000000ff000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x00000000ff000000
116
117ncu_ssi_ifill_ack_nack_5 ncu_ssi_ifill_ack_nack.s -finish_mask=0x000000ff00000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x000000ff00000000
118
119ncu_ssi_ifill_ack_nack_6 ncu_ssi_ifill_ack_nack.s -finish_mask=0x0000ff0000000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x0000ff0000000000
120
121ncu_ssi_ifill_ack_nack_7 ncu_ssi_ifill_ack_nack.s -finish_mask=0x00ff000000000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x00ff000000000000
122
123ncu_ssi_ifill_ack_nack_8 ncu_ssi_ifill_ack_nack.s -finish_mask=0xff00000000000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0xff00000000000000
124
125ncu_asi_cmp_tick_enable ncu_asi_cmp_tick_enable.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
126
127ncu_asi_cmp_tick_enable_2 ncu_asi_cmp_tick_enable_2.s -finish_mask=0xffffffffffffffff -midas_args=-DPART_0_BASE=0x200000000
128
129ncu_asi_cmp_tick_enable_3 ncu_asi_cmp_tick_enable_3.s -finish_mask=0xffffffffffffffff -midas_args=-DPART_0_BASE=0x200000000
130
131ncu_bank_en_subset ncu_bank_en_subset.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xc3 -vcs_run_args=+bank_set_mask=9 -midas_args=-DCORE_AVAIL=0xa2 -vcs_run_args=+core_set_mask=a2 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -nofast_boot -vcs_run_args=+gchkr_off
132
133ncu_bank_en_wptect_basic_1 ncu_bank_en_wptect_basic.s -finish_mask=0x0000000001000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x03 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCORE_AVAIL=0x0c -vcs_run_args=+core_set_mask=0c -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
134
135ncu_bank_en_wptect_basic_2 ncu_bank_en_wptect_basic.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x0c -vcs_run_args=+bank_set_mask=2 -midas_args=-DCORE_AVAIL=0x60 -vcs_run_args=+core_set_mask=60 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
136
137ncu_bank_en_wptect_basic_3 ncu_bank_en_wptect_basic.s -finish_mask=0x0000010000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x30 -vcs_run_args=+bank_set_mask=4 -midas_args=-DCORE_AVAIL=0x28 -vcs_run_args=+core_set_mask=28 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
138
139ncu_bank_en_wptect_basic_4 ncu_bank_en_wptect_basic.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xc0 -vcs_run_args=+bank_set_mask=8 -midas_args=-DCORE_AVAIL=0x81 -vcs_run_args=+core_set_mask=81 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
140
141ncu_bank_en_wptect_basic_5 ncu_bank_en_wptect_basic.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x0f -vcs_run_args=+bank_set_mask=3 -midas_args=-DCORE_AVAIL=0xe2 -vcs_run_args=+core_set_mask=e2 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
142
143ncu_bank_en_wptect_basic_6 ncu_bank_en_wptect_basic.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x33 -vcs_run_args=+bank_set_mask=5 -midas_args=-DCORE_AVAIL=0x54 -vcs_run_args=+core_set_mask=54 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
144
145ncu_bank_en_wptect_basic_7 ncu_bank_en_wptect_basic.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xc3 -vcs_run_args=+bank_set_mask=9 -midas_args=-DCORE_AVAIL=0xa3 -vcs_run_args=+core_set_mask=a3 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
146
147ncu_bank_en_wptect_basic_8 ncu_bank_en_wptect_basic.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x3c -vcs_run_args=+bank_set_mask=6 -midas_args=-DCORE_AVAIL=0x78 -vcs_run_args=+core_set_mask=78 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
148
149ncu_bank_en_wptect_basic_9 ncu_bank_en_wptect_basic.s -finish_mask=0x0000000001000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xcc -vcs_run_args=+bank_set_mask=a -midas_args=-DCORE_AVAIL=0x0f -vcs_run_args=+core_set_mask=0f -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
150
151ncu_bank_en_wptect_basic_10 ncu_bank_en_wptect_basic.s -finish_mask=0x0000000100000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xf0 -vcs_run_args=+bank_set_mask=c -midas_args=-DCORE_AVAIL=0x17 -vcs_run_args=+core_set_mask=17 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
152
153ncu_sernum_coreavail_bankavail_wptect_1 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0xa4 -vcs_run_args=+core_set_mask=a4 -midas_args=-DBANK_AVAIL=0x33 -vcs_run_args=+bank_set_mask=5 -midas_args=-DSERIAL_NUM=0x20d6732cefab3640 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
154
155ncu_sernum_coreavail_bankavail_wptect_2 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x42 -vcs_run_args=+core_set_mask=42 -midas_args=-DBANK_AVAIL=0x03 -vcs_run_args=+bank_set_mask=1 -midas_args=-DSERIAL_NUM=0x39871cddba5a09df -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
156
157ncu_sernum_coreavail_bankavail_wptect_3 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x53 -vcs_run_args=+core_set_mask=53 -midas_args=-DBANK_AVAIL=0xc3 -vcs_run_args=+bank_set_mask=9 -midas_args=-DSERIAL_NUM=0x9919192763492733 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
158
159ncu_sernum_coreavail_bankavail_wptect_4 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000010000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x28 -vcs_run_args=+core_set_mask=28 -midas_args=-DBANK_AVAIL=0x0c -vcs_run_args=+bank_set_mask=2 -midas_args=-DSERIAL_NUM=0xfbcfecdacfdecfea -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
160
161ncu_sernum_coreavail_bankavail_wptect_5 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000100000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x17 -vcs_run_args=+core_set_mask=17 -midas_args=-DBANK_AVAIL=0xf0 -vcs_run_args=+bank_set_mask=c -midas_args=-DSERIAL_NUM=0xaaaaaaaaaaaaaaaa -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
162
163ncu_sernum_coreavail_bankavail_wptect_6 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0xff -vcs_run_args=+core_set_mask=ff -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x5555555555555555 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
164
165ncu_sernum_coreavail_bankavail_wptect_7 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0000100000400001 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
166
167ncu_sernum_coreavail_bankavail_wptect_8 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0000200000800002 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
168
169ncu_sernum_coreavail_bankavail_wptect_9 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0000400001000004 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
170
171ncu_sernum_coreavail_bankavail_wptect_10 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0000800002000008 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
172
173ncu_sernum_coreavail_bankavail_wptect_11 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0001000004000010 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
174
175ncu_sernum_coreavail_bankavail_wptect_12 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0002000008000020 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
176
177ncu_sernum_coreavail_bankavail_wptect_13 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0004000010000040 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
178
179ncu_sernum_coreavail_bankavail_wptect_14 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0008000020000080 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
180
181ncu_sernum_coreavail_bankavail_wptect_15 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0010000040000100 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
182
183ncu_sernum_coreavail_bankavail_wptect_16 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0020000080000200 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
184
185ncu_sernum_coreavail_bankavail_wptect_17 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0040000100000400 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
186
187ncu_sernum_coreavail_bankavail_wptect_18 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0080000200000800 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
188
189ncu_sernum_coreavail_bankavail_wptect_19 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0100000400001000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
190
191ncu_sernum_coreavail_bankavail_wptect_20 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0200000800002000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
192
193ncu_sernum_coreavail_bankavail_wptect_21 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0400001000004000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
194
195ncu_sernum_coreavail_bankavail_wptect_22 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0800002000008000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
196
197ncu_sernum_coreavail_bankavail_wptect_23 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x1000004000010000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
198
199ncu_sernum_coreavail_bankavail_wptect_24 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x2000008000020000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
200
201ncu_sernum_coreavail_bankavail_wptect_25 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x4000010000040000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
202
203ncu_sernum_coreavail_bankavail_wptect_26 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x8000020000080000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
204
205ncu_sernum_coreavail_bankavail_wptect_27 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x8000040000100000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
206
207ncu_sernum_coreavail_bankavail_wptect_28 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x8000080000200000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
208
209</runargs>
210
211</sys(daily)>
212</sys(all)>
213</sys(cmp8)>
214
Full OpenSPARC design & verification tarball including full HDL.