projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / core_qual.diaglist
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: core_qual.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<sys(core_qualify)>
36
37
38<sys(core_qual) name=sys(core_qual)>
39// Always run with TSO_CHECKER enabled
40<runargs -sas_run_args=-DTSO_CHECKER>
41
42#if (!defined FC)
43<sys(all)>
44<sys(all_T2)>
45#endif
46<sys(nightly)>
47// <runargs -drm_cpufreq="1200 .." >
48//---------------------------------------------------------------------------
49// Upto 8-threaded diags to be run on 1 core benches, or
50// multicore (2,4 core) benches, with PORTABLE_CORE
51//--------------------------------------------------------------------------
52
53//------------Diags for Non 8 core benches -------------------------------{{{
54#if(!defined FC8 && !defined CCM8 && !defined CMP8)
55
56//---tsotool diag {{{
57<runargs -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-allow_tsb_conflicts -fast_boot -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+8_FBDIMMS -vcs_run_args=+l2cpx_errmon_off>
58n2_8tcasxa_2 n2_8tcasxa_2.s
59n2_8t_ldst1_7 n2_8t_ldst1_7.s
60n2_8t_bstbld_1 n2_8t_bstbld_1.s
61</runargs>
62
63//---tsotool diag }}}
64
65//---ccx diag {{{
66<runargs -fast_boot -midas_args=-allow_tsb_conflicts -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -vcs_run_args=+l2esr_mon_off -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS -midas_args=-DL2_REG_PROG -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2cpx_errmon_off>
67n2_cpx_fill_io_8b n2_cpx_fill_io_8b.s
68n2_cpx_ifill8b n2_cpx_ifill8b.s
69</runargs>
70//---ccx diag }}}
71
72//---gendiag diag {{{
73<runargs -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+l2esr_mon_off>
74#include "diaglists/isa/v9_gendiag.diaglist"
75</runargs>
76//---gendiag diag }}}
77
78//---blimp diag {{{
79//---blimp diag }}}
80
81//---MPGen diags {{{
82<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>
83mpgen_semi_full_isa_1 mpgen_semi_full_isa_1.s
84mpgen_semi_full_isa_2 mpgen_semi_full_isa_2.s
85mpgen_semi_full_isa_3 mpgen_semi_full_isa_3.s
86mpgen_ldst_mix mpgen_ldst_mix.s
87mpgen_ldst_int_no_asi mpgen_ldst_int_no_asi.s
88mpgen_ldst_all_l2_banks mpgen_ldst_all_l2_banks.s
89mpgen_smc_1 mpgen_smc_1.s
90mpgen_smc_2 mpgen_smc_2.s
91mpgen_smc_3 mpgen_smc_3.s
92mpgen_smc_4 mpgen_smc_4.s
93mpgen_dynamic_spec_cache mpgen_dynamic_spec_cache.s
94mpgen_tso_atomic_1_bank mpgen_tso_atomic_1_bank.s
95</runargs>
96//---MPGen diags }}}
97
98//---TLU_RAND5 diags {{{
99<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+l2cpx_errmon_off>
100<sys(fcrand05)>
101<runargs -rtl_timeout=20000 -vcs_run_args=+skt_timeout=20000 -vcs_run_args=+th_timeout=50000>
102tlu_fcrand05_ind_14 tlu_fcrand05_ind_14.s
103// fcrand05_rand_38 fcrand05_rand_38.s -midas_args=-DMULTIPASS=2
104fcrand05_rand_88 fcrand05_rand_88.s -midas_args=-DMULTIPASS=2
105// fcrand05_rand_4 fcrand05_rand_4.s -midas_args=-DMULTIPASS=2
106// fcrand05_rand_37 fcrand05_rand_37.s -midas_args=-DMULTIPASS=2
107// fcrand05_rand_43 fcrand05_rand_43.s -midas_args=-DMULTIPASS=2
108tlu_rand5fc_8149597 tlu_rand5fc_8149597.s -midas_args=-DMULTIPASS=1
109</runargs>
110</sys(fcrand05)>
111</runargs>
112//---TLU_RAND5 diags }}}
113
114#else
115//------------------------------------------------------------------------}}}
116
117//---------------------------------------------------------------------------
118// Upto 64-threaded diags to be run on 8 core benches
119//---------------------------------------------------------------------------
120//------------Diags for 8 core benches------------------------------------{{{
121
122// --- tsotool diags // {{{
123<runargs -fast_boot -midas_args=-allow_tsb_conflicts -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+show_load -vcs_run_args=+show_delta -finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -vcs_run_args=+8_FBDIMMS -midas_args=-DL2_REG_PROG -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2cpx_errmon_off>
124n2_8t-fullraw n2_8t-fullraw.s
125n2_8t-bstld n2_8t-bstld.s
126niagara2_bldst niagara2_bldst.s
127n2_64t_ldcasxa_8bank n2_64t_ldcasxa_8bank.s
128</runargs>
129// --- tsotool diags // }}}
130
131//---ccx diag real 64 threads {{{
132<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -midas_args=-DPORTABLE_CORE -vcs_run_args=+l2esr_mon_off -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+8_FBDIMMS -vcs_run_args=+l2cpx_errmon_off>
133#if(!defined FC8 && !defined CMP8)
134n2_st_atomic_8t8b n2_st_atomic_8t8b.s
135#endif
136</runargs>
137//---ccx diag real 64 threads }}}
138
139//---gendiag diag {{{
140<runargs -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+l2esr_mon_off>
141#include "diaglists/isa/v9_gendiag.diaglist"
142</runargs>
143//---gendiag diag }}}
144
145//---blimp diag {{{
146//---blimp diag }}}
147
148//---MPGen diags {{{
149<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>
150mpgen_dynamic_caches mpgen_dynamic_caches.s
151mpgen_dynamic_pwr_mgmt mpgen_dynamic_pwr_mgmt.s
152mpgen_tso_one_bank mpgen_tso_one_bank.s
153mpgen_tso_all_banks mpgen_tso_all_banks.s
154mpgen_tso_ba_all_banks mpgen_tso_ba_all_banks.s
155mpgen_tso_atomic_one_bank mpgen_tso_atomic_one_bank.s
156mpgen_tso_atomic_all_banks mpgen_tso_atomic_all_banks.s
157
158#if(!defined FC && !defined CMP8)
159mpgen_semi_full_isa_1 mpgen_semi_full_isa_1.s
160mpgen_semi_full_isa_2 mpgen_semi_full_isa_2.s
161mpgen_semi_full_isa_3 mpgen_semi_full_isa_3.s
162mpgen_ldst_mix mpgen_ldst_mix.s
163mpgen_ldst_all_l2_banks mpgen_ldst_all_l2_banks.s
164mpgen_ldst_int_no_asi mpgen_ldst_int_no_asi.s
165mpgen_tso_ba_one_bank mpgen_tso_ba_one_bank.s
166mpgen_tso_atomic_asi_one_bank mpgen_tso_atomic_asi_one_bank.s
167mpgen_tso_atomic_asi_all_banks mpgen_tso_atomic_asi_all_banks.s
168#endif
169
170</runargs>
171//---MPGen diags }}}
172
173//---TLU_RAND5 diags {{{
174<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -vcs_run_args=+l2esr_mon_off -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_OOB_CHECK -vcs_run_args=+l2cpx_errmon_off>
175<sys(fcrand05)>
176tlu_fcrand05_ind_14 tlu_fcrand05_ind_14.s
177fcrand05_rand_38 fcrand05_rand_38.s -midas_args=-DMULTIPASS=1
178
179#if(!defined FC && !defined CMP8 )
180fcrand05_rand_4 fcrand05_rand_4.s -midas_args=-DMULTIPASS=1
181fcrand05_rand_37 fcrand05_rand_37.s -midas_args=-DMULTIPASS=1
182fcrand05_rand_43 fcrand05_rand_43.s -midas_args=-DMULTIPASS=1
183fcrand05_rand_88 fcrand05_rand_88.s -midas_args=-DMULTIPASS=1
184#endif
185
186</sys(fcrand05)>
187</runargs>
188//---TLU_RAND5 diags }}}
189
190
191#endif
192//========================================================================}}}
193//===========================================================================
194
195// </runargs>
196</sys(nightly)>
197#if (!defined FC)
198</sys(all_T2)>
199</sys(all)>
200#endif
201</runargs>
202</sys(core_qual)>
203
204</sys(core_qualify)>
205
Full OpenSPARC design & verification tarball including full HDL.