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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / cov / FcNiuPIO_1C_8T.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: FcNiuPIO_1C_8T.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define RCRSTAT_A_Addr mpeval(DMC_ADDRESS_RANGE+0x00050)
40#define H_HT0_Data_access_error_0x32
41#define SUN_H_HT0_Data_access_error_0x32 \
42 inc %l4; \
43 done;
44# 20 "diag.j.pp"
45#include "hboot.s"
46#include "niu_defines.h"
47.text
48.global main
49main:
50 ta T_CHANGE_HPRIV
51 nop
52! branch to main by comparing thread id.
53
54 ta T_RD_THID
55
56 mov 0x1, %g2
57 cmp %g2, %o1
58 be THREAD_01
59 nop
60
61 mov 0x2, %g2
62 cmp %g2, %o1
63 be THREAD_02
64 nop
65
66 mov 0x3, %g2
67 cmp %g2, %o1
68 be THREAD_03
69 nop
70
71 mov 0x4, %g2
72 cmp %g2, %o1
73 be THREAD_04
74 nop
75
76 mov 0x5, %g2
77 cmp %g2, %o1
78 be THREAD_05
79 nop
80
81 mov 0x6, %g2
82 cmp %g2, %o1
83 be THREAD_06
84 nop
85
86 mov 0x7, %g2
87 cmp %g2, %o1
88 be THREAD_07
89 nop
90
91 brz %o1, THREAD_00
92 and %o1, %g3, %g1
93 nop
94
95!
96! Thread 0 Start
97!
98!
99THREAD_00:
100
101 setx fflp_config_addr, %g1, %g2
102 setx ipp_config0_addr, %g1, %g3
103 add %g3, 0x160, %g5
104 setx 0xaa, %g1, %o3
105 ldxa [%g2]ASI_PRIMARY_LITTLE, %o2
106 stxa %o3, [%g3]ASI_PRIMARY_LITTLE
107 nop
108 setx loop_count, %g1, %g4
109delay_loop_0:
110 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1
111 ldxa [%g5]ASI_PRIMARY_LITTLE, %g6
112 ldxa [%g3]ASI_PRIMARY_LITTLE, %g1
113 dec %g4
114 brnz %g4, delay_loop_0
115 nop
116
117test_passed_00:
118 nop
119 EXIT_GOOD
120
121
122THREAD_01:
123
124 nop
125
126 setx fflp_config_addr, %g1, %g2
127 setx ipp_config0_addr, %g1, %g3
128 add %g3, 0x160, %g5
129 setx 0x55, %g1, %o2
130 ldxa [%g3]ASI_PRIMARY_LITTLE, %o3
131
132 stxa %o2, [%g2]ASI_PRIMARY_LITTLE
133 setx loop_count, %g1, %g4
134delay_loop_1:
135 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1
136 ldxa [%g5]ASI_PRIMARY_LITTLE, %g6
137 ldxa [%g3]ASI_PRIMARY_LITTLE, %g1
138 nop
139 nop
140 dec %g4
141 brnz %g4, delay_loop_1
142 nop
143
144test_passed_01:
145 nop
146 EXIT_GOOD
147# 163 "diag.j.pp"
148
149THREAD_02:
150
151 nop
152
153 setx fflp_config_addr, %g1, %g2
154 setx ipp_config0_addr, %g1, %g3
155 add %g3, 0x160, %g5
156 setx 0x55, %g1, %o2
157 ldxa [%g3]ASI_PRIMARY_LITTLE, %o3
158
159 stxa %o2, [%g2]ASI_PRIMARY_LITTLE
160 setx loop_count, %g1, %g4
161delay_loop_2:
162 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1
163 ldxa [%g5]ASI_PRIMARY_LITTLE, %g6
164 ldxa [%g3]ASI_PRIMARY_LITTLE, %g1
165 dec %g4
166 brnz %g4, delay_loop_2
167 nop
168
169test_passed_02:
170 nop
171 EXIT_GOOD
172# 198 "diag.j.pp"
173
174THREAD_03:
175
176 nop
177
178 setx fflp_config_addr, %g1, %g2
179 setx ipp_config0_addr, %g1, %g3
180 add %g3, 0x160, %g5
181 setx 0x55, %g1, %o2
182 ldxa [%g3]ASI_PRIMARY_LITTLE, %o3
183
184 stxa %o2, [%g2]ASI_PRIMARY_LITTLE
185 setx loop_count, %g1, %g4
186delay_loop_3:
187 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1
188 ldxa [%g5]ASI_PRIMARY_LITTLE, %g6
189 ldxa [%g3]ASI_PRIMARY_LITTLE, %g1
190 dec %g4
191 brnz %g4, delay_loop_3
192 nop
193
194test_passed_03:
195 nop
196 EXIT_GOOD
197# 233 "diag.j.pp"
198
199THREAD_04:
200
201 nop
202
203 setx fflp_config_addr, %g1, %g2
204 setx ipp_config0_addr, %g1, %g3
205 add %g3, 0x160, %g5
206 setx 0x55, %g1, %o2
207 ldxa [%g3]ASI_PRIMARY_LITTLE, %o3
208
209 stxa %o2, [%g2]ASI_PRIMARY_LITTLE
210 setx loop_count, %g1, %g4
211delay_loop_4:
212 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1
213 ldxa [%g5]ASI_PRIMARY_LITTLE, %g6
214 ldxa [%g3]ASI_PRIMARY_LITTLE, %g1
215 dec %g4
216 brnz %g4, delay_loop_4
217 nop
218
219test_passed_04:
220 nop
221 EXIT_GOOD
222# 268 "diag.j.pp"
223
224THREAD_05:
225
226 nop
227
228 setx fflp_config_addr, %g1, %g2
229 setx ipp_config0_addr, %g1, %g3
230 add %g3, 0x160, %g5
231 setx 0x55, %g1, %o2
232 ldxa [%g3]ASI_PRIMARY_LITTLE, %o3
233
234 stxa %o2, [%g2]ASI_PRIMARY_LITTLE
235 setx loop_count, %g1, %g4
236delay_loop_5:
237 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1
238 ldxa [%g5]ASI_PRIMARY_LITTLE, %g6
239 ldxa [%g3]ASI_PRIMARY_LITTLE, %g1
240 dec %g4
241 brnz %g4, delay_loop_5
242 nop
243
244test_passed_05:
245 nop
246 EXIT_GOOD
247# 302 "diag.j.pp"
248
249THREAD_06:
250
251 nop
252
253 setx fflp_config_addr, %g1, %g2
254 setx ipp_config0_addr, %g1, %g3
255 add %g3, 0x160, %g5
256 setx 0x55, %g1, %o2
257 ldxa [%g3]ASI_PRIMARY_LITTLE, %o3
258
259 stxa %o2, [%g2]ASI_PRIMARY_LITTLE
260 setx loop_count, %g1, %g4
261delay_loop_6:
262 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1
263 ldxa [%g5]ASI_PRIMARY_LITTLE, %g6
264 ldxa [%g3]ASI_PRIMARY_LITTLE, %g1
265 dec %g4
266 brnz %g4, delay_loop_6
267 nop
268
269test_passed_06:
270 nop
271 EXIT_GOOD
272# 336 "diag.j.pp"
273
274THREAD_07:
275
276 nop
277
278 setx fflp_config_addr, %g1, %g2
279 setx ipp_config0_addr, %g1, %g3
280 add %g3, 0x160, %g5
281 setx 0x55, %g1, %o2
282 ldxa [%g3]ASI_PRIMARY_LITTLE, %o3
283
284 stxa %o2, [%g2]ASI_PRIMARY_LITTLE
285 setx loop_count, %g1, %g4
286delay_loop_7:
287 ldxa [%g2]ASI_PRIMARY_LITTLE, %g1
288 ldxa [%g5]ASI_PRIMARY_LITTLE, %g6
289 ldxa [%g3]ASI_PRIMARY_LITTLE, %g1
290 dec %g4
291 brnz %g4, delay_loop_7
292 nop
293
294test_passed_07:
295 nop
296 EXIT_GOOD
297# 373 "diag.j.pp"
298
299#if 0
300#endif
301
Full OpenSPARC design & verification tarball including full HDL.