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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: FcNiuPeuRand_1.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | #define RCRSTAT_A_Addr mpeval(DMC_ADDRESS_RANGE+0x00050) | |
40 | #define RBR_STAT_Addr mpeval(DMC_ADDRESS_RANGE+0x00028) | |
41 | #define ENABLE_PCIE_LINK_TRAINING | |
42 | #define ENABLE_PCIE_MPS_512 | |
43 | #define MAIN_PAGE_HV_ALSO | |
44 | ||
45 | #define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA) | |
46 | #define DMA_DATA_ADDR 0x0000000050000000 | |
47 | ||
48 | #define PEU_DEVICE_CNTRL_REG_ADDR FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR | |
49 | #define PEU_DEVICE_CNTRL__MPS_128 0 | |
50 | #define PEU_DEVICE_CNTRL__MPS_256 0x20 | |
51 | #define PEU_DEVICE_CNTRL__MPS_512 0x40 | |
52 | ||
53 | #include "hboot.s" | |
54 | #include "niu_defines.h" | |
55 | #include "peu_defines.h" | |
56 | .text | |
57 | .global main | |
58 | main: | |
59 | ta T_CHANGE_HPRIV | |
60 | nop | |
61 | ! enable bypass in IOMMU | |
62 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
63 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
64 | stx %g3, [%g2] | |
65 | ldx [%g2], %g3 | |
66 | ! branch to main by comparing thread id. | |
67 | ||
68 | ta T_RD_THID | |
69 | mov 0x1, %g2 | |
70 | ||
71 | setx 0x0000000000000001, %o0, %g3 ! thread-group bits for the template | |
72 | cmp %g2, %o1 | |
73 | be _FcN0_main | |
74 | nop | |
75 | ||
76 | setx 0x0000000000000010, %o0, %g3 ! thread-group bits for the template | |
77 | brz %o1, _FcN1_main | |
78 | mov 0x2, %g2 | |
79 | cmp %g2, %o1 | |
80 | be _FcN2_main | |
81 | nop | |
82 | # 116 "diag.j.pp" | |
83 | ! | |
84 | ! Thread 0 Start | |
85 | ! | |
86 | ! | |
87 | _FcN0_main: | |
88 | ||
89 | P_NIU_RxInitDma: | |
90 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma)) -> NIU_InitRxDma(1, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, NIU_Xlate_On) | |
91 | setx NIU_PKTGEN_CSR_EV2A_RBR_KICK, %g7, %g2 | |
92 | delay_loop_Rx: | |
93 | ldx [%g2], %g5 | |
94 | cmp %g5, RX_INITIAL_KICK | |
95 | bne delay_loop_Rx | |
96 | nop | |
97 | ||
98 | setx 0x1, %g1, %o0 | |
99 | setx RX_DESC_RING_LENGTH, %g1, %o1 | |
100 | setx RX_COMPL_RING_LEN, %g1, %o2 | |
101 | setx RBR_CONFIG_B_DATA, %g1, %o3 | |
102 | setx RX_INITIAL_KICK, %g1, %o4 | |
103 | call NiuInitRxDma | |
104 | nop | |
105 | P_NIU_RxPkt_Conf: | |
106 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT) | |
107 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
108 | nop | |
109 | setx RXMAC_PKTCNT, %g1, %g6 | |
110 | mulx %o0, 0x200, %g5 | |
111 | setx RBR_STAT_Addr, %g7, %g2 | |
112 | add %g2, %g5, %g2 | |
113 | P_NIU_Rx_GenPkt: | |
114 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
115 | brz %g5, P_NIU_Rx_GenPkt | |
116 | nop | |
117 | cmp %g5, %o4 | |
118 | be P_NIU_Rx_GenPkt | |
119 | nop | |
120 | ||
121 | Rx_pktcnt_loop: | |
122 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, 1, RXMAC_PKTCNT, 0x5dc, 0x0, RX_NIU_MULTI_DMA, 1) | |
123 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
124 | nop | |
125 | ||
126 | mulx %o0, 0x200, %g5 | |
127 | setx RCRSTAT_A_Addr, %g7, %g2 | |
128 | add %g2, %g5, %g2 | |
129 | delay_loop: | |
130 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
131 | cmp %g5, RXMAC_PKTCNT - RXMAC_PKTCNT%8 | |
132 | bne delay_loop | |
133 | nop | |
134 | ||
135 | ||
136 | test_passed: | |
137 | nop | |
138 | EXIT_GOOD | |
139 | # 188 "diag.j.pp" | |
140 | ||
141 | _FcN1_main: | |
142 | ||
143 | Init_flow: | |
144 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS, 5dc) | |
145 | ||
146 | P_TxDMAActivate: | |
147 | setx MAC_ID, %g1, %o0 | |
148 | setx 0x8000, %g1, %o1 | |
149 | call SetTxDMAActive | |
150 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, 8000) | |
151 | setx XMAC0_MAX_addr, %g7, %g2 | |
152 | ||
153 | ||
154 | P_AddTxChannels: | |
155 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, f) | |
156 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
157 | nop | |
158 | ||
159 | P_SetTxMaxBurst: | |
160 | setx 0xf, %g1, %o0 | |
161 | setx SetTxMaxBurst_Data, %g1, %o1 | |
162 | call SetTxMaxBurst | |
163 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, f, TxMaxBurst_Data) | |
164 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
165 | nop | |
166 | ||
167 | P_InitTxDma: | |
168 | setx 0xf, %g1, %o0 | |
169 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, f, NIU_Xlate_On) | |
170 | call InitTxDma | |
171 | nop | |
172 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
173 | nop | |
174 | ||
175 | Gen_Packet: | |
176 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, f, 0xcf, 0, 0) | |
177 | nop | |
178 | ||
179 | setx 0x5, %g1, %g4 | |
180 | delay_loop_tmp: | |
181 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
182 | nop | |
183 | nop | |
184 | nop | |
185 | nop | |
186 | dec %g4 | |
187 | brnz %g4, delay_loop_tmp | |
188 | nop | |
189 | ||
190 | SetTxRingKick: | |
191 | setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, f) | |
192 | setx 0xf, %g1, %o0 | |
193 | ldx [%g2], %g3 | |
194 | nop | |
195 | mulx %o0, 0x200, %g5 | |
196 | setx TX_RING_KICK_Addr, %g1, %g2 | |
197 | add %g2, %g5, %g2 | |
198 | stxa %g3, [%g2]ASI_PRIMARY_LITTLE | |
199 | nop | |
200 | ||
201 | SetTxCs: | |
202 | setx 0xf, %g1, %o0 | |
203 | setx TX_CS_Data, %g1, %g3 | |
204 | mulx %o0, 0x200, %g5 | |
205 | setx TX_CS_Addr, %g1, %g2 | |
206 | add %g2, %g5, %g2 | |
207 | stxa %g3, [%g2]ASI_PRIMARY_LITTLE | |
208 | nop | |
209 | ||
210 | #ifdef JUMBO_FRAME_EN | |
211 | setx loop_count, %g1, %g4 | |
212 | delay_loop: | |
213 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
214 | nop | |
215 | nop | |
216 | nop | |
217 | nop | |
218 | dec %g4 | |
219 | brnz %g4, delay_loop | |
220 | nop | |
221 | #endif | |
222 | ||
223 | ||
224 | NIUTx_Pkt_Cnt_Chk: | |
225 | setx MAC_ID, %g1, %o0 | |
226 | setx 0xcf, %g1, %o1 | |
227 | call NiuTx_check_pkt_cnt | |
228 | nop | |
229 | ||
230 | setx loop_count, %g1, %g4 | |
231 | delay_loop_end: | |
232 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
233 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
234 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
235 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
236 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
237 | dec %g4 | |
238 | brnz %g4, delay_loop_end | |
239 | nop | |
240 | ||
241 | test_passed_tx: | |
242 | nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed_tx)) -> NIU_EXIT_chk(MAC_ID) | |
243 | EXIT_GOOD | |
244 | ||
245 | ||
246 | _FcN2_main: | |
247 | setx RX_INITIAL_KICK, %g1, %o4 | |
248 | setx 0x1, %g1, %o0 | |
249 | mulx %o0, 0x200, %g5 | |
250 | setx RBR_STAT_Addr, %g7, %g2 | |
251 | add %g2, %g5, %g2 | |
252 | wt_for_niu: | |
253 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
254 | brz %g5, wt_for_niu | |
255 | nop | |
256 | cmp %g5, %o4 | |
257 | be wt_for_niu | |
258 | nop | |
259 | !Initializing integer registers | |
260 | setx 0xffffffff0000003f, %r30, %r28 | |
261 | ldx [%r31+0], %r0 | |
262 | andn %r0, %r28, %r0 | |
263 | ldx [%r31+8], %r1 | |
264 | andn %r1, %r28, %r1 | |
265 | ldx [%r31+16], %r2 | |
266 | andn %r2, %r28, %r2 | |
267 | ldx [%r31+24], %r3 | |
268 | andn %r3, %r28, %r3 | |
269 | ldx [%r31+32], %r4 | |
270 | andn %r4, %r28, %r4 | |
271 | ldx [%r31+40], %r5 | |
272 | andn %r5, %r28, %r5 | |
273 | ldx [%r31+48], %r6 | |
274 | andn %r6, %r28, %r6 | |
275 | ldx [%r31+56], %r7 | |
276 | andn %r7, %r28, %r7 | |
277 | ldx [%r31+64], %r8 | |
278 | andn %r8, %r28, %r8 | |
279 | ldx [%r31+72], %r9 | |
280 | andn %r9, %r28, %r9 | |
281 | ldx [%r31+80], %r10 | |
282 | andn %r10, %r28, %r10 | |
283 | ldx [%r31+88], %r11 | |
284 | andn %r11, %r28, %r11 | |
285 | ldx [%r31+96], %r12 | |
286 | andn %r12, %r28, %r12 | |
287 | ldx [%r31+104], %r13 | |
288 | andn %r13, %r28, %r13 | |
289 | save %r31, %r0, %r31 | |
290 | restore | |
291 | ||
292 | _DMAWr_t_DMA_store_exword_0: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
293 | ||
294 | _DMAWr_t_DMA_write_0: nop | |
295 | ||
296 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_0)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
297 | ||
298 | _DMAWr_t_DMA_store_partial_1: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
299 | ||
300 | _DMAWr_t_DMA_store_exword_2: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
301 | .word 0xd4408005 ! 4: LDSW_R ldsw [%r2 + %r5], %r10 | |
302 | ||
303 | _DMAWr_t_DMA_write_1: nop | |
304 | ||
305 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_1)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
306 | ||
307 | _DMAWr_t_DMA_store_partial_3: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
308 | ||
309 | _DMAWr_t_DMA_write_2: nop | |
310 | ||
311 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_2)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
312 | ||
313 | _DMAWr_t_DMA_store_partial_4: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
314 | ||
315 | _DMAWr_t_DMA_write_3: nop | |
316 | ||
317 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_3)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
318 | ||
319 | _DMAWr_t_DMA_store_partial_5: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
320 | ||
321 | _DMAWr_t_DMA_write_4: nop | |
322 | ||
323 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_4)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
324 | ||
325 | _DMAWr_t_DMA_store_partial_6: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
326 | ||
327 | _DMAWr_t_DMA_write_5: nop | |
328 | ||
329 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_5)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
330 | ||
331 | _DMAWr_t_DMA_store_partial_7: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
332 | ||
333 | _DMAWr_t_DMA_store_exword_8: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
334 | .word 0xd2288006 ! 16: STB_R stb %r9, [%r2 + %r6] | |
335 | ||
336 | _DMAWr_t_DMA_store_exword_9: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
337 | .word 0xd0704004 ! 18: STX_R stx %r8, [%r1 + %r4] | |
338 | ||
339 | _DMAWr_t_DMA_store_exword_10: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
340 | .word 0xd670c005 ! 20: STX_R stx %r11, [%r3 + %r5] | |
341 | ||
342 | _DMAWr_t_DMA_store_exword_11: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
343 | .word 0xd2280007 ! 22: STB_R stb %r9, [%r0 + %r7] | |
344 | ||
345 | _DMAWr_t_DMA_store_exword_12: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
346 | .word 0xd040c005 ! 24: LDSW_R ldsw [%r3 + %r5], %r8 | |
347 | ||
348 | _DMAWr_t_DMA_write_6: nop | |
349 | ||
350 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_6)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
351 | ||
352 | _DMAWr_t_DMA_store_partial_13: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
353 | ||
354 | _DMAWr_t_DMA_store_exword_14: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
355 | .word 0xd4288004 ! 28: STB_R stb %r10, [%r2 + %r4] | |
356 | ||
357 | _DMAWr_t_DMA_store_exword_15: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
358 | .word 0xd6408004 ! 30: LDSW_R ldsw [%r2 + %r4], %r11 | |
359 | ||
360 | _DMAWr_t_DMA_store_exword_16: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
361 | .word 0xd0304005 ! 32: STH_R sth %r8, [%r1 + %r5] | |
362 | ||
363 | _DMAWr_t_DMA_write_7: nop | |
364 | ||
365 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_7)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
366 | ||
367 | _DMAWr_t_DMA_store_partial_17: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
368 | ||
369 | _DMAWr_t_DMA_write_8: nop | |
370 | ||
371 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_8)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
372 | ||
373 | _DMAWr_t_DMA_store_partial_18: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
374 | ||
375 | _DMAWr_t_DMA_store_exword_19: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
376 | .word 0xd6704007 ! 38: STX_R stx %r11, [%r1 + %r7] | |
377 | ||
378 | _DMAWr_t_DMA_store_exword_20: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
379 | .word 0xd2284004 ! 40: STB_R stb %r9, [%r1 + %r4] | |
380 | ||
381 | _DMAWr_t_DMA_write_9: nop | |
382 | ||
383 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_9)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
384 | ||
385 | _DMAWr_t_DMA_store_partial_21: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
386 | ||
387 | _DMAWr_t_DMA_store_exword_22: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
388 | .word 0xd640c004 ! 44: LDSW_R ldsw [%r3 + %r4], %r11 | |
389 | ||
390 | _DMAWr_t_DMA_write_10: nop | |
391 | ||
392 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_10)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
393 | ||
394 | _DMAWr_t_DMA_store_partial_23: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
395 | ||
396 | _DMAWr_t_DMA_store_exword_24: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
397 | .word 0xd470c007 ! 48: STX_R stx %r10, [%r3 + %r7] | |
398 | ||
399 | _DMAWr_t_DMA_write_11: nop | |
400 | ||
401 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_11)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
402 | ||
403 | _DMAWr_t_DMA_store_partial_25: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
404 | ||
405 | _DMAWr_t_DMA_write_12: nop | |
406 | ||
407 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_12)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
408 | ||
409 | _DMAWr_t_DMA_store_partial_26: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
410 | ||
411 | _DMAWr_t_DMA_store_exword_27: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
412 | .word 0xd0584005 ! 54: LDX_R ldx [%r1 + %r5], %r8 | |
413 | ||
414 | _DMAWr_t_DMA_store_exword_28: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
415 | .word 0xd0304004 ! 56: STH_R sth %r8, [%r1 + %r4] | |
416 | ||
417 | _DMAWr_t_DMA_write_13: nop | |
418 | ||
419 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_13)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
420 | ||
421 | _DMAWr_t_DMA_store_partial_29: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
422 | ||
423 | _DMAWr_t_DMA_write_14: nop | |
424 | ||
425 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_14)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
426 | ||
427 | _DMAWr_t_DMA_store_partial_30: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
428 | ||
429 | _DMAWr_t_DMA_write_15: nop | |
430 | ||
431 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_15)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
432 | ||
433 | _DMAWr_t_DMA_store_partial_31: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
434 | ||
435 | _DMAWr_t_DMA_store_exword_32: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
436 | .word 0xd4404007 ! 64: LDSW_R ldsw [%r1 + %r7], %r10 | |
437 | ||
438 | _DMAWr_t_DMA_write_16: nop | |
439 | ||
440 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_16)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
441 | ||
442 | _DMAWr_t_DMA_store_partial_33: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
443 | ||
444 | _DMAWr_t_DMA_store_exword_34: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
445 | .word 0xd4200004 ! 68: STW_R stw %r10, [%r0 + %r4] | |
446 | ||
447 | _DMAWr_t_DMA_write_17: nop | |
448 | ||
449 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_17)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
450 | ||
451 | _DMAWr_t_DMA_store_partial_35: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
452 | ||
453 | _DMAWr_t_DMA_write_18: nop | |
454 | ||
455 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_18)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
456 | ||
457 | _DMAWr_t_DMA_store_partial_36: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
458 | ||
459 | _DMAWr_t_DMA_store_exword_37: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
460 | .word 0xd4700006 ! 74: STX_R stx %r10, [%r0 + %r6] | |
461 | ||
462 | _DMAWr_t_DMA_write_19: nop | |
463 | ||
464 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_19)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
465 | ||
466 | _DMAWr_t_DMA_store_partial_38: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
467 | ||
468 | _DMAWr_t_DMA_store_exword_39: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
469 | .word 0xd2400005 ! 78: LDSW_R ldsw [%r0 + %r5], %r9 | |
470 | ||
471 | _DMAWr_t_DMA_store_exword_40: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
472 | .word 0xd4208006 ! 80: STW_R stw %r10, [%r2 + %r6] | |
473 | ||
474 | _DMAWr_t_DMA_write_20: nop | |
475 | ||
476 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_20)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
477 | ||
478 | _DMAWr_t_DMA_store_partial_41: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
479 | ||
480 | _DMAWr_t_DMA_store_exword_42: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
481 | .word 0xd2704006 ! 84: STX_R stx %r9, [%r1 + %r6] | |
482 | ||
483 | _DMAWr_t_DMA_store_exword_43: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
484 | .word 0xd070c006 ! 86: STX_R stx %r8, [%r3 + %r6] | |
485 | ||
486 | _DMAWr_t_DMA_store_exword_44: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
487 | .word 0xd4280004 ! 88: STB_R stb %r10, [%r0 + %r4] | |
488 | ||
489 | _DMAWr_t_DMA_store_exword_45: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
490 | .word 0xd430c007 ! 90: STH_R sth %r10, [%r3 + %r7] | |
491 | ||
492 | _DMAWr_t_DMA_store_exword_46: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
493 | .word 0xd2400007 ! 92: LDSW_R ldsw [%r0 + %r7], %r9 | |
494 | ||
495 | _DMAWr_t_DMA_store_exword_47: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
496 | .word 0xd4400007 ! 94: LDSW_R ldsw [%r0 + %r7], %r10 | |
497 | ||
498 | _DMAWr_t_DMA_write_21: nop | |
499 | ||
500 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_21)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
501 | ||
502 | _DMAWr_t_DMA_store_partial_48: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
503 | ||
504 | _DMAWr_t_DMA_store_exword_49: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
505 | .word 0xd2308007 ! 98: STH_R sth %r9, [%r2 + %r7] | |
506 | ||
507 | _DMAWr_t_DMA_store_exword_50: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
508 | .word 0xd2284005 ! 100: STB_R stb %r9, [%r1 + %r5] | |
509 | ||
510 | _DMAWr_t_DMA_store_exword_51: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
511 | .word 0xd2308006 ! 102: STH_R sth %r9, [%r2 + %r6] | |
512 | ||
513 | _DMAWr_t_DMA_write_22: nop | |
514 | ||
515 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_22)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
516 | ||
517 | _DMAWr_t_DMA_store_partial_52: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
518 | ||
519 | _DMAWr_t_DMA_write_23: nop | |
520 | ||
521 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_23)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
522 | ||
523 | _DMAWr_t_DMA_store_partial_53: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
524 | ||
525 | _DMAWr_t_DMA_store_exword_54: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
526 | .word 0xd6288004 ! 108: STB_R stb %r11, [%r2 + %r4] | |
527 | ||
528 | _DMAWr_t_DMA_write_24: nop | |
529 | ||
530 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_24)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
531 | ||
532 | _DMAWr_t_DMA_store_partial_55: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
533 | ||
534 | _DMAWr_t_DMA_store_exword_56: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
535 | .word 0xd0308007 ! 112: STH_R sth %r8, [%r2 + %r7] | |
536 | ||
537 | _DMAWr_t_DMA_store_exword_57: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
538 | .word 0xd4584007 ! 114: LDX_R ldx [%r1 + %r7], %r10 | |
539 | ||
540 | _DMAWr_t_DMA_write_25: nop | |
541 | ||
542 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_25)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
543 | ||
544 | _DMAWr_t_DMA_store_partial_58: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
545 | ||
546 | _DMAWr_t_DMA_store_exword_59: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25] | |
547 | .word 0xd2704007 ! 118: STX_R stx %r9, [%r1 + %r7] | |
548 | ||
549 | _DMAWr_t_DMA_write_26: nop | |
550 | ||
551 | ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_26)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1) | |
552 | ||
553 | _DMAWr_t_DMA_store_partial_60: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27] | |
554 | nop | |
555 | nop | |
556 | ||
557 | ! select a MEM32 address in PCI address range and transmit the command to NCU | |
558 | ||
559 | setx MEM32_RD_ADDR, %g1, %g2 | |
560 | setx 0x080, %g1, %g4 ! loop 128 times | |
561 | ||
562 | delay_loop_pcie: | |
563 | stx %g2, [%g2] ! MEM32 PIO Write | |
564 | ldx [%g2], %l0 ! MEM32 PIO READ | |
565 | add %g2, 8, %g2 ! increment PIO address | |
566 | ||
567 | dec %g4 ! decrement counter | |
568 | brnz %g4, delay_loop_pcie ! loop if not zero | |
569 | nop | |
570 | ||
571 | ||
572 | pcie_test_passed: | |
573 | EXIT_GOOD | |
574 | ||
575 | pcie_test_failed: | |
576 | EXIT_BAD | |
577 | ||
578 | SECTION descriptor data_va=DMA_DATA_ADDR | |
579 | attr_data { | |
580 | Name = descriptor, | |
581 | hypervisor, | |
582 | compressimage | |
583 | } | |
584 | ||
585 | .data | |
586 | .global PCIAddr9 | |
587 | ||
588 | .xword 0x1011121314151617 | |
589 | .xword 0x18191a1b1c1d1e1f | |
590 | .xword 0x2021222324252627 | |
591 | .xword 0x28292a2b2c2d2e2f | |
592 | .xword 0x3031323334353637 | |
593 | .xword 0x38393a3b3c3d3e3f | |
594 | .xword 0x4041424344454647 | |
595 | .xword 0x48494a4b4c4d4e4f | |
596 | .xword 0xffffffffffffffff | |
597 | .xword 0xffffffffffffffff | |
598 | .xword 0x1011121314151617 | |
599 | .xword 0x18191a1b1c1d1e1f | |
600 | .xword 0x2021222324252627 | |
601 | .xword 0x28292a2b2c2d2e2f | |
602 | .xword 0x3031323334353637 | |
603 | .xword 0x38393a3b3c3d3e3f | |
604 | .xword 0x4041424344454647 | |
605 | .xword 0x48494a4b4c4d4e4f | |
606 | .xword 0xffffffffffffffff | |
607 | .xword 0xffffffffffffffff | |
608 | .xword 0x1011121314151617 | |
609 | .xword 0x18191a1b1c1d1e1f | |
610 | .xword 0x2021222324252627 | |
611 | .xword 0x28292a2b2c2d2e2f | |
612 | .xword 0x3031323334353637 | |
613 | .xword 0x38393a3b3c3d3e3f | |
614 | .xword 0x4041424344454647 | |
615 | .xword 0x48494a4b4c4d4e4f | |
616 | .xword 0xffffffffffffffff | |
617 | .xword 0xffffffffffffffff | |
618 | .xword 0x1011121314151617 | |
619 | .xword 0x18191a1b1c1d1e1f | |
620 | .xword 0x2021222324252627 | |
621 | .xword 0x28292a2b2c2d2e2f | |
622 | .xword 0x3031323334353637 | |
623 | .xword 0x38393a3b3c3d3e3f | |
624 | .xword 0x4041424344454647 | |
625 | .xword 0x48494a4b4c4d4e4f | |
626 | .xword 0xffffffffffffffff | |
627 | .xword 0xffffffffffffffff | |
628 | .xword 0x1011121314151617 | |
629 | .xword 0x18191a1b1c1d1e1f | |
630 | .xword 0x2021222324252627 | |
631 | .xword 0x28292a2b2c2d2e2f | |
632 | .xword 0x3031323334353637 | |
633 | .xword 0x38393a3b3c3d3e3f | |
634 | .xword 0x4041424344454647 | |
635 | .xword 0x48494a4b4c4d4e4f | |
636 | .xword 0xffffffffffffffff | |
637 | .xword 0xffffffffffffffff | |
638 | .xword 0x1011121314151617 | |
639 | .xword 0x18191a1b1c1d1e1f | |
640 | .xword 0x2021222324252627 | |
641 | .xword 0x28292a2b2c2d2e2f | |
642 | .xword 0x3031323334353637 | |
643 | .xword 0x38393a3b3c3d3e3f | |
644 | .xword 0x4041424344454647 | |
645 | .xword 0x48494a4b4c4d4e4f | |
646 | .xword 0xffffffffffffffff | |
647 | .xword 0xffffffffffffffff | |
648 | .xword 0x1011121314151617 | |
649 | .xword 0x18191a1b1c1d1e1f | |
650 | .xword 0x2021222324252627 | |
651 | .xword 0x28292a2b2c2d2e2f | |
652 | .xword 0x3031323334353637 | |
653 | .xword 0x38393a3b3c3d3e3f | |
654 | .xword 0x4041424344454647 | |
655 | .xword 0x48494a4b4c4d4e4f | |
656 | .xword 0xffffffffffffffff | |
657 | .xword 0xffffffffffffffff | |
658 | .xword 0x1011121314151617 | |
659 | .xword 0x18191a1b1c1d1e1f | |
660 | .xword 0x2021222324252627 | |
661 | .xword 0x28292a2b2c2d2e2f | |
662 | .xword 0x3031323334353637 | |
663 | .xword 0x38393a3b3c3d3e3f | |
664 | .xword 0x4041424344454647 | |
665 | .xword 0x48494a4b4c4d4e4f | |
666 | .xword 0xffffffffffffffff | |
667 | .xword 0xffffffffffffffff | |
668 | .xword 0x1011121314151617 | |
669 | .xword 0x18191a1b1c1d1e1f | |
670 | .xword 0x2021222324252627 | |
671 | .xword 0x28292a2b2c2d2e2f | |
672 | .xword 0x3031323334353637 | |
673 | .xword 0x38393a3b3c3d3e3f | |
674 | .xword 0x4041424344454647 | |
675 | .xword 0x48494a4b4c4d4e4f | |
676 | .xword 0xffffffffffffffff | |
677 | .xword 0xffffffffffffffff | |
678 | ||
679 | ||
680 | #if 0 | |
681 | #endif | |
682 |