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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / cov / FcNiuPeuRand_2.s
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: FcNiuPeuRand_2.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define RCRSTAT_A_Addr mpeval(DMC_ADDRESS_RANGE+0x00050)
40#define RBR_STAT_Addr mpeval(DMC_ADDRESS_RANGE+0x00028)
41#define ENABLE_PCIE_LINK_TRAINING
42#define ENABLE_PCIE_MPS_512
43#define MAIN_PAGE_HV_ALSO
44
45#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
46#define DMA_DATA_ADDR 0x0000000050000000
47
48#define PEU_DEVICE_CNTRL_REG_ADDR FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR
49#define PEU_DEVICE_CNTRL__MPS_128 0
50#define PEU_DEVICE_CNTRL__MPS_256 0x20
51#define PEU_DEVICE_CNTRL__MPS_512 0x40
52
53#include "hboot.s"
54#include "niu_defines.h"
55#include "peu_defines.h"
56.text
57.global main
58main:
59 ta T_CHANGE_HPRIV
60 nop
61 ! enable bypass in IOMMU
62 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
63 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
64 stx %g3, [%g2]
65 ldx [%g2], %g3
66! branch to main by comparing thread id.
67
68 ta T_RD_THID
69 mov 0x1, %g2
70
71 setx 0x0000000000000001, %o0, %g3 ! thread-group bits for the template
72 cmp %g2, %o1
73 be _FcN0_main
74 nop
75
76 setx 0x0000000000000010, %o0, %g3 ! thread-group bits for the template
77 brz %o1, _FcN1_main
78 mov 0x2, %g2
79 cmp %g2, %o1
80 be _FcN2_main
81 nop
82# 116 "diag.j.pp"
83!
84! Thread 0 Start
85!
86!
87_FcN0_main:
88
89P_NIU_RxInitDma:
90 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma)) -> NIU_InitRxDma(a, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, NIU_Xlate_On)
91 setx NIU_PKTGEN_CSR_EV2A_RBR_KICK, %g7, %g2
92delay_loop_Rx:
93 ldx [%g2], %g5
94 cmp %g5, RX_INITIAL_KICK
95 bne delay_loop_Rx
96 nop
97
98 setx 0xa, %g1, %o0
99 setx RX_DESC_RING_LENGTH, %g1, %o1
100 setx RX_COMPL_RING_LEN, %g1, %o2
101 setx RBR_CONFIG_B_DATA, %g1, %o3
102 setx RX_INITIAL_KICK, %g1, %o4
103 call NiuInitRxDma
104 nop
105P_NIU_RxPkt_Conf:
106 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT)
107 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
108 nop
109 setx RXMAC_PKTCNT, %g1, %g6
110 mulx %o0, 0x200, %g5
111 setx RBR_STAT_Addr, %g7, %g2
112 add %g2, %g5, %g2
113P_NIU_Rx_GenPkt:
114 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
115 brz %g5, P_NIU_Rx_GenPkt
116 nop
117 cmp %g5, %o4
118 be P_NIU_Rx_GenPkt
119 nop
120
121Rx_pktcnt_loop:
122 nop ! $EV trig_pc_d(1, @VA(.MAIN.Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, a, RXMAC_PKTCNT, 0xc8, 0x0, RX_NIU_MULTI_DMA, 1)
123 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
124 nop
125
126 mulx %o0, 0x200, %g5
127 setx RCRSTAT_A_Addr, %g7, %g2
128 add %g2, %g5, %g2
129delay_loop:
130 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
131 cmp %g5, RXMAC_PKTCNT - RXMAC_PKTCNT%8
132 bne delay_loop
133 nop
134
135
136test_passed:
137 nop
138 EXIT_GOOD
139# 188 "diag.j.pp"
140
141_FcN1_main:
142
143Init_flow:
144 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS, 5dc)
145
146P_TxDMAActivate:
147 setx MAC_ID, %g1, %o0
148 setx 0x1, %g1, %o1
149 call SetTxDMAActive
150 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, 1)
151 setx XMAC0_MAX_addr, %g7, %g2
152
153
154P_AddTxChannels:
155 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, 0)
156 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
157 nop
158
159P_SetTxMaxBurst:
160 setx 0x0, %g1, %o0
161 setx SetTxMaxBurst_Data, %g1, %o1
162 call SetTxMaxBurst
163 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, 0, TxMaxBurst_Data)
164 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
165 nop
166
167P_InitTxDma:
168 setx 0x0, %g1, %o0
169 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, 0, NIU_Xlate_On)
170 call InitTxDma
171 nop
172 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
173 nop
174
175Gen_Packet:
176 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, 0, 0x86,0,0)
177 nop
178
179 setx 0x5, %g1, %g4
180delay_loop_tmp:
181 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
182 nop
183 nop
184 nop
185 nop
186 dec %g4
187 brnz %g4, delay_loop_tmp
188 nop
189
190SetTxRingKick:
191 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, 0)
192 setx 0x0, %g1, %o0
193 ldx [%g2], %g3
194 nop
195 mulx %o0, 0x200, %g5
196 setx TX_RING_KICK_Addr, %g1, %g2
197 add %g2, %g5, %g2
198 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
199 nop
200
201SetTxCs:
202 setx 0x0, %g1, %o0
203 setx TX_CS_Data, %g1, %g3
204 mulx %o0, 0x200, %g5
205 setx TX_CS_Addr, %g1, %g2
206 add %g2, %g5, %g2
207 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
208 nop
209
210#ifdef JUMBO_FRAME_EN
211 setx loop_count, %g1, %g4
212delay_loop:
213 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
214 nop
215 nop
216 nop
217 nop
218 dec %g4
219 brnz %g4, delay_loop
220 nop
221#endif
222
223
224NIUTx_Pkt_Cnt_Chk:
225 setx MAC_ID, %g1, %o0
226 setx 0x86, %g1, %o1
227 call NiuTx_check_pkt_cnt
228 nop
229
230 setx loop_count, %g1, %g4
231delay_loop_end:
232 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
233 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
234 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
235 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
236 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
237 dec %g4
238 brnz %g4, delay_loop_end
239 nop
240
241test_passed_tx:
242 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed_tx)) -> NIU_EXIT_chk(MAC_ID)
243 EXIT_GOOD
244
245
246_FcN2_main:
247 setx RX_INITIAL_KICK, %g1, %o4
248 setx 0xa, %g1, %o0
249 mulx %o0, 0x200, %g5
250 setx RBR_STAT_Addr, %g7, %g2
251 add %g2, %g5, %g2
252wt_for_niu:
253 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
254 brz %g5, wt_for_niu
255 nop
256 cmp %g5, %o4
257 be wt_for_niu
258 nop
259!Initializing integer registers
260 setx 0xffffffff0000003f, %r30, %r28
261 ldx [%r31+0], %r0
262 andn %r0, %r28, %r0
263 ldx [%r31+8], %r1
264 andn %r1, %r28, %r1
265 ldx [%r31+16], %r2
266 andn %r2, %r28, %r2
267 ldx [%r31+24], %r3
268 andn %r3, %r28, %r3
269 ldx [%r31+32], %r4
270 andn %r4, %r28, %r4
271 ldx [%r31+40], %r5
272 andn %r5, %r28, %r5
273 ldx [%r31+48], %r6
274 andn %r6, %r28, %r6
275 ldx [%r31+56], %r7
276 andn %r7, %r28, %r7
277 ldx [%r31+64], %r8
278 andn %r8, %r28, %r8
279 ldx [%r31+72], %r9
280 andn %r9, %r28, %r9
281 ldx [%r31+80], %r10
282 andn %r10, %r28, %r10
283 ldx [%r31+88], %r11
284 andn %r11, %r28, %r11
285 ldx [%r31+96], %r12
286 andn %r12, %r28, %r12
287 ldx [%r31+104], %r13
288 andn %r13, %r28, %r13
289 save %r31, %r0, %r31
290 restore
291
292_DMAWr_t_DMA_store_exword_0: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
293
294_DMAWr_t_DMA_store_exword_1: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
295 .word 0xd0708004 ! 2: STX_R stx %r8, [%r2 + %r4]
296
297_DMAWr_t_DMA_write_0: nop
298
299 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_0)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
300
301_DMAWr_t_DMA_store_partial_2: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
302
303_DMAWr_t_DMA_write_1: nop
304
305 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_1)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
306
307_DMAWr_t_DMA_store_partial_3: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
308
309_DMAWr_t_DMA_store_exword_4: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
310 .word 0xd070c004 ! 8: STX_R stx %r8, [%r3 + %r4]
311
312_DMAWr_t_DMA_write_2: nop
313
314 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_2)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
315
316_DMAWr_t_DMA_store_partial_5: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
317
318_DMAWr_t_DMA_store_exword_6: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
319 .word 0xd4588007 ! 12: LDX_R ldx [%r2 + %r7], %r10
320
321_DMAWr_t_DMA_write_3: nop
322
323 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_3)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
324
325_DMAWr_t_DMA_store_partial_7: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
326
327_DMAWr_t_DMA_store_exword_8: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
328 .word 0xd0280005 ! 16: STB_R stb %r8, [%r0 + %r5]
329
330_DMAWr_t_DMA_store_exword_9: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
331 .word 0xd058c005 ! 18: LDX_R ldx [%r3 + %r5], %r8
332
333_DMAWr_t_DMA_write_4: nop
334
335 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_4)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
336
337_DMAWr_t_DMA_store_partial_10: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
338
339_DMAWr_t_DMA_store_exword_11: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
340 .word 0xd4580005 ! 22: LDX_R ldx [%r0 + %r5], %r10
341
342_DMAWr_t_DMA_store_exword_12: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
343 .word 0xd6580007 ! 24: LDX_R ldx [%r0 + %r7], %r11
344
345_DMAWr_t_DMA_store_exword_13: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
346 .word 0xd2708007 ! 26: STX_R stx %r9, [%r2 + %r7]
347
348_DMAWr_t_DMA_store_exword_14: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
349 .word 0xd6400004 ! 28: LDSW_R ldsw [%r0 + %r4], %r11
350
351_DMAWr_t_DMA_write_5: nop
352
353 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_5)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
354
355_DMAWr_t_DMA_store_partial_15: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
356
357_DMAWr_t_DMA_write_6: nop
358
359 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_6)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
360
361_DMAWr_t_DMA_store_partial_16: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
362
363_DMAWr_t_DMA_write_7: nop
364
365 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_7)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
366
367_DMAWr_t_DMA_store_partial_17: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
368
369_DMAWr_t_DMA_write_8: nop
370
371 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_8)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
372
373_DMAWr_t_DMA_store_partial_18: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
374
375_DMAWr_t_DMA_store_exword_19: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
376 .word 0xd2308005 ! 38: STH_R sth %r9, [%r2 + %r5]
377
378_DMAWr_t_DMA_write_9: nop
379
380 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_9)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
381
382_DMAWr_t_DMA_store_partial_20: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
383
384_DMAWr_t_DMA_store_exword_21: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
385 .word 0xd6704005 ! 42: STX_R stx %r11, [%r1 + %r5]
386
387_DMAWr_t_DMA_write_10: nop
388
389 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_10)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
390
391_DMAWr_t_DMA_store_partial_22: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
392
393_DMAWr_t_DMA_write_11: nop
394
395 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_11)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
396
397_DMAWr_t_DMA_store_partial_23: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
398
399_DMAWr_t_DMA_write_12: nop
400
401 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_12)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
402
403_DMAWr_t_DMA_store_partial_24: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
404
405_DMAWr_t_DMA_write_13: nop
406
407 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_13)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
408
409_DMAWr_t_DMA_store_partial_25: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
410
411_DMAWr_t_DMA_store_exword_26: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
412 .word 0xd2300006 ! 52: STH_R sth %r9, [%r0 + %r6]
413
414_DMAWr_t_DMA_store_exword_27: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
415 .word 0xd4700007 ! 54: STX_R stx %r10, [%r0 + %r7]
416
417_DMAWr_t_DMA_write_14: nop
418
419 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_14)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
420
421_DMAWr_t_DMA_store_partial_28: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
422
423_DMAWr_t_DMA_store_exword_29: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
424 .word 0xd2200005 ! 58: STW_R stw %r9, [%r0 + %r5]
425
426_DMAWr_t_DMA_write_15: nop
427
428 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_15)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
429
430_DMAWr_t_DMA_store_partial_30: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
431
432_DMAWr_t_DMA_store_exword_31: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
433 .word 0xd6588005 ! 62: LDX_R ldx [%r2 + %r5], %r11
434
435_DMAWr_t_DMA_store_exword_32: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
436 .word 0xd6404004 ! 64: LDSW_R ldsw [%r1 + %r4], %r11
437
438_DMAWr_t_DMA_write_16: nop
439
440 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_16)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
441
442_DMAWr_t_DMA_store_partial_33: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
443
444_DMAWr_t_DMA_write_17: nop
445
446 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_17)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
447
448_DMAWr_t_DMA_store_partial_34: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
449
450_DMAWr_t_DMA_write_18: nop
451
452 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_18)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
453
454_DMAWr_t_DMA_store_partial_35: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
455
456_DMAWr_t_DMA_store_exword_36: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
457 .word 0xd0288006 ! 72: STB_R stb %r8, [%r2 + %r6]
458
459_DMAWr_t_DMA_write_19: nop
460
461 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_19)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
462
463_DMAWr_t_DMA_store_partial_37: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
464
465_DMAWr_t_DMA_store_exword_38: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
466 .word 0xd4580007 ! 76: LDX_R ldx [%r0 + %r7], %r10
467
468_DMAWr_t_DMA_store_exword_39: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
469 .word 0xd640c005 ! 78: LDSW_R ldsw [%r3 + %r5], %r11
470
471_DMAWr_t_DMA_store_exword_40: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
472 .word 0xd0300006 ! 80: STH_R sth %r8, [%r0 + %r6]
473
474_DMAWr_t_DMA_write_20: nop
475
476 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_20)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
477
478_DMAWr_t_DMA_store_partial_41: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
479
480_DMAWr_t_DMA_store_exword_42: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
481 .word 0xd2584004 ! 84: LDX_R ldx [%r1 + %r4], %r9
482
483_DMAWr_t_DMA_store_exword_43: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
484 .word 0xd0400007 ! 86: LDSW_R ldsw [%r0 + %r7], %r8
485
486_DMAWr_t_DMA_write_21: nop
487
488 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_21)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
489
490_DMAWr_t_DMA_store_partial_44: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
491
492_DMAWr_t_DMA_store_exword_45: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
493 .word 0xd6400005 ! 90: LDSW_R ldsw [%r0 + %r5], %r11
494
495_DMAWr_t_DMA_write_22: nop
496
497 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_22)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
498
499_DMAWr_t_DMA_store_partial_46: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
500
501_DMAWr_t_DMA_store_exword_47: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
502 .word 0xd0208004 ! 94: STW_R stw %r8, [%r2 + %r4]
503
504_DMAWr_t_DMA_write_23: nop
505
506 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_23)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
507
508_DMAWr_t_DMA_store_partial_48: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
509
510_DMAWr_t_DMA_write_24: nop
511
512 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_24)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
513
514_DMAWr_t_DMA_store_partial_49: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
515
516_DMAWr_t_DMA_store_exword_50: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
517 .word 0xd2400006 ! 100: LDSW_R ldsw [%r0 + %r6], %r9
518
519_DMAWr_t_DMA_write_25: nop
520
521 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_25)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
522
523_DMAWr_t_DMA_store_partial_51: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
524
525_DMAWr_t_DMA_write_26: nop
526
527 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_26)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
528
529_DMAWr_t_DMA_store_partial_52: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
530
531_DMAWr_t_DMA_store_exword_53: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
532 .word 0xd4300005 ! 106: STH_R sth %r10, [%r0 + %r5]
533
534_DMAWr_t_DMA_write_27: nop
535
536 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_27)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
537
538_DMAWr_t_DMA_store_partial_54: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
539
540_DMAWr_t_DMA_store_exword_55: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
541 .word 0xd220c007 ! 110: STW_R stw %r9, [%r3 + %r7]
542
543_DMAWr_t_DMA_store_exword_56: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
544 .word 0xd2400007 ! 112: LDSW_R ldsw [%r0 + %r7], %r9
545
546_DMAWr_t_DMA_write_28: nop
547
548 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_28)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
549
550_DMAWr_t_DMA_store_partial_57: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
551
552_DMAWr_t_DMA_store_exword_58: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
553 .word 0xd2588007 ! 116: LDX_R ldx [%r2 + %r7], %r9
554
555_DMAWr_t_DMA_write_29: nop
556
557 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_29)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
558
559_DMAWr_t_DMA_store_partial_59: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
560
561_DMAWr_t_DMA_write_30: nop
562
563 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_30)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
564
565_DMAWr_t_DMA_store_partial_60: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
566 nop
567 nop
568
569 ! select a MEM32 address in PCI address range and transmit the command to NCU
570
571 setx MEM32_RD_ADDR, %g1, %g2
572 setx 0x080, %g1, %g4 ! loop 128 times
573
574delay_loop_pcie:
575 stx %g2, [%g2] ! MEM32 PIO Write
576 ldx [%g2], %l0 ! MEM32 PIO READ
577 add %g2, 8, %g2 ! increment PIO address
578
579 dec %g4 ! decrement counter
580 brnz %g4, delay_loop_pcie ! loop if not zero
581 nop
582
583
584pcie_test_passed:
585 EXIT_GOOD
586
587pcie_test_failed:
588 EXIT_BAD
589
590SECTION descriptor data_va=DMA_DATA_ADDR
591attr_data {
592 Name = descriptor,
593 hypervisor,
594 compressimage
595}
596
597.data
598.global PCIAddr9
599
600 .xword 0x1011121314151617
601 .xword 0x18191a1b1c1d1e1f
602 .xword 0x2021222324252627
603 .xword 0x28292a2b2c2d2e2f
604 .xword 0x3031323334353637
605 .xword 0x38393a3b3c3d3e3f
606 .xword 0x4041424344454647
607 .xword 0x48494a4b4c4d4e4f
608 .xword 0xffffffffffffffff
609 .xword 0xffffffffffffffff
610 .xword 0x1011121314151617
611 .xword 0x18191a1b1c1d1e1f
612 .xword 0x2021222324252627
613 .xword 0x28292a2b2c2d2e2f
614 .xword 0x3031323334353637
615 .xword 0x38393a3b3c3d3e3f
616 .xword 0x4041424344454647
617 .xword 0x48494a4b4c4d4e4f
618 .xword 0xffffffffffffffff
619 .xword 0xffffffffffffffff
620 .xword 0x1011121314151617
621 .xword 0x18191a1b1c1d1e1f
622 .xword 0x2021222324252627
623 .xword 0x28292a2b2c2d2e2f
624 .xword 0x3031323334353637
625 .xword 0x38393a3b3c3d3e3f
626 .xword 0x4041424344454647
627 .xword 0x48494a4b4c4d4e4f
628 .xword 0xffffffffffffffff
629 .xword 0xffffffffffffffff
630 .xword 0x1011121314151617
631 .xword 0x18191a1b1c1d1e1f
632 .xword 0x2021222324252627
633 .xword 0x28292a2b2c2d2e2f
634 .xword 0x3031323334353637
635 .xword 0x38393a3b3c3d3e3f
636 .xword 0x4041424344454647
637 .xword 0x48494a4b4c4d4e4f
638 .xword 0xffffffffffffffff
639 .xword 0xffffffffffffffff
640 .xword 0x1011121314151617
641 .xword 0x18191a1b1c1d1e1f
642 .xword 0x2021222324252627
643 .xword 0x28292a2b2c2d2e2f
644 .xword 0x3031323334353637
645 .xword 0x38393a3b3c3d3e3f
646 .xword 0x4041424344454647
647 .xword 0x48494a4b4c4d4e4f
648 .xword 0xffffffffffffffff
649 .xword 0xffffffffffffffff
650 .xword 0x1011121314151617
651 .xword 0x18191a1b1c1d1e1f
652 .xword 0x2021222324252627
653 .xword 0x28292a2b2c2d2e2f
654 .xword 0x3031323334353637
655 .xword 0x38393a3b3c3d3e3f
656 .xword 0x4041424344454647
657 .xword 0x48494a4b4c4d4e4f
658 .xword 0xffffffffffffffff
659 .xword 0xffffffffffffffff
660 .xword 0x1011121314151617
661 .xword 0x18191a1b1c1d1e1f
662 .xword 0x2021222324252627
663 .xword 0x28292a2b2c2d2e2f
664 .xword 0x3031323334353637
665 .xword 0x38393a3b3c3d3e3f
666 .xword 0x4041424344454647
667 .xword 0x48494a4b4c4d4e4f
668 .xword 0xffffffffffffffff
669 .xword 0xffffffffffffffff
670 .xword 0x1011121314151617
671 .xword 0x18191a1b1c1d1e1f
672 .xword 0x2021222324252627
673 .xword 0x28292a2b2c2d2e2f
674 .xword 0x3031323334353637
675 .xword 0x38393a3b3c3d3e3f
676 .xword 0x4041424344454647
677 .xword 0x48494a4b4c4d4e4f
678 .xword 0xffffffffffffffff
679 .xword 0xffffffffffffffff
680 .xword 0x1011121314151617
681 .xword 0x18191a1b1c1d1e1f
682 .xword 0x2021222324252627
683 .xword 0x28292a2b2c2d2e2f
684 .xword 0x3031323334353637
685 .xword 0x38393a3b3c3d3e3f
686 .xword 0x4041424344454647
687 .xword 0x48494a4b4c4d4e4f
688 .xword 0xffffffffffffffff
689 .xword 0xffffffffffffffff
690
691
692#if 0
693#endif
694
Full OpenSPARC design & verification tarball including full HDL.