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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / cov / FcNiuPeuRand_3.s
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: FcNiuPeuRand_3.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define RCRSTAT_A_Addr mpeval(DMC_ADDRESS_RANGE+0x00050)
40#define RBR_STAT_Addr mpeval(DMC_ADDRESS_RANGE+0x00028)
41#define ENABLE_PCIE_LINK_TRAINING
42#define ENABLE_PCIE_MPS_512
43#define MAIN_PAGE_HV_ALSO
44
45#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
46#define DMA_DATA_ADDR 0x0000000050000000
47
48#define PEU_DEVICE_CNTRL_REG_ADDR FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR
49#define PEU_DEVICE_CNTRL__MPS_128 0
50#define PEU_DEVICE_CNTRL__MPS_256 0x20
51#define PEU_DEVICE_CNTRL__MPS_512 0x40
52
53#include "hboot.s"
54#include "niu_defines.h"
55#include "peu_defines.h"
56.text
57.global main
58main:
59 ta T_CHANGE_HPRIV
60 nop
61 ! enable bypass in IOMMU
62 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
63 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
64 stx %g3, [%g2]
65 ldx [%g2], %g3
66! branch to main by comparing thread id.
67
68 ta T_RD_THID
69 mov 0x1, %g2
70
71 setx 0x0000000000000001, %o0, %g3 ! thread-group bits for the template
72 cmp %g2, %o1
73 be _FcN0_main
74 nop
75
76 setx 0x0000000000000010, %o0, %g3 ! thread-group bits for the template
77 brz %o1, _FcN1_main
78 mov 0x2, %g2
79 cmp %g2, %o1
80 be _FcN2_main
81 nop
82# 116 "diag.j.pp"
83!
84! Thread 0 Start
85!
86!
87_FcN0_main:
88
89P_NIU_RxInitDma:
90 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma)) -> NIU_InitRxDma(a, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, NIU_Xlate_On)
91 setx NIU_PKTGEN_CSR_EV2A_RBR_KICK, %g7, %g2
92delay_loop_Rx:
93 ldx [%g2], %g5
94 cmp %g5, RX_INITIAL_KICK
95 bne delay_loop_Rx
96 nop
97
98 setx 0xa, %g1, %o0
99 setx RX_DESC_RING_LENGTH, %g1, %o1
100 setx RX_COMPL_RING_LEN, %g1, %o2
101 setx RBR_CONFIG_B_DATA, %g1, %o3
102 setx RX_INITIAL_KICK, %g1, %o4
103 call NiuInitRxDma
104 nop
105P_NIU_RxPkt_Conf:
106 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT)
107 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
108 nop
109 setx RXMAC_PKTCNT, %g1, %g6
110 mulx %o0, 0x200, %g5
111 setx RBR_STAT_Addr, %g7, %g2
112 add %g2, %g5, %g2
113P_NIU_Rx_GenPkt:
114 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
115 brz %g5, P_NIU_Rx_GenPkt
116 nop
117 cmp %g5, %o4
118 be P_NIU_Rx_GenPkt
119 nop
120
121Rx_pktcnt_loop:
122 nop ! $EV trig_pc_d(1, @VA(.MAIN.Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, a, RXMAC_PKTCNT, 0x1f4, 0x0, RX_NIU_MULTI_DMA, 1)
123 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
124 nop
125
126 mulx %o0, 0x200, %g5
127 setx RCRSTAT_A_Addr, %g7, %g2
128 add %g2, %g5, %g2
129delay_loop:
130 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
131 cmp %g5, RXMAC_PKTCNT - RXMAC_PKTCNT%8
132 bne delay_loop
133 nop
134
135
136test_passed:
137 nop
138 EXIT_GOOD
139# 188 "diag.j.pp"
140
141_FcN1_main:
142
143Init_flow:
144 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS, 5dc)
145
146P_TxDMAActivate:
147 setx MAC_ID, %g1, %o0
148 setx 0x8000, %g1, %o1
149 call SetTxDMAActive
150 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, 8000)
151 setx XMAC0_MAX_addr, %g7, %g2
152
153
154P_AddTxChannels:
155 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, f)
156 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
157 nop
158
159P_SetTxMaxBurst:
160 setx 0xf, %g1, %o0
161 setx SetTxMaxBurst_Data, %g1, %o1
162 call SetTxMaxBurst
163 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, f, TxMaxBurst_Data)
164 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
165 nop
166
167P_InitTxDma:
168 setx 0xf, %g1, %o0
169 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, f, NIU_Xlate_On)
170 call InitTxDma
171 nop
172 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
173 nop
174
175Gen_Packet:
176 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, f, 0xff,0,0)
177 nop
178
179 setx 0x5, %g1, %g4
180delay_loop_tmp:
181 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
182 nop
183 nop
184 nop
185 nop
186 dec %g4
187 brnz %g4, delay_loop_tmp
188 nop
189
190SetTxRingKick:
191 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, f)
192 setx 0xf, %g1, %o0
193 ldx [%g2], %g3
194 nop
195 mulx %o0, 0x200, %g5
196 setx TX_RING_KICK_Addr, %g1, %g2
197 add %g2, %g5, %g2
198 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
199 nop
200
201SetTxCs:
202 setx 0xf, %g1, %o0
203 setx TX_CS_Data, %g1, %g3
204 mulx %o0, 0x200, %g5
205 setx TX_CS_Addr, %g1, %g2
206 add %g2, %g5, %g2
207 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
208 nop
209
210#ifdef JUMBO_FRAME_EN
211 setx loop_count, %g1, %g4
212delay_loop:
213 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
214 nop
215 nop
216 nop
217 nop
218 dec %g4
219 brnz %g4, delay_loop
220 nop
221#endif
222
223
224NIUTx_Pkt_Cnt_Chk:
225 setx MAC_ID, %g1, %o0
226 setx 0xff, %g1, %o1
227 call NiuTx_check_pkt_cnt
228 nop
229
230 setx loop_count, %g1, %g4
231delay_loop_end:
232 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
233 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
234 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
235 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
236 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
237 dec %g4
238 brnz %g4, delay_loop_end
239 nop
240
241test_passed_tx:
242 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed_tx)) -> NIU_EXIT_chk(MAC_ID)
243 EXIT_GOOD
244
245
246_FcN2_main:
247 setx RX_INITIAL_KICK, %g1, %o4
248 setx 0xa, %g1, %o0
249 mulx %o0, 0x200, %g5
250 setx RBR_STAT_Addr, %g7, %g2
251 add %g2, %g5, %g2
252wt_for_niu:
253 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
254 brz %g5, wt_for_niu
255 nop
256 cmp %g5, %o4
257 be wt_for_niu
258 nop
259!Initializing integer registers
260 setx 0xffffffff0000003f, %r30, %r28
261 ldx [%r31+0], %r0
262 andn %r0, %r28, %r0
263 ldx [%r31+8], %r1
264 andn %r1, %r28, %r1
265 ldx [%r31+16], %r2
266 andn %r2, %r28, %r2
267 ldx [%r31+24], %r3
268 andn %r3, %r28, %r3
269 ldx [%r31+32], %r4
270 andn %r4, %r28, %r4
271 ldx [%r31+40], %r5
272 andn %r5, %r28, %r5
273 ldx [%r31+48], %r6
274 andn %r6, %r28, %r6
275 ldx [%r31+56], %r7
276 andn %r7, %r28, %r7
277 ldx [%r31+64], %r8
278 andn %r8, %r28, %r8
279 ldx [%r31+72], %r9
280 andn %r9, %r28, %r9
281 ldx [%r31+80], %r10
282 andn %r10, %r28, %r10
283 ldx [%r31+88], %r11
284 andn %r11, %r28, %r11
285 ldx [%r31+96], %r12
286 andn %r12, %r28, %r12
287 ldx [%r31+104], %r13
288 andn %r13, %r28, %r13
289 save %r31, %r0, %r31
290 restore
291
292_DMAWr_t_DMA_store_exword_0: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
293
294_DMAWr_t_DMA_store_exword_1: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
295 .word 0xd2404006 ! 2: LDSW_R ldsw [%r1 + %r6], %r9
296
297_DMAWr_t_DMA_write_0: nop
298
299 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_0)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
300
301_DMAWr_t_DMA_store_partial_2: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
302
303_DMAWr_t_DMA_write_1: nop
304
305 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_1)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
306
307_DMAWr_t_DMA_store_partial_3: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
308
309_DMAWr_t_DMA_store_exword_4: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
310 .word 0xd6288005 ! 8: STB_R stb %r11, [%r2 + %r5]
311
312_DMAWr_t_DMA_store_exword_5: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
313 .word 0xd470c004 ! 10: STX_R stx %r10, [%r3 + %r4]
314
315_DMAWr_t_DMA_write_2: nop
316
317 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_2)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
318
319_DMAWr_t_DMA_store_partial_6: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
320
321_DMAWr_t_DMA_store_exword_7: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
322 .word 0xd6200005 ! 14: STW_R stw %r11, [%r0 + %r5]
323
324_DMAWr_t_DMA_write_3: nop
325
326 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_3)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
327
328_DMAWr_t_DMA_store_partial_8: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
329
330_DMAWr_t_DMA_write_4: nop
331
332 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_4)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
333
334_DMAWr_t_DMA_store_partial_9: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
335
336_DMAWr_t_DMA_store_exword_10: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
337 .word 0xd6288005 ! 20: STB_R stb %r11, [%r2 + %r5]
338
339_DMAWr_t_DMA_store_exword_11: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
340 .word 0xd2308006 ! 22: STH_R sth %r9, [%r2 + %r6]
341
342_DMAWr_t_DMA_store_exword_12: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
343 .word 0xd2584007 ! 24: LDX_R ldx [%r1 + %r7], %r9
344
345_DMAWr_t_DMA_store_exword_13: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
346 .word 0xd2308004 ! 26: STH_R sth %r9, [%r2 + %r4]
347
348_DMAWr_t_DMA_write_5: nop
349
350 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_5)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
351
352_DMAWr_t_DMA_store_partial_14: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
353
354_DMAWr_t_DMA_write_6: nop
355
356 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_6)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
357
358_DMAWr_t_DMA_store_partial_15: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
359
360_DMAWr_t_DMA_store_exword_16: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
361 .word 0xd4588006 ! 32: LDX_R ldx [%r2 + %r6], %r10
362
363_DMAWr_t_DMA_store_exword_17: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
364 .word 0xd470c006 ! 34: STX_R stx %r10, [%r3 + %r6]
365
366_DMAWr_t_DMA_store_exword_18: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
367 .word 0xd220c005 ! 36: STW_R stw %r9, [%r3 + %r5]
368
369_DMAWr_t_DMA_store_exword_19: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
370 .word 0xd2208005 ! 38: STW_R stw %r9, [%r2 + %r5]
371
372_DMAWr_t_DMA_store_exword_20: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
373 .word 0xd6400006 ! 40: LDSW_R ldsw [%r0 + %r6], %r11
374
375_DMAWr_t_DMA_store_exword_21: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
376 .word 0xd4584007 ! 42: LDX_R ldx [%r1 + %r7], %r10
377
378_DMAWr_t_DMA_write_7: nop
379
380 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_7)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
381
382_DMAWr_t_DMA_store_partial_22: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
383
384_DMAWr_t_DMA_write_8: nop
385
386 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_8)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
387
388_DMAWr_t_DMA_store_partial_23: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
389
390_DMAWr_t_DMA_write_9: nop
391
392 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_9)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
393
394_DMAWr_t_DMA_store_partial_24: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
395
396_DMAWr_t_DMA_store_exword_25: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
397 .word 0xd2408004 ! 50: LDSW_R ldsw [%r2 + %r4], %r9
398
399_DMAWr_t_DMA_store_exword_26: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
400 .word 0xd6700005 ! 52: STX_R stx %r11, [%r0 + %r5]
401
402_DMAWr_t_DMA_store_exword_27: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
403 .word 0xd6304006 ! 54: STH_R sth %r11, [%r1 + %r6]
404
405_DMAWr_t_DMA_write_10: nop
406
407 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_10)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
408
409_DMAWr_t_DMA_store_partial_28: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
410
411_DMAWr_t_DMA_store_exword_29: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
412 .word 0xd4204007 ! 58: STW_R stw %r10, [%r1 + %r7]
413
414_DMAWr_t_DMA_write_11: nop
415
416 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_11)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
417
418_DMAWr_t_DMA_store_partial_30: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
419
420_DMAWr_t_DMA_write_12: nop
421
422 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_12)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
423
424_DMAWr_t_DMA_store_partial_31: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
425
426_DMAWr_t_DMA_write_13: nop
427
428 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_13)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
429
430_DMAWr_t_DMA_store_partial_32: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
431
432_DMAWr_t_DMA_store_exword_33: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
433 .word 0xd2404007 ! 66: LDSW_R ldsw [%r1 + %r7], %r9
434
435_DMAWr_t_DMA_write_14: nop
436
437 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_14)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
438
439_DMAWr_t_DMA_store_partial_34: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
440
441_DMAWr_t_DMA_write_15: nop
442
443 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_15)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
444
445_DMAWr_t_DMA_store_partial_35: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
446
447_DMAWr_t_DMA_write_16: nop
448
449 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_16)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
450
451_DMAWr_t_DMA_store_partial_36: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
452
453_DMAWr_t_DMA_store_exword_37: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
454 .word 0xd228c007 ! 74: STB_R stb %r9, [%r3 + %r7]
455
456_DMAWr_t_DMA_store_exword_38: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
457 .word 0xd2300004 ! 76: STH_R sth %r9, [%r0 + %r4]
458
459_DMAWr_t_DMA_store_exword_39: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
460 .word 0xd6588005 ! 78: LDX_R ldx [%r2 + %r5], %r11
461
462_DMAWr_t_DMA_store_exword_40: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
463 .word 0xd0208004 ! 80: STW_R stw %r8, [%r2 + %r4]
464
465_DMAWr_t_DMA_store_exword_41: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
466 .word 0xd040c006 ! 82: LDSW_R ldsw [%r3 + %r6], %r8
467
468_DMAWr_t_DMA_write_17: nop
469
470 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_17)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
471
472_DMAWr_t_DMA_store_partial_42: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
473
474_DMAWr_t_DMA_store_exword_43: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
475 .word 0xd458c004 ! 86: LDX_R ldx [%r3 + %r4], %r10
476
477_DMAWr_t_DMA_store_exword_44: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
478 .word 0xd2200007 ! 88: STW_R stw %r9, [%r0 + %r7]
479
480_DMAWr_t_DMA_store_exword_45: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
481 .word 0xd0304004 ! 90: STH_R sth %r8, [%r1 + %r4]
482
483_DMAWr_t_DMA_store_exword_46: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
484 .word 0xd0704007 ! 92: STX_R stx %r8, [%r1 + %r7]
485
486_DMAWr_t_DMA_write_18: nop
487
488 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_18)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
489
490_DMAWr_t_DMA_store_partial_47: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
491
492_DMAWr_t_DMA_store_exword_48: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
493 .word 0xd4408005 ! 96: LDSW_R ldsw [%r2 + %r5], %r10
494
495_DMAWr_t_DMA_store_exword_49: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
496 .word 0xd620c007 ! 98: STW_R stw %r11, [%r3 + %r7]
497
498_DMAWr_t_DMA_write_19: nop
499
500 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_19)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
501
502_DMAWr_t_DMA_store_partial_50: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
503
504_DMAWr_t_DMA_store_exword_51: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
505 .word 0xd2588006 ! 102: LDX_R ldx [%r2 + %r6], %r9
506
507_DMAWr_t_DMA_store_exword_52: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
508 .word 0xd4708004 ! 104: STX_R stx %r10, [%r2 + %r4]
509
510_DMAWr_t_DMA_write_20: nop
511
512 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_20)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
513
514_DMAWr_t_DMA_store_partial_53: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
515
516_DMAWr_t_DMA_store_exword_54: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
517 .word 0xd058c005 ! 108: LDX_R ldx [%r3 + %r5], %r8
518
519_DMAWr_t_DMA_write_21: nop
520
521 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_21)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
522
523_DMAWr_t_DMA_store_partial_55: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
524
525_DMAWr_t_DMA_write_22: nop
526
527 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_22)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
528
529_DMAWr_t_DMA_store_partial_56: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
530
531_DMAWr_t_DMA_write_23: nop
532
533 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_23)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
534
535_DMAWr_t_DMA_store_partial_57: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
536
537_DMAWr_t_DMA_write_24: nop
538
539 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_24)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
540
541_DMAWr_t_DMA_store_partial_58: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
542
543_DMAWr_t_DMA_write_25: nop
544
545 ! $EV trig_pc_d(1, @VA(.MAIN._DMAWr_t_DMA_write_25)) -> EnablePCIeIgCmd("DMAWR", fffc000000000000,fffc000050000000, "64'h1ff", 1)
546
547_DMAWr_t_DMA_store_partial_59: .word 0xfc2a001b !STB_R stb %r30,[%r8+%r27]
548
549_DMAWr_t_DMA_store_exword_60: .word 0xf871c019 ! STX_R stx %r28, [%r7 + %r25]
550 .word 0xd0580004 ! 120: LDX_R ldx [%r0 + %r4], %r8
551 nop
552 nop
553
554 ! select a MEM32 address in PCI address range and transmit the command to NCU
555
556 setx MEM32_RD_ADDR, %g1, %g2
557 setx 0x080, %g1, %g4 ! loop 128 times
558
559delay_loop_pcie:
560 stx %g2, [%g2] ! MEM32 PIO Write
561 ldx [%g2], %l0 ! MEM32 PIO READ
562 add %g2, 8, %g2 ! increment PIO address
563
564 dec %g4 ! decrement counter
565 brnz %g4, delay_loop_pcie ! loop if not zero
566 nop
567
568
569pcie_test_passed:
570 EXIT_GOOD
571
572pcie_test_failed:
573 EXIT_BAD
574
575SECTION descriptor data_va=DMA_DATA_ADDR
576attr_data {
577 Name = descriptor,
578 hypervisor,
579 compressimage
580}
581
582.data
583.global PCIAddr9
584
585 .xword 0x1011121314151617
586 .xword 0x18191a1b1c1d1e1f
587 .xword 0x2021222324252627
588 .xword 0x28292a2b2c2d2e2f
589 .xword 0x3031323334353637
590 .xword 0x38393a3b3c3d3e3f
591 .xword 0x4041424344454647
592 .xword 0x48494a4b4c4d4e4f
593 .xword 0xffffffffffffffff
594 .xword 0xffffffffffffffff
595 .xword 0x1011121314151617
596 .xword 0x18191a1b1c1d1e1f
597 .xword 0x2021222324252627
598 .xword 0x28292a2b2c2d2e2f
599 .xword 0x3031323334353637
600 .xword 0x38393a3b3c3d3e3f
601 .xword 0x4041424344454647
602 .xword 0x48494a4b4c4d4e4f
603 .xword 0xffffffffffffffff
604 .xword 0xffffffffffffffff
605 .xword 0x1011121314151617
606 .xword 0x18191a1b1c1d1e1f
607 .xword 0x2021222324252627
608 .xword 0x28292a2b2c2d2e2f
609 .xword 0x3031323334353637
610 .xword 0x38393a3b3c3d3e3f
611 .xword 0x4041424344454647
612 .xword 0x48494a4b4c4d4e4f
613 .xword 0xffffffffffffffff
614 .xword 0xffffffffffffffff
615 .xword 0x1011121314151617
616 .xword 0x18191a1b1c1d1e1f
617 .xword 0x2021222324252627
618 .xword 0x28292a2b2c2d2e2f
619 .xword 0x3031323334353637
620 .xword 0x38393a3b3c3d3e3f
621 .xword 0x4041424344454647
622 .xword 0x48494a4b4c4d4e4f
623 .xword 0xffffffffffffffff
624 .xword 0xffffffffffffffff
625 .xword 0x1011121314151617
626 .xword 0x18191a1b1c1d1e1f
627 .xword 0x2021222324252627
628 .xword 0x28292a2b2c2d2e2f
629 .xword 0x3031323334353637
630 .xword 0x38393a3b3c3d3e3f
631 .xword 0x4041424344454647
632 .xword 0x48494a4b4c4d4e4f
633 .xword 0xffffffffffffffff
634 .xword 0xffffffffffffffff
635 .xword 0x1011121314151617
636 .xword 0x18191a1b1c1d1e1f
637 .xword 0x2021222324252627
638 .xword 0x28292a2b2c2d2e2f
639 .xword 0x3031323334353637
640 .xword 0x38393a3b3c3d3e3f
641 .xword 0x4041424344454647
642 .xword 0x48494a4b4c4d4e4f
643 .xword 0xffffffffffffffff
644 .xword 0xffffffffffffffff
645 .xword 0x1011121314151617
646 .xword 0x18191a1b1c1d1e1f
647 .xword 0x2021222324252627
648 .xword 0x28292a2b2c2d2e2f
649 .xword 0x3031323334353637
650 .xword 0x38393a3b3c3d3e3f
651 .xword 0x4041424344454647
652 .xword 0x48494a4b4c4d4e4f
653 .xword 0xffffffffffffffff
654 .xword 0xffffffffffffffff
655 .xword 0x1011121314151617
656 .xword 0x18191a1b1c1d1e1f
657 .xword 0x2021222324252627
658 .xword 0x28292a2b2c2d2e2f
659 .xword 0x3031323334353637
660 .xword 0x38393a3b3c3d3e3f
661 .xword 0x4041424344454647
662 .xword 0x48494a4b4c4d4e4f
663 .xword 0xffffffffffffffff
664 .xword 0xffffffffffffffff
665 .xword 0x1011121314151617
666 .xword 0x18191a1b1c1d1e1f
667 .xword 0x2021222324252627
668 .xword 0x28292a2b2c2d2e2f
669 .xword 0x3031323334353637
670 .xword 0x38393a3b3c3d3e3f
671 .xword 0x4041424344454647
672 .xword 0x48494a4b4c4d4e4f
673 .xword 0xffffffffffffffff
674 .xword 0xffffffffffffffff
675
676
677#if 0
678#endif
679
Full OpenSPARC design & verification tarball including full HDL.