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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / cov / FcNiuPeuRdRand_1.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: FcNiuPeuRdRand_1.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define RCRSTAT_A_Addr mpeval(DMC_ADDRESS_RANGE+0x00050)
40#define RBR_STAT_Addr mpeval(DMC_ADDRESS_RANGE+0x00028)
41#define ENABLE_PCIE_LINK_TRAINING
42#define ENABLE_PCIE_MPS_512
43#define MAIN_PAGE_HV_ALSO
44
45#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
46#define DMA_DATA_ADDR 0x0000000050000000
47
48#define PEU_DEVICE_CNTRL_REG_ADDR FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR
49#define PEU_DEVICE_CNTRL__MPS_128 0
50#define PEU_DEVICE_CNTRL__MPS_256 0x20
51#define PEU_DEVICE_CNTRL__MPS_512 0x40
52
53#include "hboot.s"
54#include "niu_defines.h"
55#include "peu_defines.h"
56.text
57.global main
58main:
59 ta T_CHANGE_HPRIV
60 nop
61 ! enable bypass in IOMMU
62 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
63 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
64 stx %g3, [%g2]
65 ldx [%g2], %g3
66
67! branch to main by comparing thread id.
68
69 ta T_RD_THID
70 mov 0x1, %g2
71
72 setx 0x0000000000000001, %o0, %g3 ! thread-group bits for the template
73 cmp %g2, %o1
74 be _FcN1_main
75 nop
76
77 setx 0x0000000000000010, %o0, %g3 ! thread-group bits for the template
78 brz %o1, _FcN0_main
79 mov 0x2, %g2
80 cmp %g2, %o1
81 be _FcN2_main
82 nop
83# 87 "diag.j.pp"
84!
85! Thread 0 Start
86!
87!
88_FcN0_main:
89
90Init_flow:
91 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS, 64)
92
93P_TxDMAActivate:
94 setx MAC_ID, %g1, %o0
95 setx 0x1, %g1, %o1
96 call SetTxDMAActive
97 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, 1)
98 setx XMAC0_MAX_addr, %g7, %g2
99
100
101P_AddTxChannels:
102 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, 0)
103 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
104 nop
105
106P_SetTxMaxBurst:
107 setx 0x0, %g1, %o0
108 setx SetTxMaxBurst_Data, %g1, %o1
109 call SetTxMaxBurst
110 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, 0, TxMaxBurst_Data)
111 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
112 nop
113
114P_InitTxDma:
115 setx 0x0, %g1, %o0
116 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, 0, NIU_Xlate_On)
117 call InitTxDma
118 nop
119 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
120 nop
121
122Gen_Packet:
123 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, 0, 0x31,0,0)
124 nop
125
126 setx 0x5, %g1, %g4
127delay_loop_tmp:
128 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
129 nop
130 nop
131 nop
132 nop
133 dec %g4
134 brnz %g4, delay_loop_tmp
135 nop
136
137SetTxRingKick:
138 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, 0)
139 setx 0x0, %g1, %o0
140 ldx [%g2], %g3
141 nop
142 mulx %o0, 0x200, %g5
143 setx TX_RING_KICK_Addr, %g1, %g2
144 add %g2, %g5, %g2
145 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
146 nop
147
148SetTxCs:
149 setx 0x0, %g1, %o0
150 setx TX_CS_Data, %g1, %g3
151 mulx %o0, 0x200, %g5
152 setx TX_CS_Addr, %g1, %g2
153 add %g2, %g5, %g2
154 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
155 nop
156
157#ifdef JUMBO_FRAME_EN
158 setx loop_count, %g1, %g4
159delay_loop:
160 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
161 nop
162 nop
163 nop
164 nop
165 dec %g4
166 brnz %g4, delay_loop
167 nop
168#endif
169
170
171NIUTx_Pkt_Cnt_Chk:
172 setx MAC_ID, %g1, %o0
173 setx 0x31, %g1, %o1
174 call NiuTx_check_pkt_cnt
175 nop
176
177 setx loop_count, %g1, %g4
178delay_loop_end:
179 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
180 nop
181 nop
182 nop
183 nop
184 dec %g4
185 brnz %g4, delay_loop_end
186 nop
187
188test_passed_tx:
189 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed_tx)) -> NIU_EXIT_chk(MAC_ID)
190 EXIT_GOOD
191
192
193_FcN1_main:
194
195P_NIU_RxInitDma:
196 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma)) -> NIU_InitRxDma(1, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, NIU_Xlate_On)
197 setx NIU_PKTGEN_CSR_EV2A_RBR_KICK, %g7, %g2
198delay_loop_Rx:
199 ldx [%g2], %g5
200 cmp %g5, RX_INITIAL_KICK
201 bne delay_loop_Rx
202 nop
203
204 setx 0x1, %g1, %o0
205 setx RX_DESC_RING_LENGTH, %g1, %o1
206 setx RX_COMPL_RING_LEN, %g1, %o2
207 setx RBR_CONFIG_B_DATA, %g1, %o3
208 setx RX_INITIAL_KICK, %g1, %o4
209 call NiuInitRxDma
210 nop
211P_NIU_RxPkt_Conf:
212 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT)
213 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
214 nop
215 setx RXMAC_PKTCNT, %g1, %g6
216 mulx %o0, 0x200, %g5
217 setx RBR_STAT_Addr, %g7, %g2
218 add %g2, %g5, %g2
219P_NIU_Rx_GenPkt:
220 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
221 brz %g5, P_NIU_Rx_GenPkt
222 nop
223 cmp %g5, %o4
224 be P_NIU_Rx_GenPkt
225 nop
226
227Rx_pktcnt_loop:
228 nop ! $EV trig_pc_d(1, @VA(.MAIN.Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, 1, RXMAC_PKTCNT, 0x64, 0x0, RX_NIU_MULTI_DMA, 1)
229 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
230 nop
231
232 mulx %o0, 0x200, %g5
233 setx RCRSTAT_A_Addr, %g7, %g2
234 add %g2, %g5, %g2
235delay_loop:
236 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
237 cmp %g5, RXMAC_PKTCNT - RXMAC_PKTCNT%8
238 bne delay_loop
239 nop
240
241
242test_passed:
243 nop
244 EXIT_GOOD
245# 276 "diag.j.pp"
246
247_FcN2_main:
248 setx RX_INITIAL_KICK, %g1, %o4
249 setx 0x1, %g1, %o0
250 mulx %o0, 0x200, %g5
251 setx RBR_STAT_Addr, %g7, %g2
252 add %g2, %g5, %g2
253wt_for_niu:
254 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
255 brz %g5, wt_for_niu
256 nop
257 cmp %g5, %o4
258 be wt_for_niu
259 nop
260
261_DMARd_t_DMA_read_0: nop
262
263 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 9be, 1)
264
265_DMARd_t_ldst_0: nop
266! start
267 .word 0xfc0d8018 ! 1: LDUB_R ldub [%r22 + %r24], %r30
268
269_DMARd_t_DMA_read_1: nop
270
271 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 4b, 1)
272
273_DMARd_t_DMA_read_2: nop
274
275 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_2)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, e88, 1)
276
277_DMARd_t_ldst_1: nop
278! start
279 .word 0xf835a110 ! 5: STH_I sth %r28, [%r22 + 0x0110]
280
281_DMARd_t_DMA_read_4: nop
282
283 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 9a9, 1)
284
285_DMARd_t_DMA_read_5: nop
286
287 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_5)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 85a, 1)
288
289_DMARd_t_DMA_read_7: nop
290
291 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_7)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 36, 1)
292
293_DMARd_t_DMA_read_8: nop
294
295 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_8)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 468, 1)
296
297_DMARd_t_DMA_read_10: nop
298
299 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_10)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, d2, 1)
300
301_DMARd_t_DMA_read_11: nop
302
303 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_11)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 2fc, 1)
304
305_DMARd_t_ldst_2: nop
306! start
307 .word 0xfc0d8018 ! 16: LDUB_R ldub [%r22 + %r24], %r30
308
309_DMARd_t_DMA_read_12: nop
310
311 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_12)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, a57, 1)
312
313_DMARd_t_ldst_3: nop
314! start
315 .word 0xfe0dc01b ! 20: LDUB_R ldub [%r23 + %r27], %r31
316
317_DMARd_t_ldst_4: nop
318! start
319 .word 0xf8754018 ! 22: STX_R stx %r28, [%r21 + %r24]
320
321_DMARd_t_DMA_read_14: nop
322
323 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_14)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, b90, 1)
324
325_DMARd_t_DMA_read_15: nop
326
327 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_15)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 518, 1)
328
329_DMARd_t_ldst_5: nop
330! start
331 .word 0xfa75401b ! 26: STX_R stx %r29, [%r21 + %r27]
332
333_DMARd_t_ldst_6: nop
334! start
335 .word 0xf84d6120 ! 28: LDSB_I ldsb [%r21 + 0x0120], %r28
336
337_DMARd_t_DMA_read_16: nop
338
339 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_16)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 42, 1)
340
341_DMARd_t_DMA_read_17: nop
342
343 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_17)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 4b0, 1)
344
345_DMARd_t_ldst_7: nop
346! start
347 .word 0xf80d801a ! 32: LDUB_R ldub [%r22 + %r26], %r28
348
349_DMARd_t_ldst_8: nop
350! start
351 .word 0xfc356120 ! 34: STH_I sth %r30, [%r21 + 0x0120]
352
353_DMARd_t_DMA_read_18: nop
354
355 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_18)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 725, 1)
356
357_DMARd_t_ldst_9: nop
358! start
359 .word 0xfc0dc019 ! 37: LDUB_R ldub [%r23 + %r25], %r30
360
361_DMARd_t_DMA_read_19: nop
362
363 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_19)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 11d, 1)
364
365_DMARd_t_DMA_read_20: nop
366
367 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_20)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 4a7, 1)
368
369_DMARd_t_DMA_read_21: nop
370
371 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_21)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, a8f, 1)
372
373_DMARd_t_ldst_10: nop
374! start
375 .word 0xfc75401b ! 42: STX_R stx %r30, [%r21 + %r27]
376
377_DMARd_t_ldst_11: nop
378! start
379 .word 0xfa4d2100 ! 44: LDSB_I ldsb [%r20 + 0x0100], %r29
380
381_DMARd_t_DMA_read_22: nop
382
383 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_22)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, b3, 1)
384
385_DMARd_t_ldst_12: nop
386! start
387 .word 0xfa0d801b ! 47: LDUB_R ldub [%r22 + %r27], %r29
388
389_DMARd_t_DMA_read_23: nop
390
391 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_23)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, f24, 1)
392
393_DMARd_t_DMA_read_24: nop
394
395 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_24)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, d09, 1)
396
397_DMARd_t_DMA_read_25: nop
398
399 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_25)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 7d4, 1)
400
401_DMARd_t_DMA_read_26: nop
402
403 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_26)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 1c6, 1)
404
405_DMARd_t_DMA_read_27: nop
406
407 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_27)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 5d4, 1)
408
409_DMARd_t_DMA_read_28: nop
410
411 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_28)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 505, 1)
412
413_DMARd_t_ldst_13: nop
414! start
415 .word 0xfa75801b ! 55: STX_R stx %r29, [%r22 + %r27]
416
417_DMARd_t_ldst_14: nop
418! start
419 .word 0xfa4da120 ! 57: LDSB_I ldsb [%r22 + 0x0120], %r29
420
421_DMARd_t_ldst_15: nop
422! start
423 .word 0xf84d6100 ! 59: LDSB_I ldsb [%r21 + 0x0100], %r28
424
425_DMARd_t_DMA_read_29: nop
426
427 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_29)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 9a8, 1)
428
429_DMARd_t_DMA_read_30: nop
430
431 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_30)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 36d, 1)
432
433_DMARd_t_DMA_read_31: nop
434
435 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_31)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 865, 1)
436
437_DMARd_t_ldst_16: nop
438! start
439 .word 0xf875c019 ! 64: STX_R stx %r28, [%r23 + %r25]
440 nop
441 nop
442
443 ! select a MEM32 address in PCI address range and transmit the command to NCU
444
445 setx MEM32_RD_ADDR, %g1, %g2
446 setx 0x080, %g1, %g4 ! loop 128 times
447
448delay_loop_pcie:
449 stx %g2, [%g2] ! MEM32 PIO Write
450 ldx [%g2], %l0 ! MEM32 PIO READ
451 add %g2, 8, %g2 ! increment PIO address
452
453 dec %g4 ! decrement counter
454 brnz %g4, delay_loop_pcie ! loop if not zero
455 nop
456
457
458pcie_test_passed:
459 EXIT_GOOD
460
461pcie_test_failed:
462 EXIT_BAD
463
464SECTION descriptor data_va=DMA_DATA_ADDR
465attr_data {
466 Name = descriptor,
467 hypervisor,
468 compressimage
469}
470
471.data
472.global PCIAddr9
473
474 .xword 0x1011121314151617
475 .xword 0x18191a1b1c1d1e1f
476 .xword 0x2021222324252627
477 .xword 0x28292a2b2c2d2e2f
478 .xword 0x3031323334353637
479 .xword 0x38393a3b3c3d3e3f
480 .xword 0x4041424344454647
481 .xword 0x48494a4b4c4d4e4f
482 .xword 0xffffffffffffffff
483 .xword 0xffffffffffffffff
484 .xword 0x1011121314151617
485 .xword 0x18191a1b1c1d1e1f
486 .xword 0x2021222324252627
487 .xword 0x28292a2b2c2d2e2f
488 .xword 0x3031323334353637
489 .xword 0x38393a3b3c3d3e3f
490 .xword 0x4041424344454647
491 .xword 0x48494a4b4c4d4e4f
492 .xword 0xffffffffffffffff
493 .xword 0xffffffffffffffff
494 .xword 0x1011121314151617
495 .xword 0x18191a1b1c1d1e1f
496 .xword 0x2021222324252627
497 .xword 0x28292a2b2c2d2e2f
498 .xword 0x3031323334353637
499 .xword 0x38393a3b3c3d3e3f
500 .xword 0x4041424344454647
501 .xword 0x48494a4b4c4d4e4f
502 .xword 0xffffffffffffffff
503 .xword 0xffffffffffffffff
504 .xword 0x1011121314151617
505 .xword 0x18191a1b1c1d1e1f
506 .xword 0x2021222324252627
507 .xword 0x28292a2b2c2d2e2f
508 .xword 0x3031323334353637
509 .xword 0x38393a3b3c3d3e3f
510 .xword 0x4041424344454647
511 .xword 0x48494a4b4c4d4e4f
512 .xword 0xffffffffffffffff
513 .xword 0xffffffffffffffff
514 .xword 0x1011121314151617
515 .xword 0x18191a1b1c1d1e1f
516 .xword 0x2021222324252627
517 .xword 0x28292a2b2c2d2e2f
518 .xword 0x3031323334353637
519 .xword 0x38393a3b3c3d3e3f
520 .xword 0x4041424344454647
521 .xword 0x48494a4b4c4d4e4f
522 .xword 0xffffffffffffffff
523 .xword 0xffffffffffffffff
524 .xword 0x1011121314151617
525 .xword 0x18191a1b1c1d1e1f
526 .xword 0x2021222324252627
527 .xword 0x28292a2b2c2d2e2f
528 .xword 0x3031323334353637
529 .xword 0x38393a3b3c3d3e3f
530 .xword 0x4041424344454647
531 .xword 0x48494a4b4c4d4e4f
532 .xword 0xffffffffffffffff
533 .xword 0xffffffffffffffff
534 .xword 0x1011121314151617
535 .xword 0x18191a1b1c1d1e1f
536 .xword 0x2021222324252627
537 .xword 0x28292a2b2c2d2e2f
538 .xword 0x3031323334353637
539 .xword 0x38393a3b3c3d3e3f
540 .xword 0x4041424344454647
541 .xword 0x48494a4b4c4d4e4f
542 .xword 0xffffffffffffffff
543 .xword 0xffffffffffffffff
544 .xword 0x1011121314151617
545 .xword 0x18191a1b1c1d1e1f
546 .xword 0x2021222324252627
547 .xword 0x28292a2b2c2d2e2f
548 .xword 0x3031323334353637
549 .xword 0x38393a3b3c3d3e3f
550 .xword 0x4041424344454647
551 .xword 0x48494a4b4c4d4e4f
552 .xword 0xffffffffffffffff
553 .xword 0xffffffffffffffff
554 .xword 0x1011121314151617
555 .xword 0x18191a1b1c1d1e1f
556 .xword 0x2021222324252627
557 .xword 0x28292a2b2c2d2e2f
558 .xword 0x3031323334353637
559 .xword 0x38393a3b3c3d3e3f
560 .xword 0x4041424344454647
561 .xword 0x48494a4b4c4d4e4f
562 .xword 0xffffffffffffffff
563 .xword 0xffffffffffffffff
564
565
566#if 0
567#endif
568
Full OpenSPARC design & verification tarball including full HDL.