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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / cov / FcNiuPeuRdRand_3.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: FcNiuPeuRdRand_3.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define RCRSTAT_A_Addr mpeval(DMC_ADDRESS_RANGE+0x00050)
40#define RBR_STAT_Addr mpeval(DMC_ADDRESS_RANGE+0x00028)
41#define ENABLE_PCIE_LINK_TRAINING
42#define ENABLE_PCIE_MPS_512
43#define MAIN_PAGE_HV_ALSO
44
45#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
46#define DMA_DATA_ADDR 0x0000000050000000
47
48#define PEU_DEVICE_CNTRL_REG_ADDR FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR
49#define PEU_DEVICE_CNTRL__MPS_128 0
50#define PEU_DEVICE_CNTRL__MPS_256 0x20
51#define PEU_DEVICE_CNTRL__MPS_512 0x40
52
53#include "hboot.s"
54#include "niu_defines.h"
55#include "peu_defines.h"
56.text
57.global main
58main:
59 ta T_CHANGE_HPRIV
60 nop
61 ! enable bypass in IOMMU
62 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
63 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
64 stx %g3, [%g2]
65 ldx [%g2], %g3
66
67! branch to main by comparing thread id.
68
69 ta T_RD_THID
70 mov 0x1, %g2
71
72 setx 0x0000000000000001, %o0, %g3 ! thread-group bits for the template
73 cmp %g2, %o1
74 be _FcN1_main
75 nop
76
77 setx 0x0000000000000010, %o0, %g3 ! thread-group bits for the template
78 brz %o1, _FcN0_main
79 mov 0x2, %g2
80 cmp %g2, %o1
81 be _FcN2_main
82 nop
83# 87 "diag.j.pp"
84!
85! Thread 0 Start
86!
87!
88_FcN0_main:
89
90Init_flow:
91 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS, 40)
92
93P_TxDMAActivate:
94 setx MAC_ID, %g1, %o0
95 setx 0x1, %g1, %o1
96 call SetTxDMAActive
97 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, 1)
98 setx XMAC0_MAX_addr, %g7, %g2
99
100
101P_AddTxChannels:
102 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, 0)
103 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
104 nop
105
106P_SetTxMaxBurst:
107 setx 0x0, %g1, %o0
108 setx SetTxMaxBurst_Data, %g1, %o1
109 call SetTxMaxBurst
110 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, 0, TxMaxBurst_Data)
111 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
112 nop
113
114P_InitTxDma:
115 setx 0x0, %g1, %o0
116 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, 0, NIU_Xlate_On)
117 call InitTxDma
118 nop
119 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
120 nop
121
122Gen_Packet:
123 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, 0, 0x76,0,0)
124 nop
125
126 setx 0x5, %g1, %g4
127delay_loop_tmp:
128 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
129 nop
130 nop
131 nop
132 nop
133 dec %g4
134 brnz %g4, delay_loop_tmp
135 nop
136
137SetTxRingKick:
138 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, 0)
139 setx 0x0, %g1, %o0
140 ldx [%g2], %g3
141 nop
142 mulx %o0, 0x200, %g5
143 setx TX_RING_KICK_Addr, %g1, %g2
144 add %g2, %g5, %g2
145 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
146 nop
147
148SetTxCs:
149 setx 0x0, %g1, %o0
150 setx TX_CS_Data, %g1, %g3
151 mulx %o0, 0x200, %g5
152 setx TX_CS_Addr, %g1, %g2
153 add %g2, %g5, %g2
154 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
155 nop
156
157#ifdef JUMBO_FRAME_EN
158 setx loop_count, %g1, %g4
159delay_loop:
160 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
161 nop
162 nop
163 nop
164 nop
165 dec %g4
166 brnz %g4, delay_loop
167 nop
168#endif
169
170
171NIUTx_Pkt_Cnt_Chk:
172 setx MAC_ID, %g1, %o0
173 setx 0x76, %g1, %o1
174 call NiuTx_check_pkt_cnt
175 nop
176
177 setx loop_count, %g1, %g4
178delay_loop_end:
179 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
180 nop
181 nop
182 nop
183 nop
184 dec %g4
185 brnz %g4, delay_loop_end
186 nop
187
188test_passed_tx:
189 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed_tx)) -> NIU_EXIT_chk(MAC_ID)
190 EXIT_GOOD
191
192
193_FcN1_main:
194
195P_NIU_RxInitDma:
196 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma)) -> NIU_InitRxDma(a, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, NIU_Xlate_On)
197 setx NIU_PKTGEN_CSR_EV2A_RBR_KICK, %g7, %g2
198delay_loop_Rx:
199 ldx [%g2], %g5
200 cmp %g5, RX_INITIAL_KICK
201 bne delay_loop_Rx
202 nop
203
204 setx 0xa, %g1, %o0
205 setx RX_DESC_RING_LENGTH, %g1, %o1
206 setx RX_COMPL_RING_LEN, %g1, %o2
207 setx RBR_CONFIG_B_DATA, %g1, %o3
208 setx RX_INITIAL_KICK, %g1, %o4
209 call NiuInitRxDma
210 nop
211P_NIU_RxPkt_Conf:
212 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT)
213 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
214 nop
215 setx RXMAC_PKTCNT, %g1, %g6
216 mulx %o0, 0x200, %g5
217 setx RBR_STAT_Addr, %g7, %g2
218 add %g2, %g5, %g2
219P_NIU_Rx_GenPkt:
220 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
221 brz %g5, P_NIU_Rx_GenPkt
222 nop
223 cmp %g5, %o4
224 be P_NIU_Rx_GenPkt
225 nop
226
227Rx_pktcnt_loop:
228 nop ! $EV trig_pc_d(1, @VA(.MAIN.Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, a, RXMAC_PKTCNT, 0x64, 0x0, RX_NIU_MULTI_DMA, 1)
229 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
230 nop
231
232 mulx %o0, 0x200, %g5
233 setx RCRSTAT_A_Addr, %g7, %g2
234 add %g2, %g5, %g2
235delay_loop:
236 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
237 cmp %g5, RXMAC_PKTCNT - RXMAC_PKTCNT%8
238 bne delay_loop
239 nop
240
241
242test_passed:
243 nop
244 EXIT_GOOD
245# 276 "diag.j.pp"
246
247_FcN2_main:
248 setx RX_INITIAL_KICK, %g1, %o4
249 setx 0xa, %g1, %o0
250 mulx %o0, 0x200, %g5
251 setx RBR_STAT_Addr, %g7, %g2
252 add %g2, %g5, %g2
253wt_for_niu:
254 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
255 brz %g5, wt_for_niu
256 nop
257 cmp %g5, %o4
258 be wt_for_niu
259 nop
260
261_DMARd_t_ldst_0: nop
262! start
263
264_DMARd_t_DMA_read_0: nop
265
266 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_0)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 4bd, 1)
267
268_DMARd_t_DMA_read_1: nop
269
270 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_1)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 376, 1)
271
272_DMARd_t_DMA_read_3: nop
273
274 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_3)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, e17, 1)
275
276_DMARd_t_DMA_read_4: nop
277
278 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_4)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 5ce, 1)
279
280_DMARd_t_ldst_1: nop
281! start
282 .word 0xfa0dc019 ! 8: LDUB_R ldub [%r23 + %r25], %r29
283
284_DMARd_t_ldst_2: nop
285! start
286 .word 0xfa35e110 ! 10: STH_I sth %r29, [%r23 + 0x0110]
287
288_DMARd_t_DMA_read_6: nop
289
290 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_6)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 8f0, 1)
291
292_DMARd_t_ldst_3: nop
293! start
294 .word 0xfc35e100 ! 14: STH_I sth %r30, [%r23 + 0x0100]
295
296_DMARd_t_DMA_read_10: nop
297
298 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_10)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, b9d, 1)
299
300_DMARd_t_DMA_read_11: nop
301
302 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_11)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 6b1, 1)
303
304_DMARd_t_ldst_5: nop
305! start
306 .word 0xfc35e120 ! 22: STH_I sth %r30, [%r23 + 0x0120]
307
308_DMARd_t_DMA_read_12: nop
309
310 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_12)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, bdb, 1)
311
312_DMARd_t_ldst_6: nop
313! start
314 .word 0xfa4da110 ! 25: LDSB_I ldsb [%r22 + 0x0110], %r29
315
316_DMARd_t_DMA_read_14: nop
317
318 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_14)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, e67, 1)
319
320_DMARd_t_DMA_read_15: nop
321
322 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_15)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, eee, 1)
323
324_DMARd_t_DMA_read_16: nop
325
326 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_16)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, ca0, 1)
327
328_DMARd_t_DMA_read_17: nop
329
330 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_17)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, f33, 1)
331
332_DMARd_t_DMA_read_18: nop
333
334 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_18)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 590, 1)
335
336_DMARd_t_DMA_read_19: nop
337
338 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_19)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, e49, 1)
339
340_DMARd_t_DMA_read_20: nop
341
342 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_20)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, fcf, 1)
343
344_DMARd_t_ldst_7: nop
345! start
346 .word 0xf80d4019 ! 35: LDUB_R ldub [%r21 + %r25], %r28
347
348_DMARd_t_ldst_8: nop
349! start
350 .word 0xfc75c01a ! 37: STX_R stx %r30, [%r23 + %r26]
351
352_DMARd_t_DMA_read_21: nop
353
354 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_21)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 86f, 1)
355
356_DMARd_t_DMA_read_22: nop
357
358 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_22)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 4ee, 1)
359
360_DMARd_t_DMA_read_23: nop
361
362 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_23)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, bdc, 1)
363
364_DMARd_t_ldst_9: nop
365! start
366 .word 0xfa0dc019 ! 42: LDUB_R ldub [%r23 + %r25], %r29
367
368_DMARd_t_DMA_read_24: nop
369
370 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_24)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, db5, 1)
371
372_DMARd_t_ldst_10: nop
373! start
374 .word 0xf835a100 ! 45: STH_I sth %r28, [%r22 + 0x0100]
375
376_DMARd_t_ldst_11: nop
377! start
378 .word 0xfe4d6130 ! 47: LDSB_I ldsb [%r21 + 0x0130], %r31
379
380_DMARd_t_DMA_read_25: nop
381
382 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_25)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 876, 1)
383
384_DMARd_t_DMA_read_26: nop
385
386 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_26)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 9ba, 1)
387
388_DMARd_t_DMA_read_27: nop
389
390 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_27)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 91e, 1)
391
392_DMARd_t_DMA_read_28: nop
393
394 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_28)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, cf4, 1)
395
396_DMARd_t_DMA_read_29: nop
397
398 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_29)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 356, 1)
399
400_DMARd_t_DMA_read_30: nop
401
402 ! $EV trig_pc_d(1, @VA(.MAIN._DMARd_t_DMA_read_30)) -> EnablePCIeIgCmd("DMARD", fffc000056789000,fffc000056789000, 776, 1)
403
404_DMARd_t_ldst_12: nop
405! start
406 .word 0xfe0d8018 ! 55: LDUB_R ldub [%r22 + %r24], %r31
407 nop
408 nop
409
410 ! select a MEM32 address in PCI address range and transmit the command to NCU
411
412 setx MEM32_RD_ADDR, %g1, %g2
413 setx 0x080, %g1, %g4 ! loop 128 times
414
415delay_loop_pcie:
416 stx %g2, [%g2] ! MEM32 PIO Write
417 ldx [%g2], %l0 ! MEM32 PIO READ
418 add %g2, 8, %g2 ! increment PIO address
419
420 dec %g4 ! decrement counter
421 brnz %g4, delay_loop_pcie ! loop if not zero
422 nop
423
424
425pcie_test_passed:
426 EXIT_GOOD
427
428pcie_test_failed:
429 EXIT_BAD
430
431SECTION descriptor data_va=DMA_DATA_ADDR
432attr_data {
433 Name = descriptor,
434 hypervisor,
435 compressimage
436}
437
438.data
439.global PCIAddr9
440
441 .xword 0x1011121314151617
442 .xword 0x18191a1b1c1d1e1f
443 .xword 0x2021222324252627
444 .xword 0x28292a2b2c2d2e2f
445 .xword 0x3031323334353637
446 .xword 0x38393a3b3c3d3e3f
447 .xword 0x4041424344454647
448 .xword 0x48494a4b4c4d4e4f
449 .xword 0xffffffffffffffff
450 .xword 0xffffffffffffffff
451 .xword 0x1011121314151617
452 .xword 0x18191a1b1c1d1e1f
453 .xword 0x2021222324252627
454 .xword 0x28292a2b2c2d2e2f
455 .xword 0x3031323334353637
456 .xword 0x38393a3b3c3d3e3f
457 .xword 0x4041424344454647
458 .xword 0x48494a4b4c4d4e4f
459 .xword 0xffffffffffffffff
460 .xword 0xffffffffffffffff
461 .xword 0x1011121314151617
462 .xword 0x18191a1b1c1d1e1f
463 .xword 0x2021222324252627
464 .xword 0x28292a2b2c2d2e2f
465 .xword 0x3031323334353637
466 .xword 0x38393a3b3c3d3e3f
467 .xword 0x4041424344454647
468 .xword 0x48494a4b4c4d4e4f
469 .xword 0xffffffffffffffff
470 .xword 0xffffffffffffffff
471 .xword 0x1011121314151617
472 .xword 0x18191a1b1c1d1e1f
473 .xword 0x2021222324252627
474 .xword 0x28292a2b2c2d2e2f
475 .xword 0x3031323334353637
476 .xword 0x38393a3b3c3d3e3f
477 .xword 0x4041424344454647
478 .xword 0x48494a4b4c4d4e4f
479 .xword 0xffffffffffffffff
480 .xword 0xffffffffffffffff
481 .xword 0x1011121314151617
482 .xword 0x18191a1b1c1d1e1f
483 .xword 0x2021222324252627
484 .xword 0x28292a2b2c2d2e2f
485 .xword 0x3031323334353637
486 .xword 0x38393a3b3c3d3e3f
487 .xword 0x4041424344454647
488 .xword 0x48494a4b4c4d4e4f
489 .xword 0xffffffffffffffff
490 .xword 0xffffffffffffffff
491 .xword 0x1011121314151617
492 .xword 0x18191a1b1c1d1e1f
493 .xword 0x2021222324252627
494 .xword 0x28292a2b2c2d2e2f
495 .xword 0x3031323334353637
496 .xword 0x38393a3b3c3d3e3f
497 .xword 0x4041424344454647
498 .xword 0x48494a4b4c4d4e4f
499 .xword 0xffffffffffffffff
500 .xword 0xffffffffffffffff
501 .xword 0x1011121314151617
502 .xword 0x18191a1b1c1d1e1f
503 .xword 0x2021222324252627
504 .xword 0x28292a2b2c2d2e2f
505 .xword 0x3031323334353637
506 .xword 0x38393a3b3c3d3e3f
507 .xword 0x4041424344454647
508 .xword 0x48494a4b4c4d4e4f
509 .xword 0xffffffffffffffff
510 .xword 0xffffffffffffffff
511 .xword 0x1011121314151617
512 .xword 0x18191a1b1c1d1e1f
513 .xword 0x2021222324252627
514 .xword 0x28292a2b2c2d2e2f
515 .xword 0x3031323334353637
516 .xword 0x38393a3b3c3d3e3f
517 .xword 0x4041424344454647
518 .xword 0x48494a4b4c4d4e4f
519 .xword 0xffffffffffffffff
520 .xword 0xffffffffffffffff
521 .xword 0x1011121314151617
522 .xword 0x18191a1b1c1d1e1f
523 .xword 0x2021222324252627
524 .xword 0x28292a2b2c2d2e2f
525 .xword 0x3031323334353637
526 .xword 0x38393a3b3c3d3e3f
527 .xword 0x4041424344454647
528 .xword 0x48494a4b4c4d4e4f
529 .xword 0xffffffffffffffff
530 .xword 0xffffffffffffffff
531
532
533#if 0
534#endif
535
Full OpenSPARC design & verification tarball including full HDL.