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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / fc.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<sys(fc_all)>
36<sys(all)>
37<sys(daily)>
38
39<sys(cmp) name=sys(cmp)>
40
41
42////////////////////////////////////////////////////////////////////////////
43// CMT diags, 1 core
44
45<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 -midas_args=-DTHREAD_COUNT=2>
46
47cmp_park_self cmp_park_self.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
48
49</runargs>
50</sys(cmp)>
51
52
53<sys(interrupt) name=sys(interrupt)>
54
55////////////////////////////////////////////////////////////////////////////
56// Single-threaded interrupt diags
57<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
58
59interrupt_INT_VEC_DIS interrupt_INT_VEC_DIS.s
60interrupt_INT_VEC_DIS_all2 interrupt_INT_VEC_DIS_all2.s
61interrupt_SWVR_INTR_R interrupt_SWVR_INTR_R.s
62interrupt_SWVR_INTR_W interrupt_SWVR_INTR_W.s
63interrupt_SWVR_INTR_W_all_vectors interrupt_SWVR_INTR_W_all_vectors.s
64interrupt_INTR_REC_priority interrupt_INTR_REC_priority.s
65interrupt_QUEUE_CPU_MONDO_trap interrupt_QUEUE_CPU_MONDO_trap.s
66interrupt_QUEUE_DEV_MONDO_trap interrupt_QUEUE_DEV_MONDO_trap.s
67interrupt_SPU_interrupt interrupt_SPU_interrupt.s
68interrupt_ncu_regs_rw interrupt_ncu_regs_rw.s
69interrupt_QUEUE_CPU_MONDO_mode interrupt_QUEUE_CPU_MONDO_mode.s
70interrupt_QUEUE_DEV_MONDO_mode interrupt_QUEUE_DEV_MONDO_mode.s
71interrupt_DMU_CORE_BLK_enable1 interrupt_DMU_CORE_BLK_enable1.s
72interrupt_pci_regs interrupt_pci_regs.s
73interrupt_pci_pwr_msg interrupt_pci_pwr_msg.s -vcs_run_args=+PEU_TEST
74
75</runargs>
76
77////////////////////////////////////////////////////////////////////////////
78// 2-threaded interrupt diags
79<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 -midas_args=-DSYNC_THREADS >
80
81interrupt_SWVR_INTR_REC_mode interrupt_SWVR_INTR_REC_mode.s
82interrupt_SWVR_INTR_R_mode interrupt_SWVR_INTR_R_mode.s
83interrupt_SWVR_INTR_W_mode interrupt_SWVR_INTR_W_mode.s
84
85</runargs>
86
87
88////////////////////////////////////////////////////////////////////////////
89// Miscellaneous interrupt diags
90interrupt_dmu_cntrl_stall interrupt_dmu_cntrl_stall.s -midas_args=-DCMP_THREAD_START=0xf -finish_mask=f -vcs_run_args=+PEU_TEST
91interrupt_pci_spurious_INTX interrupt_pci_spurious_INTX.s -vcs_run_args=+PEU_TEST -nosas
92
93interrupt_pci_spurious_err interrupt_pci_spurious_err.s -nosas
94
95interrupt_niu_regs_rw interrupt_niu_regs_rw.s
96interrupt_INT_MAN_vector interrupt_INT_MAN_vector.s
97interrupt_niu_device_id interrupt_niu_device_id.s -nosas
98
99
100////////////////////////////////////////////////////////////////////////////
101// 8-threaded interrupt diags
102
103<runargs -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff >
104
105interrupt_INT_MAN_thread interrupt_INT_MAN_thread.s
106
107<runargs -vcs_run_args=+PEU_TEST -nosas>
108interrupt_dmu_intr_reloc interrupt_dmu_intr_reloc.s -midas_args=-DTHREAD_COUNT=8 -midas_args=-DSKIP_EQ_CHECK
109interrupt_mix interrupt_mix.s
110interrupt_pci_dup_intx interrupt_pci_dup_intx.s
111interrupt_pci_multiple_INTX interrupt_pci_multiple_INTX.s
112</runargs>
113
114</runargs>
115
116
117////////////////////////////////////////////////////////////////////////////
118// NIU interrupt diags
119
120<runargs -vcs_run_args=+MAC_SPEED0=10000 -midas_args=-DMAC_SPEED0=10000 >
121<runargs -vcs_run_args=+MAC_SPEED1=10000 -midas_args=-DMAC_SPEED1=10000 >
122<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
123<runargs -vcs_run_args=+PCS_SERDES -midas_args=-DPCS_SERDES >
124<runargs -vcs_run_args=+displaySysRdWr >
125<runargs -vcs_run_args=+ORIG_META >
126
127<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
128
129<runargs -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST >
130
131<runargs -vcs_run_args=+TX_INT_MARK=1 >
132<runargs -midas_args=-DNIU_TX_DMA_NUM=0 -midas_args=-DNIU_TX_PKT_CNT=1 >
133<runargs -midas_args=-DNIU_TX_DMA_ACT_LIST=1 >
134
135<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 >
136
137interrupt_ether_send interrupt_ether_send.s
138interrupt_niu_sys_data interrupt_niu_sys_data.s
139
140</runargs> // thread=0x1
141</runargs> // NIU_TX_DMA_ACT_LIST
142</runargs> // NIU_TX_DMA_NUM
143</runargs> // TX_INT_MARK
144
145interrupt_niutx interrupt_niutx.s -vcs_run_args=+NIU_TX_MARK_LAST_PACKET_FOR_INTERRUPT -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3
146
147</runargs> // TX_TEST
148
149
150<runargs -midas_args=-DRX_TEST -midas_args=-DMAC_ID=0 >
151<runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=20 -midas_args=-DSKIP_TRAPCHECK >
152
153interrupt_niurx interrupt_niurx.s -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3
154
155</runargs> // RX_TEST
156</runargs> // RXMAC_PKTCNT
157
158</runargs> // PEU_TEST
159
160
161<runargs -midas_args=-DMAC_RX_FRAME_INTR >
162
163//interrupt_MAC interrupt_MAC.s
164
165</runargs> // MAC_RX_FRAME_INTR
166
167</runargs> // ORIG_META
168</runargs> // displaySysRdWr
169</runargs> // PCS_SERDES
170</runargs> // GET_MAC_PORTS
171</runargs> // MAC_SPEED1
172</runargs> // MAC_SPEED0
173
174interrupt_ether_receive interrupt_ether_receive.s -sas
175
176</sys(interrupt)>
177
178////////////////////////////////////////////////////////////////////////////
179////////////////////////////////////////////////////////////////////////////
180 <sys(peu_daily) name=sys(peu_daily)>
181
182 <runargs -sas >
183// NcuRegRw NcuRegRw.s
184 RegRdReset RegRdReset.s
185 Bug103049 Bug103049.s
186 PCIeWrPeuDiagCsr PCIeWrPeuDiagCsr.s
187
188 <runargs -vcs_run_args=+PEU_TEST>
189 PCIeCFGRd PCIeCFGRd.s
190 PCIeCFGWr PCIeCFGWr.s
191 PCIeCFG0Rw PCIeCFG0Rw.s
192 PCIeIORw PCIeIORw.s
193 PCIeIORw_pll PCIeIORw.s -vcs_run_args=+pll_bypass -vcs_run_args=+NO_CCU_CSR_SLAM -vcs_run_args=+POR_pulse_width=4
194 PCIeMemRd PCIeMemRd.s
195 PCIeMemWr PCIeMemWr.s
196
197 PCIeMem32Rd PCIeMem32Rd.s
198 PCIeMem64Rd PCIeMem64Rd.s
199 PCIeMem64Rd32 PCIeMem64Rd32.s -nosas
200 PCIeMem64RdWr PCIeMem64RdWr.s
201 PCIeMem32AllBMsk PCIeMem32AllBMsk.s
202 PCIeMem64AllBMsk PCIeMem64AllBMsk.s
203 PCIeMem32AllBMsk2 PCIeMem32AllBMsk2.s
204 PCIeMem64AllBMsk2 PCIeMem64AllBMsk2.s
205 PCIeIOAllBMsk PCIeIOAllBMsk.s
206 PCIeCFG1AllBMsk PCIeCFG1AllBMsk.s
207 PCIeBadPIOAccess PCIeBadPIOAccess.s -vcs_run_args=+ios_0in_ras_chk_off
208
209 PCIeDMARw PCIeDMARw.s
210 PCIeIntx PCIeIntx.s
211 PCIeMsi PCIeMsi.s
212 PCIeRFE6298418 PCIeRFE6298418.s
213
214 PCIeDMAWrAdr32 PCIeDMAWrAdr32.s
215 PCIeDMAWrAdr64 PCIeDMAWrAdr64.s
216 PCIeDMARdAdr32 PCIeDMARdAdr32.s
217 PCIeDMARdAdr64 PCIeDMARdAdr64.s
218
219 PCIeDMARdPerf PCIeDMARdPerf.s
220 PCIeDMAWrPerf PCIeDMAWrPerf.s
221
222 PCIeDMARdAllCacheLineOffsets PCIeDMARdAllCacheLineOffsets.s -vcs_run_args=+bank_set_mask=f
223 PCIeDMAWrAllCacheLineOffsets PCIeDMAWrAllCacheLineOffsets.s -vcs_run_args=+bank_set_mask=f
224
225 PCIeIommu4U64kTr PCIeIommu4U64kTr.s
226 PCIeIommu4U8kTr PCIeIommu4U8kTr.s
227 PCIeIommu4V64kTr PCIeIommu4V64kTr.s
228 PCIeIommu4V8kTr PCIeIommu4V8kTr.s
229 PCIeIommu4V4mTr PCIeIommu4V4mTr.s
230 PCIeIommu4V256mTr PCIeIommu4V256mTr.s -vcs_run_args=+4_FBDIMMS
231
232 PCIeIommu4UBypTrInv PCIeIommu4UBypTrInv.s
233 PCIeIommu4VBypTrInv PCIeIommu4VBypTrInv.s
234
235 PCIeIommu4VBadTr2 PCIeIommu4VBadTr2.s
236
237 PCIeDrainState PCIeDrainState.s -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+no_verilog_finish -vcs_run_args=+no_dmu2peu_ibc_req_ack
238 PCIePIOTimOut PCIePIOTimeout.s -vcs_run_args=+ios_0in_ras_chk_off
239 PCIePIOUc PCIePIOUc.s -vcs_run_args=+ios_0in_ras_chk_off
240
241 <runargs -vcs_run_args=+ios_0in_ras_chk_off -midas_args=-DPCIE_USE_SSYS_RESET >
242 PCIeEgrHPeDrainState PCIeEgrHPeDrainState.s
243 PCIeEgrDPeDrainState PCIeEgrDPeDrainState.s -vcs_run_args=+no_dmu2peu_edb_parity
244 PCIeIgrHPeDrainState PCIeIgrHPeDrainState.s
245 </runargs>
246
247 PCIeDMAWrNonContigDWBE PCIeDMAWrNonContigDWBE.s
248 PCIeDMA0LenRd PCIeDMA0LenRd.s
249
250 PCIeDMARdMPS128Rcb PCIeDMARdMPS128Rcb.s
251 PCIeDMARdMPS256Rcb PCIeDMARdMPS256Rcb.s
252 PCIeDMARdMPS512Rcb PCIeDMARdMPS512Rcb.s
253
254 // multi thread peu diags
255 <runargs -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff >
256 PCIeFireDeadlockScn1 PCIeFireDeadlockScn1.s
257 PCIeFireDeadlockScn2pm1 PCIeFireDeadlockScn2.s -midas_args=-DPEU_PIO_MODE=1 -vcs_run_args=+th_timeout=250000
258 PCIeFireDeadlockScn2pm2 PCIeFireDeadlockScn2.s -midas_args=-DPEU_PIO_MODE=2 -vcs_run_args=+th_timeout=250000
259 Bug107906 Bug107906.s -rtl_timeout=100000
260 </runargs>
261
262 PCIeMem64AdrCov PCIeMem64AdrCov.s -nosas
263 PCIeDMARdLk PCIeDMARdLk.s
264 PCIeReqId PCIeReqId.s
265 PCIeInterrupt PCIeInterrupt.s
266 </runargs>
267 </runargs>
268 </sys(peu_daily)>
269
270<sys(pll) name=sys(pll)>
271<runargs -sas>
272
273<runargs -vcs_run_args=+bank_set_mask=3 -vcs_run_args=+core_set_mask=01>
274memop_all_atomics_pll memop_all_atomics.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff -vcs_run_args=+pll_bypass -vcs_run_args=+NO_CCU_CSR_SLAM -vcs_run_args=+POR_pulse_width=4 -vcs_run_args=+gchkr_off
275</runargs>
276
277<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
278<runargs -vcs_run_args=+MAC_SPEED1=10000 >
279<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
280<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
281<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST >
282<runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
283<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
284
285<runargs -midas_args=-DNIU_TX_DMA_NUM=1 -midas_args=-DNIU_TX_DMA_ACT_LIST=2 >
286FcNiuTx_DMA1_pll FcNiuBasicTx.s -vcs_run_args=+pll_bypass -vcs_run_args=+NO_CCU_CSR_SLAM -vcs_run_args=+POR_pulse_width=4
287</runargs>
288
289</runargs>
290</runargs>
291</runargs>
292</runargs>
293</runargs>
294</runargs>
295</runargs>
296
297</runargs>
298</sys(pll)>
299
300#include "fc_dbp.diaglist"
301
302</sys(daily)>
303</sys(all)>
304</sys(fc_all)>
305
Full OpenSPARC design & verification tarball including full HDL.