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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / fc_adv_err.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_adv_err.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<sys(fc_all)>
36<sys(all)>
37<sys(daily)>
38
39
40
41// Applied for ALL Error diags
42// esr mon off
43
44<runargs -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+500000 -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable >
45
46<sys(ios-mss_adv_ras) name=sys(ios-mss_adv_ras)>
47
48<runargs -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+ios_0in_ras_chk_off -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 -vcs_run_args=+MAC_SPEED1=10000 -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+nb_crc_mon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+lsu_mon_off -vcs_run_args=+dmusiu_bid_chk_off -vcs_run_args=+siu_order_chk_off -vcs_run_args=+sio_dmu_ras_chk_off -vcs_run_args=+sio_niu_ras_chk_off>
49
50L2_Drc_Mcu_Io_err Drc_Mcu_Io_err.s
51L2_Ldac_Mcu_Io_err Ldac_Mcu_Io_err.s -nosas -vcs_run_args=+siu_mon_l2err
52L2_Ldrc_Mcu_Io_err Ldrc_Mcu_Io_err.s -nosas -vcs_run_args=+siu_mon_l2err
53L2_Lvc_Mcu_Io_err Lvc_Mcu_Io_err.s -nosas
54
55
56</runargs>
57
58</sys(ios-mss_adv_ras)>
59
60
61<sys(ios_adv_dmu_ras) name=sys(ios_adv_dmu_ras)>
62
63<runargs -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+PEU_TEST >
64
65n2_err_adv_DmuWrm_DP n2_err_adv_DmuWrm_DP.s -nosas
66n2_err_adv_DmuWri_DP n2_err_adv_DmuWri_DP.s
67
68n2_err_adv_Dmu_AP_Bank0 n2_err_adv_Dmu_AP.s -midas_args=-DBANK0
69n2_err_adv_Dmu_AP_Bank1 n2_err_adv_Dmu_AP.s -midas_args=-DBANK1
70n2_err_adv_Dmu_AP_Bank2 n2_err_adv_Dmu_AP.s -midas_args=-DBANK2
71n2_err_adv_Dmu_AP_Bank3 n2_err_adv_Dmu_AP.s -midas_args=-DBANK3
72n2_err_adv_Dmu_AP_Bank4 n2_err_adv_Dmu_AP.s -midas_args=-DBANK4
73n2_err_adv_Dmu_AP_Bank5 n2_err_adv_Dmu_AP.s -midas_args=-DBANK5
74n2_err_adv_Dmu_AP_Bank6 n2_err_adv_Dmu_AP.s -midas_args=-DBANK6
75n2_err_adv_Dmu_AP_Bank7 n2_err_adv_Dmu_AP.s -midas_args=-DBANK7
76
77n2_err_adv_dmu_CtagUe n2_err_adv_dmu_CtagUe.s -vcs_run_args=+dmusiu_bid_chk_off
78
79n2_err_adv_mcuUe_piuRd_L2_0 n2_err_adv_mcuUe_piuRd.s -midas_args=-DL2_0
80n2_err_adv_mcuUe_piuRd_L2_1 n2_err_adv_mcuUe_piuRd.s -midas_args=-DL2_1
81n2_err_adv_mcuUe_piuRd_L2_2 n2_err_adv_mcuUe_piuRd.s -midas_args=-DL2_2
82n2_err_adv_mcuUe_piuRd_L2_3 n2_err_adv_mcuUe_piuRd.s -midas_args=-DL2_3
83n2_err_adv_mcuUe_piuRd_L2_4 n2_err_adv_mcuUe_piuRd.s -midas_args=-DL2_4
84n2_err_adv_mcuUe_piuRd_L2_5 n2_err_adv_mcuUe_piuRd.s -midas_args=-DL2_5
85n2_err_adv_mcuUe_piuRd_L2_6 n2_err_adv_mcuUe_piuRd.s -midas_args=-DL2_6
86n2_err_adv_mcuUe_piuRd_L2_7 n2_err_adv_mcuUe_piuRd.s -midas_args=-DL2_7
87
88n2_err_adv_L2Ue_piuRd n2_err_adv_L2Ue_piuRd.s -nosas
89n2_err_adv_Dmu_AP_synd n2_err_adv_Dmu_AP_synd.s -vcs_run_args=+dmusiu_bid_chk_off
90n2_err_adv_DmuWrRd_mult_err n2_err_adv_DmuWrRd_mult_err.s -vcs_run_args=+dmusiu_bid_chk_off -vcs_run_args=+siu_order_chk_off -vcs_run_args=+sio_dmu_ras_chk_off -vcs_run_args=+sio_niu_ras_chk_off
91n2_err_adv_DmuRd_mult_ce n2_err_adv_DmuRd_mult_ce.s -vcs_run_args=+sio_dmu_ras_chk_off
92
93n2_err_adv_mcuUe_SiiDmuctagUe_L2_0 n2_err_adv_mcuUe_SiiDmuctagUe.s -midas_args=-DL2_0 -vcs_run_args=+dmusiu_bid_chk_off
94n2_err_adv_mcuUe_SiiDmuctagUe_L2_1 n2_err_adv_mcuUe_SiiDmuctagUe.s -midas_args=-DL2_1 -vcs_run_args=+dmusiu_bid_chk_off
95n2_err_adv_mcuUe_SiiDmuctagUe_L2_2 n2_err_adv_mcuUe_SiiDmuctagUe.s -midas_args=-DL2_2 -vcs_run_args=+dmusiu_bid_chk_off
96n2_err_adv_mcuUe_SiiDmuctagUe_L2_3 n2_err_adv_mcuUe_SiiDmuctagUe.s -midas_args=-DL2_3 -vcs_run_args=+dmusiu_bid_chk_off
97n2_err_adv_mcuUe_SiiDmuctagUe_L2_4 n2_err_adv_mcuUe_SiiDmuctagUe.s -midas_args=-DL2_4 -vcs_run_args=+dmusiu_bid_chk_off
98n2_err_adv_mcuUe_SiiDmuctagUe_L2_5 n2_err_adv_mcuUe_SiiDmuctagUe.s -midas_args=-DL2_5 -vcs_run_args=+dmusiu_bid_chk_off
99n2_err_adv_mcuUe_SiiDmuctagUe_L2_6 n2_err_adv_mcuUe_SiiDmuctagUe.s -midas_args=-DL2_6 -vcs_run_args=+dmusiu_bid_chk_off
100n2_err_adv_mcuUe_SiiDmuctagUe_L2_7 n2_err_adv_mcuUe_SiiDmuctagUe.s -midas_args=-DL2_7 -vcs_run_args=+dmusiu_bid_chk_off
101
102// Error Injection using User events
103n2_err_adv_DMUSII_CCE n2_err_adv_DMUSII_CCE.s
104n2_err_adv_DMUSII_CUE n2_err_adv_DMUSII_CUE.s -midas_args=-DERR_TYPE=DMUSII_CUE -midas_args=-DERR_FIELD=SiiDmuCtagUe -midas_args=-DSII_SYND=0x8100010123456000 -vcs_run_args=+dmusiu_bid_chk_off
105n2_err_adv_DMUSII_AP n2_err_adv_DMUSII_CUE.s -midas_args=-DERR_TYPE=DMUSII_AP -midas_args=-DERR_FIELD=SiiDmuAParity -midas_args=-DSII_SYND=0x8700010123456000
106n2_err_adv_DMUSII_CMDP n2_err_adv_DMUSII_CUE.s -midas_args=-DERR_TYPE=DMUSII_CMDP -midas_args=-DERR_FIELD=SiiDmuCtagUe -midas_args=-DSII_SYND=0x8100010123456000 -vcs_run_args=+dmusiu_bid_chk_off -vcs_run_args=+ios_ras_interrupt_chk_off
107n2_err_adv_SIODMU_CCE n2_err_adv_SIODMU_CCE.s
108n2_err_adv_SIODMU_CUE n2_err_adv_SIODMU_CUE.s -vcs_run_args=+dmusiu_bid_chk_off
109n2_err_adv_SIODMU_DP n2_err_adv_SIODMU_DP.s -vcs_run_args=+sio_dmu_ras_chk_off
110n2_err_adv_L2SIO_CCE n2_err_adv_L2SIO_CCE.s
111n2_err_adv_L2SIO_CUE n2_err_adv_L2SIO_CUE.s -vcs_run_args=+dmusiu_bid_chk_off
112// n2_err_adv_L2SIO_DP n2_err_adv_L2SIO_DP.s
113n2_err_adv_SIIDMU_WRACK_P n2_err_adv_SIIDMU_WRACK_P.s -midas_args=-DBANK0
114n2_err_adv_NCUDMU_MONDO_IDP n2_err_adv_NCUDMU_MONDO_IDP.s -midas_args=-DERR_FIELD=DmuNcuCredit -midas_args=-DTT=0x40
115
116// for coverage
117n2_err_adv_piu_mix_1 n2_err_adv_piu_mix_1.s -vcs_run_args=+L2DA_1Bit_ERR_ENABLE -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -midas_args=-DBANK0 -vcs_run_args=+sio_dmu_ras_chk_off
118
119
120// Stream of transactions
121n2_err_adv_piu_strm_wri_DMUSII_AP n2_err_adv_piu_strm_wri_DMUSII_UEV.s -midas_args=-DERR_TYPE=DMUSII_AP -midas_args=-DERR_FIELD=SiiDmuAParity
122n2_err_adv_piu_strm_wri_DMUSII_DP n2_err_adv_piu_strm_wri_DMUSII_UEV.s -midas_args=-DERR_TYPE=DMUSII_DP -midas_args=-DERR_FIELD=SiiDmuDParity
123
124n2_err_adv_piu_strm_wri_SiiDmuCtagUe n2_err_adv_piu_strm_wri_ejr.s -midas_args=-DERR_FIELD=SiiDmuCtagUe -midas_args=-DSII_SYND=0x8100000000000000 -nosas
125n2_err_adv_piu_strm_wri_SiiDmuAParity n2_err_adv_piu_strm_wri_ejr.s -midas_args=-DERR_FIELD=SiiDmuAParity -midas_args=-DSII_SYND=0x8700000000000000 -nosas
126//n2_err_adv_piu_strm_wri_SiiDmuDParity n2_err_adv_piu_strm_wri_ejr.s -midas_args=-DERR_FIELD=SiiDmuDParity -midas_args=-DSII_SYND=0x8500000000000000
127n2_err_adv_piu_strm_wri_DmuSiiCredit n2_err_adv_piu_strm_wri_ejr.s -midas_args=-DERR_FIELD=DmuSiiCredit -midas_args=-DSII_SYND=0x0 -nosas
128
129n2_err_adv_piu_strm_wrm_SiiDmuCtagUe n2_err_adv_piu_strm_wrm_ejr.s -midas_args=-DERR_FIELD=SiiDmuCtagUe -midas_args=-DSII_SYND=0x8100000000000000 -nosas
130n2_err_adv_piu_strm_wrm_SiiDmuAParity n2_err_adv_piu_strm_wrm_ejr.s -midas_args=-DERR_FIELD=SiiDmuAParity -midas_args=-DSII_SYND=0x8700000000000000
131//n2_err_adv_piu_strm_wrm_SiiDmuDParity n2_err_adv_piu_strm_wrm_ejr.s -midas_args=-DERR_FIELD=SiiDmuDParity -midas_args=-DSII_SYND=0x8500000000000000
132n2_err_adv_piu_strm_wrm_DmuSiiCredit n2_err_adv_piu_strm_wrm_ejr.s -midas_args=-DERR_FIELD=DmuSiiCredit -midas_args=-DSII_SYND=0x0 -nosas
133
134n2_err_adv_piu_strm_rdd_SiiDmuCtagUe n2_err_adv_piu_strm_rdd_ejr.s -midas_args=-DERR_FIELD=SiiDmuCtagUe -vcs_run_args=+dmusiu_bid_chk_off -midas_args=-DSII_SYND=0x8100000000000000
135n2_err_adv_piu_strm_rdd_SiiDmuAParity n2_err_adv_piu_strm_rdd_ejr.s -midas_args=-DERR_FIELD=SiiDmuAParity -midas_args=-DSII_SYND=0x8700000000000000
136n2_err_adv_piu_strm_rdd_SioCtagUe n2_err_adv_piu_strm_rdd_ejr.s -midas_args=-DERR_FIELD=SioCtagUe -vcs_run_args=+dmusiu_bid_chk_off -midas_args=-DSII_SYND=0x0
137n2_err_adv_piu_strm_rdd_DmuCtagUe n2_err_adv_piu_strm_rdd_ejr.s -midas_args=-DERR_FIELD=DmuCtagUe -vcs_run_args=+sio_dmu_ras_chk_off -midas_args=-DSII_SYND=0x0
138// dmu-ras chkr fail n2_err_adv_piu_strm_rdd_DmuDataParity n2_err_adv_piu_strm_rdd_ejr.s -midas_args=-DERR_FIELD=DmuDataParity
139
140// New
141n2_err_adv_pio_SiiDmuCtagCe n2_err_adv_pio_err.s -midas_args=-DERR_FIELD=SiiDmuCtagCe -vcs_run_args=+ios_0in_ras_chk_off -nosas
142n2_err_pio_DMUSII_CMDP n2_err_pio_DMUSII_CMDP.s -midas_args=-DERR_FIELD=SiiDmuCtagUe -vcs_run_args=+ios_0in_ras_chk_off -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=2 -vcs_run_args=+ios_ras_interrupt_chk_off
143
144</runargs>
145
146</sys(ios_adv_dmu_ras)>
147
148
149
150
151
152
153<sys(ios_adv_niu_ras) name=sys(ios_adv_niu_ras)>
154
155// NIU TX
156<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 >
157<runargs -vcs_run_args=+MAC_SPEED1=10000 >
158<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
159<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
160<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST >
161<runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
162<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
163
164n2_err_adv_NIUSII_CCE n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=SiiNiuCtagCe -midas_args=-DERR_TYPE=NIUSII_CCE -midas_args=-DCE -vcs_run_args=+ios_ras_interrupt_chk_off
165n2_err_adv_NIUSII_CUE n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -vcs_run_args=+ios_ras_interrupt_chk_off
166// To be added after NIU UE infrastructure is done. n2_err_adv_NIUSII_CUE_INT n2_err_adv_tx_uev_INT.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE
167n2_err_adv_NIUSII_AP n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=SiiNiuAParity -midas_args=-DERR_TYPE=NIUSII_AP -vcs_run_args=+ios_ras_interrupt_chk_off -vcs_run_args=+ios_ras_interrupt_chk_off
168
169n2_err_adv_SIONIU_CCE n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=NiuCtagCe -midas_args=-DERR_TYPE=SIONIU_CCE -midas_args=-DCE -vcs_run_args=+ios_ras_interrupt_chk_off
170n2_err_adv_SIONIU_CUE n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=NiuCtagUe -midas_args=-DERR_TYPE=SIONIU_CUE
171// To be added after NIU UE infrastructure is done. n2_err_adv_SIONIU_CUE_INT n2_err_adv_tx_uev_INT.s -midas_args=-DERR_FIELD=NiuCtagUe -midas_args=-DERR_TYPE=SIONIU_CUE
172n2_err_adv_SIONIU_DP n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=NiuDataParity -midas_args=-DERR_TYPE=SIONIU_DP
173
174n2_err_adv_L2SIO_CCE n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=SioCtagCe -midas_args=-DERR_TYPE=L2SIO_CCE -midas_args=-DCE -vcs_run_args=+ios_ras_interrupt_chk_off
175n2_err_adv_L2SIO_CUE n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=SioCtagUe -midas_args=-DERR_TYPE=L2SIO_CUE
176// n2_err_adv_L2SIO_DP n2_err_adv_tx_uev.s -midas_args=-DERR_FIELD=NiuDataParity -midas_args=-DERR_TYPE=L2SIO_DP
177n2_err_adv_tx_memerr n2_err_adv_tx_memerr.s -midas_args=-DERR_FIELD=SiiNiuCtagCe -midas_args=-DERR_TYPE=NIUSII_CCE
178
179
180n2_err_adv_Tx_NIUSII_CUE_B1 n2_err_adv_tx_uev_banks.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=3456040 -midas_args=-DERR_CTAG=0401 -vcs_run_args=+TX_PKT_LEN=512 -midas_args=-DTX_PKT_LEN=0x200
181
182n2_err_adv_Tx_NIUSII_CUE_B2 n2_err_adv_tx_uev_banks.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=3456080 -midas_args=-DERR_CTAG=0402 -vcs_run_args=+TX_PKT_LEN=512 -midas_args=-DTX_PKT_LEN=0x200
183
184n2_err_adv_Tx_NIUSII_CUE_B3 n2_err_adv_tx_uev_banks.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=34560c0 -midas_args=-DERR_CTAG=0403 -vcs_run_args=+TX_PKT_LEN=512 -midas_args=-DTX_PKT_LEN=0x200
185
186n2_err_adv_Tx_NIUSII_CUE_B4 n2_err_adv_tx_uev_banks.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=3456100 -midas_args=-DERR_CTAG=0404 -vcs_run_args=+TX_PKT_LEN=512 -midas_args=-DTX_PKT_LEN=0x200
187
188n2_err_adv_Tx_NIUSII_CUE_B5 n2_err_adv_tx_uev_banks.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=3456140 -midas_args=-DERR_CTAG=0405 -vcs_run_args=+TX_PKT_LEN=512 -midas_args=-DTX_PKT_LEN=0x200
189
190n2_err_adv_Tx_NIUSII_CUE_B6 n2_err_adv_tx_uev_banks.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=3456180 -midas_args=-DERR_CTAG=0406 -vcs_run_args=+TX_PKT_LEN=512 -midas_args=-DTX_PKT_LEN=0x200
191
192n2_err_adv_Tx_NIUSII_CUE_B7 n2_err_adv_tx_uev_banks.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=34561c0 -midas_args=-DERR_CTAG=0407 -vcs_run_args=+TX_PKT_LEN=512 -midas_args=-DTX_PKT_LEN=0x200
193
194
195</runargs>
196</runargs>
197</runargs>
198</runargs>
199</runargs>
200</runargs>
201</runargs>
202
203// NIU RX
204<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
205<runargs -vcs_run_args=+MAC_SPEED1=10000 >
206<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
207<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
208<runargs -vcs_run_args=+ORIG_META -midas_args=-DRX_TEST >
209<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
210<runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=10 >
211<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
212
213// Talking with MAQ: -vcs_run_args=+no_verilog_finish to NP writes only; as NP wrtes completion are not checked by checker
214// Posted writes are checked by checker; so turned off
215
216<runargs -vcs_run_args=+RX_TEST>
217n2_err_adv_rx_NPwr_SIONIU_CUE n2_err_adv_rx.s -midas_args=-DERR_FIELD=NiuCtagUe -midas_args=-DERR_TYPE=SIONIU_CUE -midas_args=-DERR_ADDR=d3b40000 -midas_args=-DERR_TAG=a000 -vcs_run_args=+no_verilog_finish
218n2_err_adv_rx_NPwr_SIONIU_CUE_INT n2_err_adv_rx_INT.s -midas_args=-DERR_FIELD=NiuCtagUe -midas_args=-DERR_TYPE=SIONIU_CUE -midas_args=-DERR_ADDR=d3b40000 -midas_args=-DERR_TAG=a000 -vcs_run_args=+no_verilog_finish
219n2_err_adv_rx_NPwr_NIUSII_CUE n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=d3b40000 -midas_args=-DERR_TAG=a000 -vcs_run_args=+no_verilog_finish
220n2_err_adv_rx_NPwr_NIUSII_CUE_INT n2_err_adv_rx_INT.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=d3b40000 -midas_args=-DERR_TAG=a000 -vcs_run_args=+no_verilog_finish
221n2_err_adv_rx_NPwr_NIUSII_AP n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuAParity -midas_args=-DERR_TYPE=NIUSII_AP -midas_args=-DERR_ADDR=d3b40000 -midas_args=-DERR_TAG=a000 -vcs_run_args=+no_verilog_finish
222n2_err_adv_rx_NPwr_NIUSII_DP n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuDParity -midas_args=-DERR_TYPE=NIUSII_DP -midas_args=-DERR_ADDR=d3b40000 -midas_args=-DERR_TAG=a000 -vcs_run_args=+no_verilog_finish
223n2_err_adv_rx_NPwr_L2SIO_CUE n2_err_adv_rx.s -midas_args=-DERR_FIELD=SioCtagUe -midas_args=-DERR_TYPE=L2SIO_CUE -midas_args=-DERR_ADDR=d3b40000 -midas_args=-DERR_TAG=a000 -vcs_run_args=+no_verilog_finish
224</runargs>
225
226n2_err_adv_rx_Pwr_NIUSII_CUE n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=5829b000 -midas_args=-DERR_TAG=9800
227n2_err_adv_rx_Pwr_NIUSII_AP n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuAParity -midas_args=-DERR_TYPE=NIUSII_AP -midas_args=-DERR_ADDR=5829b000 -midas_args=-DERR_TAG=9800
228n2_err_adv_rx_Pwr_NIUSII_DP n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuDParity -midas_args=-DERR_TYPE=NIUSII_DP -midas_args=-DERR_ADDR=5829b000 -midas_args=-DERR_TAG=9800
229// add a testcase not to expect error logging as the resonse is thrown out for Posted write
230// n2_err_adv_rx_Pwr_L2SIO_CUE n2_err_adv_rx.s -midas_args=-DERR_FIELD=SioCtagUe -midas_args=-DERR_TYPE=L2SIO_CUE -midas_args=-DERR_ADDR=5829b000 -midas_args=-DERR_TAG=9800
231
232n2_err_adv_rx_Pwr_NIUSII_CUE_B1 n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=58298040 -midas_args=-DERR_TAG=8001 -midas_args=-DMAC_PKT_LEN=0x300
233n2_err_adv_rx_Pwr_NIUSII_CUE_B2 n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=58298080 -midas_args=-DERR_TAG=8002 -midas_args=-DMAC_PKT_LEN=0x300
234n2_err_adv_rx_Pwr_NIUSII_CUE_B3 n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=582980c0 -midas_args=-DERR_TAG=8003 -midas_args=-DMAC_PKT_LEN=0x300
235n2_err_adv_rx_Pwr_NIUSII_CUE_B4 n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=58298100 -midas_args=-DERR_TAG=8004 -midas_args=-DMAC_PKT_LEN=0x300
236n2_err_adv_rx_Pwr_NIUSII_CUE_B5 n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=58298140 -midas_args=-DERR_TAG=8005 -midas_args=-DMAC_PKT_LEN=0x300
237n2_err_adv_rx_Pwr_NIUSII_CUE_B6 n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=58298180 -midas_args=-DERR_TAG=8006 -midas_args=-DMAC_PKT_LEN=0x300
238n2_err_adv_rx_Pwr_NIUSII_CUE_B7 n2_err_adv_rx.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=582981c0 -midas_args=-DERR_TAG=8007 -midas_args=-DMAC_PKT_LEN=0x300
239
240//for coverage
241n2_err_adv_niu_mix_rx_1 n2_err_adv_niu_mix_rx_1.s -midas_args=-DERR_FIELD=SiiNiuCtagUe -midas_args=-DERR_TYPE=NIUSII_CUE -midas_args=-DERR_ADDR=5829b000 -midas_args=-DERR_TAG=9800 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0
242
243</runargs>
244</runargs>
245</runargs>
246</runargs>
247</runargs>
248</runargs>
249</runargs>
250</runargs>
251
252</sys(ios_adv_niu_ras)>
253
254
255
256<sys(ios_adv_ncu_ras) name=sys(ios_adv_ncu_ras)>
257<runargs -vcs_run_args=+ios_0in_ras_chk_off >
258
259//NCU: using EJR
260n2_err_adv_NcuCtagCe_ld_trap n2_err_adv_ncuctagce.s -midas_args=-DERR_FIELD=NcuCtagCe -vcs_run_args=+PEU_TEST
261n2_err_adv_NcuCtagUe_ld_trap n2_err_adv_ncuctague.s -vcs_run_args=+PEU_TEST -midas_args=-DERR_FIELD=NcuCtagUe -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=2
262
263n2_err_adv_NcuCtagUe_int n2_err_adv_piu_int_ejr.s -midas_args=-DERR_FIELD=NcuCtagUe -midas_args=-DTT=0x40 -vcs_run_args=+lsu_mon_off
264n2_err_adv_NcuCtagCe_int n2_err_adv_piu_int_ejr.s -midas_args=-DERR_FIELD=NcuCtagCe -midas_args=-DTT=0x63
265
266n2_err_adv_NcuDataParity_mondo n2_err_adv_piu_int_ejr_nomondo.s -midas_args=-DERR_FIELD=NcuDataParity -vcs_run_args=+PEU_TEST
267n2_err_adv_NcuDmuUe_st n2_err_adv_NcuDmuUe_st.s -vcs_run_args=+PEU_TEST -midas_args=-DERR_FIELD=NcuDmuUe -nosas
268
269//NCU: using userevents
270n2_err_adv_DMUSII_TOUT n2_err_adv_peu_piord_uev.s -vcs_run_args=+PEU_TEST -midas_args=-DERR_TYPE=DMUSII_TOUT
271n2_err_adv_DMUSII_IOAE n2_err_adv_peu_piord_uev.s -vcs_run_args=+PEU_TEST -midas_args=-DERR_TYPE=DMUSII_IOAE
272n2_err_adv_DMUSII_IOUE n2_err_adv_peu_piord_uev.s -vcs_run_args=+PEU_TEST -midas_args=-DERR_TYPE=DMUSII_IOUE
273
274n2_err_pio_DMUSIIDP_NcuDP_UEV n2_err_pio_DMUSIIDP_NcuDP.s -vcs_run_args=+PEU_TEST -midas_args=-DERR_FIELD=SiiDmuDParity -midas_args=-DERR_FIELD_DETECT=NcuDataParity -midas_args=-DUEV -nosas -vcs_run_args=+ios_ras_interrupt_chk_off
275n2_err_pio_DMUSIIDP_NcuDP_EJR n2_err_pio_DMUSIIDP_NcuDP.s -vcs_run_args=+PEU_TEST -midas_args=-DERR_FIELD=SiiDmuDParity -midas_args=-DERR_FIELD_DETECT=NcuDataParity -midas_args=-DEJR -nosas
276
277
278//DMU
279n2_err_adv_DmuNcuCredit_int n2_err_adv_piu_int_ejr.s -midas_args=-DERR_FIELD=DmuNcuCredit -midas_args=-DTT=0x40
280
281</runargs>
282</sys(ios_adv_ncu_ras)>
283
284
285/////////////////////// Diags with follow up of Silicon Level Testing ////////////////////////////
286
287<sys(mcu_si_ras) name=sys(mcu_si_ras)>
288n2_mcu_si_DSC n2_mcu_si_DSC.s -vcs_run_args=+l2cpx_mon_off -midas_args=-DMCU0
289
290</sys(mcu_si_ras)>
291
292
293
294
295// for all diags
296</runargs>
297
298
299</sys(daily)>
300</sys(all)>
301</sys(fc_all)>
302
Full OpenSPARC design & verification tarball including full HDL.