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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fc_jtag_debug.diaglist | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | <sys(jtag_debug)> | |
36 | <runargs -tg_seed=1 -fast_boot -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DL2_REG_PROG> // seed locked to 1 for regression section only | |
37 | ||
38 | <core_ss name=core_ss> | |
39 | memop_all_atomics memop_all_atomics.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff fc_jtag_single_step_core.vr -rtl_timeout=100000 | |
40 | </core_ss> | |
41 | ||
42 | <core_do name=core_do> | |
43 | memop_all_atomics memop_all_atomics.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff fc_jtag_disable_overlap_core.vr -rtl_timeout=100000 | |
44 | </core_do> | |
45 | ||
46 | <shadow_scan_core name=shadow_scan_core> | |
47 | memop_all_atomics memop_all_atomics.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff fc_jtag_shadow_scan_core.vr | |
48 | ||
49 | <runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1> | |
50 | interrupt_SPU_interrupt interrupt_SPU_interrupt.s fc_jtag_shadow_scan_core.vr | |
51 | interrupt_ncu_regs_rw interrupt_ncu_regs_rw.s fc_jtag_shadow_scan_core.vr | |
52 | </runargs> | |
53 | ||
54 | // NIU diags | |
55 | <runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 > | |
56 | <runargs -vcs_run_args=+MAC_SPEED1=10000 > | |
57 | <runargs -vcs_run_args=+GET_MAC_PORTS=0 -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING > | |
58 | <runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr > | |
59 | <runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -vcs_run_args=+ORIG_META -vcs_run_args=+PEU_TEST > | |
60 | <runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES > | |
61 | <runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_PKT_LEN=200 -midas_args=-Dloop_count=100 -midas_args=-DJUMBO_FRAME_EN > | |
62 | FcNiuTx_PktLen_Gather FcNiuBasicTx.s fc_jtag_shadow_scan_core.vr -rtl_timeout=100000 | |
63 | </runargs> | |
64 | </runargs> | |
65 | </runargs> | |
66 | </runargs> | |
67 | </runargs> | |
68 | </runargs> | |
69 | </runargs> | |
70 | ||
71 | //PEU diags | |
72 | <runargs -sas -vcs_run_args=+PEU_TEST > | |
73 | PCIeMemRd PCIeMemRd.s fc_jtag_shadow_scan_core.vr | |
74 | </runargs> | |
75 | </shadow_scan_core> | |
76 | ||
77 | <shadow_scan_l2 name=shadow_scan_l2> | |
78 | <runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -rtl_timeout=100000> | |
79 | // L2 error diags | |
80 | n2_err_L2_NotData_NDSP_meu n2_err_L2_NotData_NDSP_meu.s -midas_args=-DL2_NDSP_err fc_jtag_shadow_scan_l2t.vr | |
81 | n2_err_L2_NotData_NDDM n2_err_L2_NotData_NDDM.s -midas_args=-DL2_NDSP_err -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off fc_jtag_shadow_scan_l2t.vr | |
82 | n2_err_L2_NotData_NDDM_meu n2_err_L2_NotData_NDDM_meu.s -midas_args=-DL2_NDSP_err -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off fc_jtag_shadow_scan_l2t.vr | |
83 | n2_err_l2_LDRC_cecc_trap n2_err_l2_LDRC_cecc_trap.s -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off fc_jtag_shadow_scan_l2t.vr | |
84 | </runargs> | |
85 | </shadow_scan_l2> | |
86 | ||
87 | <jtag_l2_access name=jtag_l2_access> | |
88 | jtag_and_PCIe_access_same_L2_bank PCIeDMARw_bug116647.s fc_tcu_siu_bug116647.vr -vcs_run_args=+PEU_TEST -sas | |
89 | tcu_l2_access_ld_st_allbanks tcu_l2_access_ld_st_allbanks.s fc_jtag_l2_access.vr | |
90 | </jtag_l2_access> | |
91 | ||
92 | <asm_ucb_access name=asm_ucb_access> | |
93 | tcu_asm_ucb_accesses_fc_a tcu_asm_ucb_accesses_fc_a.s tcu_asm_ucb_accesses_fc.vr | |
94 | </asm_ucb_access> | |
95 | ||
96 | </runargs> // -tg_seed=1 -fast_boot | |
97 | </sys(jtag_debug)> | |
98 | ||
99 | <fc_jtag_debug_gate> | |
100 | ||
101 | // <shadow_scan_l2 name=shadow_scan_l2> | |
102 | // <runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off> | |
103 | // // L2 error diags | |
104 | // n2_err_L2_NotData_NDSP_meu n2_err_L2_NotData_NDSP_meu.s -midas_args=-DL2_NDSP_err fc_jtag_shadow_scan_l2t_gate.vr | |
105 | // n2_err_L2_NotData_NDDM n2_err_L2_NotData_NDDM.s -midas_args=-DL2_NDSP_err -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off fc_jtag_shadow_scan_l2t_gate.vr | |
106 | // n2_err_L2_NotData_NDDM_meu n2_err_L2_NotData_NDDM_meu.s -midas_args=-DL2_NDSP_err -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off fc_jtag_shadow_scan_l2t_gate.vr | |
107 | // n2_err_l2_LDRC_cecc_trap n2_err_l2_LDRC_cecc_trap.s -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off fc_jtag_shadow_scan_l2t_gate.vr | |
108 | // </runargs> | |
109 | // </shadow_scan_l2> | |
110 | ||
111 | <jtag_l2_access name=jtag_l2_access> | |
112 | tcu_l2_access_ld_st_allbanks tcu_l2_access_ld_st_allbanks.s fc_jtag_l2_access.vr | |
113 | </jtag_l2_access> | |
114 | </fc_jtag_debug_gate> |