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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / fc_niu.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_niu.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35
36//<sys(fc_all)>
37//<sys(all)>
38//<sys(daily)>
39
40<fc_niu_all>
41
42#ifdef NIU_SYSTEMC_T2
43<runargs -vcs_run_args=+BYPASS_TXDRR -vcs_run_args=+ENABLE_MAC_HDR_DEBUG>
44<runargs -vcs_run_args=+RXWRITE_TIMEOUT=12000 -midas_args=-DNIU_SYSTEMC_T2>
45#endif
46
47// ****************************************************************************
48// ****************************************************************************
49// ****************************************************************************
50// ****************************************************************************
51// NIU PIO Read & Write
52// ****************************************************************************
53// The pio diag is moved to FcNiuQual.diaglist
54// ****************************************************************************
55
56
57// ****************************************************************************
58// 10G -> MAC0 -> NIU Tx.
59// ****************************************************************************
60<FcNiu10GMac0Tx name=FcNiu10GMac0Tx>
61
62<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
63<runargs -vcs_run_args=+MAC_SPEED1=10000 >
64<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
65<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
66<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST >
67<runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
68<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
69
70<runargs -midas_args=-DNIU_TX_DMA_NUM=1 -midas_args=-DNIU_TX_DMA_ACT_LIST=2 >
71FcNiuTx_DMA1 FcNiuBasicTx.s
72</runargs>
73
74<runargs -midas_args=-DNIU_TX_DMA_NUM=15 -midas_args=-DNIU_TX_DMA_ACT_LIST=0x8000 >
75FcNiuTx_DMA15 FcNiuBasicTx.s
76</runargs>
77
78<runargs -midas_args=-DNIU_TX_PKT_CNT=0x19 -midas_args=-Dloop_count=20 -midas_args=-DJUMBO_FRAME_EN >
79FcNiuTx_PktCnt25 FcNiuBasicTx.s
80</runargs>
81
82<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_PKT_LEN=200 -midas_args=-Dloop_count=100 -midas_args=-DJUMBO_FRAME_EN >
83FcNiuTx_PktLen_Gather FcNiuBasicTx.s
84</runargs>
85
86<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_BUFFSZ=4080 -midas_args=-Dloop_count=0xff >
87<runargs -midas_args=-DJUMBO_FRAME_EN -vcs_run_args=+TX_PKT_LEN=9500 -midas_args=-DTX_PKT_LEN=251c -midas_args=-DNIU_TX_PKT_CNT=1 >
88FcNiuTx_PktCnt1_Jumbo FcNiuBasicTx.s
89</runargs>
90</runargs>
91
92
93</runargs>
94</runargs>
95</runargs>
96</runargs>
97</runargs>
98</runargs>
99</runargs>
100
101</FcNiu10GMac0Tx>
102// ****************************************************************************
103
104// ****************************************************************************
105// 10G -> MAC0 -> NIU Rx.
106// ****************************************************************************
107<FcNiu10GMac0Rx name=FcNiu10GMac0Rx>
108
109<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
110<runargs -vcs_run_args=+MAC_SPEED1=10000 >
111<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
112<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
113<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+RX_TEST -midas_args=-DRX_TEST >
114<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
115<runargs -vcs_run_args=+no_verilog_finish >
116<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
117
118<runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=10 >
119<runargs -midas_args=-DRXDMA_CHNL=0xf >
120FcNiuRx_DMA15 FcNiuBasicRx_sweep1.s
121
122<runargs -midas_args=-DXLATE_ON >
123FcNiuRx_DMA15_Xlate FcNiuBasicRx_sweep1.s
124</runargs>
125
126</runargs>
127</runargs>
128
129<runargs -midas_args=-DMAC_PKT_LEN=0x251c -vcs_run_args=+WRCHK_TO=3400 -midas_args=-Dloop_count=100 >
130<runargs -midas_args=-DJUMBO_FRAME_EN >
131FcNiuRx_DMA15_Xlate_Jumbo FcNiuBasicRx_sweep1.s
132
133</runargs>
134</runargs>
135
136</runargs>
137</runargs>
138</runargs>
139</runargs>
140</runargs>
141</runargs>
142</runargs>
143</runargs>
144
145</FcNiu10GMac0Rx>
146// ****************************************************************************
147
148// ****************************************************************************
149// 10G -> MAC1 -> NIU Tx.
150// ****************************************************************************
151<FcNiu10GMac1Tx name=FcNiu10GMac1Tx>
152
153<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
154<runargs -vcs_run_args=+MAC_SPEED1=10000 >
155<runargs -vcs_run_args=+GET_MAC_PORTS=1 >
156<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
157<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST >
158<runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
159<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
160<runargs -midas_args=-DMAC_ID=1 >
161
162<runargs -midas_args=-DNIU_TX_DMA_NUM=15 -midas_args=-DNIU_TX_DMA_ACT_LIST=0x8000 >
163<runargs -midas_args=-DNIU_TX_PKT_CNT=0x19 -midas_args=-Dloop_count=20 -midas_args=-DJUMBO_FRAME_EN >
164FcNiuTx_McPort1_DMA15_PktCnt25 FcNiuBasicTx.s
165
166<runargs -midas_args=-DXLATE_ON -vcs_run_args=+USE_RANDOM_ADDRESS >
167FcNiuTx_McPort1_DMA15_PktCnt25_Xlate FcNiuBasicTx.s
168</runargs>
169
170</runargs>
171</runargs>
172
173<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_BUFFSZ=4080 -midas_args=-Dloop_count=0xff >
174<runargs -midas_args=-DJUMBO_FRAME_EN -vcs_run_args=+TX_PKT_LEN=9500 -midas_args=-DTX_PKT_LEN=251c -midas_args=-DNIU_TX_PKT_CNT=1 >
175FcNiuTx_McPort1_PktCnt1_Jumbo FcNiuBasicTx.s
176</runargs>
177</runargs>
178
179</runargs>
180</runargs>
181</runargs>
182</runargs>
183</runargs>
184</runargs>
185</runargs>
186</runargs>
187
188</FcNiu10GMac1Tx>
189// ****************************************************************************
190
191// ****************************************************************************
192// 10G -> MAC1 -> NIU Rx.
193// ****************************************************************************
194<FcNiu10GMac1Rx name=FcNiu10GMac1Rx>
195
196<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
197<runargs -vcs_run_args=+MAC_SPEED1=10000 >
198<runargs -vcs_run_args=+GET_MAC_PORTS=1 >
199<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
200<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+RX_TEST -midas_args=-DRX_TEST >
201<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
202<runargs -midas_args=-DMAC_ID=1 >
203<runargs -vcs_run_args=+no_verilog_finish >
204<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
205
206<runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=10 >
207<runargs -midas_args=-DRXDMA_CHNL=0xf >
208FcNiuRx_McPort1_DMA15 FcNiuBasicRx_sweep1.s
209
210<runargs -midas_args=-DXLATE_ON >
211FcNiuRx_McPort1_DMA15_Xlate FcNiuBasicRx_sweep1.s
212</runargs>
213
214</runargs>
215</runargs>
216
217<runargs -midas_args=-DMAC_PKT_LEN=0x251c -vcs_run_args=+WRCHK_TO=3400 -midas_args=-Dloop_count=100 >
218<runargs -midas_args=-DJUMBO_FRAME_EN >
219FcNiuRx_McPort1_DMA15_Jumbo FcNiuBasicRx_sweep1.s
220
221</runargs>
222</runargs>
223
224</runargs>
225</runargs>
226</runargs>
227</runargs>
228</runargs>
229</runargs>
230</runargs>
231</runargs>
232</runargs>
233
234</FcNiu10GMac1Rx>
235// ****************************************************************************
236
237// ****************************************************************************
238// ****************************************************************************
239// ****************************************************************************
240// ****************************************************************************
241#include "FcNiuQual.diaglist"
242#include "Fc_MT.diaglist"
243#include "Fc_Niu_Multi.diaglist"
244<runargs -midas_args=-Dloop_count=100>
245//#include "Fc_Niu_Multi_Perf.diaglist"
246</runargs>
247
248//KH #include "fc_niu_rx_P0P1_2DMA.diaglist"
249//KH #include "fc_niu_rx_P0P1_4DMA.diaglist"
250//KH #include "fc_niu_rx_P0P1_8DMA.diaglist"
251
252//KH #include "fc_niu_tx_P0P1_2DMA.diaglist"
253// ****************************************************************************
254// ****************************************************************************
255// ****************************************************************************
256// ****************************************************************************
257#ifdef NIU_SYSTEMC_T2
258</runargs>
259</runargs>
260#endif
261</fc_niu_all>
262
263//</sys(daily)>
264//</sys(all)>
265//</sys(fc_all)>
Full OpenSPARC design & verification tarball including full HDL.