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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / fc_niu_rx_P0P1_2DMA.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_niu_rx_P0P1_2DMA.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<FcNiuRx_MP_2DMA name=FcNiuRx_MP_2DMA>
36
37<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
38<runargs -vcs_run_args=+MAC_SPEED1=10000 >
39<runargs -vcs_run_args=+GET_MAC_PORTS=01 >
40<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
41<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+RX_TEST -midas_args=-DRX_TEST >
42<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
43<runargs -vcs_run_args=+no_verilog_finish >
44<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
45<runargs -vcs_run_args=+MULTI_TEST -midas_args=-DMULTI_TEST -vcs_run_args=+NIU_RX_MULTI_PORT -midas_args=-DNIU_RX_MULTI_PORT >
46
47//KH <runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=10 >
48//KH <runargs -midas_args=-DRXDMA_CHNL=0xf >
49//KH FcNiuRx_DMA15 FcNiuBasicRx_sweep1.s
50//KH <runargs -midas_args=-DXLATE_ON >
51//KH FcNiuRx_DMA15_Xlate FcNiuBasicRx_sweep1.s
52//KH </runargs>
53//KH </runargs>
54//KH </runargs>
55//KH <runargs -midas_args=-DMAC_PKT_LEN=0x251c -vcs_run_args=+WRCHK_TO=3400 -midas_args=-Dloop_count=100 >
56//KH <runargs -midas_args=-DJUMBO_FRAME_EN >
57//KH FcNiuRx_DMA15_Xlate_Jumbo FcNiuBasicRx_sweep1.s
58//KH </runargs>
59//KH </runargs>
60
61<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
62<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x11 -vcs_run_args=+NIU_RX_MULTI_DMA=11 >
63FcNiuRx_MP_2DMA_1_1 rx_p0p1_MULTI_2DMA_rand_11.s
64</runargs>
65</runargs>
66
67<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
68<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x21 -vcs_run_args=+NIU_RX_MULTI_DMA=21 >
69FcNiuRx_MP_2DMA_2_1 rx_p0p1_MULTI_2DMA_rand_21.s
70</runargs>
71</runargs>
72
73<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
74<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x41 -vcs_run_args=+NIU_RX_MULTI_DMA=41 >
75FcNiuRx_MP_2DMA_4_1 rx_p0p1_MULTI_2DMA_rand_41.s
76</runargs>
77</runargs>
78
79<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
80<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x81 -vcs_run_args=+NIU_RX_MULTI_DMA=81 >
81FcNiuRx_MP_2DMA_8_1 rx_p0p1_MULTI_2DMA_rand_81.s
82</runargs>
83</runargs>
84
85<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
86<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x12 -vcs_run_args=+NIU_RX_MULTI_DMA=12 >
87FcNiuRx_MP_2DMA_1_2 rx_p0p1_MULTI_2DMA_rand_12.s
88</runargs>
89</runargs>
90
91<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
92<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x22 -vcs_run_args=+NIU_RX_MULTI_DMA=22 >
93FcNiuRx_MP_2DMA_2_2 rx_p0p1_MULTI_2DMA_rand_22.s
94</runargs>
95</runargs>
96
97<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
98<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x42 -vcs_run_args=+NIU_RX_MULTI_DMA=42 >
99FcNiuRx_MP_2DMA_4_2 rx_p0p1_MULTI_2DMA_rand_42.s
100</runargs>
101</runargs>
102
103<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
104<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x82 -vcs_run_args=+NIU_RX_MULTI_DMA=82 >
105FcNiuRx_MP_2DMA_8_2 rx_p0p1_MULTI_2DMA_rand_82.s
106</runargs>
107</runargs>
108
109<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
110<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x14 -vcs_run_args=+NIU_RX_MULTI_DMA=14 >
111FcNiuRx_MP_2DMA_1_4 rx_p0p1_MULTI_2DMA_rand_14.s
112</runargs>
113</runargs>
114
115<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
116<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x24 -vcs_run_args=+NIU_RX_MULTI_DMA=24 >
117FcNiuRx_MP_2DMA_2_4 rx_p0p1_MULTI_2DMA_rand_24.s
118</runargs>
119</runargs>
120
121<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
122<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x44 -vcs_run_args=+NIU_RX_MULTI_DMA=44 >
123FcNiuRx_MP_2DMA_4_4 rx_p0p1_MULTI_2DMA_rand_44.s
124</runargs>
125</runargs>
126
127<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
128<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x84 -vcs_run_args=+NIU_RX_MULTI_DMA=84 >
129FcNiuRx_MP_2DMA_8_4 rx_p0p1_MULTI_2DMA_rand_84.s
130</runargs>
131</runargs>
132
133<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
134<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x18 -vcs_run_args=+NIU_RX_MULTI_DMA=18 >
135FcNiuRx_MP_2DMA_1_8 rx_p0p1_MULTI_2DMA_rand_18.s
136</runargs>
137</runargs>
138
139<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
140<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x28 -vcs_run_args=+NIU_RX_MULTI_DMA=28 >
141FcNiuRx_MP_2DMA_2_8 rx_p0p1_MULTI_2DMA_rand_28.s
142</runargs>
143</runargs>
144
145<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
146<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x48 -vcs_run_args=+NIU_RX_MULTI_DMA=48 >
147FcNiuRx_MP_2DMA_4_8 rx_p0p1_MULTI_2DMA_rand_48.s
148</runargs>
149</runargs>
150
151<runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 >
152<runargs -midas_args=-DNIU_RX_MULTI_DMA=0x88 -vcs_run_args=+NIU_RX_MULTI_DMA=88 >
153FcNiuRx_MP_2DMA_8_8 rx_p0p1_MULTI_2DMA_rand_88.s
154</runargs>
155</runargs>
156
157</runargs>
158</runargs>
159</runargs>
160</runargs>
161</runargs>
162</runargs>
163</runargs>
164</runargs>
165</runargs>
166
167</FcNiuRx_MP_2DMA>
Full OpenSPARC design & verification tarball including full HDL.