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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fc_niu_rx_P0P1_4DMA.diaglist | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | <FcNiuRx_MP_4DMA name=FcNiuRx_MP_4DMA> | |
36 | ||
37 | <runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 > | |
38 | <runargs -vcs_run_args=+MAC_SPEED1=10000 > | |
39 | <runargs -vcs_run_args=+GET_MAC_PORTS=01 > | |
40 | <runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr > | |
41 | <runargs -vcs_run_args=+ORIG_META -vcs_run_args=+RX_TEST -midas_args=-DRX_TEST > | |
42 | <runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES > | |
43 | <runargs -vcs_run_args=+no_verilog_finish > | |
44 | <runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING > | |
45 | <runargs -vcs_run_args=+MULTI_TEST -midas_args=-DMULTI_TEST -vcs_run_args=+NIU_RX_MULTI_PORT -midas_args=-DNIU_RX_MULTI_PORT > | |
46 | ||
47 | //KH <runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=10 > | |
48 | //KH <runargs -midas_args=-DRXDMA_CHNL=0xf > | |
49 | //KH FcNiuRx_McPort1_DMA15 FcNiuBasicRx_sweep1.s | |
50 | //KH <runargs -midas_args=-DXLATE_ON > | |
51 | //KH FcNiuRx_McPort1_DMA15_Xlate FcNiuBasicRx_sweep1.s | |
52 | //KH </runargs> | |
53 | //KH </runargs> | |
54 | //KH </runargs> | |
55 | //KH <runargs -midas_args=-DMAC_PKT_LEN=0x251c -vcs_run_args=+WRCHK_TO=3400 -midas_args=-Dloop_count=100 > | |
56 | //KH <runargs -midas_args=-DJUMBO_FRAME_EN > | |
57 | //KH FcNiuRx_McPort1_DMA15_Jumbo FcNiuBasicRx_sweep1.s | |
58 | //KH </runargs> | |
59 | //KH </runargs> | |
60 | ||
61 | <runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 > | |
62 | <runargs -midas_args=-DNIU_RX_MULTI_DMA=0x33 -vcs_run_args=+NIU_RX_MULTI_DMA=33 > | |
63 | FcNiuRx_MP_4DMA_3-1_2-0 rx_p0p1_MULTI_4DMA_rand_33.s | |
64 | </runargs> | |
65 | </runargs> | |
66 | ||
67 | <runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 > | |
68 | <runargs -midas_args=-DNIU_RX_MULTI_DMA=0xcc -vcs_run_args=+NIU_RX_MULTI_DMA=cc > | |
69 | FcNiuRx_MP_4DMA_7-5_6-4 rx_p0p1_MULTI_4DMA_rand_CC.s | |
70 | </runargs> | |
71 | </runargs> | |
72 | ||
73 | <runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 > | |
74 | <runargs -midas_args=-DNIU_RX_MULTI_DMA=0x66 -vcs_run_args=+NIU_RX_MULTI_DMA=66 > | |
75 | FcNiuRx_MP_4DMA_5-3_4-2 rx_p0p1_MULTI_4DMA_rand_66.s | |
76 | </runargs> | |
77 | </runargs> | |
78 | ||
79 | <runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 > | |
80 | <runargs -midas_args=-DNIU_RX_MULTI_DMA=0x55 -vcs_run_args=+NIU_RX_MULTI_DMA=55 > | |
81 | FcNiuRx_MP_4DMA_5-1_4-0 rx_p0p1_MULTI_4DMA_rand_55.s | |
82 | </runargs> | |
83 | </runargs> | |
84 | ||
85 | <runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 > | |
86 | <runargs -midas_args=-DNIU_RX_MULTI_DMA=0xaa -vcs_run_args=+NIU_RX_MULTI_DMA=aa > | |
87 | FcNiuRx_MP_4DMA_7-3_6-2 rx_p0p1_MULTI_4DMA_rand_AA.s | |
88 | </runargs> | |
89 | </runargs> | |
90 | ||
91 | <runargs -midas_args=-DRXMAC_PKTCNT=0x20 -vcs_run_args=+RXMAC_PKTCNT=32 -midas_args=-DNIU_RX_PKT_LEN=0x100 > | |
92 | <runargs -midas_args=-DNIU_RX_MULTI_DMA=0x99 -vcs_run_args=+NIU_RX_MULTI_DMA=99 > | |
93 | FcNiuRx_MP_4DMA_7-1_6-0 rx_p0p1_MULTI_4DMA_rand_99.s | |
94 | </runargs> | |
95 | </runargs> | |
96 | ||
97 | </runargs> | |
98 | </runargs> | |
99 | </runargs> | |
100 | </runargs> | |
101 | </runargs> | |
102 | </runargs> | |
103 | </runargs> | |
104 | </runargs> | |
105 | </runargs> | |
106 | ||
107 | </FcNiuRx_MP_4DMA> |