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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / fc_niu_tx_P0P1_2DMA.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_niu_tx_P0P1_2DMA.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<FcNiuP0P1_2DMA_0 name=FcNiuP0P1_2DMA_0>
36
37<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
38<runargs -vcs_run_args=+MAC_SPEED1=10000 -vcs_run_args=+GET_MAC_PORTS=01 >
39<runargs -vcs_run_args=+NIU_TX_PKT_LEN_P0=64 -midas_args=-DNIU_TX_PKT_LEN_P0=0x40 >
40<runargs -vcs_run_args=+NIU_TX_PKT_LEN_P1=70 -midas_args=-DNIU_TX_PKT_LEN_P1=0x46 >
41<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
42<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DNIU_TX_PKT_CNT=0x20 >
43<runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
44<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
45<runargs -vcs_run_args=+NIU_TX_MULTI_TEST -midas_args=-DNIU_TX_MULTI_TEST -vcs_run_args=+NIU_TX_MULTI_PORT -midas_args=-DNIU_TX_MULTI_PORT >
46
47//KH <runargs -midas_args=-DNIU_TX_DMA_NUM=15 -midas_args=-DNIU_TX_DMA_ACT_LIST=0x8000 >
48//KH <runargs -midas_args=-DNIU_TX_PKT_CNT=0x19 -midas_args=-Dloop_count=20 -midas_args=-DJUMBO_FRAME_EN >
49//KH FcNiuTx_McPort1_DMA15_PktCnt25 FcNiuBasicTx.s
50//KH <runargs -midas_args=-DXLATE_ON -vcs_run_args=+USE_RANDOM_ADDRESS >
51//KH FcNiuTx_McPort1_DMA15_PktCnt25_Xlate FcNiuBasicTx.s
52//KH </runargs>
53//KH </runargs>
54//KH </runargs>
55//KH <runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_BUFFSZ=4080 -midas_args=-Dloop_count=0xff >
56//KH <runargs -midas_args=-DJUMBO_FRAME_EN -vcs_run_args=+TX_PKT_LEN=9500 -midas_args=-DNIU_TX_PKT_CNT=1 >
57//KH FcNiuTx_McPort1_PktCnt1_Jumbo FcNiuBasicTx.s
58//KH </runargs>
59//KH </runargs>
60
61//<runargs -midas_args=-DNIU_TX_DMA_NUM=1 -midas_args=-DNIU_TX_DMA_ACT_LIST=2 >
62<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
63<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0002 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0002 >
64FcNiuTx_MULTI_P0DMA_0001_P1DMA_0002 tx_MULTI_PORT_DMA_rand.s
65</runargs>
66</runargs>
67
68//<runargs -midas_args=-DNIU_TX_DMA_NUM=15 -midas_args=-DNIU_TX_DMA_ACT_LIST=0x8000 >
69<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
70<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0004 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0004 >
71FcNiuTx_MULTI_P0DMA_0001_P1DMA_0004 tx_MULTI_PORT_DMA_rand.s
72</runargs>
73</runargs>
74
75//<runargs -midas_args=-DNIU_TX_PKT_CNT=0x19 -midas_args=-Dloop_count=20 -midas_args=-DJUMBO_FRAME_EN >
76<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
77<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0008 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0008 >
78FcNiuTx_MULTI_P0DMA_0001_P1DMA_0008 tx_MULTI_PORT_DMA_rand.s
79</runargs>
80</runargs>
81
82//<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_PKT_LEN=200 -midas_args=-Dloop_count=100 -midas_args=-DJUMBO_FRAME_EN >
83<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
84<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0010 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0010 >
85FcNiuTx_MULTI_P0DMA_0001_P1DMA_0010_TX_GATHER tx_MULTI_PORT_DMA_rand.s
86</runargs>
87</runargs>
88
89//<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_BUFFSZ=4080 -midas_args=-Dloop_count=0xff >
90//<runargs -midas_args=-DJUMBO_FRAME_EN -vcs_run_args=+TX_PKT_LEN=9500 -midas_args=-DNIU_TX_PKT_CNT=8 >
91<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
92<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0020 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0020 >
93FcNiuTx_MULTI_P0DMA_0001_P1DMA_0020 tx_MULTI_PORT_DMA_rand.s
94</runargs>
95</runargs>
96
97<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
98<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0040 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0040 >
99FcNiuTx_MULTI_P0DMA_0001_P1DMA_0040 tx_MULTI_PORT_DMA_rand.s
100</runargs>
101</runargs>
102
103<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
104<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0080 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0080 >
105FcNiuTx_MULTI_P0DMA_0001_P1DMA_0080 tx_MULTI_PORT_DMA_rand.s
106</runargs>
107</runargs>
108
109<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
110<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0100 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0100 >
111FcNiuTx_MULTI_P0DMA_0001_P1DMA_0100 tx_MULTI_PORT_DMA_rand.s
112</runargs>
113</runargs>
114
115<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
116<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0200 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0200 >
117FcNiuTx_MULTI_P0DMA_0001_P1DMA_0200 tx_MULTI_PORT_DMA_rand.s
118</runargs>
119</runargs>
120
121<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
122<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0400 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0400 >
123FcNiuTx_MULTI_P0DMA_0001_P1DMA_0400 tx_MULTI_PORT_DMA_rand.s
124</runargs>
125</runargs>
126
127<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
128<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0800 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0800 >
129FcNiuTx_MULTI_P0DMA_0001_P1DMA_0800 tx_MULTI_PORT_DMA_rand.s
130</runargs>
131</runargs>
132
133<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
134<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=1000 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x1000 >
135FcNiuTx_MULTI_P0DMA_0001_P1DMA_1000 tx_MULTI_PORT_DMA_rand.s
136</runargs>
137</runargs>
138
139<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
140<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=2000 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x2000 >
141FcNiuTx_MULTI_P0DMA_0001_P1DMA_2000 tx_MULTI_PORT_DMA_rand.s
142</runargs>
143</runargs>
144
145<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
146<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=4000 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x4000 >
147FcNiuTx_MULTI_P0DMA_0001_P1DMA_4000 tx_MULTI_PORT_DMA_rand.s
148</runargs>
149</runargs>
150
151<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0001 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0001 >
152<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=8000 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x8000 >
153FcNiuTx_MULTI_P0DMA_0001_P1DMA_8000 tx_MULTI_PORT_DMA_rand.s
154</runargs>
155</runargs>
156
157
158</runargs>
159</runargs>
160</runargs>
161</runargs>
162</runargs>
163</runargs>
164</runargs>
165</runargs>
166</runargs>
167
168</FcNiuP0P1_2DMA_0>
169// ****************************************************************************
170
171// ****************************************************************************
172// P0P1 Multi_Port/Mluti_DMA (Port0 DMA1-15, Port1 DMA0)
173// ****************************************************************************
174<FcNiuP0P1_2DMA_1 name=FcNiuP0P1_2DMA_1>
175
176<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
177<runargs -vcs_run_args=+MAC_SPEED1=10000 -vcs_run_args=+GET_MAC_PORTS=01 >
178<runargs -vcs_run_args=+NIU_TX_PKT_LEN_P0=64 -midas_args=-DNIU_TX_PKT_LEN_P0=0x40 >
179<runargs -vcs_run_args=+NIU_TX_PKT_LEN_P1=70 -midas_args=-DNIU_TX_PKT_LEN_P1=0x46 >
180<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
181<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST -midas_args=-DNIU_TX_PKT_CNT=0x20 >
182<runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
183<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
184<runargs -vcs_run_args=+NIU_TX_MULTI_TEST -midas_args=-DNIU_TX_MULTI_TEST -vcs_run_args=+NIU_TX_MULTI_PORT -midas_args=-DNIU_TX_MULTI_PORT >
185
186//<runargs -midas_args=-DNIU_TX_DMA_NUM=1 -midas_args=-DNIU_TX_DMA_ACT_LIST=2 >
187<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
188<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0002 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0002 >
189FcNiuTx_MULTI_P1DMA_0001_P0DMA_0002 tx_MULTI_PORT_DMA_rand.s
190</runargs>
191</runargs>
192
193//<runargs -midas_args=-DNIU_TX_DMA_NUM=15 -midas_args=-DNIU_TX_DMA_ACT_LIST=0x8000 >
194<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
195<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0004 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0004 >
196FcNiuTx_MULTI_P1DMA_0001_P0DMA_0004 tx_MULTI_PORT_DMA_rand.s
197</runargs>
198</runargs>
199
200//<runargs -midas_args=-DNIU_TX_PKT_CNT=0x19 -midas_args=-Dloop_count=20 -midas_args=-DJUMBO_FRAME_EN >
201<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
202<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0008 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0008 >
203FcNiuTx_MULTI_P1DMA_0001_P0DMA_0008 tx_MULTI_PORT_DMA_rand.s
204</runargs>
205</runargs>
206
207//<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_PKT_LEN=200 -midas_args=-Dloop_count=100 -midas_args=-DJUMBO_FRAME_EN >
208<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
209<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0010 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0010 >
210FcNiuTx_MULTI_P1DMA_0001_P0DMA_0010_TX_GATHER tx_MULTI_PORT_DMA_rand.s
211</runargs>
212</runargs>
213
214//<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_BUFFSZ=4080 -midas_args=-Dloop_count=0xff >
215//<runargs -midas_args=-DJUMBO_FRAME_EN -vcs_run_args=+TX_PKT_LEN=9500 -midas_args=-DNIU_TX_PKT_CNT=8 >
216<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
217<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0020 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0020 >
218FcNiuTx_MULTI_P1DMA_0001_P0DMA_0020 tx_MULTI_PORT_DMA_rand.s
219</runargs>
220</runargs>
221
222<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
223<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0040 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0040 >
224FcNiuTx_MULTI_P1DMA_0001_P0DMA_0040 tx_MULTI_PORT_DMA_rand.s
225</runargs>
226</runargs>
227
228<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
229<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0080 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0080 >
230FcNiuTx_MULTI_P1DMA_0001_P0DMA_0080 tx_MULTI_PORT_DMA_rand.s
231</runargs>
232</runargs>
233
234<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
235<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0100 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0100 >
236FcNiuTx_MULTI_P1DMA_0001_P0DMA_0100 tx_MULTI_PORT_DMA_rand.s
237</runargs>
238</runargs>
239
240<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
241<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0200 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0200 >
242FcNiuTx_MULTI_P1DMA_0001_P0DMA_0200 tx_MULTI_PORT_DMA_rand.s
243</runargs>
244</runargs>
245
246<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
247<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0400 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0400 >
248FcNiuTx_MULTI_P1DMA_0001_P0DMA_0400 tx_MULTI_PORT_DMA_rand.s
249</runargs>
250</runargs>
251
252<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
253<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=0800 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x0800 >
254FcNiuTx_MULTI_P1DMA_0001_P0DMA_0800 tx_MULTI_PORT_DMA_rand.s
255</runargs>
256</runargs>
257
258<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
259<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=1000 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x1000 >
260FcNiuTx_MULTI_P1DMA_0001_P0DMA_1000 tx_MULTI_PORT_DMA_rand.s
261</runargs>
262</runargs>
263
264<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
265<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=2000 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x2000 >
266FcNiuTx_MULTI_P1DMA_0001_P0DMA_2000 tx_MULTI_PORT_DMA_rand.s
267</runargs>
268</runargs>
269
270<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
271<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=4000 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x4000 >
272FcNiuTx_MULTI_P1DMA_0001_P0DMA_4000 tx_MULTI_PORT_DMA_rand.s
273</runargs>
274</runargs>
275
276<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P1=0001 -midas_args=-DNIU_TX_MULTI_DMA_P1=0x0001 >
277<runargs -vcs_run_args=+NIU_TX_MULTI_DMA_P0=8000 -midas_args=-DNIU_TX_MULTI_DMA_P0=0x8000 >
278FcNiuTx_MULTI_P0DMA_0001_P1DMA_8000 tx_MULTI_PORT_DMA_rand.s
279</runargs>
280</runargs>
281
282
283</runargs>
284</runargs>
285</runargs>
286</runargs>
287</runargs>
288</runargs>
289</runargs>
290</runargs>
291</runargs>
292
293</FcNiuP0P1_2DMA_1>
294// ****************************************************************************
295
Full OpenSPARC design & verification tarball including full HDL.