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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / misc / spc_mbist.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: spc_mbist.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<spc2_mbist sys=spc2 -sunv_run -config_cpp_args=-DMBIST -zeroIn_build CONFIG_ARG1 -config_rtl=ZIN_CORE_MBIST>
36
37<core_mbist name=core_mbist>
38<runargs -tg_seed=1 -config_cpp_args=-DMBIST>
39
40//--------------------------------------
41// Long diags - run once a week
42
43<spc_secondary_all>
44<core_mbist_long>
45
46mbist_default spc2_hboot_test.s -vcs_run_args=+mbist_mode=4 -max_cycle=1336000 -drm_cpufreq='1200 ..'
47mbist_user_mb0_icd spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=1 -max_cycle=690000 -drm_cpufreq='1200 ..'
48mbist_user_mb2_irfsh spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=4 -max_cycle=288000 -drm_cpufreq='1200 ..'
49
50
51//mbist_default_mb0_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=4 -max_cycle=1336000 -drm_cpufreq='1200 ..' -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=507452 -vcs_run_args=+mbist_force_array=1ffe000
52//mbist_default_mb1_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=4 -max_cycle=1336000 -drm_cpufreq='1200 ..' -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=61056 -vcs_run_args=+mbist_force_array=0001fc0
53//mbist_default_mb2_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=4 -max_cycle=1336000 -drm_cpufreq='1200 ..' -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=85696 -vcs_run_args=+mbist_force_array=000003f
54mbist_user_mb0_icd_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=1 -max_cycle=690000 -drm_cpufreq='1200 ..' -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=294912 -vcs_run_args=+mbist_force_array=0004000
55mbist_user_mb2_irfsh_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=4 -max_cycle=288000 -drm_cpufreq='1200 ..' -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=39872 -vcs_run_args=+mbist_force_array=0000010
56
57</core_mbist_long>
58
59//--------------------------------------
60// Short diags - run nightly
61
62<spc_secondary_nightly>
63<core_mbist_fast>
64
65mbist_bisi spc2_hboot_test.s -vcs_run_args=+mbist_mode=6 -max_cycle=14000
66
67mbist_ubisi_mb0_dva spc2_hboot_test.s -vcs_run_args=+mbist_mode=7 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=6 -max_cycle=300
68mbist_ubisi_mb1_tca spc2_hboot_test.s -vcs_run_args=+mbist_mode=7 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=2 -max_cycle=300
69mbist_ubisi_mb2_irfsh spc2_hboot_test.s -vcs_run_args=+mbist_mode=7 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=4 -max_cycle=13000
70
71mbist_user_mb0_dta_LP spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=5 -max_cycle=8000 -vcs_run_args=+user_loop_mode=1 -vcs_run_args=+user_loop_count=3 -vcs_run_args=+user_addr_mode=1 -vcs_run_args=+user_start_addr=0 -vcs_run_args=+user_stop_addr=3f -vcs_run_args=+user_incr_addr=1 -vcs_run_args=+ten_n_mode=1
72mbist_user_mb1_tsa0_LP spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=0 -max_cycle=82000 -vcs_run_args=+user_loop_mode=1 -vcs_run_args=+user_loop_count=3
73mbist_user_mb2_rrf_LP spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=1 -max_cycle=2500 -vcs_run_args=+user_loop_mode=1 -vcs_run_args=+user_loop_count=3 -vcs_run_args=+user_addr_mode=1 -vcs_run_args=+user_start_addr=3 -vcs_run_args=+user_stop_addr=1b -vcs_run_args=+user_incr_addr=4
74
75mbist_ubisi_mb0_lru_LP spc2_hboot_test.s -vcs_run_args=+mbist_mode=7 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=b -max_cycle=3100 -vcs_run_args=+user_loop_mode=1 -vcs_run_args=+user_loop_count=10
76mbist_ubisi_mb1_scp1_LP spc2_hboot_test.s -vcs_run_args=+mbist_mode=7 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=4 -max_cycle=1800 -vcs_run_args=+user_loop_mode=1 -vcs_run_args=+user_loop_count=10 -vcs_run_args=+user_addr_mode=1 -vcs_run_args=+user_start_addr=0 -vcs_run_args=+user_stop_addr=1f -vcs_run_args=+user_incr_addr=1
77mbist_ubisi_mb2_frf_LP spc2_hboot_test.s -vcs_run_args=+mbist_mode=7 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=5 -max_cycle=6000 -vcs_run_args=+user_loop_mode=1 -vcs_run_args=+user_loop_count=10 -vcs_run_args=+user_data_mode=1 -vcs_run_args=+user_data=be
78
79
80mbist_user_mb0_ict spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=0 -max_cycle=87000
81mbist_user_mb0_icv spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=2 -max_cycle=6000
82mbist_user_mb0_itb spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=3 -max_cycle=45000
83mbist_user_mb0_dca spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=4 -max_cycle=174000
84mbist_user_mb0_dta spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=5 -max_cycle=87000
85mbist_user_mb0_dva spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=6 -max_cycle=6000
86mbist_user_mb0_dtlb spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=7 -max_cycle=46000
87mbist_user_mb0_cpq spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=8 -max_cycle=12000
88mbist_user_mb0_stbcam spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=9 -max_cycle=12000
89mbist_user_mb0_stbram spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=a -max_cycle=34000
90mbist_user_mb0_lru spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=b -max_cycle=22000
91
92mbist_user_mb1_tsa0 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=0 -max_cycle=28000
93mbist_user_mb1_tsa1 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=1 -max_cycle=28000
94mbist_user_mb1_tca spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=2 -max_cycle=17000
95mbist_user_mb1_scp0 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=3 -max_cycle=17000
96mbist_user_mb1_scp1 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=4 -max_cycle=17000
97mbist_user_mb1_mra0 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=5 -max_cycle=23000
98mbist_user_mb1_mra1 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=6 -max_cycle=23000
99
100mbist_user_mb2_arf spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=0 -max_cycle=6000
101mbist_user_mb2_rrf spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=1 -max_cycle=12000
102mbist_user_mb2_mam spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=2 -max_cycle=28000
103mbist_user_mb2_irf spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=3 -max_cycle=23000
104mbist_user_mb2_frf spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=5 -max_cycle=45000
105
106
107mbist_user_mb0_ict_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=0 -max_cycle=87000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=36864 -vcs_run_args=+mbist_force_array=0002000
108mbist_user_mb0_icv_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=2 -max_cycle=6000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=2304 -vcs_run_args=+mbist_force_array=0008000
109mbist_user_mb0_itb_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=3 -max_cycle=46000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=18432 -vcs_run_args=+mbist_force_array=0010000
110mbist_user_mb0_dca_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=4 -max_cycle=174000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=73728 -vcs_run_args=+mbist_force_array=0020000
111mbist_user_mb0_dta_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=5 -max_cycle=87000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=36864 -vcs_run_args=+mbist_force_array=0040000
112mbist_user_mb0_dva_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=6 -max_cycle=6000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=2304 -vcs_run_args=+mbist_force_array=0080000
113mbist_user_mb0_dtlb_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=7 -max_cycle=46000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=18432 -vcs_run_args=+mbist_force_array=0100000
114mbist_user_mb0_cpq_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=8 -max_cycle=12000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=4608 -vcs_run_args=+mbist_force_array=0200000
115mbist_user_mb0_stbcam_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=9 -max_cycle=12000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=4608 -vcs_run_args=+mbist_force_array=0400000
116mbist_user_mb0_stbram_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=a -max_cycle=34000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=12672 -vcs_run_args=+mbist_force_array=0800000
117mbist_user_mb0_lru_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_array=b -max_cycle=22000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=6912 -vcs_run_args=+mbist_force_array=1000000
118
119
120mbist_user_mb1_tsa0_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=0 -max_cycle=28000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=11520 -vcs_run_args=+mbist_force_array=0000040
121mbist_user_mb1_tsa1_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=1 -max_cycle=28000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=11520 -vcs_run_args=+mbist_force_array=0000080
122mbist_user_mb1_tca_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=2 -max_cycle=17000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=6912 -vcs_run_args=+mbist_force_array=0000100
123mbist_user_mb1_scp0_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=3 -max_cycle=17000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=6912 -vcs_run_args=+mbist_force_array=0000200
124mbist_user_mb1_scp1_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=4 -max_cycle=17000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=6912 -vcs_run_args=+mbist_force_array=0000400
125mbist_user_mb1_mra0_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=5 -max_cycle=23000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=8640 -vcs_run_args=+mbist_force_array=0000800
126mbist_user_mb1_mra1_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=010 -vcs_run_args=+user_array=6 -max_cycle=23000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=8640 -vcs_run_args=+mbist_force_array=0001000
127
128mbist_user_mb2_arf_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=0 -max_cycle=6000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=2304 -vcs_run_args=+mbist_force_array=0000001
129mbist_user_mb2_rrf_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=1 -max_cycle=12000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=4608 -vcs_run_args=+mbist_force_array=0000002
130mbist_user_mb2_mam_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=2 -max_cycle=28000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=11520 -vcs_run_args=+mbist_force_array=0000004
131mbist_user_mb2_irf_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=3 -max_cycle=23000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=8960 -vcs_run_args=+mbist_force_array=0000008
132mbist_user_mb2_frf_err spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=100 -vcs_run_args=+user_array=5 -max_cycle=45000 -vcs_run_args=+mbist_errinj -vcs_run_args=+mbist_fail_count=18432 -vcs_run_args=+mbist_force_array=0000020
133
134
135
136cbist_user_dtlb_ctest0 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=0 -max_cycle=825
137cbist_user_dtlb_ctest1 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=1 -max_cycle=825
138cbist_user_dtlb_ctest2 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=2 -max_cycle=825
139cbist_user_dtlb_ctest3 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=3 -max_cycle=825
140cbist_user_dtlb_ctest4 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=4 -max_cycle=825
141cbist_user_dtlb_ctest5 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=5 -max_cycle=825
142cbist_user_dtlb_ctest6 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=6 -max_cycle=575
143cbist_user_dtlb_ctest7 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=7 -max_cycle=575
144cbist_user_dtlb_ctest8 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=8 -max_cycle=575
145cbist_user_dtlb_ctest9 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=9 -max_cycle=575
146cbist_user_dtlb_ctest10 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=a -max_cycle=1000
147cbist_user_dtlb_ctest11 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=b -max_cycle=1250
148cbist_user_dtlb_ctest12 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=c -max_cycle=1600
149cbist_user_dtlb_ctest13 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=0 -vcs_run_args=+user_cam_test_sel=d -max_cycle=70000
150
151cbist_user_itlb_ctest0 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=0 -max_cycle=550
152cbist_user_itlb_ctest1 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=1 -max_cycle=550
153cbist_user_itlb_ctest2 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=2 -max_cycle=550
154cbist_user_itlb_ctest3 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=3 -max_cycle=550
155cbist_user_itlb_ctest4 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=4 -max_cycle=550
156cbist_user_itlb_ctest5 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=5 -max_cycle=550
157cbist_user_itlb_ctest6 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=6 -max_cycle=375
158cbist_user_itlb_ctest7 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=7 -max_cycle=375
159cbist_user_itlb_ctest8 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=8 -max_cycle=375
160cbist_user_itlb_ctest9 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=9 -max_cycle=375
161cbist_user_itlb_ctest10 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=a -max_cycle=575
162cbist_user_itlb_ctest11 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=b -max_cycle=375
163cbist_user_itlb_ctest12 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=c -max_cycle=1000
164cbist_user_itlb_ctest13 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=1 -vcs_run_args=+user_cam_test_sel=d -max_cycle=17000
165
166cbist_user_stb_ctest0 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=0 -max_cycle=400
167cbist_user_stb_ctest1 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=1 -max_cycle=425
168cbist_user_stb_ctest2 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=2 -max_cycle=425
169cbist_user_stb_ctest3 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=3 -max_cycle=425
170cbist_user_stb_ctest4 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=4 -max_cycle=425
171cbist_user_stb_ctest5 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=5 -max_cycle=425
172cbist_user_stb_ctest6 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=6 -max_cycle=775
173cbist_user_stb_ctest7 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=7 -max_cycle=325
174cbist_user_stb_ctest8 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=8 -max_cycle=1800
175cbist_user_stb_ctest9 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=9 -max_cycle=375
176cbist_user_stb_ctest10 spc2_hboot_test.s -vcs_run_args=+mbist_mode=5 -vcs_run_args=+mb_enable=001 -vcs_run_args=+user_cam_mode=1 -vcs_run_args=+user_cam_sel=2 -vcs_run_args=+user_cam_test_sel=a -max_cycle=3000
177
178</core_mbist_fast>
179
180</spc_secondary_nightly>
181</spc_secondary_all>
182
183</runargs>
184</core_mbist>
185</spc2_mbist>
Full OpenSPARC design & verification tarball including full HDL.