projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / mss / mcu_dimm_cfg_1c1r.diaglist
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcu_dimm_cfg_1c1r.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef SYSNAME
36# ifdef FC8
37// // FC8 parameters
38# define SYSNAME fc8
39# define sys(x) mss_fc8_ ## x
40# else
41// // FC1 parameters
42# define SYSNAME fc1
43# define sys(x) mss_fc1_ ## x
44# endif
45#endif
46//
47#ifdef SETMODREL
48# define MODREL_1c1r -vcs_rel_name=fc1_dimm8_1rank_sng
49#else
50# define MODREL_1c1r
51#endif
52//
53//==============================================================================
54//
55<sys(dimmCfg_1c1r) name=sys(dimmCfg_1c1r)>
56//
57//==============================================================================
58<sys(build_dimmCfg_1c1r) sys=SYSNAME -sunv_run -vcs_build -zeroIn_build -config_rtl=ZIN_USE_CORE_CHECKERS -vcs_build_args=+define+DEBUG_PIPE -vcs_build_args=+define+FBDIMM_NUM_8 -vcs_build_args=+define+SNG_CHANNEL>
59//
60//==============================================================================
61//
62<runargs -vcs_run -sas -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DPART_0_BASE=0x80000000 -vcs_run_args=+l2esr_mon_off -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+noDebugChecks -max_cycle=+10000000 -vcs_run_args=+TIMEOUT=250000 -rtl_timeout=100000000 -vcs_run_args=+th_timeout=100000000 -vcs_run_args=+skt_timeout=100000000 -tg_seed=1 -midas_args=-DDISABLE_ALL_CACHES -vcs_run_args=+SNG_CHANNEL -drm_freeram=2000 -drm_freeswap=2000 -drm_type=rgrs -regress MODREL_1c1r -nosaslog -midas_args=-DHBOOT_HV_ONLY -vcs_run_args=+err_chkrs_off -vcs_run_args=+PEU_TEST>
63//
64//==============================================================================
65//
66indra_mcu_1c1r_Dma0Cac0Mcu1Tog0_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu1Tog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+2_FBDIMMS -vcs_run_args=+DIMM_SIZE_512
67indra_mcu_1c1r_Dma0Cac0Mcu1Tog1_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu1Tog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_2G
68indra_mcu_1c1r_Dma0Cac0Mcu1Tog2_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu1Tog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+2_FBDIMMS -vcs_run_args=+DIMM_SIZE_2G
69indra_mcu_1c1r_Dma0Cac0Mcu1Tog3_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu1Tog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G
70indra_mcu_1c1r_Dma0Cac0Mcu2Tog0_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu2Tog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_2G
71indra_mcu_1c1r_Dma0Cac0Mcu2Tog1_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu2Tog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_1G
72indra_mcu_1c1r_Dma0Cac0Mcu2Tog2_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu2Tog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_2G
73indra_mcu_1c1r_Dma0Cac0Mcu2Tog3_rand_0 indra_mcu_1c1r_Dma0Cac0Mcu2Tog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G
74indra_mcu_1c1r_Dma0Cac0McurTog0_rand_0 indra_mcu_1c1r_Dma0Cac0McurTog0_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+8_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G
75indra_mcu_1c1r_Dma0Cac0McurTog1_rand_0 indra_mcu_1c1r_Dma0Cac0McurTog1_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+1_FBDIMM -vcs_run_args=+DIMM_SIZE_512
76indra_mcu_1c1r_Dma0Cac0McurTog2_rand_0 indra_mcu_1c1r_Dma0Cac0McurTog2_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_HIGH -vcs_run_args=+8_FBDIMMS -vcs_run_args=+DIMM_SIZE_512
77indra_mcu_1c1r_Dma0Cac0McurTog3_rand_0 indra_mcu_1c1r_Dma0Cac0McurTog3_rand_0.s -vcs_run_args=+SNG_CHANNEL -vcs_run_args=+RANK_LOW -vcs_run_args=+4_FBDIMMS -vcs_run_args=+DIMM_SIZE_1G
78//
79// =========================================================================================
80//
81</runargs>
82//
83//==============================================================================
84//
85<runargs -vcs_run -sas -midas_args=-DCMP_THREAD_START=ALL -finish_mask=all -midas_args=-DPART_0_BASE=0x80000000 -vcs_run_args=+l2esr_mon_off -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+noDebugChecks -max_cycle=+10000000 -vcs_run_args=+TIMEOUT=250000 -rtl_timeout=100000000 -vcs_run_args=+th_timeout=100000000 -vcs_run_args=+skt_timeout=100000000 -tg_seed=1 -midas_args=-DDISABLE_ALL_CACHES -vcs_run_args=+SNG_CHANNEL -drm_freeram=2000 -drm_freeswap=2000 -drm_type=rgrs -regress MODREL_1c1r>
86//==============================================================================
87//
88// 18 diags generated from MPGen
89
90mpgen_1ch_hi_2g_1r_4fb mpgen_1ch_hi_2g_1r_4fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+4_FBDIMMS
91mpgen_1ch_hi_2g_1r_2fb mpgen_1ch_hi_2g_1r_2fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+2_FBDIMMS
92mpgen_1ch_hi_2g_1r_1fb mpgen_1ch_hi_2g_1r_1fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+1_FBDIMM
93mpgen_1ch_hi_1g_1r_4fb mpgen_1ch_hi_1g_1r_4fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+4_FBDIMMS
94mpgen_1ch_hi_1g_1r_2fb mpgen_1ch_hi_1g_1r_2fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+2_FBDIMMS
95mpgen_1ch_hi_1g_1r_1fb mpgen_1ch_hi_1g_1r_1fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+1_FBDIMM
96mpgen_1ch_hi_0g_1r_4fb mpgen_1ch_hi_0g_1r_4fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+4_FBDIMMS
97mpgen_1ch_hi_0g_1r_2fb mpgen_1ch_hi_0g_1r_2fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+2_FBDIMMS
98mpgen_1ch_hi_0g_1r_1fb mpgen_1ch_hi_0g_1r_1fb.s -vcs_run_args=+RANK_HIGH -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+1_FBDIMM
99mpgen_1ch_lo_2g_1r_4fb mpgen_1ch_lo_2g_1r_4fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+4_FBDIMMS
100mpgen_1ch_lo_2g_1r_2fb mpgen_1ch_lo_2g_1r_2fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+2_FBDIMMS
101mpgen_1ch_lo_2g_1r_1fb mpgen_1ch_lo_2g_1r_1fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_2G -vcs_run_args=+1_FBDIMM
102mpgen_1ch_lo_1g_1r_4fb mpgen_1ch_lo_1g_1r_4fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+4_FBDIMMS
103mpgen_1ch_lo_1g_1r_2fb mpgen_1ch_lo_1g_1r_2fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+2_FBDIMMS
104mpgen_1ch_lo_1g_1r_1fb mpgen_1ch_lo_1g_1r_1fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_1G -vcs_run_args=+1_FBDIMM
105mpgen_1ch_lo_0g_1r_4fb mpgen_1ch_lo_0g_1r_4fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+4_FBDIMMS
106mpgen_1ch_lo_0g_1r_2fb mpgen_1ch_lo_0g_1r_2fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+2_FBDIMMS
107mpgen_1ch_lo_0g_1r_1fb mpgen_1ch_lo_0g_1r_1fb.s -vcs_run_args=+RANK_LOW -vcs_run_args=+DIMM_SIZE_512 -vcs_run_args=+1_FBDIMM
108
109</runargs>
110
111</sys(build_dimmCfg_1c1r)>
112
113</sys(dimmCfg_1c1r)>
114
115//==============================================================================
Full OpenSPARC design & verification tarball including full HDL.