Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / tlu / tlu.diaglist
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: tlu.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<sys(tlu)>
36
37<runargs -vcs_run_args=+noredwdrkill>
38//--------------------------------LONG-------------------------------------
39<sys(tlu_long) name=sys(tlu_long)>
40// Longer Diags ..
41// MultiThread
42<sys(all)>
43<sys(all_T2)>
44
45#if (! defined FC)
46<runargs -vcs_run_args=+thread=all>
47#endif
48
49#if (defined FC)
50<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
51#endif
52
53 tlu_rand01_ind_02 tlu_rand01_ind_02.s
54
55 tlu_rand02_ind_07 tlu_rand02_ind_07.s
56
57 tlu_rand02_ind_08 tlu_rand02_ind_08.s
58 tlu_rand02_ind_09 tlu_rand02_ind_09.s
59 tlu_rand02_ind_10 tlu_rand02_ind_10.s
60
61 // For long running diags in FC.
62
63#if( !defined FC)
64
65 tlu_rand03_ind_03 tlu_rand03_ind_03.s
66 tlu_rand03_ind_04 tlu_rand03_ind_04.s
67 tlu_rand03_ind_07 tlu_rand03_ind_07.s
68 tlu_rand03_ind_08 tlu_rand03_ind_08.s
69 tlu_rand03_ind_05 tlu_rand03_ind_05.s
70 tlu_rand03_ind_06 tlu_rand03_ind_06.s
71 tlu_rand03_ind_09 tlu_rand03_ind_09.s
72
73#endif
74
75#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)
76
77 tlu_rand04_ind_02 tlu_rand04_ind_02.s
78 tlu_rand04_ind_03 tlu_rand04_ind_03.s
79 tlu_rand04_ind_04 tlu_rand04_ind_04.s
80
81 tlu_rand04_ind_19 tlu_rand04_ind_19.s
82 tlu_rand04_ind_21 tlu_rand04_ind_21.s
83 tlu_rand04_ind_22 tlu_rand04_ind_22.s
84
85// TLU rand5 diags use user events .
86
87<sys(nightly)>
88
89#if (defined SPC)
90<sys(tlu_ras)>
91 tlu_rand05_ind_04_08_9 tlu_rand05_ind_04_08_9.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on
92 tlu_rand05_ind_04_08_10 tlu_rand05_ind_04_08_10.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_stb_on
93 tlu_rand05_ind_04_15_1 tlu_rand05_ind_04_15_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on
94 tlu_rand05_ind_04_27_1 tlu_rand05_ind_04_27_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_sca_on
95 tlu_rand05_ind_04_27_3 tlu_rand05_ind_04_27_3.s -vcs_run_args=+err_sync_on
96 tlu_rand05_ind_05_02_5 tlu_rand05_ind_05_02_5.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_sca_on
97 tlu_rand05_ind_05_02_8 tlu_rand05_ind_05_02_8.s -vcs_run_args=+err_sync_on
98 tlu_rand05_ind_05_03_1 tlu_rand05_ind_05_03_1.s
99 tlu_rand05_ind_05_11_3 tlu_rand05_ind_05_11_3.s -vcs_run_args=+err_sync_on
100 tlu_rand05_ind_05_19_1 tlu_rand05_ind_05_19_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
101 tlu_rand05_ind_06_10_4 tlu_rand05_ind_06_10_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
102 tlu_rand05_ind_06_14_10 tlu_rand05_ind_06_14_10.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_itlb_on
103 tlu_rand05_ind_06_17_3 tlu_rand05_ind_06_17_3.s -vcs_run_args=+err_sync_on
104 tlu_rand05_ind_06_20_9 tlu_rand05_ind_06_20_9.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
105 tlu_rand05_ind_06_27_5 tlu_rand05_ind_06_27_5.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
106 tlu_rand05_ind_06_20_6 tlu_rand05_ind_06_20_6.s -vcs_run_args=+err_ic_on
107 tlu_rand05_ind_07_28_1 tlu_rand05_ind_07_28_1.s -vcs_run_args=+err_sync_on
108 tlu_rand05_ind_07_28_3 tlu_rand05_ind_07_28_3.s -vcs_run_args=+err_sync_on
109 tlu_rand05_ind_08_01_3 tlu_rand05_ind_08_01_3.s -vcs_run_args=+err_sync_on
110 tlu_rand05_ind_08_04_5 tlu_rand05_ind_08_04_5.s -vcs_run_args=+err_sync_on
111 tlu_rand05_ind_08_04_6 tlu_rand05_ind_08_04_6.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_tcc_on
112 tlu_rand05_ind_08_04_2 tlu_rand05_ind_08_04_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
113 tlu_rand05_ind_08_05_3 tlu_rand05_ind_08_05_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on
114 tlu_rand05_ind_08_17_5 tlu_rand05_ind_08_17_5.s -vcs_run_args=+err_sync_on
115 tlu_rand05_ind_08_22_1 tlu_rand05_ind_08_22_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_stb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
116 tlu_rand05_ind_08_22_4 tlu_rand05_ind_08_22_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
117 tlu_rand05_ind_08_29_7 tlu_rand05_ind_08_29_7.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_stb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
118 tlu_rand05_ind_08_31_1 tlu_rand05_ind_08_31_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_stb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
119 tlu_rand05_ind_08_31_2 tlu_rand05_ind_08_31_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_sca_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_stb_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on
120 tlu_rand05_ind_08_31_5 tlu_rand05_ind_08_31_5.s -vcs_run_args=+err_sync_on
121 tlu_rand05_ind_08_31_6 tlu_rand05_ind_08_31_6.s -vcs_run_args=+err_sync_on
122 tlu_rand05_ind_09_01_3 tlu_rand05_ind_09_01_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on
123 tlu_rand05_ind_09_01_4 tlu_rand05_ind_09_01_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on
124 tlu_rand05_ind_09_02_1 tlu_rand05_ind_09_02_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on
125 tlu_rand05_ind_09_02_2 tlu_rand05_ind_09_02_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on
126 tlu_rand05_ind_09_07_5 tlu_rand05_ind_09_07_5.s -vcs_run_args=+err_sync_on
127 tlu_rand05_ind_09_08_7 tlu_rand05_ind_09_08_7.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on -vcs_run_args=+dsfsr_chkr_on
128 tlu_rand05_ind_09_09_1 tlu_rand05_ind_09_09_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on -vcs_run_args=+dsfsr_chkr_on
129 tlu_rand05_ind_09_15_6 tlu_rand05_ind_09_15_6.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_ic_on -vcs_run_args=+dsfsr_chkr_on
130 tlu_rand05_ind_09_20_4 tlu_rand05_ind_09_20_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
131 tlu_rand05_ind_09_22_1 tlu_rand05_ind_09_22_1.s -vcs_run_args=+ssModeFreq=2200
132 tlu_rand05_ind_09_22_2 tlu_rand05_ind_09_22_2.s -vcs_run_args=+ssModeFreq=2200 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on -vcs_run_args=+err_dsfsr_chkr_on
133 tlu_rand05_ind_09_26_1 tlu_rand05_ind_09_26_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on -vcs_run_args=+ssModeFreq=2200 -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on
134 tlu_rand05_ind_09_26_3 tlu_rand05_ind_09_26_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
135 tlu_rand05_ind_09_26_4 tlu_rand05_ind_09_26_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
136 tlu_rand05_ind_09_27_1 tlu_rand05_ind_09_27_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on -vcs_run_args=+ssModeFreq=2200 -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on
137 tlu_rand05_ind_09_27_3 tlu_rand05_ind_09_27_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
138 tlu_rand05_ind_09_27_4 tlu_rand05_ind_09_27_4.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
139 tlu_rand05_ind_09_29_1 tlu_rand05_ind_09_29_1.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on -vcs_run_args=+doModeFreq=2200 -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on
140 tlu_rand05_ind_09_29_2 tlu_rand05_ind_09_29_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
141 tlu_rand05_ind_09_29_3 tlu_rand05_ind_09_29_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_itlb_on -vcs_run_args=+dsfsr_chkr_on
142 tlu_rand05_ind_09_29_5 tlu_rand05_ind_09_29_5.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+dsfsr_chkr_on
143 tlu_rand05_ind_09_29_7 tlu_rand05_ind_09_29_7.s -vcs_run_args=+err_sync_on -vcs_run_args=+dsfsr_chkr_on
144 tlu_rand05_ind_10_04_3 tlu_rand05_ind_10_04_3.s -vcs_run_args=+ssModeFreq=2000 -vcs_run_args=+ssModeMaxSessions=100 -vcs_run_args=+ssModeMin=1000 -vcs_run_args=+ssModeMax=1500 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on -vcs_run_args=+err_dsfsr_chkr_on
145 tlu_rand05_ind_10_04_4 tlu_rand05_ind_10_04_4.s -vcs_run_args=+doModeFreq=2200 -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on -vcs_run_args=+err_dtlb_on -vcs_run_args=+err_itlb_on -vcs_run_args=+err_frf_on -vcs_run_args=+err_ic_on -vcs_run_args=+err_dsfsr_chkr_on
146 tlu_rand05_ind_10_13_1 tlu_rand05_ind_10_13_1.s -vcs_run_args=+err_sync_on
147 tlu_rand05_ind_10_31_3 tlu_rand05_ind_10_31_3.s -vcs_run_args=+err_sync_on
148 tlu_rand05_ind_11_13 tlu_rand05_ind_11_13.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_frf_on
149 tlu_rand05_ind_11_27 tlu_rand05_ind_11_27.s -vcs_run_args=+err_sync_on -midas_args=-DCREGS_LSU_CTL_REG_DC=0
150
151 tlu_trap_state_ind_01_31_1 tlu_trap_state_ind_01_31_1.s
152 tlu_trap_state_ind_01_31_2 tlu_trap_state_ind_01_31_2.s
153 tlu_trap_state_ind_01_31_3 tlu_trap_state_ind_01_31_3.s
154 bug_112121_case3 bug_112121_case3.s
155 bug_112121_case2 bug_112121_case2.s
156 bug_112121_case1 bug_112121_case1.s
157</runargs> // -vcs_run_args=+thread=all
158
159<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off>
160 err_tcc_hstick_diag err_tcc_hstick_diag.s -vcs_run_args=+thread=01
161 err_tcc_hstick_diag_1 err_tcc_hstick_diag.s -vcs_run_args=+thread=02
162 err_tcc_hstick_diag_2 err_tcc_hstick_diag.s -vcs_run_args=+thread=04
163 err_tcc_hstick_diag_3 err_tcc_hstick_diag.s -vcs_run_args=+thread=08
164 err_tcc_hstick_diag_4 err_tcc_hstick_diag.s -vcs_run_args=+thread=10
165 err_tcc_hstick_diag_5 err_tcc_hstick_diag.s -vcs_run_args=+thread=20
166 err_tcc_hstick_diag_6 err_tcc_hstick_diag.s -vcs_run_args=+thread=40
167 err_tcc_hstick_diag_7 err_tcc_hstick_diag.s -vcs_run_args=+thread=80
168
169 err_tcc_stick_diag err_tcc_stick_diag.s -vcs_run_args=+thread=01
170 err_tcc_stick_diag_1 err_tcc_stick_diag.s -vcs_run_args=+thread=02
171 err_tcc_stick_diag_2 err_tcc_stick_diag.s -vcs_run_args=+thread=04
172 err_tcc_stick_diag_3 err_tcc_stick_diag.s -vcs_run_args=+thread=08
173 err_tcc_stick_diag_4 err_tcc_stick_diag.s -vcs_run_args=+thread=10
174 err_tcc_stick_diag_5 err_tcc_stick_diag.s -vcs_run_args=+thread=20
175 err_tcc_stick_diag_6 err_tcc_stick_diag.s -vcs_run_args=+thread=40
176 err_tcc_stick_diag_7 err_tcc_stick_diag.s -vcs_run_args=+thread=80
177
178 err_tcc_tick_diag err_tcc_tick_diag.s -vcs_run_args=+thread=01
179 err_tcc_tick_diag_1 err_tcc_tick_diag.s -vcs_run_args=+thread=02
180 err_tcc_tick_diag_2 err_tcc_tick_diag.s -vcs_run_args=+thread=04
181 err_tcc_tick_diag_3 err_tcc_tick_diag.s -vcs_run_args=+thread=08
182 err_tcc_tick_diag_4 err_tcc_tick_diag.s -vcs_run_args=+thread=10
183 err_tcc_tick_diag_5 err_tcc_tick_diag.s -vcs_run_args=+thread=20
184 err_tcc_tick_diag_6 err_tcc_tick_diag.s -vcs_run_args=+thread=40
185 err_tcc_tick_diag_7 err_tcc_tick_diag.s -vcs_run_args=+thread=80
186
187 err_inj_mondo_diag err_inj_mondo_diag.s -vcs_run_args=+thread=01
188 err_inj_mondo_diag_1 err_inj_mondo_diag.s -vcs_run_args=+thread=02
189 err_inj_mondo_diag_2 err_inj_mondo_diag.s -vcs_run_args=+thread=04
190 err_inj_mondo_diag_3 err_inj_mondo_diag.s -vcs_run_args=+thread=08
191 err_inj_mondo_diag_4 err_inj_mondo_diag.s -vcs_run_args=+thread=10
192 err_inj_mondo_diag_5 err_inj_mondo_diag.s -vcs_run_args=+thread=20
193 err_inj_mondo_diag_6 err_inj_mondo_diag.s -vcs_run_args=+thread=40
194 err_inj_mondo_diag_7 err_inj_mondo_diag.s -vcs_run_args=+thread=80
195
196 err_tsa_diag err_tsa_diag.s -vcs_run_args=+thread=01
197 err_tsa_diag_1 err_tsa_diag.s -vcs_run_args=+thread=02
198 err_tsa_diag_2 err_tsa_diag.s -vcs_run_args=+thread=04
199 err_tsa_diag_3 err_tsa_diag.s -vcs_run_args=+thread=08
200 err_tsa_diag_4 err_tsa_diag.s -vcs_run_args=+thread=10
201 err_tsa_diag_5 err_tsa_diag.s -vcs_run_args=+thread=20
202 err_tsa_diag_6 err_tsa_diag.s -vcs_run_args=+thread=40
203 err_tsa_diag_7 err_tsa_diag.s -vcs_run_args=+thread=80
204 err_ittp_bug_103663 err_ittp_bug_103663.s -vcs_run_args=+thread=01
205
206 err_hstick_cmpr_cycle err_hstick_cmpr_cycle.s -vcs_run_args=+thread=01
207 err_hstick_cmpr_cycle_1 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=02
208 err_hstick_cmpr_cycle_2 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=04
209 err_hstick_cmpr_cycle_3 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=08
210 err_hstick_cmpr_cycle_4 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=10
211 err_hstick_cmpr_cycle_5 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=20
212 err_hstick_cmpr_cycle_6 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=40
213 err_hstick_cmpr_cycle_7 err_hstick_cmpr_cycle.s -vcs_run_args=+thread=80
214
215 err_stick_cmpr_cycle err_stick_cmpr_cycle.s -vcs_run_args=+thread=01
216 err_stick_cmpr_cycle_1 err_stick_cmpr_cycle.s -vcs_run_args=+thread=02
217 err_stick_cmpr_cycle_2 err_stick_cmpr_cycle.s -vcs_run_args=+thread=04
218 err_stick_cmpr_cycle_3 err_stick_cmpr_cycle.s -vcs_run_args=+thread=08
219 err_stick_cmpr_cycle_4 err_stick_cmpr_cycle.s -vcs_run_args=+thread=10
220 err_stick_cmpr_cycle_5 err_stick_cmpr_cycle.s -vcs_run_args=+thread=20
221 err_stick_cmpr_cycle_6 err_stick_cmpr_cycle.s -vcs_run_args=+thread=40
222 err_stick_cmpr_cycle_7 err_stick_cmpr_cycle.s -vcs_run_args=+thread=80
223
224 err_tick_cmpr_cycle_c0_n2 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=01
225 err_tick_cmpr_cycle_c0_n2_1 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=02
226 err_tick_cmpr_cycle_c0_n2_2 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=04
227 err_tick_cmpr_cycle_c0_n2_3 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=08
228 err_tick_cmpr_cycle_c0_n2_4 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=10
229 err_tick_cmpr_cycle_c0_n2_5 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=20
230 err_tick_cmpr_cycle_c0_n2_6 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=40
231 err_tick_cmpr_cycle_c0_n2_7 err_tick_cmpr_cycle_c0_n2.s -vcs_run_args=+thread=80
232
233 err_tick_cmpr_cycle_c1_n2 err_tick_cmpr_cycle_c1_n2.s -vcs_run_args=+thread=01
234
235 err_tick_cmpr_ue_n2 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=01
236 err_tick_cmpr_ue_n2_1 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=02
237 err_tick_cmpr_ue_n2_2 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=04
238 err_tick_cmpr_ue_n2_3 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=08
239 err_tick_cmpr_ue_n2_4 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=10
240 err_tick_cmpr_ue_n2_5 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=20
241 err_tick_cmpr_ue_n2_6 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=40
242 err_tick_cmpr_ue_n2_7 err_tick_cmpr_ue_n2.s -vcs_run_args=+thread=80
243
244
245
246 //err_hstick_cmpr_ue_n2 err_hstick_cmpr_ue_n2.s -vcs_run_args=+thread=01
247 //err_stick_cmpr_ue_n2 err_stick_cmpr_ue_n2.s -vcs_run_args=+thread=01
248 //err_stick_cmpr_diag_n2 err_stick_cmpr_diag_n2.s -vcs_run_args=+thread=01
249</runargs>
250
251#if (! defined FC)
252<runargs -vcs_run_args=+thread=all>
253#endif
254
255#if (defined FC)
256<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
257#endif
258
259</sys(tlu_ras)>
260#endif
261
262
263
264#if (defined SPC || defined CMP)
265
266 tlu_rand05_ind_10_11_8 tlu_rand05_ind_10_11_8.s
267
268// tlu_rand05_ind_85 tlu_rand05_ind_85.s
269// tlu_rand05_ind_88 tlu_rand05_ind_88.s
270// tlu_rand05_ind_89 tlu_rand05_ind_89.s
271// tlu_rand5_7745150 tlu_rand5_7745150.s
272
273#if (defined SPC)
274 tlu_rand05_ind_89_1 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=1
275 tlu_rand05_ind_89_2 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=2
276 tlu_rand05_ind_89_3 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=3
277 tlu_rand05_ind_89_4 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=4
278 tlu_rand05_ind_89_5 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=5
279 tlu_rand05_ind_89_6 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=6
280 tlu_rand05_ind_89_7 tlu_rand05_ind_89.s -vcs_run_args=+tlu_sscan_shscanid=7
281
282 tlu_rand5_nocmp_8130761 tlu_rand5_nocmp_8130761.s
283
284 tlu_rand5_nocmp_8257449 tlu_rand5_nocmp_8257449.s -midas_args=-DMULTIPASS=1 -vcs_run_args=+ssModeFreq=2200 -max_cycle 1500000 -vcs_run_args=+ssModeFreq=2000 -vcs_run_args=+ssModeMaxSessions=75 -vcs_run_args=+ssModeInterleaveWeight=40 -vcs_run_args=+doModeFreq=2000 -vcs_run_args=+doModeMaxSessions=100 -vcs_run_args=+doModeLenMin=3000 -vcs_run_args=+softStopFreq=2000 -vcs_run_args=+softStopMaxSessions=20 -vcs_run_args=+softStopLenMax=50
285 tlu_rand05_nocmp_20050919 tlu_rand05_nocmp_20050919.s -vcs_run_args=+ssModeFreq=2200 -midas_args=-DMULTIPASS=1
286
287 tlu_rand5_7833446 tlu_rand5_7833446.s -midas_args=-DMULTIPASS=2
288 tlu_rand5_nocmp_8334648 tlu_rand5_nocmp_8334648.s -midas_args=-DMULTIPASS=1 -vcs_run_args=+doModeFreq=2200 -vcs_run_args=+doModeLenMin=300 -vcs_run_args=+doModeLenMax=1000
289
290<runargs -rtl_timeout=20000 -vcs_run_args=+th_timeout=50000 -vcs_run_args=+skt_timeout=20000 -max_cycle 1500000 -vcs_run_args=+ssModeFreq=2000 -vcs_run_args=+ssModeMaxSessions=75 -vcs_run_args=+ssModeInterleaveWeight=40 -vcs_run_args=+doModeFreq=2000 -vcs_run_args=+doModeMaxSessions=100 -vcs_run_args=+doModeLenMin=500 -vcs_run_args=+softStopFreq=2000 -vcs_run_args=+softStopMaxSessions=20 -vcs_run_args=+softStopLenMax=50 >
291
292 tlu_rand5_nocmp_8823163 tlu_rand5_nocmp_8823163.s
293 tlu_rand5_nocmp_8820184 tlu_rand5_nocmp_8820184.s
294 tlu_rand5_nocmp_8814718 tlu_rand5_nocmp_8814718.s
295</runargs>
296
297 tlu_rand05_bug_118933 tlu_rand05_bug_118933.s -vcs_run_args=+thread=all -rtl_timeout=20000 -vcs_run_args=+th_timeout=50000 -vcs_run_args=+skt_timeout=20000 -midas_args=-DMULTIPASS=0 -max_cycle 1500000 -vcs_run_args=+err_sync_on -vcs_run_args=+err_l2c_on -vcs_run_args=+err_l2c_freq=40 -midas_args=-DINC_ERR_TRAPS -vcs_run_args=+err_stb_on -vcs_run_args=+err_tcc_on
298
299 tlu_rand5spu_8687845 tlu_rand5spu_8687845.s -rtl_timeout=10000 -vcs_run_args=+th_timeout=50000 -max_cycle=1500000
300#endif
301
302// tlu_rand5err_10529315 tlu_rand5err_10529315.s -rtl_timeout=20000 -vcs_run_args=+th_timeout=50000 -vcs_run_args=+skt_timeout=20000 -midas_args=-DMULTIPASS=0 -max_cycle 2000000 -vcs_run_args=+err_sync_on -vcs_run_args=+err_stb_on -midas_args=-DINC_ERR_TRAPS
303
304#if(! defined CMP1)
305 tlu_rand5stress_10530146 tlu_rand5stress_10530146.s -rtl_timeout=2000 -vcs_run_args=+th_timeout=20000 -midas_args=-DMULTIPASS=1 -max_cycle=2000000
306#endif
307
308#if (defined SPC || defined CMP1 || defined CMP1L2X )
309
310// tlu_rand05_ind_01_15_1 tlu_rand05_ind_01_15_1.s
311// tlu_rand05_ind_01_24_3 tlu_rand05_ind_01_24_3.s
312// tlu_rand05_ind_01_28_1 tlu_rand05_ind_01_28_1.s
313// tlu_rand05_ind_12_15_3 tlu_rand05_ind_12_15_3.s
314// tlu_rand05_ind_04_27_2 tlu_rand05_ind_04_27_2.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_sca_on
315</sys(nightly)>
316// tlu_rand05_ind_34 tlu_rand05_ind_34.s
317// tlu_rand05_ind_36 tlu_rand05_ind_36.s
318// tlu_rand05_ind_37 tlu_rand05_ind_37.s
319// tlu_rand05_ind_38 tlu_rand05_ind_38.s
320// tlu_rand05_ind_41 tlu_rand05_ind_41.s
321// tlu_rand05_ind_42 tlu_rand05_ind_42.s
322// tlu_rand05_ind_53 tlu_rand05_ind_53.s
323// tlu_rand05_ind_57 tlu_rand05_ind_57.s
324// tlu_rand05_ind_60 tlu_rand05_ind_60.s
325// tlu_rand05_ind_63 tlu_rand05_ind_63.s
326<sys(nightly)>
327 tlu_swtraps tlu_swtraps.pal
328
329// tlu_rand05_ind_69 tlu_rand05_ind_69.s
330// tlu_rand05_ind_72 tlu_rand05_ind_72.s
331
332#endif
333
334#endif
335#endif
336
337
338</sys(nightly)>
339
340</sys(all_T2)>
341</sys(all)>
342
343</runargs> // -vcs_run_args=+thread=all
344
345// SingleThread
346</sys(tlu_long)>
347
348
349<sys(tlu_fast) name=sys(tlu_fast)>
350//--------------------------------FAST-------------------------------------
351// Smaller fast diags ..
352// MultiThread
353
354#if (! defined FC)
355<runargs -vcs_run_args=+thread=all>
356#endif
357
358#if (defined FC)
359<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
360#endif
361
362<sys(all)>
363<sys(all_T2)>
364<sys(nightly)>
365 tlu_allintvec1 tlu_allintvec1.s
366 tlu_allintvec2 tlu_allintvec2.s
367
368 tlu_simulint tlu_simulint.s -vcs_run_args=+err_chkrs_off
369#if (defined SPC)
370 spc_hver_minor_mask_rev_0 spc_hver_minor_mask_rev.s
371 spc_hver_minor_mask_rev_a spc_hver_minor_mask_rev.s -nosas -vcs_run_args=+hver_mask_minor_rev=10 -midas_args=-DHVER_MASK_MINOR_REV=10
372 spc_hver_minor_mask_rev_f spc_hver_minor_mask_rev.s -nosas -vcs_run_args=+hver_mask_minor_rev=15 -midas_args=-DHVER_MASK_MINOR_REV=15
373 tlu_registers_1 tlu_registers_1.pal
374 tlu_win_traps_n2 tlu_win_traps_n2.s
375 tlu_tba_htba_range tlu_tba_htba_range.s
376 tlu_ticknpt_user tlu_ticknpt_user.s
377 tlu_donret_glsat tlu_donret_glsat.s
378 tlu_vahole_101221 tlu_vahole_101221.s
379 tlu_vahole tlu_vahole.s
380 //tlu_vahole2 tlu_vahole2.s // Cases that are not implemented.
381 tlu_reset_maxtl tlu_reset_maxtl.s
382 tlu_reset_maxtl tlu_bug_103663.s
383 tlu_wr_alltl tlu_wr_alltl.s
384 tlu_hitl_priv2hpriv tlu_hitl_priv2hpriv.s // Coverage cases
385
386</sys(nightly)>
387 tlu_rand01_ind_01 tlu_rand01_ind_01.s
388 tlu_rand01_ind_03 tlu_rand01_ind_03.s
389 tlu_rand01_ind_04 tlu_rand01_ind_04.s
390 tlu_rand01_ind_05 tlu_rand01_ind_05.s
391 tlu_rand01_ind_06 tlu_rand01_ind_06.s
392 tlu_rand01_ind_07 tlu_rand01_ind_07.s
393 tlu_rand01_ind_08 tlu_rand01_ind_08.s
394
395 tlu_rand02_ind_01 tlu_rand02_ind_01.s
396 tlu_rand02_ind_03 tlu_rand02_ind_03.s
397 tlu_rand02_ind_04 tlu_rand02_ind_04.s
398 tlu_rand02_ind_05 tlu_rand02_ind_05.s
399 tlu_rand02_ind_06 tlu_rand02_ind_06.s
400
401 tlu_rand03_ind_01 tlu_rand03_ind_01.s
402
403<sys(nightly)>
404 // ECO (1.1/2.0) diags
405 tlu_stick_112960 tlu_stick_112960.s
406 tlu_queueregsiz_114417 tlu_queueregsiz_114417.s
407 tlu_tct_ret tlu_tct_ret.s
408
409// TLU ASI diags which need to sync for updates
410<runargs -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK>
411 tlu_asi_03_08_1 tlu_asi_03_08_1.s
412 tlu_asi_03_09_1 tlu_asi_03_09_1.s
413 tlu_asi_03_11_1 tlu_asi_03_11_1.s
414 tlu_asi_03_16_2 tlu_asi_03_16_2.s
415 tlu_asi_03_18_2 tlu_asi_03_18_2.s
416 tlu_asi_04_06_1 tlu_asi_04_06_1.s
417</runargs> // -vcs_run_args=+err_sync_on -midas_args=-DNOERRCHK
418
419 tlu_nonseq_retry_pdist tlu_nonseq_retry_pdist.s
420 tlu_nonseq_retry_cas tlu_nonseq_retry_cas.s
421 tlu_nonseq_retry_blk tlu_nonseq_retry_blk.s
422
423#endif
424
425#if(! defined FC)
426
427 tlu_rand04_ind_01 tlu_rand04_ind_01.s
428
429#endif
430
431#if (defined SPC || defined CMP1 || defined CMP1L2X || defined CCM1 || defined FC1 )
432
433// tlu_rand05_ind_01_05_2 tlu_rand05_ind_01_05_2.s
434 tlu_rand05_ind_01_13_1 tlu_rand05_ind_01_13_1.s
435// tlu_rand05_ind_01_15_3 tlu_rand05_ind_01_15_3.s
436// tlu_rand05_ind_01_27_4 tlu_rand05_ind_01_27_4.s
437// tlu_rand05_ind_02_08_4 tlu_rand05_ind_02_08_4.s
438// tlu_rand05_ind_03_01_1 tlu_rand05_ind_03_01_1.s
439 tlu_rand05_ind_39 tlu_rand05_ind_39.s
440 tlu_rand01_ind_09 tlu_rand01_ind_09.s
441
442// tlu_rand05_ind_39_1 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=1
443// tlu_rand05_ind_39_2 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=2
444// tlu_rand05_ind_39_3 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=3
445// tlu_rand05_ind_39_4 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=4
446// tlu_rand05_ind_39_5 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=5
447// tlu_rand05_ind_39_6 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=6
448// tlu_rand05_ind_39_7 tlu_rand05_ind_39.s -vcs_run_args=+tlu_sscan_shscanid=7
449#endif
450
451</sys(nightly)>
452</sys(all_T2)>
453</sys(all)>
454</runargs> // -vcs_run_args=+thread=all
455
456// SingleThread ONLY
457
458<sys(all)>
459<sys(all_T2)>
460
461 tlu_rand01_ind_11 tlu_rand01_ind_11.s
462
463 tlu_rand02_ind_02 tlu_rand02_ind_02.s
464
465
466#if( !defined FC)
467
468 tlu_rand03_ind_02 tlu_rand03_ind_02.s
469 tlu_rand04_ind_02 tlu_rand04_ind_02.s
470
471 tlu_rand04_ind_14 tlu_rand04_ind_14.s
472 tlu_rand04_ind_15 tlu_rand04_ind_15.s
473 tlu_rand04_ind_21 tlu_rand04_ind_21.s
474
475 tlu_rand03_ind_05 tlu_rand03_ind_05.s
476 tlu_rand03_ind_06 tlu_rand03_ind_06.s
477 tlu_rand03_ind_09 tlu_rand03_ind_09.s
478 tlu_rand04_ind_03 tlu_rand04_ind_03.s
479 tlu_rand04_ind_04 tlu_rand04_ind_04.s
480 tlu_rand04_ind_06 tlu_rand04_ind_06.s
481 tlu_rand04_ind_07 tlu_rand04_ind_07.s
482 tlu_rand04_ind_16 tlu_rand04_ind_16.s
483 tlu_rand04_ind_19 tlu_rand04_ind_19.s
484 tlu_rand04_ind_20 tlu_rand04_ind_20.s
485 tlu_rand04_ind_22 tlu_rand04_ind_22.s
486 tlu_rand04_ind_08 tlu_rand04_ind_08.s
487
488 tlu_rand04_ind_11 tlu_rand04_ind_11.s -vcs_run_args=+thread=e7
489
490 tlu_rand04_ind_11 tlu_rand04_ind_11.s -midas_args=-DCMP_THREAD_START=0xe7 -finish_mask=e7
491#endif
492
493<sys(nightly)>
494
495#if (defined SPC || defined CMP)
496
497
498#if(! defined CMP1)
499 tlu_iaw_range_1 tlu_iaw_range.s -vcs_run_args=+thread=11
500 tlu_iaw_range_2 tlu_iaw_range.s -vcs_run_args=+thread=22
501 tlu_iaw_range_3 tlu_iaw_range.s -vcs_run_args=+thread=44
502 tlu_iaw_range_4 tlu_iaw_range.s -vcs_run_args=+thread=88
503#endif
504
505#endif
506
507 tlu_107450 tlu_107450.s
508 tlu_107450_mt tlu_107450_mt.s
509
510</sys(nightly)>
511</sys(all_T2)>
512</sys(all)>
513
514
515</sys(tlu_fast)>
516
517// Disrupting Traps (Old & New)
518
519<sys(tlu_disrupting) name=tlu_disrupting>
520<sys(all)>
521<sys(all_T2)>
522<sys(nightly)>
523
524#if (defined SPC || defined CMP)
525 tlu_rand05_ind_08 tlu_rand05_ind_08.s
526 tlu_rand05_ind_10 tlu_rand05_ind_10.s
527 tlu_rand05_ind_11 tlu_rand05_ind_11.s
528 tlu_rand05_ind_12 tlu_rand05_ind_12.s
529 tlu_rand05_ind_15 tlu_rand05_ind_15.s
530 tlu_rand05_ind_16 tlu_rand05_ind_16.s
531#endif
532</sys(nightly)>
533</sys(all_T2)>
534</sys(all)>
535
536<sys(tlu_fast)>
537
538<sys(all)>
539<sys(all_T2)>
540<sys(nightly)>
541
542#if (defined SPC || defined CMP)
543
544 tlu_rand05_ind_01 tlu_rand05_ind_01.s
545 tlu_rand05_ind_02 tlu_rand05_ind_02.s
546 tlu_rand05_ind_03 tlu_rand05_ind_03.s
547 tlu_rand05_ind_04 tlu_rand05_ind_04.s
548 tlu_rand05_ind_06 tlu_rand05_ind_06.s
549 tlu_rand05_ind_07 tlu_rand05_ind_07.s
550
551 tlu_rand05_ind_01_mt tlu_rand05_ind_01.s -vcs_run_args=+thread=all
552
553 // tlu_rand05_ind_23 tlu_rand05_ind_23.s -vcs_run_args=+thread=ff
554
555 isa3_1215ivtrap2 isa3_1215ivtrap2.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
556
557#endif
558</sys(nightly)>
559</sys(all_T2)>
560</sys(all)>
561
562// OLD DIAGS from ISA3 days .. not duplicated in nightly/all
563
564#if (! defined FC)
565 isa3_1215ivtrap isa3_1215ivtrap.s -vcs_run_args=+thread=all
566 isa3_intlevel_121503 isa3_intlevel_121503.s -vcs_run_args=+thread=all
567 isa3_mondo_121503 isa3_mondo_121503.s -vcs_run_args=+thread=all
568
569 isa3_xir_121503 isa3_xir_121503.s -vcs_run_args=+thread=all -vcs_run_args=+intr_en=all -vcs_run_args=+intr_vect=3 -vcs_run_args=+intr_type=1 -vcs_run_args=+intr_wait=3000 -vcs_run_args=+intr_delay=100
570
571 isa3_1215hsysmatrap isa3_1215hsysmatrap.s -vcs_run_args=+thread=all
572 isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -vcs_run_args=+thread=1
573 isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -vcs_run_args=+thread=ff
574
575// isa3_mod_arith_int_1215_0x3d isa3_mod_arith_int_1215_0x3d.s
576 isa3_spu_cwq_trap_121503 isa3_spu_cwq_trap_121503.s -rtl_timeout=500000 -max_cycle=+5000000
577#endif
578
579#if (defined FC)
580 isa3_1215ivtrap isa3_1215ivtrap.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
581 isa3_intlevel_121503 isa3_intlevel_121503.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
582 isa3_mondo_121503 isa3_mondo_121503.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
583
584 isa3_xir_121503 isa3_xir_121503.s -midas_args=-DCMP_THREAD_START=all -vcs_run_args=+intr_en=all -vcs_run_args=+intr_vect=3 -vcs_run_args=+intr_type=1 -vcs_run_args=+intr_wait=3000 -vcs_run_args=+intr_delay=100 -finish_mask=all
585
586 isa3_1215hsysmatrap isa3_1215hsysmatrap.s -midas_args=-DCMP_THREAD_START=all -finish_mask=all
587 isa3_asi_cmp_core_1 isa3_asi_cmp_core_1.s -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1
588 isa3_asi_cmp_core_2 isa3_asi_cmp_core_2.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
589
590// isa3_mod_arith_int_1215_0x3d isa3_mod_arith_int_1215_0x3d.s
591 isa3_spu_cwq_trap_121503 isa3_spu_cwq_trap_121503.s -rtl_timeout=500000 -max_cycle=+5000000
592#endif
593
594
595</sys(tlu_fast)>
596
597
598</sys(tlu_disrupting)>
599
600
601<sys(tlu_riesling) name=sys(tlu_riesling)>
602
603#if (! defined FC)
604<runargs -vcs_run_args=+thread=all>
605#endif
606
607#if (defined FC)
608<runargs -midas_args=-DCMP_THREAD_START=all -finish_mask=all >
609#endif
610
611 tlu_rand05_ind_05_04_3 tlu_rand05_ind_05_04_3.s -vcs_run_args=+err_sync_on -vcs_run_args=+err_dc_on
612</runargs>
613</sys(tlu_riesling)>
614
615<sys(tlu_l2cerr) name=sys(tlu_l2cerr)>
616<sys(tlu_ras)>
617<runargs -vcs_run_args=+thread=all -midas_args=-DINC_ERR_TRAPS>
618err_soc_l2c_rand0 err_soc_l2c_rand0.s
619err_soc_l2c_rand1 err_soc_l2c_rand1.s
620err_soc_l2c_rand2 err_soc_l2c_rand2.s
621err_soc_l2c_rand3 err_soc_l2c_rand3.s
622err_soc_l2c_rand4 err_soc_l2c_rand4.s
623
624err_ifu_l2c_rand0 err_ifu_l2c_rand0.s
625err_ifu_l2c_rand1 err_ifu_l2c_rand1.s
626err_ifu_l2c_rand2 err_ifu_l2c_rand2.s
627err_ifu_l2c_rand3 err_ifu_l2c_rand3.s
628err_ifu_l2c_rand4 err_ifu_l2c_rand4.s
629
630err_dcu_l2c_rand0 err_dcu_l2c_rand0.s
631err_dcu_l2c_rand1 err_dcu_l2c_rand1.s
632err_dcu_l2c_rand2 err_dcu_l2c_rand2.s
633err_dcu_l2c_rand3 err_dcu_l2c_rand3.s
634err_dcu_l2c_rand4 err_dcu_l2c_rand4.s
635
636err_mmu_l2c_rand0 err_mmu_l2c_rand0.s
637err_mmu_l2c_rand1 err_mmu_l2c_rand1.s
638err_mmu_l2c_rand2 err_mmu_l2c_rand2.s
639err_mmu_l2c_rand3 err_mmu_l2c_rand3.s
640err_mmu_l2c_rand4 err_mmu_l2c_rand4.s
641</runargs>
642</sys(tlu_ras)>
643</sys(tlu_l2cerr)>
644
645<sys(all)>
646<sys(all_T2)>
647<sys(nightly)>
648<sys(tlu_halt) name=sys(tlu_halt)>
649 err_dcdp_halt err_dcdp_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
650 err_tcc_hstick_halt err_tcc_hstick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
651 err_tcc_stick_halt err_tcc_stick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
652 err_tcc_tick_halt err_tcc_tick_halt_diag.s -vcs_run_args=+thread=all -midas_args=-DNOERRCHK -vcs_run_args=+err_chkrs_off
653 tlu_halt_hstmatch tlu_halt_hstmatch.s -vcs_run_args=+thread=all
654 tlu_halt_intvec tlu_halt_intvec.s -vcs_run_args=+thread=all
655// tlu_halt_modint tlu_halt_modint.s -vcs_run_args=+thread=all
656// tlu_halt_cwqint tlu_halt_cwqint.s -vcs_run_args=+thread=all
657 tlu_halt_park tlu_halt_park.s -vcs_run_args=+thread=all
658 tlu_halt_stickint tlu_halt_stickint.s -vcs_run_args=+thread=all
659 tlu_halt_tickint tlu_halt_tickint.s -vcs_run_args=+thread=all
660 tlu_halt_xir tlu_halt_xir.s -vcs_run_args=+thread=all
661// tlu_intspu_stb_118933 tlu_intspu_stb_118933.s -vcs_run_args=thread=all
662
663#if(! defined CMP1)
664 err_dcl2c_halt err_dcl2c_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
665 err_dcl2u_halt err_dcl2u_halt_diag.s -vcs_run_args=+err_chkrs_off -nosas -midas_args=-DNOERRCHK
666 tlu_halt_modint_desr tlu_halt_modint.s -midas_args=-DINJECT_ERR
667 tlu_halt_cwqint_desr tlu_halt_cwqint.s -midas_args=-DINJECT_ERR
668#endif
669
670</sys(tlu_halt)>
671</sys(nightly)>
672</sys(all_T2)>
673</sys(all)>
674</runargs>
675</sys(tlu)>
676
677