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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / fc8.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc8.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef SYSNAME
36#define SYSNAME fc8
37#define sys(x) fc8_ ## x
38#define FC
39#define FC8
40#define ALL_THREADS 64
41#endif
42
43
44
45////////////////////////////////////////////////////////////////////////////////////////////
46//
47// added this group of tests for OpenSparc T2 fc8 (called fc8_mini_T2)
48//
49////////////////////////////////////////////////////////////////////////////////////////////
50
51
52<sys(mini_T2) sys=fc8 -vcs_build_args=+define+FBDIMM_NUM_8+ >
53<runargs -sys=fc8 -fast_boot -tg_seed=1 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DL2_REG_PROG>
54<runargs -sas -vcs_run_args=+show_delta -vcs_run_args=+NIU_STUB_TIME=600000 >
55
56
57// has 17 tests that should pass
58// should not have any more than 17 tests, please keep it small so it is quicker to run
59
60
61<fc8_memop8_mini name=fc8_memop8_mini>
62memop_mt_l2_dep_store memop_mt_l2_dep_store.s -midas_args=-DCMP_THREAD_START=0x0101010101010101 -midas_args=-DSYNC_THREADS=0x101010101010101 -finish_mask=0101010101010101
63memop_mt_l2_miss_buff memop_mt_l2_miss_buff.s -midas_args=-DCMP_THREAD_START=0x0101010101010101 -midas_args=-DSYNC_THREADS=0x101010101010101 -finish_mask=0101010101010101
64memop_mt_l2_dep_store_midas memop_mt_l2_dep_store.s -midas_args=-DCMP_THREAD_START=0x101010101010101 -midas_args=-DSYNC_THREADS=0x101010101010101 -finish_mask=0101010101010101
65memop_mt_l2_miss_buff_midas memop_mt_l2_miss_buff.s -midas_args=-DCMP_THREAD_START=0x101010101010101 -midas_args=-DSYNC_THREADS=0x101010101010101 -finish_mask=0101010101010101
66
67memop_mt_fpu_ld_st memop_mt_fpu_ld_st.s -midas_args=-DCMP_THREAD_START=0x0101010101010101 -finish_mask=0101010101010101
68memop_all_stores memop_all_stores.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
69memop_all_loads memop_all_loads.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
70</fc8_memop8_mini>
71
72<fc8_mcu8_mini name=fc8_mcu8_mini>
73<runargs -vcs_run_args=+8_FBDIMMS -midas_args=-allow_tsb_conflicts >
74n2_mcu_0_all_bcopy_all_banks_64t n2_mcu_0_all_bcopy_all_banks.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
75</runargs>
76<runargs -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000 -vcs_run_args=+8_FBDIMMS >
77n2_all_th_ldst_th32_boot n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffff -finish_mask=ffffffff
78</runargs>
79</fc8_mcu8_mini>
80
81<fc8_l2_mini name=fc8_l2_mini>
82<runargs -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000>
83allcores_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01
84</runargs>
85</fc8_l2_mini>
86
87<fc8_interrupt_mini name=fc8_interrupt_mini>
88<runargs -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000>
89interrupt_SWVR_INTR_W_all_threads interrupt_SWVR_INTR_W_all_threads.s -midas_args=-DCMP_THREAD_START=0xffffff -finish_mask=ffffff -midas_args=-DSYNC_THREADS=0xffffff
90
91<runargs -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DSYNC_THREADS=0xffffffffffffffff>
92interrupt_INT_VEC_DIS_all interrupt_INT_VEC_DIS_all.s
93//interrupt_INT_MAN_thread_all interrupt_INT_MAN_thread_all.s -midas_args=-DDIAG_NUM_THREADS=64
94//interrupt_mondo_intr_all_threads interrupt_mondo_intr_all_threads.s -vcs_run_args=+PEU_TEST -nosas
95interrupt_send_cc_all_thr interrupt_send_cc_all_thr.s -midas_args=-DTHREAD_COUNT=64
96</runargs>
97</runargs>
98</fc8_interrupt_mini>
99
100<fc8_pm_mini name=fc8_pm_mini>
101<runargs -vcs_run_args=+gchkr_off -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=4>
102core_01_bank_4_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -midas_args=-DPART_0_BASE=0x0
103</runargs>
104</fc8_pm_mini>
105
106<fc8_cmp8_mini name=fc8_cmp8_mini>
107<runargs -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DTHREAD_COUNT=64>
108cmp_master_park_unpark_all_rw cmp_master_park_unpark_all_rw.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
109</runargs>
110<runargs -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000 -vcs_run_args=+8_FBDIMMS >
111n2_all_th_ldst_core_0_1_2_3_4_8th n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffffff -finish_mask=ffffffffff
112n2_all_th_ldst_th64_force n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
113</runargs>
114</fc8_cmp8_mini>
115
116
117
118
119</runargs>
120</runargs>
121
122</sys(mini_T2)>
123
124
125////////////////////////////////////////////////////////////////////////////////////////////////////
126
127
128<sys(all_T2) sys=fc8 -vcs_build_args=+define+FBDIMM_NUM_8+ >
129<runargs -sys=fc8 -fast_boot -tg_seed=1 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DL2_REG_PROG>
130<runargs -nosas -vcs_run_args=+show_delta -vcs_run_args=+NIU_STUB_TIME=600000 >
131
132#ifndef FC_NO_NIU_T2
133#include "diaglists/fc/fc_niu.diaglist"
134#endif
135
136<fc8_ucb_acc_all name=fc8_ucb_acc_all>
137<runargs -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -fast_boot>
138//ncu_ios ncu_ios.s
139ncu_tcu ncu_tcu.s
140//ncu_ios_nack ncu_ios_nack.s
141</runargs>
142</fc8_ucb_acc_all>
143
144<fc8_pm_all name=fc8_pm_all>
145<runargs -vcs_run_args=+gchkr_off>
146<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=4>
147
148core_01_bank_4_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -midas_args=-DPART_0_BASE=0x0 -fast_boot -sas
149</runargs>
150
151<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=4>
152
153core_02_bank_4_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -midas_args=-DPART_0_BASE=0x0 -fast_boot -sas
154
155</runargs>
156
157<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=a>
158
159core_01_bank_a_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -midas_args=-DPART_0_BASE=0x200000000 -fast_boot -sas
160
161</runargs>
162
163<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=a>
164
165core_02_bank_a_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -midas_args=-DPART_0_BASE=0x200000000 -fast_boot -sas
166
167</runargs>
168
169<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=f>
170
171core_01_bank_f_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -midas_args=-DPART_0_BASE=0x200000000 -fast_boot -sas
172
173</runargs>
174
175<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=f>
176
177core_02_bank_f_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -midas_args=-DPART_0_BASE=0x200000000 -fast_boot -sas
178
179</runargs>
180
181<runargs -vcs_run_args=+core_set_mask=a6 -vcs_run_args=+bank_set_mask=6>
182
183core_a6_bank_6_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x0100010000010100 -finish_mask=0100010000010100 -midas_args=-DPART_0_BASE=0x200000000 -fast_boot -sas
184
185</runargs>
186
187<runargs -vcs_run_args=+core_set_mask=ff -vcs_run_args=+bank_set_mask=f>
188
189core_ff_bank_f_memop_ccx_packets memop_ccx_packets.s -midas_args=-DCMP_THREAD_START=0x0101010101010101 -finish_mask=0101010101010101 -midas_args=-DPART_0_BASE=0x200000000 -fast_boot -sas
190
191</runargs>
192
193</runargs>
194</fc8_pm_all>
195
196<fc8_memop8_all name=fc8_memop8_all>
197memop_mt_l2_dep_store memop_mt_l2_dep_store.s -midas_args=-DCMP_THREAD_START=0x0101010101010101 -nosas -midas_args=-DSYNC_THREADS=0x101010101010101 -finish_mask=0101010101010101
198memop_mt_l2_miss_buff memop_mt_l2_miss_buff.s -midas_args=-DCMP_THREAD_START=0x0101010101010101 -nosas -midas_args=-DSYNC_THREADS=0x101010101010101 -finish_mask=0101010101010101
199memop_mt_l2_dep_store_midas memop_mt_l2_dep_store.s -midas_args=-DCMP_THREAD_START=0x101010101010101 -nosas -midas_args=-DSYNC_THREADS=0x101010101010101 -finish_mask=0101010101010101
200memop_mt_l2_miss_buff_midas memop_mt_l2_miss_buff.s -midas_args=-DCMP_THREAD_START=0x101010101010101 -nosas -midas_args=-DSYNC_THREADS=0x101010101010101 -finish_mask=0101010101010101
201
202memop_mt_fpu_ld_st memop_mt_fpu_ld_st.s -midas_args=-DCMP_THREAD_START=0x0101010101010101 -nosas -finish_mask=0101010101010101
203memop_all_stores memop_all_stores.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -sas
204memop_all_loads memop_all_loads.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -sas
205</fc8_memop8_all>
206
207<fc8_mcu8_all name=fc8_mcu8_all>
208<runargs -vcs_run_args=+8_FBDIMMS -sas -midas_args=-allow_tsb_conflicts >
209n2_mcu_0_all_bcopy_all_banks_64t n2_mcu_0_all_bcopy_all_banks.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
210</runargs>
211<runargs -sas -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000 -vcs_run_args=+8_FBDIMMS >
212n2_all_th_ldst_th16_boot n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffff -finish_mask=ffff
213n2_all_th_ldst_th20_boot n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xfffff -finish_mask=fffff
214n2_all_th_ldst_th24_boot n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffff -finish_mask=ffffff
215n2_all_th_ldst_th28_boot n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xfffffff -finish_mask=fffffff
216n2_all_th_ldst_th32_boot n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffff -finish_mask=ffffffff
217</runargs>
218</fc8_mcu8_all>
219
220<fc8_l2_all name=fc8_l2_all>
221<runargs -nosas -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000>
222allcores_allbanks_atomic allcores_allbanks_atomic.s -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01
223allcores_allbanks allcores_allbanks.s -midas_args=-DCMP_THREAD_START=0x0101010101010101 -finish_mask=0101010101010101
224</runargs>
225</fc8_l2_all>
226
227<fc8_interrupt_all name=fc8_interrupt_all>
228<runargs -sas -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000>
229interrupt_SWVR_INTR_W_all_threads interrupt_SWVR_INTR_W_all_threads.s -midas_args=-DCMP_THREAD_START=0xffffff -finish_mask=ffffff -midas_args=-DSYNC_THREADS=0xffffff
230<runargs -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DSYNC_THREADS=0xffffffffffffffff>
231interrupt_INT_VEC_DIS_all interrupt_INT_VEC_DIS_all.s
232//interrupt_INT_MAN_thread_all interrupt_INT_MAN_thread_all.s -midas_args=-DDIAG_NUM_THREADS=64
233//interrupt_mondo_intr_all_threads interrupt_mondo_intr_all_threads.s -vcs_run_args=+PEU_TEST -nosas
234interrupt_send_cc_all_thr interrupt_send_cc_all_thr.s -midas_args=-DTHREAD_COUNT=64 -nosas
235
236</runargs>
237</runargs>
238</fc8_interrupt_all>
239
240<fc8_cmp8_all name=fc8_cmp8_all>
241<runargs -sas -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+skt_timeout=250000 -vcs_run_args=+8_FBDIMMS >
242
243n2_all_th_ldst_th64_force n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
244n2_all_th_ldst_th0_1_9 n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0x203 -finish_mask=0x203
245n2_all_th_ldst_th64 n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
246
247// different core combinations
248n2_all_th_ldst_core_0_2_8th n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xff00ff -finish_mask=0xff00ff
249n2_all_th_ldst_core_0_1_2_4_8th n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xff00ffffff -finish_mask=ff00ffffff
250n2_all_th_ldst_core_0_1_2_3_4_8th n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xffffffffff -finish_mask=ffffffffff
251
252n2_mcu_0_all_fbdimm_rkhi_mcu0_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU0 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
253n2_mcu_0_all_fbdimm_rkhi_mcu1_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU1 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
254n2_mcu_0_all_fbdimm_rkhi_mcu2_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU2 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
255n2_mcu_0_all_fbdimm_rkhi_mcu3_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU3 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff
256
257n2_mcu_0_all_fbdimm_rkhi_mcu0_L2off_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU0 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
258n2_mcu_0_all_fbdimm_rkhi_mcu1_L2off_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU1 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
259n2_mcu_0_all_fbdimm_rkhi_mcu2_L2off_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU2 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
260n2_mcu_0_all_fbdimm_rkhi_mcu3_L2off_64th n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU3 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
261
262</runargs>
263
264////////////////////////////////////////////////////////////////////////////
265// CMT diags, 8 core
266////////////////////////////////////////////////////////////////////////////
267
268<runargs -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -finish_mask=ffffffffffffffff -midas_args=-DTHREAD_COUNT=64>
269
270cmp_park_all_w1c_w1s cmp_park_all_w1c_w1s.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
271
272cmp_master_park_unpark_all_rw cmp_master_park_unpark_all_rw.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
273
274cmp_master_park_unpark_all_w1s_w1c cmp_master_park_unpark_all_w1s_w1c.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
275
276cmp_park_all_rw cmp_park_all_rw.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
277
278</runargs>
279<runargs -sas -max_cycle=+10000000 -rtl_timeout=4000000 -vcs_run_args=+l2cpx_errmon_off>
280ncu_park_unpark_by_running_rw ncu_park_unpark_by_running_rw.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
281
282ncu_park_unpark_multiple_times ncu_park_unpark_multiple_times.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
283
284ncu_park_by_running_rw1c ncu_park_by_running_rw1c.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
285
286ncu_unpark_by_running_rw1s ncu_unpark_by_running_rw1s.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
287
288ncu_force_unpark_thr1 ncu_force_unpark_thr1.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
289
290ncu_force_unpark_thr2 ncu_force_unpark_thr2.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
291
292ncu_core_id ncu_core_id.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
293
294ncu_xir ncu_xir.s -finish_mask=0x0006060000060607 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DCMP_THREAD_START=0xffffffffffffffff
295
296ncu_xir_allth ncu_xir_allth.s -finish_mask=0xffffffffffffffff -midas_args=-DPART_0_BASE=0x200000000
297
298ncu_pcx_pkts_allth ncu_pcx_pkts_allth.s -finish_mask=0xffffffffffffffff -midas_args=-DPART_0_BASE=0x200000000
299
300ncu_ssi_mt ncu_ssi_mt.s -finish_mask=0x0040000000000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot
301
302ncu_ssi_ifill_ack_nack_1 ncu_ssi_ifill_ack_nack.s -finish_mask=0x00000000000000ff -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x00000000000000ff
303
304ncu_ssi_ifill_ack_nack_2 ncu_ssi_ifill_ack_nack.s -finish_mask=0x000000000000ff00 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x000000000000ff00
305
306ncu_ssi_ifill_ack_nack_3 ncu_ssi_ifill_ack_nack.s -finish_mask=0x0000000000ff0000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x0000000000ff0000
307
308ncu_ssi_ifill_ack_nack_4 ncu_ssi_ifill_ack_nack.s -finish_mask=0x00000000ff000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x00000000ff000000
309
310ncu_ssi_ifill_ack_nack_5 ncu_ssi_ifill_ack_nack.s -finish_mask=0x000000ff00000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x000000ff00000000
311
312ncu_ssi_ifill_ack_nack_6 ncu_ssi_ifill_ack_nack.s -finish_mask=0x0000ff0000000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x0000ff0000000000
313
314ncu_ssi_ifill_ack_nack_7 ncu_ssi_ifill_ack_nack.s -finish_mask=0x00ff000000000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0x00ff000000000000
315
316ncu_ssi_ifill_ack_nack_8 ncu_ssi_ifill_ack_nack.s -finish_mask=0xff00000000000000 -midas_args=-DPART_0_BASE=0x200000000 -nofast_boot -midas_args=-DCORE_RUNNING=0xff00000000000000
317
318ncu_asi_cmp_tick_enable ncu_asi_cmp_tick_enable.s -finish_mask=0x8000000000000000 -midas_args=-DPART_0_BASE=0x200000000
319
320ncu_asi_cmp_tick_enable_2 ncu_asi_cmp_tick_enable_2.s -finish_mask=0xffffffffffffffff -midas_args=-DPART_0_BASE=0x200000000
321
322ncu_asi_cmp_tick_enable_3 ncu_asi_cmp_tick_enable_3.s -finish_mask=0xffffffffffffffff -midas_args=-DPART_0_BASE=0x200000000
323
324ncu_bank_en_subset ncu_bank_en_subset.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xc3 -vcs_run_args=+bank_set_mask=9 -midas_args=-DCORE_AVAIL=0xa2 -vcs_run_args=+core_set_mask=a2 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -nofast_boot -vcs_run_args=+gchkr_off
325
326ncu_bank_en_wptect_basic_1 ncu_bank_en_wptect_basic.s -finish_mask=0x0000000001000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x03 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCORE_AVAIL=0x0c -vcs_run_args=+core_set_mask=0c -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
327
328ncu_bank_en_wptect_basic_2 ncu_bank_en_wptect_basic.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x0c -vcs_run_args=+bank_set_mask=2 -midas_args=-DCORE_AVAIL=0x60 -vcs_run_args=+core_set_mask=60 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
329
330ncu_bank_en_wptect_basic_3 ncu_bank_en_wptect_basic.s -finish_mask=0x0000010000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x30 -vcs_run_args=+bank_set_mask=4 -midas_args=-DCORE_AVAIL=0x28 -vcs_run_args=+core_set_mask=28 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
331
332ncu_bank_en_wptect_basic_4 ncu_bank_en_wptect_basic.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xc0 -vcs_run_args=+bank_set_mask=8 -midas_args=-DCORE_AVAIL=0x81 -vcs_run_args=+core_set_mask=81 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
333
334ncu_bank_en_wptect_basic_5 ncu_bank_en_wptect_basic.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x0f -vcs_run_args=+bank_set_mask=3 -midas_args=-DCORE_AVAIL=0xe2 -vcs_run_args=+core_set_mask=e2 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
335
336ncu_bank_en_wptect_basic_6 ncu_bank_en_wptect_basic.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x33 -vcs_run_args=+bank_set_mask=5 -midas_args=-DCORE_AVAIL=0x54 -vcs_run_args=+core_set_mask=54 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
337
338ncu_bank_en_wptect_basic_7 ncu_bank_en_wptect_basic.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xc3 -vcs_run_args=+bank_set_mask=9 -midas_args=-DCORE_AVAIL=0xa3 -vcs_run_args=+core_set_mask=a3 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
339
340ncu_bank_en_wptect_basic_8 ncu_bank_en_wptect_basic.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0x3c -vcs_run_args=+bank_set_mask=6 -midas_args=-DCORE_AVAIL=0x78 -vcs_run_args=+core_set_mask=78 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
341
342ncu_bank_en_wptect_basic_9 ncu_bank_en_wptect_basic.s -finish_mask=0x0000000001000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xcc -vcs_run_args=+bank_set_mask=a -midas_args=-DCORE_AVAIL=0x0f -vcs_run_args=+core_set_mask=0f -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
343
344ncu_bank_en_wptect_basic_10 ncu_bank_en_wptect_basic.s -finish_mask=0x0000000100000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DBANK_AVAIL=0xf0 -vcs_run_args=+bank_set_mask=c -midas_args=-DCORE_AVAIL=0x17 -vcs_run_args=+core_set_mask=17 -vcs_run_args=+FAST_BISI -midas_args=-DL2_CORE_ENABLE -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
345
346ncu_sernum_coreavail_bankavail_wptect_1 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0xa4 -vcs_run_args=+core_set_mask=a4 -midas_args=-DBANK_AVAIL=0x33 -vcs_run_args=+bank_set_mask=5 -midas_args=-DSERIAL_NUM=0x20d6732cefab3640 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
347
348ncu_sernum_coreavail_bankavail_wptect_2 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x42 -vcs_run_args=+core_set_mask=42 -midas_args=-DBANK_AVAIL=0x03 -vcs_run_args=+bank_set_mask=1 -midas_args=-DSERIAL_NUM=0x39871cddba5a09df -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
349
350ncu_sernum_coreavail_bankavail_wptect_3 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0001000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x53 -vcs_run_args=+core_set_mask=53 -midas_args=-DBANK_AVAIL=0xc3 -vcs_run_args=+bank_set_mask=9 -midas_args=-DSERIAL_NUM=0x9919192763492733 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
351
352ncu_sernum_coreavail_bankavail_wptect_4 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000010000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x28 -vcs_run_args=+core_set_mask=28 -midas_args=-DBANK_AVAIL=0x0c -vcs_run_args=+bank_set_mask=2 -midas_args=-DSERIAL_NUM=0xfbcfecdacfdecfea -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
353
354ncu_sernum_coreavail_bankavail_wptect_5 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000100000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x17 -vcs_run_args=+core_set_mask=17 -midas_args=-DBANK_AVAIL=0xf0 -vcs_run_args=+bank_set_mask=c -midas_args=-DSERIAL_NUM=0xaaaaaaaaaaaaaaaa -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
355
356ncu_sernum_coreavail_bankavail_wptect_6 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0100000000000000 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0xff -vcs_run_args=+core_set_mask=ff -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x5555555555555555 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS -vcs_run_args=+gchkr_off
357
358ncu_sernum_coreavail_bankavail_wptect_7 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0000100000400001 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
359
360ncu_sernum_coreavail_bankavail_wptect_8 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0000200000800002 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
361
362ncu_sernum_coreavail_bankavail_wptect_9 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0000400001000004 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
363
364ncu_sernum_coreavail_bankavail_wptect_10 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0000800002000008 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
365
366ncu_sernum_coreavail_bankavail_wptect_11 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0001000004000010 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
367
368ncu_sernum_coreavail_bankavail_wptect_12 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0002000008000020 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
369
370ncu_sernum_coreavail_bankavail_wptect_13 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0004000010000040 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
371
372ncu_sernum_coreavail_bankavail_wptect_14 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0008000020000080 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
373
374ncu_sernum_coreavail_bankavail_wptect_15 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0010000040000100 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
375
376ncu_sernum_coreavail_bankavail_wptect_16 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0020000080000200 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
377
378ncu_sernum_coreavail_bankavail_wptect_17 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0040000100000400 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
379
380ncu_sernum_coreavail_bankavail_wptect_18 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0080000200000800 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
381
382ncu_sernum_coreavail_bankavail_wptect_19 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0100000400001000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
383
384ncu_sernum_coreavail_bankavail_wptect_20 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0200000800002000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
385
386ncu_sernum_coreavail_bankavail_wptect_21 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0400001000004000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
387
388ncu_sernum_coreavail_bankavail_wptect_22 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x0800002000008000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
389
390ncu_sernum_coreavail_bankavail_wptect_23 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x1000004000010000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
391
392ncu_sernum_coreavail_bankavail_wptect_24 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x2000008000020000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
393
394ncu_sernum_coreavail_bankavail_wptect_25 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x4000010000040000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
395
396ncu_sernum_coreavail_bankavail_wptect_26 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x8000020000080000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
397
398ncu_sernum_coreavail_bankavail_wptect_27 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x8000040000100000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
399
400ncu_sernum_coreavail_bankavail_wptect_28 ncu_sernum_coreavail_bankavail_wptect.s -finish_mask=0x0000000000000001 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DRESET_STAT_CHECK -midas_args=-DCORE_AVAIL=0x01 -vcs_run_args=+core_set_mask=01 -midas_args=-DBANK_AVAIL=0xff -vcs_run_args=+bank_set_mask=f -midas_args=-DSERIAL_NUM=0x8000080000200000 -vcs_run_args=+FAST_BISI -vcs_run_args=+4_FBDIMMS
401
402</runargs>
403</fc8_cmp8_all>
404
405
406
407<fc8_power_diag name=fc8_power_diag>
408<runargs -vcs_run_args=+l2esr_mon_off -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2cpx_errmon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+8_FBDIMMS -midas_args=-DBOOT_SLAVE_THREADS_FROM_MEMORY -midas_args=-DFAST_BOOT -sas>
409
410n2_noIo_noSpu_64threads_active n2_noIo_noSpu_64_thread_active.s -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -midas_args=-DSYNC_THREADS=0xffffffffffffffff -midas_args=-Dloop_cnt=0xffffffffff -midas_args=-Dloop_cnt_2=0xffffffffff -midas_args=-Dloop_cnt_3=0xffffffffff -midas_args=-DN_SPU_TIMES=0xfffffff -midas_args=-Dloop_cnt_4=0xffffffffff -midas_args=-Dloop_cnt_4_th0=0xdfff -finish_mask=0000000000000080 -midas_args=-DNUM_LOOP_TH7=0x700 -midas_args=-DNUM_LOOP_TH7_C0=50
411</runargs>
412</fc8_power_diag>
413
414
415<6core_diags name=6core_diags>
416
417<runargs -midas_args=-DSIXGUNS>
418
419// Always run with TSO_CHECKER enabled
420<runargs -sas_run_args=-DTSO_CHECKER -sas_run_args=-DTHREAD_MASK=xxxxffffffffffff -midas_args=-DSIXGUNS -vcs_run_args=+core_set_mask=3f -midas_args=-DCMP_THREAD_START=0xffffffffffffffff -vcs_run_args=+finish_mask=0000ffffffffffff -vcs_run_args=+gchkr_off>
421
422//---MPGen diags {{{
423<runargs -midas_args=-allow_tsb_conflicts>
424
425<6core_mpgen_dynamic_caches>
426mpgen_dynamic_caches_2 mpgen_dynamic_caches_2.s
427mpgen_dynamic_caches_4 mpgen_dynamic_caches_4.s
428mpgen_dynamic_caches_5 mpgen_dynamic_caches_5.s
429</6core_mpgen_dynamic_caches>
430
431<6core_mpgen_dynamic_pwr_mgmt>
432mpgen_dynamic_pwr_mgmt mpgen_dynamic_pwr_mgmt.s
433mpgen_dynamic_pwr_mgmt_2 mpgen_dynamic_pwr_mgmt_2.s
434mpgen_dynamic_pwr_mgmt_3 mpgen_dynamic_pwr_mgmt_3.s
435mpgen_dynamic_pwr_mgmt_4 mpgen_dynamic_pwr_mgmt_4.s
436</6core_mpgen_dynamic_pwr_mgmt>
437
438<6core_mpgen_tso_all_banks>
439mpgen_tso_all_banks_2 mpgen_tso_all_banks_2.s
440mpgen_tso_all_banks_3 mpgen_tso_all_banks_3.s
441mpgen_tso_all_banks_4 mpgen_tso_all_banks_4.s
442mpgen_tso_all_banks_5 mpgen_tso_all_banks_5.s
443</6core_mpgen_tso_all_banks>
444
445<6core_mpgen_tso_atomic_all_banks>
446mpgen_tso_atomic_all_banks_2 mpgen_tso_atomic_all_banks_2.s
447mpgen_tso_atomic_all_banks_3 mpgen_tso_atomic_all_banks_3.s
448mpgen_tso_atomic_all_banks_4 mpgen_tso_atomic_all_banks_4.s
449mpgen_tso_atomic_all_banks_5 mpgen_tso_atomic_all_banks_5.s
450</6core_mpgen_tso_atomic_all_banks>
451
452<6core_mpgen_tso_atomic_asi_one_bank>
453mpgen_tso_atomic_asi_one_bank_3 mpgen_tso_atomic_asi_one_bank_3.s
454mpgen_tso_atomic_asi_one_bank_4 mpgen_tso_atomic_asi_one_bank_4.s
455mpgen_tso_atomic_asi_one_bank_5 mpgen_tso_atomic_asi_one_bank_5.s
456</6core_mpgen_tso_atomic_asi_one_bank>
457
458<6core_mpgen_tso_atomic_one_bank>
459mpgen_tso_atomic_one_bank mpgen_tso_atomic_one_bank.s
460mpgen_tso_atomic_one_bank_2 mpgen_tso_atomic_one_bank_2.s
461mpgen_tso_atomic_one_bank_3 mpgen_tso_atomic_one_bank_3.s
462mpgen_tso_atomic_one_bank_4 mpgen_tso_atomic_one_bank_4.s
463mpgen_tso_atomic_one_bank_5 mpgen_tso_atomic_one_bank_5.s
464</6core_mpgen_tso_atomic_one_bank>
465
466<6core_mpgen_tso_ba_all_banks>
467mpgen_tso_ba_all_banks mpgen_tso_ba_all_banks.s
468mpgen_tso_ba_all_banks_2 mpgen_tso_ba_all_banks_2.s
469mpgen_tso_ba_all_banks_3 mpgen_tso_ba_all_banks_3.s
470mpgen_tso_ba_all_banks_4 mpgen_tso_ba_all_banks_4.s
471mpgen_tso_ba_all_banks_5 mpgen_tso_ba_all_banks_5.s
472</6core_mpgen_tso_ba_all_banks>
473
474<6core_mpgen_tso_ba_one_bank>
475mpgen_tso_ba_one_bank_3 mpgen_tso_ba_one_bank_3.s
476mpgen_tso_ba_one_bank_4 mpgen_tso_ba_one_bank_4.s
477mpgen_tso_ba_one_bank_5 mpgen_tso_ba_one_bank_5.s
478</6core_mpgen_tso_ba_one_bank>
479
480<6core_mpgen_tso_one_bank>
481mpgen_tso_one_bank mpgen_tso_one_bank.s
482mpgen_tso_one_bank_3 mpgen_tso_one_bank_3.s
483mpgen_tso_one_bank_4 mpgen_tso_one_bank_4.s
484mpgen_tso_one_bank_5 mpgen_tso_one_bank_5.s
485</6core_mpgen_tso_one_bank>
486
487
488</runargs>
489//---MPGen diags }}}
490
491</runargs>
492
493</runargs> // SIXGUNS
494
495</6core_diags>
496
497<8core_diags name=8core_diags>
498
499<runargs -vcs_run_args=+EIGHT_CORE_DTM2_TESTER>
500
501
502// Always run with TSO_CHECKER enabled
503<runargs -sas_run_args=-DTSO_CHECKER>
504
505//---MPGen diags {{{
506<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>
507
508<8core_mpgen_dynamic_caches>
509mpgen_dynamic_caches_2 mpgen_dynamic_caches_2.s
510mpgen_dynamic_caches_4 mpgen_dynamic_caches_4.s
511mpgen_dynamic_caches_5 mpgen_dynamic_caches_5.s
512</8core_mpgen_dynamic_caches>
513
514<8core_mpgen_dynamic_pwr_mgmt>
515mpgen_dynamic_pwr_mgmt mpgen_dynamic_pwr_mgmt.s
516mpgen_dynamic_pwr_mgmt_2 mpgen_dynamic_pwr_mgmt_2.s
517mpgen_dynamic_pwr_mgmt_3 mpgen_dynamic_pwr_mgmt_3.s
518mpgen_dynamic_pwr_mgmt_4 mpgen_dynamic_pwr_mgmt_4.s
519</8core_mpgen_dynamic_pwr_mgmt>
520
521<8core_mpgen_tso_all_banks>
522mpgen_tso_all_banks_2 mpgen_tso_all_banks_2.s
523mpgen_tso_all_banks_3 mpgen_tso_all_banks_3.s
524mpgen_tso_all_banks_4 mpgen_tso_all_banks_4.s
525mpgen_tso_all_banks_5 mpgen_tso_all_banks_5.s
526</8core_mpgen_tso_all_banks>
527
528<8core_mpgen_tso_atomic_all_banks>
529mpgen_tso_atomic_all_banks_2 mpgen_tso_atomic_all_banks_2.s
530mpgen_tso_atomic_all_banks_3 mpgen_tso_atomic_all_banks_3.s
531mpgen_tso_atomic_all_banks_4 mpgen_tso_atomic_all_banks_4.s
532mpgen_tso_atomic_all_banks_5 mpgen_tso_atomic_all_banks_5.s
533</8core_mpgen_tso_atomic_all_banks>
534
535<8core_mpgen_tso_atomic_asi_one_bank>
536mpgen_tso_atomic_asi_one_bank_3 mpgen_tso_atomic_asi_one_bank_3.s
537mpgen_tso_atomic_asi_one_bank_4 mpgen_tso_atomic_asi_one_bank_4.s
538mpgen_tso_atomic_asi_one_bank_5 mpgen_tso_atomic_asi_one_bank_5.s
539</8core_mpgen_tso_atomic_asi_one_bank>
540
541<8core_mpgen_tso_atomic_one_bank>
542mpgen_tso_atomic_one_bank mpgen_tso_atomic_one_bank.s
543mpgen_tso_atomic_one_bank_2 mpgen_tso_atomic_one_bank_2.s
544mpgen_tso_atomic_one_bank_3 mpgen_tso_atomic_one_bank_3.s
545mpgen_tso_atomic_one_bank_4 mpgen_tso_atomic_one_bank_4.s
546mpgen_tso_atomic_one_bank_5 mpgen_tso_atomic_one_bank_5.s
547</8core_mpgen_tso_atomic_one_bank>
548
549<8core_mpgen_tso_ba_all_banks>
550mpgen_tso_ba_all_banks mpgen_tso_ba_all_banks.s
551mpgen_tso_ba_all_banks_2 mpgen_tso_ba_all_banks_2.s
552mpgen_tso_ba_all_banks_3 mpgen_tso_ba_all_banks_3.s
553mpgen_tso_ba_all_banks_4 mpgen_tso_ba_all_banks_4.s
554mpgen_tso_ba_all_banks_5 mpgen_tso_ba_all_banks_5.s
555</8core_mpgen_tso_ba_all_banks>
556
557<8core_mpgen_tso_ba_one_bank>
558mpgen_tso_ba_one_bank_3 mpgen_tso_ba_one_bank_3.s
559mpgen_tso_ba_one_bank_4 mpgen_tso_ba_one_bank_4.s
560mpgen_tso_ba_one_bank_5 mpgen_tso_ba_one_bank_5.s
561</8core_mpgen_tso_ba_one_bank>
562
563<8core_mpgen_tso_one_bank>
564mpgen_tso_one_bank mpgen_tso_one_bank.s
565mpgen_tso_one_bank_3 mpgen_tso_one_bank_3.s
566mpgen_tso_one_bank_4 mpgen_tso_one_bank_4.s
567mpgen_tso_one_bank_5 mpgen_tso_one_bank_5.s
568</8core_mpgen_tso_one_bank>
569
570
571</runargs>
572//---MPGen diags }}}
573
574</runargs>
575
576<8core_ncu>
577
578<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
579interrupt_int_vec_dis interrupt_INT_VEC_DIS.s
580interrupt_pci_spurious_err interrupt_pci_spurious_err.s
581interrupt_queue_cpu_mondo_mode interrupt_QUEUE_CPU_MONDO_mode.s
582interrupt_queue_cpu_mondo_trap interrupt_QUEUE_CPU_MONDO_trap.s
583interrupt_queue_dev_mondo_mode interrupt_QUEUE_DEV_MONDO_mode.s
584interrupt_queue_dev_mondo_trap interrupt_QUEUE_DEV_MONDO_trap.s
585interrupt_swvr_intr_r interrupt_SWVR_INTR_R.s
586</runargs>
587
588<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 -midas_args=-DSYNC_THREADS=0x3 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
589<8core_ncu_subset>
590interrupt_swvr_intr_r_mode interrupt_SWVR_INTR_R_mode.s
591interrupt_swvr_intr_rec_mode interrupt_SWVR_INTR_REC_mode.s
592interrupt_swvr_intr_w_mode interrupt_SWVR_INTR_W_mode.s
593</8core_ncu_subset>
594</runargs>
595
596<runargs -midas_args=-DCMP_THREAD_START=0x1 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
597n2_cmp_upk_pk_upk n2_cmp_upk_pk_upk.s -finish_mask=3
598</runargs>
599
600<runargs -midas_args=-DCMP_THREAD_START=0x1 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
601ncu_1core_wakup ncu_1core_wakup.s -finish_mask=0x2b
602</runargs>
603
604</8core_ncu>
605
606</runargs> // EIGHT_CORE_DTM2_TESTER
607
608</8core_diags>
609
610
611<runargs -sas -finish_mask=01 >
612
613////////////////////////////////////////////////////////////////////////////////////////////////////
614
615<runargs -tg_seed=1 -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DL2_REG_PROG >
616<runargs -nosas >
617
618
619<fc8_memop_all name=fc8_memop_all>
620
621////////////////////////
622// Single thread diags
623///////////////////////
624
625<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
626<runargs -sas>
627
628memop_all_atomics memop_all_atomics.s
629
630memop_all_mcu memop_all_mcu.s
631
632memop_all_stores memop_all_stores.s
633
634memop_byte_mask memop_byte_mask.s
635
636memop_ccx_packets memop_ccx_packets.s
637
638memop_halfword_byte_mask memop_halfword_byte_mask.s
639
640memop_l2_disable memop_l2_disable.s
641
642memop_word_byte_mask memop_word_byte_mask.s
643
644memop_all_loads memop_all_loads.s -vcs_run_args=+l2warm=1
645
646</runargs>
647
648<runargs -nosas>
649
650#ifndef CCM
651
652// Must '-nosas' until Riesling support MCU CSR's
653
654memop_mcu_regs_ro memop_mcu_regs_ro.s
655
656memop_mcu_regs_rw memop_mcu_regs_rw.s
657
658memop_mcu_regs_other memop_mcu_regs_other.s -vcs_run_args=+mcu_errmon_disable
659
660#endif
661
662// Must use '-nosas' since follow me support is not there for SPU interrupts
663
664// memop_all_packet memop_all_packet.s -midas_args=-allow_tsb_conflicts
665
666memop_all_l2_banks memop_all_l2_banks.s
667
668memop_all_mcu_banks memop_all_mcu_banks.s
669
670memop_l2_vuad_access memop_l2_vuad_access.s
671
672memop_walk_one_addr memop_walk_one_addr.s
673
674memop_l2_control_reg memop_l2_control_reg.s
675
676</runargs>
677
678memop_mem_out_of_range memop_mem_out_of_range.s -vcs_run_args=+l2esr_mon_off -vcs_run_args=+8_FBDIMMS
679
680memop_l2_size memop_l2_size.s -midas_args=-allow_tsb_conflicts
681
682memop_all_byte_mask memop_all_byte_mask.s
683
684memop_l2_err_en_reg memop_l2_err_en_reg.s
685
686memop_l2_err_address_reg memop_l2_err_address_reg.s
687
688memop_l2_err_status_reg memop_l2_err_status_reg.s
689
690memop_l2_err_inject_reg memop_l2_err_inject_reg.s
691
692memop_l2_notdata_err_addr_reg memop_l2_notdata_err_addr_reg.s
693
694</runargs>
695
696/////////////////////////
697// Multiple thread diags
698////////////////////////
699
700<runargs -sas>
701
702memop_mt_l2_dep_store memop_mt_l2_dep_store.s -nosas -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
703
704memop_mt_l2_miss_buff memop_mt_l2_miss_buff.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
705
706memop_random_noatomic_multithrd memop_random_noatomic_multithrd.s -vcs_run_args=+TB_RANDOM_XIR -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DL2_REG_PROG -nofast_boot -vcs_run_args=+ios_0in_ras_chk_off
707
708#if (! defined FC)
709
710memop_mt_fpu_ld_st memop_mt_fpu_ld_st.s -midas_args=-DCMP_THREAD_START=0x01010101010101 -nosas -finish_mask=01010101010101
711
712#endif
713
714#if (! defined CCM)
715
716memop_mt2_invalidate_l1 memop_mt2_invalidate_l1.s -midas_args=-DCMP_THREAD_START=0x3 -nosas -midas_args=-allow_tsb_conflicts -finish_mask=3 -midas_args=-DSYNC_THREADS
717
718#endif
719
720</runargs>
721
722
723<runargs -vcs_run_args=+0in_no_checksim_db -vcs_run_args=+0in_no_statistics >
724
725n2_8tload_weight_486046 n2_8tload_weight_486046.s -nosas -midas_args=-DCMP_THREAD_START=0xff -midas_args=-allow_tsb_conflicts -max_cycle=+3000000 -drm_freeram=4000 -drm_freeswap=2000 -tg_seed=1600189735 -finish_mask=ff
726
727</runargs>
728
729
730////////////////////////
731// Long (over 20 hrs) memop diags
732////////////////////////
733
734<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
735
736memop_l2_data_access memop_l2_data_access.s -nosas
737
738memop_l2_tag_access memop_l2_tag_access.s -nosas
739
740</runargs>
741
742</fc8_memop_all>
743
744
745<arch_diags name=arch_diags >
746
747//Removed from FC 2005_09_13
748#if (!defined FC)
749<runargs -vcs_run_args=+thread=0f -sas -midas_args=-DSYNC_THREADS>
750
751<runargs -midas_args=-allow_tsb_conflicts -midas_args=-pal_diag_args=-thrd_count=4>
752
753ldst_tl0 ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldst_tl0"
754ldst_tl0_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldst_tl0_super"
755
756ldst_tl1 ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldst_tl1"
757ldst_tl1_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldst_tl1_super"
758
759<runargs -nofast_boot>
760ldst_tl0_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldst_tl0_hyper"
761ldst_tl1_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldst_tl1_hyper"
762</runargs>
763
764</runargs>
765
766<sys(long)>
767
768<runargs -midas_args=-allow_tsb_conflicts -midas_args=-pal_diag_args=-thrd_count=4>
769<runargs -vcs_run_args=+l2warm=1>
770
771ldf_ld_misalgn_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_dataacc_vawatch"
772ldf_ld_fpdis_misalgn_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_dataacc_vawatch"
773ldf_ld_fpdis_misalgn_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_vawatch_super"
774ldf_ld_misalgn_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_vawatch_super"
775ldf_ld_misalgn_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_vawatch"
776ldf_ld_fpdis_misalgn_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_vawatch"
777
778ldaf_lda_fpdis_misalgn_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn_vawatch"
779ldaf_lda_fpdis_misalgn_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn_vawatch_super"
780ldaf_lda_misalgn_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn_vawatch"
781ldaf_lda_misalgn_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn_vawatch_super"
782
783</runargs> // -midas_args=-allow_tsb_conflicts -midas_arg...
784</runargs> // -vcs_run_args=+l2warm=1
785
786</sys(long)>
787
788
789
790
791#endif // for ! defined FC
792
793#if (defined FC)
794<runargs -midas_args=-DCMP_THREAD_START=0x0f -sas -midas_args=-DSYNC_THREADS -finish_mask=f >
795#endif
796
797
798
799<runargs -midas_args=-allow_tsb_conflicts -midas_args=-pal_diag_args=-thrd_count=4>
800
801ldf_ld_fpdis ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis"
802ldf_ld_misalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn"
803ldf_ld_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_dataacc"
804ldf_ld_fpdis_misalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn"
805ldf_ld_fpdis_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_dataacc"
806//Removed From FC 2005_10_10 ldf_ld_fpdis_misalgn_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_dataacc"
807ldf_ld_misalgn_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_dataacc"
808ldf_ld_fpdis_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_super"
809ldf_ld_misalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_super"
810ldf_ld_fpdis_misalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_super"
811
812<runargs -nofast_boot>
813ldf_ld_fpdis_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_hyper"
814ldf_ld_misalgn_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_hyper"
815//ldf_ld_vawatch_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_vawatch_hyper" -rtl_timeout=100000
816ldf_ld_fpdis_misalgn_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_hyper"
817ldf_ld_fpdis_vawatch_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_vawatch_hyper"
818</runargs>
819
820lddf_ldd_alldest ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_alldest"
821lddf_ldd_fpdis ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis"
822lddf_ldd_misalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_misalgn"
823lddf_ldd_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_dataacc"
824lddf_ldd_dmisalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_dmisalgn"
825lddf_ldd_fpdis_misalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_misalgn"
826lddf_ldd_fpdis_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_dataacc"
827lddf_ldd_fpdis_dmisalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_dmisalgn"
828lddf_ldd_fpdis_dataacc_dmisalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_dataacc_dmisalgn"
829lddf_ldd_dataacc_dmisalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_dataacc_dmisalgn"
830lddf_ldd_fpdis_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_super"
831lddf_ldd_misalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_misalgn_super"
832lddf_ldd_dmisalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_dmisalgn_super"
833lddf_ldd_fpdis_misalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_misalgn_super"
834lddf_ldd_fpdis_dmisalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_dmisalgn_super"
835
836</runargs>
837
838//////////////////////////////
839// Long diags (over 8hrs), not to be run in daily
840//////////////////////////////
841
842<runargs -midas_args=-allow_tsb_conflicts -midas_args=-pal_diag_args=-thrd_count=4>
843
844// Removed From FC 2005_09_13
845#if( ! defined FC)
846
847
848ldf_ld_fpdis_misalgn_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_dataacc_vawatch"
849ldf_ld_fpdis_misalgn_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_vawatch_super"
850ldf_ld_misalgn_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_dataacc_vawatch"
851ldf_ld_misalgn_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_vawatch"
852ldf_ld_misalgn_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_vawatch_super"
853
854
855ldf_ld_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_vawatch_super"
856
857<runargs -nofast_boot>
858ldf_ld_misalgn_vawatch_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_misalgn_vawatch_hyper"
859ldf_ld_fpdis_misalgn_vawatch_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_vawatch_hyper"
860ldf_ld_alldest_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_alldest_hyper" -rtl_timeout=100000
861</runargs>
862
863ldf_ld_fpdis_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_vawatch"
864ldf_ld_fpdis_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_vawatch_super"
865ldf_ld_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_dataacc_vawatch"
866ldf_ld_fpdis_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_dataacc_vawatch"
867ldf_ld_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_vawatch"
868lddf_ldd_fpdis_vawatch_dmisalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_vawatch_dmisalgn_super"
869lddf_ldd_fpdis_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_vawatch"
870lddf_ldd_fpdis_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_vawatch_super"
871lddf_ldd_misalgn_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_misalgn_dataacc"
872lddf_ldd_dataacc_vawatch_dmisalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_dataacc_vawatch_dmisalgn"
873lddf_ldd_fpdis_vawatch_dmisalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_vawatch_dmisalgn"
874lddf_ldd_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_dataacc_vawatch"
875lddf_ldd_fpdis_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_dataacc_vawatch"
876#endif
877
878// Removed From FC 2005_10_06 lddf_ldd_fpdis_misalgn_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="lddf_ldd_fpdis_misalgn_dataacc"
879// Removed From FC 2005_10_06 ldf_ld_fpdis_misalgn_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_fpdis_misalgn_vawatch"
880ldf_ld_alldest ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_alldest"
881ldf_ld_alldest_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldf_ld_alldest_super"
882
883</runargs>
884
885//////////////////////////////
886// End of long diags
887//////////////////////////////
888
889
890<runargs -midas_args=-allow_tsb_conflicts -midas_args=-pal_diag_args=-thrd_count=4>
891
892ldaf_lda_fpdis ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis"
893ldaf_lda_fpdis_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_dataacc"
894ldaf_lda_fpdis_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_super"
895ldaf_lda_misalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn_super"
896
897
898<runargs -vcs_run_args=+l2warm=1> //Only one diag with cache warming
899ldaf_lda_fpdis_misalgn_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn_super"
900</runargs>
901
902<runargs -nofast_boot>
903ldaf_lda_fpdis_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_hyper"
904ldaf_lda_misalgn_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn_hyper"
905// Removed from FC 2005_10_10 ldaf_lda_vawatch_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_vawatch_hyper" -rtl_timeout=100000
906</runargs>
907
908</runargs>
909
910//////////////////////////////
911// Long diags (over 8hrs), not to be run in daily
912//////////////////////////////
913
914<runargs -midas_args=-allow_tsb_conflicts -midas_args=-pal_diag_args=-thrd_count=4>
915
916#if (!defined FC)
917ldaf_lda_fpdis_misalgn_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn_vawatch"
918ldaf_lda_fpdis_misalgn_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn_vawatch_super"
919ldaf_lda_misalgn_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn_vawatch"
920ldaf_lda_misalgn_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn_vawatch_super"
921
922ldaf_lda_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_dataacc_vawatch"
923ldaf_lda_fpdis_dataacc_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_dataacc_vawatch"
924ldaf_lda_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_vawatch"
925#endif // End if (!defined FC)
926
927<runargs -nofast_boot>
928ldaf_lda_fpdis_vawatch_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_vawatch_hyper"
929ldaf_lda_fpdis_misalgn_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn_hyper"
930
931// Removed from FC 2005_09_13
932#if (!defined FC)
933ldaf_lda_fpdis_misalgn_vawatch_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn_vawatch_hyper"
934ldaf_lda_alldest_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_alldest_hyper" -rtl_timeout=100000
935
936ldaf_lda_misalgn_vawatch_hyper ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn_vawatch_hyper"
937
938#endif // End if (!defined FC)
939
940</runargs>
941
942// Removed from FC 2005_09_13
943#if (!defined FC)
944
945ldaf_lda_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_vawatch_super"
946ldaf_lda_misalgn_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn_dataacc"
947ldaf_lda_fpdis_vawatch_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_vawatch_super"
948ldaf_lda_fpdis_misalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn"
949ldaf_lda_fpdis_misalgn_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_misalgn_dataacc"
950
951#endif // End if (!defined FC)
952
953ldaf_lda_dataacc ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_dataacc"
954ldaf_lda_fpdis_vawatch ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_fpdis_vawatch"
955ldaf_lda_alldest ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_alldest"
956ldaf_lda_alldest_super ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_alldest_super"
957ldaf_lda_misalgn ldf_alldest.pal -midas_args=-pal_diag_args=-name="ldaf_lda_misalgn"
958
959</runargs>
960
961//////////////////////////////
962// End of long diags
963//////////////////////////////
964
965
966</runargs>
967</arch_diags>
968
969<sys(cmp) name=sys(cmp)>
970
971
972////////////////////////////////////////////////////////////////////////////
973// CMT diags, 1 core
974
975<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 -midas_args=-DTHREAD_COUNT=2>
976
977cmp_park_self cmp_park_self.s -midas_args=-DSYNC_THREADS -midas_args=-allow_tsb_conflicts
978
979</runargs>
980</sys(cmp)>
981
982
983<sys(interrupt) name=sys(interrupt)>
984
985////////////////////////////////////////////////////////////////////////////
986// Single-threaded interrupt diags
987<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1>
988
989interrupt_INT_VEC_DIS interrupt_INT_VEC_DIS.s
990interrupt_INT_VEC_DIS_all2 interrupt_INT_VEC_DIS_all2.s
991interrupt_SWVR_INTR_R interrupt_SWVR_INTR_R.s
992interrupt_SWVR_INTR_W interrupt_SWVR_INTR_W.s
993interrupt_SWVR_INTR_W_all_vectors interrupt_SWVR_INTR_W_all_vectors.s
994interrupt_INTR_REC_priority interrupt_INTR_REC_priority.s
995interrupt_QUEUE_CPU_MONDO_trap interrupt_QUEUE_CPU_MONDO_trap.s
996interrupt_QUEUE_DEV_MONDO_trap interrupt_QUEUE_DEV_MONDO_trap.s
997interrupt_ncu_regs_rw interrupt_ncu_regs_rw.s
998interrupt_QUEUE_CPU_MONDO_mode interrupt_QUEUE_CPU_MONDO_mode.s
999interrupt_QUEUE_DEV_MONDO_mode interrupt_QUEUE_DEV_MONDO_mode.s
1000interrupt_DMU_CORE_BLK_enable1 interrupt_DMU_CORE_BLK_enable1.s
1001
1002</runargs>
1003////////////////////////////////////////////////////////////////////////////
1004// 2-threaded interrupt diags
1005<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 -midas_args=-DSYNC_THREADS >
1006
1007interrupt_SWVR_INTR_REC_mode interrupt_SWVR_INTR_REC_mode.s
1008interrupt_SWVR_INTR_R_mode interrupt_SWVR_INTR_R_mode.s
1009interrupt_SWVR_INTR_W_mode interrupt_SWVR_INTR_W_mode.s
1010
1011</runargs>
1012
1013
1014////////////////////////////////////////////////////////////////////////////
1015// Miscellaneous interrupt diags
1016
1017interrupt_pci_spurious_err interrupt_pci_spurious_err.s -nosas
1018
1019</sys(interrupt)>
1020
1021<sys(pll) name=sys(pll)>
1022<runargs -sas>
1023
1024<runargs -vcs_run_args=+bank_set_mask=3 -vcs_run_args=+core_set_mask=01>
1025memop_all_atomics_pll memop_all_atomics.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff -vcs_run_args=+pll_bypass -vcs_run_args=+NO_CCU_CSR_SLAM -vcs_run_args=+POR_pulse_width=4 -vcs_run_args=+gchkr_off
1026
1027</runargs>
1028</runargs>
1029
1030</sys(pll)>
1031
1032<sys(tcu_no_tck) name=sys(tcu_no_tck)>
1033<runargs -midas_args=-DINC_SOC_ERR_TRAPS -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off >
1034 tcu_csr_regs_rw tcu_csr_regs_rw.s -nosas
1035 tcu_regs_l2 tcu_regs_l2.s
1036 tcu_regs_soc tcu_regs_soc.s
1037 tcu_regs_bist tcu_regs_bist.s -nosas
1038</runargs>
1039
1040<runargs -midas_args=-DINC_SOC_ERR_TRAPS -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+MCU_REG_DEFAULT_VAL -vcs_run_args=+NO_MCU_CSR_SLAM>
1041 tcu_regs_dram tcu_regs_dram.s -nofast_boot
1042 tcu_regs_dram_2 tcu_regs_dram_2.s -nofast_boot
1043 tcu_regs_dram_piu tcu_regs_dram_piu.s -nofast_boot
1044</runargs>
1045
1046</sys(tcu_no_tck)>
1047
1048<sys(dbg) name=sys(dbg)>
1049<runargs -vcs_run_args=-DL2_7 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+50000 -nosas -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+DISABLE_L2_CHECKER -vcs_run_args=+BOOT_CODE_FINISH=13000000 -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+PEU_TEST>
1050Debug_Event_Mcu_Ctl2 Debug_Event_Mcu2.s
1051</runargs>
1052
1053<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off>
1054Debug_Event_L2_PABank0 Debug_Event_L2PaBank.s -midas_args=-DMCU0
1055Debug_Event_L2_PABank2 Debug_Event_L2PaBank.s -midas_args=-DMCU1
1056Debug_Event_L2_PABank4 Debug_Event_L2PaBank.s -midas_args=-DMCU2
1057Debug_Event_L2_PABank6 Debug_Event_L2PaBank.s -midas_args=-DMCU3
1058Debug_Event_L2_PABank1 Debug_Event_L2PaBankOdd.s -midas_args=-DMCU0
1059Debug_Event_L2_PABank3 Debug_Event_L2PaBankOdd.s -midas_args=-DMCU1
1060Debug_Event_L2_PABank5 Debug_Event_L2PaBankOdd.s -midas_args=-DMCU2
1061Debug_Event_L2_PABank7 Debug_Event_L2PaBankOdd.s -midas_args=-DMCU3
1062</runargs>
1063
1064
1065
1066
1067<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
1068Debug_Event_Mcu_Ctl0 Debug_Event_Mcu.s -midas_args=-DMCU0
1069Debug_Event_Mcu_Ctl1 Debug_Event_Mcu.s -midas_args=-DMCU1
1070Debug_Event_Mcu_Ctl2 Debug_Event_Mcu.s -midas_args=-DMCU2
1071Debug_Event_Mcu_Ctl3 Debug_Event_Mcu.s -midas_args=-DMCU3
1072</runargs>
1073
1074<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
1075Debug_Event_L2Bank0 Debug_Event_L2.s -midas_args=-DL2_0 -midas_args=-DMCU0
1076Debug_Event_L2Bank2 Debug_Event_L2.s -midas_args=-DL2_2 -midas_args=-DMCU1
1077Debug_Event_L2Bank4 Debug_Event_L2.s -midas_args=-DL2_4 -midas_args=-DMCU2
1078Debug_Event_L2Bank6 Debug_Event_L2.s -midas_args=-DL2_6 -midas_args=-DMCU3
1079</runargs>
1080
1081
1082<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+DISABLE_L2_CHECKER>
1083Debug_Event_L2Bank1 Debug_Event_L2Odd.s -midas_args=-DMCU0
1084Debug_Event_L2Bank3 Debug_Event_L2Odd.s -midas_args=-DMCU1
1085Debug_Event_L2Bank5 Debug_Event_L2Odd.s -midas_args=-DMCU2
1086Debug_Event_L2Bank7 Debug_Event_L2Odd.s -midas_args=-DMCU3
1087</runargs>
1088
1089
1090#ifndef FC_NO_NIU_T2
1091<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -midas_args=-DMCU1 -vcs_run_args=+ios_0in_ras_chk_off>
1092// Debug_Niu_Obs Debug_Niu_Mode.s
1093</runargs>
1094#endif
1095
1096</sys(dbg)>
1097
1098<runargs -vcs_run_args=+8_FBDIMMS -midas_args=-DPART_0_BASE=0x1000000000>
1099
1100<sys(ras)>
1101
1102// Applied for ALL Error diags
1103// esr mon off
1104// CEEN and NCEEN bit OFF
1105<runargs -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+100000 -midas_args=-DCREGS_L2_ERR_EN_REG_CEEN=0 -midas_args=-DCREGS_L2_ERR_EN_REG_NCEEN=0 -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+siu_mon_l2err>
1106
1107// L2 RAS DIAGS
1108<sys(err_l2) name=sys(err_l2)>
1109
1110// Need -nosas because of L2$ diagnostic load
1111// Use +L2_SCRUB_FREQ=1000 to speed simulation
1112// Use +L2_SCRUB_IDX=50 to match the corrupted address
1113n2_err_l2_LDSC_cecc_trap n2_err_l2_LDSC_cecc_trap.s -nosas -vcs_run_args=+L2_SCRUB_FREQ=1000 -vcs_run_args=+L2_SCRUB_IDX=50
1114n2_err_l2_LDSU_uecc_trap n2_err_l2_LDSU_uecc_trap.s -nosas -vcs_run_args=+L2_SCRUB_FREQ=1000 -vcs_run_args=+L2_SCRUB_IDX=50
1115
1116// Only for following few l2 error diags
1117<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS -midas_args=-DL2_LDAC_err>
1118
1119n2_err_l2_LDAC_tid_01.s n2_err_l2_LDAC_all_tids.s -midas_args=-DCMP_THREAD_START=0x03 -finish_mask=03
1120n2_err_l2_LDAC_tid_02.s n2_err_l2_LDAC_all_tids.s -midas_args=-DCMP_THREAD_START=0x05 -finish_mask=05
1121n2_err_l2_LDAC_tid_03.s n2_err_l2_LDAC_all_tids.s -midas_args=-DCMP_THREAD_START=0x09 -finish_mask=09
1122n2_err_l2_LDAC_tid_04.s n2_err_l2_LDAC_all_tids.s -midas_args=-DCMP_THREAD_START=0x11 -finish_mask=11
1123n2_err_l2_LDAC_tid_05.s n2_err_l2_LDAC_all_tids.s -midas_args=-DCMP_THREAD_START=0x21 -finish_mask=21
1124n2_err_l2_LDAC_tid_06.s n2_err_l2_LDAC_all_tids.s -midas_args=-DCMP_THREAD_START=0x41 -finish_mask=41
1125n2_err_l2_LDAC_tid_07.s n2_err_l2_LDAC_all_tids.s -midas_args=-DCMP_THREAD_START=0x81 -finish_mask=81
1126</runargs>
1127
1128//Only for following L2 RAS diags
1129<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS >
1130
1131n2_err_L2_LDWC_cecc_trap n2_err_L2_LDWC_cecc_trap.s
1132n2_err_L2_LDWC_cecc n2_err_L2_LDWC_cecc.s
1133n2_err_L2_LVC_cecc_trap n2_err_L2_LVC_cecc_trap.s
1134n2_err_L2_LVC_cecc n2_err_L2_LVC_cecc.s
1135n2_err_L2_LVC_cecc_Synd_check n2_err_L2_LVC_cecc_SyndCheck.s
1136n2_err_L2_LDWU_MEU_uecc n2_err_L2_LDWU_uecc.s
1137n2_err_l2_LDAC_st_cecc_trap n2_err_l2_LDAC_st_cecc_trap.s
1138n2_err_l2_LDAC_st_cecc n2_err_l2_LDAC_st_cecc.s
1139n2_err_l2_LDAC_cecc_trap n2_err_l2_LDAC_cecc_trap.s -midas_args=-DL2_LDAC_err
1140n2_err_l2_LDAC_cecc n2_err_l2_LDAC_cecc.s
1141n2_err_l2_LDAU_trap n2_err_l2_LDAU_uecc_trap.s
1142//n2_err_l2_LDAU_trap_inj n2_err_l2_trap_ErrInj.s -midas_args=-DLDAU -midas_args=-DL2_0 -vcs_run_args=+L2DA_INJECT_UE
1143n2_err_l2_LDAU_trap_2thrds n2_err_l2_LDAU_uecc_2thrds_trap.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
1144n2_err_l2_LDAU_uecc n2_err_l2_LDAU_uecc.s
1145n2_err_l2_LDAU_st_uecc_trap n2_err_l2_LDAU_st_uecc_trap.s -midas_args=-DL2_DWS_err
1146n2_err_l2_LDAU_st_uecc n2_err_l2_LDAU_st_uecc.s
1147n2_err_l2_LDWU_uecc n2_err_l2_LDWU_uecc.s
1148n2_err_l2_csrs n2_err_l2_csrs.s
1149n2_err_l2_LTC_cecc_trap n2_err_l2_LTC_cecc_trap.s
1150n2_err_l2_LTC_cecc n2_err_l2_LTC_cecc.s
1151n2_err_l2_LTC_4bnk_trap n2_err_l2_LTC_4bnk_cecc_trap.s -vcs_run_args=+bank_set_mask=3
1152n2_err_l2_LTC_L2off_trap n2_err_l2_LTC_cecc_trap_L2off.s -vcs_run_args=+gchkr_off
1153//n2_err_l2_LRU n2_err_l2_LRU.s
1154n2_err_l2_LDWU_uecc_trap n2_err_l2_LDWU_uecc_trap.s -midas_args=-DL2_DWS_err
1155
1156
1157// L2 Not Data diag, In Fc because MCU registers prog in FC
1158n2_err_L2_NotData_NDSP n2_err_L2_NotData.s -midas_args=-DL2_NDSP_err
1159n2_err_L2_NotData_NDSP_meu n2_err_L2_NotData_NDSP_meu.s
1160n2_err_L2_NotData_NDSP_meu_trap0 n2_err_L2_NotData_NDSP_meu_trap.s -midas_args=-DL2_NDSP_err -midas_args=-DL20
1161n2_err_L2_NotData_NDSP_meu_trap1 n2_err_L2_NotData_NDSP_meu_trap.s -midas_args=-DL2_NDSP_err -midas_args=-DL21
1162n2_err_L2_NotData_NDSP_meu_trap2 n2_err_L2_NotData_NDSP_meu_trap.s -midas_args=-DL2_NDSP_err -midas_args=-DL22
1163n2_err_L2_NotData_NDSP_meu_trap3 n2_err_L2_NotData_NDSP_meu_trap.s -midas_args=-DL2_NDSP_err -midas_args=-DL23
1164n2_err_L2_NotData_NDSP_meu_trap4 n2_err_L2_NotData_NDSP_meu_trap.s -midas_args=-DL2_NDSP_err -midas_args=-DL24
1165n2_err_L2_NotData_NDSP_meu_trap5 n2_err_L2_NotData_NDSP_meu_trap.s -midas_args=-DL2_NDSP_err -midas_args=-DL25
1166n2_err_L2_NotData_NDSP_meu_trap6 n2_err_L2_NotData_NDSP_meu_trap.s -midas_args=-DL2_NDSP_err -midas_args=-DL26
1167n2_err_L2_NotData_NDSP_meu_trap7 n2_err_L2_NotData_NDSP_meu_trap.s -midas_args=-DL2_NDSP_err -midas_args=-DL27
1168
1169// n2_err_L2_NotData_NDDM n2_err_L2_NotData_NDDM.s -midas_args=-DL2_NDSP_err -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off
1170// n2_err_L2_NotData_NDDM_meu n2_err_L2_NotData_NDDM_meu.s -midas_args=-DL2_NDDM_err -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off
1171// n2_err_L2_NotData_NDDM_meu_trap n2_err_L2_NotData_NDDM_meu_trap.s -midas_args=-DL2_NDDM_err -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off -midas_args=-DL20
1172
1173// n2_err_l2_LDRC_cecc_trap n2_err_l2_LDRC_cecc_trap.s -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off
1174// n2_err_l2_LDRU_cecc_trap n2_err_l2_LDRU_cecc_trap.s -vcs_run_args=+PEU_TEST -vcs_run_args=+PEU_MEM_Chkr_off
1175</runargs>
1176</sys(err_l2)>
1177
1178
1179// ADVANCED L2 RAS DIAGS
1180<sys(err_l2_ADV) name=sys(err_l2_ADV)>
1181
1182<runargs -nosas -midas_args=-DINC_SOC_ERR_TRAPS >
1183n2_err_dram_L2_Off_DAU_ld_mcu0 n2_err_dram_DAU_ld_trap_L2_Off.s -midas_args=-DMCU0
1184n2_err_dram_L2_Off_DAU_ld_mcu1 n2_err_dram_DAU_ld_trap_L2_Off.s -midas_args=-DMCU1
1185n2_err_dram_L2_Off_DAU_ld_mcu2 n2_err_dram_DAU_ld_trap_L2_Off.s -midas_args=-DMCU2
1186n2_err_dram_L2_Off_DAU_ld_mcu3 n2_err_dram_DAU_ld_trap_L2_Off.s -midas_args=-DMCU3
1187
1188n2_err_dram_L2_Off_DAC_st n2_err_dram_DAC_st_trap_L2_Off.s -midas_args=-DMCU0
1189n2_err_dram_L2_Off_DAU_st_mcu0 n2_err_dram_DAU_st_trap_L2_Off.s -midas_args=-DMCU0 -midas_args=-DL2_DWS_err
1190//n2_err_dram_L2_Off_DAU_st_mcu1 n2_err_dram_DAU_st_trap_L2_Off.s -midas_args=-DMCU1 -midas_args=-DL2_DWS_err
1191//n2_err_dram_L2_Off_DAU_st_mcu2 n2_err_dram_DAU_st_trap_L2_Off.s -midas_args=-DMCU2 -midas_args=-DL2_DWS_err
1192//n2_err_dram_L2_Off_DAU_st_mcu3 n2_err_dram_DAU_st_trap_L2_Off.s -midas_args=-DMCU3 -midas_args=-DL2_DWS_err
1193
1194n2_err_dram_L2_Off_DAC_ld_mcu0 n2_err_dram_DAC_ld_trap_L2_Off.s -midas_args=-DMCU0 -midas_args=-DL2_LDAC_err
1195n2_err_dram_L2_Off_DAC_ld_mcu1 n2_err_dram_DAC_ld_trap_L2_Off.s -midas_args=-DMCU1 -midas_args=-DL2_LDAC_err
1196n2_err_dram_L2_Off_DAC_ld_mcu2 n2_err_dram_DAC_ld_trap_L2_Off.s -midas_args=-DMCU2 -midas_args=-DL2_LDAC_err
1197n2_err_dram_L2_Off_DAC_ld_mcu3 n2_err_dram_DAC_ld_trap_L2_Off.s -midas_args=-DMCU3 -midas_args=-DL2_LDAC_err
1198
1199n2_err_L2_LVF_WrmRst_uecc n2_err_L2_LVF_uecc_WrmRst.s
1200//n2_err_L2_FatalErr_WrmRst n2_err_L2_FatalErr_WrmRst.s
1201
1202</runargs>
1203
1204<runargs -nosas >
1205n2_err_l2_LDAC_LDWC_noDAC n2_err_l2_LDAC_LDWC_noDAC.s
1206
1207</runargs>
1208</sys(err_l2_ADV)>
1209
1210//End of L2 Advanced Diags
1211
1212
1213// MCU Error diags; except FBD errors
1214<sys(err_mcu) name=sys(err_mcu)>
1215
1216
1217<runargs -midas_args=-DINC_SOC_ERR_TRAPS -midas_args=-DINC_MCU_ERR_REG>
1218
1219//-nosas to be debugged and removed
1220n2_err_mcu_csrs n2_err_mcu_csrs.s -vcs_run_args=+mcu_errmon_disable -nosas
1221
1222n2_err_dram_DAC_ld_mcu0 n2_err_dram_DAC_ld.s -midas_args=-DMCU0 -sas
1223n2_err_dram_DAC_ld_mcu1 n2_err_dram_DAC_ld.s -midas_args=-DMCU1
1224n2_err_dram_DAC_ld_mcu2 n2_err_dram_DAC_ld.s -midas_args=-DMCU2
1225n2_err_dram_DAC_ld_mcu3 n2_err_dram_DAC_ld.s -midas_args=-DMCU3
1226
1227n2_err_dram_DAC_ld_trap_mcu0 n2_err_dram_DAC_ld_trap.s -midas_args=-DMCU0
1228n2_err_dram_DAC_ld_trap_mcu1 n2_err_dram_DAC_ld_trap.s -midas_args=-DMCU1
1229n2_err_dram_DAC_ld_trap_mcu2 n2_err_dram_DAC_ld_trap.s -midas_args=-DMCU2
1230n2_err_dram_DAC_ld_trap_mcu3 n2_err_dram_DAC_ld_trap.s -midas_args=-DMCU3
1231
1232n2_err_dram_DAC_st_mcu0 n2_err_dram_DAC_st.s -midas_args=-DMCU0
1233n2_err_dram_DAC_st_mcu1 n2_err_dram_DAC_st.s -midas_args=-DMCU1
1234n2_err_dram_DAC_st_mcu2 n2_err_dram_DAC_st.s -midas_args=-DMCU2
1235n2_err_dram_DAC_st_mcu3 n2_err_dram_DAC_st.s -midas_args=-DMCU3
1236
1237n2_err_dram_DAC_st_trap n2_err_dram_DAC_st_trap.s
1238
1239n2_err_dram_DAU_st n2_err_dram_DAU_st.s
1240n2_err_dram_DAU_st_trap n2_err_dram_DAU_st_trap.s -midas_args=-DL2_DWS_err
1241
1242
1243// advanced Directed Diags
1244n2_err_dram_Mem_Poisn_L2Bank0 n2_err_dram_Mem_Poisn.s -midas_args=-DL2_0 -nosas
1245n2_err_dram_Mem_Poisn_L2Bank1 n2_err_dram_Mem_Poisn.s -midas_args=-DL2_1 -nosas
1246n2_err_all_4_mcu n2_err_all_4_mcu.s
1247
1248
1249</runargs>
1250
1251</sys(err_mcu)>
1252
1253// MCU Err Advanced Diags
1254<sys(err_mcu_ADV) name=sys(err_mcu_ADV)>
1255
1256<runargs -vcs_run_args=+mcu_errmon_disable >
1257
1258n2_err_dram_dac_dau_fbr_mcu0 n2_err_dram_dac_dau_fbr.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1259n2_err_dram_dac_dau_fbr_mcu1 n2_err_dram_dac_dau_fbr.s -midas_args=-DMCU1 -midas_args=-DERR_FIELD=Mcu1Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1260n2_err_dram_dac_dau_fbr_mcu2 n2_err_dram_dac_dau_fbr.s -midas_args=-DMCU2 -midas_args=-DERR_FIELD=Mcu2Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1261n2_err_dram_dac_dau_fbr_mcu3 n2_err_dram_dac_dau_fbr.s -midas_args=-DMCU3 -midas_args=-DERR_FIELD=Mcu3Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1262n2_err_dram_dau_fbr_mcu0 n2_err_dram_dau_fbr.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1263n2_err_dram_dau_fbr_mcu1 n2_err_dram_dau_fbr.s -midas_args=-DMCU1 -midas_args=-DERR_FIELD=Mcu1Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1264n2_err_dram_dau_fbr_mcu2 n2_err_dram_dau_fbr.s -midas_args=-DMCU2 -midas_args=-DERR_FIELD=Mcu2Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1265n2_err_dram_dau_fbr_mcu3 n2_err_dram_dau_fbr.s -midas_args=-DMCU3 -midas_args=-DERR_FIELD=Mcu3Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1266n2_err_dram_afe_NoMemOp n2_err_dram_afe_NoMemOp.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x1 -midas_args=-DINJ_ERR_SRC=1
1267n2_err_dram_sfe_NoMemOp n2_err_dram_sfe_NoMemOp.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1268
1269n2_err_dram_dac_dau_fbr_fbu_mcu0 n2_err_dram_dac_dau_fbr_fbu.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbu -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1270n2_err_dram_dac_dau_fbr_fbu_mcu1 n2_err_dram_dac_dau_fbr_fbu.s -midas_args=-DMCU1 -midas_args=-DERR_FIELD=Mcu1Fbu -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1271n2_err_dram_dac_dau_fbr_fbu_mcu2 n2_err_dram_dac_dau_fbr_fbu.s -midas_args=-DMCU2 -midas_args=-DERR_FIELD=Mcu2Fbu -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1272n2_err_dram_dac_dau_fbr_fbu_mcu3 n2_err_dram_dac_dau_fbr_fbu.s -midas_args=-DMCU3 -midas_args=-DERR_FIELD=Mcu3Fbu -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1273
1274</runargs>
1275
1276</sys(err_mcu_ADV)>
1277
1278
1279
1280// IOS Error diags
1281// runarg for all IOS diags
1282<runargs -vcs_run_args=+ios_0in_ras_chk_off >
1283<sys(ios_mcu_err) name=sys(ios_mcu_err)>
1284
1285<runargs -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable >
1286
1287//FBR
1288n2_err_Mcu0Fbr_C n2_err_mcu_int.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1289n2_err_Mcu0Fbr_AFE n2_err_mcu_int.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x1 -midas_args=-DINJ_ERR_SRC=1
1290n2_err_Mcu0Fbr_AA n2_err_mcu_int.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x2 -midas_args=-DINJ_ERR_SRC=2
1291n2_err_Mcu0Fbr_SFPE n2_err_mcu_int.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1292
1293
1294n2_err_Mcu0Fbr_C_trap n2_err_mcu_ios_fbr_trap.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1295n2_err_Mcu0Fbr_AFE_trap n2_err_mcu_ios_fbr_trap.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x1 -midas_args=-DINJ_ERR_SRC=1
1296n2_err_Mcu0Fbr_AA_trap n2_err_mcu_ios_fbr_trap.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x2 -midas_args=-DINJ_ERR_SRC=2
1297n2_err_Mcu0Fbr_SFPE_trap n2_err_mcu_ios_fbr_trap.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1298
1299n2_err_Mcu1Fbr_C n2_err_mcu_int.s -midas_args=-DMCU1 -midas_args=-DERR_FIELD=Mcu1Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1300n2_err_Mcu1Fbr_trap n2_err_mcu_ios_fbr_trap.s -midas_args=-DMCU1 -midas_args=-DERR_FIELD=Mcu1Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1301
1302n2_err_Mcu2Fbr_C n2_err_mcu_int.s -midas_args=-DMCU2 -midas_args=-DERR_FIELD=Mcu2Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1303n2_err_Mcu2Fbr_trap n2_err_mcu_ios_fbr_trap.s -midas_args=-DMCU2 -midas_args=-DERR_FIELD=Mcu2Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1304
1305n2_err_Mcu3Fbr_C n2_err_mcu_int.s -midas_args=-DMCU3 -midas_args=-DERR_FIELD=Mcu3Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1306n2_err_Mcu3Fbr_trap n2_err_mcu_ios_fbr_trap.s -midas_args=-DMCU3 -midas_args=-DERR_FIELD=Mcu3Fbr -midas_args=-DFBR -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1307
1308<runargs -vcs_run_args=+nb_crc_mon_disable >
1309
1310n2_err_Mcu0Fbu_C n2_err_mcu_int_fbu.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbu -midas_args=-DFBSYND=0x0 -midas_args=-DINJ_ERR_SRC=0
1311
1312n2_err_Mcu0Fbu_AFE n2_err_mcu_int_fbu.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbu -midas_args=-DFBSYND=0x1 -midas_args=-DINJ_ERR_SRC=1
1313
1314n2_err_Mcu0Fbu_AA n2_err_mcu_int_fbu_AA.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbu -midas_args=-DFBSYND=0x2 -midas_args=-DINJ_ERR_SRC=2
1315
1316n2_err_Mcu0Fbu_SFPE n2_err_mcu_int_fbu.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Fbu -midas_args=-DFBSYND=0x3 -midas_args=-DINJ_ERR_SRC=3
1317</runargs>
1318
1319//ECC
1320n2_err_Mcu0Ecc n2_err_mcu_int.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Ecc -midas_args=-DECC
1321n2_err_Mcu0Ecc_trap n2_err_mcu_ios_ecc_trap.s -midas_args=-DMCU0 -midas_args=-DERR_FIELD=Mcu0Ecc -midas_args=-DECC
1322
1323n2_err_Mcu1Ecc n2_err_mcu_int.s -midas_args=-DMCU1 -midas_args=-DERR_FIELD=Mcu1Ecc -midas_args=-DECC
1324n2_err_Mcu1Ecc_trap n2_err_mcu_ios_ecc_trap.s -midas_args=-DMCU1 -midas_args=-DERR_FIELD=Mcu1Ecc -midas_args=-DECC
1325
1326n2_err_Mcu2Ecc n2_err_mcu_int.s -midas_args=-DMCU2 -midas_args=-DERR_FIELD=Mcu2Ecc -midas_args=-DECC
1327n2_err_Mcu2Ecc_trap n2_err_mcu_ios_ecc_trap.s -midas_args=-DMCU2 -midas_args=-DERR_FIELD=Mcu2Ecc -midas_args=-DECC
1328
1329n2_err_Mcu3Ecc n2_err_mcu_int.s -midas_args=-DMCU3 -midas_args=-DERR_FIELD=Mcu3Ecc -midas_args=-DECC
1330n2_err_Mcu3Ecc_trap n2_err_mcu_ios_ecc_trap.s -midas_args=-DMCU3 -midas_args=-DERR_FIELD=Mcu3Ecc -midas_args=-DECC
1331
1332//FBR and ECC both
1333
1334</runargs>
1335
1336</sys(ios_mcu_err)>
1337
1338
1339
1340// IOS ncu error diags
1341
1342<sys(ios_ncu_err) name=sys(ios_ncu_err)>
1343
1344//temporarily disabling sas because of outstanding bug 103339; associated diag n2_err_NcuDmuCredit
1345n2_err_ncu_csrs n2_err_ncu_csrs.s -nosas
1346n2_err_ncu_ejr_ce_10 n2_err_ncu_ejr_ce_10.s
1347n2_err_ncu_esr_3 n2_err_ncu_esr_3.s
1348
1349n2_err_ncu_all_int n2_err_ncu_all_int.s
1350n2_err_ncu_NcuMondoTable n2_err_ncu_dmu_mondo.s -midas_args=-DERR_FIELD=NcuMondoTable -midas_args=-DTT=0x32
1351n2_err_ncu_NcuMondoFifo n2_err_ncu_dmu_mondo_2th.s -midas_args=-DERR_FIELD=NcuMondoFifo -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=2 -midas_args=-DTT=0x32
1352</sys(ios_ncu_err)>
1353
1354
1355</runargs>
1356
1357//all diags
1358</runargs>
1359
1360</sys(ras)>
1361
1362// Applied for ALL Error diags
1363// esr mon off
1364
1365<runargs -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -max_cycle=+500000 -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcu_errmon_disable >
1366
1367// This suit requires PEU
1368
1369// </sys(ios_adv_niu_ras)>
1370
1371<sys(ios_adv_ncu_ras) name=sys(ios_adv_ncu_ras)>
1372<runargs -vcs_run_args=+ios_0in_ras_chk_off >
1373
1374//NCU: using EJR
1375
1376n2_err_adv_NcuCtagUe_int n2_err_adv_piu_int_ejr.s -midas_args=-DERR_FIELD=NcuCtagUe -midas_args=-DTT=0x40 -vcs_run_args=+lsu_mon_off
1377n2_err_adv_NcuCtagCe_int n2_err_adv_piu_int_ejr.s -midas_args=-DERR_FIELD=NcuCtagCe -midas_args=-DTT=0x63
1378
1379n2_err_adv_NcuDataParity_mondo n2_err_adv_piu_int_ejr_nomondo.s -midas_args=-DERR_FIELD=NcuDataParity -vcs_run_args=+PEU_TEST
1380
1381//DMU
1382n2_err_adv_DmuNcuCredit_int n2_err_adv_piu_int_ejr.s -midas_args=-DERR_FIELD=DmuNcuCredit -midas_args=-DTT=0x40
1383
1384</runargs>
1385
1386</sys(ios_adv_ncu_ras)>
1387
1388
1389/////////////////////// Diags with follow up of Silicon Level Testing ////////////////////////////
1390
1391<sys(mcu_si_ras) name=sys(mcu_si_ras)>
1392n2_mcu_si_DSC n2_mcu_si_DSC.s -vcs_run_args=+l2cpx_mon_off -midas_args=-DMCU0
1393
1394</sys(mcu_si_ras)>
1395
1396// for all diags
1397
1398</runargs>
1399</runargs>
1400
1401
1402<tso_diags name=tso_diags>
1403
1404tso_n1_bcopy tso_n1_bcopy.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
1405tso_n1_binit1 tso_n1_binit1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
1406tso_n1_binit2 tso_n1_binit2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
1407
1408#if (! defined FC)
1409
1410tso_n1_binit3 tso_n1_binit3.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
1411tso_n1_cross_mod1 tso_n1_cross_mod1.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1412tso_n1_cross_mod101 tso_n1_cross_mod101.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1413tso_n1_cross_mod102 tso_n1_cross_mod102.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1414tso_n1_cross_mod103 tso_n1_cross_mod103.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1415tso_n1_cross_mod2 tso_n1_cross_mod2.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1416tso_n1_cross_mod201 tso_n1_cross_mod201.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1417tso_n1_cross_mod203 tso_n1_cross_mod203.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1418tso_n1_cross_mod3 tso_n1_cross_mod3.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+inst_check_off=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1419tso_n1_cross_mod4 tso_n1_cross_mod4.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
1420tso_n1_cross_mod5 tso_n1_cross_mod5.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1421tso_n1_cross_mod6_bug6372 tso_n1_cross_mod6_bug6372.s -midas_args=-DTHREAD_COUNT=4 -finish_mask=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=f
1422tso_n1_dekker1 tso_n1_dekker1.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1423tso_n1_dekker2 tso_n1_dekker2.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3
1424tso_n1_dekker10 tso_n1_dekker10.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1425tso_n1_dekker11 tso_n1_dekker11.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -vcs_run_args=+thread=3 -nosas
1426tso_n1_false_sharing1 tso_n1_false_sharing1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1427tso_n1_false_sharing2 tso_n1_false_sharing2.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
1428tso_n1_false_sharing_vershort tso_n1_false_sharing_vershort.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff
1429tso_n1_indirection1 tso_n1_indirection1.s -finish_mask=7 -midas_args=-DTHREAD_COUNT=3 -vcs_run_args=+show_delta -vcs_run_args=+thread=7 -nosas
1430tso_n1_indirection2 tso_n1_indirection2.s -finish_mask=7 -midas_args=-DTHREAD_COUNT=3 -vcs_run_args=+show_delta -vcs_run_args=+thread=7 -nosas
1431tso_n1_membar1 tso_n1_membar1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
1432tso_n1_mutex1 tso_n1_mutex1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1433tso_n1_mutex2_ldstub tso_n1_mutex2_ldstub.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1434tso_n1_mutex3_cas tso_n1_mutex3_cas.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1435tso_n1_mutex4_casx tso_n1_mutex4_casx.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1436tso_n1_mutex5_swap_casx tso_n1_mutex5_swap_casx.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1437tso_n1_prod_cons1 tso_n1_prod_cons1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1438tso_n1_prod_cons2 tso_n1_prod_cons2.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1439tso_n1_prod_cons_variation1_1 tso_n1_prod_cons_variation1_1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1440tso_n1_prod_cons_variation2_1 tso_n1_prod_cons_variation2_1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -vcs_run_args=+thread=ff -nosas
1441tso_n1_self_mod1 tso_n1_self_mod1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1442tso_n1_self_mod2 tso_n1_self_mod2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1443tso_n1_self_mod3 tso_n1_self_mod3.s -midas_args=-DCMP_THREAD_START=0x11 -finish_mask=11 -vcs_run_args=+show_delta
1444tso_n1_self_mod5 tso_n1_self_mod5.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1445tso_n1_self_mod6 tso_n1_self_mod6.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1446tso_n1_self_mod7 tso_n1_self_mod7.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1447tso_n1_self_mod8 tso_n1_self_mod8.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1448tso_n1_self_mod9 tso_n1_self_mod9.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1449tso_n1_self_mod10 tso_n1_self_mod10.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1450tso_n1_self_mod11 tso_n1_self_mod11.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1451tso_n1_self_mod101 tso_n1_self_mod101.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1452tso_n1_self_mod102 tso_n1_self_mod102.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1453tso_n1_self_mod103 tso_n1_self_mod103.s -finish_mask=11 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=11 -nosas
1454tso_n1_self_mod104 tso_n1_self_mod104.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1455tso_n1_self_mod105 tso_n1_self_mod105.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1456
1457tso_n1_self_mod106 tso_n1_self_mod106.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1458tso_n1_self_mod107 tso_n1_self_mod107.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1459tso_n1_self_mod108 tso_n1_self_mod108.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1460tso_n1_self_mod109 tso_n1_self_mod109.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1461tso_n1_self_mod110 tso_n1_self_mod110.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1462tso_n1_self_mod111 tso_n1_self_mod111.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1463tso_n1_self_mod201 tso_n1_self_mod201.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1464tso_n1_self_mod202 tso_n1_self_mod202.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1465tso_n1_self_mod203 tso_n1_self_mod203.s -finish_mask=11 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=11 -nosas
1466tso_n1_self_mod206 tso_n1_self_mod206.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1467tso_n1_self_mod207 tso_n1_self_mod207.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -vcs_run_args=+thread=1
1468tso_n1_starve0 tso_n1_starve0.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
1469tso_n1_starve1 tso_n1_starve1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
1470
1471#endif
1472
1473#if (defined FC)
1474
1475tso_n1_binit3 tso_n1_binit3.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff
1476tso_n1_cross_mod1 tso_n1_cross_mod1.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1477tso_n1_cross_mod101 tso_n1_cross_mod101.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1478tso_n1_cross_mod102 tso_n1_cross_mod102.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1479tso_n1_cross_mod103 tso_n1_cross_mod103.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1480tso_n1_cross_mod2 tso_n1_cross_mod2.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1481tso_n1_cross_mod201 tso_n1_cross_mod201.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1482tso_n1_cross_mod203 tso_n1_cross_mod203.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1483tso_n1_cross_mod3 tso_n1_cross_mod3.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+inst_check_off=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1484tso_n1_cross_mod4 tso_n1_cross_mod4.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff
1485tso_n1_cross_mod5 tso_n1_cross_mod5.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1486tso_n1_cross_mod6_bug6372 tso_n1_cross_mod6_bug6372.s -midas_args=-DTHREAD_COUNT=4 -finish_mask=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xf
1487tso_n1_dekker1 tso_n1_dekker1.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1488tso_n1_dekker2 tso_n1_dekker2.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3
1489tso_n1_dekker10 tso_n1_dekker10.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1490tso_n1_dekker11 tso_n1_dekker11.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x3 -nosas
1491tso_n1_false_sharing1 tso_n1_false_sharing1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1492tso_n1_false_sharing2 tso_n1_false_sharing2.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff
1493tso_n1_false_sharing_vershort tso_n1_false_sharing_vershort.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff
1494tso_n1_indirection1 tso_n1_indirection1.s -finish_mask=7 -midas_args=-DTHREAD_COUNT=3 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x7 -nosas
1495tso_n1_indirection2 tso_n1_indirection2.s -finish_mask=7 -midas_args=-DTHREAD_COUNT=3 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x7 -nosas
1496tso_n1_membar1 tso_n1_membar1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta
1497tso_n1_mutex1 tso_n1_mutex1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1498tso_n1_mutex2_ldstub tso_n1_mutex2_ldstub.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1499tso_n1_mutex3_cas tso_n1_mutex3_cas.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1500tso_n1_mutex4_casx tso_n1_mutex4_casx.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1501tso_n1_mutex5_swap_casx tso_n1_mutex5_swap_casx.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1502tso_n1_prod_cons1 tso_n1_prod_cons1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1503tso_n1_prod_cons2 tso_n1_prod_cons2.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1504tso_n1_prod_cons_variation1_1 tso_n1_prod_cons_variation1_1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1505tso_n1_prod_cons_variation2_1 tso_n1_prod_cons_variation2_1.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xff -nosas
1506tso_n1_self_mod1 tso_n1_self_mod1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1507tso_n1_self_mod2 tso_n1_self_mod2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1508tso_n1_self_mod3 tso_n1_self_mod3.s -finish_mask=11 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x11
1509tso_n1_self_mod5 tso_n1_self_mod5.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1510tso_n1_self_mod6 tso_n1_self_mod6.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1511tso_n1_self_mod7 tso_n1_self_mod7.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1512tso_n1_self_mod8 tso_n1_self_mod8.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1513tso_n1_self_mod9 tso_n1_self_mod9.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1514tso_n1_self_mod10 tso_n1_self_mod10.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1515tso_n1_self_mod11 tso_n1_self_mod11.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1516tso_n1_self_mod101 tso_n1_self_mod101.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1517tso_n1_self_mod102 tso_n1_self_mod102.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1518tso_n1_self_mod103 tso_n1_self_mod103.s -finish_mask=11 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=4 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x11 -nosas
1519tso_n1_self_mod104 tso_n1_self_mod104.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1520tso_n1_self_mod105 tso_n1_self_mod105.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1521
1522tso_n1_self_mod106 tso_n1_self_mod106.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1523tso_n1_self_mod107 tso_n1_self_mod107.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1524tso_n1_self_mod108 tso_n1_self_mod108.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1525tso_n1_self_mod109 tso_n1_self_mod109.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1526tso_n1_self_mod110 tso_n1_self_mod110.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1527tso_n1_self_mod111 tso_n1_self_mod111.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1528tso_n1_self_mod201 tso_n1_self_mod201.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1529tso_n1_self_mod202 tso_n1_self_mod202.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1530tso_n1_self_mod203 tso_n1_self_mod203.s -finish_mask=11 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DTHREAD_STRIDE=4 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x11 -nosas
1531tso_n1_self_mod206 tso_n1_self_mod206.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1532tso_n1_self_mod207 tso_n1_self_mod207.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0x1
1533tso_n1_starve0 tso_n1_starve0.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xf -vcs_run_args=+gchkr_off
1534tso_n1_starve1 tso_n1_starve1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xf -vcs_run_args=+gchkr_off
1535
1536#endif
1537
1538#if (! defined FC)
1539
1540tso_n1_prod_cons1_pio tso_n1_prod_cons1_pio.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
1541tso_n1_prod_cons2_pio tso_n1_prod_cons1_pio.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
1542tso_n1_dekker1_pio tso_n1_dekker1_pio.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+thread=3
1543tso_n1_dekker2_pio tso_n1_dekker2_pio.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -vcs_run_args=+thread=3
1544tso_n1_dekker7 tso_n1_dekker7.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
1545tso_n1_dekker8 tso_n1_dekker8.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
1546tso_n1_dekker9 tso_n1_dekker9.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
1547tso_n1_peterson1 tso_n1_peterson1.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
1548tso_n1_peterson2 tso_n1_peterson2.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
1549tso_n1_peterson3 tso_n1_peterson3.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -vcs_run_args=+thread=ff -sas
1550
1551#endif
1552
1553#if (defined FC)
1554
1555tso_n1_prod_cons1_pio tso_n1_prod_cons1_pio.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -midas_args=-DCMP_THREAD_START=0xff -sas
1556tso_n1_prod_cons2_pio tso_n1_prod_cons1_pio.s -finish_mask=ff -midas_args=-DTHREAD_COUNT=8 -midas_args=-DCMP_THREAD_START=0xff -sas
1557tso_n1_dekker1_pio tso_n1_dekker1_pio.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DCMP_THREAD_START=0x3
1558tso_n1_dekker2_pio tso_n1_dekker2_pio.s -finish_mask=3 -midas_args=-DTHREAD_COUNT=2 -midas_args=-DCMP_THREAD_START=0x3
1559tso_n1_dekker7 tso_n1_dekker7.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -midas_args=-DCMP_THREAD_START=0xff -sas
1560tso_n1_dekker8 tso_n1_dekker8.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -midas_args=-DCMP_THREAD_START=0xff -sas
1561tso_n1_dekker9 tso_n1_dekker9.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -midas_args=-DCMP_THREAD_START=0xff -sas
1562tso_n1_peterson1 tso_n1_peterson1.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -midas_args=-DCMP_THREAD_START=0xff -sas
1563tso_n1_peterson2 tso_n1_peterson2.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -midas_args=-DCMP_THREAD_START=0xff -sas
1564tso_n1_peterson3 tso_n1_peterson3.pal -finish_mask=ff -midas_args=-pal_diag_args=8 -midas_args=-DTHREAD_COUNT=8 -midas_args=-DCMP_THREAD_START=0xff -sas
1565
1566#endif
1567
1568#if (!defined CCM && !defined CMP)
1569
1570#if (! defined FC)
1571
1572tso_n1_ld_starve1 tso_n1_ld_starve1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
1573tso_n1_ld_starve2 tso_n1_ld_starve2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -vcs_run_args=+thread=f -vcs_run_args=+gchkr_off
1574
1575#endif
1576
1577#if (defined FC)
1578
1579tso_n1_ld_starve1 tso_n1_ld_starve1.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xf -vcs_run_args=+gchkr_off
1580tso_n1_ld_starve2 tso_n1_ld_starve2.s -finish_mask=1 -midas_args=-DTHREAD_COUNT=4 -vcs_run_args=+show_delta -midas_args=-DCMP_THREAD_START=0xf -vcs_run_args=+gchkr_off
1581
1582#endif
1583
1584#endif
1585
1586</tso_diags>
1587
1588<sys(ccu_clk_ratios) name=sys(ccu_clk_ratios)>
1589
1590 <fc_ccu_166> // fc bench: default is 166mhz sys clk
1591
1592 <runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1> // single thread (ie. thread 0)
1593 <runargs -midas_args=-DRESET_STAT_CHECK> // must specify this option when doing WMR reset
1594 <runargs -nofast_boot -vcs_run_args=+NO_CCU_CSR_SLAM -midas_args=-DCCU_REG_PROG -midas_args=-DWARM_RESET_INIT>
1595 <runargs -sas -midas_args=-DBOOTPROM_INIT>
1596 <runargs -vcs_run_args=+SSI_CLK_4 -vcs_run_args=+show_delta>
1597 <runargs -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+l2esr_mon_off>
1598 <runargs -vcs_run_args=+ccu_checker>
1599 memop_all_atomics_CMPDR_RATIO_2_00_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_2_00
1600 memop_all_atomics_CMPDR_RATIO_2_25_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_2_25
1601 memop_all_atomics_CMPDR_RATIO_2_50_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_2_50
1602 memop_all_atomics_CMPDR_RATIO_2_75_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_2_75
1603 memop_all_atomics_CMPDR_RATIO_3_00_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_3_00
1604 memop_all_atomics_CMPDR_RATIO_3_25_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_3_25
1605 memop_all_atomics_CMPDR_RATIO_3_50_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_3_50
1606 memop_all_atomics_CMPDR_RATIO_3_75_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_3_75
1607 memop_all_atomics_CMPDR_RATIO_4_00_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_4_00
1608 memop_all_atomics_CMPDR_RATIO_4_25_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_4_25
1609 memop_all_atomics_CMPDR_RATIO_4_50_sysclk166 memop_all_atomics.s -midas_args=-DCMPDR_RATIO_4_50
1610 </runargs>
1611 </runargs>
1612 </runargs>
1613 </runargs>
1614 </runargs>
1615 </runargs>
1616 </runargs>
1617
1618</fc_ccu_166>
1619</sys(ccu_clk_ratios)>
1620
1621<sys(mcu) name=sys(mcu)>
1622
1623
1624#if (!defined FC)
1625<runargs -sas -vcs_run -vcs_run_args=+8_FBDIMMS -midas_args=-allow_tsb_conflicts -vcs_run_args=+thread=ff>
1626#endif
1627#if (defined FC)
1628<runargs -sas -vcs_run -vcs_run_args=+8_FBDIMMS -midas_args=-allow_tsb_conflicts -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff >
1629#endif
1630
1631n2_mcu_0_all_bcopy_all_banks n2_mcu_0_all_bcopy_all_banks.s
1632</runargs>
1633
1634<runargs -sas -vcs_run_args=+8_FBDIMMS >
1635n2_mcu_0_all_fbdimm_rkhi_mcu0 n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU0 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
1636n2_mcu_0_all_fbdimm_rkhi_mcu1 n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU1 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
1637n2_mcu_0_all_fbdimm_rkhi_mcu2 n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU2 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
1638n2_mcu_0_all_fbdimm_rkhi_mcu3 n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU3 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
1639
1640n2_mcu_0_all_fbdimm_rkhi_mcu0_L2off n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU0 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
1641n2_mcu_0_all_fbdimm_rkhi_mcu1_L2off n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU1 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
1642n2_mcu_0_all_fbdimm_rkhi_mcu2_L2off n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU2 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
1643n2_mcu_0_all_fbdimm_rkhi_mcu3_L2off n2_mcu_0_all_fbdimm_rkhi.s -midas_args=-DMCU3 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff -midas_args=-DL2_OFF -vcs_run_args=+gchkr_off
1644
1645n2_all_mcu_all_l2_8th n2_all_mcu_all_l2.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
1646n2_all_th_ldst_8th n2_all_th_ldst.s -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff
1647
1648</runargs>
1649
1650</sys(mcu)>
1651
1652<sys(cmp) name=sys(cmp)>
1653
1654n2_cmp_upk_pk_upk n2_cmp_upk_pk_upk.s -finish_mask=3 -sas
1655n2_cmp_upk_pk_upk_nosas n2_cmp_upk_pk_upk.s -finish_mask=3 -nosas
1656
1657ncu_1core_wakup ncu_1core_wakup.s -finish_mask=0x2b -sas -midas_args=-DPART_0_BASE=0x200000000
1658ncu_ssi_rw ncu_ssi_rw.s -finish_mask=0x1 -nofast_boot -sas -midas_args=-DPART_0_BASE=0x200000000
1659ncu_ssi_rw_b2b ncu_ssi_rw_b2b.s -finish_mask=0x1 -nofast_boot -sas -midas_args=-DPART_0_BASE=0x200000000
1660
1661</sys(cmp)>
1662
1663</runargs>
1664</runargs>
1665
1666</runargs>
1667
1668
1669</runargs>
1670</runargs>
1671</sys(all_T2)>
1672
1673
1674//////////////////////////////////////////////////////////////////////
1675
1676
1677#ifdef FC
1678#undef FC
1679#undef FC8
1680#undef sys
1681#undef SYSNAME
1682#undef ALL_THREADS
1683#endif
1684
Full OpenSPARC design & verification tarball including full HDL.