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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / cmp / cmp_top.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cmp_top.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module tb_top;
36
37`include "cpu.h"
38`include "cmp.vh"
39
40 // Global registers & values
41 reg [63:0] finished_tids ;
42 integer last_act_cycle ;
43 integer th_last_act_cycle[63:0];
44
45 wire [63:0] gOutOfBoot; // Vera Interface signal. Vera drives.
46
47 // Other signals
48 reg SystemClock ;
49 reg reset;
50 reg arst;
51
52 // I/O to DUT
53
54 // Outputs from L2 BFMs to LDST_sync
55`ifdef NOL2RTL
56 wire [39:0] b0_cpx_pa;
57 wire [145:0] b0_cpx_pkt;
58 wire [39:0] b1_cpx_pa;
59 wire [145:0] b1_cpx_pkt;
60 wire [39:0] b2_cpx_pa;
61 wire [145:0] b2_cpx_pkt;
62 wire [39:0] b3_cpx_pa;
63 wire [145:0] b3_cpx_pkt;
64 wire [39:0] b4_cpx_pa;
65 wire [145:0] b4_cpx_pkt;
66 wire [39:0] b5_cpx_pa;
67 wire [145:0] b5_cpx_pkt;
68 wire [39:0] b6_cpx_pa;
69 wire [145:0] b6_cpx_pkt;
70 wire [39:0] b7_cpx_pa;
71 wire [145:0] b7_cpx_pkt;
72 wire [2:0] b0_cpx_cid;
73 wire b0_cpx_ctrue;
74 wire b0_cpx_swap;
75 wire [2:0] b1_cpx_cid;
76 wire b1_cpx_ctrue;
77 wire b1_cpx_swap;
78 wire [2:0] b2_cpx_cid;
79 wire b2_cpx_ctrue;
80 wire b2_cpx_swap;
81 wire [2:0] b3_cpx_cid;
82 wire b3_cpx_ctrue;
83 wire b3_cpx_swap;
84 wire [2:0] b4_cpx_cid;
85 wire b4_cpx_ctrue;
86 wire b4_cpx_swap;
87 wire [2:0] b5_cpx_cid;
88 wire b5_cpx_ctrue;
89 wire b5_cpx_swap;
90 wire [2:0] b6_cpx_cid;
91 wire b6_cpx_ctrue;
92 wire b6_cpx_swap;
93 wire [2:0] b7_cpx_cid;
94 wire b7_cpx_ctrue;
95 wire b7_cpx_swap;
96`endif
97 // for NCU BFM, always present
98 wire [39:0] b8_cpx_pa;
99 wire [145:0] b8_cpx_pkt;
100 wire [2:0] b8_cpx_cid;
101 wire b8_cpx_ctrue;
102 wire b8_cpx_swap;
103
104 reg ccu_slow_cmp_sync_en;
105 reg ccu_cmp_slow_sync_en;
106 integer rand_sync_en_skew;
107 integer sync_en_delay;
108 reg [31:0] rand32;
109 integer half_period;
110
111 // debug, remove
112// wire [1:0] count0;
113// wire [1:0] count1;
114// wire [1:0] count2;
115// wire [1:0] count3;
116// wire [1:0] count4;
117// wire [1:0] count5;
118// wire [1:0] count6;
119// wire [1:0] count7;
120
121 // error/warn count tasks and integers and plusargs
122 `include "errorCountTasks.v"
123
124 // handle thread enables and all CMP register details
125 `include "cmp_tasks.v"
126
127 // initial values
128 initial begin
129 finished_tids = 0;
130 last_act_cycle = 0;
131 cmp_core_running_rw = 64'h0;
132
133 end
134
135
136
137
138 //----------------------------------------------------------
139 // Clock Generator
140 //
141
142 initial begin
143 // This is needed to prevent an X->0|1 edge at time zero.
144 // See VCS manual "Time Zero Race Conditions" for info.
145 SystemClock = 1'bx;
146 #1 SystemClock = 0;
147 #49 SystemClock = 1;
148 SystemClock = 1'b0;
149 half_period = `TOP.core_period/2;
150
151 // core_period is defined in misc_tasks.v
152 forever begin
153 #(half_period)
154 SystemClock = ~SystemClock;
155 end
156 end
157
158 assign `CPU.ccu_cmp_io_sync_en = ccu_slow_cmp_sync_en;
159 assign `CPU.ccu_io_cmp_sync_en = ccu_cmp_slow_sync_en;
160 initial begin
161 // This is needed to prevent an X->0|1 edge at time zero.
162 // See VCS manual "Time Zero Race Conditions" for info.
163 ccu_slow_cmp_sync_en = 1'bx;
164 ccu_cmp_slow_sync_en = 1'bx;
165 #1
166 ccu_slow_cmp_sync_en = 0;
167 ccu_cmp_slow_sync_en = 0;
168 @(posedge tb_top.cpu.cmp_gclk_c3_spc0);
169 rand32 = $random(`PARGS.seed);
170 repeat (rand32[17:16]) @(posedge tb_top.cpu.cmp_gclk_c3_spc0);
171 rand_sync_en_skew = rand32[28:25] + 10; sync_en_delay = `TOP.core_period;
172 #rand_sync_en_skew
173 ccu_slow_cmp_sync_en = 1;
174 forever begin
175 #sync_en_delay
176 ccu_slow_cmp_sync_en = 0;
177 #sync_en_delay
178 ccu_cmp_slow_sync_en = 1;
179 #sync_en_delay
180 ccu_cmp_slow_sync_en = 0;
181 #sync_en_delay
182 ccu_slow_cmp_sync_en = 1;
183 end
184 end
185
186
187 initial begin
188
189 // review to enable as needed
190// `ifdef CORE_0 force `CPU.spc0.ncu_spc_l2_idx_hash_en = 0; `endif
191// `ifdef CORE_1 force `CPU.spc1.ncu_spc_l2_idx_hash_en = 0; `endif
192// `ifdef CORE_2 force `CPU.spc2.ncu_spc_l2_idx_hash_en = 0; `endif
193// `ifdef CORE_3 force `CPU.spc3.ncu_spc_l2_idx_hash_en = 0; `endif
194// `ifdef CORE_4 force `CPU.spc4.ncu_spc_l2_idx_hash_en = 0; `endif
195// `ifdef CORE_5 force `CPU.spc5.ncu_spc_l2_idx_hash_en = 0; `endif
196// `ifdef CORE_6 force `CPU.spc6.ncu_spc_l2_idx_hash_en = 0; `endif
197// `ifdef CORE_7 force `CPU.spc7.ncu_spc_l2_idx_hash_en = 0; `endif
198
199
200 // start reset
201 reset = 1'b0;
202 arst = 1'b0;
203 #1550
204
205 // end reset
206 @(negedge SystemClock);
207 @(posedge SystemClock) begin
208 reset = 1'b1;
209 repeat (10) @(posedge SystemClock);
210 arst = 1'b1;
211 repeat (10) @(posedge SystemClock);
212 end // @ SystemClock
213
214 end // initial
215
216
217
218// force L2 cache on
219 initial begin
220
221`ifndef NOL2RTL
222
223 while (tb_top.in_reset !== 0 || tb_top.in_reset_core !== 0) #100;
224 repeat (2) @(posedge tb_top.cpu.l2clk);
225
226// RTL_NO_BNKXX not used by N2, we always build in all banks for N2.
227// these defs are always not defined for N2.
228`ifndef RTL_NO_BNK01
229 force tb_top.cpu.l2t0.csr.arbdat_csr_inst_wr_data_c8[0] = 0;
230 force tb_top.cpu.l2t0.csr.csreg_csr_wr_en_c8 = 1;
231 force tb_top.cpu.l2t1.csr.arbdat_csr_inst_wr_data_c8[0] = 0;
232 force tb_top.cpu.l2t1.csr.csreg_csr_wr_en_c8 = 1;
233 @(negedge tb_top.cpu.l2t1.csr.l1clk);
234 @(posedge tb_top.cpu.l2t1.csr.l1clk);
235 @(negedge tb_top.cpu.l2t1.csr.l1clk);
236 release tb_top.cpu.l2t0.csr.arbdat_csr_inst_wr_data_c8[0];
237 release tb_top.cpu.l2t0.csr.csreg_csr_wr_en_c8;
238 release tb_top.cpu.l2t1.csr.arbdat_csr_inst_wr_data_c8[0];
239 release tb_top.cpu.l2t1.csr.csreg_csr_wr_en_c8;
240`endif
241`ifndef RTL_NO_BNK23
242 force tb_top.cpu.l2t2.csr.arbdat_csr_inst_wr_data_c8[0] = 0;
243 force tb_top.cpu.l2t2.csr.csreg_csr_wr_en_c8 = 1;
244 force tb_top.cpu.l2t3.csr.arbdat_csr_inst_wr_data_c8[0] = 0;
245 force tb_top.cpu.l2t3.csr.csreg_csr_wr_en_c8 = 1;
246 @(negedge tb_top.cpu.l2t2.csr.l1clk);
247 @(posedge tb_top.cpu.l2t2.csr.l1clk);
248 @(negedge tb_top.cpu.l2t2.csr.l1clk);
249 release tb_top.cpu.l2t2.csr.arbdat_csr_inst_wr_data_c8[0];
250 release tb_top.cpu.l2t2.csr.csreg_csr_wr_en_c8;
251 release tb_top.cpu.l2t3.csr.arbdat_csr_inst_wr_data_c8[0];
252 release tb_top.cpu.l2t3.csr.csreg_csr_wr_en_c8;
253`endif
254`ifndef RTL_NO_BNK45
255 force tb_top.cpu.l2t4.csr.arbdat_csr_inst_wr_data_c8[0] = 0;
256 force tb_top.cpu.l2t4.csr.csreg_csr_wr_en_c8 = 1;
257 force tb_top.cpu.l2t5.csr.arbdat_csr_inst_wr_data_c8[0] = 0;
258 force tb_top.cpu.l2t5.csr.csreg_csr_wr_en_c8 = 1;
259 @(negedge tb_top.cpu.l2t4.csr.l1clk);
260 @(posedge tb_top.cpu.l2t4.csr.l1clk);
261 @(negedge tb_top.cpu.l2t4.csr.l1clk);
262 release tb_top.cpu.l2t4.csr.arbdat_csr_inst_wr_data_c8[0];
263 release tb_top.cpu.l2t4.csr.csreg_csr_wr_en_c8;
264 release tb_top.cpu.l2t5.csr.arbdat_csr_inst_wr_data_c8[0];
265 release tb_top.cpu.l2t5.csr.csreg_csr_wr_en_c8;
266`endif
267`ifndef RTL_NO_BNK67
268 force tb_top.cpu.l2t6.csr.arbdat_csr_inst_wr_data_c8[0] = 0;
269 force tb_top.cpu.l2t6.csr.csreg_csr_wr_en_c8 = 1;
270 force tb_top.cpu.l2t7.csr.arbdat_csr_inst_wr_data_c8[0] = 0;
271 force tb_top.cpu.l2t7.csr.csreg_csr_wr_en_c8 = 1;
272 @(negedge tb_top.cpu.l2t6.csr.l1clk);
273 @(posedge tb_top.cpu.l2t6.csr.l1clk);
274 @(negedge tb_top.cpu.l2t6.csr.l1clk);
275 release tb_top.cpu.l2t6.csr.arbdat_csr_inst_wr_data_c8[0];
276 release tb_top.cpu.l2t6.csr.csreg_csr_wr_en_c8;
277 release tb_top.cpu.l2t7.csr.arbdat_csr_inst_wr_data_c8[0];
278 release tb_top.cpu.l2t7.csr.csreg_csr_wr_en_c8;
279`endif
280
281`endif
282 end // initial
283
284 initial begin
285 // Partial bank modes...
286 // these are after time 0 and over-ride time 0 forces
287 // based on missing cache banks or dissabled banks.
288 // bank_set_mask should be consistant with any missing banks
289 // that are not built in by use of RTL_NO_BNKxx defines.
290
291 #0 // wait for plus arg processing to complete.
292 if (`PARGS.bank_set_mask) begin
293 force `CPU.ncu_spc_pm = 1;
294 force `CPU.ncu_l2t_pm = 1;
295 force `CPU.ncu_sii_pm = 1;
296 force `CPU.ncu_mcu_pm = 1;
297 force `CPU.ncu_spc_ba01 = `PARGS.bank_set_mask[0];
298 force `CPU.ncu_spc_ba23 = `PARGS.bank_set_mask[1];
299 force `CPU.ncu_spc_ba45 = `PARGS.bank_set_mask[2];
300 force `CPU.ncu_spc_ba67 = `PARGS.bank_set_mask[3];
301 force `CPU.ncu_l2t_ba01 = `PARGS.bank_set_mask[0];
302 force `CPU.ncu_l2t_ba23 = `PARGS.bank_set_mask[1];
303 force `CPU.ncu_l2t_ba45 = `PARGS.bank_set_mask[2];
304 force `CPU.ncu_l2t_ba67 = `PARGS.bank_set_mask[3];
305 force `CPU.ncu_sii_ba01 = `PARGS.bank_set_mask[0];
306 force `CPU.ncu_sii_ba23 = `PARGS.bank_set_mask[1];
307 force `CPU.ncu_sii_ba45 = `PARGS.bank_set_mask[2];
308 force `CPU.ncu_sii_ba67 = `PARGS.bank_set_mask[3];
309 force `CPU.ncu_mcu_ba01 = `PARGS.bank_set_mask[0];
310 force `CPU.ncu_mcu_ba23 = `PARGS.bank_set_mask[1];
311 force `CPU.ncu_mcu_ba45 = `PARGS.bank_set_mask[2];
312 force `CPU.ncu_mcu_ba67 = `PARGS.bank_set_mask[3];
313 end
314
315 end // initial
316
317
318
319
320 //----------------------------------------------------------
321 // Bench Code Instantiation
322
323
324 // +args and the vars they set.
325 // use `PARGS.var to get value
326 // +args should be processed first so other initial blocks can use
327 // the values. Any initial block that uses `PARGS.var should have a #0 first.
328 //
329 // defines globals and inits them first.
330 // has an initial block that reads +args and sets some values.
331 verif_args verif_args();
332
333 nas_top nas_top ();
334
335 `ifdef CORE_0 nas_probes0 intf0(); `endif
336 `ifdef CORE_1 nas_probes1 intf1(); `endif
337 `ifdef CORE_2 nas_probes2 intf2(); `endif
338 `ifdef CORE_3 nas_probes3 intf3(); `endif
339 `ifdef CORE_4 nas_probes4 intf4(); `endif
340 `ifdef CORE_5 nas_probes5 intf5(); `endif
341 `ifdef CORE_6 nas_probes6 intf6(); `endif
342 `ifdef CORE_7 nas_probes7 intf7(); `endif
343
344 tlb_sync tlb_sync ();
345
346 ldst_sync ldst_sync ();
347
348 int_sync int_sync ();
349
350 err_sync err_sync ();
351
352 reg_slam reg_slam ();
353
354 monitors monitors ();
355
356 l2_scrub l2_scrub ();
357
358 //----------------------------------------------------------
359 // Device Under Test
360 //
361
362 cpu cpu ();
363
364 // clocks
365
366 assign cmp_gclk_c3_spc0 = SystemClock; // cmp_gclk_c1_r[1])
367 assign cmp_gclk_c3_spc1 = SystemClock;
368 assign cmp_gclk_c3_spc2 = SystemClock;
369 assign cmp_gclk_c3_spc3 = SystemClock;
370 assign cmp_gclk_c3_spc4 = SystemClock;
371 assign cmp_gclk_c3_spc5 = SystemClock;
372 assign cmp_gclk_c3_spc6 = SystemClock;
373 assign cmp_gclk_c3_spc7 = SystemClock;
374 assign gl_spc0_clk_stop = 0;
375 assign gl_spc1_clk_stop = 0;
376 assign gl_spc2_clk_stop = 0;
377 assign gl_spc3_clk_stop = 0;
378 assign gl_spc4_clk_stop = 0;
379 assign gl_spc5_clk_stop = 0;
380 assign gl_spc6_clk_stop = 0;
381 assign gl_spc7_clk_stop = 0;
382
383 assign cmp_gclk_c2_ccx_left = SystemClock;
384 assign cmp_gclk_c2_ccx_right = SystemClock;
385 assign gl_ccx_clk_stop_left = 0;
386 assign gl_ccx_clk_stop_right = 0;
387
388 assign cmp_gclk_c3_l2d0 = SystemClock;
389 assign cmp_gclk_c3_l2d1 = SystemClock;
390 assign cmp_gclk_c3_l2d2 = SystemClock;
391 assign cmp_gclk_c3_l2d3 = SystemClock;
392 assign cmp_gclk_c3_l2d4 = SystemClock;
393 assign cmp_gclk_c3_l2d5 = SystemClock;
394 assign cmp_gclk_c3_l2d6 = SystemClock;
395 assign cmp_gclk_c3_l2d7 = SystemClock;
396
397 assign gl_l2d0_clk_stop = 0;
398 assign gl_l2d1_clk_stop = 0;
399 assign gl_l2d2_clk_stop = 0;
400 assign gl_l2d3_clk_stop = 0;
401 assign gl_l2d4_clk_stop = 0;
402 assign gl_l2d5_clk_stop = 0;
403 assign gl_l2d6_clk_stop = 0;
404 assign gl_l2d7_clk_stop = 0;
405
406 assign cmp_gclk_c3_l2t0 = SystemClock;
407 assign cmp_gclk_c3_l2t1 = SystemClock;
408 assign cmp_gclk_c3_l2t2 = SystemClock;
409 assign cmp_gclk_c3_l2t3 = SystemClock;
410 assign cmp_gclk_c3_l2t4 = SystemClock;
411 assign cmp_gclk_c3_l2t5 = SystemClock;
412 assign cmp_gclk_c3_l2t6 = SystemClock;
413 assign cmp_gclk_c3_l2t7 = SystemClock;
414
415 assign gl_l2t0_clk_stop = 0;
416 assign gl_l2t1_clk_stop = 0;
417 assign gl_l2t2_clk_stop = 0;
418 assign gl_l2t3_clk_stop = 0;
419 assign gl_l2t4_clk_stop = 0;
420 assign gl_l2t5_clk_stop = 0;
421 assign gl_l2t6_clk_stop = 0;
422 assign gl_l2t7_clk_stop = 0;
423
424 assign `CPU.l2clk = SystemClock;
425 //assign `CPU.efu_ncu_fuse_clk1 = SystemClock;
426
427
428
429 // Force outputs of Vera to 0,1 when driven to Z - NCU interface
430 // need !!!
431 assign (weak0, weak1) `CPU.ncu_cpx_req_cq = 8'b0;
432 assign (weak0, weak1) `CPU.ncu_cpx_data_ca = 146'b0;
433 assign (weak0, weak1) `CPU.ncu_pcx_stall_pq = 1'b0;
434
435 // for time zero, CCX inputs from vera BFMs
436 // vera drives later
437`ifdef NOL2RTL
438 assign (weak0, weak1) `CPU.sctag0_cpx_atom_cq = 0;
439 assign (weak0, weak1) `CPU.sctag0_cpx_req_cq = 0;
440 assign (weak0, weak1) `CPU.sctag0_cpx_data_ca = 0;
441 assign (weak0, weak1) `CPU.sctag0_pcx_stall_pq = 0;
442 assign (weak0, weak1) `CPU.sctag1_cpx_atom_cq = 0;
443 assign (weak0, weak1) `CPU.sctag1_cpx_req_cq = 0;
444 assign (weak0, weak1) `CPU.sctag1_cpx_data_ca = 0;
445 assign (weak0, weak1) `CPU.sctag1_pcx_stall_pq = 0;
446 assign (weak0, weak1) `CPU.sctag2_cpx_atom_cq = 0;
447 assign (weak0, weak1) `CPU.sctag2_cpx_req_cq = 0;
448 assign (weak0, weak1) `CPU.sctag2_cpx_data_ca = 0;
449 assign (weak0, weak1) `CPU.sctag2_pcx_stall_pq = 0;
450 assign (weak0, weak1) `CPU.sctag3_cpx_atom_cq = 0;
451 assign (weak0, weak1) `CPU.sctag3_cpx_req_cq = 0;
452 assign (weak0, weak1) `CPU.sctag3_cpx_data_ca = 0;
453 assign (weak0, weak1) `CPU.sctag3_pcx_stall_pq = 0;
454 assign (weak0, weak1) `CPU.sctag4_cpx_atom_cq = 0;
455 assign (weak0, weak1) `CPU.sctag4_cpx_req_cq = 0;
456 assign (weak0, weak1) `CPU.sctag4_cpx_data_ca = 0;
457 assign (weak0, weak1) `CPU.sctag4_pcx_stall_pq = 0;
458 assign (weak0, weak1) `CPU.sctag5_cpx_atom_cq = 0;
459 assign (weak0, weak1) `CPU.sctag5_cpx_req_cq = 0;
460 assign (weak0, weak1) `CPU.sctag5_cpx_data_ca = 0;
461 assign (weak0, weak1) `CPU.sctag5_pcx_stall_pq = 0;
462 assign (weak0, weak1) `CPU.sctag6_cpx_atom_cq = 0;
463 assign (weak0, weak1) `CPU.sctag6_cpx_req_cq = 0;
464 assign (weak0, weak1) `CPU.sctag6_cpx_data_ca = 0;
465 assign (weak0, weak1) `CPU.sctag6_pcx_stall_pq = 0;
466 assign (weak0, weak1) `CPU.sctag7_cpx_atom_cq = 0;
467 assign (weak0, weak1) `CPU.sctag7_cpx_req_cq = 0;
468 assign (weak0, weak1) `CPU.sctag7_cpx_data_ca = 0;
469 assign (weak0, weak1) `CPU.sctag7_pcx_stall_pq = 0;
470`endif
471
472
473
474// missing core inputs to CCX. Should be done in cpu.sv but is not.
475`ifndef CORE_0
476 assign (weak0, weak1) `CPU.spc0_pcx_req_pq = 9'b0;
477 assign (weak0, weak1) `CPU.spc0_pcx_data_pa = 130'b0;
478 assign (weak0, weak1) `CPU.spc0_pcx_atm_pq = 9'b0;
479`endif
480`ifndef CORE_1
481 assign (weak0, weak1) `CPU.spc1_pcx_req_pq = 9'b0;
482 assign (weak0, weak1) `CPU.spc1_pcx_data_pa = 130'b0;
483 assign (weak0, weak1) `CPU.spc1_pcx_atm_pq = 9'b0;
484`endif
485`ifndef CORE_2
486 assign (weak0, weak1) `CPU.spc2_pcx_req_pq = 9'b0;
487 assign (weak0, weak1) `CPU.spc2_pcx_data_pa = 130'b0;
488 assign (weak0, weak1) `CPU.spc2_pcx_atm_pq = 9'b0;
489`endif
490`ifndef CORE_3
491 assign (weak0, weak1) `CPU.spc3_pcx_req_pq = 9'b0;
492 assign (weak0, weak1) `CPU.spc3_pcx_data_pa = 130'b0;
493 assign (weak0, weak1) `CPU.spc3_pcx_atm_pq = 9'b0;
494`endif
495`ifndef CORE_4
496 assign (weak0, weak1) `CPU.spc4_pcx_req_pq = 9'b0;
497 assign (weak0, weak1) `CPU.spc4_pcx_data_pa = 130'b0;
498 assign (weak0, weak1) `CPU.spc4_pcx_atm_pq = 9'b0;
499`endif
500`ifndef CORE_5
501 assign (weak0, weak1) `CPU.spc5_pcx_req_pq = 9'b0;
502 assign (weak0, weak1) `CPU.spc5_pcx_data_pa = 130'b0;
503 assign (weak0, weak1) `CPU.spc5_pcx_atm_pq = 9'b0;
504`endif
505`ifndef CORE_6
506 assign (weak0, weak1) `CPU.spc6_pcx_req_pq = 9'b0;
507 assign (weak0, weak1) `CPU.spc6_pcx_data_pa = 130'b0;
508 assign (weak0, weak1) `CPU.spc6_pcx_atm_pq = 9'b0;
509`endif
510`ifndef CORE_7
511 assign (weak0, weak1) `CPU.spc7_pcx_req_pq = 9'b0;
512 assign (weak0, weak1) `CPU.spc7_pcx_data_pa = 130'b0;
513 assign (weak0, weak1) `CPU.spc7_pcx_atm_pq = 9'b0;
514`endif
515
516
517
518 // all forces at time 0
519 initial begin
520
521
522 // L2
523 // RTL_NO_BNKXX not used by N2, we always build in all banks for N2.
524 // these defs are always not defined for N2.
525
526// `ifdef NOL2RTL
527// `else
528// `ifndef RTL_NO_BNK01
529// force `CPU.l2d0_efu_fuse_data = 1'b0;
530// force `CPU.l2d1_efu_fuse_data = 1'b0;
531// `endif
532// `ifndef RTL_NO_BNK23
533// force `CPU.l2d2_efu_fuse_data = 1'b0;
534// force `CPU.l2d3_efu_fuse_data = 1'b0;
535// `endif
536// `ifndef RTL_NO_BNK45
537// force `CPU.l2d4_efu_fuse_data = 1'b0;
538// force `CPU.l2d5_efu_fuse_data = 1'b0;
539// `endif
540// `ifndef RTL_NO_BNK67
541// force `CPU.l2d6_efu_fuse_data = 1'b0;
542// force `CPU.l2d7_efu_fuse_data = 1'b0;
543// `endif
544// `endif
545
546
547 force `CPU.rst_l2_por_ = arst;
548 force `CPU.rst_l2_wmr_ = reset;
549
550 force `CPU.rst_wmr_protect = 0;
551// force `CPU.l2b0_l2d0_fuse_clr = 0;
552// force `CPU.l2b1_l2d1_fuse_clr = 0;
553// force `CPU.l2b2_l2d2_fuse_clr = 0;
554// force `CPU.l2b3_l2d3_fuse_clr = 0;
555// force `CPU.l2b4_l2d4_fuse_clr = 0;
556// force `CPU.l2b5_l2d5_fuse_clr = 0;
557// force `CPU.l2b6_l2d6_fuse_clr = 0;
558// force `CPU.l2b7_l2d7_fuse_clr = 0;
559// force `CPU.efu_l2t0_fuse_clr = 0;
560// force `CPU.efu_l2t1_fuse_clr = 0;
561// force `CPU.efu_l2t2_fuse_clr = 0;
562// force `CPU.efu_l2t3_fuse_clr = 0;
563// force `CPU.efu_l2t4_fuse_clr = 0;
564// force `CPU.efu_l2t5_fuse_clr = 0;
565// force `CPU.efu_l2t6_fuse_clr = 0;
566// force `CPU.efu_l2t7_fuse_clr = 0;
567// force `CPU.efu_l2b0_fuse_clr = 0;
568// force `CPU.efu_l2b1_fuse_clr = 0;
569// force `CPU.efu_l2b2_fuse_clr = 0;
570// force `CPU.efu_l2b3_fuse_clr = 0;
571// force `CPU.efu_l2b4_fuse_clr = 0;
572// force `CPU.efu_l2b5_fuse_clr = 0;
573// force `CPU.efu_l2b6_fuse_clr = 0;
574// force `CPU.efu_l2b7_fuse_clr = 0;
575
576// force `CPU.l2t0.efu_l2t_fuse_clr = 0;
577// force `CPU.l2t0.efu_l2t_fuse_xfer_en = 0;
578// force `CPU.l2t0.efu_l2t_fuse_data = 0;
579// force `CPU.l2t1.efu_l2t_fuse_clr = 0;
580// force `CPU.l2t1.efu_l2t_fuse_xfer_en = 0;
581// force `CPU.l2t1.efu_l2t_fuse_data = 0;
582// force `CPU.l2t2.efu_l2t_fuse_clr = 0;
583// force `CPU.l2t2.efu_l2t_fuse_xfer_en = 0;
584// force `CPU.l2t2.efu_l2t_fuse_data = 0;
585// force `CPU.l2t3.efu_l2t_fuse_clr = 0;
586// force `CPU.l2t3.efu_l2t_fuse_xfer_en = 0;
587// force `CPU.l2t3.efu_l2t_fuse_data = 0;
588// force `CPU.l2t4.efu_l2t_fuse_clr = 0;
589// force `CPU.l2t4.efu_l2t_fuse_xfer_en = 0;
590// force `CPU.l2t4.efu_l2t_fuse_data = 0;
591// force `CPU.l2t5.efu_l2t_fuse_clr = 0;
592// force `CPU.l2t5.efu_l2t_fuse_xfer_en = 0;
593// force `CPU.l2t5.efu_l2t_fuse_data = 0;
594// force `CPU.l2t6.efu_l2t_fuse_clr = 0;
595// force `CPU.l2t6.efu_l2t_fuse_xfer_en = 0;
596// force `CPU.l2t6.efu_l2t_fuse_data = 0;
597// force `CPU.l2t7.efu_l2t_fuse_clr = 0;
598// force `CPU.l2t7.efu_l2t_fuse_xfer_en = 0;
599// force `CPU.l2t7.efu_l2t_fuse_data = 0;
600//
601// force `CPU.l2t0.l2t_tag_fuse_clr = 0;
602// force `CPU.l2t1.l2t_tag_fuse_clr = 0;
603// force `CPU.l2t2.l2t_tag_fuse_clr = 0;
604// force `CPU.l2t3.l2t_tag_fuse_clr = 0;
605// force `CPU.l2t4.l2t_tag_fuse_clr = 0;
606// force `CPU.l2t5.l2t_tag_fuse_clr = 0;
607// force `CPU.l2t6.l2t_tag_fuse_clr = 0;
608// force `CPU.l2t7.l2t_tag_fuse_clr = 0;
609//
610// force `CPU.l2t0.mux_drive_disable = 0;
611// force `CPU.l2t1.mux_drive_disable = 0;
612// force `CPU.l2t2.mux_drive_disable = 0;
613// force `CPU.l2t3.mux_drive_disable = 0;
614// force `CPU.l2t4.mux_drive_disable = 0;
615// force `CPU.l2t5.mux_drive_disable = 0;
616// force `CPU.l2t6.mux_drive_disable = 0;
617// force `CPU.l2t7.mux_drive_disable = 0;
618//
619// force `CPU.l2t0.l2t_fuse_repair_en[1:0] = 0;
620// force `CPU.l2t1.l2t_fuse_repair_en[1:0] = 0;
621// force `CPU.l2t2.l2t_fuse_repair_en[1:0] = 0;
622// force `CPU.l2t3.l2t_fuse_repair_en[1:0] = 0;
623// force `CPU.l2t4.l2t_fuse_repair_en[1:0] = 0;
624// force `CPU.l2t5.l2t_fuse_repair_en[1:0] = 0;
625// force `CPU.l2t6.l2t_fuse_repair_en[1:0] = 0;
626// force `CPU.l2t7.l2t_fuse_repair_en[1:0] = 0;
627//
628// force `CPU.l2t0.fuse_l2t_wren = 0;
629// force `CPU.l2t1.fuse_l2t_wren = 0;
630// force `CPU.l2t2.fuse_l2t_wren = 0;
631// force `CPU.l2t3.fuse_l2t_wren = 0;
632// force `CPU.l2t4.fuse_l2t_wren = 0;
633// force `CPU.l2t5.fuse_l2t_wren = 0;
634// force `CPU.l2t6.fuse_l2t_wren = 0;
635// force `CPU.l2t7.fuse_l2t_wren = 0;
636//
637// force `CPU.l2t0.rdmat_sii_req_vld_buf = 0;
638// force `CPU.l2t1.rdmat_sii_req_vld_buf = 0;
639// force `CPU.l2t2.rdmat_sii_req_vld_buf = 0;
640// force `CPU.l2t3.rdmat_sii_req_vld_buf = 0;
641// force `CPU.l2t4.rdmat_sii_req_vld_buf = 0;
642// force `CPU.l2t5.rdmat_sii_req_vld_buf = 0;
643// force `CPU.l2t6.rdmat_sii_req_vld_buf = 0;
644// force `CPU.l2t7.rdmat_sii_req_vld_buf = 0;
645//
646//
647// force `CPU.l2b0.l2b_l2d_fuse_clr = 0;
648// force `CPU.l2b1.l2b_l2d_fuse_clr = 0;
649// force `CPU.l2b2.l2b_l2d_fuse_clr = 0;
650// force `CPU.l2b3.l2b_l2d_fuse_clr = 0;
651// force `CPU.l2b4.l2b_l2d_fuse_clr = 0;
652// force `CPU.l2b5.l2b_l2d_fuse_clr = 0;
653// force `CPU.l2b6.l2b_l2d_fuse_clr = 0;
654// force `CPU.l2b7.l2b_l2d_fuse_clr = 0;
655//
656// force `CPU.l2b0.efu_l2b_fuse_clr = 0;
657// force `CPU.l2b1.efu_l2b_fuse_clr = 0;
658// force `CPU.l2b2.efu_l2b_fuse_clr = 0;
659// force `CPU.l2b3.efu_l2b_fuse_clr = 0;
660// force `CPU.l2b4.efu_l2b_fuse_clr = 0;
661// force `CPU.l2b5.efu_l2b_fuse_clr = 0;
662// force `CPU.l2b6.efu_l2b_fuse_clr = 0;
663// force `CPU.l2b7.efu_l2b_fuse_clr = 0;
664//
665// force `CPU.l2b0.efu_l2b_fuse_data = 0;
666// force `CPU.l2b1.efu_l2b_fuse_data = 0;
667// force `CPU.l2b2.efu_l2b_fuse_data = 0;
668// force `CPU.l2b3.efu_l2b_fuse_data = 0;
669// force `CPU.l2b4.efu_l2b_fuse_data = 0;
670// force `CPU.l2b5.efu_l2b_fuse_data = 0;
671// force `CPU.l2b6.efu_l2b_fuse_data = 0;
672// force `CPU.l2b7.efu_l2b_fuse_data = 0;
673//
674// force `CPU.l2b0.efu_l2b_fuse_xfer_en = 0;
675// force `CPU.l2b1.efu_l2b_fuse_xfer_en = 0;
676// force `CPU.l2b2.efu_l2b_fuse_xfer_en = 0;
677// force `CPU.l2b3.efu_l2b_fuse_xfer_en = 0;
678// force `CPU.l2b4.efu_l2b_fuse_xfer_en = 0;
679// force `CPU.l2b5.efu_l2b_fuse_xfer_en = 0;
680// force `CPU.l2b6.efu_l2b_fuse_xfer_en = 0;
681// force `CPU.l2b7.efu_l2b_fuse_xfer_en = 0;
682
683 // initial partial bank values
684 force `CPU.ncu_spc_pm = 0;
685 force `CPU.ncu_l2t_pm = 0;
686 force `CPU.ncu_sii_pm = 0;
687 force `CPU.ncu_mcu_pm = 0;
688 force `CPU.ncu_spc_ba01 = 1;
689 force `CPU.ncu_spc_ba23 = 1;
690 force `CPU.ncu_spc_ba45 = 1;
691 force `CPU.ncu_spc_ba67 = 1;
692 force `CPU.ncu_l2t_ba01 = 1;
693 force `CPU.ncu_l2t_ba23 = 1;
694 force `CPU.ncu_l2t_ba45 = 1;
695 force `CPU.ncu_l2t_ba67 = 1;
696 force `CPU.ncu_sii_ba01 = 1;
697 force `CPU.ncu_sii_ba23 = 1;
698 force `CPU.ncu_sii_ba45 = 1;
699 force `CPU.ncu_sii_ba67 = 1;
700 force `CPU.ncu_mcu_ba01 = 1;
701 force `CPU.ncu_mcu_ba23 = 1;
702 force `CPU.ncu_mcu_ba45 = 1;
703 force `CPU.ncu_mcu_ba67 = 1;
704
705
706 // if banks are missing, that implies partial bank mode, so...
707 // not used by N2, we always build in all banks for N2
708`ifdef RTL_NO_BNK01
709 force `CPU.ncu_spc_pm = 1;
710 force `CPU.ncu_l2t_pm = 1;
711 force `CPU.ncu_sii_pm = 1;
712 force `CPU.ncu_mcu_pm = 1;
713 force `CPU.ncu_spc_ba01 = 0;
714 force `CPU.ncu_spc_ba23 = 1;
715 force `CPU.ncu_spc_ba45 = 1;
716 force `CPU.ncu_spc_ba67 = 1;
717 force `CPU.ncu_l2t_ba01 = 0;
718 force `CPU.ncu_l2t_ba23 = 1;
719 force `CPU.ncu_l2t_ba45 = 1;
720 force `CPU.ncu_l2t_ba67 = 1;
721 force `CPU.ncu_sii_ba01 = 0;
722 force `CPU.ncu_sii_ba23 = 1;
723 force `CPU.ncu_sii_ba45 = 1;
724 force `CPU.ncu_sii_ba67 = 1;
725 force `CPU.ncu_mcu_ba01 = 0;
726 force `CPU.ncu_mcu_ba23 = 1;
727 force `CPU.ncu_mcu_ba45 = 1;
728 force `CPU.ncu_mcu_ba67 = 1;
729`endif
730`ifdef RTL_NO_BNK23
731 force `CPU.ncu_spc_pm = 1;
732 force `CPU.ncu_l2t_pm = 1;
733 force `CPU.ncu_sii_pm = 1;
734 force `CPU.ncu_mcu_pm = 1;
735 force `CPU.ncu_spc_ba01 = 1;
736 force `CPU.ncu_spc_ba23 = 0;
737 force `CPU.ncu_spc_ba45 = 1;
738 force `CPU.ncu_spc_ba67 = 1;
739 force `CPU.ncu_l2t_ba01 = 1;
740 force `CPU.ncu_l2t_ba23 = 0;
741 force `CPU.ncu_l2t_ba45 = 1;
742 force `CPU.ncu_l2t_ba67 = 1;
743 force `CPU.ncu_sii_ba01 = 1;
744 force `CPU.ncu_sii_ba23 = 0;
745 force `CPU.ncu_sii_ba45 = 1;
746 force `CPU.ncu_sii_ba67 = 1;
747 force `CPU.ncu_mcu_ba01 = 1;
748 force `CPU.ncu_mcu_ba23 = 0;
749 force `CPU.ncu_mcu_ba45 = 1;
750 force `CPU.ncu_mcu_ba67 = 1;
751`endif
752`ifdef RTL_NO_BNK45
753 force `CPU.ncu_spc_pm = 1;
754 force `CPU.ncu_l2t_pm = 1;
755 force `CPU.ncu_sii_pm = 1;
756 force `CPU.ncu_mcu_pm = 1;
757 force `CPU.ncu_spc_ba01 = 1;
758 force `CPU.ncu_spc_ba23 = 1;
759 force `CPU.ncu_spc_ba45 = 0;
760 force `CPU.ncu_spc_ba67 = 1;
761 force `CPU.ncu_l2t_ba01 = 1;
762 force `CPU.ncu_l2t_ba23 = 1;
763 force `CPU.ncu_l2t_ba45 = 0;
764 force `CPU.ncu_l2t_ba67 = 1;
765 force `CPU.ncu_sii_ba01 = 1;
766 force `CPU.ncu_sii_ba23 = 1;
767 force `CPU.ncu_sii_ba45 = 0;
768 force `CPU.ncu_sii_ba67 = 1;
769 force `CPU.ncu_mcu_ba01 = 1;
770 force `CPU.ncu_mcu_ba23 = 1;
771 force `CPU.ncu_mcu_ba45 = 0;
772 force `CPU.ncu_mcu_ba67 = 1;
773`endif
774`ifdef RTL_NO_BNK67
775 force `CPU.ncu_spc_pm = 1;
776 force `CPU.ncu_l2t_pm = 1;
777 force `CPU.ncu_sii_pm = 1;
778 force `CPU.ncu_mcu_pm = 1;
779 force `CPU.ncu_spc_ba01 = 1;
780 force `CPU.ncu_spc_ba23 = 1;
781 force `CPU.ncu_spc_ba45 = 1;
782 force `CPU.ncu_spc_ba67 = 0;
783 force `CPU.ncu_l2t_ba01 = 1;
784 force `CPU.ncu_l2t_ba23 = 1;
785 force `CPU.ncu_l2t_ba45 = 1;
786 force `CPU.ncu_l2t_ba67 = 0;
787 force `CPU.ncu_sii_ba01 = 1;
788 force `CPU.ncu_sii_ba23 = 1;
789 force `CPU.ncu_sii_ba45 = 1;
790 force `CPU.ncu_sii_ba67 = 0;
791 force `CPU.ncu_mcu_ba01 = 1;
792 force `CPU.ncu_mcu_ba23 = 1;
793 force `CPU.ncu_mcu_ba45 = 1;
794 force `CPU.ncu_mcu_ba67 = 0;
795`endif
796
797
798 // MISC cache bank enable
799
800
801
802 // TCU-L2
803 // RTL_NO_BNKXX not used by N2, we always build in all banks for N2.
804 // these defs are always not defined for N2.
805`ifndef RTL_NO_BNK01
806 force `CPU.l2b0.scan_in = 0;
807 force `CPU.l2b0.tcu_se_scancollar_in = 1'b0;
808 force `CPU.l2b0.tcu_se_scancollar_out = 1'b0;
809 force `CPU.l2b1.scan_in = 0;
810 force `CPU.l2b1.tcu_se_scancollar_in = 1'b0;
811 force `CPU.l2b1.tcu_se_scancollar_out = 1'b0;
812 force `CPU.l2d0.scan_in = 0;
813 force `CPU.l2d0.tcu_clk_stop = 0;
814 force `CPU.l2d1.scan_in = 0;
815 force `CPU.l2d1.tcu_clk_stop = 0;
816 force `CPU.l2t0.tcu_se_scancollar_in = 1'b0;
817 force `CPU.l2t0.tcu_se_scancollar_out = 1'b0;
818 force `CPU.l2t1.tcu_se_scancollar_in = 1'b0;
819 force `CPU.l2t1.tcu_se_scancollar_out = 1'b0;
820`endif
821`ifndef RTL_NO_BNK23
822 force `CPU.l2b2.scan_in = 0;
823 force `CPU.l2b2.tcu_se_scancollar_in = 1'b0;
824 force `CPU.l2b2.tcu_se_scancollar_out = 1'b0;
825 force `CPU.l2b3.scan_in = 0;
826 force `CPU.l2b3.tcu_se_scancollar_in = 1'b0;
827 force `CPU.l2b3.tcu_se_scancollar_out = 1'b0;
828 force `CPU.l2d2.scan_in = 0;
829 force `CPU.l2d2.tcu_clk_stop = 0;
830 force `CPU.l2d3.scan_in = 0;
831 force `CPU.l2d3.tcu_clk_stop = 0;
832 force `CPU.l2t2.tcu_se_scancollar_in = 1'b0;
833 force `CPU.l2t2.tcu_se_scancollar_out = 1'b0;
834 force `CPU.l2t3.tcu_se_scancollar_in = 1'b0;
835 force `CPU.l2t3.tcu_se_scancollar_out = 1'b0;
836`endif
837`ifndef RTL_NO_BNK45
838 force `CPU.l2b4.scan_in = 0;
839 force `CPU.l2b4.tcu_se_scancollar_in = 1'b0;
840 force `CPU.l2b4.tcu_se_scancollar_out = 1'b0;
841 force `CPU.l2b5.scan_in = 0;
842 force `CPU.l2b5.tcu_se_scancollar_in = 1'b0;
843 force `CPU.l2b5.tcu_se_scancollar_out = 1'b0;
844 force `CPU.l2d4.scan_in = 0;
845 force `CPU.l2d4.tcu_clk_stop = 0;
846 force `CPU.l2d5.scan_in = 0;
847 force `CPU.l2d5.tcu_clk_stop = 0;
848 force `CPU.l2t4.tcu_se_scancollar_in = 1'b0;
849 force `CPU.l2t4.tcu_se_scancollar_out = 1'b0;
850 force `CPU.l2t5.tcu_se_scancollar_in = 1'b0;
851 force `CPU.l2t5.tcu_se_scancollar_out = 1'b0;
852`endif
853`ifndef RTL_NO_BNK67
854 force `CPU.l2b6.scan_in = 0;
855 force `CPU.l2b6.tcu_se_scancollar_in = 1'b0;
856 force `CPU.l2b6.tcu_se_scancollar_out = 1'b0;
857 force `CPU.l2b7.scan_in = 0;
858 force `CPU.l2b7.tcu_se_scancollar_in = 1'b0;
859 force `CPU.l2b7.tcu_se_scancollar_out = 1'b0;
860 force `CPU.l2d6.scan_in = 0;
861 force `CPU.l2d6.tcu_clk_stop = 0;
862 force `CPU.l2d7.scan_in = 0;
863 force `CPU.l2d7.tcu_clk_stop = 0;
864 force `CPU.l2t6.tcu_se_scancollar_in = 1'b0;
865 force `CPU.l2t6.tcu_se_scancollar_out = 1'b0;
866 force `CPU.l2t7.tcu_se_scancollar_in = 1'b0;
867 force `CPU.l2t7.tcu_se_scancollar_out = 1'b0;
868`endif
869
870
871 force `CPU.ccx.cpx.cpx_dpa_scanin = 1'b0;
872 force `CPU.ccx.scan_in = 0;
873 force `CPU.ccx.tcu_aclk = 0;
874 force `CPU.ccx.tcu_bclk = 0;
875 force `CPU.ccx.tcu_pce_ov = 0;
876 force `CPU.ccx.tcu_scan_en = 0;
877 force `CPU.rst_ncu_vld = 1'b0;
878 force `CPU.sii_l2b0_ecc = 7'b0;
879 force `CPU.sii_l2b1_ecc = 7'b0;
880 force `CPU.sii_l2b2_ecc = 7'b0;
881 force `CPU.sii_l2b3_ecc = 7'b0;
882 force `CPU.sii_l2b4_ecc = 7'b0;
883 force `CPU.sii_l2b5_ecc = 7'b0;
884 force `CPU.sii_l2b6_ecc = 7'b0;
885 force `CPU.sii_l2b7_ecc = 7'b0;
886 force `CPU.sii_l2t0_req = 32'b0;
887 force `CPU.sii_l2t0_req_vld = 1'b0;
888 force `CPU.sii_l2t1_req = 32'b0;
889 force `CPU.sii_l2t1_req_vld = 1'b0;
890 force `CPU.sii_l2t2_req = 32'b0;
891 force `CPU.sii_l2t2_req_vld = 1'b0;
892 force `CPU.sii_l2t3_req = 32'b0;
893 force `CPU.sii_l2t3_req_vld = 1'b0;
894 force `CPU.sii_l2t4_req = 32'b0;
895 force `CPU.sii_l2t4_req_vld = 1'b0;
896 force `CPU.sii_l2t5_req = 32'b0;
897 force `CPU.sii_l2t5_req_vld = 1'b0;
898 force `CPU.sii_l2t6_req = 32'b0;
899 force `CPU.sii_l2t6_req_vld = 1'b0;
900 force `CPU.sii_l2t7_req = 32'b0;
901 force `CPU.sii_l2t7_req_vld = 1'b0;
902 force `CPU.sii_ncu_syn_vld = 1'b0;
903 force `CPU.tck = 0;
904
905// leave this out of cmp model
906`ifdef OPENSPARC_CMP
907`else
908 force `CPU.tcu.tcu_soc0_scan_out = 1'b0;
909 force `CPU.tcu.tcu_soc1_scan_out = 1'b0;
910 force `CPU.tcu.tcu_soc2_scan_out = 1'b0;
911 force `CPU.tcu.tcu_soc3_scan_out = 1'b0;
912 force `CPU.tcu.tcu_soc4_scan_out = 1'b0;
913 force `CPU.tcu.tcu_soc5_scan_out = 1'b0;
914 force `CPU.tcu.tcu_soc6_scan_out = 1'b0;
915`endif // OPENSPARC_CMP
916
917 force `CPU.tcu_aclk = 0;
918 force `CPU.tcu_array_bypass = 0;
919 force `CPU.tcu_array_wr_inhibit = 0;
920 force `CPU.tcu_bclk = 0;
921
922 force `CPU.tcu_dectest = 1;
923 force `CPU.tcu_div_bypass = 1'b0;
924
925 // l2 scan in
926 force `CPU.tcu_l2b0_mbist_scan_in = 0;
927 force `CPU.tcu_l2b0_mbist_start = 0;
928 force `CPU.tcu_l2b1_mbist_scan_in = 0;
929 force `CPU.tcu_l2b1_mbist_start = 0;
930 force `CPU.tcu_l2b2_mbist_scan_in = 0;
931 force `CPU.tcu_l2b2_mbist_start = 0;
932 force `CPU.tcu_l2b3_mbist_scan_in = 0;
933 force `CPU.tcu_l2b3_mbist_start = 0;
934 force `CPU.tcu_l2b4_mbist_scan_in = 0;
935 force `CPU.tcu_l2b4_mbist_start = 0;
936 force `CPU.tcu_l2b5_mbist_scan_in = 0;
937 force `CPU.tcu_l2b5_mbist_start = 0;
938 force `CPU.tcu_l2b6_mbist_scan_in = 0;
939 force `CPU.tcu_l2b6_mbist_start = 0;
940 force `CPU.tcu_l2b7_mbist_scan_in = 0;
941 force `CPU.tcu_l2b7_mbist_start = 0;
942
943 force `CPU.tcu_l2t0_mbist_scan_in = 0;
944 force `CPU.tcu_l2t0_mbist_start = 0;
945 force `CPU.tcu_l2t0_shscan_scan_in = 0;
946 force `CPU.tcu_l2t1_mbist_scan_in = 0;
947 force `CPU.tcu_l2t1_mbist_start = 0;
948 force `CPU.tcu_l2t1_shscan_scan_in = 0;
949 force `CPU.tcu_l2t2_mbist_scan_in = 0;
950 force `CPU.tcu_l2t2_mbist_start = 0;
951 force `CPU.tcu_l2t2_shscan_scan_in = 0;
952 force `CPU.tcu_l2t3_mbist_scan_in = 0;
953 force `CPU.tcu_l2t3_mbist_start = 0;
954 force `CPU.tcu_l2t3_shscan_scan_in = 0;
955 force `CPU.tcu_l2t4_mbist_scan_in = 0;
956 force `CPU.tcu_l2t4_mbist_start = 0;
957 force `CPU.tcu_l2t4_shscan_scan_in = 0;
958 force `CPU.tcu_l2t5_mbist_scan_in = 0;
959 force `CPU.tcu_l2t5_mbist_start = 0;
960 force `CPU.tcu_l2t5_shscan_scan_in = 0;
961 force `CPU.tcu_l2t6_mbist_scan_in = 0;
962 force `CPU.tcu_l2t6_mbist_start = 0;
963 force `CPU.tcu_l2t6_shscan_scan_in = 0;
964 force `CPU.tcu_l2t7_mbist_scan_in = 0;
965 force `CPU.tcu_l2t7_mbist_start = 0;
966 force `CPU.tcu_l2t7_shscan_scan_in = 0;
967
968 force `CPU.tcu_l2t_shscan_aclk = 0;
969 force `CPU.tcu_l2t_shscan_bclk = 0;
970 force `CPU.tcu_l2t_shscan_pce_ov = 0;
971 force `CPU.tcu_l2t_shscan_scan_en = 0;
972
973 force `CPU.tcu_mbist_bisi_en = 0;
974 force `CPU.tcu_muxtest = 1'b1;
975 force `CPU.tcu_pce_ov = 0;
976
977 force `CPU.tcu_atpg_mode = 0;
978 force `CPU.tcu_srd_atpgd = 0;
979 force `CPU.tcu_srd_atpgse = 0;
980 force `CPU.tcu_srd_atpgmode = 3'b0;
981
982 force `CPU.tcu_mbist_user_mode = 0;
983 force `CPU.tcu_scan_en = 0;
984 force `CPU.tcu_se_scancollar_in = 0;
985 force `CPU.tcu_se_scancollar_out = 0;
986 force `CPU.tcu_spc0_aclk = 1'b0;
987 force `CPU.tcu_spc0_array_wr_inhibit = 1'b0;
988 force `CPU.tcu_spc0_bclk = 1'b0;
989 force `CPU.tcu_spc0_mbist_scan_in = 1'b0;
990 force `CPU.tcu_spc0_scan_en = 1'b0;
991 force `CPU.tcu_spc0_scan_out = 0;
992 force `CPU.tcu_spc0_se_scancollar_in = 1'b0;
993 force `CPU.tcu_spc0_se_scancollar_out = 1'b0;
994 force `CPU.tcu_spc0_shscan_scan_out = 1'b0;
995 force `CPU.tcu_spc1_aclk = 1'b0;
996 force `CPU.tcu_spc1_array_wr_inhibit = 1'b0;
997 force `CPU.tcu_spc1_bclk = 1'b0;
998 force `CPU.tcu_spc1_mbist_scan_in = 1'b0;
999 force `CPU.tcu_spc1_scan_en = 1'b0;
1000 force `CPU.tcu_spc1_scan_out = 0;
1001 force `CPU.tcu_spc1_se_scancollar_in = 1'b0;
1002 force `CPU.tcu_spc1_se_scancollar_out = 1'b0;
1003 force `CPU.tcu_spc1_shscan_scan_out = 1'b0;
1004 force `CPU.tcu_spc2_aclk = 1'b0;
1005 force `CPU.tcu_spc2_array_wr_inhibit = 1'b0;
1006 force `CPU.tcu_spc2_bclk = 1'b0;
1007 force `CPU.tcu_spc2_mbist_scan_in = 1'b0;
1008 force `CPU.tcu_spc2_scan_en = 1'b0;
1009 force `CPU.tcu_spc2_scan_out = 0;
1010 force `CPU.tcu_spc2_se_scancollar_in = 1'b0;
1011 force `CPU.tcu_spc2_se_scancollar_out = 1'b0;
1012 force `CPU.tcu_spc2_shscan_scan_out = 1'b0;
1013 force `CPU.tcu_spc3_aclk = 1'b0;
1014 force `CPU.tcu_spc3_array_wr_inhibit = 1'b0;
1015 force `CPU.tcu_spc3_bclk = 1'b0;
1016 force `CPU.tcu_spc3_mbist_scan_in = 1'b0;
1017 force `CPU.tcu_spc3_scan_en = 1'b0;
1018 force `CPU.tcu_spc3_scan_out = 0;
1019 force `CPU.tcu_spc3_se_scancollar_in = 1'b0;
1020 force `CPU.tcu_spc3_se_scancollar_out = 1'b0;
1021 force `CPU.tcu_spc3_shscan_scan_out = 1'b0;
1022 force `CPU.tcu_spc4_aclk = 1'b0;
1023 force `CPU.tcu_spc4_array_wr_inhibit = 1'b0;
1024 force `CPU.tcu_spc4_bclk = 1'b0;
1025 force `CPU.tcu_spc4_mbist_scan_in = 1'b0;
1026 force `CPU.tcu_spc4_scan_en = 1'b0;
1027 force `CPU.tcu_spc4_scan_out = 0;
1028 force `CPU.tcu_spc4_se_scancollar_in = 1'b0;
1029 force `CPU.tcu_spc4_se_scancollar_out = 1'b0;
1030 force `CPU.tcu_spc4_shscan_scan_out = 1'b0;
1031 force `CPU.tcu_spc5_aclk = 1'b0;
1032 force `CPU.tcu_spc5_array_wr_inhibit = 1'b0;
1033 force `CPU.tcu_spc5_bclk = 1'b0;
1034 force `CPU.tcu_spc5_mbist_scan_in = 1'b0;
1035 force `CPU.tcu_spc5_scan_en = 1'b0;
1036 force `CPU.tcu_spc5_scan_out = 0;
1037 force `CPU.tcu_spc5_se_scancollar_in = 1'b0;
1038 force `CPU.tcu_spc5_se_scancollar_out = 1'b0;
1039 force `CPU.tcu_spc5_shscan_scan_out = 1'b0;
1040 force `CPU.tcu_spc6_aclk = 1'b0;
1041 force `CPU.tcu_spc6_array_wr_inhibit = 1'b0;
1042 force `CPU.tcu_spc6_bclk = 1'b0;
1043 force `CPU.tcu_spc6_mbist_scan_in = 1'b0;
1044 force `CPU.tcu_spc6_scan_en = 1'b0;
1045 force `CPU.tcu_spc6_scan_out = 0;
1046 force `CPU.tcu_spc6_se_scancollar_in = 1'b0;
1047 force `CPU.tcu_spc6_se_scancollar_out = 1'b0;
1048 force `CPU.tcu_spc6_shscan_scan_out = 1'b0;
1049 force `CPU.tcu_spc7_aclk = 1'b0;
1050 force `CPU.tcu_spc7_array_wr_inhibit = 1'b0;
1051 force `CPU.tcu_spc7_bclk = 1'b0;
1052 force `CPU.tcu_spc7_mbist_scan_in = 1'b0;
1053 force `CPU.tcu_spc7_scan_en = 1'b0;
1054 force `CPU.tcu_spc7_scan_out = 0;
1055 force `CPU.tcu_spc7_se_scancollar_in = 1'b0;
1056 force `CPU.tcu_spc7_se_scancollar_out = 1'b0;
1057 force `CPU.tcu_spc7_shscan_scan_out = 1'b0;
1058
1059 force `CPU.tcu_spc_mbist_start = 0;
1060`ifdef NOL2RTL
1061 force `CPU.tcu_spc0_mbist_start_t1lff_0 = 0;
1062 force `CPU.tcu_spc_mbist_start_t3lff_2 = 0;
1063`endif
1064
1065 force `CPU.tcu_spc_shscan_aclk = 0;
1066 force `CPU.tcu_spc_shscan_bclk = 0;
1067 force `CPU.tcu_spc_shscan_pce_ov = 0;
1068 force `CPU.tcu_spc_shscan_scan_en = 0;
1069 force `CPU.tcu_spc_shscanid = 3'b0;
1070
1071 force `CPU.L2T_VNW = 8'hff;
1072 force `CPU.SPC_VNW = 8'hff;
1073 force `CPU.L2D_VNW0 = 8'hff;
1074 force `CPU.L2D_VNW1 = 8'hff;
1075
1076
1077// force `CPU.tcu_do_mode = 0; //in cmp_tasks
1078// force `CPU.tcu_ss_mode = 0; //in cmp_tasks
1079
1080 force `CPU.tcu_ss_request = 0;
1081`ifdef NOL2RTL
1082 force `CPU.tcu_ss_request_t1lff_0 = 0;
1083 force `CPU.tcu_ss_request_t3lff_2 = 0;
1084`endif
1085
1086 force `CPU.dmo_coresel[5:0] = 6'h3f;
1087 force `CPU.dmo_tagmuxctl = 0;
1088 force `CPU.dmo_l2tsel[5:0] = 6'b0;
1089 force `CPU.dmo_icmuxctl = 0;
1090 force `CPU.dmo_dcmuxctl = 0;
1091 force `CPU.tcu_spc_lbist_start[7:0] = 8'b0;
1092// force `CPU.tcu_spc_test_mode = 0;
1093
1094
1095
1096// clock stop
1097 force `CPU.tcu_ccx_clk_stop = 0;
1098 force `CPU.tcu_l2b0_clk_stop = 0;
1099 force `CPU.tcu_l2b1_clk_stop = 0;
1100 force `CPU.tcu_l2b2_clk_stop = 0;
1101 force `CPU.tcu_l2b3_clk_stop = 0;
1102 force `CPU.tcu_l2b4_clk_stop = 0;
1103 force `CPU.tcu_l2b5_clk_stop = 0;
1104 force `CPU.tcu_l2b6_clk_stop = 0;
1105 force `CPU.tcu_l2b7_clk_stop = 0;
1106 force `CPU.tcu_l2d0_clk_stop = 0;
1107 force `CPU.tcu_l2d1_clk_stop = 0;
1108 force `CPU.tcu_l2d2_clk_stop = 0;
1109 force `CPU.tcu_l2d3_clk_stop = 0;
1110 force `CPU.tcu_l2d4_clk_stop = 0;
1111 force `CPU.tcu_l2d5_clk_stop = 0;
1112 force `CPU.tcu_l2d6_clk_stop = 0;
1113 force `CPU.tcu_l2d7_clk_stop = 0;
1114 force `CPU.tcu_l2t0_clk_stop = 0;
1115 force `CPU.tcu_l2t0_shscan_clk_stop = 0;
1116 force `CPU.tcu_l2t1_clk_stop = 0;
1117 force `CPU.tcu_l2t1_shscan_clk_stop = 0;
1118 force `CPU.tcu_l2t2_clk_stop = 0;
1119 force `CPU.tcu_l2t2_shscan_clk_stop = 0;
1120 force `CPU.tcu_l2t3_clk_stop = 0;
1121 force `CPU.tcu_l2t3_shscan_clk_stop = 0;
1122 force `CPU.tcu_l2t4_clk_stop = 0;
1123 force `CPU.tcu_l2t4_shscan_clk_stop = 0;
1124 force `CPU.tcu_l2t5_clk_stop = 0;
1125 force `CPU.tcu_l2t5_shscan_clk_stop = 0;
1126 force `CPU.tcu_l2t6_clk_stop = 0;
1127 force `CPU.tcu_l2t6_shscan_clk_stop = 0;
1128 force `CPU.tcu_l2t7_clk_stop = 0;
1129 force `CPU.tcu_l2t7_shscan_clk_stop = 0;
1130
1131
1132// done in cmp_tasks.v
1133 force `CPU.tcu_spc0_clk_stop = 0;
1134 force `CPU.tcu_spc0_shscan_clk_stop = 0;
1135 force `CPU.tcu_spc1_clk_stop = 0;
1136 force `CPU.tcu_spc1_shscan_clk_stop = 0;
1137 force `CPU.tcu_spc2_clk_stop = 0;
1138 force `CPU.tcu_spc2_shscan_clk_stop = 0;
1139 force `CPU.tcu_spc3_clk_stop = 0;
1140 force `CPU.tcu_spc3_shscan_clk_stop = 0;
1141 force `CPU.tcu_spc4_clk_stop = 0;
1142 force `CPU.tcu_spc4_shscan_clk_stop = 0;
1143 force `CPU.tcu_spc5_clk_stop = 0;
1144 force `CPU.tcu_spc5_shscan_clk_stop = 0;
1145 force `CPU.tcu_spc6_clk_stop = 0;
1146 force `CPU.tcu_spc6_shscan_clk_stop = 0;
1147 force `CPU.tcu_spc7_clk_stop = 0;
1148 force `CPU.tcu_spc7_shscan_clk_stop = 0;
1149
1150
1151 force `CPU.cluster_arst_l = 1;
1152 force `CPU.efu_spc0_fuse_ixfer_en = 0;
1153 force `CPU.efu_spc0_fuse_iclr = 0;
1154 force `CPU.efu_spc0_fuse_dxfer_en = 0;
1155 force `CPU.efu_spc0_fuse_dclr = 0;
1156 force `CPU.tcu_spc_lbist_pgm = 0;
1157 force `CPU.tcu_spc_lbist_scan_in = 0;
1158
1159 force `CPU.spc_revid_out[3:0] = 0;
1160
1161 end // forces
1162
1163
1164 // The vera shell. Give it the fastest bench clock, always.
1165 // You could pass in all the DUTs top wires, but it is not required.
1166 // Vera can still get to any hdl node through interface.if.vrh files.
1167 // NTB on the otherhand...
1168
1169 // review
1170 `ifdef NTB
1171 cmp_test vshell(
1172 .SystemClock (SystemClock),
1173 .\top_if.clk (SystemClock),
1174 // .\top_if.spc_pcx_req_pq (spc_pcx_req_pq),
1175 // .\top_if.spc_pcx_atm_pq (spc_pcx_atm_pq),
1176 // .\top_if.spc_pcx_data_pa (spc_pcx_data_pa),
1177 // .\top_if.pcx_spc_grant_px (pcx_spc_grant_px),
1178 // .\top_if.cpx_spc_data_cx (cpx_spc_data_cx),
1179 // .\top_if.cmp_core_running_rw (cmp_core_running_rw),
1180 .\probe_if.raw_set (`TB_TOP.spc.lsu.lmc.ld_rawp_disabled_set[7:0])
1181 );
1182
1183// `else
1184// cmp_top_shell vshell();
1185// //`else
1186// //cmp_top_shell vshell(
1187// // .SystemClock (SystemClock),
1188// // .topInterface_clk (SystemClock),
1189// // .topInterface_spc_pcx_req_pq (spc_pcx_req_pq),
1190// // .topInterface_spc_pcx_atm_pq (spc_pcx_atm_pq),
1191// // .topInterface_spc_pcx_data_pa (spc_pcx_data_pa),
1192// // .topInterface_pcx_spc_grant_px (pcx_spc_grant_px),
1193// // .topInterface_cpx_spc_data_cx (cpx_spc_data_cx),
1194// // .topInterface_cmp_core_running_rw (cmp_core_running_rw)
1195// // );
1196 `endif
1197
1198
1199 //----------------------------------------------------------
1200 `include "misc_tasks.v"
1201
1202endmodule
1203//----------------------------------------------------------
1204//----------------------------------------------------------
Full OpenSPARC design & verification tarball including full HDL.