Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / dmu / dmu_clu_sample.vrh
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_clu_sample.vrh
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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8//
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10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
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13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
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20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
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32// have any questions.
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34// ========== Copyright Header End ============================================
35sample dmu_clu_cl2ps (dmu_clu_coverage.cl2ps_e_trn)
36{
37
38state DMU_CLU_ADR_00 ( 5'b00000 );
39state DMU_CLU_ADR_01 ( 5'b00001 );
40state DMU_CLU_ADR_02 ( 5'b00010 );
41state DMU_CLU_ADR_03 ( 5'b00011 );
42state DMU_CLU_ADR_04 ( 5'b00100 );
43state DMU_CLU_ADR_05 ( 5'b00101 );
44state DMU_CLU_ADR_06 ( 5'b00110 );
45state DMU_CLU_ADR_07 ( 5'b00111 );
46state DMU_CLU_ADR_08 ( 5'b01000 );
47state DMU_CLU_ADR_09 ( 5'b01001 );
48state DMU_CLU_ADR_10 ( 5'b01010 );
49state DMU_CLU_ADR_11 ( 5'b01011 );
50state DMU_CLU_ADR_12 ( 5'b01100 );
51state DMU_CLU_ADR_13 ( 5'b01101 );
52state DMU_CLU_ADR_14 ( 5'b01110 );
53state DMU_CLU_ADR_15 ( 5'b01111 );
54state DMU_CLU_ADR_16 ( 5'b10000 );
55state DMU_CLU_ADR_17 ( 5'b10001 );
56state DMU_CLU_ADR_18 ( 5'b10010 );
57state DMU_CLU_ADR_19 ( 5'b10011 );
58state DMU_CLU_ADR_20 ( 5'b10100 );
59state DMU_CLU_ADR_21 ( 5'b10101 );
60state DMU_CLU_ADR_22 ( 5'b10110 );
61state DMU_CLU_ADR_23 ( 5'b10111 );
62state DMU_CLU_ADR_24 ( 5'b11000 );
63state DMU_CLU_ADR_25 ( 5'b11001 );
64state DMU_CLU_ADR_26 ( 5'b11010 );
65state DMU_CLU_ADR_27 ( 5'b11011 );
66state DMU_CLU_ADR_28 ( 5'b11100 );
67state DMU_CLU_ADR_29 ( 5'b11101 );
68state DMU_CLU_ADR_30 ( 5'b11110 );
69state DMU_CLU_ADR_31 ( 5'b11111 );
70
71}