[OpenSPARC-T2-DV] / verif / env / common / coverage / dmu / dmu_cov.if.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_cov.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#inc "dmu_cov_inc.pal";
#ifndef __DMU_IF_VRH__
#define __DMU_IF_VRH__

#include <vera_defines.vrh>

#define INPUT_EDGE   PSAMPLE
#define INPUT_SKEW   #-3
`define TOP tb_top
`define DMU tb_top.cpu.dmu

interface dmu_coverage_ifc {
  // Common & Clock Signals
  input dmu_gclk               CLOCK ;
  input dmu_rst_l              PSAMPLE ;
  
  // dmu interface
  input           dmureq          INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.dmu_sii_hdr_vld";
  input           dmubypass       INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.dmu_sii_reqbypass";
  input           dmudatareq      INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.dmu_sii_datareq";
  input           dmudatareq16    INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.dmu_sii_datareq16";
  input [127:0]   dmudata         INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.dmu_sii_data";
  input [1:0]     dmuparity       INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.dmu_sii_parity";
  input [15:0]    dmube           INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.dmu_sii_be";
  input           dmuwrack_vld    INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.sii_dmu_wrack_vld";
  input [3:0]     dmuwrack_tag    INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.sii_dmu_wrack_tag";
  input           dmuwrack_par    INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.sii_dmu_wrack_par";

  //sio-dmu
  input           sio_dmu_req     INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.sio_dmu_hdr_vld";
  input [127:0]   sio_dmu_data    INPUT_EDGE      INPUT_SKEW      verilog_node "`DMU.sio_dmu_data";
}

interface dmu_ncu_error_if {
  input         clk                CLOCK                 verilog_node "`DMU.iol2clk";
  input         ncu_dmu_ctag_uei   INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_ctag_uei";
  input         ncu_dmu_ctag_cei   INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_ctag_cei";
  input         ncu_dmu_d_pei      INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_d_pei";
  input         ncu_dmu_siicr_pei  INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_siicr_pei";
  input         ncu_dmu_ncucr_pei  INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_ncucr_pei";
  input         ncu_dmu_iei        INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_iei";

  input         dmu_ncu_d_pe       INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_d_pe";
  input         dmu_ncu_siicr_pe   INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_siicr_pe";
  input         dmu_ncu_ctag_ue    INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_ctag_ue";
  input         dmu_ncu_ctag_ce    INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_ctag_ce";
  input         dmu_ncu_ncucr_pe   INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_ncucr_pe";
  input         dmu_ncu_ie         INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_ie";
}

// #ifndef FC_COVERAGE
interface dmu_cov_dmupio {
        input           clk                     CLOCK                   verilog_node "`DMU.iol2clk";
        input           dmu_ncu_wrack_vld       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmu_ncu_wrack_vld";
        input [3:0]     dmu_ncu_wrack_tag       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmu_ncu_wrack_tag";
        input           dmu_ncu_wrack_par       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmu_ncu_wrack_par";
        input           ncu_dmu_pio_hdr_vld     INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.ncu_dmu_pio_hdr_vld";
        input           ncu_dmu_mmu_addr_vld    INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.ncu_dmu_mmu_addr_vld";
        input   [63:0]  ncu_dmu_pio_data        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.ncu_dmu_pio_data";
}
// #endif

interface dmu_ncu_mondo_if {
        input           clk                     CLOCK                   verilog_node "`DMU.iol2clk";
        input           ncu_dmu_mondo_ack       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.ncu_dmu_mondo_ack";
        input           ncu_dmu_mondo_nack      INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.ncu_dmu_mondo_nack";
        input	[5:0]	ncu_dmu_mondo_id        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.ncu_dmu_mondo_id";
        input	        ncu_dmu_mondo_id_par    INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.ncu_dmu_mondo_id_par";
}

interface ilu_dmu_coverage {
        input                clk                CLOCK                   verilog_node "`DMU.iol2clk";
        input [125:0]        y2k_rcd            INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_rcd";
        input                y2k_rcd_enq        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_rcd_enq";

        input  [7:0]         k2y_buf_addr       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_buf_addr";
        input                k2y_buf_addr_vld   INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_buf_addr_vld_monitor";
        input [127:0]        y2k_buf_data       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_buf_data";
        input [3:0]          y2k_buf_dpar       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_buf_dpar";

        // egress release 
        input                k2y_rcd_deq        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_rcd_deq";
        input                k2y_rel_enq        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_rel_enq";
        input  [8:0]         k2y_rel_rcd        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_rel_rcd";
        input  [2:0]         mps                INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_mps";

}

interface dmu_ilu_coverage {
        input                clk                CLOCK                   verilog_node "`DMU.iol2clk";
        input  [7:0]         y2k_buf_addr       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_buf_addr";
        input                y2k_buf_addr_vld   INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_buf_addr_vld_monitor";
        input  [127:0]       k2y_buf_data       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_buf_data";
        input  [3:0]         k2y_buf_dpar       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_buf_dpar";
        input  [125:0]       k2y_rcd            INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_rcd";

        input                k2y_rcd_enq        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.k2y_rcd_enq";
        input                y2k_rcd_deq        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_rcd_deq";
        input                y2k_rel_enq        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_rel_enq";
        input  [8:0]         y2k_rel_rcd        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.y2k_rel_rcd";
}

interface dmu_clu_coverage {
        input                l2clk              CLOCK                   verilog_node "`DMU.dmc.l2clk";
        input                cl2pm_rcd_full     INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cl2pm_rcd_full";
        input                cm2cl_rcd_full     INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cm2cl_rcd_full";
        input                cl2ps_e_req        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cl2ps_e_req";
        input  [4:0]         cl2ps_e_trn        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cl2ps_e_trn";
}

interface dmu_pmu_coverage {
        input                l2clk              CLOCK                   verilog_node "`DMU.dmc.l2clk";
        input                pm2cm_rcd_full     INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.pm2cm_rcd_full";
        input                cl2pm_rcd_full     INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cl2pm_rcd_full";
}

interface dmu_psb_coverage {
        input                l2clk              CLOCK                   verilog_node "`DMU.dmc.l2clk";
        input                ps2pm_i_full       INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.ps2pm_i_full";
        input                ps2pm_i_gnt        INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.ps2pm_i_gnt";
        input  [4:0]         ps2pm_i_n_trn      INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.ps2pm_i_n_trn";
}


interface dmu_dmc_coverage {
        input                l2clk              CLOCK                   verilog_node "`DMU.dmc.l2clk";
        input  [3:0]         im2di_addr       INPUT_EDGE INPUT_SKEW     verilog_node "`DMU.dmc.im2di_addr";
        input  [15:0]        im2di_bmask      INPUT_EDGE INPUT_SKEW     verilog_node "`DMU.dmc.im2di_bmask";
        input                im2di_wr         INPUT_EDGE INPUT_SKEW     verilog_node "`DMU.dmc.im2di_wr";
        input  [8:0]         cl2di_addr       INPUT_EDGE INPUT_SKEW     verilog_node "`DMU.dmc.cl2di_addr";
        input                cl2di_rd         INPUT_EDGE INPUT_SKEW     verilog_node "`DMU.dmc.cl2di_rd_en";
        input                d2j_cmd_vld      INPUT_EDGE INPUT_SKEW     verilog_node "`DMU.dmc.d2j_cmd_vld";
        input                d2j_data_vld     INPUT_EDGE INPUT_SKEW     verilog_node "`DMU.dmc.d2j_data_vld";
        input  [3:0]         d2j_cmd         INPUT_EDGE INPUT_SKEW      verilog_node "`DMU.dmc.d2j_cmd";
}

interface dmu_cmu_coverage {
        input                l2clk              CLOCK                   verilog_node "`DMU.dmc.l2clk";
        input [92:0]         cm2pm_rcd          INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cm2pm_rcd";
        input                cm2pm_rcd_enq      INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cm2pm_rcd_enq";
        input [10:0]         maxpyld            INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cmu.rcm.maxpyld";
}

interface dmu_ncu_csr_if {
  input              clk                CLOCK                   verilog_node "`DMU.iol2clk";
  input              dmu_ncu_stall      INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmu_ncu_stall";
  input              ncu_dmu_stall      INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.ncu_dmu_stall";
}

interface dmu_debug {
  input              clk                CLOCK                   verilog_node "`DMU.iol2clk";
  input  [7:0]       jdi_dbg_a          INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmu_mio_debug_bus_a";
  input  [7:0]       jdi_dbg_b          INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmu_mio_debug_bus_b";
  input              dmu_dbg1_stall_ack INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmu_dbg1_stall_ack";
  input              dmu_dbg_err_event  INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmu_dbg_err_event";
  input              dbg1_dmu_stall     INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dbg1_dmu_stall";
  input              dbg1_dmu_resume    INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dbg1_dmu_resume";

  input  [63:0]      dbg_sel_a          INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cru.csr.dmu_cru_default_grp.dmc_dbg_sel_a_reg_csrbus_read_data";
  input  [63:0]      dbg_sel_b          INPUT_EDGE INPUT_SKEW   verilog_node "`DMU.dmc.cru.csr.dmu_cru_default_grp.dmc_dbg_sel_b_reg_csrbus_read_data";
}

interface dmu_int_controller_if {
  input              clk                CLOCK                   verilog_node "`DMU.dmc.imu.gcs.clk";
  input  [1:0]       intctl0            INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmc.imu.gcs.gc_0.fsm.state";
  input  [1:0]       intctl1            INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmc.imu.gcs.gc_1.fsm.state";
  input  [1:0]       intctl2            INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmc.imu.gcs.gc_2.fsm.state";
  input  [1:0]       intctl3            INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmc.imu.gcs.gc_3.fsm.state";
}

#ifdef FC_COVERAGE
interface dmu_int_relocation_if {
 input              clk                 CLOCK                   verilog_node "`DMU.dmc.imu.gcs.clk";
 input    [41:0]    reloc_cov_seq       INPUT_EDGE  INPUT_SKEW  verilog_node "dmu_int_relocation_cov_mon.seq_covered_status";
}
#endif

interface dmu_cov_ios {
 input              clk                 CLOCK                   verilog_node "`DMU.iol2clk";
 input      rcd_is_msi       INPUT_EDGE  INPUT_SKEW  verilog_node "`DMU.dmc.tmu.dim.rcd_is_msi";

        
}


#endif
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_cov.if.vrhpal
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#inc "dmu_cov_inc.pal";
	36	#ifndef __DMU_IF_VRH__
	37	#define __DMU_IF_VRH__
	38
	39	#include <vera_defines.vrh>
	40
	41	#define INPUT_EDGE PSAMPLE
	42	#define INPUT_SKEW #-3
	43	`define TOP tb_top
	44	`define DMU tb_top.cpu.dmu
	45
	46	interface dmu_coverage_ifc {
	47	// Common & Clock Signals
	48	input dmu_gclk CLOCK ;
	49	input dmu_rst_l PSAMPLE ;
	50
	51	// dmu interface
	52	input dmureq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_sii_hdr_vld";
	53	input dmubypass INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_sii_reqbypass";
	54	input dmudatareq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_sii_datareq";
	55	input dmudatareq16 INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_sii_datareq16";
	56	input [127:0] dmudata INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_sii_data";
	57	input [1:0] dmuparity INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_sii_parity";
	58	input [15:0] dmube INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_sii_be";
	59	input dmuwrack_vld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.sii_dmu_wrack_vld";
	60	input [3:0] dmuwrack_tag INPUT_EDGE INPUT_SKEW verilog_node "`DMU.sii_dmu_wrack_tag";
	61	input dmuwrack_par INPUT_EDGE INPUT_SKEW verilog_node "`DMU.sii_dmu_wrack_par";
	62
	63	//sio-dmu
	64	input sio_dmu_req INPUT_EDGE INPUT_SKEW verilog_node "`DMU.sio_dmu_hdr_vld";
65	input [127:0] sio_dmu_data INPUT_EDGE INPUT_SKEW verilog_node "`DMU.sio_dmu_data";
66	}
67
68	interface dmu_ncu_error_if {
69	input clk CLOCK verilog_node "`DMU.iol2clk";
70	input ncu_dmu_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_ctag_uei";
71	input ncu_dmu_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_ctag_cei";
72	input ncu_dmu_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_d_pei";
73	input ncu_dmu_siicr_pei INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_siicr_pei";
74	input ncu_dmu_ncucr_pei INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_ncucr_pei";
75	input ncu_dmu_iei INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_iei";
76
77	input dmu_ncu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_d_pe";
78	input dmu_ncu_siicr_pe INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_siicr_pe";
79	input dmu_ncu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_ctag_ue";
80	input dmu_ncu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_ctag_ce";
81	input dmu_ncu_ncucr_pe INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_ncucr_pe";
82	input dmu_ncu_ie INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_ie";
83	}
84
85	// #ifndef FC_COVERAGE
86	interface dmu_cov_dmupio {
87	input clk CLOCK verilog_node "`DMU.iol2clk";
88	input dmu_ncu_wrack_vld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_wrack_vld";
89	input [3:0] dmu_ncu_wrack_tag INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_wrack_tag";
90	input dmu_ncu_wrack_par INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_wrack_par";
91	input ncu_dmu_pio_hdr_vld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_pio_hdr_vld";
92	input ncu_dmu_mmu_addr_vld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_mmu_addr_vld";
93	input [63:0] ncu_dmu_pio_data INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_pio_data";
94	}
95	// #endif
96
97	interface dmu_ncu_mondo_if {
98	input clk CLOCK verilog_node "`DMU.iol2clk";
99	input ncu_dmu_mondo_ack INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_mondo_ack";
100	input ncu_dmu_mondo_nack INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_mondo_nack";
101	input [5:0] ncu_dmu_mondo_id INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_mondo_id";
102	input ncu_dmu_mondo_id_par INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_mondo_id_par";
103	}
104
105	interface ilu_dmu_coverage {
106	input clk CLOCK verilog_node "`DMU.iol2clk";
107	input [125:0] y2k_rcd INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_rcd";
108	input y2k_rcd_enq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_rcd_enq";
109
110	input [7:0] k2y_buf_addr INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_buf_addr";
111	input k2y_buf_addr_vld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_buf_addr_vld_monitor";
112	input [127:0] y2k_buf_data INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_buf_data";
113	input [3:0] y2k_buf_dpar INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_buf_dpar";
114
115	// egress release
116	input k2y_rcd_deq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_rcd_deq";
117	input k2y_rel_enq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_rel_enq";
118	input [8:0] k2y_rel_rcd INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_rel_rcd";
119	input [2:0] mps INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_mps";
120
121	}
122
123	interface dmu_ilu_coverage {
124	input clk CLOCK verilog_node "`DMU.iol2clk";
125	input [7:0] y2k_buf_addr INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_buf_addr";
126	input y2k_buf_addr_vld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_buf_addr_vld_monitor";
127	input [127:0] k2y_buf_data INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_buf_data";
128	input [3:0] k2y_buf_dpar INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_buf_dpar";
129	input [125:0] k2y_rcd INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_rcd";
130
131	input k2y_rcd_enq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.k2y_rcd_enq";
132	input y2k_rcd_deq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_rcd_deq";
133	input y2k_rel_enq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_rel_enq";
134	input [8:0] y2k_rel_rcd INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_rel_rcd";
135	}
136
137	interface dmu_clu_coverage {
138	input l2clk CLOCK verilog_node "`DMU.dmc.l2clk";
139	input cl2pm_rcd_full INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cl2pm_rcd_full";
140	input cm2cl_rcd_full INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cm2cl_rcd_full";
141	input cl2ps_e_req INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cl2ps_e_req";
142	input [4:0] cl2ps_e_trn INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cl2ps_e_trn";
143	}
144
145	interface dmu_pmu_coverage {
146	input l2clk CLOCK verilog_node "`DMU.dmc.l2clk";
147	input pm2cm_rcd_full INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.pm2cm_rcd_full";
148	input cl2pm_rcd_full INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cl2pm_rcd_full";
149	}
150
151	interface dmu_psb_coverage {
152	input l2clk CLOCK verilog_node "`DMU.dmc.l2clk";
153	input ps2pm_i_full INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.ps2pm_i_full";
154	input ps2pm_i_gnt INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.ps2pm_i_gnt";
155	input [4:0] ps2pm_i_n_trn INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.ps2pm_i_n_trn";
156	}
157
158
159	interface dmu_dmc_coverage {
160	input l2clk CLOCK verilog_node "`DMU.dmc.l2clk";
161	input [3:0] im2di_addr INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.im2di_addr";
162	input [15:0] im2di_bmask INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.im2di_bmask";
163	input im2di_wr INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.im2di_wr";
164	input [8:0] cl2di_addr INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cl2di_addr";
165	input cl2di_rd INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cl2di_rd_en";
166	input d2j_cmd_vld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.d2j_cmd_vld";
167	input d2j_data_vld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.d2j_data_vld";
168	input [3:0] d2j_cmd INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.d2j_cmd";
169	}
170
171	interface dmu_cmu_coverage {
172	input l2clk CLOCK verilog_node "`DMU.dmc.l2clk";
173	input [92:0] cm2pm_rcd INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cm2pm_rcd";
174	input cm2pm_rcd_enq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cm2pm_rcd_enq";
175	input [10:0] maxpyld INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cmu.rcm.maxpyld";
176	}
177
178	interface dmu_ncu_csr_if {
179	input clk CLOCK verilog_node "`DMU.iol2clk";
180	input dmu_ncu_stall INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_ncu_stall";
181	input ncu_dmu_stall INPUT_EDGE INPUT_SKEW verilog_node "`DMU.ncu_dmu_stall";
182	}
183
184	interface dmu_debug {
185	input clk CLOCK verilog_node "`DMU.iol2clk";
186	input [7:0] jdi_dbg_a INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_mio_debug_bus_a";
187	input [7:0] jdi_dbg_b INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_mio_debug_bus_b";
188	input dmu_dbg1_stall_ack INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_dbg1_stall_ack";
189	input dmu_dbg_err_event INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmu_dbg_err_event";
190	input dbg1_dmu_stall INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dbg1_dmu_stall";
191	input dbg1_dmu_resume INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dbg1_dmu_resume";
192
193	input [63:0] dbg_sel_a INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cru.csr.dmu_cru_default_grp.dmc_dbg_sel_a_reg_csrbus_read_data";
194	input [63:0] dbg_sel_b INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.cru.csr.dmu_cru_default_grp.dmc_dbg_sel_b_reg_csrbus_read_data";
195	}
196
197	interface dmu_int_controller_if {
198	input clk CLOCK verilog_node "`DMU.dmc.imu.gcs.clk";
199	input [1:0] intctl0 INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.imu.gcs.gc_0.fsm.state";
200	input [1:0] intctl1 INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.imu.gcs.gc_1.fsm.state";
201	input [1:0] intctl2 INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.imu.gcs.gc_2.fsm.state";
202	input [1:0] intctl3 INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.imu.gcs.gc_3.fsm.state";
203	}
204
205	#ifdef FC_COVERAGE
206	interface dmu_int_relocation_if {
207	input clk CLOCK verilog_node "`DMU.dmc.imu.gcs.clk";
208	input [41:0] reloc_cov_seq INPUT_EDGE INPUT_SKEW verilog_node "dmu_int_relocation_cov_mon.seq_covered_status";
209	}
210	#endif
211
212	interface dmu_cov_ios {
213	input clk CLOCK verilog_node "`DMU.iol2clk";
214	input rcd_is_msi INPUT_EDGE INPUT_SKEW verilog_node "`DMU.dmc.tmu.dim.rcd_is_msi";
215
216
217	}
218
219
220	#endif
221