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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ilu_ingress_sample.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #inc "dmu_cov_inc.pal"; | |
36 | ||
37 | #ifndef DMU_INTF_COV | |
38 | sample ilu_dmu_intf_iHdr_F_Type_cov (ilu_dmu_hdr_F_Type) { | |
39 | state PEC_Ingress_DMA_MRd32 ( 7'b0000000); | |
40 | state PEC_Ingress_DMA_MRd64 ( 7'b0100000); | |
41 | #ifndef DMU_INTF_COV | |
42 | state PEC_Ingress_DMA_MRdLk32 ( 7'b0000001); | |
43 | state PEC_Ingress_DMA_MRdLk64 ( 7'b0100001); | |
44 | #endif | |
45 | state PEC_Ingress_Unsupported ( 7'b0001001); | |
46 | state PEC_Ingress_DMA_MWr32 ( 7'b1000000); | |
47 | state PEC_Ingress_DMA_MWr64 ( 7'b1100000); | |
48 | wildcard state PEC_Ingress_Msg ( 7'b0110xxx); | |
49 | state PEC_Ingress_PIO_Cpl ( 7'b0001010); | |
50 | state PEC_Ingress_PIO_CplD ( 7'b1001010); | |
51 | } | |
52 | ||
53 | ||
54 | ||
55 | sample ilu_dmu_intf_iHdr_DMARd_Len_cov (ilu_dmu_hdr_Len) { | |
56 | m_state DMA_MRd_mps128(0:1023) if ((ilu_dmu_hdr_F_Type =?= 7'b0x0000x) && (ilu_dmu_mps==3'b000)); | |
57 | m_state DMA_MRd_mps256(0:1023) if ((ilu_dmu_hdr_F_Type =?= 7'b0x0000x) && (ilu_dmu_mps==3'b001)); | |
58 | m_state DMA_MRd_mps512(0:1023) if ((ilu_dmu_hdr_F_Type =?= 7'b0x0000x) && (ilu_dmu_mps==3'b010)); | |
59 | } | |
60 | ||
61 | sample ilu_dmu_intf_iHdr_TC_cov (ilu_dmu_hdr_TC) { | |
62 | . &toggle(3); | |
63 | cov_weight = 1; | |
64 | } | |
65 | ||
66 | sample ilu_dmu_intf_iHdr_Atr_cov (ilu_dmu_hdr_Atr) { | |
67 | . &toggle(2); | |
68 | cov_weight = 1; | |
69 | } | |
70 | ||
71 | sample ilu_dmu_intf_iHdr_ReqID_cov (ilu_dmu_hdr_ReqID) { | |
72 | . &toggle(16); | |
73 | cov_weight = 1; | |
74 | } | |
75 | ||
76 | sample ilu_dmu_intf_iHdr_TLPTag_cov (ilu_dmu_hdr_TLPTag) { | |
77 | . &toggle(8); | |
78 | cov_weight = 1; | |
79 | } | |
80 | ||
81 | sample ilu_dmu_intf_iHdr_LastDWBE_cov (ilu_dmu_hdr_LastDWBE) { | |
82 | m_state DWBE (0:15); | |
83 | cov_weight = 1; | |
84 | } | |
85 | ||
86 | sample ilu_dmu_intf_iHdr_FirstDWBE_cov (ilu_dmu_hdr_FirstDWBE) { | |
87 | m_state DWBE (0:15); | |
88 | cov_weight = 1; | |
89 | } | |
90 | ||
91 | sample ilu_dmu_intf_iHdr_Addr_cov (ilu_dmu_hdr_Addr) { | |
92 | . &toggle(62); | |
93 | cov_weight = 1; | |
94 | } | |
95 | ||
96 | #endif | |
97 | ||
98 | ||
99 | sample dmu_peu_intf_intr_intx_dup_msg_cov (intx_dup_reg) { | |
100 | wildcard state ASSERT_INTA_B2B ( 8'bxxxxxxx1); | |
101 | wildcard state ASSERT_INTB_B2B ( 8'bxxxxxx1x); | |
102 | wildcard state ASSERT_INTC_B2B ( 8'bxxxxx1xx); | |
103 | wildcard state ASSERT_INTD_B2B ( 8'bxxxx1xxx); | |
104 | wildcard state DE_ASSERT_INTA_B2B ( 8'bxxx1xxxx); | |
105 | wildcard state DE_ASSERT_INTB_B2B ( 8'bxx1xxxxx); | |
106 | wildcard state DE_ASSERT_INTC_B2B ( 8'bx1xxxxxx); | |
107 | wildcard state DE_ASSERT_INTD_B2B ( 8'b1xxxxxxx); | |
108 | } | |
109 | ||
110 | sample dmu_peu_intf_intr_intx_msg_cov (ilu_dmu_hdr_msg_code) { | |
111 | state Assert_INTA ( 8'b00100000) if (ilu_dmu_hdr_F_Type == 7'b0110100); | |
112 | state Assert_INTB ( 8'b00100001) if (ilu_dmu_hdr_F_Type == 7'b0110100); | |
113 | state Assert_INTC ( 8'b00100010) if (ilu_dmu_hdr_F_Type == 7'b0110100); | |
114 | state Assert_INTD ( 8'b00100011) if (ilu_dmu_hdr_F_Type == 7'b0110100); | |
115 | state Deasert_INTA ( 8'b00100100) if (ilu_dmu_hdr_F_Type == 7'b0110100); | |
116 | state Deasert_INTB ( 8'b00100101) if (ilu_dmu_hdr_F_Type == 7'b0110100); | |
117 | state Deasert_INTC ( 8'b00100110) if (ilu_dmu_hdr_F_Type == 7'b0110100); | |
118 | state Deasert_INTD ( 8'b00100111) if (ilu_dmu_hdr_F_Type == 7'b0110100); | |
119 | } | |
120 | ||
121 | ||
122 | sample dmu_peu_intf_intr_pwr_msg_cov (ilu_dmu_hdr_msg_code) { | |
123 | state PM_PME ( 8'b00011000) if (ilu_dmu_hdr_F_Type == 7'b0110000); | |
124 | state PME_TO_ACK ( 8'b00011011) if (ilu_dmu_hdr_F_Type == 7'b0110101); | |
125 | state ERR_COR ( 8'b00110000) if (ilu_dmu_hdr_F_Type == 7'b0110000); | |
126 | state ERR_NONFTAL ( 8'b00110001) if (ilu_dmu_hdr_F_Type == 7'b0110000); | |
127 | state ERR_FATAL ( 8'b00110011) if (ilu_dmu_hdr_F_Type == 7'b0110000); | |
128 | } |