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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_sii_sample.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #inc "dmu_cov_inc.pal"; | |
36 | ||
37 | sample dmu_sii_cmd_sample_this (this_dmu_cmd) | |
38 | { | |
39 | state RDD_ord ( 7'b0010_100 ); | |
40 | state WRI_pstd_ord ( 7'b0100_100 ); | |
41 | state WRM_pstd_ord ( 7'b0101_100 ); | |
42 | state PIO_RD_RET ( 7'b1010_011 ); | |
43 | state INT ( 7'b0000_010 ); | |
44 | cov_weight = 0; | |
45 | } | |
46 | ||
47 | . $j = 5; | |
48 | . $k = 2; | |
49 | . for ($i=1; $i<11; $i++) | |
50 | . { | |
51 | sample dmu_sii_cmd_sample_${i}_clk_last (last_dmu_cmd) | |
52 | { | |
53 | state RDD_ord ( 7'b0010_100 ) if (dmu_back_to_back == ${i}); | |
54 | state WRI_pstd_ord ( 7'b0100_100 ) if (dmu_back_to_back == ${j}); | |
55 | state WRM_pstd_ord ( 7'b0101_100 ) if (dmu_back_to_back == ${j}); | |
56 | state PIO_RD_RET ( 7'b1010_011 ) if (dmu_back_to_back == ${k}); | |
57 | state INT ( 7'b0000_010 ) if (dmu_back_to_back == ${k}); | |
58 | . $j++; | |
59 | . $k++; | |
60 | cov_weight = 0; | |
61 | } | |
62 | .} | |
63 | ||
64 | ||
65 | // bins for back to back dmu commands | |
66 | . for ($i=1; $i<11; $i++) | |
67 | . { | |
68 | cross dmu_sii_cmd_${i}_clk_cross (dmu_sii_cmd_sample_${i}_clk_last, dmu_sii_cmd_sample_this) | |
69 | { | |
70 | cov_weight = 2; | |
71 | } | |
72 | .} | |
73 | ||
74 | sample dmu_sii_byte_en_sample ( dmu_sii_byte_en ) | |
75 | { | |
76 | . &toggle( 16 ); | |
77 | ||
78 | cov_weight = 1; | |
79 | } | |
80 | ||
81 | sample dmu_siu_intf_iHdr_AddrPar_cov (dmu_sii_parity) | |
82 | { | |
83 | . &toggle( 2 ); | |
84 | cov_weight = 1; | |
85 | } | |
86 | ||
87 | sample dmu_siu_intf_iHdr_PioTimeoutErr_cov (dmu_sii_pio_cpl_to_err) | |
88 | { | |
89 | m_state (0:1) if (this_dmu_cmd == 7'b1010_011); | |
90 | cov_weight = 1; | |
91 | } | |
92 | ||
93 | sample dmu_siu_intf_iHdr_PioUnmapAddrErr_cov (dmu_sii_pio_cpl_bus_err) | |
94 | { | |
95 | m_state (0:1) if (this_dmu_cmd == 7'b1010_011); | |
96 | cov_weight = 1; | |
97 | } | |
98 | ||
99 | sample dmu_siu_intf_iHdr_PioDmcTag_CreditId_cov (dmc_tag[11:8]) | |
100 | { | |
101 | m_state (0:15) if (this_dmu_cmd == 7'b1010_011); | |
102 | cov_weight = 1; | |
103 | } | |
104 | ||
105 | sample dmu_siu_intf_iHdr_PioDmcTag_ThreadId_cov (dmc_tag[6:0]) | |
106 | { | |
107 | m_state (0:127) if (this_dmu_cmd == 7'b1010_011); | |
108 | cov_weight = 1; | |
109 | } | |
110 | ||
111 | // make sure all bits of the dmc tag field are toggled. | |
112 | sample dmu_siu_intf_iHdr_DmaDmcTag_cov (dmc_tag) | |
113 | { | |
114 | wildcard state s_bit_15_0 ( 16'b0xxxxxxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
115 | wildcard state s_bit_15_1 ( 16'b1xxxxxxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
116 | wildcard state s_bit_14_0 ( 16'bx0xxxxxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
117 | wildcard state s_bit_14_1 ( 16'bx1xxxxxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
118 | wildcard state s_bit_13_0 ( 16'bxx0xxxxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
119 | wildcard state s_bit_13_1 ( 16'bxx1xxxxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
120 | wildcard state s_bit_12_0 ( 16'bxxx0xxxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
121 | wildcard state s_bit_12_1 ( 16'bxxx1xxxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
122 | wildcard state s_bit_11_0 ( 16'bxxxx0xxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
123 | wildcard state s_bit_11_1 ( 16'bxxxx1xxxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
124 | wildcard state s_bit_10_0 ( 16'bxxxxx0xxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
125 | wildcard state s_bit_10_1 ( 16'bxxxxx1xxxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
126 | wildcard state s_bit_09_0 ( 16'bxxxxxx0xxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
127 | wildcard state s_bit_09_1 ( 16'bxxxxxx1xxxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
128 | wildcard state s_bit_08_0 ( 16'bxxxxxxx0xxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
129 | wildcard state s_bit_08_1 ( 16'bxxxxxxx1xxxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
130 | wildcard state s_bit_07_0 ( 16'bxxxxxxxx0xxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
131 | wildcard state s_bit_07_1 ( 16'bxxxxxxxx1xxxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
132 | wildcard state s_bit_06_0 ( 16'bxxxxxxxxx0xxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
133 | wildcard state s_bit_06_1 ( 16'bxxxxxxxxx1xxxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
134 | wildcard state s_bit_05_0 ( 16'bxxxxxxxxxx0xxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
135 | wildcard state s_bit_05_1 ( 16'bxxxxxxxxxx1xxxxx ) if (this_dmu_cmd != 7'b1010_011); | |
136 | wildcard state s_bit_04_0 ( 16'bxxxxxxxxxxx0xxxx ) if (this_dmu_cmd != 7'b1010_011); | |
137 | wildcard state s_bit_04_1 ( 16'bxxxxxxxxxxx1xxxx ) if (this_dmu_cmd != 7'b1010_011); | |
138 | wildcard state s_bit_03_0 ( 16'bxxxxxxxxxxxx0xxx ) if (this_dmu_cmd != 7'b1010_011); | |
139 | wildcard state s_bit_03_1 ( 16'bxxxxxxxxxxxx1xxx ) if (this_dmu_cmd != 7'b1010_011); | |
140 | wildcard state s_bit_02_0 ( 16'bxxxxxxxxxxxxx0xx ) if (this_dmu_cmd != 7'b1010_011); | |
141 | wildcard state s_bit_02_1 ( 16'bxxxxxxxxxxxxx1xx ) if (this_dmu_cmd != 7'b1010_011); | |
142 | wildcard state s_bit_01_0 ( 16'bxxxxxxxxxxxxxx0x ) if (this_dmu_cmd != 7'b1010_011); | |
143 | wildcard state s_bit_01_1 ( 16'bxxxxxxxxxxxxxx1x ) if (this_dmu_cmd != 7'b1010_011); | |
144 | wildcard state s_bit_00_0 ( 16'bxxxxxxxxxxxxxxx0 ) if (this_dmu_cmd != 7'b1010_011); | |
145 | wildcard state s_bit_00_1 ( 16'bxxxxxxxxxxxxxxx1 ) if (this_dmu_cmd != 7'b1010_011); | |
146 | cov_weight = 1; | |
147 | } | |
148 | ||
149 | sample dmu_siu_intf_iHdr_CtagECC_cov (dmudata[61:56]) | |
150 | { | |
151 | cov_weight = 1; | |
152 | } | |
153 | ||
154 | sample dmu_siu_intf_iHdr_Type_cov ({dmu_sii_datareq,dmu_sii_datareq16,dmubypass}) | |
155 | { | |
156 | state NO_DATA (3'b000); | |
157 | state FOUR_DB (3'b100); | |
158 | state ONE_DB (3'b110); | |
159 | state INTPIO_ONE_DB (3'b111); | |
160 | cov_weight = 1; | |
161 | } | |
162 | ||
163 |