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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_dmu_pio_sample.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | coverage_goal = 100; // override default of 90% | |
36 | cross_num_print_missing = (1 << 32) - 1; // INT_MAX | |
37 | ||
38 | sample ncu_dmu_intf_PIO_CreditId_cov (ncu_pio_credit) | |
39 | { | |
40 | m_state PIO_CREDIT (0:15); | |
41 | } | |
42 | ||
43 | sample ncu_dmu_intf_PIOWrMem_Cmd_cov ({ncu_pio_wr,ncu_pio_cmd}) | |
44 | { | |
45 | state PIO_WR_MEM32 (3'b010); | |
46 | state PIO_WR_MEM64 (3'b011); | |
47 | cov_weight = 0; | |
48 | } | |
49 | ||
50 | sample ncu_dmu_intf_PIOWrCfgIO_Cmd_cov ({ncu_pio_wr,ncu_pio_cmd}) | |
51 | { | |
52 | state PIO_WR_CONFIG (3'b000); | |
53 | state PIO_WR_IO (3'b001); | |
54 | cov_weight = 0; | |
55 | } | |
56 | ||
57 | sample ncu_dmu_intf_PIORdMem_Cmd_cov ({ncu_pio_wr,ncu_pio_cmd}) | |
58 | { | |
59 | state PIO_RD_MEM32 (3'b110); | |
60 | state PIO_RD_MEM64 (3'b111); | |
61 | cov_weight = 0; | |
62 | } | |
63 | sample ncu_dmu_intf_PIORdCfgIO_Cmd_cov ({ncu_pio_wr,ncu_pio_cmd}) | |
64 | { | |
65 | state PIO_RD_CONFIG (3'b100); | |
66 | state PIO_RD_IO (3'b101); | |
67 | cov_weight = 0; | |
68 | } | |
69 | ||
70 | sample ncu_dmu_intf_PIORd_Cmd_cov ({ncu_pio_wr,ncu_pio_cmd}) | |
71 | { | |
72 | state PIO_RD_CONFIG (3'b100); | |
73 | state PIO_RD_IO (3'b101); | |
74 | state PIO_RD_MEM32 (3'b110); | |
75 | state PIO_RD_MEM64 (3'b111); | |
76 | cov_weight = 0; | |
77 | } | |
78 | ||
79 | // PIO Config/IO's write/read byte masks | |
80 | // Concatenate bytemask with address[3] to cover all byte & address alignments | |
81 | // Address is aligned to # of bytes and only 1,2,4,8 are legal for writes | |
82 | sample ncu_dmu_intf_PIOWrCfgIO_bmsk_cov ({ncu_pio_add[3],ncu_pio_bmsk}) | |
83 | { | |
84 | // 1 Byte | |
85 | m_state BMsk1B_even (9'b000000001, 9'b000000010, 9'b000000100, 9'b000001000, | |
86 | 9'b000010000, 9'b000100000, 9'b001000000, 9'b010000000) if (ncu_pio_wr == 1'b0); | |
87 | m_state BMsk1B_odd (9'b100000001, 9'b100000010, 9'b100000100, 9'b100001000, | |
88 | 9'b100010000, 9'b100100000, 9'b101000000, 9'b110000000) if (ncu_pio_wr == 1'b0); | |
89 | // 2 Byte | |
90 | m_state BMsk2B_even (9'b000000011, 9'b000001100, 9'b000110000, 9'b011000000) if (ncu_pio_wr == 1'b0); | |
91 | m_state BMsk2B_odd (9'b100000011, 9'b100001100, 9'b100110000, 9'b111000000) if (ncu_pio_wr == 1'b0); | |
92 | // 4 Byte | |
93 | m_state BMsk4B_even (9'b000001111, 9'b011110000) if (ncu_pio_wr == 1'b0); | |
94 | m_state BMsk4B_odd (9'b100001111, 9'b111110000) if (ncu_pio_wr == 1'b0); | |
95 | cov_weight = 0; | |
96 | } | |
97 | ||
98 | // PIOMemWr - 1,2,4,8 bytes + partial. Partial case covers 1,2,4,8 cases | |
99 | // Partial Store's to PIO MEM space can use and 8 bit value in byte mask | |
100 | // Concatenate bytemask with address[3] to cover all byte & address alignments | |
101 | sample ncu_dmu_intf_PIOWr_bmsk_cov ({ncu_pio_add[3], ncu_pio_bmsk}) | |
102 | { | |
103 | m_state BMsk_even (0:255) if (ncu_pio_wr == 1'b0); | |
104 | m_state BMsk_odd (256:511) if (ncu_pio_wr == 1'b0); | |
105 | cov_weight = 0; | |
106 | } | |
107 | ||
108 | // cross/sample PIO Read commands with length and address offsets | |
109 | sample ncu_dmu_intf_PIORd_addr1_cov (ncu_pio_add[3:0]) { | |
110 | m_state Addr3to0(0:15) if (ncu_pio_wr == 1'b1); | |
111 | cov_weight = 0; | |
112 | } | |
113 | sample ncu_dmu_intf_PIORd_size1B_cov (ncu_pio_size) { | |
114 | state Size1B (3'b000) if (ncu_pio_wr == 1'b1); | |
115 | cov_weight = 0; | |
116 | } | |
117 | ||
118 | sample ncu_dmu_intf_PIORd_addr2_cov (ncu_pio_add[3:1]) { | |
119 | m_state Addr3to1(0:7) if (ncu_pio_wr == 1'b1); | |
120 | cov_weight = 0; | |
121 | } | |
122 | sample ncu_dmu_intf_PIORd_size2B_cov (ncu_pio_size) { | |
123 | state Size2B (3'b001) if (ncu_pio_wr == 1'b1); | |
124 | cov_weight = 0; | |
125 | } | |
126 | ||
127 | sample ncu_dmu_intf_PIORd_addr4_cov (ncu_pio_add[3:2]) { | |
128 | m_state Addr3to2(0:3) if (ncu_pio_wr == 1'b1); | |
129 | cov_weight = 0; | |
130 | } | |
131 | sample ncu_dmu_intf_PIORd_size4B_cov (ncu_pio_size) { | |
132 | state Size4B (3'b010) if (ncu_pio_wr == 1'b1); | |
133 | cov_weight = 0; | |
134 | } | |
135 | ||
136 | sample ncu_dmu_intf_PIORd_addr8_cov (ncu_pio_add[3:3]) { | |
137 | m_state Addr3to3(0:1) if (ncu_pio_wr == 1'b1); | |
138 | cov_weight = 0; | |
139 | } | |
140 | sample ncu_dmu_intf_PIORd_size8B_cov (ncu_pio_size) { | |
141 | state Size8B (3'b011) if (ncu_pio_wr == 1'b1); | |
142 | cov_weight = 0; | |
143 | } | |
144 | ||
145 | // 16B PIO Reads are supported by DMU but not FC | |
146 | #ifndef DMU_INTF_COV | |
147 | sample ncu_dmu_intf_PIORd_addr16_cov (ncu_pio_add[3:0]) { | |
148 | state Addr3to0 (0) if (ncu_pio_wr == 1'b1); | |
149 | cov_weight = 0; | |
150 | } | |
151 | sample ncu_dmu_intf_PIORd_size16B_cov (ncu_pio_size) { | |
152 | state Size16B (3'b100) if (ncu_pio_wr == 1'b1); | |
153 | cov_weight = 0; | |
154 | } | |
155 | #endif | |
156 | ||
157 | cross ncu_dmu_intf_PIOWrCfgIO_Bmsk_cov (ncu_dmu_intf_PIOWrCfgIO_Cmd_cov, | |
158 | ncu_dmu_intf_PIOWrCfgIO_bmsk_cov); | |
159 | ||
160 | cross ncu_dmu_intf_PIOWrMem_Bmsk_cov (ncu_dmu_intf_PIOWrMem_Cmd_cov, | |
161 | ncu_dmu_intf_PIOWr_bmsk_cov); | |
162 | ||
163 | cross ncu_dmu_intf_PIORd_AddrSize1B_cov (ncu_dmu_intf_PIORd_Cmd_cov, | |
164 | ncu_dmu_intf_PIORd_addr1_cov, | |
165 | ncu_dmu_intf_PIORd_size1B_cov); | |
166 | ||
167 | cross ncu_dmu_intf_PIORd_AddrSize2B_cov (ncu_dmu_intf_PIORd_Cmd_cov, | |
168 | ncu_dmu_intf_PIORd_addr2_cov, | |
169 | ncu_dmu_intf_PIORd_size2B_cov); | |
170 | ||
171 | cross ncu_dmu_intf_PIORd_AddrSize4B_cov (ncu_dmu_intf_PIORd_Cmd_cov, | |
172 | ncu_dmu_intf_PIORd_addr4_cov, | |
173 | ncu_dmu_intf_PIORd_size4B_cov); | |
174 | ||
175 | cross ncu_dmu_intf_PIORdMem_AddrSize8B_cov (ncu_dmu_intf_PIORdMem_Cmd_cov, | |
176 | ncu_dmu_intf_PIORd_addr8_cov, | |
177 | ncu_dmu_intf_PIORd_size8B_cov); | |
178 | ||
179 | // 16B PIO Reads are supported by DMU but not FC | |
180 | #ifndef DMU_INTF_COV | |
181 | cross ncu_dmu_intf_PIORdMem_AddrSize16B_cov (ncu_dmu_intf_PIORdMem_Cmd_cov, | |
182 | ncu_dmu_intf_PIORd_addr16_cov, | |
183 | ncu_dmu_intf_PIORd_size16B_cov); | |
184 | #endif | |
185 | ||
186 | sample ncu_dmu_intf_PIO_CmdMap_cov (ncu_pio_cmap) | |
187 | { | |
188 | m_state PIO_CMAP (0:3); | |
189 | } | |
190 | ||
191 | sample ncu_dmu_intf_PIO_BufId_cov (ncu_pio_bufid) | |
192 | { | |
193 | //m_state BUFID (0:1) ; // need jtag to access BUFID == 1 | |
194 | state BUFID (0) ; | |
195 | } | |
196 | ||
197 | sample ncu_dmu_intf_PIO_CPUThread_cov (ncu_pio_cpu) | |
198 | { | |
199 | m_state CPUThread (0:63); | |
200 | } | |
201 | ||
202 | sample ncu_dmu_intf_PIO_PA_cov (ncu_pio_add[35:3]) | |
203 | { | |
204 | state PIO_ADD (0:33'h1ffffffff); | |
205 | at_least = 100; | |
206 | } | |
207 | ||
208 | sample ncu_dmu_intf_PIO_b2b_cov (ncu_pio_b2b) | |
209 | { | |
210 | m_state PIO_B2B (2:32) ; | |
211 | } |