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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / fc / fc_coverage.vrpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_coverage.vrpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include <ListMacros.vrh>
37#include "plusArgMacros.vri"
38#include "std_display_class.vrh"
39#include "std_display_defines.vri"
40#include "fc_cov.if.vrh"
41#include "fc_cov_ports_binds.vrh"
42
43////////////////////////////////////////////////////////////////////////////
44//Adding modes coverage object
45///////////////////////////////////////////////////////////////////////////
46
47class fc_modes_cov
48{
49 // for dispmon
50// StandardDisplay dbg;
51// local string myname;
52
53
54 //PLL Control reg
55 coverage_group N2_modes_coverage_group {
56 sample_event = @(posedge fc_modes_cov_if.boot_done);
57 //sample_event = wait_var(gOutOfBoot); //Global
58 sample cmp_dr_ratio ({fc_modes_cov_if.pll_div4,
59 fc_modes_cov_if.pll_div3,
60 fc_modes_cov_if.pll_div2,
61 fc_modes_cov_if.pll_div1
62 })
63 {
64 wildcard state CMP_DR_RATIO_2_00 ({6'h8, 6'h1, 6'h7, 6'h1});
65 wildcard state CMP_DR_RATIO_2_75 ({6'hb, 6'h1, 6'ha, 6'h1});
66 wildcard state CMP_DR_RATIO_3_50 ({6'he, 6'h1, 6'hd, 6'h1});
67 wildcard state CMP_DR_RATIO_3_75 ({6'hf, 6'h1, 6'he, 6'h1});
68 wildcard state CMP_DR_RATIO_4_00 ({6'h10, 6'h1, 6'hf, 6'h1});
69 wildcard state CMP_DR_RATIO_4_25 ({6'h11, 6'h1, 6'h10, 6'h1});
70 }
71
72//System clock
73 sample system_clock_freq (fc_modes_cov_if.system_clock)
74 {
75 wildcard state system_clock_166 ({2'b00});
76 wildcard state system_clock_133 ({2'b01});
77 }
78
79//Index hashing
80 sample index_hashing (fc_modes_cov_if.hash_enable)
81 {
82 wildcard state index_hash_ON ({1'b1});
83 wildcard state index_hash_OFF ({1'b0});
84 }
85//PCIE ref clock
86 sample pcie_ref_clock (fc_modes_cov_if.pcie_ref_clk)
87 {
88 wildcard state PCIE_REF_CLK_100 ({2'b00});
89 wildcard state PCIE_REF_CLK_150 ({2'b01}); //not usefull
90 wildcard state PCIE_REF_CLK_250 ({2'b10}); //not usefull
91 }
92
93//PCIE mps
94 sample pcie_mps (fc_modes_cov_if.pcie_mps)
95 {
96 wildcard state PCIE_MPS_128 ({3'b000}); //not usefull
97 wildcard state PCIE_MPS_256 ({3'b001});
98 wildcard state PCIE_MPS_512 ({3'b010});
99 }
100
101//Random efu redundancy
102 sample RANDOM_REDUNDANCY_VALUES (fc_modes_cov_if.RANDOM_REDUNDANCY_VALUES)
103 {
104 wildcard state RANDOM_REDUNDANCY_VALUES_ON ({1'b1});
105// wildcard state RANDOM_REDUNDANCY_VALUES_OFF ({1'b0});
106 }
107
108//Denali link width
109 sample denali_link_width (fc_modes_cov_if.denali_link_width)
110 {
111 wildcard state denali_link_width_1 ({4'b0001}); //low priortiy
112 wildcard state denali_link_width_2 ({4'b0010}); //low prio
113 wildcard state denali_link_width_4 ({4'b0100}); //low prio
114 wildcard state denali_link_width_8 ({4'b1000}); //low prio
115 }
116
117//NCU clock ratio
118 sample ssi_clk_ratio (fc_modes_cov_if.ncu_clk_ratio)
119 {
120 wildcard state SSI_CLK_RATIO_8 ({1'b0});
121 wildcard state SSI_CLK_RATIO_4 ({1'b1}); //low prior
122 }
123//RANDOM_POR_RST
124 sample RANDOM_POR_RST (fc_modes_cov_if.RANDOM_POR_RST)
125 {
126 wildcard state RANDOM_POR_RST ({1'b1});
127 }
128
129//RANDOM_PB_RST
130 sample RANDOM_PB_RST (fc_modes_cov_if.RANDOM_PB_RST)
131 {
132 wildcard state RANDOM_PB_RST ({1'b1});
133 }
134
135//AMB used
136 sample amb_used (fc_modes_cov_if.amb_used) {
137 wildcard state SUN_AMB ({2'b00}); //low prio
138 wildcard state IDT_AMB ({2'b01});
139 wildcard state NEC_AMB ({2'b11});
140 }
141//Memory Configurations
142//{SNG_CHANNEL, NO_OF_DIMMS, SIZE_512, RANK_SEL, STACK_DIMM}
143#define SNG_CHANNEL 1'b1
144#define DUAL_CHANNEL 1'b0
145
146#define FBDIMM_1 3'h1
147#define FBDIMM_2 3'h2
148#define FBDIMM_3 3'h3
149#define FBDIMM_4 3'h4
150#define FBDIMM_5 3'h5
151#define FBDIMM_6 3'h6
152#define FBDIMM_7 3'h7
153#define FBDIMM_8 3'h0
154
155#define DIMM_SIZE_1G 5'h1e
156#define DIMM_SIZE_2G 5'h1f
157#define DIMM_SIZE_512 5'h0e
158#define DIMM_SIZE_256 5'h0d
159
160#define STACK_DIMM 1'b1
161#define NO_STACK_DIMM 1'b0
162
163#define RANK_LOW 1'b1
164#define RANK_HIGH 1'b0
165
166
167 sample memory_config ({fc_modes_cov_if.single_channel, fc_modes_cov_if.no_of_dimms, fc_modes_cov_if.mem_density, fc_modes_cov_if.rank_sel, fc_modes_cov_if.stack_dimm}) {
168
169wildcard state sng_channel__1_fbdimm__dimm_size_512__rank_low ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_512, RANK_LOW ,NO_STACK_DIMM});
170wildcard state sng_channel__1_fbdimm__dimm_size_512__rank_high ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_512, RANK_HIGH ,NO_STACK_DIMM});
171wildcard state sng_channel__1_fbdimm__dimm_size_1g__rank_low ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_1G, RANK_LOW ,NO_STACK_DIMM});
172wildcard state sng_channel__1_fbdimm__dimm_size_1g__rank_high ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_1G, RANK_HIGH ,NO_STACK_DIMM});
173wildcard state sng_channel__1_fbdimm__dimm_size_2g__rank_low ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_2G, RANK_LOW ,NO_STACK_DIMM});
174wildcard state sng_channel__1_fbdimm__dimm_size_2g__rank_high ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_2G, RANK_HIGH ,NO_STACK_DIMM});
175wildcard state sng_channel__2_fbdimms__dimm_size_512__rank_low ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_512, RANK_LOW ,NO_STACK_DIMM});
176wildcard state sng_channel__2_fbdimms__dimm_size_512__rank_high ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_512, RANK_HIGH,NO_STACK_DIMM});
177wildcard state sng_channel__2_fbdimms__dimm_size_1g__rank_low ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_1G, RANK_LOW ,NO_STACK_DIMM});
178wildcard state sng_channel__2_fbdimms__dimm_size_1g__rank_high ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_1G, RANK_HIGH ,NO_STACK_DIMM});
179wildcard state sng_channel__2_fbdimms__dimm_size_2g__rank_low ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_2G, RANK_LOW ,NO_STACK_DIMM});
180wildcard state sng_channel__2_fbdimms__dimm_size_2g__rank_high ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_2G, RANK_HIGH ,NO_STACK_DIMM});
181wildcard state sng_channel__4_fbdimms__dimm_size_512__rank_low ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_512, RANK_LOW ,NO_STACK_DIMM});
182wildcard state sng_channel__4_fbdimms__dimm_size_512__rank_high ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_512, RANK_HIGH,NO_STACK_DIMM});
183wildcard state sng_channel__4_fbdimms__dimm_size_1g__rank_low ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_1G, RANK_LOW ,NO_STACK_DIMM});
184wildcard state sng_channel__4_fbdimms__dimm_size_1g__rank_high ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_1G, RANK_HIGH ,NO_STACK_DIMM});
185wildcard state sng_channel__4_fbdimms__dimm_size_2g__rank_low ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_2G, RANK_LOW ,NO_STACK_DIMM});
186wildcard state sng_channel__4_fbdimms__dimm_size_2g__rank_high ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_2G, RANK_HIGH ,NO_STACK_DIMM});
187
188//2 RANKS
189wildcard state sng_channel__1_fbdimm__dimm_size_512__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_512, RANK_LOW ,STACK_DIMM});
190wildcard state sng_channel__1_fbdimm__dimm_size_512__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_512, RANK_HIGH ,STACK_DIMM});
191wildcard state sng_channel__1_fbdimm__dimm_size_1g__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_1G, RANK_LOW ,STACK_DIMM});
192wildcard state sng_channel__1_fbdimm__dimm_size_1g__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_1G, RANK_HIGH ,STACK_DIMM});
193wildcard state sng_channel__1_fbdimm__dimm_size_2g__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_2G, RANK_LOW ,STACK_DIMM});
194wildcard state sng_channel__1_fbdimm__dimm_size_2g__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_1, DIMM_SIZE_2G, RANK_HIGH ,STACK_DIMM});
195wildcard state sng_channel__2_fbdimms__dimm_size_512__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_512, RANK_LOW ,STACK_DIMM});
196wildcard state sng_channel__2_fbdimms__dimm_size_512__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_512, RANK_HIGH,STACK_DIMM});
197wildcard state sng_channel__2_fbdimms__dimm_size_1g__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_1G, RANK_LOW ,STACK_DIMM});
198wildcard state sng_channel__2_fbdimms__dimm_size_1g__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_1G, RANK_HIGH ,STACK_DIMM});
199wildcard state sng_channel__2_fbdimms__dimm_size_2g__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_2G, RANK_LOW ,STACK_DIMM});
200wildcard state sng_channel__2_fbdimms__dimm_size_2g__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_2, DIMM_SIZE_2G, RANK_HIGH ,STACK_DIMM});
201wildcard state sng_channel__4_fbdimms__dimm_size_512__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_512, RANK_LOW ,STACK_DIMM});
202wildcard state sng_channel__4_fbdimms__dimm_size_512__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_512, RANK_HIGH,STACK_DIMM});
203wildcard state sng_channel__4_fbdimms__dimm_size_1g__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_1G, RANK_LOW ,STACK_DIMM});
204wildcard state sng_channel__4_fbdimms__dimm_size_1g__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_1G, RANK_HIGH ,STACK_DIMM});
205wildcard state sng_channel__4_fbdimms__dimm_size_2g__rank_low__stack_dimm ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_2G, RANK_LOW ,STACK_DIMM});
206wildcard state sng_channel__4_fbdimms__dimm_size_2g__rank_high_stack_dimm ({ SNG_CHANNEL, FBDIMM_4, DIMM_SIZE_2G, RANK_HIGH ,STACK_DIMM});
207
208//DUAL_CHANNEL
209wildcard state dual_channel__1_fbdimm__dimm_size_512__rank_low ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_512, RANK_LOW ,NO_STACK_DIMM});
210wildcard state dual_channel__1_fbdimm__dimm_size_512__rank_high ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_512, RANK_HIGH ,NO_STACK_DIMM});
211wildcard state dual_channel__1_fbdimm__dimm_size_1g__rank_low ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_1G, RANK_LOW ,NO_STACK_DIMM});
212wildcard state dual_channel__1_fbdimm__dimm_size_1g__rank_high ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_1G, RANK_HIGH ,NO_STACK_DIMM});
213wildcard state dual_channel__1_fbdimm__dimm_size_2g__rank_low ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_2G, RANK_LOW ,NO_STACK_DIMM});
214wildcard state dual_channel__1_fbdimm__dimm_size_2g__rank_high ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_2G, RANK_HIGH ,NO_STACK_DIMM});
215wildcard state dual_channel__2_fbdimms__dimm_size_512__rank_low ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_512, RANK_LOW ,NO_STACK_DIMM});
216wildcard state dual_channel__2_fbdimms__dimm_size_512__rank_high ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_512, RANK_HIGH,NO_STACK_DIMM});
217wildcard state dual_channel__2_fbdimms__dimm_size_1g__rank_low ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_1G, RANK_LOW ,NO_STACK_DIMM});
218wildcard state dual_channel__2_fbdimms__dimm_size_1g__rank_high ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_1G, RANK_HIGH ,NO_STACK_DIMM});
219wildcard state dual_channel__2_fbdimms__dimm_size_2g__rank_low ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_2G, RANK_LOW ,NO_STACK_DIMM});
220wildcard state dual_channel__2_fbdimms__dimm_size_2g__rank_high ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_2G, RANK_HIGH ,NO_STACK_DIMM});
221wildcard state dual_channel__4_fbdimms__dimm_size_512__rank_low ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_512, RANK_LOW ,NO_STACK_DIMM});
222wildcard state dual_channel__4_fbdimms__dimm_size_512__rank_high ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_512, RANK_HIGH,NO_STACK_DIMM});
223wildcard state dual_channel__4_fbdimms__dimm_size_1g__rank_low ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_1G, RANK_LOW ,NO_STACK_DIMM});
224wildcard state dual_channel__4_fbdimms__dimm_size_1g__rank_high ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_1G, RANK_HIGH ,NO_STACK_DIMM});
225wildcard state dual_channel__4_fbdimms__dimm_size_2g__rank_low ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_2G, RANK_LOW ,NO_STACK_DIMM});
226wildcard state dual_channel__4_fbdimms__dimm_size_2g__rank_high ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_2G, RANK_HIGH ,NO_STACK_DIMM});
227
228//2 RANKS
229wildcard state dual_channel__1_fbdimm__dimm_size_512__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_512, RANK_LOW ,STACK_DIMM});
230wildcard state dual_channel__1_fbdimm__dimm_size_512__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_512, RANK_HIGH ,STACK_DIMM});
231wildcard state dual_channel__1_fbdimm__dimm_size_1g__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_1G, RANK_LOW ,STACK_DIMM});
232wildcard state dual_channel__1_fbdimm__dimm_size_1g__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_1G, RANK_HIGH ,STACK_DIMM});
233wildcard state dual_channel__1_fbdimm__dimm_size_2g__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_2G, RANK_LOW ,STACK_DIMM});
234wildcard state dual_channel__1_fbdimm__dimm_size_2g__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_1, DIMM_SIZE_2G, RANK_HIGH ,STACK_DIMM});
235wildcard state dual_channel__2_fbdimms__dimm_size_512__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_512, RANK_LOW ,STACK_DIMM});
236wildcard state dual_channel__2_fbdimms__dimm_size_512__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_512, RANK_HIGH,STACK_DIMM});
237wildcard state dual_channel__2_fbdimms__dimm_size_1g__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_1G, RANK_LOW ,STACK_DIMM});
238wildcard state dual_channel__2_fbdimms__dimm_size_1g__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_1G, RANK_HIGH ,STACK_DIMM});
239wildcard state dual_channel__2_fbdimms__dimm_size_2g__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_2G, RANK_LOW ,STACK_DIMM});
240wildcard state dual_channel__2_fbdimms__dimm_size_2g__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_2, DIMM_SIZE_2G, RANK_HIGH ,STACK_DIMM});
241wildcard state dual_channel__4_fbdimms__dimm_size_512__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_512, RANK_LOW ,STACK_DIMM});
242wildcard state dual_channel__4_fbdimms__dimm_size_512__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_512, RANK_HIGH,STACK_DIMM});
243wildcard state dual_channel__4_fbdimms__dimm_size_1g__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_1G, RANK_LOW ,STACK_DIMM});
244wildcard state dual_channel__4_fbdimms__dimm_size_1g__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_1G, RANK_HIGH ,STACK_DIMM});
245wildcard state dual_channel__4_fbdimms__dimm_size_2g__rank_low__stack_dimm ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_2G, RANK_LOW ,STACK_DIMM});
246wildcard state dual_channel__4_fbdimms__dimm_size_2g__rank_high_stack_dimm ({ DUAL_CHANNEL, FBDIMM_4, DIMM_SIZE_2G, RANK_HIGH ,STACK_DIMM});
247
248
249}
250
251//L2 cache states
252 sample l2_ctl_reg (fc_modes_cov_if.l2_ctl_reg[1:0]) {
253
254 wildcard state L2_SET_ASSOCIATIVE ({2'b00});
255 wildcard state L2_DIRECT_MAP ({2'b10});
256 wildcard state L2_OFF ({2'b01});
257
258 }
259
260
261 sample l2_cache_scrub_en (fc_modes_cov_if.l2_ctl_reg[2]) {
262 wildcard state L2_SCRUB ({1'b1});
263 }
264
265
266 cross_num_print_missing = (1 << 32) - 1;
267
268//Create a cross product so that we know system clocks and ratios
269 cross N2_modes_cross (system_clock_freq, cmp_dr_ratio, ssi_clk_ratio, pcie_ref_clock, index_hashing, memory_config, l2_ctl_reg, RANDOM_REDUNDANCY_VALUES) {
270 //cross_num_print_missing = (1 << 32) - 1;
271 cov_weight = 0;
272 }
273
274
275///////////////////////////////////////////////////////////////
276// 1 Low Rank 1G * vendor * Freq * L2_SET_ASSOCIATIVE
277// 2 Rank 1G * vendor * Freq * L2_SET_ASSOCIATIVE
278// One or Two Freq * Memory configs * L2_SET
279// L2_DIRECT * Freq
280// L2_OFF * Freq
281///////////////////////////////////////////////////////////////
282
283///////////////////////////////////////////////////////////////
284//Partial mode combinations
285//Core 0 w/ 2 Banks
286//Core 0 w/ 4 Banks
287//Core 1 w/ 2 Banks
288//Core 1 w/ 4 Banks
289//Core 1 w/ 8 Banks
290//Cores 1,2,5,7 w/ 4 Banks
291//
292//Now within each of these I randomize on the bank combinations. There
293//are 4 2 Bank combinations 01, 23, 45, 67 and 6 4 Bank combinations 0123,
294//0145, 0167, 2345, 2367, 4567.
295///////////////////////////////////////////////////////////////
296 sample banks_2 ({fc_modes_cov_if.l2t_pm, fc_modes_cov_if.l2t_ba01, fc_modes_cov_if.l2t_ba23, fc_modes_cov_if.l2t_ba45, fc_modes_cov_if.l2t_ba67}) {
297
298 wildcard state bank_01 ({5'b11000});
299 wildcard state bank_23 ({5'b10100});
300 wildcard state bank_45 ({5'b10010});
301 wildcard state bank_67 ({5'b10001});
302 }
303
304 sample banks_4 ({fc_modes_cov_if.l2t_pm, fc_modes_cov_if.l2t_ba01, fc_modes_cov_if.l2t_ba23, fc_modes_cov_if.l2t_ba45, fc_modes_cov_if.l2t_ba67}) {
305
306 wildcard state bank_0123 ({5'b11100});
307 wildcard state bank_0145 ({5'b11010});
308 wildcard state bank_0167 ({5'b11001});
309 wildcard state bank_2345 ({5'b10110});
310 wildcard state bank_2367 ({5'b10101});
311 wildcard state bank_4567 ({5'b10011});
312 }
313
314 sample banks_8 ({fc_modes_cov_if.l2t_pm, fc_modes_cov_if.l2t_ba01, fc_modes_cov_if.l2t_ba23, fc_modes_cov_if.l2t_ba45, fc_modes_cov_if.l2t_ba67}) {
315
316 wildcard state bank_01234567 ({5'b01111});
317 }
318
319
320 sample core0 ({fc_modes_cov_if.spc0_core_available, fc_modes_cov_if.spc1_core_available,
321 fc_modes_cov_if.spc2_core_available, fc_modes_cov_if.spc3_core_available,
322 fc_modes_cov_if.spc4_core_available, fc_modes_cov_if.spc5_core_available,
323 fc_modes_cov_if.spc6_core_available, fc_modes_cov_if.spc7_core_available}) {
324 wildcard state core0 ({8'b10000000});
325 }
326
327 sample core1 ({fc_modes_cov_if.spc0_core_available, fc_modes_cov_if.spc1_core_available,
328 fc_modes_cov_if.spc2_core_available, fc_modes_cov_if.spc3_core_available,
329 fc_modes_cov_if.spc4_core_available, fc_modes_cov_if.spc5_core_available,
330 fc_modes_cov_if.spc6_core_available, fc_modes_cov_if.spc7_core_available}) {
331 wildcard state core1 ({8'b01000000});
332 }
333
334 sample core1_core2_core5_core7 ({fc_modes_cov_if.spc0_core_available, fc_modes_cov_if.spc1_core_available,
335 fc_modes_cov_if.spc2_core_available, fc_modes_cov_if.spc3_core_available,
336 fc_modes_cov_if.spc4_core_available, fc_modes_cov_if.spc5_core_available,
337 fc_modes_cov_if.spc6_core_available, fc_modes_cov_if.spc7_core_available}) {
338 wildcard state core1_core2_core5_core7 ({8'b01100101});
339 }
340
341cross core0_2banks (core0, banks_2) {
342 cov_weight = 0;
343}
344cross core0_4banks (core0, banks_4) {
345 cov_weight = 0;
346}
347cross core1_2banks (core1, banks_2) {
348 cov_weight = 0;
349}
350cross core1_4banks (core1, banks_4) {
351 cov_weight = 0;
352}
353cross core1_8banks (core1, banks_8) {
354 cov_weight = 0;
355}
356
357cross core1_core2_core5_core7_banks_4 (core1_core2_core5_core7, banks_4) {
358 cov_weight = 0;
359}
360////////////////////////////////////////////////////////////////////////////////////////
361//Determine Fire modes
362////////////////////////////////////////////////////////////////////////////////////////
363sample Fire_deadlock_modes ({fc_modes_cov_if.p2d_npwr_stall_en,fc_modes_cov_if.im2crm_ilu_stall_en}) {
364 wildcard state p2d_npwr_stall_NOT_en___im2crm_ilu_stall_NOT_en ({2'b00});
365 wildcard state p2d_npwr_stall_en___im2crm_ilu_stall_NOT_en ({2'b10});
366 wildcard state p2d_npwr_stall_NOT_en___im2crm_ilu_stall_en ({2'b01});
367 wildcard state p2d_npwr_stall_en___im2crm_ilu_stall_en ({2'b11});
368}
369
370/////////////////////////////////////////////////////////////////////////////////////////
371//Power throttle En
372/////////////////////////////////////////////////////////////////////////////////////////
373sample power_throttle_en ({fc_modes_cov_if.power_throttle_en}) {
374 wildcard state power_throttle_en ({1'b1});
375}
376//////////////////////////////////////////////////////////////////////////////////////////
377//FSRRTL used or not
378//////////////////////////////////////////////////////////////////////////////////////////
379sample FSR_RTL_or_BEHAV ({fc_modes_cov_if.FSR_RTL}) {
380 wildcard state FSR_RTL ({1'b1});
381 wildcard state FSR_BEHAV ({1'b0});
382}
383
384//////////////////////////////////////////////////////////////////////////////////////////
385//SCRUB happened in one of the L2 banks
386//////////////////////////////////////////////////////////////////////////////////////////
387sample scrub_happened_in_some_bank ({fc_modes_cov_if.scrub_happened}) {
388 wildcard state scrub_happened ({1'b1});
389}
390
391
392///////END coverage group/////////////////////////////////////////////////////////////////
393}
394
395/////////////////////////////////////////////////////////////////////////////////////////
396//Determine Sun4v
397/////////////////////////////////////////////////////////////////////////////////////////
398coverage_group N2_modes_coverage_group_diag {
399
400sample_event = @(posedge fc_modes_cov_if.clk);
401
402sample sun4v ({fc_modes_cov_if.sun4v_mode}) {
403 wildcard state sun4v_mode ({1'b1});
404 wildcard state sun4u_mode ({1'b0});
405}
406}
407
408
409}
410
411class fc_cov
412{
413 // for dispmon
414 StandardDisplay dbg;
415 local string myname;
416
417 event l2t0_cpx_error_ncu1_win_evnt_trig;
418 event l2t0_cpx_error_ncu2_win_evnt_trig;
419 event l2t0_cpx_error_ncu3_win_evnt_trig;
420 event ncu_cpx_error_l2t0_win_1_evnt_trig;
421 event ncu_cpx_error_l2t0_win_2_evnt_trig;
422 event l2t0_cpx_error_1_win_evnt_trig;
423 event l2t0_cpx_error_2_win_evnt_trig;
424 event l2t0_cpx_error_3_win_evnt_trig;
425 event l2t0_cpx_error_4_win_evnt_trig;
426 event l2t0_cpx_error_5_win_evnt_trig;
427 event l2t0_cpx_error_6_win_evnt_trig;
428
429 integer counter = 0;
430 integer counter_2 = 0;
431 integer counter_3 = 0;
432 integer counter_4 = 0;
433 integer counter_5 = 0;
434 integer err_counter = 0;
435 integer err_counter2 = 0;
436 integer err_counter3 = 0;
437 integer err_counter4 = 0;
438 integer err_counter5 = 0;
439 integer err_counter6 = 0;
440 integer start_count = 0;
441
442 #include "fc_cov_intf_ver_defines.vrh"
443
444 // ----------- coverage_group ----------------
445//----------PCX -> SPC-------------------
446 coverage_group spc_ccx_intf_cov_group
447 {
448 const_sample_reference = 1; // ref. to sample vars. is constant
449 sample_event = sync (ANY, spc_ccx_intf_event);
450 #include "spc_ccx_sample.vrh"
451 } // fc_cov_group
452
453//----------L2 -> NCU-------------------
454 coverage_group l2_ncu_intf_cov_group
455 {
456 const_sample_reference = 1; // ref. to sample vars. is constant
457 sample_event = sync (ANY, l2t0_cpx_error_ncu1_win_evnt_trig, l2t0_cpx_error_ncu2_win_evnt_trig, l2t0_cpx_error_ncu3_win_evnt_trig);
458 #include "fc_err_l2_ncu_sample.vrh"
459 } // l2_ncu_intf_cov_group
460
461//----------NCU -> L2-------------------
462 coverage_group ncu_l2_intf_cov_group
463 {
464 const_sample_reference = 1; // ref. to sample vars. is constant
465 sample_event = sync (ANY, ncu_cpx_error_l2t0_win_1_evnt_trig, ncu_cpx_error_l2t0_win_2_evnt_trig );
466 #include "fc_err_ncu_l2_sample.vrh"
467 } // ncu_l2_intf_cov_group
468
469//----------L2 -> NCU-------------------
470 coverage_group l2_ncu_intf_allerr_cov_group
471 {
472 const_sample_reference = 1; // ref. to sample vars. is constant
473 sample_event = sync (ANY, l2t0_cpx_error_1_win_evnt_trig, l2t0_cpx_error_2_win_evnt_trig, l2t0_cpx_error_3_win_evnt_trig, l2t0_cpx_error_4_win_evnt_trig, l2t0_cpx_error_5_win_evnt_trig, l2t0_cpx_error_6_win_evnt_trig);
474 #include "fc_err_ncul2both_sample.vrh"
475 } // l2_ncu_intf_allerr_cov_group
476
477// *******************************************************************************************
478// MCU RAS Coverage objects
479// - 01/23/06 Changed some combinations to make them legal
480// *******************************************************************************************
481 // ----------- coverage_group ----------------Table 9----------------------
482 coverage_group fc_err_l2_mcu_ncu_multi
483 {
484 const_sample_reference = 1; // ref. to sample vars. is constant
485 sample_event = @(posedge fc_MCU_L2_NCU_ESR_intf.clk);
486 sample fc_err_l2_mcu_ncu_multi_sample ({fc_MCU_L2_NCU_ESR_intf.mcu_mec_error,
487 fc_MCU_L2_NCU_ESR_intf.mcu_dac_error,
488 fc_MCU_L2_NCU_ESR_intf.mcu_fbr_error,
489 fc_MCU_L2_NCU_ESR_intf.l2_esr[62],
490 fc_MCU_L2_NCU_ESR_intf.l2_esr[53],
491 fc_MCU_L2_NCU_ESR_intf.l2_esr[51],
492 fc_MCU_L2_NCU_ESR_intf.l2_esr[49],
493 fc_MCU_L2_NCU_ESR_intf.l2_esr[45],
494 fc_MCU_L2_NCU_ESR_intf.l2_esr[42],
495 fc_MCU_L2_NCU_ESR_intf.l2_esr[40],
496 fc_MCU_L2_NCU_ESR_intf.l2_esr[38],
497 fc_MCU_L2_NCU_ESR_intf.l2_esr[34],
498 fc_MCU_L2_NCU_ESR_intf.ncu_esr[41],
499 fc_MCU_L2_NCU_ESR_intf.ncu_esr[40],
500 fc_MCU_L2_NCU_ESR_intf.ncu_esr[38],
501 fc_MCU_L2_NCU_ESR_intf.ncu_esr[37],
502 fc_MCU_L2_NCU_ESR_intf.ncu_esr[35],
503 fc_MCU_L2_NCU_ESR_intf.ncu_esr[34],
504 fc_MCU_L2_NCU_ESR_intf.ncu_esr[32],
505 fc_MCU_L2_NCU_ESR_intf.ncu_esr[31],
506 fc_MCU_L2_NCU_ESR_intf.ncu_esr[27],
507 fc_MCU_L2_NCU_ESR_intf.ncu_esr[26],
508 fc_MCU_L2_NCU_ESR_intf.ncu_esr[23],
509 fc_MCU_L2_NCU_ESR_intf.ncu_esr[10],
510 fc_MCU_L2_NCU_ESR_intf.ncu_esr[3],
511 fc_MCU_L2_NCU_ESR_intf.ncu_esr[2]
512 })
513 {
514 wildcard state fc_err_l2_mcu_ncu_multi_case_1 (26'bx1x_x1xxxxxxx_xxxxxxxxxxxxx1) ;
515 wildcard state fc_err_l2_mcu_ncu_multi_case_2 (26'bx1x_x1xxxxxxx_xxxxxxxxx1xxx1) ;
516 wildcard state fc_err_l2_mcu_ncu_multi_case_3 (26'bx1x_x1xxxxxxx_xxxxxxxxxxxx1x) ;
517 wildcard state fc_err_l2_mcu_ncu_multi_case_4 (26'bx1x_x1xxxxxxx_xxxxxxxxx1xx1x) ;
518 wildcard state fc_err_l2_mcu_ncu_multi_case_5 (26'bx1x_x1xxxxxxx_xxxxxxxx11x111) ;
519 wildcard state fc_err_l2_mcu_ncu_multi_case_6 (26'bx1x_11xxxxxxx_xxxxxxxx11x111) ;
520 wildcard state fc_err_l2_mcu_ncu_multi_case_7 (26'b11x_11xxxxxxx_1x1x1x1xxxxx11) ;
521 wildcard state fc_err_l2_mcu_ncu_multi_case_8 (26'bx1x_x1xxxxxxx_xxxxxxx1x1xx11) ;
522 wildcard state fc_err_l2_mcu_ncu_multi_case_9 (26'b111_11xxxxxxx_x1x1x111x1xx11) ;
523 wildcard state fc_err_l2_mcu_ncu_multi_case_10 (26'bx1x_xx1xxxxxx_xxxxxxxxxxxxxx) ;
524 wildcard state fc_err_l2_mcu_ncu_multi_case_11 (26'bx1x_xxx1xxxxx_xxxxxxxxxxxx11) ;
525 wildcard state fc_err_l2_mcu_ncu_multi_case_12 (26'bx1x_xxx1xxxxx_xxxxxx1x11x111) ;
526 wildcard state fc_err_l2_mcu_ncu_multi_case_13 (26'bx1x_xxxxxx1xx_xxxxxxxxxxxx11) ;
527 wildcard state fc_err_l2_mcu_ncu_multi_case_14 (26'bx1x_xxxxxx1xx_xxxxxx1x11x111) ;
528 wildcard state fc_err_l2_mcu_ncu_multi_case_15 (26'bx1x_xxx1xxxxx_xxxxxx1x11x111) ;
529 wildcard state fc_err_l2_mcu_ncu_multi_case_16 (26'bx11_xxxxxxxxx_xxxxxxxxxxxx11) ;
530 wildcard state fc_err_l2_mcu_ncu_multi_case_17 (26'bx11_xxxxxxxxx_xxxxxxxx11x111) ;
531 wildcard state fc_err_l2_mcu_ncu_multi_case_18 (26'b111_11xxxxxxx_xxxxxxxx11x111) ;
532 wildcard state fc_err_l2_mcu_ncu_multi_case_19 (26'b111_11xxxxxxx_xxxxxxxx111111) ;
533 wildcard state fc_err_l2_mcu_ncu_multi_case_20 (26'b11x_xxxxxxxxx_xxxxxxxx111111) ;
534 wildcard state fc_err_l2_mcu_ncu_multi_case_21 (26'b11x_1xxxxxxx1_xxxxxxxx111111) ;
535 }
536 }
537
538// *******************************************************************************************
539
540
541 task new(string myname, StandardDisplay dbg);
542 task set_spc_pcx_cov_point (string myname, fc_cov_spc_pcx_port spp, reg [5:0] spc_idx);
543 task set_cpx_spc_cov_point (string myname, fc_cov_cpx_spc_port csp, reg [5:0] spc_id);
544 task set_int_cnt_cov_point (string myname);
545 task set_cov_cond_bits ();
546
547
548} //class fc_cov
549
550
551/////////////////////////////////////////////////////////////////
552// Class creation
553/////////////////////////////////////////////////////////////////
554task fc_cov::new(string myname, StandardDisplay dbg)
555{
556
557 // for dispmon
558
559 this.myname = myname;
560 this.dbg = dbg;
561
562 spc_ccx_intf_cov_group = new();
563 l2_ncu_intf_cov_group = new();
564 ncu_l2_intf_cov_group = new();
565 l2_ncu_intf_allerr_cov_group = new();
566 fc_err_l2_mcu_ncu_multi = new();
567
568 fork
569.for($b=0; $b<=7; $b++){
570 set_spc_pcx_cov_point ({myname, ".spc${b}_pcx"}, fc_cov_spc${b}_pcx_bind, $b);
571 set_cpx_spc_cov_point ({myname, ".cpx_spc${b}"}, fc_cov_cpx_spc${b}_bind, $b);
572.}
573 join none
574
575} // fc_cov::new()
576
577
578
579
580
581task fc_cov::set_spc_pcx_cov_point (string myname, fc_cov_spc_pcx_port spp, reg [5:0] spc_idx)
582{
583reg [8:0] spc_pcx_req0 = 0;
584reg [8:0] spc_pcx_req1 = 0;
585reg [5:0] cpu_thr_id;
586
587reg [39:0] spc_pcx_add;
588reg [4:0] spc_pcx_type;
589reg [3:0] spc_pcx_thr;
590reg [7:0] spc_pcx_size;
591
592
593 myname = {myname, ".set_spc_pcx_cov_point"};
594 while (1) {
595 @ (posedge spp.\$clk);
596 spc_pcx_req1 = spc_pcx_req0;
597 spc_pcx_req0 = spp.\$req;
598
599 //=============================
600
601
602 if (spc_pcx_req1[8]) {
603 reg [39:0] tmp_add;
604 spc_pcx_add = spp.\$data[103:64];
605 spc_pcx_type = spp.\$data[128:124];
606 spc_pcx_thr = spp.\$data[119:117];
607 spc_pcx_size = spp.\$data[111:104];
608 tmp_add = spc_pcx_add & 40'hff03ffffff;
609 if ((tmp_add == 40'h9001cc0000) && (spc_pcx_type == 5'b00001)) {
610 cpu_thr_id = (spc_idx*8)+spc_pcx_thr;
611 spc_pcx_int_cpu_thr_reg[cpu_thr_id] = 1;
612 int_des_cpu_thr_reg [cpu_thr_id] = 1;
613 int_des_clk_cnt_en = 1;
614 dbg.dispmon(myname, MON_INFO, psprintf("SPC%0d->PCX(IO): spc_pcx_int_cpu_thr_reg %0h int_des_cpu_thr_reg %0h int_des_clk_cnt %0d, cpu_thr_id %b",
615 spc_idx, spc_pcx_int_cpu_thr_reg, int_des_cpu_thr_reg, int_des_clk_cnt , cpu_thr_id));
616
617 trigger (spc_ccx_intf_event );
618 } else {
619 spc_pcx_int_cpu_thr_reg=0;
620 }
621 dbg.dispmon(myname, MON_INFO, psprintf("SPC%0D->PCX(IO) :: pkt %0h", spc_idx, spp.\$data)) ;
622 dbg.dispmon(myname, MON_INFO, psprintf("SPC%0D->PCX(IO) :: add %0h type %h cpu_thr_id %h size %h spc_idx %h", spc_idx, spc_pcx_add,spc_pcx_type,cpu_thr_id, spc_pcx_size, spc_idx));
623
624 if (spc_idx !== spp.\$data[122:120]){
625 dbg.dispmon(myname, MON_ERR, psprintf(" SPC%0D->PCX didn't send right cpu_thr_id %0d", spc_idx , spp.\$data[122:120]));
626 }
627 }
628 }
629} // task set_spc_pcx_cov_point
630
631
632
633task fc_cov::set_cpx_spc_cov_point (string myname, fc_cov_cpx_spc_port csp, reg [5:0] spc_idx )
634{
635reg cpx_io_grant0;
636reg cpx_io_grant1;
637reg [2:0] cpu_id;
638reg [2:0] spc_cpx_thr;
639reg [5:0] cpu_thr_id;
640
641 reg [3:0] spc_cpx_type;
642 reg [7:0] spc_cpx_cpu;
643 reg [1:0] spc_cpx_err;
644
645 myname = {myname, ".set_cpx_spc_cov_point"};
646
647 //dbg.dispmon(myname, MON_DEBUG, psprintf("Task is on"));
648 while (1) {
649 @(posedge csp.\$clk);
650 cpx_io_grant1 = cpx_io_grant0;
651 cpx_io_grant0 = csp.\$grant;
652
653 if (cpx_io_grant1){
654 spc_cpx_type = csp.\$data[144:141];
655 spc_cpx_err = csp.\$data[139:138];
656 spc_cpx_thr = csp.\$data[136:134];
657
658 dbg.dispmon(myname, MON_INFO, psprintf("CPX(IO)->SPC%0d : pkt %0h",spc_idx, csp.\$data)) ;
659 dbg.dispmon(myname, MON_INFO, psprintf("CPX(IO)->SPC%0d : type %h %h err %0h, thr_id %0h ,", spc_idx, spc_cpx_type, spc_cpx_err, spc_cpx_thr));
660
661 if(spc_cpx_type === 4'b0111){
662 cpu_thr_id = (spc_idx*8)+spc_cpx_thr;
663 cpx_spc_int_cpu_thr_reg[cpu_thr_id] = 1;
664 spc_cpx_int_vec = csp.\$data[5:0];
665 dbg.dispmon(myname, MON_INFO, psprintf("CPX(IO)->SCP%0d: cpu_thr_id %h, cpx_spc_int_cpu_thr_reg %0h, spc_cpx_int_vec %0h", spc_idx, cpu_thr_id, cpx_spc_int_cpu_thr_reg, spc_cpx_int_vec)) ;
666 trigger (spc_ccx_intf_event );
667 } else {
668 cpx_spc_int_cpu_thr_reg = 0;
669 spc_cpx_int_vec = 6'hxx;
670 }
671 }
672 }
673
674}
675
676
677task fc_cov::set_int_cnt_cov_point (string myname){
678 myname = {myname, ".set_int_cnt_cov_point"};
679 pcx_int_clk_cnt = 0;
680 while (1){
681 @(posedge fc_cov_ccx.clk);
682 if (int_des_clk_cnt_en){
683 if (int_des_clk_cnt <804){
684 int_des_clk_cnt++;
685 } else {
686 int_des_clk_cnt = 0;
687 int_des_clk_cnt_en=0;
688 int_des_cpu_thr_reg = 0;
689 }
690 } else {
691 int_des_clk_cnt = 0;
692 }
693 }
694}
695
696task fc_cov:: set_cov_cond_bits ()
697{
698
699fork
700 {
701 while (1)
702 {
703 @(posedge CLOCK);
704 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00 && ( start_count == 0) )
705 {
706 start_count = 1 ;
707 counter = 0 ;
708 }
709 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00 && ( start_count == 1) )
710 {
711 if (counter === 'd10)
712 {
713 trigger (l2t0_cpx_error_ncu1_win_evnt_trig );
714 start_count = 0 ;
715 counter = 0 ;
716 }
717 }
718 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && (fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00) && ( start_count == 1) && (counter <=10) )
719 {
720 counter = counter + 1 ;
721 }
722 else if (( start_count == 1) && (counter > 10))
723 {
724 start_count = 0 ;
725 counter = 0 ;
726 }
727 }
728 }
729join none
730
731fork
732 {
733 while (1)
734 {
735 @(posedge CLOCK);
736 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00 && ( start_count == 0) )
737 {
738 start_count = 1 ;
739 counter_2 = 0 ;
740 }
741 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00 && ( start_count == 1) )
742 {
743 if (counter_2 === 'd10)
744 {
745 trigger (l2t0_cpx_error_ncu2_win_evnt_trig );
746 start_count = 0 ;
747 counter_2 = 0 ;
748 }
749 }
750 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && (fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00) && ( start_count == 1) && (counter_2 <=10) )
751 {
752 counter_2 = counter_2 + 1 ;
753 }
754 else if (( start_count == 1) && (counter_2 > 10))
755 {
756 start_count = 0 ;
757 counter_2 = 0 ;
758 }
759 }
760 }
761join none
762
763fork
764 {
765 while (1)
766 {
767 @(posedge CLOCK);
768 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00 && ( start_count == 0) )
769 {
770 start_count = 1 ;
771 counter_3 = 0 ;
772 }
773 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00 && ( start_count == 1) )
774 {
775 if (counter_3 === 'd10)
776 {
777 trigger (l2t0_cpx_error_ncu3_win_evnt_trig );
778 start_count = 0 ;
779 counter_3 = 0 ;
780 }
781 }
782 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && (fc_cov_ncu.ncu_cpx_data[139:138] === 2'b00) && ( start_count == 1) && (counter_3 <=10) )
783 {
784 counter_3 = counter_3 + 1 ;
785 }
786 else if (( start_count == 1) && (counter_3 > 10))
787 {
788 start_count = 0 ;
789 counter_3 = 0 ;
790 }
791 }
792 }
793join none
794
795
796fork
797 {
798 while (1)
799 {
800 @(posedge CLOCK);
801 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 0) )
802 {
803 start_count = 1 ;
804 counter_4 = 0 ;
805 }
806 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 1) )
807 {
808 if (counter_4 === 'd10)
809 {
810 trigger (ncu_cpx_error_l2t0_win_1_evnt_trig );
811 start_count = 0 ;
812 counter_4 = 0 ;
813 }
814 }
815 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && (fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01) && ( start_count == 1) && (counter_4 <=10) )
816 {
817 counter_4 = counter_4 + 1 ;
818 }
819 else if (( start_count == 1) && (counter_4 > 10))
820 {
821 start_count = 0 ;
822 counter_4 = 0 ;
823 }
824 }
825 }
826join none
827
828/*
829fork
830 {
831 while (1)
832 {
833 @(posedge CLOCK);
834 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 0) )
835 {
836 start_count = 1 ;
837 counter_4 = 0 ;
838 }
839 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && (fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 1) )
840 {
841 if (counter_4 === 'd10)
842 {
843 trigger (ncu_cpx_error_l2t0_win_1_evnt_trig );
844 start_count = 0 ;
845 counter_4 = 0 ;
846 }
847 }
848 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && !(fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01) && ( start_count == 1) && (counter_4 <=10) )
849 {
850 counter_4 = counter_4 + 1 ;
851 }
852 else if (( start_count == 1) && (counter_4 > 10))
853 {
854 start_count = 0 ;
855 counter_4 = 0 ;
856 }
857 }
858 }
859join none
860*/
861
862fork
863 {
864 while (1)
865 {
866 @(posedge CLOCK);
867 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10 && ( start_count == 0) )
868 {
869 start_count = 1 ;
870 counter_5 = 0 ;
871 }
872 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && (fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10) && ( start_count == 1) )
873 {
874 if (counter_5 === 'd10)
875 {
876 trigger (ncu_cpx_error_l2t0_win_2_evnt_trig );
877 start_count = 0 ;
878 counter_5 = 0 ;
879 }
880 }
881 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b00) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && !(fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10) && ( start_count == 1) && (counter_5 <=10) )
882 {
883 counter_5 = counter_5 + 1 ;
884 }
885 else if (( start_count == 1) && (counter_5 > 10))
886 {
887 start_count = 0 ;
888 counter_5 = 0 ;
889 }
890 }
891 }
892join none
893
894fork
895 {
896 while (1)
897 {
898 @(posedge CLOCK);
899 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 0) )
900 {
901 start_count = 1 ;
902 err_counter = 0 ;
903 }
904 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 1) )
905 {
906 if (err_counter === 'd10)
907 {
908 trigger (l2t0_cpx_error_1_win_evnt_trig );
909 start_count = 0 ;
910 err_counter = 0 ;
911 }
912 }
913 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && !(fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01) && ( start_count == 1) && (err_counter <=10) )
914 {
915 err_counter = err_counter + 1 ;
916 }
917 else if (( start_count == 1) && (err_counter > 10))
918 {
919 start_count = 0 ;
920 err_counter = 0 ;
921 }
922 }
923 }
924join none
925
926fork
927 {
928 while (1)
929 {
930 @(posedge CLOCK);
931 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10 && ( start_count == 0) )
932 {
933 start_count = 1 ;
934 err_counter2 = 0 ;
935 }
936 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10 && ( start_count == 1) )
937 {
938 if (err_counter2 === 'd10)
939 {
940 trigger (l2t0_cpx_error_2_win_evnt_trig );
941 start_count = 0 ;
942 err_counter2 = 0 ;
943 }
944 }
945 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b01) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && !(fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10) && ( start_count == 1) && (err_counter2 <=10) )
946 {
947 err_counter2 = err_counter2 + 1 ;
948 }
949 else if (( start_count == 1) && (err_counter2 > 10))
950 {
951 start_count = 0 ;
952 err_counter2 = 0 ;
953 }
954 }
955 }
956join none
957
958fork
959 {
960 while (1)
961 {
962 @(posedge CLOCK);
963 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 0) )
964 {
965 start_count = 1 ;
966 err_counter3 = 0 ;
967 }
968 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 1) )
969 {
970 if (err_counter3 === 'd10)
971 {
972 trigger (l2t0_cpx_error_3_win_evnt_trig );
973 start_count = 0 ;
974 err_counter3 = 0 ;
975 }
976 }
977 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && !(fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01) && ( start_count == 1) && (err_counter3 <=10) )
978 {
979 err_counter3 = err_counter3 + 1 ;
980 }
981 else if (( start_count == 1) && (err_counter3 > 10))
982 {
983 start_count = 0 ;
984 err_counter3 = 0 ;
985 }
986 }
987 }
988join none
989
990fork
991 {
992 while (1)
993 {
994 @(posedge CLOCK);
995 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10 && ( start_count == 0) )
996 {
997 start_count = 1 ;
998 err_counter4 = 0 ;
999 }
1000 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10 && ( start_count == 1) )
1001 {
1002 if (err_counter4 === 'd10)
1003 {
1004 trigger (l2t0_cpx_error_4_win_evnt_trig );
1005 start_count = 0 ;
1006 err_counter4 = 0 ;
1007 }
1008 }
1009 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b10) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && !(fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10) && ( start_count == 1) && (err_counter4 <=10) )
1010 {
1011 err_counter4 = err_counter4 + 1 ;
1012 }
1013 else if (( start_count == 1) && (err_counter4 > 10))
1014 {
1015 start_count = 0 ;
1016 err_counter4 = 0 ;
1017 }
1018 }
1019 }
1020join none
1021
1022fork
1023 {
1024 while (1)
1025 {
1026 @(posedge CLOCK);
1027 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 0) )
1028 {
1029 start_count = 1 ;
1030 err_counter5 = 0 ;
1031 }
1032 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01 && ( start_count == 1) )
1033 {
1034 if (err_counter5 === 'd10)
1035 {
1036 trigger (l2t0_cpx_error_5_win_evnt_trig );
1037 start_count = 0 ;
1038 err_counter5 = 0 ;
1039 }
1040 }
1041 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && !(fc_cov_ncu.ncu_cpx_data[139:138] === 2'b01) && ( start_count == 1) && (err_counter5 <=10) )
1042 {
1043 err_counter5 = err_counter5 + 1 ;
1044 }
1045 else if (( start_count == 1) && (err_counter5 > 10))
1046 {
1047 start_count = 0 ;
1048 err_counter5 = 0 ;
1049 }
1050 }
1051 }
1052join none
1053
1054fork
1055 {
1056 while (1)
1057 {
1058 @(posedge CLOCK);
1059 if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10 && ( start_count == 0) )
1060 {
1061 start_count = 1 ;
1062 err_counter6 = 0 ;
1063 }
1064 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11 && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10 && ( start_count == 1) )
1065 {
1066 if (err_counter6 === 'd10)
1067 {
1068 trigger (l2t0_cpx_error_6_win_evnt_trig );
1069 start_count = 0 ;
1070 err_counter6 = 0 ;
1071 }
1072 }
1073 else if ( fc_cov_l2.l2t0_cpx_data[145] === 1'b1 && fc_cov_l2.l2t0_cpx_data[144:141] === 4'b0000 && !(fc_cov_l2.l2t0_cpx_data[139:138] === 2'b11) && fc_cov_ncu.ncu_cpx_data[145] === 1 && fc_cov_ncu.ncu_cpx_data[144:141] === 4'b1000 && !(fc_cov_ncu.ncu_cpx_data[139:138] === 2'b10) && ( start_count == 1) && (err_counter6 <=10) )
1074 {
1075 err_counter6 = err_counter6 + 1 ;
1076 }
1077 else if (( start_count == 1) && (err_counter6 > 10))
1078 {
1079 start_count = 0 ;
1080 err_counter6 = 0 ;
1081 }
1082 }
1083 }
1084join none
1085
1086}
Full OpenSPARC design & verification tarball including full HDL.