Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / ilu_peu / ilu_dmu_ingress_data_sample.vrh

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ilu_dmu_ingress_data_sample.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
sample dmu_ilu_coverage_ifc.y2k_buf_addr
{

state ILU_DMU_ADR_00  ( 8'b00000000 ); 
state ILU_DMU_ADR_01  ( 8'b00000001 ); 
state ILU_DMU_ADR_02  ( 8'b00000010 ); 
state ILU_DMU_ADR_03  ( 8'b00000011 ); 
state ILU_DMU_ADR_04  ( 8'b00000100 ); 
state ILU_DMU_ADR_05  ( 8'b00000101 ); 
state ILU_DMU_ADR_06  ( 8'b00000110 ); 
state ILU_DMU_ADR_07  ( 8'b00000111 ); 
state ILU_DMU_ADR_08  ( 8'b00001000 ); 
state ILU_DMU_ADR_09  ( 8'b00001001 ); 
state ILU_DMU_ADR_10  ( 8'b00001010 ); 
state ILU_DMU_ADR_11  ( 8'b00001011 ); 
state ILU_DMU_ADR_12  ( 8'b00001100 ); 
state ILU_DMU_ADR_13  ( 8'b00001101 ); 
state ILU_DMU_ADR_14  ( 8'b00001110 ); 
state ILU_DMU_ADR_15  ( 8'b00001111 ); 
state ILU_DMU_ADR_16  ( 8'b00010000 ); 
state ILU_DMU_ADR_17  ( 8'b00010001 ); 
state ILU_DMU_ADR_18  ( 8'b00010010 ); 
state ILU_DMU_ADR_19  ( 8'b00010011 ); 
state ILU_DMU_ADR_20  ( 8'b00010100 ); 
state ILU_DMU_ADR_21  ( 8'b00010101 ); 
state ILU_DMU_ADR_22  ( 8'b00010110 ); 
state ILU_DMU_ADR_23  ( 8'b00010111 ); 
state ILU_DMU_ADR_24  ( 8'b00011000 ); 
state ILU_DMU_ADR_25  ( 8'b00011001 ); 
state ILU_DMU_ADR_26  ( 8'b00011010 ); 
state ILU_DMU_ADR_27  ( 8'b00011011 ); 
state ILU_DMU_ADR_28  ( 8'b00011100 ); 
state ILU_DMU_ADR_29  ( 8'b00011101 ); 
state ILU_DMU_ADR_30  ( 8'b00011110 ); 
state ILU_DMU_ADR_31  ( 8'b00011111 ); 
state ILU_DMU_ADR_32  ( 8'b00100000 ); 
state ILU_DMU_ADR_33  ( 8'b00100001 ); 
state ILU_DMU_ADR_34  ( 8'b00100010 ); 
state ILU_DMU_ADR_35  ( 8'b00100011 ); 
state ILU_DMU_ADR_36  ( 8'b00100100 ); 
state ILU_DMU_ADR_37  ( 8'b00100101 ); 
state ILU_DMU_ADR_38  ( 8'b00100110 ); 
state ILU_DMU_ADR_39  ( 8'b00100111 ); 
state ILU_DMU_ADR_40  ( 8'b00101000 ); 
state ILU_DMU_ADR_41  ( 8'b00101001 ); 
state ILU_DMU_ADR_42  ( 8'b00101010 ); 
state ILU_DMU_ADR_43  ( 8'b00101011 ); 
state ILU_DMU_ADR_44  ( 8'b00101100 ); 
state ILU_DMU_ADR_45  ( 8'b00101101 ); 
state ILU_DMU_ADR_46  ( 8'b00101110 ); 
state ILU_DMU_ADR_47  ( 8'b00101111 ); 
state ILU_DMU_ADR_48  ( 8'b00110000 ); 
state ILU_DMU_ADR_49  ( 8'b00110001 ); 
state ILU_DMU_ADR_50  ( 8'b00110010 ); 
state ILU_DMU_ADR_51  ( 8'b00110011 ); 
state ILU_DMU_ADR_52  ( 8'b00110100 ); 
state ILU_DMU_ADR_53  ( 8'b00110101 ); 
state ILU_DMU_ADR_54  ( 8'b00110110 ); 
state ILU_DMU_ADR_55  ( 8'b00110111 ); 
state ILU_DMU_ADR_56  ( 8'b00111000 ); 
state ILU_DMU_ADR_57  ( 8'b00111001 ); 
state ILU_DMU_ADR_58  ( 8'b00111010 ); 
state ILU_DMU_ADR_59  ( 8'b00111011 ); 
state ILU_DMU_ADR_60  ( 8'b00111100 ); 
state ILU_DMU_ADR_61  ( 8'b00111101 ); 
state ILU_DMU_ADR_62  ( 8'b00111110 ); 
state ILU_DMU_ADR_63  ( 8'b00111111 ); 
state ILU_DMU_ADR_64  ( 8'b01000000 ); 
state ILU_DMU_ADR_65  ( 8'b01000001 ); 
state ILU_DMU_ADR_66  ( 8'b01000010 ); 
state ILU_DMU_ADR_67  ( 8'b01000011 ); 
state ILU_DMU_ADR_68  ( 8'b01000100 ); 
state ILU_DMU_ADR_69  ( 8'b01000101 ); 
state ILU_DMU_ADR_70  ( 8'b01000110 ); 
state ILU_DMU_ADR_71  ( 8'b01000111 ); 
state ILU_DMU_ADR_72  ( 8'b01001000 ); 
state ILU_DMU_ADR_73  ( 8'b01001001 ); 
state ILU_DMU_ADR_74  ( 8'b01001010 ); 
state ILU_DMU_ADR_75  ( 8'b01001011 ); 
state ILU_DMU_ADR_76  ( 8'b01001100 ); 
state ILU_DMU_ADR_77  ( 8'b01001101 ); 
state ILU_DMU_ADR_78  ( 8'b01001110 ); 
state ILU_DMU_ADR_79  ( 8'b01001111 ); 
state ILU_DMU_ADR_80  ( 8'b01010000 ); 
state ILU_DMU_ADR_81  ( 8'b01010001 ); 
state ILU_DMU_ADR_82  ( 8'b01010010 ); 
state ILU_DMU_ADR_83  ( 8'b01010011 ); 
state ILU_DMU_ADR_84  ( 8'b01010100 ); 
state ILU_DMU_ADR_85  ( 8'b01010101 ); 
state ILU_DMU_ADR_86  ( 8'b01010110 ); 
state ILU_DMU_ADR_87  ( 8'b01010111 ); 
state ILU_DMU_ADR_88  ( 8'b01011000 ); 
state ILU_DMU_ADR_89  ( 8'b01011001 ); 
state ILU_DMU_ADR_90  ( 8'b01011010 ); 
state ILU_DMU_ADR_91  ( 8'b01011011 ); 
state ILU_DMU_ADR_92  ( 8'b01011100 ); 
state ILU_DMU_ADR_93  ( 8'b01011101 ); 
state ILU_DMU_ADR_94  ( 8'b01011110 ); 
state ILU_DMU_ADR_95  ( 8'b01011111 ); 
state ILU_DMU_ADR_96  ( 8'b01100000 ); 
state ILU_DMU_ADR_97  ( 8'b01100001 ); 
state ILU_DMU_ADR_98  ( 8'b01100010 ); 
state ILU_DMU_ADR_99  ( 8'b01100011 ); 
state ILU_DMU_ADR_100 ( 8'b01100100 ); 
state ILU_DMU_ADR_101 ( 8'b01100101 ); 
state ILU_DMU_ADR_102 ( 8'b01100110 ); 
state ILU_DMU_ADR_103 ( 8'b01100111 ); 
state ILU_DMU_ADR_104 ( 8'b01101000 ); 
state ILU_DMU_ADR_105 ( 8'b01101001 ); 
state ILU_DMU_ADR_106 ( 8'b01101010 ); 
state ILU_DMU_ADR_107 ( 8'b01101011 ); 
state ILU_DMU_ADR_108 ( 8'b01101100 ); 
state ILU_DMU_ADR_109 ( 8'b01101101 ); 
state ILU_DMU_ADR_110 ( 8'b01101110 ); 
state ILU_DMU_ADR_111 ( 8'b01101111 ); 
state ILU_DMU_ADR_112 ( 8'b01110000 ); 
state ILU_DMU_ADR_113 ( 8'b01110001 ); 
state ILU_DMU_ADR_114 ( 8'b01110010 ); 
state ILU_DMU_ADR_115 ( 8'b01110011 ); 
state ILU_DMU_ADR_116 ( 8'b01110100 ); 
state ILU_DMU_ADR_117 ( 8'b01110101 ); 
state ILU_DMU_ADR_118 ( 8'b01110110 ); 
state ILU_DMU_ADR_119 ( 8'b01110111 ); 
state ILU_DMU_ADR_120 ( 8'b01111000 ); 
state ILU_DMU_ADR_121 ( 8'b01111001 ); 
state ILU_DMU_ADR_122 ( 8'b01111010 ); 
state ILU_DMU_ADR_123 ( 8'b01111011 ); 
state ILU_DMU_ADR_124 ( 8'b01111100 ); 
state ILU_DMU_ADR_125 ( 8'b01111101 ); 
state ILU_DMU_ADR_126 ( 8'b01111110 ); 
state ILU_DMU_ADR_127 ( 8'b01111111 ); 
state ILU_DMU_ADR_128 ( 8'b10000000 ); 
state ILU_DMU_ADR_129 ( 8'b10000001 ); 
state ILU_DMU_ADR_130 ( 8'b10000010 ); 
state ILU_DMU_ADR_131 ( 8'b10000011 ); 
state ILU_DMU_ADR_132 ( 8'b10000100 ); 
state ILU_DMU_ADR_133 ( 8'b10000101 ); 
state ILU_DMU_ADR_134 ( 8'b10000110 ); 
state ILU_DMU_ADR_135 ( 8'b10000111 ); 
state ILU_DMU_ADR_136 ( 8'b10001000 ); 
state ILU_DMU_ADR_137 ( 8'b10001001 ); 
state ILU_DMU_ADR_138 ( 8'b10001010 ); 
state ILU_DMU_ADR_139 ( 8'b10001011 ); 
state ILU_DMU_ADR_140 ( 8'b10001100 ); 
state ILU_DMU_ADR_141 ( 8'b10001101 ); 
state ILU_DMU_ADR_142 ( 8'b10001110 ); 
state ILU_DMU_ADR_143 ( 8'b10001111 ); 

//
// PIOs use x80-x8f and dma completions use x0-x7f


}