Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / ilu_peu / ilu_dmu_ingress_sample.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ilu_dmu_ingress_sample.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#inc "ilu_peu_cov_inc.pal";
// ilu_dmu ingress interface

sample dmu_ilu_ihdr_F_Type (ilu_dmu_hdr_F_Type) {
           state PEC_Ingress_DMA_MRd32   ( 7'b0000000);
           state PEC_Ingress_DMA_MRd64   ( 7'b0100000);
           state PEC_Ingress_DMA_MRdLk32 ( 7'b0000001);
           state PEC_Ingress_DMA_MRdLk64 ( 7'b0100001);
           state PEC_Ingress_Unsupported ( 7'b0001001);
           state PEC_Ingress_DMA_MWr32   ( 7'b1000000);
           state PEC_Ingress_DMA_MWr64   ( 7'b1100000);
  wildcard state PEC_Ingress_Msg         ( 7'b0110xxx);
           state PEC_Ingress_PIO_Cpl     ( 7'b0001010);
           state PEC_Ingress_PIO_CplD    ( 7'b1001010);
}

sample dmu_ilu_ihdr_TC (ilu_dmu_hdr_TC) {
. &toggle( 3 );

  cov_weight = 1;
}

sample dmu_ilu_ihdr_Atr (ilu_dmu_hdr_Atr) {
. &toggle( 2 );

  cov_weight = 1;
}

sample dmu_ilu_ihdr_Len (ilu_dmu_hdr_Len) {
. &toggle( 10);
  cov_weight = 1;
}
sample dmu_ilu_ihdr_ReqID (ilu_dmu_hdr_ReqID) {
. &toggle( 16);
  cov_weight = 1;
}

sample dmu_ilu_ihdr_TLPtag (ilu_dmu_hdr_TLPTag) {
. &toggle( 8);
  cov_weight = 1;
}
sample dmu_ilu_ihdr_LastDWBE (ilu_dmu_hdr_LastDWBE) {
. &toggle(4 );
  cov_weight = 1;
}
sample dmu_ilu_ihdr_FirstDWBE (ilu_dmu_hdr_FirstDWBE) {
. &toggle(4 );
  cov_weight = 1;
}

sample dmu_ilu_ihdr_Addr (ilu_dmu_hdr_Addr) {
. &toggle(62 );
  cov_weight = 1;
}

 sample dmu_ilu_ihdr_DMA_RD_LEN (ilu_dmu_hdr_Len) {
     m_state DMA_MRd_mps128 (0:1023) if ((ilu_dmu_hdr_F_Type =?= 7'b0x0000x) && (ilu_dmu_mps==3'b000));
     m_state DMA_MRd_mps256 (0:1023) if ((ilu_dmu_hdr_F_Type =?= 7'b0x0000x) && (ilu_dmu_mps==3'b001));
     m_state DMA_MRd_mps512 (0:1023) if ((ilu_dmu_hdr_F_Type =?= 7'b0x0000x) && (ilu_dmu_mps==3'b010));
}