projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: ilu_peu_coverage.vrpal | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #include <vera_defines.vrh> | |
| 36 | #include <ListMacros.vrh> | |
| 37 | #include "plusArgMacros.vri" | |
| 38 | ||
| 39 | #inc "ilu_peu_cov_inc.pal" | |
| 40 | // #include "std_display_class.vrh" | |
| 41 | // #include "std_display_defines.vri" | |
| 42 | // # include "ilu_peu_defines.vrh" | |
| 43 | ||
| 44 | #include "ilu_peu_cov.if.vrh" | |
| 45 | //#include "ILU_PEU_cov_ports_binds.vrh" | |
| 46 | ||
| 47 | class ilu_peu_intf_coverage | |
| 48 | { | |
| 49 | // for dispmon | |
| 50 | // StandardDisplay dbg; | |
| 51 | // local string myname; | |
| 52 | ||
| 53 | event y2k_rcd_enq_event_trig; | |
| 54 | event y2k_rel_enq_event_trig; | |
| 55 | event y2k_rel1_enq_event_trig; | |
| 56 | event y2k_rel2_enq_event_trig; | |
| 57 | event k2y_rcd_enq_event_trig; | |
| 58 | event k2y_rel_enq_event_trig; | |
| 59 | event k2y_rel1_enq_event_trig; | |
| 60 | event k2y_rel2_enq_event_trig; | |
| 61 | event y2k_buf_addr_vld_monitor_event_trig; | |
| 62 | event k2y_buf_addr_vld_monitor_event_trig; | |
| 63 | event k2y_dou_vld_event_trig; | |
| 64 | event dmu_psr_rate_event_trig; | |
| 65 | ||
| 66 | //-----------------ILU-DMU-egress DP----------- | |
| 67 | bit y2k_buf_addr_vld_monitor = 1'b0; | |
| 68 | bit k2y_buf_addr_vld_monitor = 1'b0; | |
| 69 | reg [1:0] ilu_dmu_hdr_F; | |
| 70 | reg [4:0] ilu_dmu_hdr_Type; | |
| 71 | reg [6:0] ilu_dmu_hdr_F_Type; | |
| 72 | reg [2:0] ilu_dmu_hdr_TC; | |
| 73 | reg [1:0] ilu_dmu_hdr_Atr; | |
| 74 | reg [9:0] ilu_dmu_hdr_Len; | |
| 75 | reg [15:0] ilu_dmu_hdr_ReqID; | |
| 76 | reg [7:0] ilu_dmu_hdr_TLPTag; | |
| 77 | reg [3:0] ilu_dmu_hdr_LastDWBE; | |
| 78 | reg [3:0] ilu_dmu_hdr_FirstDWBE; | |
| 79 | reg [61:0] ilu_dmu_hdr_Addr; | |
| 80 | reg [2:0] ilu_dmu_mps; | |
| 81 | reg [4:0] pec_ingress_rel; | |
| 82 | reg [4:0] pec_ingress_rel1; | |
| 83 | reg [3:0] pec_ingress_rel2; | |
| 84 | ||
| 85 | //-----------------ILU-DMU-egress-------------- | |
| 86 | reg [1:0] dmu_ilu_hdr_F; | |
| 87 | reg [4:0] dmu_ilu_hdr_Type; | |
| 88 | reg [6:0] dmu_ilu_hdr_F_Type; | |
| 89 | reg [2:0] dmu_ilu_hdr_TC; | |
| 90 | reg [1:0] dmu_ilu_hdr_Atr; | |
| 91 | reg [7:0] dmu_ilu_hdr_Len; | |
| 92 | reg [15:0] dmu_ilu_hdr_ReqID; | |
| 93 | reg [7:0] dmu_ilu_hdr_TLPTag; | |
| 94 | reg [3:0] dmu_ilu_hdr_LastDWBE; | |
| 95 | reg [3:0] dmu_ilu_hdr_FirstDWBE; | |
| 96 | reg [63:0] dmu_ilu_hdr_Addr; | |
| 97 | reg [5:0] dmu_ilu_hdr_Dptr; | |
| 98 | reg [8:0] pec_egress_rel; | |
| 99 | reg [4:0] pec_egress_rel1; | |
| 100 | reg [3:0] pec_egress_rel2; | |
| 101 | ||
| 102 | reg [4:0] k2y_dou_dptr1; | |
| 103 | bit k2y_dou_err1; | |
| 104 | bit rx_b0sds0_var; | |
| 105 | bit rx_b0sds1_var; | |
| 106 | bit rx_b1sds0_var; | |
| 107 | bit rx_b1sds1_var; | |
| 108 | bit rx_b2sds0_var; | |
| 109 | bit rx_b2sds1_var; | |
| 110 | bit rx_b3sds0_var; | |
| 111 | bit rx_b3sds1_var; | |
| 112 | bit tx_b0sds0_var; | |
| 113 | bit tx_b0sds1_var; | |
| 114 | bit tx_b1sds0_var; | |
| 115 | bit tx_b1sds1_var; | |
| 116 | bit tx_b2sds0_var; | |
| 117 | bit tx_b2sds1_var; | |
| 118 | bit tx_b3sds0_var; | |
| 119 | bit tx_b3sds1_var; | |
| 120 | ||
| 121 | //////ILU_PEU interface ////// | |
| 122 | ||
| 123 | ||
| 124 | coverage_group ilu_dmu_ingress_coverage_group | |
| 125 | { | |
| 126 | const_sample_reference = 1; | |
| 127 | // sample_event = @(posedge dmu_ilu_coverage_ifc.y2k_rcd_enq ); | |
| 128 | sample_event = sync (ANY, y2k_rcd_enq_event_trig); | |
| 129 | #include "ilu_dmu_ingress_sample.vrh" | |
| 130 | } | |
| 131 | ||
| 132 | coverage_group ilu_dmu_ingress_data_coverage_group | |
| 133 | { | |
| 134 | const_sample_reference = 1; | |
| 135 | sample_event = sync (ANY, y2k_buf_addr_vld_monitor_event_trig); | |
| 136 | #include "ilu_dmu_ingress_data_sample.vrh" | |
| 137 | } | |
| 138 | ||
| 139 | coverage_group ilu_dmu_ingress_rel_coverage_group | |
| 140 | { | |
| 141 | const_sample_reference = 1; | |
| 142 | sample_event = sync (ANY, y2k_rel_enq_event_trig, y2k_rel1_enq_event_trig, y2k_rel2_enq_event_trig); | |
| 143 | #include "ilu_dmu_ingress_rel_sample.vrh" | |
| 144 | } | |
| 145 | ||
| 146 | coverage_group ilu_dmu_egress_coverage_group | |
| 147 | { | |
| 148 | const_sample_reference = 1; | |
| 149 | sample_event = sync (ANY, k2y_rcd_enq_event_trig); | |
| 150 | #include "ilu_dmu_egress_sample.vrh" | |
| 151 | } | |
| 152 | ||
| 153 | coverage_group ilu_dmu_egress_data_coverage_group | |
| 154 | { | |
| 155 | const_sample_reference = 1; | |
| 156 | // sample_event = sync (ANY, k2y_buf_addr_vld_monitor_event_trig); | |
| 157 | sample_event = sync (ANY, k2y_rcd_enq_event_trig); | |
| 158 | #include "ilu_dmu_egress_data_sample.vrh" | |
| 159 | } | |
| 160 | ||
| 161 | coverage_group ilu_dmu_egress_rel_coverage_group | |
| 162 | { | |
| 163 | const_sample_reference = 1; | |
| 164 | sample_event = sync (ANY, k2y_rel_enq_event_trig, k2y_rel1_enq_event_trig, k2y_rel2_enq_event_trig); | |
| 165 | #include "ilu_dmu_egress_rel_sample.vrh" | |
| 166 | } | |
| 167 | ||
| 168 | coverage_group ilu_dmu_d2p_req_coverage_group | |
| 169 | { | |
| 170 | sample_event = @(posedge dmu_ilu_coverage_ifc.ilu_clk ); | |
| 171 | sample dmu_ilu_coverage_ifc.d2p_req_id_1 | |
| 172 | { | |
| 173 | state s_0 (3'b000); | |
| 174 | state s_1 (3'b101); | |
| 175 | state s_2 (3'b111); | |
| 176 | } | |
| 177 | ||
| 178 | sample dmu_ilu_coverage_ifc.d2p_req_id_2 | |
| 179 | { | |
| 180 | state s_0 (5'b00000); | |
| 181 | state s_1 (5'b00101); | |
| 182 | state s_2 (5'b01010); | |
| 183 | state s_3 (5'b11111); | |
| 184 | } | |
| 185 | ||
| 186 | sample dmu_ilu_coverage_ifc.d2p_req_id_3 | |
| 187 | { | |
| 188 | state s_0 (8'b00000000); | |
| 189 | state s_1 (8'b00000101); | |
| 190 | state s_2 (8'b00001010); | |
| 191 | state s_3 (8'b11111111); | |
| 192 | } | |
| 193 | ||
| 194 | } | |
| 195 | ||
| 196 | coverage_group ilu_dmu_dou_coverage_group | |
| 197 | { | |
| 198 | const_sample_reference = 1; | |
| 199 | sample_event = sync (ANY, k2y_dou_vld_event_trig); | |
| 200 | #include "ilu_dmu_dou_sample.vrh" | |
| 201 | } | |
| 202 | ||
| 203 | coverage_group ilu_peu_interface_psr_rate_rx_b0sds0_coverage_group | |
| 204 | { | |
| 205 | const_sample_reference = 1; | |
| 206 | sample_event = wait_var(rx_b0sds0_var); | |
| 207 | // sample_event = sync (ANY, dmu_psr_rate_event_trig); | |
| 208 | // sample_event = @(posedge dmu_ilu_coverage_ifc.ilu_clk && dmu_ilu_coverage_ifc.ccu_serdes_dtm ); | |
| 209 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b0sds0 | |
| 210 | { | |
| 211 | state s_0 (2'b00); | |
| 212 | state s_1 (2'b01); | |
| 213 | state s_2 (2'b10); | |
| 214 | } | |
| 215 | } | |
| 216 | coverage_group ilu_peu_interface_psr_rate_rx_b0sds1_coverage_group | |
| 217 | { | |
| 218 | const_sample_reference = 1; | |
| 219 | sample_event = wait_var(rx_b0sds1_var); | |
| 220 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b0sds1 | |
| 221 | { | |
| 222 | state s_0 (2'b00); | |
| 223 | state s_1 (2'b01); | |
| 224 | state s_2 (2'b10); | |
| 225 | } | |
| 226 | } | |
| 227 | coverage_group ilu_peu_interface_psr_rate_rx_b1sds0_coverage_group | |
| 228 | { | |
| 229 | const_sample_reference = 1; | |
| 230 | sample_event = wait_var(rx_b1sds0_var); | |
| 231 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b1sds0 | |
| 232 | { | |
| 233 | state s_0 (2'b00); | |
| 234 | state s_1 (2'b01); | |
| 235 | state s_2 (2'b10); | |
| 236 | } | |
| 237 | } | |
| 238 | coverage_group ilu_peu_interface_psr_rate_rx_b1sds1_coverage_group | |
| 239 | { | |
| 240 | const_sample_reference = 1; | |
| 241 | sample_event = wait_var(rx_b1sds1_var); | |
| 242 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b1sds1 | |
| 243 | { | |
| 244 | state s_0 (2'b00); | |
| 245 | state s_1 (2'b01); | |
| 246 | state s_2 (2'b10); | |
| 247 | } | |
| 248 | } | |
| 249 | coverage_group ilu_peu_interface_psr_rate_rx_b2sds0_coverage_group | |
| 250 | { | |
| 251 | const_sample_reference = 1; | |
| 252 | sample_event = wait_var(rx_b2sds0_var); | |
| 253 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b2sds0 | |
| 254 | { | |
| 255 | state s_0 (2'b00); | |
| 256 | state s_1 (2'b01); | |
| 257 | state s_2 (2'b10); | |
| 258 | } | |
| 259 | } | |
| 260 | coverage_group ilu_peu_interface_psr_rate_rx_b2sds1_coverage_group | |
| 261 | { | |
| 262 | const_sample_reference = 1; | |
| 263 | sample_event = wait_var(rx_b2sds1_var); | |
| 264 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b2sds1 | |
| 265 | { | |
| 266 | state s_0 (2'b00); | |
| 267 | state s_1 (2'b01); | |
| 268 | state s_2 (2'b10); | |
| 269 | } | |
| 270 | } | |
| 271 | coverage_group ilu_peu_interface_psr_rate_rx_b3sds0_coverage_group | |
| 272 | { | |
| 273 | const_sample_reference = 1; | |
| 274 | sample_event = wait_var(rx_b3sds0_var); | |
| 275 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b3sds0 | |
| 276 | { | |
| 277 | state s_0 (2'b00); | |
| 278 | state s_1 (2'b01); | |
| 279 | state s_2 (2'b10); | |
| 280 | } | |
| 281 | } | |
| 282 | coverage_group ilu_peu_interface_psr_rate_rx_b3sds1_coverage_group | |
| 283 | { | |
| 284 | const_sample_reference = 1; | |
| 285 | sample_event = wait_var(rx_b3sds1_var); | |
| 286 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b3sds1 | |
| 287 | { | |
| 288 | state s_0 (2'b00); | |
| 289 | state s_1 (2'b01); | |
| 290 | state s_2 (2'b10); | |
| 291 | } | |
| 292 | } | |
| 293 | coverage_group ilu_peu_interface_psr_rate_tx_b0sds0_coverage_group | |
| 294 | { | |
| 295 | const_sample_reference = 1; | |
| 296 | sample_event = wait_var(tx_b0sds0_var); | |
| 297 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b0sds0 | |
| 298 | { | |
| 299 | state s_0 (2'b00); | |
| 300 | state s_1 (2'b01); | |
| 301 | state s_2 (2'b10); | |
| 302 | } | |
| 303 | } | |
| 304 | coverage_group ilu_peu_interface_psr_rate_tx_b0sds1_coverage_group | |
| 305 | { | |
| 306 | const_sample_reference = 1; | |
| 307 | sample_event = wait_var(tx_b0sds1_var); | |
| 308 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b0sds1 | |
| 309 | { | |
| 310 | state s_0 (2'b00); | |
| 311 | state s_1 (2'b01); | |
| 312 | state s_2 (2'b10); | |
| 313 | } | |
| 314 | } | |
| 315 | coverage_group ilu_peu_interface_psr_rate_tx_b1sds0_coverage_group | |
| 316 | { | |
| 317 | const_sample_reference = 1; | |
| 318 | sample_event = wait_var(tx_b1sds0_var); | |
| 319 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b1sds0 | |
| 320 | { | |
| 321 | state s_0 (2'b00); | |
| 322 | state s_1 (2'b01); | |
| 323 | state s_2 (2'b10); | |
| 324 | } | |
| 325 | } | |
| 326 | coverage_group ilu_peu_interface_psr_rate_tx_b1sds1_coverage_group | |
| 327 | { | |
| 328 | const_sample_reference = 1; | |
| 329 | sample_event = wait_var(tx_b1sds1_var); | |
| 330 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b1sds1 | |
| 331 | { | |
| 332 | state s_0 (2'b00); | |
| 333 | state s_1 (2'b01); | |
| 334 | state s_2 (2'b10); | |
| 335 | } | |
| 336 | } | |
| 337 | coverage_group ilu_peu_interface_psr_rate_tx_b2sds0_coverage_group | |
| 338 | { | |
| 339 | const_sample_reference = 1; | |
| 340 | sample_event = wait_var(tx_b2sds0_var); | |
| 341 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b2sds0 | |
| 342 | { | |
| 343 | state s_0 (2'b00); | |
| 344 | state s_1 (2'b01); | |
| 345 | state s_2 (2'b10); | |
| 346 | } | |
| 347 | } | |
| 348 | coverage_group ilu_peu_interface_psr_rate_tx_b2sds1_coverage_group | |
| 349 | { | |
| 350 | const_sample_reference = 1; | |
| 351 | sample_event = wait_var(tx_b2sds1_var); | |
| 352 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b2sds1 | |
| 353 | { | |
| 354 | state s_0 (2'b00); | |
| 355 | state s_1 (2'b01); | |
| 356 | state s_2 (2'b10); | |
| 357 | } | |
| 358 | } | |
| 359 | coverage_group ilu_peu_interface_psr_rate_tx_b3sds0_coverage_group | |
| 360 | { | |
| 361 | const_sample_reference = 1; | |
| 362 | sample_event = wait_var(tx_b3sds0_var); | |
| 363 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b3sds0 | |
| 364 | { | |
| 365 | state s_0 (2'b00); | |
| 366 | state s_1 (2'b01); | |
| 367 | state s_2 (2'b10); | |
| 368 | } | |
| 369 | } | |
| 370 | coverage_group ilu_peu_interface_psr_rate_tx_b3sds1_coverage_group | |
| 371 | { | |
| 372 | const_sample_reference = 1; | |
| 373 | sample_event = wait_var(tx_b3sds1_var); | |
| 374 | sample dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b3sds1 | |
| 375 | { | |
| 376 | state s_0 (2'b00); | |
| 377 | state s_1 (2'b01); | |
| 378 | state s_2 (2'b10); | |
| 379 | } | |
| 380 | } | |
| 381 | ||
| 382 | ||
| 383 | coverage_group ilu_peu_interface_interrupt_coverage_group | |
| 384 | { | |
| 385 | const_sample_reference = 1; | |
| 386 | // sample_event = @(posedge dmu_ilu_coverage_ifc.ilu_clk ); | |
| 387 | // sample_event = @(posedge dmu_ilu_coverage_ifc.peu_clk ); | |
| 388 | // sample_event = @(posedge dmu_ilu_coverage_ifc.j2d_por_l ); | |
| 389 | // work | |
| 390 | // sample_event = @(posedge dmu_ilu_coverage_ifc.iol2clk); | |
| 391 | // trying | |
| 392 | sample_event = @(posedge dmu_ilu_coverage_ifc.ilu_clk ); | |
| 393 | ||
| 394 | sample dmu_ilu_coverage_ifc.y2k_int_l | |
| 395 | { | |
| 396 | state y2k_int0 (0); | |
| 397 | state y2k_int1 (1); | |
| 398 | } | |
| 399 | sample dmu_ilu_coverage_ifc.p2d_ue_int | |
| 400 | { | |
| 401 | state p2d_ue_int0 (0); | |
| 402 | state p2d_ue_int1 (1); | |
| 403 | } | |
| 404 | sample dmu_ilu_coverage_ifc.p2d_ce_int | |
| 405 | { | |
| 406 | state p2d_ce_int0 (0); | |
| 407 | state p2d_ce_int1 (1); | |
| 408 | } | |
| 409 | sample dmu_ilu_coverage_ifc.p2d_oe_int | |
| 410 | { | |
| 411 | state p2d_oe_int0 (0); | |
| 412 | state p2d_oe_int1 (1); | |
| 413 | } | |
| 414 | ||
| 415 | // sample dmu_ilu_coverage_ifc.y2k_int_l, | |
| 416 | // dmu_ilu_coverage_ifc.p2d_ue_int, | |
| 417 | // dmu_ilu_coverage_ifc.p2d_ce_int, | |
| 418 | // dmu_ilu_coverage_ifc.p2d_oe_int; | |
| 419 | // { | |
| 420 | // state y2k_int_l; | |
| 421 | // state p2d_ue_int; | |
| 422 | // state p2d_ce_int; | |
| 423 | // state p2d_oe_int; | |
| 424 | // } | |
| 425 | // cross ilu_peu_interrupts_cross_cov ( | |
| 426 | // dmu_ilu_coverage_ifc.y2k_int_l, | |
| 427 | // dmu_ilu_coverage_ifc.p2d_ue_int, | |
| 428 | // dmu_ilu_coverage_ifc.p2d_ce_int, | |
| 429 | // dmu_ilu_coverage_ifc.p2d_oe_int ); | |
| 430 | ||
| 431 | } | |
| 432 | ||
| 433 | ||
| 434 | task new(); | |
| 435 | ||
| 436 | // task set_cov_cond_bits (); | |
| 437 | task set_cov_cond_bits (); | |
| 438 | ||
| 439 | ||
| 440 | } //class ilu_peu_intf_coverage | |
| 441 | ||
| 442 | task ilu_peu_intf_coverage::new() { | |
| 443 | bit coverage_on; | |
| 444 | ||
| 445 | if (get_plus_arg (CHECK, "ilu_peu_intf_coverage") || get_plus_arg (CHECK, "coverage_on")) { | |
| 446 | coverage_on = 1; | |
| 447 | } else { | |
| 448 | coverage_on = 0; | |
| 449 | } | |
| 450 | ||
| 451 | if (coverage_on) { | |
| 452 | ilu_dmu_ingress_coverage_group = new(); | |
| 453 | ilu_dmu_ingress_data_coverage_group = new(); | |
| 454 | ilu_dmu_ingress_rel_coverage_group = new(); | |
| 455 | ilu_dmu_egress_coverage_group = new(); | |
| 456 | ilu_dmu_egress_data_coverage_group = new(); | |
| 457 | ilu_dmu_egress_rel_coverage_group = new(); | |
| 458 | ilu_peu_interface_interrupt_coverage_group = new(); | |
| 459 | ||
| 460 | set_cov_cond_bits(); | |
| 461 | printf("\n\n AC: Coverage turned on for ilu_peu objects\n\n"); | |
| 462 | ||
| 463 | ||
| 464 | } | |
| 465 | ||
| 466 | } | |
| 467 | ||
| 468 | task ilu_peu_intf_coverage::set_cov_cond_bits() | |
| 469 | { | |
| 470 | reg [115:0] pec_ingress_rcd; | |
| 471 | reg [123:0] pec_egress_rcd; | |
| 472 | printf("============= AC: start set_cov_cond_bits\n"); | |
| 473 | fork | |
| 474 | { | |
| 475 | // setting event trigger for y2k_rcd_enq | |
| 476 | while (1) | |
| 477 | { | |
| 478 | @(posedge dmu_ilu_coverage_ifc.ilu_clk); | |
| 479 | ||
| 480 | rx_b0sds0_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b0sds0 ; | |
| 481 | rx_b0sds1_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b0sds1 ; | |
| 482 | rx_b1sds0_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b1sds0 ; | |
| 483 | rx_b1sds1_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b1sds1 ; | |
| 484 | rx_b2sds0_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b2sds0 ; | |
| 485 | rx_b2sds1_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b2sds1 ; | |
| 486 | rx_b3sds0_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b3sds0 ; | |
| 487 | rx_b3sds1_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_rx_b3sds1 ; | |
| 488 | tx_b0sds0_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b0sds0 ; | |
| 489 | tx_b0sds1_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b0sds1 ; | |
| 490 | tx_b1sds0_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b1sds0 ; | |
| 491 | tx_b1sds1_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b1sds1 ; | |
| 492 | tx_b2sds0_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b2sds0 ; | |
| 493 | tx_b2sds1_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b2sds1 ; | |
| 494 | tx_b3sds0_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b3sds0 ; | |
| 495 | tx_b3sds1_var = dmu_ilu_coverage_ifc.dmu_psr_rate_scale_tx_b3sds1 ; | |
| 496 | if (dmu_ilu_coverage_ifc.y2k_rcd_enq) | |
| 497 | ||
| 498 | { | |
| 499 | pec_ingress_rcd = dmu_ilu_coverage_ifc.y2k_rcd[115:0]; | |
| 500 | ilu_dmu_hdr_F = pec_ingress_rcd[115:114]; | |
| 501 | ilu_dmu_hdr_Type = pec_ingress_rcd[113:109]; | |
| 502 | ilu_dmu_hdr_F_Type = pec_ingress_rcd[115:109]; | |
| 503 | ilu_dmu_hdr_TC = pec_ingress_rcd[108:106]; | |
| 504 | ilu_dmu_hdr_Atr = pec_ingress_rcd[105:104]; | |
| 505 | ilu_dmu_hdr_Len = pec_ingress_rcd[103:94]; | |
| 506 | ilu_dmu_hdr_ReqID = pec_ingress_rcd[93:78]; | |
| 507 | ilu_dmu_hdr_TLPTag = pec_ingress_rcd[77:70]; | |
| 508 | ilu_dmu_hdr_LastDWBE = pec_ingress_rcd[69:66]; | |
| 509 | ilu_dmu_hdr_FirstDWBE = pec_ingress_rcd[65:62]; | |
| 510 | ilu_dmu_hdr_Addr = pec_ingress_rcd[61:0]; | |
| 511 | ilu_dmu_mps = dmu_ilu_coverage_ifc.y2k_mps; // max payload size | |
| 512 | trigger (y2k_rcd_enq_event_trig); | |
| 513 | printf("============= AC: cov: y2k_rcd_enq_event_trig triggered, %0d \n",get_time(LO)); | |
| 514 | //printf("============= y2k_rcd[115] = %d, y2k_rcd[114] = %d, %0d \n", dmu_ilu_coverage_ifc.y2k_rcd[115], dmu_ilu_coverage_ifc.y2k_rcd[114] ); | |
| 515 | //printf("============= y2k_rcd[115:0] = %x \n", dmu_ilu_coverage_ifc.y2k_rcd[115:0] ); | |
| 516 | } | |
| 517 | ||
| 518 | ||
| 519 | if (dmu_ilu_coverage_ifc.k2y_rcd_enq) | |
| 520 | { | |
| 521 | pec_egress_rcd = dmu_ilu_coverage_ifc.k2y_rcd[123:0]; | |
| 522 | dmu_ilu_hdr_F = pec_egress_rcd[123:122]; | |
| 523 | dmu_ilu_hdr_Type = pec_egress_rcd[121:117]; | |
| 524 | dmu_ilu_hdr_F_Type = pec_egress_rcd[123:117]; | |
| 525 | dmu_ilu_hdr_TC = pec_egress_rcd[116:114]; | |
| 526 | dmu_ilu_hdr_Atr = pec_egress_rcd[113:112]; | |
| 527 | dmu_ilu_hdr_Len = pec_egress_rcd[109:102]; | |
| 528 | dmu_ilu_hdr_ReqID = pec_egress_rcd[101:86]; | |
| 529 | dmu_ilu_hdr_TLPTag = pec_egress_rcd[85:78]; | |
| 530 | dmu_ilu_hdr_LastDWBE = pec_egress_rcd[77:74]; | |
| 531 | dmu_ilu_hdr_FirstDWBE = pec_egress_rcd[73:70]; | |
| 532 | dmu_ilu_hdr_Addr = pec_egress_rcd[69:6]; | |
| 533 | dmu_ilu_hdr_Dptr = pec_egress_rcd[5:0]; | |
| 534 | trigger (k2y_rcd_enq_event_trig); | |
| 535 | printf("============= AC: cov: k2y_rcd_enq_event_trig triggered, TLPTag %0x Addr %0x %0d \n", dmu_ilu_hdr_TLPTag, dmu_ilu_hdr_Addr, get_time(LO)); | |
| 536 | } | |
| 537 | ||
| 538 | // Egress datapath y2k_buf_addr_vld_monitor | |
| 539 | if (dmu_ilu_coverage_ifc.y2k_buf_addr_vld_monitor) | |
| 540 | { | |
| 541 | trigger (y2k_buf_addr_vld_monitor_event_trig); | |
| 542 | printf("============= AC: cov: y2k_buf_addr_vld_monitor_event_trig triggered, %0d \n",get_time(LO)); | |
| 543 | } | |
| 544 | ||
| 545 | // Egress datapath y2k_rel_enq | |
| 546 | if (dmu_ilu_coverage_ifc.y2k_rel_enq) | |
| 547 | { | |
| 548 | pec_ingress_rel = dmu_ilu_coverage_ifc.y2k_rel_rcd[4:0]; | |
| 549 | trigger (y2k_rel_enq_event_trig); | |
| 550 | printf("============= AC: cov: y2k_rel_enq_event_trig triggered, %0d \n",get_time(LO)); | |
| 551 | } | |
| 552 | ||
| 553 | if (dmu_ilu_coverage_ifc.y2k_rel_enq) | |
| 554 | { | |
| 555 | if ( dmu_ilu_coverage_ifc.y2k_rel_rcd[8] === 1'b1 ) | |
| 556 | pec_ingress_rel1 = dmu_ilu_coverage_ifc.y2k_rel_rcd[4:0]; | |
| 557 | trigger (y2k_rel1_enq_event_trig); | |
| 558 | printf("============= AC: cov: y2k_rel1_enq_event_trig triggered, %0d \n",get_time(LO)); | |
| 559 | } | |
| 560 | ||
| 561 | if (dmu_ilu_coverage_ifc.y2k_rel_enq) | |
| 562 | { | |
| 563 | if ( dmu_ilu_coverage_ifc.y2k_rel_rcd[8] === 1'b0 ) | |
| 564 | pec_ingress_rel2 = dmu_ilu_coverage_ifc.y2k_rel_rcd[3:0]; | |
| 565 | trigger (y2k_rel2_enq_event_trig); | |
| 566 | printf("============= AC: cov: y2k_rel2_enq_event_trig triggered, %0d \n",get_time(LO)); | |
| 567 | } | |
| 568 | ||
| 569 | // Egress datapath y2k_buf_addr_vld_monitor | |
| 570 | if (dmu_ilu_coverage_ifc.k2y_buf_addr_vld_monitor) | |
| 571 | { | |
| 572 | trigger (k2y_buf_addr_vld_monitor_event_trig); | |
| 573 | printf("============= AC: cov: k2y_buf_addr_vld_monitor_event_trig triggered, %0d \n",get_time(LO)); | |
| 574 | } | |
| 575 | ||
| 576 | // Egress datapath k2y_rel_enq | |
| 577 | if (dmu_ilu_coverage_ifc.k2y_rel_enq) | |
| 578 | { | |
| 579 | pec_egress_rel = dmu_ilu_coverage_ifc.k2y_rel_rcd[8:0]; | |
| 580 | trigger (k2y_rel_enq_event_trig); | |
| 581 | printf("============= AC: cov: k2y_rel_enq_event_trig triggered, %0d \n",get_time(LO)); | |
| 582 | } | |
| 583 | ||
| 584 | if (dmu_ilu_coverage_ifc.k2y_rel_enq) | |
| 585 | { | |
| 586 | if ( dmu_ilu_coverage_ifc.k2y_rel_rcd[8] === 1'b1 ) | |
| 587 | pec_egress_rel1 = dmu_ilu_coverage_ifc.k2y_rel_rcd[4:0]; | |
| 588 | trigger (k2y_rel1_enq_event_trig); | |
| 589 | printf("============= AC: cov: k2y_rel1_enq_event_trig triggered, %0d \n",get_time(LO)); | |
| 590 | } | |
| 591 | ||
| 592 | if (dmu_ilu_coverage_ifc.k2y_rel_enq) | |
| 593 | { | |
| 594 | if ( dmu_ilu_coverage_ifc.k2y_rel_rcd[8] === 1'b0 ) | |
| 595 | pec_egress_rel2 = dmu_ilu_coverage_ifc.k2y_rel_rcd[3:0]; | |
| 596 | trigger (k2y_rel2_enq_event_trig); | |
| 597 | printf("============= AC: cov: k2y_rel2_enq_event_trig triggered, %0d \n",get_time(LO)); | |
| 598 | } | |
| 599 | ||
| 600 | if (dmu_ilu_coverage_ifc.k2y_dou_vld) | |
| 601 | { | |
| 602 | k2y_dou_dptr1 = dmu_ilu_coverage_ifc.k2y_dou_dptr[4:0]; | |
| 603 | k2y_dou_err1 = dmu_ilu_coverage_ifc.k2y_dou_err; | |
| 604 | trigger (k2y_dou_vld_event_trig); | |
| 605 | printf("============= AC: cov: k2y_dou_vld_event_trig triggered, %0d \n",get_time(LO)); | |
| 606 | } | |
| 607 | ||
| 608 | if (dmu_ilu_coverage_ifc.ccu_serdes_dtm) | |
| 609 | { | |
| 610 | trigger (dmu_psr_rate_event_trig); | |
| 611 | printf("============= AC: cov: dmu_psr_rate_event_trig triggered, %0d \n",get_time(LO)); | |
| 612 | } | |
| 613 | ||
| 614 | ||
| 615 | } // end while | |
| 616 | } | |
| 617 | join none | |
| 618 | } | |
| 619 | ||
| 620 | ||
| 621 | ||
| 622 | ||
| 623 | class peu_registers_coverage | |
| 624 | { | |
| 625 | // event y2k_rcd_enq_event_trig; | |
| 626 | event oe_log_w_ld_event_trig; | |
| 627 | event oe_int_en_w_ld_event_trig; | |
| 628 | event oe_err_rw1c_event_trig; | |
| 629 | event oe_err_rw1s_event_trig; | |
| 630 | event peu_oe_err_cycle_afer_hw_set_event_trig; | |
| 631 | ||
| 632 | event ue_log_w_ld_event_trig; | |
| 633 | event ue_int_en_w_ld_event_trig; | |
| 634 | event ue_err_rw1c_event_trig; | |
| 635 | event ue_err_rw1s_event_trig; | |
| 636 | event peu_ue_err_cycle_afer_hw_set_event_trig; | |
| 637 | ||
| 638 | event ce_log_w_ld_event_trig; | |
| 639 | event ce_int_en_w_ld_event_trig; | |
| 640 | event ce_err_rw1c_event_trig; | |
| 641 | event ce_err_rw1s_event_trig; | |
| 642 | event peu_ce_err_cycle_afer_hw_set_event_trig; | |
| 643 | ||
| 644 | event peu_event_rw1c_event_trig; | |
| 645 | event peu_event_rw1s_event_trig; | |
| 646 | event peu_event_cycle_afer_hw_set_event_trig; | |
| 647 | ||
| 648 | event peu_link_bit_error_counter_I_reg_cnt_bad_event_trig; | |
| 649 | ||
| 650 | bit [63:0] peu_oe_err_hw_set_var; | |
| 651 | bit [63:0] peu_ue_err_hw_set_var; | |
| 652 | bit [63:0] peu_ce_err_hw_set_var; | |
| 653 | bit [63:0] peu_event_hw_set_var; | |
| 654 | ||
| 655 | bit [8:0] peu_debug_select_a_reg_var = 9'b0; | |
| 656 | // bit [63:0] peu_trn_off_reg_var = 64'b0; | |
| 657 | ||
| 658 | bit [63:0] peu_oe_log_en_reg_var; | |
| 659 | bit [63:0] peu_oe_int_en_reg_var; | |
| 660 | bit [63:0] peu_ce_log_en_reg_var; | |
| 661 | bit [63:0] peu_ce_int_en_reg_var; | |
| 662 | bit [63:0] peu_ue_log_en_reg_var; | |
| 663 | bit [63:0] peu_ue_int_en_reg_var; | |
| 664 | ||
| 665 | bit [63:0] peu_event_log_en_reg_var; | |
| 666 | bit [63:0] peu_event_int_en_reg_var; | |
| 667 | ||
| 668 | bit [5:0] d2p_ihb_addr = 6'b0; | |
| 669 | bit [5:0] it2ih_addr = 6'b0; | |
| 670 | bit [5:0] ihb_rd_adr = 6'b0; | |
| 671 | bit [5:0] ihb_wr_adr = 6'b0; | |
| 672 | bit [7:0] d2p_idb_addr = 8'b0; | |
| 673 | bit [7:0] it2id_addr = 8'b0; | |
| 674 | bit [7:0] idb_rd_adr = 8'b0; | |
| 675 | bit [7:0] idb_wr_adr = 8'b0; | |
| 676 | bit [5:0] et2eh_addr = 6'b0; | |
| 677 | bit [5:0] ehb_rd_adr = 6'b0; | |
| 678 | bit [5:0] ehb_wr_adr = 6'b0; | |
| 679 | bit [5:0] d2p_ehb_addr = 6'b0; | |
| 680 | bit [7:0] et2ed_addr = 8'b0; | |
| 681 | bit [7:0] edb_rd_adr = 8'b0; | |
| 682 | bit [7:0] edb_wr_adr = 8'b0; | |
| 683 | bit [7:0] d2p_edb_addr = 8'b0; | |
| 684 | bit [3:0] lpm2ctb_pmc_state = 4'b0; | |
| 685 | bit [3:0] fc_state = 4'b0; | |
| 686 | bit [4:0] lts_state = 5'b0; | |
| 687 | bit [1:0] replay_num = 2'b0; | |
| 688 | bit [7:0] rbuf_raddr = 8'b0; | |
| 689 | bit [7:0] rbuf_waddr = 8'b0; | |
| 690 | bit [7:0] retry_rd_adr = 8'b0; | |
| 691 | bit [7:0] retry_wr_adr = 8'b0; | |
| 692 | ||
| 693 | integer ihb_size = 0; | |
| 694 | integer idb_size = 0; | |
| 695 | integer ehb_size = 0; | |
| 696 | integer edb_size = 0; | |
| 697 | integer rbuf_size = 0; | |
| 698 | ||
| 699 | integer ihb_d_rd_b2b = 0; | |
| 700 | integer ihb_d_wr_b2b = 0; | |
| 701 | integer idb_d_rd_b2b = 0; | |
| 702 | integer idb_d_wr_b2b = 0; | |
| 703 | integer ehb_d_rd_b2b = 0; | |
| 704 | integer ehb_d_wr_b2b = 0; | |
| 705 | integer edb_d_rd_b2b = 0; | |
| 706 | integer edb_d_wr_b2b = 0; | |
| 707 | integer rbuf_d_rd_b2b = 0; | |
| 708 | integer rbuf_d_wr_b2b = 0; | |
| 709 | ||
| 710 | ||
| 711 | coverage_group peu_debug_select_a_reg_coverage_group | |
| 712 | { | |
| 713 | const_sample_reference = 1; | |
| 714 | sample_event = wait_var(peu_debug_select_a_reg_var); | |
| 715 | sample peu_registers_coverage_ifc.peu_debug_select_a_block[2:0] { | |
| 716 | . &toggle( 3 ); | |
| 717 | cov_weight = 1; | |
| 718 | } | |
| 719 | sample peu_registers_coverage_ifc.peu_debug_select_a_module[2:0] { | |
| 720 | . &toggle( 3 ); | |
| 721 | cov_weight = 1; | |
| 722 | } | |
| 723 | sample peu_registers_coverage_ifc.peu_debug_select_a_signal[2:0] { | |
| 724 | . &toggle( 3 ); | |
| 725 | cov_weight = 1; | |
| 726 | } | |
| 727 | ||
| 728 | cross peu_debug_select_a_reg_cross_coverage | |
| 729 | ( | |
| 730 | peu_registers_coverage_ifc.peu_debug_select_a_block[2:0], | |
| 731 | peu_registers_coverage_ifc.peu_debug_select_a_module[2:0], | |
| 732 | peu_registers_coverage_ifc.peu_debug_select_a_signal[2:0] | |
| 733 | ); | |
| 734 | } | |
| 735 | ||
| 736 | bit [8:0] peu_debug_select_b_reg_var = 9'b0; | |
| 737 | coverage_group peu_debug_select_b_reg_coverage_group | |
| 738 | { | |
| 739 | const_sample_reference = 1; | |
| 740 | sample_event = wait_var(peu_debug_select_b_reg_var); | |
| 741 | sample peu_registers_coverage_ifc.peu_debug_select_b_block[2:0] { | |
| 742 | . &toggle( 3 ); | |
| 743 | cov_weight = 1; | |
| 744 | } | |
| 745 | sample peu_registers_coverage_ifc.peu_debug_select_b_module[2:0] { | |
| 746 | . &toggle( 3 ); | |
| 747 | cov_weight = 1; | |
| 748 | } | |
| 749 | sample peu_registers_coverage_ifc.peu_debug_select_b_signal[2:0] { | |
| 750 | . &toggle( 3 ); | |
| 751 | cov_weight = 1; | |
| 752 | } | |
| 753 | ||
| 754 | cross peu_debug_select_b_reg_cross_coverage | |
| 755 | ( | |
| 756 | peu_registers_coverage_ifc.peu_debug_select_b_block[2:0], | |
| 757 | peu_registers_coverage_ifc.peu_debug_select_b_module[2:0], | |
| 758 | peu_registers_coverage_ifc.peu_debug_select_b_signal[2:0] | |
| 759 | ); | |
| 760 | } | |
| 761 | ||
| 762 | ||
| 763 | bit [63:0] peu_control_reg_var = 64'b0; | |
| 764 | ||
| 765 | coverage_group peu_control_reg_coverage_group | |
| 766 | { | |
| 767 | const_sample_reference = 1; | |
| 768 | // sample_event = wait_var(peu_registers_coverage_ifc.peu_control_reg); | |
| 769 | // sample_event = wait_var(peu_control_reg_los_tim_var); | |
| 770 | sample_event = wait_var(peu_control_reg_var); | |
| 771 | sample peu_registers_coverage_ifc.peu_control_reg_los_tim { | |
| 772 | //state peu_control_los_tim_reg_s0 (8'h0, 8'h1, 8'h2, 8'hda, 8'hff); | |
| 773 | state peu_control_los_tim_reg_s0 (8'h0); | |
| 774 | state peu_control_los_tim_reg_s1 (8'h1); | |
| 775 | state peu_control_los_tim_reg_s2 (8'h2); | |
| 776 | state peu_control_los_tim_reg_sda (8'hda); | |
| 777 | state peu_control_los_tim_reg_sff (8'hff); | |
| 778 | } | |
| 779 | ||
| 780 | ||
| 781 | ||
| 782 | } | |
| 783 | ||
| 784 | coverage_group peu_bit_error_cnt1_reg_cnt_bad_coverage_group | |
| 785 | { | |
| 786 | const_sample_reference = 1; | |
| 787 | sample_event = sync(ANY,peu_link_bit_error_counter_I_reg_cnt_bad_event_trig); | |
| 788 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg_cnt_bad_dllp[7:0] { | |
| 789 | . for ($i=0; $i<255; $i++) | |
| 790 | . { | |
| 791 | . $j = $i + 1; | |
| 792 | trans peu_bit_error_cnt_bad_dllp_t${i}_to_t${j} (${i} -> ${j}); | |
| 793 | . } | |
| 794 | bad_trans peu_bit_error_cnt_bad_dllp_t255_to_0 (255 -> 0); | |
| 795 | } | |
| 796 | ||
| 797 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg_cnt_bad_tlp[7:0] { | |
| 798 | . for ($i=0; $i<255; $i++) | |
| 799 | . { | |
| 800 | . $j = $i + 1; | |
| 801 | trans peu_bit_error_cnt_bad_tllp_t${i}_to_t${j} (${i} -> ${j}); | |
| 802 | . } | |
| 803 | bad_trans peu_bit_error_cnt_bad_tllp_t255_to_0 (255 -> 0); | |
| 804 | } | |
| 805 | ||
| 806 | ||
| 807 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg_cnt_pre[9:0] { | |
| 808 | . for ($i=0; $i<1023; $i++) | |
| 809 | . { | |
| 810 | . $j = $i + 1; | |
| 811 | trans peu_bit_error_cnt_pre_t${i}_to_t${j} (${i} -> ${j}); | |
| 812 | . } | |
| 813 | bad_trans peu_bit_error_cnt_pre_t1023_to_0 (1023 -> 0); | |
| 814 | } | |
| 815 | ||
| 816 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_II_reg[5:0] { | |
| 817 | . for ($i=0; $i<63; $i++) | |
| 818 | . { | |
| 819 | . $j = $i + 1; | |
| 820 | trans peu_bit_error_cnt_bad_sym_0_t${i}_to_t${j} (${i} -> ${j}); | |
| 821 | . } | |
| 822 | bad_trans peu_bit_error_cnt_bad_sym_t63_to_0 (63 -> 0); | |
| 823 | } | |
| 824 | ||
| 825 | ||
| 826 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_II_reg[13:8] { | |
| 827 | . for ($i=0; $i<63; $i++) | |
| 828 | . { | |
| 829 | . $j = $i + 1; | |
| 830 | trans peu_bit_error_cnt_bad_sym_1_t${i}_to_t${j} (${i} -> ${j}); | |
| 831 | . } | |
| 832 | bad_trans peu_bit_error_cnt_bad_sym_t63_to_0 (63 -> 0); | |
| 833 | } | |
| 834 | ||
| 835 | ||
| 836 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_II_reg[21:16] { | |
| 837 | . for ($i=0; $i<63; $i++) | |
| 838 | . { | |
| 839 | . $j = $i + 1; | |
| 840 | trans peu_bit_error_cnt_bad_sym_2_t${i}_to_t${j} (${i} -> ${j}); | |
| 841 | . } | |
| 842 | bad_trans peu_bit_error_cnt_bad_sym_t63_to_0 (63 -> 0); | |
| 843 | } | |
| 844 | ||
| 845 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_II_reg[29:24] { | |
| 846 | . for ($i=0; $i<63; $i++) | |
| 847 | . { | |
| 848 | . $j = $i + 1; | |
| 849 | trans peu_bit_error_cnt_bad_sym_3_t${i}_to_t${j} (${i} -> ${j}); | |
| 850 | . } | |
| 851 | bad_trans peu_bit_error_cnt_bad_sym_t63_to_0 (63 -> 0); | |
| 852 | } | |
| 853 | ||
| 854 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_II_reg[37:32] { | |
| 855 | . for ($i=0; $i<63; $i++) | |
| 856 | . { | |
| 857 | . $j = $i + 1; | |
| 858 | trans peu_bit_error_cnt_bad_sym_4_t${i}_to_t${j} (${i} -> ${j}); | |
| 859 | . } | |
| 860 | bad_trans peu_bit_error_cnt_bad_sym_t63_to_0 (63 -> 0); | |
| 861 | } | |
| 862 | ||
| 863 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_II_reg[45:40] { | |
| 864 | . for ($i=0; $i<63; $i++) | |
| 865 | . { | |
| 866 | . $j = $i + 1; | |
| 867 | trans peu_bit_error_cnt_bad_sym_5_t${i}_to_t${j} (${i} -> ${j}); | |
| 868 | . } | |
| 869 | bad_trans peu_bit_error_cnt_bad_sym_t63_to_0 (63 -> 0); | |
| 870 | } | |
| 871 | ||
| 872 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_II_reg[53:48] { | |
| 873 | . for ($i=0; $i<63; $i++) | |
| 874 | . { | |
| 875 | . $j = $i + 1; | |
| 876 | trans peu_bit_error_cnt_bad_sym_6_t${i}_to_t${j} (${i} -> ${j}); | |
| 877 | . } | |
| 878 | bad_trans peu_bit_error_cnt_bad_sym_t63_to_0 (63 -> 0); | |
| 879 | } | |
| 880 | ||
| 881 | sample peu_registers_coverage_ifc.peu_link_bit_error_counter_II_reg[61:56] { | |
| 882 | . for ($i=0; $i<63; $i++) | |
| 883 | . { | |
| 884 | . $j = $i + 1; | |
| 885 | trans peu_bit_error_cnt_bad_sym_7_t${i}_to_t${j} (${i} -> ${j}); | |
| 886 | . } | |
| 887 | bad_trans peu_bit_error_cnt_bad_sym_t63_to_0 (63 -> 0); | |
| 888 | } | |
| 889 | ||
| 890 | } | |
| 891 | ||
| 892 | #include "peu_register_coverage_sample.vrh" | |
| 893 | ||
| 894 | //========= peu RAS | |
| 895 | //== peu oe log enable reg ; | |
| 896 | coverage_group peu_oe_log_en_reg_coverage_group | |
| 897 | { | |
| 898 | const_sample_reference = 1; | |
| 899 | // sample_event = sync(ANY, oe_log_w_ld_event_trig); | |
| 900 | sample_event = wait_var(peu_oe_log_en_reg_var); | |
| 901 | sample peu_oe_log_en_reg_sample (peu_registers_coverage_ifc.peu_oe_log_en_reg) { | |
| 902 | . &toggle( 24 ); | |
| 903 | cov_weight = 1; | |
| 904 | } | |
| 905 | ||
| 906 | // #include "peu_ras_coverage_sample.vrh" | |
| 907 | } | |
| 908 | ||
| 909 | // peu interrupt enable register | |
| 910 | coverage_group peu_oe_int_en_reg_coverage_group | |
| 911 | { | |
| 912 | const_sample_reference = 1; | |
| 913 | // sample_event = sync(ANY, oe_int_en_w_ld_event_trig); | |
| 914 | sample_event = wait_var(peu_oe_int_en_reg_var); | |
| 915 | sample peu_oe_int_en_reg_55_32_sample (peu_registers_coverage_ifc.peu_oe_int_en_reg[55:32]) { | |
| 916 | . &toggle( 24 ); | |
| 917 | cov_weight = 1; | |
| 918 | } | |
| 919 | sample peu_oe_int_en_reg_23_0_sample (peu_registers_coverage_ifc.peu_oe_int_en_reg[23:0]) | |
| 920 | { | |
| 921 | . &toggle( 24 ); | |
| 922 | cov_weight = 1; | |
| 923 | } | |
| 924 | } | |
| 925 | ||
| 926 | ||
| 927 | // peu oe error register | |
| 928 | // == oe error reg : sw clear status coverage group | |
| 929 | coverage_group peu_oe_err_sw_clear_coverage_group | |
| 930 | { | |
| 931 | const_sample_reference = 1; | |
| 932 | sample_event = sync(ANY, oe_err_rw1c_event_trig); | |
| 933 | sample peu_oe_err_csr_rw1c_22_0_secondary (peu_registers_coverage_ifc.peu_oe_err_csrbus_wr_data[22:0]) { | |
| 934 | . &toggle( 23 ); | |
| 935 | cov_weight = 1; | |
| 936 | } | |
| 937 | sample peu_oe_err_csr_rw1c_42_32_secondary (peu_registers_coverage_ifc.peu_oe_err_csrbus_wr_data[42:32]) { | |
| 938 | . &toggle( 11 ); | |
| 939 | cov_weight = 1; | |
| 940 | } | |
| 941 | sample peu_oe_err_csr_rw1c_54_44_primary (peu_registers_coverage_ifc.peu_oe_err_csrbus_wr_data[54:44]) { | |
| 942 | . &toggle( 11 ); | |
| 943 | cov_weight = 1; | |
| 944 | } | |
| 945 | } | |
| 946 | ||
| 947 | // == oe error reg : sw set status coverage group | |
| 948 | coverage_group peu_oe_err_sw_set_coverage_group | |
| 949 | { | |
| 950 | const_sample_reference = 1; | |
| 951 | sample_event = sync(ANY, oe_err_rw1s_event_trig); | |
| 952 | sample peu_oe_err_csr_rw1s_22_0_secondary (peu_registers_coverage_ifc.peu_oe_err_csrbus_wr_data[22:0]) { | |
| 953 | . &toggle( 23 ); | |
| 954 | cov_weight = 1; | |
| 955 | } | |
| 956 | sample peu_oe_err_csr_rw1s_42_32_primary (peu_registers_coverage_ifc.peu_oe_err_csrbus_wr_data[42:32]) { | |
| 957 | . &toggle( 11 ); | |
| 958 | cov_weight = 1; | |
| 959 | } | |
| 960 | sample peu_oe_err_csr_rw1s_54_44_primary (peu_registers_coverage_ifc.peu_oe_err_csrbus_wr_data[54:44]) { | |
| 961 | . &toggle( 11 ); | |
| 962 | cov_weight = 1; | |
| 963 | } | |
| 964 | } | |
| 965 | ||
| 966 | // == oe error reg : hw set status coverage group | |
| 967 | coverage_group peu_oe_err_hw_set_coverage_group | |
| 968 | { | |
| 969 | const_sample_reference = 1; | |
| 970 | ||
| 971 | sample_event = sync(ANY, peu_oe_err_cycle_afer_hw_set_event_trig); | |
| 972 | // sample_event = sync(ANY, oe_log_w_ld_event_trig); | |
| 973 | #include "peu_oe_error_sample.vrh" | |
| 974 | // sample peu_oe_eip ( { peu_registers_coverage_ifc.peu_oe_err_csrbus_read_data[32], | |
| 975 | // peu_registers_coverage_ifc.peu_oe_err_csrbus_read_data[0] }); | |
| 976 | ||
| 977 | ||
| 978 | } | |
| 979 | ||
| 980 | ||
| 981 | //== peu ue log enable reg ; | |
| 982 | coverage_group peu_ue_log_en_reg_coverage_group | |
| 983 | { | |
| 984 | const_sample_reference = 1; | |
| 985 | // sample_event = sync(ANY, ue_log_w_ld_event_trig); | |
| 986 | sample_event = wait_var(peu_ue_log_en_reg_var); | |
| 987 | sample peu_ue_log_en_reg_20_0_sample (peu_registers_coverage_ifc.peu_ue_log_en_reg[20:0]) { | |
| 988 | . &toggle( 21 ); | |
| 989 | cov_weight = 1; | |
| 990 | } | |
| 991 | } | |
| 992 | ||
| 993 | // peu interrupt enable register | |
| 994 | coverage_group peu_ue_int_en_reg_coverage_group | |
| 995 | { | |
| 996 | const_sample_reference = 1; | |
| 997 | // sample_event = sync(ANY, ue_int_en_w_ld_event_trig); | |
| 998 | sample_event = wait_var(peu_ue_int_en_reg_var); | |
| 999 | sample peu_ue_int_en_reg_52_32_sample (peu_registers_coverage_ifc.peu_ue_int_en_reg[52:32]) { | |
| 1000 | . &toggle( 21 ); | |
| 1001 | cov_weight = 1; | |
| 1002 | } | |
| 1003 | sample peu_ue_int_en_reg_20_0_sample (peu_registers_coverage_ifc.peu_ue_int_en_reg[20:0]) | |
| 1004 | { | |
| 1005 | . &toggle( 21 ); | |
| 1006 | cov_weight = 1; | |
| 1007 | } | |
| 1008 | } | |
| 1009 | ||
| 1010 | ||
| 1011 | // peu ue error register | |
| 1012 | // == ue error reg : sw clear status coverage group | |
| 1013 | coverage_group peu_ue_err_sw_clear_coverage_group | |
| 1014 | { | |
| 1015 | const_sample_reference = 1; | |
| 1016 | sample_event = sync(ANY, ue_err_rw1c_event_trig); | |
| 1017 | sample peu_ue_err_csr_rw1c_4_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[4]) { | |
| 1018 | . &toggle( 1 ); | |
| 1019 | cov_weight = 1; | |
| 1020 | } | |
| 1021 | sample peu_ue_err_csr_rw1c_14_12_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[14:12]) { | |
| 1022 | . &toggle( 3 ); | |
| 1023 | cov_weight = 1; | |
| 1024 | } | |
| 1025 | sample peu_ue_err_csr_rw1c_18_16_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[18:16]) { | |
| 1026 | . &toggle( 3 ); | |
| 1027 | cov_weight = 1; | |
| 1028 | } | |
| 1029 | sample peu_ue_err_csr_rw1c_20_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[20]) { | |
| 1030 | . &toggle( 1 ); | |
| 1031 | cov_weight = 1; | |
| 1032 | } | |
| 1033 | sample peu_ue_err_csr_rw1c_36_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[36]) { | |
| 1034 | . &toggle( 1 ); | |
| 1035 | cov_weight = 1; | |
| 1036 | } | |
| 1037 | sample peu_ue_err_csr_rw1c_46_44_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[46:44]) { | |
| 1038 | . &toggle( 3 ); | |
| 1039 | cov_weight = 1; | |
| 1040 | } | |
| 1041 | sample peu_ue_err_csr_rw1c_50_48_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[50:48]) { | |
| 1042 | . &toggle( 3 ); | |
| 1043 | cov_weight = 1; | |
| 1044 | } | |
| 1045 | sample peu_ue_err_csr_rw1c_52_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[52]) { | |
| 1046 | . &toggle( 1 ); | |
| 1047 | cov_weight = 1; | |
| 1048 | } | |
| 1049 | } | |
| 1050 | ||
| 1051 | // == ue error reg : sw set status coverage group | |
| 1052 | coverage_group peu_ue_err_sw_set_coverage_group | |
| 1053 | { | |
| 1054 | const_sample_reference = 1; | |
| 1055 | sample_event = sync(ANY, ue_err_rw1s_event_trig); | |
| 1056 | sample peu_ue_err_csr_rw1s_4_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[4]) { | |
| 1057 | . &toggle( 1 ); | |
| 1058 | cov_weight = 1; | |
| 1059 | } | |
| 1060 | sample peu_ue_err_csr_rw1s_14_12_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[14:12]) { | |
| 1061 | . &toggle( 3 ); | |
| 1062 | cov_weight = 1; | |
| 1063 | } | |
| 1064 | sample peu_ue_err_csr_rw1s_18_16_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[18:16]) { | |
| 1065 | . &toggle( 3 ); | |
| 1066 | cov_weight = 1; | |
| 1067 | } | |
| 1068 | sample peu_ue_err_csr_rw1s_20_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[20]) { | |
| 1069 | . &toggle( 1 ); | |
| 1070 | cov_weight = 1; | |
| 1071 | } | |
| 1072 | sample peu_ue_err_csr_rw1s_36_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[36]) { | |
| 1073 | . &toggle( 1 ); | |
| 1074 | cov_weight = 1; | |
| 1075 | } | |
| 1076 | sample peu_ue_err_csr_rw1s_46_44_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[46:44]) { | |
| 1077 | . &toggle( 3 ); | |
| 1078 | cov_weight = 1; | |
| 1079 | } | |
| 1080 | sample peu_ue_err_csr_rw1s_50_48_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[50:48]) { | |
| 1081 | . &toggle( 3 ); | |
| 1082 | cov_weight = 1; | |
| 1083 | } | |
| 1084 | sample peu_ue_err_csr_rw1s_52_secondary (peu_registers_coverage_ifc.peu_ue_err_csrbus_wr_data[52]) { | |
| 1085 | . &toggle( 1 ); | |
| 1086 | cov_weight = 1; | |
| 1087 | } | |
| 1088 | } | |
| 1089 | ||
| 1090 | // == ue error reg : hw set status coverage group | |
| 1091 | coverage_group peu_ue_err_hw_set_coverage_group | |
| 1092 | { | |
| 1093 | const_sample_reference = 1; | |
| 1094 | sample_event = sync(ANY, peu_ue_err_cycle_afer_hw_set_event_trig); | |
| 1095 | #include "peu_ue_error_sample.vrh" | |
| 1096 | } | |
| 1097 | ||
| 1098 | ||
| 1099 | ||
| 1100 | //== peu ce log enable reg ; | |
| 1101 | coverage_group peu_ce_log_en_reg_coverage_group | |
| 1102 | { | |
| 1103 | const_sample_reference = 1; | |
| 1104 | // sample_event = sync(ANY, ce_log_w_ld_event_trig); | |
| 1105 | sample_event = wait_var(peu_ce_log_en_reg_var); | |
| 1106 | sample peu_ce_log_en_reg_12_0_sample (peu_registers_coverage_ifc.peu_ce_log_en_reg[12:0]) { | |
| 1107 | . &toggle( 13 ); | |
| 1108 | cov_weight = 1; | |
| 1109 | } | |
| 1110 | } | |
| 1111 | ||
| 1112 | // peu interrupt enable register | |
| 1113 | coverage_group peu_ce_int_en_reg_coverage_group | |
| 1114 | { | |
| 1115 | const_sample_reference = 1; | |
| 1116 | // sample_event = sync(ANY, ce_int_en_w_ld_event_trig); | |
| 1117 | sample_event = wait_var(peu_ce_int_en_reg_var); | |
| 1118 | sample peu_ce_int_en_reg_44_32_sample (peu_registers_coverage_ifc.peu_ce_int_en_reg[44:32]) { | |
| 1119 | . &toggle( 13 ); | |
| 1120 | cov_weight = 1; | |
| 1121 | } | |
| 1122 | sample peu_ce_int_en_reg_12_0_sample (peu_registers_coverage_ifc.peu_ce_int_en_reg[12:0]) | |
| 1123 | { | |
| 1124 | . &toggle( 13 ); | |
| 1125 | cov_weight = 1; | |
| 1126 | } | |
| 1127 | } | |
| 1128 | ||
| 1129 | ||
| 1130 | // peu ce error register | |
| 1131 | // == ce error reg : sw clear status coverage group | |
| 1132 | coverage_group peu_ce_err_sw_clear_coverage_group | |
| 1133 | { | |
| 1134 | const_sample_reference = 1; | |
| 1135 | sample_event = sync(ANY, ce_err_rw1c_event_trig); | |
| 1136 | sample peu_ce_err_csr_rw1c_0_primary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[0]) { | |
| 1137 | . &toggle( 1); | |
| 1138 | cov_weight = 1; | |
| 1139 | } | |
| 1140 | sample peu_ce_err_csr_rw1c_8_6_primary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[8:6]) { | |
| 1141 | . &toggle( 3 ); | |
| 1142 | cov_weight = 1; | |
| 1143 | } | |
| 1144 | sample peu_ce_err_csr_rw1c_12_primary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[12]) { | |
| 1145 | . &toggle( 1); | |
| 1146 | cov_weight = 1; | |
| 1147 | } | |
| 1148 | sample peu_ce_err_csr_rw1c_32_secondary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[32]) { | |
| 1149 | . &toggle( 1); | |
| 1150 | cov_weight = 1; | |
| 1151 | } | |
| 1152 | sample peu_ce_err_csr_rw1c_40_38_secondary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[40:38]) { | |
| 1153 | . &toggle( 3 ); | |
| 1154 | cov_weight = 1; | |
| 1155 | } | |
| 1156 | sample peu_ce_err_csr_rw1c_44_secondary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[44]) { | |
| 1157 | . &toggle( 1); | |
| 1158 | cov_weight = 1; | |
| 1159 | } | |
| 1160 | } | |
| 1161 | ||
| 1162 | // == ce error reg : sw set status coverage group | |
| 1163 | coverage_group peu_ce_err_sw_set_coverage_group | |
| 1164 | { | |
| 1165 | const_sample_reference = 1; | |
| 1166 | sample_event = sync(ANY, ce_err_rw1s_event_trig); | |
| 1167 | sample peu_ce_err_csr_rw1s_0_primary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[0]) { | |
| 1168 | . &toggle( 1); | |
| 1169 | cov_weight = 1; | |
| 1170 | } | |
| 1171 | sample peu_ce_err_csr_rw1s_8_6_primary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[8:6]) { | |
| 1172 | . &toggle( 3 ); | |
| 1173 | cov_weight = 1; | |
| 1174 | } | |
| 1175 | sample peu_ce_err_csr_rw1s_12_primary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[12]) { | |
| 1176 | . &toggle( 1); | |
| 1177 | cov_weight = 1; | |
| 1178 | } | |
| 1179 | sample peu_ce_err_csr_rw1s_32_secondary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[32]) { | |
| 1180 | . &toggle( 1); | |
| 1181 | cov_weight = 1; | |
| 1182 | } | |
| 1183 | sample peu_ce_err_csr_rw1s_40_38_secondary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[40:38]) { | |
| 1184 | . &toggle( 3 ); | |
| 1185 | cov_weight = 1; | |
| 1186 | } | |
| 1187 | sample peu_ce_err_csr_rw1s_44_secondary (peu_registers_coverage_ifc.peu_ce_err_csrbus_wr_data[44]) { | |
| 1188 | . &toggle( 1); | |
| 1189 | cov_weight = 1; | |
| 1190 | } | |
| 1191 | ||
| 1192 | } | |
| 1193 | ||
| 1194 | // == ce error reg : hw set status coverage group | |
| 1195 | coverage_group peu_ce_err_hw_set_coverage_group | |
| 1196 | { | |
| 1197 | const_sample_reference = 1; | |
| 1198 | sample_event = sync(ANY, peu_ce_err_cycle_afer_hw_set_event_trig); | |
| 1199 | #include "peu_ce_error_sample.vrh" | |
| 1200 | } | |
| 1201 | ||
| 1202 | ||
| 1203 | //== peu dlpl err log enable reg | |
| 1204 | coverage_group peu_event_log_en_reg_coverage_group | |
| 1205 | { | |
| 1206 | const_sample_reference = 1; | |
| 1207 | sample_event = wait_var(peu_event_log_en_reg_var); | |
| 1208 | sample peu_event_log_en_reg_17_0_sample (peu_registers_coverage_ifc.peu_event_log_en_reg[17:0]) { | |
| 1209 | . &toggle( 18 ); | |
| 1210 | cov_weight = 1; | |
| 1211 | } | |
| 1212 | sample peu_event_log_en_reg_31_24_sample (peu_registers_coverage_ifc.peu_event_log_en_reg[31:24]) { | |
| 1213 | . &toggle( 8 ); | |
| 1214 | cov_weight = 1; | |
| 1215 | } | |
| 1216 | } | |
| 1217 | ||
| 1218 | // peu dlpl error interrupt enable register | |
| 1219 | coverage_group peu_event_int_en_reg_coverage_group | |
| 1220 | { | |
| 1221 | const_sample_reference = 1; | |
| 1222 | sample_event = wait_var(peu_event_int_en_reg_var); | |
| 1223 | sample peu_event_int_en_reg_17_0_sample (peu_registers_coverage_ifc.peu_event_int_en_reg[17:0]) { | |
| 1224 | . &toggle( 18 ); | |
| 1225 | cov_weight = 1; | |
| 1226 | } | |
| 1227 | sample peu_event_int_en_reg_31_24_sample (peu_registers_coverage_ifc.peu_event_int_en_reg[31:24]) | |
| 1228 | { | |
| 1229 | . &toggle( 8 ); | |
| 1230 | cov_weight = 1; | |
| 1231 | } | |
| 1232 | } | |
| 1233 | ||
| 1234 | ||
| 1235 | // peu dlpl err error register | |
| 1236 | // == dlpl error reg : sw clear status coverage group | |
| 1237 | coverage_group peu_event_sw_clear_coverage_group | |
| 1238 | { | |
| 1239 | const_sample_reference = 1; | |
| 1240 | sample_event = sync(ANY, peu_event_rw1c_event_trig); | |
| 1241 | sample peu_event_csr_rw1c_17_0 (peu_registers_coverage_ifc.peu_event_csrbus_wr_data[17:0]) { | |
| 1242 | . &toggle( 18 ); | |
| 1243 | cov_weight = 1; | |
| 1244 | } | |
| 1245 | sample peu_event_csr_rw1c_31_24 (peu_registers_coverage_ifc.peu_event_csrbus_wr_data[31:24]) { | |
| 1246 | . &toggle( 8 ); | |
| 1247 | cov_weight = 1; | |
| 1248 | } | |
| 1249 | } | |
| 1250 | ||
| 1251 | // == dlpl error reg : sw set status coverage group | |
| 1252 | coverage_group peu_event_sw_set_coverage_group | |
| 1253 | { | |
| 1254 | const_sample_reference = 1; | |
| 1255 | sample_event = sync(ANY, peu_event_rw1s_event_trig); | |
| 1256 | sample peu_event_csr_rw1s_17_0 (peu_registers_coverage_ifc.peu_event_csrbus_wr_data[17:0]) { | |
| 1257 | . &toggle( 18 ); | |
| 1258 | cov_weight = 1; | |
| 1259 | } | |
| 1260 | sample peu_event_csr_rw1s_31_24 (peu_registers_coverage_ifc.peu_event_csrbus_wr_data[31:24]) { | |
| 1261 | . &toggle( 8 ); | |
| 1262 | cov_weight = 1; | |
| 1263 | } | |
| 1264 | } | |
| 1265 | ||
| 1266 | // == dlpl error reg : hw set status coverage group | |
| 1267 | coverage_group peu_event_hw_set_coverage_group | |
| 1268 | { | |
| 1269 | const_sample_reference = 1; | |
| 1270 | ||
| 1271 | sample_event = sync(ANY, peu_event_cycle_afer_hw_set_event_trig); | |
| 1272 | // include "peu_eventor_sample.vrh" | |
| 1273 | sample peu_event_hw_set_17_0 (peu_registers_coverage_ifc.peu_event_csrbus_read_data[17:0]) { | |
| 1274 | . &toggle( 18 ); | |
| 1275 | cov_weight = 1; | |
| 1276 | } | |
| 1277 | sample peu_event_csr_hw_set_31_24 (peu_registers_coverage_ifc.peu_event_csrbus_read_data[31:24]) { | |
| 1278 | . &toggle( 8 ); | |
| 1279 | cov_weight = 1; | |
| 1280 | } | |
| 1281 | ||
| 1282 | } | |
| 1283 | ||
| 1284 | ||
| 1285 | coverage_group ilu_peu_cov_ihb_rd_coverage_group | |
| 1286 | { | |
| 1287 | sample_event = wait_var(d2p_ihb_addr); | |
| 1288 | #include "ilu_peu_ihb_rd_sample.vrh" | |
| 1289 | } | |
| 1290 | ||
| 1291 | coverage_group ilu_peu_cov_ihb_wr_coverage_group | |
| 1292 | { | |
| 1293 | sample_event = wait_var(it2ih_addr); | |
| 1294 | #include "ilu_peu_ihb_wr_sample.vrh" | |
| 1295 | } | |
| 1296 | ||
| 1297 | coverage_group ilu_peu_cov_idb_rd_coverage_group | |
| 1298 | { | |
| 1299 | sample_event = wait_var(d2p_idb_addr); | |
| 1300 | #include "ilu_peu_idb_rd_sample.vrh" | |
| 1301 | } | |
| 1302 | ||
| 1303 | coverage_group ilu_peu_cov_idb_wr_coverage_group | |
| 1304 | { | |
| 1305 | sample_event = wait_var(it2id_addr); | |
| 1306 | #include "ilu_peu_idb_wr_sample.vrh" | |
| 1307 | } | |
| 1308 | ||
| 1309 | coverage_group ilu_peu_cov_ehb_rd_coverage_group | |
| 1310 | { | |
| 1311 | sample_event = wait_var(et2eh_addr); | |
| 1312 | #include "ilu_peu_ehb_rd_sample.vrh" | |
| 1313 | } | |
| 1314 | ||
| 1315 | coverage_group ilu_peu_cov_ehb_wr_coverage_group | |
| 1316 | { | |
| 1317 | sample_event = wait_var(d2p_ehb_addr); | |
| 1318 | #include "ilu_peu_ehb_wr_sample.vrh" | |
| 1319 | } | |
| 1320 | ||
| 1321 | coverage_group ilu_peu_cov_edb_rd_coverage_group | |
| 1322 | { | |
| 1323 | sample_event = wait_var(et2ed_addr); | |
| 1324 | #include "ilu_peu_edb_rd_sample.vrh" | |
| 1325 | } | |
| 1326 | ||
| 1327 | coverage_group ilu_peu_cov_edb_wr_coverage_group | |
| 1328 | { | |
| 1329 | sample_event = wait_var(d2p_edb_addr); | |
| 1330 | #include "ilu_peu_edb_wr_sample.vrh" | |
| 1331 | } | |
| 1332 | ||
| 1333 | coverage_group ilu_peu_cov_pmc_state_coverage_group | |
| 1334 | { | |
| 1335 | sample_event = wait_var(lpm2ctb_pmc_state); | |
| 1336 | #include "ilu_peu_pm_state_sample.vrh" | |
| 1337 | } | |
| 1338 | ||
| 1339 | coverage_group ilu_peu_cov_fcsm_state_coverage_group | |
| 1340 | { | |
| 1341 | sample_event = wait_var(fc_state); | |
| 1342 | #include "ilu_peu_fcsm_state_sample.vrh" | |
| 1343 | } | |
| 1344 | ||
| 1345 | coverage_group ilu_peu_cov_ltssm_state_coverage_group | |
| 1346 | { | |
| 1347 | sample_event = wait_var(lts_state); | |
| 1348 | #include "ilu_peu_ltssm_state_sample.vrh" | |
| 1349 | } | |
| 1350 | ||
| 1351 | coverage_group ilu_peu_cov_replay_coverage_group | |
| 1352 | { | |
| 1353 | sample_event = wait_var(replay_num); | |
| 1354 | #include "ilu_peu_replay_times_sample.vrh" | |
| 1355 | } | |
| 1356 | ||
| 1357 | coverage_group ilu_peu_cov_retry_buf_rd_coverage_group | |
| 1358 | { | |
| 1359 | sample_event = wait_var(rbuf_raddr); | |
| 1360 | #include "ilu_peu_retry_buf_rd_sample.vrh" | |
| 1361 | } | |
| 1362 | ||
| 1363 | coverage_group ilu_peu_cov_retry_buf_wr_coverage_group | |
| 1364 | { | |
| 1365 | sample_event = wait_var(rbuf_waddr); | |
| 1366 | #include "ilu_peu_retry_buf_wr_sample.vrh" | |
| 1367 | } | |
| 1368 | ||
| 1369 | // peu error log enable reg | |
| 1370 | coverage_group ilu_peu_cov_log_en_reg_coverage_group | |
| 1371 | { | |
| 1372 | const_sample_reference = 1; | |
| 1373 | sample_event = wait_var(peu_event_log_en_reg_var); | |
| 1374 | sample peu_error_log_en (peu_registers_coverage_ifc.ilu_error_log_enable_reg) { | |
| 1375 | . &toggle( 1 ); | |
| 1376 | cov_weight = 1; | |
| 1377 | } | |
| 1378 | } | |
| 1379 | ||
| 1380 | // peu error interrupt reg | |
| 1381 | coverage_group ilu_peu_cov_interrupt_coverage_group | |
| 1382 | { | |
| 1383 | const_sample_reference = 1; | |
| 1384 | sample_event = wait_var(peu_event_int_en_reg_var); | |
| 1385 | sample peu_interrupt_p (peu_registers_coverage_ifc.ilu_error_interrupt_p_reg) { | |
| 1386 | . &toggle( 1); | |
| 1387 | cov_weight = 1; | |
| 1388 | } | |
| 1389 | sample peu_interrupt_s (peu_registers_coverage_ifc.ilu_error_interrupt_s_reg) { | |
| 1390 | . &toggle( 1); | |
| 1391 | cov_weight = 1; | |
| 1392 | } | |
| 1393 | } | |
| 1394 | ||
| 1395 | // peu error status clear reg | |
| 1396 | coverage_group ilu_peu_cov_error_status_clear_coverage_group | |
| 1397 | { | |
| 1398 | const_sample_reference = 1; | |
| 1399 | sample_event = sync(ANY, peu_event_rw1c_event_trig); | |
| 1400 | sample peu_error_status_p_rw1c (peu_registers_coverage_ifc.ilu_error_status_p_reg) { | |
| 1401 | . &toggle( 1); | |
| 1402 | cov_weight = 1; | |
| 1403 | } | |
| 1404 | sample peu_error_status_s_rw1c (peu_registers_coverage_ifc.ilu_error_status_s_reg) { | |
| 1405 | . &toggle( 1); | |
| 1406 | cov_weight = 1; | |
| 1407 | } | |
| 1408 | } | |
| 1409 | ||
| 1410 | // peu error status set reg | |
| 1411 | coverage_group ilu_peu_cov_error_status_set_coverage_group | |
| 1412 | { | |
| 1413 | const_sample_reference = 1; | |
| 1414 | sample_event = sync(ANY, peu_event_rw1s_event_trig); | |
| 1415 | sample peu_error_status_p_rw1s (peu_registers_coverage_ifc.ilu_error_status_p_reg) { | |
| 1416 | . &toggle( 1); | |
| 1417 | cov_weight = 1; | |
| 1418 | } | |
| 1419 | sample peu_error_status_s_rw1s (peu_registers_coverage_ifc.ilu_error_status_s_reg) { | |
| 1420 | . &toggle( 1); | |
| 1421 | cov_weight = 1; | |
| 1422 | } | |
| 1423 | } | |
| 1424 | ||
| 1425 | ||
| 1426 | task new(); | |
| 1427 | task set_cov_cond_bits (); | |
| 1428 | ||
| 1429 | ||
| 1430 | } //class peu_registers_coverage | |
| 1431 | ||
| 1432 | ||
| 1433 | task peu_registers_coverage::new() { | |
| 1434 | bit coverage_on; | |
| 1435 | ||
| 1436 | if (get_plus_arg (CHECK, "peu_registers_coverage") || get_plus_arg (CHECK, "coverage_on")) { | |
| 1437 | coverage_on = 1; | |
| 1438 | } else { | |
| 1439 | coverage_on = 0; | |
| 1440 | } | |
| 1441 | ||
| 1442 | if (coverage_on) { | |
| 1443 | ||
| 1444 | peu_debug_select_a_reg_coverage_group = new(); | |
| 1445 | peu_debug_select_b_reg_coverage_group = new(); | |
| 1446 | peu_control_reg_coverage_group = new(); | |
| 1447 | peu_trn_off_reg_coverage_group = new(); | |
| 1448 | peu_ici_reg_coverage_group = new(); | |
| 1449 | peu_prfc_reg_coverage_group = new(); | |
| 1450 | peu_device_control_reg_coverage_group = new(); | |
| 1451 | peu_diagnostic_reg_coverage_group = new(); | |
| 1452 | peu_link_control_reg_coverage_group = new(); | |
| 1453 | peu_link_status_reg_coverage_group = new(); | |
| 1454 | peu_slot_cap_register_coverage_group = new(); | |
| 1455 | peu_dlpl_dll_control_reg_coverage_group = new(); | |
| 1456 | peu_dlpl_macl_control_reg_coverage_group = new(); | |
| 1457 | peu_dlpl_lane_skew_reg_coverage_group = new(); | |
| 1458 | peu_dlpl_sym_num_reg_coverage_group = new(); | |
| 1459 | peu_dlpl_sym_timer_reg_coverage_group = new(); | |
| 1460 | peu_link_bit_error_counter_I_reg_coverage_group = new(); | |
| 1461 | serdes_pll_csrbus_read_data_coverage_group = new(); | |
| 1462 | peu_ser_receiver_lane_ctl0_reg_coverage_group = new(); | |
| 1463 | peu_ser_receiver_lane_ctl1_reg_coverage_group = new(); | |
| 1464 | peu_ser_receiver_lane_ctl2_reg_coverage_group = new(); | |
| 1465 | peu_ser_receiver_lane_ctl3_reg_coverage_group = new(); | |
| 1466 | peu_ser_receiver_lane_ctl4_reg_coverage_group = new(); | |
| 1467 | peu_ser_receiver_lane_ctl5_reg_coverage_group = new(); | |
| 1468 | peu_ser_receiver_lane_ctl6_reg_coverage_group = new(); | |
| 1469 | peu_ser_receiver_lane_ctl7_reg_coverage_group = new(); | |
| 1470 | peu_ser_xmitter_ctl_lane0_reg_coverage_group = new(); | |
| 1471 | peu_ser_xmitter_ctl_lane1_reg_coverage_group = new(); | |
| 1472 | peu_ser_xmitter_ctl_lane2_reg_coverage_group = new(); | |
| 1473 | peu_ser_xmitter_ctl_lane3_reg_coverage_group = new(); | |
| 1474 | peu_ser_xmitter_ctl_lane4_reg_coverage_group = new(); | |
| 1475 | peu_ser_xmitter_ctl_lane5_reg_coverage_group = new(); | |
| 1476 | peu_ser_xmitter_ctl_lane6_reg_coverage_group = new(); | |
| 1477 | peu_ser_xmitter_ctl_lane7_reg_coverage_group = new(); | |
| 1478 | ||
| 1479 | peu_ser_receiver_status_lane0_reg_coverage_group = new(); | |
| 1480 | peu_ser_receiver_status_lane1_reg_coverage_group = new(); | |
| 1481 | peu_ser_receiver_status_lane2_reg_coverage_group = new(); | |
| 1482 | peu_ser_receiver_status_lane3_reg_coverage_group = new(); | |
| 1483 | peu_ser_receiver_status_lane4_reg_coverage_group = new(); | |
| 1484 | peu_ser_receiver_status_lane5_reg_coverage_group = new(); | |
| 1485 | peu_ser_receiver_status_lane6_reg_coverage_group = new(); | |
| 1486 | peu_ser_receiver_status_lane7_reg_coverage_group = new(); | |
| 1487 | ||
| 1488 | peu_ser_xmitter_status_lane0_reg_coverage_group = new(); | |
| 1489 | peu_ser_xmitter_status_lane1_reg_coverage_group = new(); | |
| 1490 | peu_ser_xmitter_status_lane2_reg_coverage_group = new(); | |
| 1491 | peu_ser_xmitter_status_lane3_reg_coverage_group = new(); | |
| 1492 | peu_ser_xmitter_status_lane4_reg_coverage_group = new(); | |
| 1493 | peu_ser_xmitter_status_lane5_reg_coverage_group = new(); | |
| 1494 | peu_ser_xmitter_status_lane6_reg_coverage_group = new(); | |
| 1495 | peu_ser_xmitter_status_lane7_reg_coverage_group = new(); | |
| 1496 | ||
| 1497 | ||
| 1498 | // RAS | |
| 1499 | peu_oe_log_en_reg_coverage_group = new(); | |
| 1500 | peu_oe_int_en_reg_coverage_group = new(); | |
| 1501 | peu_oe_err_sw_clear_coverage_group = new(); | |
| 1502 | peu_oe_err_sw_set_coverage_group = new(); | |
| 1503 | peu_oe_err_hw_set_coverage_group = new(); | |
| 1504 | ||
| 1505 | peu_ue_log_en_reg_coverage_group = new(); | |
| 1506 | peu_ue_int_en_reg_coverage_group = new(); | |
| 1507 | peu_ue_err_sw_clear_coverage_group = new(); | |
| 1508 | peu_ue_err_sw_set_coverage_group = new(); | |
| 1509 | peu_ue_err_hw_set_coverage_group = new(); | |
| 1510 | ||
| 1511 | peu_ce_log_en_reg_coverage_group = new(); | |
| 1512 | peu_ce_int_en_reg_coverage_group = new(); | |
| 1513 | peu_ce_err_sw_clear_coverage_group = new(); | |
| 1514 | peu_ce_err_sw_set_coverage_group = new(); | |
| 1515 | peu_ce_err_hw_set_coverage_group = new(); | |
| 1516 | ||
| 1517 | peu_event_log_en_reg_coverage_group = new(); | |
| 1518 | peu_event_int_en_reg_coverage_group = new(); | |
| 1519 | peu_event_sw_clear_coverage_group = new(); | |
| 1520 | peu_event_sw_set_coverage_group = new(); | |
| 1521 | peu_event_hw_set_coverage_group = new(); | |
| 1522 | ilu_peu_cov_log_en_reg_coverage_group = new(); | |
| 1523 | ilu_peu_cov_interrupt_coverage_group = new(); | |
| 1524 | ilu_peu_cov_error_status_clear_coverage_group = new(); | |
| 1525 | ilu_peu_cov_error_status_set_coverage_group = new(); | |
| 1526 | ||
| 1527 | ||
| 1528 | // Bit Error count bad | |
| 1529 | peu_bit_error_cnt1_reg_cnt_bad_coverage_group = new(); | |
| 1530 | ||
| 1531 | ||
| 1532 | ilu_peu_cov_ihb_rd_coverage_group = new(); | |
| 1533 | ilu_peu_cov_ihb_wr_coverage_group = new(); | |
| 1534 | ilu_peu_cov_idb_rd_coverage_group = new(); | |
| 1535 | ilu_peu_cov_idb_wr_coverage_group = new(); | |
| 1536 | ilu_peu_cov_ehb_rd_coverage_group = new(); | |
| 1537 | ilu_peu_cov_ehb_wr_coverage_group = new(); | |
| 1538 | ilu_peu_cov_edb_rd_coverage_group = new(); | |
| 1539 | ilu_peu_cov_edb_wr_coverage_group = new(); | |
| 1540 | ilu_peu_cov_pmc_state_coverage_group = new(); | |
| 1541 | ilu_peu_cov_fcsm_state_coverage_group = new(); | |
| 1542 | ilu_peu_cov_ltssm_state_coverage_group = new(); | |
| 1543 | ilu_peu_cov_replay_coverage_group = new(); | |
| 1544 | ilu_peu_cov_retry_buf_rd_coverage_group = new(); | |
| 1545 | ilu_peu_cov_retry_buf_wr_coverage_group = new(); | |
| 1546 | ||
| 1547 | ||
| 1548 | ||
| 1549 | ||
| 1550 | set_cov_cond_bits (); | |
| 1551 | printf("\n\n AC: Coverage turned on for peu_registers objects\n\n"); | |
| 1552 | } | |
| 1553 | ||
| 1554 | } | |
| 1555 | ||
| 1556 | task peu_registers_coverage::set_cov_cond_bits() | |
| 1557 | { | |
| 1558 | fork | |
| 1559 | { | |
| 1560 | ||
| 1561 | { | |
| 1562 | printf("============= AC: at peu_registers.set_cov_cond_bits start\n"); | |
| 1563 | } | |
| 1564 | // setting event trigger for y2k_rcd_enq | |
| 1565 | while (1) | |
| 1566 | { | |
| 1567 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1568 | ||
| 1569 | ||
| 1570 | peu_debug_select_a_reg_var = peu_registers_coverage_ifc.peu_debug_select_a_reg[63:0] ; | |
| 1571 | peu_debug_select_b_reg_var = peu_registers_coverage_ifc.peu_debug_select_b_reg[63:0] ; | |
| 1572 | peu_control_reg_var = peu_registers_coverage_ifc.peu_control_reg[63:0] ; | |
| 1573 | peu_trn_off_reg_var = peu_registers_coverage_ifc.peu_trn_off_reg[63:0] ; | |
| 1574 | peu_ici_reg_var = peu_registers_coverage_ifc.peu_ici_reg[63:0] ; | |
| 1575 | peu_prfc_reg_var = peu_registers_coverage_ifc.peu_prfc_reg[63:0] ; | |
| 1576 | peu_device_control_reg_var = peu_registers_coverage_ifc.peu_device_control_reg[63:0] ; | |
| 1577 | peu_diagnostic_reg_var = peu_registers_coverage_ifc.ilu_diagnos_csrbus_read_data[63:0] ; | |
| 1578 | peu_link_control_reg_var = peu_registers_coverage_ifc.peu_link_control_reg[63:0] ; | |
| 1579 | peu_link_status_reg_var = peu_registers_coverage_ifc.peu_link_status_reg[63:0] ; | |
| 1580 | peu_slot_cap_register_var = peu_registers_coverage_ifc.peu_slot_cap_register[9:0] ; | |
| 1581 | peu_dlpl_dll_control_reg_var = peu_registers_coverage_ifc.peu_dlpl_dll_control_reg[63:0] ; | |
| 1582 | peu_dlpl_macl_control_reg_var = peu_registers_coverage_ifc.peu_dlpl_macl_control_reg[63:0] ; | |
| 1583 | peu_dlpl_lane_skew_reg_var = peu_registers_coverage_ifc.peu_dlpl_lane_skew_reg[63:0] ; | |
| 1584 | peu_dlpl_sym_num_reg_var = peu_registers_coverage_ifc.peu_dlpl_sym_num_reg[63:0] ; | |
| 1585 | peu_dlpl_sym_timer_reg_var = peu_registers_coverage_ifc.peu_dlpl_sym_timer_reg[63:0] ; | |
| 1586 | // peu_dlpl_core_status_reg_var = peu_registers_coverage_ifc.peu_dlpl_core_status_reg[63:0] ; | |
| 1587 | peu_link_bit_error_counter_I_reg_var = peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg[1:0] ; | |
| 1588 | serdes_pll_csrbus_read_data_var = peu_registers_coverage_ifc.serdes_pll_csrbus_read_data[63:0] ; | |
| 1589 | peu_ser_receiver_lane_ctl0_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg[63:0] ; | |
| 1590 | peu_ser_receiver_lane_ctl1_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg[63:0] ; | |
| 1591 | peu_ser_receiver_lane_ctl2_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg[63:0] ; | |
| 1592 | peu_ser_receiver_lane_ctl3_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg[63:0] ; | |
| 1593 | peu_ser_receiver_lane_ctl4_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg[63:0] ; | |
| 1594 | peu_ser_receiver_lane_ctl5_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg[63:0] ; | |
| 1595 | peu_ser_receiver_lane_ctl6_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg[63:0] ; | |
| 1596 | peu_ser_receiver_lane_ctl7_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_ctl0_reg[63:0] ; | |
| 1597 | // peu_ser_receiver_lane_status0_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_lane_status0_reg[63:0] ; | |
| 1598 | peu_ser_xmitter_ctl_lane0_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane0_reg[63:0] ; | |
| 1599 | peu_ser_xmitter_ctl_lane1_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane1_reg[63:0] ; | |
| 1600 | peu_ser_xmitter_ctl_lane2_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane2_reg[63:0] ; | |
| 1601 | peu_ser_xmitter_ctl_lane3_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane3_reg[63:0] ; | |
| 1602 | peu_ser_xmitter_ctl_lane4_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane4_reg[63:0] ; | |
| 1603 | peu_ser_xmitter_ctl_lane5_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane5_reg[63:0] ; | |
| 1604 | peu_ser_xmitter_ctl_lane6_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane6_reg[63:0] ; | |
| 1605 | peu_ser_xmitter_ctl_lane7_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_ctl_lane7_reg[63:0] ; | |
| 1606 | ||
| 1607 | ||
| 1608 | peu_ser_receiver_status_lane0_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_status_lane0_reg[63:0] ; | |
| 1609 | peu_ser_receiver_status_lane1_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_status_lane1_reg[63:0] ; | |
| 1610 | peu_ser_receiver_status_lane2_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_status_lane2_reg[63:0] ; | |
| 1611 | peu_ser_receiver_status_lane3_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_status_lane3_reg[63:0] ; | |
| 1612 | peu_ser_receiver_status_lane4_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_status_lane4_reg[63:0] ; | |
| 1613 | peu_ser_receiver_status_lane5_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_status_lane5_reg[63:0] ; | |
| 1614 | peu_ser_receiver_status_lane6_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_status_lane6_reg[63:0] ; | |
| 1615 | peu_ser_receiver_status_lane7_reg_var = peu_registers_coverage_ifc.peu_ser_receiver_status_lane7_reg[63:0] ; | |
| 1616 | ||
| 1617 | ||
| 1618 | peu_ser_xmitter_status_lane0_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_status_lane0_reg[63:0] ; | |
| 1619 | peu_ser_xmitter_status_lane1_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_status_lane1_reg[63:0] ; | |
| 1620 | peu_ser_xmitter_status_lane2_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_status_lane2_reg[63:0] ; | |
| 1621 | peu_ser_xmitter_status_lane3_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_status_lane3_reg[63:0] ; | |
| 1622 | peu_ser_xmitter_status_lane4_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_status_lane4_reg[63:0] ; | |
| 1623 | peu_ser_xmitter_status_lane5_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_status_lane5_reg[63:0] ; | |
| 1624 | peu_ser_xmitter_status_lane6_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_status_lane6_reg[63:0] ; | |
| 1625 | peu_ser_xmitter_status_lane7_reg_var = peu_registers_coverage_ifc.peu_ser_xmitter_status_lane7_reg[63:0] ; | |
| 1626 | d2p_ihb_addr = ilu_peu_coverage_ihb_rd_coverage_group.d2p_ihb_addr ; | |
| 1627 | it2ih_addr = ilu_peu_coverage_ihb_wr_coverage_group.it2ih_addr ; | |
| 1628 | d2p_idb_addr = ilu_peu_coverage_idb_rd_coverage_group.d2p_idb_addr ; | |
| 1629 | it2id_addr = ilu_peu_coverage_idb_wr_coverage_group.it2id_addr ; | |
| 1630 | et2eh_addr = ilu_peu_coverage_ehb_rd_coverage_group.et2eh_addr ; | |
| 1631 | d2p_ehb_addr = ilu_peu_coverage_ehb_wr_coverage_group.d2p_ehb_addr ; | |
| 1632 | et2ed_addr = ilu_peu_coverage_edb_rd_coverage_group.et2ed_addr ; | |
| 1633 | d2p_edb_addr = ilu_peu_coverage_edb_wr_coverage_group.d2p_edb_addr ; | |
| 1634 | lpm2ctb_pmc_state = ilu_peu_coverage_pmc_state_coverage_group.lpm2ctb_pmc_state ; | |
| 1635 | fc_state = ilu_peu_coverage_fcsm_state_coverage_group.fc_state ; | |
| 1636 | lts_state = ilu_peu_coverage_ltssm_state_coverage_group.lts_state ; | |
| 1637 | replay_num = ilu_peu_coverage_replay_times_coverage_group.replay_num ; | |
| 1638 | rbuf_raddr = ilu_peu_coverage_retry_buf_rd_coverage_group.rbuf_raddr ; | |
| 1639 | rbuf_waddr = ilu_peu_coverage_retry_buf_wr_coverage_group.rbuf_waddr ; | |
| 1640 | ||
| 1641 | ||
| 1642 | ||
| 1643 | } | |
| 1644 | } | |
| 1645 | ||
| 1646 | //====== peu RAS | |
| 1647 | // OE | |
| 1648 | { | |
| 1649 | // trigger oe, ce, ue, event log event | |
| 1650 | while (1) | |
| 1651 | { | |
| 1652 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1653 | peu_oe_log_en_reg_var = peu_registers_coverage_ifc.peu_oe_log_en_reg[23:0]; | |
| 1654 | peu_oe_int_en_reg_var = peu_registers_coverage_ifc.peu_oe_int_en_reg[63:0]; | |
| 1655 | peu_ce_log_en_reg_var = peu_registers_coverage_ifc.peu_ce_log_en_reg[23:0]; | |
| 1656 | peu_ce_int_en_reg_var = peu_registers_coverage_ifc.peu_ce_int_en_reg[63:0]; | |
| 1657 | peu_ue_log_en_reg_var = peu_registers_coverage_ifc.peu_ue_log_en_reg[23:0]; | |
| 1658 | peu_ue_int_en_reg_var = peu_registers_coverage_ifc.peu_ue_int_en_reg[63:0]; | |
| 1659 | ||
| 1660 | peu_event_log_en_reg_var = peu_registers_coverage_ifc.peu_ue_log_en_reg[63:0]; | |
| 1661 | peu_event_int_en_reg_var = peu_registers_coverage_ifc.peu_ue_int_en_reg[63:0]; | |
| 1662 | ||
| 1663 | } // end while | |
| 1664 | } | |
| 1665 | ||
| 1666 | ||
| 1667 | { | |
| 1668 | // trigger oe error events | |
| 1669 | while (1) | |
| 1670 | { | |
| 1671 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1672 | ||
| 1673 | // trigger oe error sw write 1 to clear | |
| 1674 | if (peu_registers_coverage_ifc.peu_oe_err_w_ld && peu_registers_coverage_ifc.peu_oe_err_rw1c) { | |
| 1675 | trigger (oe_err_rw1c_event_trig); | |
| 1676 | } | |
| 1677 | ||
| 1678 | // trigger oe error sw write 1 to set | |
| 1679 | if (peu_registers_coverage_ifc.peu_oe_err_w_ld && peu_registers_coverage_ifc.peu_oe_err_rw1s) { | |
| 1680 | trigger (oe_err_rw1s_event_trig); | |
| 1681 | } | |
| 1682 | ||
| 1683 | } // end while | |
| 1684 | } | |
| 1685 | ||
| 1686 | { | |
| 1687 | // trigger oe hw set event | |
| 1688 | while (1) | |
| 1689 | { | |
| 1690 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1691 | // peu_oe_err_hw_set_var = peu_registers_coverage_ifc.peu_oe_err_hw_set[63:0] ; | |
| 1692 | // if (|(peu_oe_err_hw_set_var) == 1) | |
| 1693 | // if ((peu_oe_err_hw_set_var[63:0]) != 0) | |
| 1694 | if ((peu_registers_coverage_ifc.peu_oe_err_hw_set[63:0]) > 0) { | |
| 1695 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1696 | trigger (peu_oe_err_cycle_afer_hw_set_event_trig); | |
| 1697 | printf("peu_oe_err_cycle_afer_hw_set_event_trig triggered, %0d \n ", get_time(LO)); | |
| 1698 | } | |
| 1699 | ||
| 1700 | } // end while | |
| 1701 | } | |
| 1702 | ||
| 1703 | { | |
| 1704 | // trigger ue error sw set/clear events | |
| 1705 | while (1) | |
| 1706 | { | |
| 1707 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1708 | ||
| 1709 | // trigger ue error sw write 1 to clear | |
| 1710 | if (peu_registers_coverage_ifc.peu_ue_err_w_ld && peu_registers_coverage_ifc.peu_ue_err_rw1c) { | |
| 1711 | trigger (ue_err_rw1c_event_trig); | |
| 1712 | } | |
| 1713 | ||
| 1714 | // trigger ue error sw write 1 to set | |
| 1715 | if (peu_registers_coverage_ifc.peu_ue_err_w_ld && peu_registers_coverage_ifc.peu_ue_err_rw1s) { | |
| 1716 | trigger (ue_err_rw1s_event_trig); | |
| 1717 | } | |
| 1718 | ||
| 1719 | } // end while | |
| 1720 | } | |
| 1721 | ||
| 1722 | { | |
| 1723 | // trigger ue hw set event | |
| 1724 | while (1) | |
| 1725 | { | |
| 1726 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1727 | peu_ue_err_hw_set_var = peu_registers_coverage_ifc.peu_ue_err_hw_set[63:0] ; | |
| 1728 | if (|(peu_ue_err_hw_set_var) == 1) { | |
| 1729 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1730 | trigger (peu_ue_err_cycle_afer_hw_set_event_trig); | |
| 1731 | printf("peu_ue_err_cycle_afer_hw_set_event_trig triggered, %0d \n ", get_time(LO)); | |
| 1732 | } | |
| 1733 | ||
| 1734 | } // end while | |
| 1735 | } | |
| 1736 | ||
| 1737 | ||
| 1738 | { | |
| 1739 | // trigger dlpl error events | |
| 1740 | while (1) | |
| 1741 | { | |
| 1742 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1743 | ||
| 1744 | // trigger dlpl error sw write 1 to clear | |
| 1745 | if (peu_registers_coverage_ifc.peu_event_w_ld && peu_registers_coverage_ifc.peu_event_rw1c) { | |
| 1746 | trigger (peu_event_rw1c_event_trig); | |
| 1747 | } | |
| 1748 | ||
| 1749 | // trigger dlpl error sw write 1 to set | |
| 1750 | if (peu_registers_coverage_ifc.peu_event_w_ld && peu_registers_coverage_ifc.peu_event_rw1s) { | |
| 1751 | trigger (peu_event_rw1s_event_trig); | |
| 1752 | } | |
| 1753 | ||
| 1754 | } // end while | |
| 1755 | } | |
| 1756 | ||
| 1757 | { | |
| 1758 | // trigger dlpl hw set event | |
| 1759 | while (1) | |
| 1760 | { | |
| 1761 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1762 | if ((peu_registers_coverage_ifc.peu_event_hw_set[63:0]) > 0) { | |
| 1763 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1764 | trigger (peu_event_cycle_afer_hw_set_event_trig); | |
| 1765 | printf("peu_event_cycle_afer_hw_set_event_trig triggered, %0d \n ", get_time(LO)); | |
| 1766 | } | |
| 1767 | ||
| 1768 | } // end while | |
| 1769 | } | |
| 1770 | ||
| 1771 | //====== peu serdes receiver lane 0-7 status reg | |
| 1772 | ||
| 1773 | //====== peu Bit error register count bad | |
| 1774 | { | |
| 1775 | while (1) | |
| 1776 | { | |
| 1777 | @(posedge peu_registers_coverage_ifc.peu_clk); | |
| 1778 | if ( peu_registers_coverage_ifc.peu_link_bit_error_counter_I_reg_ber_en ) { | |
| 1779 | trigger (peu_link_bit_error_counter_I_reg_cnt_bad_event_trig); | |
| 1780 | // printf(" peu_link_bit_error_counter_I_reg_cnt_bad_event_trig triggered, %0d \n ", get_time(LO)); | |
| 1781 | } | |
| 1782 | ||
| 1783 | } // end while | |
| 1784 | } | |
| 1785 | ||
| 1786 | { | |
| 1787 | integer edb_wr_last_cycle = 0; | |
| 1788 | while(1) | |
| 1789 | { | |
| 1790 | integer edb_wr_this_cycle = 0; | |
| 1791 | @(posedge ilu_peu_coverage_edb_wr_coverage_group.d2p_edb_clk); | |
| 1792 | if (ilu_peu_coverage_edb_wr_coverage_group.d2p_edb_we === 1'b1) | |
| 1793 | { | |
| 1794 | edb_size++; | |
| 1795 | ||
| 1796 | edb_wr_this_cycle = get_cycle(ilu_peu_coverage_edb_wr_coverage_group.d2p_edb_clk); | |
| 1797 | edb_d_wr_b2b = edb_wr_this_cycle - edb_wr_last_cycle; | |
| 1798 | edb_wr_last_cycle = edb_wr_this_cycle; | |
| 1799 | edb_wr_adr = ilu_peu_coverage_edb_wr_coverage_group.d2p_edb_addr; | |
| 1800 | } | |
| 1801 | } | |
| 1802 | } | |
| 1803 | ||
| 1804 | { | |
| 1805 | integer edb_rd_last_cycle = 0; | |
| 1806 | while(1) | |
| 1807 | { | |
| 1808 | integer edb_rd_this_cycle = 0; | |
| 1809 | @(posedge ilu_peu_coverage_edb_rd_coverage_group.d2p_edb_clk); | |
| 1810 | if (ilu_peu_coverage_edb_rd_coverage_group.et2ed_rd === 1'b1) | |
| 1811 | { | |
| 1812 | edb_size++; | |
| 1813 | ||
| 1814 | edb_rd_this_cycle = get_cycle(ilu_peu_coverage_edb_rd_coverage_group.d2p_edb_clk); | |
| 1815 | edb_d_rd_b2b = edb_rd_this_cycle - edb_rd_last_cycle; | |
| 1816 | edb_rd_last_cycle = edb_rd_this_cycle; | |
| 1817 | edb_rd_adr = ilu_peu_coverage_edb_rd_coverage_group.et2ed_addr; | |
| 1818 | } | |
| 1819 | } | |
| 1820 | } | |
| 1821 | ||
| 1822 | { | |
| 1823 | integer ehb_wr_last_cycle = 0; | |
| 1824 | while(1) | |
| 1825 | { | |
| 1826 | integer ehb_wr_this_cycle = 0; | |
| 1827 | @(posedge ilu_peu_coverage_ehb_wr_coverage_group.d2p_ehb_clk); | |
| 1828 | if (ilu_peu_coverage_ehb_wr_coverage_group.d2p_ehb_we === 1'b1) | |
| 1829 | { | |
| 1830 | ehb_size++; | |
| 1831 | ||
| 1832 | ehb_wr_this_cycle = get_cycle(ilu_peu_coverage_ehb_wr_coverage_group.d2p_ehb_clk); | |
| 1833 | ehb_d_wr_b2b = ehb_wr_this_cycle - ehb_wr_last_cycle; | |
| 1834 | ehb_wr_last_cycle = ehb_wr_this_cycle; | |
| 1835 | ehb_wr_adr = ilu_peu_coverage_ehb_wr_coverage_group.d2p_ehb_addr; | |
| 1836 | } | |
| 1837 | } | |
| 1838 | } | |
| 1839 | ||
| 1840 | { | |
| 1841 | integer ehb_rd_last_cycle = 0; | |
| 1842 | while(1) | |
| 1843 | { | |
| 1844 | integer ehb_rd_this_cycle = 0; | |
| 1845 | @(posedge ilu_peu_coverage_ehb_rd_coverage_group.d2p_ehb_clk); | |
| 1846 | if (ilu_peu_coverage_ehb_rd_coverage_group.et2eh_rd === 1'b1) | |
| 1847 | { | |
| 1848 | ehb_size++; | |
| 1849 | ||
| 1850 | ehb_rd_this_cycle = get_cycle(ilu_peu_coverage_ehb_rd_coverage_group.d2p_ehb_clk); | |
| 1851 | ehb_d_rd_b2b = ehb_rd_this_cycle - ehb_rd_last_cycle; | |
| 1852 | ehb_rd_last_cycle = ehb_rd_this_cycle; | |
| 1853 | ehb_rd_adr = ilu_peu_coverage_ehb_rd_coverage_group.et2eh_addr; | |
| 1854 | } | |
| 1855 | } | |
| 1856 | } | |
| 1857 | ||
| 1858 | { | |
| 1859 | integer idb_wr_last_cycle = 0; | |
| 1860 | while(1) | |
| 1861 | { | |
| 1862 | integer idb_wr_this_cycle = 0; | |
| 1863 | @(posedge ilu_peu_coverage_idb_wr_coverage_group.d2p_idb_clk); | |
| 1864 | if (ilu_peu_coverage_idb_wr_coverage_group.it2id_we === 1'b1) | |
| 1865 | { | |
| 1866 | idb_size++; | |
| 1867 | ||
| 1868 | idb_wr_this_cycle = get_cycle(ilu_peu_coverage_idb_wr_coverage_group.d2p_idb_clk); | |
| 1869 | idb_d_wr_b2b = idb_wr_this_cycle - idb_wr_last_cycle; | |
| 1870 | idb_wr_last_cycle = idb_wr_this_cycle; | |
| 1871 | idb_wr_adr = ilu_peu_coverage_idb_wr_coverage_group.it2id_addr; | |
| 1872 | } | |
| 1873 | } | |
| 1874 | } | |
| 1875 | ||
| 1876 | { | |
| 1877 | integer idb_rd_last_cycle = 0; | |
| 1878 | while(1) | |
| 1879 | { | |
| 1880 | integer idb_rd_this_cycle = 0; | |
| 1881 | @(posedge ilu_peu_coverage_idb_rd_coverage_group.d2p_idb_clk); | |
| 1882 | if (ilu_peu_coverage_idb_rd_coverage_group.d2p_idb_rd === 1'b1) | |
| 1883 | { | |
| 1884 | idb_size++; | |
| 1885 | ||
| 1886 | idb_rd_this_cycle = get_cycle(ilu_peu_coverage_idb_rd_coverage_group.d2p_idb_clk); | |
| 1887 | idb_d_rd_b2b = idb_rd_this_cycle - idb_rd_last_cycle; | |
| 1888 | idb_rd_last_cycle = idb_rd_this_cycle; | |
| 1889 | idb_rd_adr = ilu_peu_coverage_idb_rd_coverage_group.d2p_idb_addr; | |
| 1890 | } | |
| 1891 | } | |
| 1892 | } | |
| 1893 | ||
| 1894 | { | |
| 1895 | integer ihb_wr_last_cycle = 0; | |
| 1896 | while(1) | |
| 1897 | { | |
| 1898 | integer ihb_wr_this_cycle = 0; | |
| 1899 | @(posedge ilu_peu_coverage_ihb_wr_coverage_group.d2p_ihb_clk); | |
| 1900 | if (ilu_peu_coverage_ihb_wr_coverage_group.it2ih_we === 1'b1) | |
| 1901 | { | |
| 1902 | ihb_size++; | |
| 1903 | ||
| 1904 | ihb_wr_this_cycle = get_cycle(ilu_peu_coverage_ihb_wr_coverage_group.d2p_ihb_clk); | |
| 1905 | ihb_d_wr_b2b = ihb_wr_this_cycle - ihb_wr_last_cycle; | |
| 1906 | ihb_wr_last_cycle = ihb_wr_this_cycle; | |
| 1907 | ihb_wr_adr = ilu_peu_coverage_ihb_wr_coverage_group.it2ih_addr; | |
| 1908 | } | |
| 1909 | } | |
| 1910 | } | |
| 1911 | ||
| 1912 | { | |
| 1913 | integer ihb_rd_last_cycle = 0; | |
| 1914 | while(1) | |
| 1915 | { | |
| 1916 | integer ihb_rd_this_cycle = 0; | |
| 1917 | @(posedge ilu_peu_coverage_ihb_rd_coverage_group.d2p_ihb_clk); | |
| 1918 | if (ilu_peu_coverage_ihb_rd_coverage_group.d2p_ihb_rd === 1'b1) | |
| 1919 | { | |
| 1920 | ihb_size++; | |
| 1921 | ||
| 1922 | ihb_rd_this_cycle = get_cycle(ilu_peu_coverage_ihb_rd_coverage_group.d2p_ihb_clk); | |
| 1923 | ihb_d_rd_b2b = ihb_rd_this_cycle - ihb_rd_last_cycle; | |
| 1924 | ihb_rd_last_cycle = ihb_rd_this_cycle; | |
| 1925 | ihb_rd_adr = ilu_peu_coverage_ihb_rd_coverage_group.d2p_ihb_addr; | |
| 1926 | } | |
| 1927 | } | |
| 1928 | } | |
| 1929 | ||
| 1930 | { | |
| 1931 | integer retry_wr_last_cycle = 0; | |
| 1932 | while(1) | |
| 1933 | { | |
| 1934 | integer retry_wr_this_cycle = 0; | |
| 1935 | @(posedge ilu_peu_coverage_retry_buf_wr_coverage_group.core_clk); | |
| 1936 | if (ilu_peu_coverage_retry_buf_wr_coverage_group.xdlh_retryram_we === 1'b1) | |
| 1937 | { | |
| 1938 | rbuf_size++; | |
| 1939 | ||
| 1940 | retry_wr_this_cycle = get_cycle(ilu_peu_coverage_retry_buf_wr_coverage_group.core_clk); | |
| 1941 | rbuf_d_wr_b2b = retry_wr_this_cycle - retry_wr_last_cycle; | |
| 1942 | retry_wr_last_cycle = retry_wr_this_cycle; | |
| 1943 | retry_wr_adr = ilu_peu_coverage_retry_buf_wr_coverage_group.rbuf_waddr; | |
| 1944 | } | |
| 1945 | } | |
| 1946 | } | |
| 1947 | ||
| 1948 | { | |
| 1949 | integer retry_rd_last_cycle = 0; | |
| 1950 | while(1) | |
| 1951 | { | |
| 1952 | integer retry_rd_this_cycle = 0; | |
| 1953 | @(posedge ilu_peu_coverage_retry_buf_rd_coverage_group.core_clk); | |
| 1954 | if (ilu_peu_coverage_retry_buf_rd_coverage_group.xdlh_rbuf_rd === 1'b1) | |
| 1955 | { | |
| 1956 | rbuf_size++; | |
| 1957 | ||
| 1958 | retry_rd_this_cycle = get_cycle(ilu_peu_coverage_retry_buf_rd_coverage_group.core_clk); | |
| 1959 | rbuf_d_rd_b2b = retry_rd_this_cycle - retry_rd_last_cycle; | |
| 1960 | retry_rd_last_cycle = retry_rd_this_cycle; | |
| 1961 | retry_rd_adr = ilu_peu_coverage_retry_buf_rd_coverage_group.rbuf_raddr; | |
| 1962 | } | |
| 1963 | } | |
| 1964 | } | |
| 1965 | ||
| 1966 | ||
| 1967 | join none | |
| 1968 | } // end task | |
| 1969 | ||
| 1970 | ||
| 1971 | ||
| 1972 | ||
| 1973 | ||
| 1974 |