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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ilu_peu_pm_state_sample.vrh | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #define IDLE 4'b0000 | |
36 | #define PM_NAK 4'b0001 | |
37 | #define PM_NAK_WAIT 4'b0010 | |
38 | #define PM_ACK_ASPM_L1 4'b0011 | |
39 | #define PM_ACK_L1 4'b0100 | |
40 | #define PM_ACK_L23 4'b0101 | |
41 | #define PM_TRANS_L0 4'b0110 | |
42 | #define PM_TRANS_L0_ASPM_L1 4'b0111 | |
43 | #define PM_TRANS_L0_L1 4'b1000 | |
44 | #define PM_TRANS_L0_L23 4'b1001 | |
45 | #define PM_TIMEOUT 4'b1010 | |
46 | #define PM_ACK_FLUSH_ASPM_L1 4'b1011 | |
47 | #define PM_ACK_FLUSH_PME_L1 4'b1100 | |
48 | #define PM_ACK_FLUSH_L23 4'b1101 | |
49 | ||
50 | ||
51 | ||
52 | sample ilu_peu_coverage_pmc_state_coverage_group.lpm2ctb_pmc_state | |
53 | { | |
54 | state s_IDLE (IDLE); | |
55 | state s_PM_NAK (PM_NAK); | |
56 | state s_PM_NAK_WAIT (PM_NAK_WAIT); | |
57 | state s_PM_ACK_ASPM_L1 (PM_ACK_ASPM_L1); | |
58 | state s_PM_ACK_L1 (PM_ACK_L1); | |
59 | state s_PM_ACK_L23 (PM_ACK_L23); | |
60 | state s_PM_TRANS_L0 (PM_TRANS_L0); | |
61 | state s_PM_TRANS_L0_ASPM_L1 (PM_TRANS_L0_ASPM_L1); | |
62 | state s_PM_TRANS_L0_L1 (PM_TRANS_L0_L1); | |
63 | state s_PM_TRANS_L0_L23 (PM_TRANS_L0_L23); | |
64 | state s_PM_TIMEOUT (PM_TIMEOUT); | |
65 | state s_PM_ACK_FLUSH_ASPM_L1 (PM_ACK_FLUSH_ASPM_L1); | |
66 | state s_PM_ACK_FLUSH_PME_L1 (PM_ACK_FLUSH_PME_L1); | |
67 | state s_PM_ACK_FLUSH_L23 (PM_ACK_FLUSH_L23); | |
68 | ||
69 | // trans t_IDLE_IDLE_01 (IDLE -> IDLE); | |
70 | trans t_IDLE_PM_TRANS_L0_02 (IDLE -> PM_TRANS_L0); | |
71 | // trans t_IDLE_PM_TIMEOUT_03 (IDLE -> PM_TIMEOUT); | |
72 | // trans t_IDLE_PM_ACK_L1_04 (IDLE -> PM_ACK_L1); | |
73 | // trans t_IDLE_PM_ACK_L23_05 (IDLE -> PM_ACK_L23); | |
74 | // trans t_IDLE_PM_NAK_06 (IDLE -> PM_NAK); | |
75 | // trans t_IDLE_PM_ACK_ASPM_L1_07 (IDLE -> PM_ACK_ASPM_L1); | |
76 | trans t_PM_NAK_PM_NAK_WAIT_03 (PM_NAK -> PM_NAK_WAIT); | |
77 | // trans t_PM_NAK_PM_NAK_04 (PM_NAK -> PM_NAK); | |
78 | ||
79 | trans t_PM_NAK_WAIT_IDLE_05 (PM_NAK_WAIT -> IDLE); | |
80 | // trans t_PM_NAK_WAIT_PM_NAK_WAIT_06 (PM_NAK_WAIT -> PM_NAK_WAIT); | |
81 | trans t_PM_ACK_ASPM_L1_PM_TRANS_L0_ASPM_L1_07 (PM_ACK_ASPM_L1 -> PM_TRANS_L0_ASPM_L1); | |
82 | trans t_PM_ACK_ASPM_L1_IDLE_08 (PM_ACK_ASPM_L1 -> IDLE); | |
83 | // trans t_PM_ACK_ASPM_L1_PM_ACK_ASPM_L1_09 (PM_ACK_ASPM_L1 -> PM_ACK_ASPM_L1); | |
84 | trans t_PM_ACK_ASPM_L1_PM_ACK_FLUSH_ASPM_L1 (PM_ACK_ASPM_L1 -> PM_ACK_FLUSH_ASPM_L1); | |
85 | trans t_PM_ACK_L1_PM_TRANS_L0_L1_10 (PM_ACK_L1 -> PM_TRANS_L0_L1); | |
86 | trans t_PM_ACK_L1_IDLE_11 (PM_ACK_L1 -> IDLE); | |
87 | // trans t_PM_ACK_L1_PM_ACK_L1_12 (PM_ACK_L1 -> PM_ACK_L1); | |
88 | trans t_PM_ACK_L23_PM_TRANS_L0_L23_13 (PM_ACK_L23 -> PM_TRANS_L0_L23); | |
89 | // trans t_PM_ACK_L23_IDLE_14 (PM_ACK_L23 -> IDLE); | |
90 | // trans t_PM_ACK_L23_PM_ACK_L23_15 (PM_ACK_L23 -> PM_ACK_L23); | |
91 | trans t_PM_TRANS_L0_IDLE_16 (PM_TRANS_L0 -> IDLE ); | |
92 | // trans t_PM_TRANS_L0_PM_TRANS_L0_17 (PM_TRANS_L0 -> PM_TRANS_L0 ); | |
93 | trans t_PM_TRANS_L0_ASPM_L1_PM_ACK_ASPM_L1_18 (PM_TRANS_L0_ASPM_L1 -> PM_ACK_ASPM_L1); | |
94 | // trans t_PM_TRANS_L0_ASPM_L1_PM_TRANS_L0_ASPM_L1_19 (PM_TRANS_L0_ASPM_L1 -> PM_TRANS_L0_ASPM_L1); | |
95 | trans t_PM_TRANS_L0_L1_PM_ACK_L1_20 (PM_TRANS_L0_L1 -> PM_ACK_L1); | |
96 | // trans t_PM_TRANS_L0_L1_PM_TRANS_L0_L1_21 (PM_TRANS_L0_L1 -> PM_TRANS_L0_L1); | |
97 | trans t_PM_TRANS_L0_L23_PM_ACK_L23_22 (PM_TRANS_L0_L23 -> PM_ACK_L23); | |
98 | // trans t_PM_TRANS_L0_L23_PM_TRANS_L0_L23_23 (PM_TRANS_L0_L23 -> PM_TRANS_L0_L23); | |
99 | trans t_PM_TIMEOUT_IDLE_24 (PM_TIMEOUT -> IDLE); | |
100 | // trans t_PM_TIMEOUT_PM_TIMEOUT_25 (PM_TIMEOUT -> PM_TIMEOUT); | |
101 | trans t_PM_ACK_FLUSH_ASPM_L1_IDLE_26 (PM_ACK_FLUSH_ASPM_L1 -> IDLE); | |
102 | trans t_PM_ACK_FLUSH_PME_L1_IDLE_27 (PM_ACK_FLUSH_PME_L1 -> IDLE); | |
103 | trans t_PM_ACK_FLUSH_L23_IDLE_28 (PM_ACK_FLUSH_L23 -> IDLE); | |
104 | ||
105 | } |