projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: l2_error_offmode_sample.vrhpal | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | wildcard state LOAD_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 36 | wildcard state LOAD_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 37 | ||
| 38 | // PREFETCH off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 39 | wildcard state PREFETCH_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); | |
| 40 | wildcard state PREFETCH_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); | |
| 41 | ||
| 42 | // IMISS off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 43 | wildcard state IMISS_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 44 | wildcard state IMISS_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 45 | ||
| 46 | // STORE off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 47 | wildcard state STORE_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 48 | wildcard state STORE_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 49 | ||
| 50 | // BLKSTORE off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 51 | wildcard state BLKSTORE_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); | |
| 52 | wildcard state BLKSTORE_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); | |
| 53 | ||
| 54 | // BLKINITST off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 55 | wildcard state BLKINITST_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); | |
| 56 | wildcard state BLKINITST_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); | |
| 57 | ||
| 58 | // CAS1 off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 59 | wildcard state CAS1_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 60 | wildcard state CAS1_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 61 | ||
| 62 | // SWAP off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 63 | wildcard state SWAP_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 64 | wildcard state SWAP_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 65 | ||
| 66 | // STRLOAD off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 67 | wildcard state STRLOAD_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 68 | wildcard state STRLOAD_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 69 | ||
| 70 | // STRST off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 71 | wildcard state STRST_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 72 | wildcard state STRST_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 73 | /* | |
| 74 | // FWDRQ_LOAD off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 75 | wildcard state FWDRQ_LOAD_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 76 | wildcard state FWDRQ_LOAD_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 77 | ||
| 78 | // FWDRQ_STORE off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 79 | wildcard state FWDRQ_STORE_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 80 | wildcard state FWDRQ_STORE_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); | |
| 81 | */ | |
| 82 | ||
| 83 | // PREFETCH_ICE off ue,ce fbhit vld diag reqtype nc jbi cputh inv pf bis | |
| 84 | wildcard state PFICE_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} ); | |
| 85 | wildcard state PFICE_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} ); | |
| 86 | ||
| 87 | // RDD off ue,ce fbhit vld diag reqtype nc jbi | |
| 88 | wildcard state RDD_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); | |
| 89 | wildcard state RDD_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); | |
| 90 | ||
| 91 | // WR8 off ue,ce fbhit vld diag reqtype nc jbi | |
| 92 | wildcard state WR8_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); | |
| 93 | wildcard state WR8_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); | |
| 94 | ||
| 95 | // WRI does not make a DRAM read request and does not hit the FB | |
| 96 | // WRI off ue,ce fbhit vld diag reqtype nc jbi | |
| 97 | //wildcard state WRI_ue( {1'b1, 2'b1x, 1'b1, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); | |
| 98 | //wildcard state WRI_ce( {1'b1, 2'bx1, 1'b1, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); |