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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_error_tag_sample.vrhpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2_error_tag_sample.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
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13// This program is distributed in the hope that it will be useful,
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16// GNU General Public License for more details.
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35wildcard state LOAD_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
36wildcard state LOAD_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
37wildcard state LOAD_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
38wildcard state LOAD_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
39
40// PREFETCH vld diag pst2 reqtype nc jbi cputh inv pf bis
41wildcard state PREFETCH_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
42wildcard state PREFETCH_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
43wildcard state PREFETCH_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
44wildcard state PREFETCH_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
45
46// IMISS vld diag pst2 reqtype nc jbi cputh inv pf bis
47wildcard state IMISS_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
48wildcard state IMISS_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
49wildcard state IMISS_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
50wildcard state IMISS_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
51
52// STORE vld diag pst2 reqtype nc jbi cputh inv pf bis
53wildcard state STORE_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
54wildcard state STORE_report ( {4'b00x1, 1'b1, 1'b0, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
55wildcard state STORE_schedule( {4'b0001, 1'b1, 1'b0, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
56wildcard state STORE_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
57
58// STORE (partial, 2nd pass) vld diag pst2 reqtype nc jbi cputh inv pf bis
59wildcard state STOREpst2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b1, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
60wildcard state STOREpst2_report ( {4'b00x1, 1'b1, 1'b0, 1'b1, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
61wildcard state STOREpst2_schedule( {4'b0001, 1'b1, 1'b0, 1'b1, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
62wildcard state STOREpst2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b1, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
63
64// BLKSTORE vld diag pst2 reqtype nc jbi cputh inv pf bis
65wildcard state BLKSTORE_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
66wildcard state BLKSTORE_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
67wildcard state BLKSTORE_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
68wildcard state BLKSTORE_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
69
70// BLKINITST vld diag pst2 reqtype nc jbi cputh inv pf bis
71wildcard state BLKINITST_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
72wildcard state BLKINITST_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
73wildcard state BLKINITST_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
74wildcard state BLKINITST_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
75
76// CAS1 vld diag pst2 reqtype nc jbi cputh inv pf bis
77wildcard state CAS1_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
78wildcard state CAS1_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
79wildcard state CAS1_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
80wildcard state CAS1_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
81
82// CAS2 vld diag pst2 reqtype nc jbi cputh inv pf bis
83wildcard state CAS2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
84wildcard state CAS2_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
85wildcard state CAS2_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
86wildcard state CAS2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
87
88// SWAP vld diag pst2 reqtype nc jbi cputh inv pf bis
89wildcard state SWAP_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
90wildcard state SWAP_report ( {4'b00x1, 1'b1, 1'b0, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
91wildcard state SWAP_schedule( {4'b0001, 1'b1, 1'b0, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
92wildcard state SWAP_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
93
94// SWAP (partial, 2nd pass) vld diag pst2 reqtype nc jbi cputh inv pf bis
95wildcard state SWAPpst2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b1, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
96wildcard state SWAPpst2_report ( {4'b00x1, 1'b1, 1'b0, 1'b1, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
97wildcard state SWAPpst2_schedule( {4'b0001, 1'b1, 1'b0, 1'b1, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
98wildcard state SWAPpst2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b1, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
99
100// STRLOAD vld diag pst2 reqtype nc jbi cputh inv pf bis
101wildcard state STRLOAD_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
102wildcard state STRLOAD_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
103wildcard state STRLOAD_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
104wildcard state STRLOAD_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
105
106// STRST vld diag pst2 reqtype nc jbi cputh inv pf bis
107wildcard state STRST_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
108wildcard state STRST_report ( {4'b00x1, 1'b1, 1'b0, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
109wildcard state STRST_schedule( {4'b0001, 1'b1, 1'b0, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
110wildcard state STRST_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
111
112// STRST (partial, 2nd pass) vld diag pst2 reqtype nc jbi cputh inv pf bis
113wildcard state STRSTpst2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b1, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
114wildcard state STRSTpst2_report ( {4'b00x1, 1'b1, 1'b0, 1'b1, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
115wildcard state STRSTpst2_schedule( {4'b0001, 1'b1, 1'b0, 1'b1, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
116wildcard state STRSTpst2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b1, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
117
118/*
119// FWDRQ_LOAD vld diag pst2 reqtype nc jbi cputh inv pf bis
120wildcard state FWDRQ_LOAD_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
121wildcard state FWDRQ_LOAD_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
122wildcard state FWDRQ_LOAD_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
123wildcard state FWDRQ_LOAD_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
124
125// FWDRQ_STORE vld diag pst2 reqtype nc jbi cputh inv pf bis
126wildcard state FWDRQ_STORE_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
127wildcard state FWDRQ_STORE_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
128wildcard state FWDRQ_STORE_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
129wildcard state FWDRQ_STORE_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
130*/
131
132// PREFETCH_ICE vld diag pst2 reqtype nc jbi cputh inv pf bis
133wildcard state PFICE_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
134wildcard state PFICE_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
135wildcard state PFICE_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
136wildcard state PFICE_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} );
137
138// RDD vld diag pst2 reqtype nc jbi
139wildcard state RDD_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, 5'bxx001, 1'b0, 1'b1, 9'bx} );
140wildcard state RDD_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, 5'bxx001, 1'b0, 1'b1, 9'bx} );
141wildcard state RDD_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, 5'bxx001, 1'b0, 1'b1, 9'bx} );
142wildcard state RDD_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, 5'bxx001, 1'b0, 1'b1, 9'bx} );
143
144// WR8 vld diag pst2 reqtype nc jbi
145wildcard state WR8_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
146wildcard state WR8_report ( {4'b00x1, 1'b1, 1'b0, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
147wildcard state WR8_schedule( {4'b0001, 1'b1, 1'b0, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
148wildcard state WR8_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
149
150// WR8 (partial, 2nd pass) vld diag pst2 reqtype nc jbi
151wildcard state WR8pst2_detect ( {4'bx0x1, 1'b1, 1'b0, 1'b1, 5'bxx010, 1'b0, 1'b1, 9'bx} );
152wildcard state WR8pst2_report ( {4'b00x1, 1'b1, 1'b0, 1'b1, 5'bxx010, 1'b0, 1'b1, 9'bx} );
153wildcard state WR8pst2_schedule( {4'b0001, 1'b1, 1'b0, 1'b1, 5'bxx010, 1'b0, 1'b1, 9'bx} );
154wildcard state WR8pst2_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'b1, 5'bxx010, 1'b0, 1'b1, 9'bx} );
155
156// WRI vld diag pst2 reqtype nc jbi
157wildcard state WRI_detect ( {4'bx0x1, 1'b1, 1'b0, 1'bx, 5'bxx100, 1'b0, 1'b1, 9'bx} );
158wildcard state WRI_report ( {4'b00x1, 1'b1, 1'b0, 1'bx, 5'bxx100, 1'b0, 1'b1, 9'bx} );
159wildcard state WRI_schedule( {4'b0001, 1'b1, 1'b0, 1'bx, 5'bxx100, 1'b0, 1'b1, 9'bx} );
160wildcard state WRI_scrub ( {4'bx1xx, 1'b1, 1'b0, 1'bx, 5'bxx100, 1'b0, 1'b1, 9'bx} );
Full OpenSPARC design & verification tarball including full HDL.