Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_fc_error_allbankerror_sample.vrhpal

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// OpenSPARC T2 Processor File: l2_fc_error_allbankerror_sample.vrhpal
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#ifdef L2_INTF_COV

sample l2_fc_err_allbankerrtype_allbank0_sample   (l2_ras_intf.l2t0_cpx_data[136:134])
  {
     state s_L2_CPX_TYPE_1 (3'b000);
     state s_L2_CPX_TYPE_2 (3'b001);
     state s_L2_CPX_TYPE_3 (3'b010);
     state s_L2_CPX_TYPE_4 (3'b011);
     state s_L2_CPX_TYPE_5 (3'b100);
     state s_L2_CPX_TYPE_6 (3'b101);
     state s_L2_CPX_TYPE_7 (3'b110);
     state s_L2_CPX_TYPE_8 (3'b111);
  }

sample l2_fc_err_allbankerrtype_allbank1_sample   (l2_ras_intf.l2t1_cpx_data[136:134])
  {
     state s_L2_CPX_TYPE_1 (3'b000);
     state s_L2_CPX_TYPE_2 (3'b001);
     state s_L2_CPX_TYPE_3 (3'b010);
     state s_L2_CPX_TYPE_4 (3'b011);
     state s_L2_CPX_TYPE_5 (3'b100);
     state s_L2_CPX_TYPE_6 (3'b101);
     state s_L2_CPX_TYPE_7 (3'b110);
     state s_L2_CPX_TYPE_8 (3'b111);
  }

sample l2_fc_err_allbankerrtype_allbank2_sample   (l2_ras_intf.l2t2_cpx_data[136:134])
  {
     state s_L2_CPX_TYPE_1 (3'b000);
     state s_L2_CPX_TYPE_2 (3'b001);
     state s_L2_CPX_TYPE_3 (3'b010);
     state s_L2_CPX_TYPE_4 (3'b011);
     state s_L2_CPX_TYPE_5 (3'b100);
     state s_L2_CPX_TYPE_6 (3'b101);
     state s_L2_CPX_TYPE_7 (3'b110);
     state s_L2_CPX_TYPE_8 (3'b111);
  }

sample l2_fc_err_allbankerrtype_allbank3_sample   (l2_ras_intf.l2t3_cpx_data[136:134])
  {
     state s_L2_CPX_TYPE_1 (3'b000);
     state s_L2_CPX_TYPE_2 (3'b001);
     state s_L2_CPX_TYPE_3 (3'b010);
     state s_L2_CPX_TYPE_4 (3'b011);
     state s_L2_CPX_TYPE_5 (3'b100);
     state s_L2_CPX_TYPE_6 (3'b101);
     state s_L2_CPX_TYPE_7 (3'b110);
     state s_L2_CPX_TYPE_8 (3'b111);
  }

sample l2_fc_err_allbankerrtype_allbank4_sample   (l2_ras_intf.l2t4_cpx_data[136:134])
  {
     state s_L2_CPX_TYPE_1 (3'b000);
     state s_L2_CPX_TYPE_2 (3'b001);
     state s_L2_CPX_TYPE_3 (3'b010);
     state s_L2_CPX_TYPE_4 (3'b011);
     state s_L2_CPX_TYPE_5 (3'b100);
     state s_L2_CPX_TYPE_6 (3'b101);
     state s_L2_CPX_TYPE_7 (3'b110);
     state s_L2_CPX_TYPE_8 (3'b111);
  }

sample l2_fc_err_allbankerrtype_allbank5_sample   (l2_ras_intf.l2t5_cpx_data[136:134])
  {
     state s_L2_CPX_TYPE_1 (3'b000);
     state s_L2_CPX_TYPE_2 (3'b001);
     state s_L2_CPX_TYPE_3 (3'b010);
     state s_L2_CPX_TYPE_4 (3'b011);
     state s_L2_CPX_TYPE_5 (3'b100);
     state s_L2_CPX_TYPE_6 (3'b101);
     state s_L2_CPX_TYPE_7 (3'b110);
     state s_L2_CPX_TYPE_8 (3'b111);
  }

sample l2_fc_err_allbankerrtype_allbank6_sample   (l2_ras_intf.l2t6_cpx_data[136:134])
  {
     state s_L2_CPX_TYPE_1 (3'b000);
     state s_L2_CPX_TYPE_2 (3'b001);
     state s_L2_CPX_TYPE_3 (3'b010);
     state s_L2_CPX_TYPE_4 (3'b011);
     state s_L2_CPX_TYPE_5 (3'b100);
     state s_L2_CPX_TYPE_6 (3'b101);
     state s_L2_CPX_TYPE_7 (3'b110);
     state s_L2_CPX_TYPE_8 (3'b111);
  }

sample l2_fc_err_allbankerrtype_allbank7_sample   (l2_ras_intf.l2t7_cpx_data[136:134])
  {
     state s_L2_CPX_TYPE_1 (3'b000);
     state s_L2_CPX_TYPE_2 (3'b001);
     state s_L2_CPX_TYPE_3 (3'b010);
     state s_L2_CPX_TYPE_4 (3'b011);
     state s_L2_CPX_TYPE_5 (3'b100);
     state s_L2_CPX_TYPE_6 (3'b101);
     state s_L2_CPX_TYPE_7 (3'b110);
     state s_L2_CPX_TYPE_8 (3'b111);
  }

#endif