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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2sat_cov.if.vrhpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2sat_cov.if.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef __L2SAT_COV_IF_VRH__
36#define __L2SAT_COV_IF_VRH__
37
38#include <vera_defines.vrh>
39#inc "l2sat_cov_inc.pal"
40
41#define OUTPUT_EDGE PHOLD
42#define OUTPUT_SKEW #3
43#define INPUT_EDGE PSAMPLE
44#define INPUT_SKEW #-3
45
46
47
48interface l2sat_coverage_ifc
49{
50 // Common & Clock Signals
51 // This clock declaration allows referencing "l2sat_coverage_ifc.clock"
52
53#ifdef FC_COVERAGE
54 input clock CLOCK verilog_node "`TOP.cpu.l2t0.gclk";
55 input reset INPUT_EDGE INPUT_SKEW verilog_node "`TOP.reset";
56#else
57 input clock CLOCK verilog_node "l2sat_top.clock";
58 input reset INPUT_EDGE INPUT_SKEW verilog_node "l2sat_top.reset";
59#endif
60
61 input cmp_diag_done PSAMPLE;
62
63 //for l2sat_ccx_cpx_req_samp
64 input [7:0] spc7_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc7_pcx_req_pq";
65 input [7:0] spc6_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc6_pcx_req_pq";
66 input [7:0] spc5_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc5_pcx_req_pq";
67 input [7:0] spc4_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc4_pcx_req_pq";
68 input [7:0] spc3_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc3_pcx_req_pq";
69 input [7:0] spc2_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc2_pcx_req_pq";
70 input [7:0] spc1_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc1_pcx_req_pq";
71 input [7:0] spc0_pcx_req PSAMPLE #-3 verilog_node "$CCX_PATH.spc0_pcx_req_pq";
72
73 input [7:0] spc7_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d1";
74 input [7:0] spc7_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d2";
75 input [7:0] spc7_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d3";
76 input [7:0] spc7_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d4";
77 input [7:0] spc7_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d5";
78 input [7:0] spc7_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d6";
79 input [7:0] spc7_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d7";
80 input [7:0] spc7_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d8";
81 input [7:0] spc7_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d9";
82 input [7:0] spc7_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_req_d10";
83 input [7:0] spc6_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d1";
84 input [7:0] spc6_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d2";
85 input [7:0] spc6_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d3";
86 input [7:0] spc6_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d4";
87 input [7:0] spc6_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d5";
88 input [7:0] spc6_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d6";
89 input [7:0] spc6_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d7";
90 input [7:0] spc6_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d8";
91 input [7:0] spc6_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d9";
92 input [7:0] spc6_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_req_d10";
93 input [7:0] spc5_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d1";
94 input [7:0] spc5_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d2";
95 input [7:0] spc5_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d3";
96 input [7:0] spc5_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d4";
97 input [7:0] spc5_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d5";
98 input [7:0] spc5_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d6";
99 input [7:0] spc5_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d7";
100 input [7:0] spc5_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d8";
101 input [7:0] spc5_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d9";
102 input [7:0] spc5_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_req_d10";
103 input [7:0] spc4_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d1";
104 input [7:0] spc4_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d2";
105 input [7:0] spc4_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d3";
106 input [7:0] spc4_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d4";
107 input [7:0] spc4_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d5";
108 input [7:0] spc4_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d6";
109 input [7:0] spc4_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d7";
110 input [7:0] spc4_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d8";
111 input [7:0] spc4_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d9";
112 input [7:0] spc4_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_req_d10";
113 input [7:0] spc3_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d1";
114 input [7:0] spc3_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d2";
115 input [7:0] spc3_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d3";
116 input [7:0] spc3_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d4";
117 input [7:0] spc3_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d5";
118 input [7:0] spc3_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d6";
119 input [7:0] spc3_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d7";
120 input [7:0] spc3_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d8";
121 input [7:0] spc3_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d9";
122 input [7:0] spc3_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_req_d10";
123 input [7:0] spc2_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d1";
124 input [7:0] spc2_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d2";
125 input [7:0] spc2_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d3";
126 input [7:0] spc2_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d4";
127 input [7:0] spc2_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d5";
128 input [7:0] spc2_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d6";
129 input [7:0] spc2_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d7";
130 input [7:0] spc2_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d8";
131 input [7:0] spc2_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d9";
132 input [7:0] spc2_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_req_d10";
133 input [7:0] spc1_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d1";
134 input [7:0] spc1_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d2";
135 input [7:0] spc1_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d3";
136 input [7:0] spc1_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d4";
137 input [7:0] spc1_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d5";
138 input [7:0] spc1_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d6";
139 input [7:0] spc1_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d7";
140 input [7:0] spc1_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d8";
141 input [7:0] spc1_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d9";
142 input [7:0] spc1_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_req_d10";
143 input [7:0] spc0_pcx_req_d1 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d1";
144 input [7:0] spc0_pcx_req_d2 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d2";
145 input [7:0] spc0_pcx_req_d3 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d3";
146 input [7:0] spc0_pcx_req_d4 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d4";
147 input [7:0] spc0_pcx_req_d5 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d5";
148 input [7:0] spc0_pcx_req_d6 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d6";
149 input [7:0] spc0_pcx_req_d7 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d7";
150 input [7:0] spc0_pcx_req_d8 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d8";
151 input [7:0] spc0_pcx_req_d9 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d9";
152 input [7:0] spc0_pcx_req_d10 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_req_d10";
153
154 input [7:0] spc7_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d1";
155 input [7:0] spc7_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d2";
156 input [7:0] spc7_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d3";
157 input [7:0] spc7_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d4";
158 input [7:0] spc7_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d5";
159 input [7:0] spc7_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d6";
160 input [7:0] spc7_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d7";
161 input [7:0] spc7_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d8";
162 input [7:0] spc7_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d9";
163 input [7:0] spc7_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc7_pcx_atm_d10";
164 input [7:0] spc6_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d1";
165 input [7:0] spc6_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d2";
166 input [7:0] spc6_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d3";
167 input [7:0] spc6_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d4";
168 input [7:0] spc6_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d5";
169 input [7:0] spc6_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d6";
170 input [7:0] spc6_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d7";
171 input [7:0] spc6_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d8";
172 input [7:0] spc6_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d9";
173 input [7:0] spc6_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc6_pcx_atm_d10";
174 input [7:0] spc5_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d1";
175 input [7:0] spc5_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d2";
176 input [7:0] spc5_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d3";
177 input [7:0] spc5_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d4";
178 input [7:0] spc5_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d5";
179 input [7:0] spc5_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d6";
180 input [7:0] spc5_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d7";
181 input [7:0] spc5_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d8";
182 input [7:0] spc5_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d9";
183 input [7:0] spc5_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc5_pcx_atm_d10";
184 input [7:0] spc4_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d1";
185 input [7:0] spc4_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d2";
186 input [7:0] spc4_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d3";
187 input [7:0] spc4_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d4";
188 input [7:0] spc4_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d5";
189 input [7:0] spc4_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d6";
190 input [7:0] spc4_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d7";
191 input [7:0] spc4_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d8";
192 input [7:0] spc4_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d9";
193 input [7:0] spc4_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc4_pcx_atm_d10";
194 input [7:0] spc3_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d1";
195 input [7:0] spc3_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d2";
196 input [7:0] spc3_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d3";
197 input [7:0] spc3_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d4";
198 input [7:0] spc3_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d5";
199 input [7:0] spc3_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d6";
200 input [7:0] spc3_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d7";
201 input [7:0] spc3_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d8";
202 input [7:0] spc3_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d9";
203 input [7:0] spc3_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc3_pcx_atm_d10";
204 input [7:0] spc2_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d1";
205 input [7:0] spc2_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d2";
206 input [7:0] spc2_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d3";
207 input [7:0] spc2_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d4";
208 input [7:0] spc2_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d5";
209 input [7:0] spc2_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d6";
210 input [7:0] spc2_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d7";
211 input [7:0] spc2_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d8";
212 input [7:0] spc2_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d9";
213 input [7:0] spc2_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc2_pcx_atm_d10";
214 input [7:0] spc1_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d1";
215 input [7:0] spc1_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d2";
216 input [7:0] spc1_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d3";
217 input [7:0] spc1_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d4";
218 input [7:0] spc1_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d5";
219 input [7:0] spc1_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d6";
220 input [7:0] spc1_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d7";
221 input [7:0] spc1_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d8";
222 input [7:0] spc1_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d9";
223 input [7:0] spc1_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc1_pcx_atm_d10";
224 input [7:0] spc0_pcx_atm_d1 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d1";
225 input [7:0] spc0_pcx_atm_d2 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d2";
226 input [7:0] spc0_pcx_atm_d3 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d3";
227 input [7:0] spc0_pcx_atm_d4 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d4";
228 input [7:0] spc0_pcx_atm_d5 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d5";
229 input [7:0] spc0_pcx_atm_d6 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d6";
230 input [7:0] spc0_pcx_atm_d7 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d7";
231 input [7:0] spc0_pcx_atm_d8 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d8";
232 input [7:0] spc0_pcx_atm_d9 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d9";
233 input [7:0] spc0_pcx_atm_d10 PSAMPLE #-3 verilog_node "`TOP.spc0_pcx_atm_d10";
234
235 input [7:0] l2t7_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_req_d1";
236 input [7:0] l2t7_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_req_d2";
237 input [7:0] l2t7_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_req_d3";
238 input [7:0] l2t7_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_req_d4";
239 input [7:0] l2t6_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_req_d1";
240 input [7:0] l2t6_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_req_d2";
241 input [7:0] l2t6_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_req_d3";
242 input [7:0] l2t6_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_req_d4";
243 input [7:0] l2t5_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_req_d1";
244 input [7:0] l2t5_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_req_d2";
245 input [7:0] l2t5_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_req_d3";
246 input [7:0] l2t5_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_req_d4";
247 input [7:0] l2t4_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_req_d1";
248 input [7:0] l2t4_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_req_d2";
249 input [7:0] l2t4_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_req_d3";
250 input [7:0] l2t4_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_req_d4";
251 input [7:0] l2t3_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_req_d1";
252 input [7:0] l2t3_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_req_d2";
253 input [7:0] l2t3_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_req_d3";
254 input [7:0] l2t3_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_req_d4";
255 input [7:0] l2t2_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_req_d1";
256 input [7:0] l2t2_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_req_d2";
257 input [7:0] l2t2_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_req_d3";
258 input [7:0] l2t2_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_req_d4";
259 input [7:0] l2t1_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_req_d1";
260 input [7:0] l2t1_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_req_d2";
261 input [7:0] l2t1_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_req_d3";
262 input [7:0] l2t1_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_req_d4";
263 input [7:0] l2t0_cpx_req_d1 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_req_d1";
264 input [7:0] l2t0_cpx_req_d2 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_req_d2";
265 input [7:0] l2t0_cpx_req_d3 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_req_d3";
266 input [7:0] l2t0_cpx_req_d4 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_req_d4";
267
268 input [7:0] l2t7_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_atom_d1";
269 input [7:0] l2t7_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_atom_d2";
270 input [7:0] l2t7_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_atom_d3";
271 input [7:0] l2t7_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t7_cpx_atom_d4";
272 input [7:0] l2t6_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_atom_d1";
273 input [7:0] l2t6_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_atom_d2";
274 input [7:0] l2t6_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_atom_d3";
275 input [7:0] l2t6_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t6_cpx_atom_d4";
276 input [7:0] l2t5_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_atom_d1";
277 input [7:0] l2t5_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_atom_d2";
278 input [7:0] l2t5_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_atom_d3";
279 input [7:0] l2t5_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t5_cpx_atom_d4";
280 input [7:0] l2t4_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_atom_d1";
281 input [7:0] l2t4_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_atom_d2";
282 input [7:0] l2t4_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_atom_d3";
283 input [7:0] l2t4_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t4_cpx_atom_d4";
284 input [7:0] l2t3_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_atom_d1";
285 input [7:0] l2t3_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_atom_d2";
286 input [7:0] l2t3_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_atom_d3";
287 input [7:0] l2t3_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t3_cpx_atom_d4";
288 input [7:0] l2t2_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_atom_d1";
289 input [7:0] l2t2_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_atom_d2";
290 input [7:0] l2t2_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_atom_d3";
291 input [7:0] l2t2_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t2_cpx_atom_d4";
292 input [7:0] l2t1_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_atom_d1";
293 input [7:0] l2t1_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_atom_d2";
294 input [7:0] l2t1_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_atom_d3";
295 input [7:0] l2t1_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t1_cpx_atom_d4";
296 input [7:0] l2t0_cpx_atom_d1 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_atom_d1";
297 input [7:0] l2t0_cpx_atom_d2 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_atom_d2";
298 input [7:0] l2t0_cpx_atom_d3 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_atom_d3";
299 input [7:0] l2t0_cpx_atom_d4 PSAMPLE #-3 verilog_node "`TOP.l2t0_cpx_atom_d4";
300
301 input [7:0] spc7_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc7_pcx_atm_pq";
302 input [7:0] spc6_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc6_pcx_atm_pq";
303 input [7:0] spc5_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc5_pcx_atm_pq";
304 input [7:0] spc4_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc4_pcx_atm_pq";
305 input [7:0] spc3_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc3_pcx_atm_pq";
306 input [7:0] spc2_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc2_pcx_atm_pq";
307 input [7:0] spc1_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc1_pcx_atm_pq";
308 input [7:0] spc0_pcx_atm PSAMPLE #-3 verilog_node "$CCX_PATH.spc0_pcx_atm_pq";
309
310
311 //for l2sat_ccx_cpx_req_samp
312 input [7:0] l2t7_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag7_cpx_req_cq";
313 input [7:0] l2t6_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag6_cpx_req_cq";
314 input [7:0] l2t5_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag5_cpx_req_cq";
315 input [7:0] l2t4_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag4_cpx_req_cq";
316 input [7:0] l2t3_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag3_cpx_req_cq";
317 input [7:0] l2t2_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag2_cpx_req_cq";
318 input [7:0] l2t1_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag1_cpx_req_cq";
319 input [7:0] l2t0_cpx_req PSAMPLE #-3 verilog_node "$CCX_PATH.sctag0_cpx_req_cq";
320
321 input l2t7_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag7_cpx_atom_cq";
322 input l2t6_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag6_cpx_atom_cq";
323 input l2t5_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag5_cpx_atom_cq";
324 input l2t4_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag4_cpx_atom_cq";
325 input l2t3_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag3_cpx_atom_cq";
326 input l2t2_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag2_cpx_atom_cq";
327 input l2t1_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag1_cpx_atom_cq";
328 input l2t0_cpx_atom PSAMPLE #-3 verilog_node "$CCX_PATH.sctag0_cpx_atom_cq";
329
330
331 //for l2sat_ccx_pcx_sequence_samp
332 input [7:0] pcx_spc0_grant PSAMPLE #-3 verilog_node "$CCX_PATH.pcx_spc0_grant_px";
333
334
335 //for l2sat_ccx_pcx_qfull_samp
336 input [7:0] pcx_arb7_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl7.arc.qfull_a";
337 input [7:0] pcx_arb6_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl6.arc.qfull_a";
338 input [7:0] pcx_arb5_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl5.arc.qfull_a";
339 input [7:0] pcx_arb4_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl4.arc.qfull_a";
340 input [7:0] pcx_arb3_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl3.arc.qfull_a";
341 input [7:0] pcx_arb2_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl2.arc.qfull_a";
342 input [7:0] pcx_arb1_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl1.arc.qfull_a";
343 input [7:0] pcx_arb0_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl0.arc.qfull_a";
344
345
346 //for l2sat_ccx_cpx_qfull_samp
347 input [7:0] cpx_arb7_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl7.arc.qfull_a";
348 input [7:0] cpx_arb6_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl6.arc.qfull_a";
349 input [7:0] cpx_arb5_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl5.arc.qfull_a";
350 input [7:0] cpx_arb4_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl4.arc.qfull_a";
351 input [7:0] cpx_arb3_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl3.arc.qfull_a";
352 input [7:0] cpx_arb2_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl2.arc.qfull_a";
353 input [7:0] cpx_arb1_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl1.arc.qfull_a";
354 input [7:0] cpx_arb0_qfull PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl0.arc.qfull_a";
355
356
357 //for l2sat_ccx_pcx_stallatom_samp
358 input [7:0] pcx_arb0_atom PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl0.ard.atom";
359 input [7:0] pcx_arb0_grant_a PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl0.ard.grant_a";
360 input pcx_arb0_stall_a_ PSAMPLE #-3 verilog_node "$CCX_PATH.pcx.pcx_arbl0.ard.stall_a_";
361
362
363 //for l2sat_ccx_cpx_stallatom_samp
364 input [7:0] cpx_arb0_atom PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl0.ard.atom";
365 input [7:0] cpx_arb0_grant_a PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl0.ard.grant_a";
366 input cpx_arb0_stall_a_ PSAMPLE #-3 verilog_node "$CCX_PATH.cpx.cpx_arbl0.ard.stall_a_";
367
368
369
370 //////////////////////////////
371 // L2 interface objects
372 //////////////////////////////
373
374 //for l2_pcx_fields_samp
375 input pcx_l2t0_data_rdy PSAMPLE #-3 verilog_node "$L2T_PATH[0].iqu.pcx_l2t_data_rdy_px1_fnl";
376 input [129:0] pcx_l2t0_data PSAMPLE #-3 verilog_node "$L2T_PATH[0].pcx_l2t_data_px2";
377
378
379 //for l2_cpx_fields_samp
380 input [145:0] l2t0_cpx_data PSAMPLE #-3 verilog_node "$L2T_PATH[0].l2t_cpx_data_ca";
381
382 // no new signals needed for l2_cpx_fields_samp (l2t0_cpx_data)
383
384 //for l2_siu_fields_samp
385 input sii_l2t0_req_vld PSAMPLE #-3 verilog_node "$L2T_PATH[0].sii_l2t_req_vld";
386 input sii_l2t1_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t1.sii_l2t_req_vld";
387 input sii_l2t2_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t2.sii_l2t_req_vld";
388 input sii_l2t3_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t3.sii_l2t_req_vld";
389 input sii_l2t4_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t4.sii_l2t_req_vld";
390 input sii_l2t5_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t5.sii_l2t_req_vld";
391 input sii_l2t6_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t6.sii_l2t_req_vld";
392 input sii_l2t7_req_vld PSAMPLE #-3 verilog_node "`TOP.cpu.l2t7.sii_l2t_req_vld";
393 input [31:0] sii_l2t0_req PSAMPLE #-3 verilog_node "$L2T_PATH[0].sii_l2t_req";
394 input [31:0] sii_l2t1_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t1.sii_l2t_req";
395 input [31:0] sii_l2t2_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t2.sii_l2t_req";
396 input [31:0] sii_l2t3_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t3.sii_l2t_req";
397 input [31:0] sii_l2t4_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t4.sii_l2t_req";
398 input [31:0] sii_l2t5_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t5.sii_l2t_req";
399 input [31:0] sii_l2t6_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t6.sii_l2t_req";
400 input [31:0] sii_l2t7_req PSAMPLE #-3 verilog_node "`TOP.cpu.l2t7.sii_l2t_req";
401 input [5:0] sii_l2b0_ecc PSAMPLE #-3 verilog_node "$L2B_PATH[0].sii_l2b_ecc";
402
403//#ifdef SIU_INTF_COV
404//
405 // input [31:0] sii_l2t0_req_pkt PSAMPLE #-3 verilog_node "$L2T_PATH[0].sii_l2t_req";
406 // input [31:0] sii_l2t1_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t1.sii_l2t_req";
407 // input [31:0] sii_l2t2_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t2.sii_l2t_req";
408 // input [31:0] sii_l2t3_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t3.sii_l2t_req";
409 // input [31:0] sii_l2t4_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t4.sii_l2t_req";
410 // input [31:0] sii_l2t5_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t5.sii_l2t_req";
411 // input [31:0] sii_l2t6_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t6.sii_l2t_req";
412 // input [31:0] sii_l2t7_req_pkt PSAMPLE #-3 verilog_node "`TOP.cpu.l2t7.sii_l2t_req";
413
414//#endif
415
416
417
418
419
420 //for l2sat_addr_samp
421 input arbctl_inst_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_vld_c2";
422 input arbctl_inst_diag_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_diag_c2";
423 input arbctl_inval_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inval_inst_c2";
424 input arb_decdp_inst_int_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_decdp_inst_int_c2";
425 input [39:0] arbdp_addr_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbadr.arbdp_addr_c2";
426
427
428 //for l2_iq_count_samp
429 input [4:0] iq_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].iqu.que_cnt";
430
431
432 //for l2_oq_count_samp
433 input [4:0] oq_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].oqu.oq_count_p";
434
435
436 //for l2_oq_fill12_samp
437 input imiss1_to_xbarq_c6_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].oqu.imiss1_to_xbarq_c6";
438 input sel_old_req_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].oqu.sel_old_req";
439
440
441 //for l2_dir_write_samp
442 input ic_wr_en_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_ic_wr_en_c4";
443 input [4:0] dir_panel_icd_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.dir_panel_icd_c4";
444 input [4:0] wr_ic_dir_entry_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.dirrep_wr_ic_dir_entry_c4";
445 input dc_wr_en_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_dc_wr_en_c4";
446 input [4:0] dir_panel_dcd_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.dir_panel_dcd_c4";
447 input [4:0] wr_dc_dir_entry_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_wr_dc_dir_entry_c4";
448
449
450 //for l2_dir_lookup_samp
451 input [3:0] ic_lkup_row_dec_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_ic_lkup_row_dec_c4";
452 input [2:0] lkup_row_addr_icd_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.lkup_row_addr_icd_c4";
453 input [3:0] dc_lkup_row_dec_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep_dc_lkup_row_dec_c4";
454 input [2:0] lkup_row_addr_dcd_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].dirrep.lkup_row_addr_dcd_c4";
455
456
457 //for l2_mb_count_samp
458 input [5:0] mb_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.mb_count_c4";
459
460
461 //for l2_mb_sameindex_samp
462 input [5:0] mb_sameindex_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.hit_count_c4";
463
464
465 //for l2_mb_hit_bypass_samp
466 input mbctl_hit_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.misbuf_hit_c2";
467 input tmp_hit_unqual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.tmp_hit_unqual_c2";
468 input tmp_cam_hit_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.tmp_cam_hit_c2";
469 input mbf_insert_c3_tmp_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.mbf_insert_c3_tmp";
470 input [15:0] cam_hit_vec_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.cam_hit_vec_c1";
471
472
473 //for l2_fb_count_samp
474 input [3:0] fb_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fb_count";
475
476
477 //for l2_fbmb_miss_entries_samp
478 input fbf_ready_miss_r1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_fbf_ready_miss_r1";
479 input [2:0] dram_rd_req_id_r0_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.mcu_rd_req_id_r0_d1";
480 input [4:0] fbf_enc_ld_mbid_r1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_fbf_enc_ld_mbid_r1";
481
482
483 //for l2_fbmb_stdep_entries_samp
484 input fbf_st_or_dep_rdy_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_fbf_st_or_dep_rdy_c4";
485 input [7:0] fill_complete_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fill_complete_c4";
486 input [4:0] fbf_enc_dep_mbid_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_fbf_enc_dep_mbid_c4";
487
488
489 //for l2_fb_bypass_entries_samp
490 input fbctl_hit_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_hit_c2";
491 input [7:0] fb_hit_vec_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fb_hit_vec_c2";
492
493
494 //for l2_fb_bypass_insts_samp
495 input [40:0] arbdp_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbdec.arbdp_inst_c2";
496
497
498 //for l2_fill_complete_samp
499 input [7:0] dec_fill_entry_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.dec_fill_entry_c3";
500 input [7:0] no_fill_entry_dequeue_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.no_fill_entry_dequeue_c3";
501 input en_hit_dequeue_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.en_hit_dequeue_c2";
502 input rdma_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.rdma_inst_c2";
503 input mbctl_rdma_reg_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.tag_misbuf_rdma_reg_vld_c2";
504
505
506 //for l2_wb_count_samp
507 input [3:0] wb_count_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wb_count";
508
509
510 //for l2_wb_hit_bypass_samp
511 input wbctl_hit_qual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wbuf_hit_qual_c2";
512 input bypass_hit_en_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.bypass_hit_en_c2";
513 input [7:0] wb_cam_hit_vec_tmp_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wb_cam_hit_vec_tmp_c2";
514
515
516 //for l2_snpiq_valid_samp
517 input [1:0] snpq_valid_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].snp.snpq_valid";
518
519
520 //for l2_rdmawb_valid_samp
521 input [3:0] rdma_valid_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].rdmat.rdma_valid";
522
523
524 //for l2_pipeline_full_samp
525 input arbctl_inst_vld_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_vld_c1";
526
527
528 //for l2_stalled_insts1_samp
529 input same_col_stall_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.same_col_stall_c1";
530 input imiss_stall_op_c1inc1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.imiss_stall_op_c1inc1";
531 input arbctl_evict_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_evict_vld_c2";
532 input arbctl_fill_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_fill_vld_c2";
533 input arbctl_fill_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_fill_vld_c3";
534 input rdma_64B_stall_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.rdma_64B_stall";
535 //input arbctl_inval_inst_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].
536 input inval_inst_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inval_inst_vld_c3";
537 input inval_inst_vld_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inval_inst_vld_c4";
538 input ic_inval_vld_c5_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ic_inval_vld_c5";
539 input ic_inval_vld_c52_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ic_inval_vld_c52";
540 input ic_inval_vld_c6_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ic_inval_vld_c6";
541 input arb_ic_inval_vld_c7_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_ic_inval_vld_c7";
542 input inst_l2data_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2data_vld_c2";
543 input inst_l2tag_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2tag_vld_c2";
544 input inst_l2tag_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2tag_vld_c3";
545 input inst_l2vuad_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2vuad_vld_c2";
546 input inst_l2vuad_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2vuad_vld_c3";
547 input inst_l2vuad_vld_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inst_l2vuad_vld_c4";
548 input inc_tag_ecc_cnt_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inc_tag_ecc_cnt_c2";
549 input inc_tag_ecc_cnt_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.inc_tag_ecc_cnt_c3";
550 input data_ecc_active_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.data_ecc_active_c4";
551 input arbctl_inst_diag_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_diag_c1";
552 input [33:0] arbdp_inst_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbdec.arbdp_inst_c1";
553
554
555 //for l2_stalled_insts2_samp
556 input arbdp_evict_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arbdec_arbdp_evict_c1";
557 input arbdp_inst_fb_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arbdec_arbdp_inst_fb_c1";
558 input decdp_imiss_inst_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.decdp_imiss_inst_c1";
559 input decdp_ic_inval_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.decdp_ic_inval_c1";
560 input decdp_dc_inval_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.decdp_dc_inval_c1";
561 input arbdp_tecc_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arbdec_arbdp_tecc_c1";
562 input arbdp_inst_rsvd_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arbdec_arbdp_inst_rsvd_c1";
563 input arbctl_stall_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_stall_c2";
564
565
566 //for l2_vuad_bypass_samp
567 input vuad_sel_c2orc3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vuad.vuaddp_vuad_sel_c2orc3";
568 input vuad_sel_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vuad.vuaddp_vuad_sel_c2";
569 input vuad_sel_c4orc5_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vuad.vuad_sel_c4orc5";
570 input vuad_sel_c4_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vuad.vuaddp_vuad_sel_c4";
571
572
573 //for l2_offmode_directmap_insts_samp
574 input l2_bypass_mode_on_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.l2_bypass_mode_on_d1";
575 input l2_dir_map_on_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagdp.l2_dir_map_on_d1";
576
577
578 //for l2_inst_flow_samp
579 input tagctl_hit_l2orfb_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.tag_hit_l2orfb_c2";
580 //input mbctl_hit_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.misbuf_hit_c2";
581 input arbdp_inst_mb_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbdec.arbdec_arbdp_inst_mb_c2";
582 //input arbctl_evict_vld_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_evict_vld_c2";
583
584
585 //for l2_buffer_hits_samp
586 input fbctl_mbctl_match_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.filbuf_misbuf_match_c2";
587 //input wbctl_hit_qual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wbuf_hit_qual_c2";
588 input rdmatctl_hit_qual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].rdmat.rdma_hit_qual_c2";
589
590
591 //for l2_error_status_reg_samp
592 input [63:0] err_state_new_c9_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csreg.err_state_new_c9";
593 input [63:0] err_status_in_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csreg.err_status_in";
594
595 //for l2_notdata_error_reg_samp
596 input [1:0] err_state_notdata_new_c9_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csreg.err_state_notdata_new_c9";
597 input [1:0] err_status_notdata_in_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csreg.err_status_notdata_in";
598
599 //for l2_two_successive_errors_samp
600 input [47:0] csr_l2_notdata_reg_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csr.csr_l2_notdata_reg";
601
602 //for l2_dir/tag/data_scrub_cov
603 input [10:0] dir_addr_cnt_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.dir_addr_cnt_c3";
604 input [7:0] tecc_st_cnt_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.tecc_st_cnt";
605 input [3:0] arb_tecc_way_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_tecc_way_c2";
606 input [8:0] arbadr_data_ecc_idx_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arbadr.arbadr_data_ecc_idx";
607
608
609 //for l2_error_trans_samp
610 input [63:0] csr_l2_errstate_reg_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].csr.csr_l2_errstate_reg";
611
612
613 //for l2_error_tag_samp
614 input tecc_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.arb_tecc_c2";
615 input par_err_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagdp.par_err_c2";
616 input arbdp_pst_with_ctrue_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_arbdp_pst_with_ctrue_c2";
617
618
619 //for l2_error_offmode_samp
620 input fbuerr0_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fbuerr0_d1";
621 input fbcerr0_d1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fbcerr0_d1";
622
623 //for l2_error_vuad_ce_samp
624 input vlddir_valid_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vlddir.valid_c2";
625 input vlddir_valid_corr_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].vlddir.valid_corr_c2";
626 input l2t_l2d_way_sel_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].l2t_l2d_way_sel_c2";
627 input tag_hit_unqual_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tag_hit_unqual_c2";
628 input arb_vuad_ce_err_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.arb_vuad_ce_err_c2_qual";
629
630 //for l2sat_partial_corebank_coverage_group
631 input ncu_l2t_pm_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_pm";
632 input ncu_l2t_ba01_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_ba01";
633 input ncu_l2t_ba23_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_ba23";
634 input ncu_l2t_ba45_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_ba45";
635 input ncu_l2t_ba67_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_l2t_ba67";
636 input ncu_spc0_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc0_core_enable_status";
637 input ncu_spc1_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc1_core_enable_status";
638 input ncu_spc2_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc2_core_enable_status";
639 input ncu_spc3_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc3_core_enable_status";
640 input ncu_spc4_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc4_core_enable_status";
641 input ncu_spc5_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc5_core_enable_status";
642 input ncu_spc6_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc6_core_enable_status";
643 input ncu_spc7_core_enable_status_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].ncu_spc7_core_enable_status";
644
645 //for l2_pipeline_arbiter_cov
646 input mbf_valid_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.mbf_valid_px2";
647 input fbf_valid_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.fbf_valid_px2_1";
648 input snp_valid_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.snp_valid_px2";
649 //input atm_instr_c1_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.atm_instr_c1";
650 input ique_iq_arb_atm_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.ique_iq_arb_atm_px2";
651 input arb_stall_c2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_stall_c2";
652 //input iqsel_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.iqsel_px2";
653 input iqu_iq_arb_vld_px2_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.iqu_iq_arb_vld_px2";
654
655 //for l2_fb_wb_iowb_cam_results_cov
656 input [7:0] fb_cam_match PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fb_cam_match";
657 input [7:0] fb_valid PSAMPLE #-3 verilog_node "$L2T_PATH[0].filbuf.fb_valid";
658 input [7:0] wb_cam_match_c2 PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wb_cam_match_c2";
659 input [7:0] wb_valid PSAMPLE #-3 verilog_node "$L2T_PATH[0].wbuf.wb_valid";
660 input [3:0] rdmat_cam_match_c2 PSAMPLE #-3 verilog_node "$L2T_PATH[0].rdmat.rdmat_cam_match_c2";
661 input [3:0] rdma_valid PSAMPLE #-3 verilog_node "$L2T_PATH[0].rdmat.rdma_valid";
662
663 //for l2_store_pipelining_cov
664 input arbctl_inst_vld_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_inst_vld_c3";
665 input arb_decdp_st_inst_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].arb.arb_decdp_st_inst_c3";
666 input misbuf_dep_inst_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.misbuf_dep_inst_c3";
667 input mbf_insert_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.mbf_insert_c3_tmp";
668 input tag_hit_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].tagctl.tag_hit_c3";
669 input arb_vuad_ce_err_c3_0 PSAMPLE #-3 verilog_node "$L2T_PATH[0].misbuf.arb_vuad_ce_err_c3";
670
671
672}
673// ******************************************************************************************************
674// Interface for l2 & SIU internal coverage obj for FC
675// ******************************************************************************************************
676interface l2_siu_ccx_intf {
677
678#ifdef FC_COVERAGE
679 input clk CLOCK verilog_node "`TOP.cpu.l2t0.gclk";
680#else
681 input clk CLOCK verilog_node "l2sat_top.clock";
682#endif
683
684 input [7:0] sctag0_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag0_cpx_req_cq";
685 input [7:0] sctag1_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag1_cpx_req_cq";
686 input [7:0] sctag2_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag2_cpx_req_cq";
687 input [7:0] sctag3_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag3_cpx_req_cq";
688 input [7:0] sctag4_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag4_cpx_req_cq";
689 input [7:0] sctag5_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag5_cpx_req_cq";
690 input [7:0] sctag6_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag6_cpx_req_cq";
691 input [7:0] sctag7_cpx_req_cq INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.sctag7_cpx_req_cq";
692 input l2b0_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b0_sio_ctag_vld";
693 input l2b1_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b1_sio_ctag_vld";
694 input l2b2_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b2_sio_ctag_vld";
695 input l2b3_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b3_sio_ctag_vld";
696 input l2b4_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b4_sio_ctag_vld";
697 input l2b5_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b5_sio_ctag_vld";
698 input l2b6_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b6_sio_ctag_vld";
699 input l2b7_sio_ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.l2b7_sio_ctag_vld";
700}
701// ******************************************************************************************************
702
703// ******************************************************************************************************
704// Interface for l2 RAS coverage obj for FC
705// ******************************************************************************************************
706interface l2_ras_intf {
707
708 input clk CLOCK verilog_node "`TOP.cpu.l2t0.gclk";
709
710 input [145:0] l2t0_cpx_data PSAMPLE #-3 verilog_node "$L2T_PATH[0].l2t_cpx_data_ca";
711 input [145:0] l2t1_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t1.l2t_cpx_data_ca";
712 input [145:0] l2t2_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t2.l2t_cpx_data_ca";
713 input [145:0] l2t3_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t3.l2t_cpx_data_ca";
714 input [145:0] l2t4_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t4.l2t_cpx_data_ca";
715 input [145:0] l2t5_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t5.l2t_cpx_data_ca";
716 input [145:0] l2t6_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t6.l2t_cpx_data_ca";
717 input [145:0] l2t7_cpx_data PSAMPLE #-3 verilog_node "`TOP.cpu.l2t7.l2t_cpx_data_ca";
718
719}
720// ******************************************************************************************************
721
722
723#endif
Full OpenSPARC design & verification tarball including full HDL.