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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2sat_coverage.vrpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #include <vera_defines.vrh> | |
36 | #include <ListMacros.vrh> | |
37 | #include "plusArgMacros.vri" | |
38 | #include "std_display_class.vrh" | |
39 | #include "std_display_defines.vri" | |
40 | #include "l2sat_defines.vrh" | |
41 | ||
42 | #include "l2sat_cov_ports_binds.vrh" | |
43 | #include "l2sat_cov.if.vrh" | |
44 | ||
45 | class l2sat_intf_coverage_class | |
46 | { | |
47 | // for dispmon | |
48 | StandardDisplay dbg; | |
49 | local string myname; | |
50 | ||
51 | event l2t0_cpx_error_pkt1_evnt_trig; | |
52 | event l2t0_cpx_error_pkt4_evnt_trig; | |
53 | event l2t0_cpx_error_pkt5_evnt_trig; | |
54 | event l2t0_cpx_error_bank0_evnt_trig; | |
55 | event l2t0_cpx_error_bank1_evnt_trig; | |
56 | event l2t0_cpx_error_bank2_evnt_trig; | |
57 | event l2t0_cpx_error_bank3_evnt_trig; | |
58 | event l2t0_cpx_error_bank4_evnt_trig; | |
59 | event l2t0_cpx_error_bank5_evnt_trig; | |
60 | event l2t0_cpx_error_bank6_evnt_trig; | |
61 | event l2t0_cpx_error_bank7_evnt_trig; | |
62 | event l2t0_cpx_anybank_error_evnt_trig; | |
63 | event l2t0_cpx_error_bank2_thread_evnt_trig; | |
64 | event l2t0_cpx_error_bank3_thread_evnt_trig; | |
65 | event l2t0_cpx_error_bank4_thread_evnt_trig; | |
66 | event l2t0_cpx_error_bank5_thread_evnt_trig; | |
67 | event l2t0_cpx_error_bank6_thread_evnt_trig; | |
68 | event l2t0_cpx_error_bank7_thread_evnt_trig; | |
69 | event l2t0_cpx_error_bank8_thread_evnt_trig; | |
70 | event l2t0_cpx_bank_error_evnt_trig; | |
71 | ||
72 | ||
73 | ||
74 | bit l2sat_intf_cov_debug; | |
75 | ||
76 | ||
77 | //variables that misc_cov triggers through the object handle | |
78 | bit l2_iq_cas12_samp_trigger; | |
79 | bit [13:0] l2_atomic_store_samp_trigger; | |
80 | bit [2:0] l2_pst1_dataerr_pst2_tagerr_samp_trigger; | |
81 | bit [19:0] l2_error_vuad_ecc_samp_trigger; | |
82 | bit l2_single_pcx_WRI_same_addr_samp_trigger; | |
83 | bit l2_double_pcx_WRI_same_addr_samp_trigger; | |
84 | bit l2_single_pcx_WR8_same_addr_samp_trigger; | |
85 | bit l2_double_pcx_WR8_same_addr_samp_trigger; | |
86 | bit l2_single_pcx_RDD_same_addr_samp_trigger; | |
87 | bit l2_double_pcx_RDD_same_addr_samp_trigger; | |
88 | bit l2_single_pcx_WRI_diff_addr_samp_trigger; | |
89 | bit l2_double_pcx_WRI_diff_addr_samp_trigger; | |
90 | bit l2_single_pcx_WR8_diff_addr_samp_trigger; | |
91 | bit l2_double_pcx_WR8_diff_addr_samp_trigger; | |
92 | bit l2_single_pcx_RDD_diff_addr_samp_trigger; | |
93 | bit l2_double_pcx_RDD_diff_addr_samp_trigger; | |
94 | ||
95 | bit pcx_l2t_atm_px2; | |
96 | bit pcx_l2t_data_rdy_px2; | |
97 | ||
98 | bit [1:0] l2t0_type1; | |
99 | bit [1:0] l2t0_type2; | |
100 | bit [1:0] l2t0_type3; | |
101 | bit [1:0] l2t0_type4; | |
102 | bit [1:0] l2t0_type5; | |
103 | bit [1:0] l2t0_bank0; | |
104 | bit [1:0] l2t0_bank1; | |
105 | bit [1:0] l2t0_bank2; | |
106 | bit [1:0] l2t0_bank3; | |
107 | bit [1:0] l2t0_bank4; | |
108 | bit [1:0] l2t0_bank5; | |
109 | bit [1:0] l2t0_bank6; | |
110 | bit [1:0] l2t0_bank7; | |
111 | ||
112 | . for ($bank=0; $bank<8; $bank++) | |
113 | . { | |
114 | bit [1:0] l2t${bank}_thread1; | |
115 | bit [1:0] l2t${bank}_thread2; | |
116 | bit [1:0] l2t${bank}_thread3; | |
117 | bit [1:0] l2t${bank}_thread4; | |
118 | bit [1:0] l2t${bank}_thread5; | |
119 | bit [1:0] l2t${bank}_thread6; | |
120 | bit [1:0] l2t${bank}_thread7; | |
121 | bit [1:0] l2t${bank}_thread8; | |
122 | . } | |
123 | ||
124 | bit [7:0] error_bits ; | |
125 | bit [7:0] thread_bits ; | |
126 | ||
127 | integer counter = 0; | |
128 | integer counter_2 = 0; | |
129 | integer counter_3 = 0; | |
130 | integer counter_4 = 0; | |
131 | integer counter_5 = 0; | |
132 | integer counter_6 = 0; | |
133 | integer counter_7 = 0; | |
134 | integer error_counter = 0; | |
135 | integer start_count = 0; | |
136 | integer counter_bank0 ; | |
137 | integer counter_bank1 ; | |
138 | integer counter_bank2 ; | |
139 | integer counter_bank3 ; | |
140 | integer counter_bank4 ; | |
141 | integer counter_bank5 ; | |
142 | integer counter_bank6 ; | |
143 | integer counter_bank7 ; | |
144 | integer counter_2bank ; | |
145 | integer counter_3bank ; | |
146 | integer counter_4bank ; | |
147 | integer counter_5bank ; | |
148 | integer counter_6bank ; | |
149 | integer counter_7bank ; | |
150 | integer counter_8bank ; | |
151 | ||
152 | ||
153 | ||
154 | // ----------- coverage_group ---------------- | |
155 | ||
156 | coverage_group l2sat_ccx_coverage_group | |
157 | { | |
158 | sample_event = @(posedge CLOCK); | |
159 | ||
160 | ////////////////////////////////// | |
161 | // CCX interface coverages | |
162 | ////////////////////////////////// | |
163 | ||
164 | sample ccxl2_intf_pcx_req_cov ({l2sat_coverage_ifc.spc7_pcx_req, l2sat_coverage_ifc.spc6_pcx_req, | |
165 | l2sat_coverage_ifc.spc5_pcx_req, l2sat_coverage_ifc.spc4_pcx_req, | |
166 | l2sat_coverage_ifc.spc3_pcx_req, l2sat_coverage_ifc.spc2_pcx_req, | |
167 | l2sat_coverage_ifc.spc1_pcx_req, l2sat_coverage_ifc.spc0_pcx_req, | |
168 | l2sat_coverage_ifc.spc7_pcx_atm, l2sat_coverage_ifc.spc6_pcx_atm, | |
169 | l2sat_coverage_ifc.spc5_pcx_atm, l2sat_coverage_ifc.spc4_pcx_atm, | |
170 | l2sat_coverage_ifc.spc3_pcx_atm, l2sat_coverage_ifc.spc2_pcx_atm, | |
171 | l2sat_coverage_ifc.spc1_pcx_atm, l2sat_coverage_ifc.spc0_pcx_atm}) { | |
172 | // {spc7_pcx_req[7:0], ... , spc0_pcx_req[7:0], | |
173 | // spc7_pcx_atom[7:0], ... , spc0_pcx_atom[7:0]} | |
174 | #inc "ccx_pcx_req_sample.vrhpal"; | |
175 | } | |
176 | ||
177 | sample ccxl2_intf_cpx_req_cov ({l2sat_coverage_ifc.l2t7_cpx_req, l2sat_coverage_ifc.l2t6_cpx_req, | |
178 | l2sat_coverage_ifc.l2t5_cpx_req, l2sat_coverage_ifc.l2t4_cpx_req, | |
179 | l2sat_coverage_ifc.l2t3_cpx_req, l2sat_coverage_ifc.l2t2_cpx_req, | |
180 | l2sat_coverage_ifc.l2t1_cpx_req, l2sat_coverage_ifc.l2t0_cpx_req, | |
181 | l2sat_coverage_ifc.l2t7_cpx_atom, l2sat_coverage_ifc.l2t6_cpx_atom, | |
182 | l2sat_coverage_ifc.l2t5_cpx_atom, l2sat_coverage_ifc.l2t4_cpx_atom, | |
183 | l2sat_coverage_ifc.l2t3_cpx_atom, l2sat_coverage_ifc.l2t2_cpx_atom, | |
184 | l2sat_coverage_ifc.l2t1_cpx_atom, l2sat_coverage_ifc.l2t0_cpx_atom}) { | |
185 | // {l2t7_cpx_req[7:0], ... , l2t0_cpx_req[7:0], | |
186 | // l2t7_cpx_atom, ... , l2t0_cpx_atom} | |
187 | #inc "ccx_cpx_req_sample.vrhpal"; | |
188 | } | |
189 | ||
190 | #ifdef L2_INTF_COV | |
191 | sample ccxl2_intf_pcx_req_window_cov ({l2sat_coverage_ifc.spc7_pcx_req_d1 || l2sat_coverage_ifc.spc7_pcx_req_d2 || l2sat_coverage_ifc.spc7_pcx_req_d3 || l2sat_coverage_ifc.spc7_pcx_req_d4, | |
192 | l2sat_coverage_ifc.spc6_pcx_req_d1 || l2sat_coverage_ifc.spc6_pcx_req_d2 || l2sat_coverage_ifc.spc6_pcx_req_d3 || l2sat_coverage_ifc.spc6_pcx_req_d4, | |
193 | l2sat_coverage_ifc.spc5_pcx_req_d1 || l2sat_coverage_ifc.spc5_pcx_req_d2 || l2sat_coverage_ifc.spc5_pcx_req_d3 || l2sat_coverage_ifc.spc5_pcx_req_d4, | |
194 | l2sat_coverage_ifc.spc4_pcx_req_d1 || l2sat_coverage_ifc.spc4_pcx_req_d2 || l2sat_coverage_ifc.spc4_pcx_req_d3 || l2sat_coverage_ifc.spc4_pcx_req_d4, | |
195 | l2sat_coverage_ifc.spc3_pcx_req_d1 || l2sat_coverage_ifc.spc3_pcx_req_d2 || l2sat_coverage_ifc.spc3_pcx_req_d3 || l2sat_coverage_ifc.spc3_pcx_req_d4, | |
196 | l2sat_coverage_ifc.spc2_pcx_req_d1 || l2sat_coverage_ifc.spc2_pcx_req_d2 || l2sat_coverage_ifc.spc2_pcx_req_d3 || l2sat_coverage_ifc.spc2_pcx_req_d4, | |
197 | l2sat_coverage_ifc.spc1_pcx_req_d1 || l2sat_coverage_ifc.spc1_pcx_req_d2 || l2sat_coverage_ifc.spc1_pcx_req_d3 || l2sat_coverage_ifc.spc1_pcx_req_d4, | |
198 | l2sat_coverage_ifc.spc0_pcx_req_d1 || l2sat_coverage_ifc.spc0_pcx_req_d2 || l2sat_coverage_ifc.spc0_pcx_req_d3 || l2sat_coverage_ifc.spc0_pcx_req_d4, | |
199 | l2sat_coverage_ifc.spc7_pcx_atm_d1 || l2sat_coverage_ifc.spc7_pcx_atm_d2 || l2sat_coverage_ifc.spc7_pcx_atm_d3 || l2sat_coverage_ifc.spc7_pcx_atm_d4, | |
200 | l2sat_coverage_ifc.spc6_pcx_atm_d1 || l2sat_coverage_ifc.spc6_pcx_atm_d2 || l2sat_coverage_ifc.spc6_pcx_atm_d3 || l2sat_coverage_ifc.spc6_pcx_atm_d4, | |
201 | l2sat_coverage_ifc.spc5_pcx_atm_d1 || l2sat_coverage_ifc.spc5_pcx_atm_d2 || l2sat_coverage_ifc.spc5_pcx_atm_d3 || l2sat_coverage_ifc.spc5_pcx_atm_d4, | |
202 | l2sat_coverage_ifc.spc4_pcx_atm_d1 || l2sat_coverage_ifc.spc4_pcx_atm_d2 || l2sat_coverage_ifc.spc4_pcx_atm_d3 || l2sat_coverage_ifc.spc4_pcx_atm_d4, | |
203 | l2sat_coverage_ifc.spc3_pcx_atm_d1 || l2sat_coverage_ifc.spc3_pcx_atm_d2 || l2sat_coverage_ifc.spc3_pcx_atm_d3 || l2sat_coverage_ifc.spc3_pcx_atm_d4, | |
204 | l2sat_coverage_ifc.spc2_pcx_atm_d1 || l2sat_coverage_ifc.spc2_pcx_atm_d2 || l2sat_coverage_ifc.spc2_pcx_atm_d3 || l2sat_coverage_ifc.spc2_pcx_atm_d4, | |
205 | l2sat_coverage_ifc.spc1_pcx_atm_d1 || l2sat_coverage_ifc.spc1_pcx_atm_d2 || l2sat_coverage_ifc.spc1_pcx_atm_d3 || l2sat_coverage_ifc.spc1_pcx_atm_d4, | |
206 | l2sat_coverage_ifc.spc0_pcx_atm_d1 || l2sat_coverage_ifc.spc0_pcx_atm_d2 || l2sat_coverage_ifc.spc0_pcx_atm_d3 || l2sat_coverage_ifc.spc0_pcx_atm_d4}) { | |
207 | #inc "ccxl2_intf_pcx_req_window_sample.vrhpal"; | |
208 | } | |
209 | ||
210 | sample ccxl2_intf_cpx_req_window_cov ({l2sat_coverage_ifc.l2t7_cpx_req_d1 || l2sat_coverage_ifc.l2t7_cpx_req_d2 || l2sat_coverage_ifc.l2t7_cpx_req_d3 || l2sat_coverage_ifc.l2t7_cpx_req_d4, | |
211 | l2sat_coverage_ifc.l2t6_cpx_req_d1 || l2sat_coverage_ifc.l2t6_cpx_req_d2 || l2sat_coverage_ifc.l2t6_cpx_req_d3 || l2sat_coverage_ifc.l2t6_cpx_req_d4, | |
212 | l2sat_coverage_ifc.l2t5_cpx_req_d1 || l2sat_coverage_ifc.l2t5_cpx_req_d2 || l2sat_coverage_ifc.l2t5_cpx_req_d3 || l2sat_coverage_ifc.l2t5_cpx_req_d4, | |
213 | l2sat_coverage_ifc.l2t4_cpx_req_d1 || l2sat_coverage_ifc.l2t4_cpx_req_d2 || l2sat_coverage_ifc.l2t4_cpx_req_d3 || l2sat_coverage_ifc.l2t4_cpx_req_d4, | |
214 | l2sat_coverage_ifc.l2t3_cpx_req_d1 || l2sat_coverage_ifc.l2t3_cpx_req_d2 || l2sat_coverage_ifc.l2t3_cpx_req_d3 || l2sat_coverage_ifc.l2t3_cpx_req_d4, | |
215 | l2sat_coverage_ifc.l2t2_cpx_req_d1 || l2sat_coverage_ifc.l2t2_cpx_req_d2 || l2sat_coverage_ifc.l2t2_cpx_req_d3 || l2sat_coverage_ifc.l2t2_cpx_req_d4, | |
216 | l2sat_coverage_ifc.l2t1_cpx_req_d1 || l2sat_coverage_ifc.l2t1_cpx_req_d2 || l2sat_coverage_ifc.l2t1_cpx_req_d3 || l2sat_coverage_ifc.l2t1_cpx_req_d4, | |
217 | l2sat_coverage_ifc.l2t0_cpx_req_d1 || l2sat_coverage_ifc.l2t0_cpx_req_d2 || l2sat_coverage_ifc.l2t0_cpx_req_d3 || l2sat_coverage_ifc.l2t0_cpx_req_d4, | |
218 | l2sat_coverage_ifc.l2t7_cpx_atom_d1 || l2sat_coverage_ifc.l2t7_cpx_atom_d2 || l2sat_coverage_ifc.l2t7_cpx_atom_d3 || l2sat_coverage_ifc.l2t7_cpx_atom_d4, | |
219 | l2sat_coverage_ifc.l2t6_cpx_atom_d1 || l2sat_coverage_ifc.l2t6_cpx_atom_d2 || l2sat_coverage_ifc.l2t6_cpx_atom_d3 || l2sat_coverage_ifc.l2t6_cpx_atom_d4, | |
220 | l2sat_coverage_ifc.l2t5_cpx_atom_d1 || l2sat_coverage_ifc.l2t5_cpx_atom_d2 || l2sat_coverage_ifc.l2t5_cpx_atom_d3 || l2sat_coverage_ifc.l2t5_cpx_atom_d4, | |
221 | l2sat_coverage_ifc.l2t4_cpx_atom_d1 || l2sat_coverage_ifc.l2t4_cpx_atom_d2 || l2sat_coverage_ifc.l2t4_cpx_atom_d3 || l2sat_coverage_ifc.l2t4_cpx_atom_d4, | |
222 | l2sat_coverage_ifc.l2t3_cpx_atom_d1 || l2sat_coverage_ifc.l2t3_cpx_atom_d2 || l2sat_coverage_ifc.l2t3_cpx_atom_d3 || l2sat_coverage_ifc.l2t3_cpx_atom_d4, | |
223 | l2sat_coverage_ifc.l2t2_cpx_atom_d1 || l2sat_coverage_ifc.l2t2_cpx_atom_d2 || l2sat_coverage_ifc.l2t2_cpx_atom_d3 || l2sat_coverage_ifc.l2t2_cpx_atom_d4, | |
224 | l2sat_coverage_ifc.l2t1_cpx_atom_d1 || l2sat_coverage_ifc.l2t1_cpx_atom_d2 || l2sat_coverage_ifc.l2t1_cpx_atom_d3 || l2sat_coverage_ifc.l2t1_cpx_atom_d4, | |
225 | l2sat_coverage_ifc.l2t0_cpx_atom_d1 || l2sat_coverage_ifc.l2t0_cpx_atom_d2 || l2sat_coverage_ifc.l2t0_cpx_atom_d3 || l2sat_coverage_ifc.l2t0_cpx_atom_d4}) { | |
226 | #inc "ccxl2_intf_cpx_req_sample.vrhpal"; | |
227 | } | |
228 | #endif | |
229 | ||
230 | ||
231 | /* | |
232 | #ifdef L2_INTF_COV | |
233 | sample pcxsiu_intf_pcx_req_cov ({l2sat_coverage_ifc.spc7_pcx_req_d1 && l2sat_coverage_ifc.spc7_pcx_req_d2 && l2sat_coverage_ifc.spc7_pcx_req_d3 && l2sat_coverage_ifc.spc7_pcx_req_d4 && l2sat_coverage_ifc.spc7_pcx_req_d5 && l2sat_coverage_ifc.spc7_pcx_req_d6 && l2sat_coverage_ifc.spc7_pcx_req_d7 && l2sat_coverage_ifc.spc7_pcx_req_d8 && l2sat_coverage_ifc.spc7_pcx_req_d9 && l2sat_coverage_ifc.spc7_pcx_req_d10 && l2sat_coverage_ifc.sii_l2t7_req_vld && (l2sat_coverage_ifc.sii_l2t7_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t7_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t7_req[26:24] === 3'b001), | |
234 | l2sat_coverage_ifc.spc6_pcx_req_d1 && l2sat_coverage_ifc.spc6_pcx_req_d2 && l2sat_coverage_ifc.spc6_pcx_req_d3 && l2sat_coverage_ifc.spc6_pcx_req_d4 && l2sat_coverage_ifc.spc6_pcx_req_d5 && l2sat_coverage_ifc.spc6_pcx_req_d6 && l2sat_coverage_ifc.spc6_pcx_req_d7 && l2sat_coverage_ifc.spc6_pcx_req_d8 && l2sat_coverage_ifc.spc6_pcx_req_d9 && l2sat_coverage_ifc.spc6_pcx_req_d10 && l2sat_coverage_ifc.sii_l2t6_req_vld && (l2sat_coverage_ifc.sii_l2t6_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t6_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t6_req[26:24] === 3'b001), | |
235 | l2sat_coverage_ifc.spc5_pcx_req_d1 && l2sat_coverage_ifc.spc5_pcx_req_d2 && l2sat_coverage_ifc.spc5_pcx_req_d3 && l2sat_coverage_ifc.spc5_pcx_req_d4 && l2sat_coverage_ifc.spc5_pcx_req_d5 && l2sat_coverage_ifc.spc5_pcx_req_d6 && l2sat_coverage_ifc.spc5_pcx_req_d7 && l2sat_coverage_ifc.spc5_pcx_req_d8 && l2sat_coverage_ifc.spc5_pcx_req_d9 && l2sat_coverage_ifc.spc5_pcx_req_d10 && l2sat_coverage_ifc.sii_l2t5_req_vld && (l2sat_coverage_ifc.sii_l2t5_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t5_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t5_req[26:24] === 3'b001), | |
236 | l2sat_coverage_ifc.spc4_pcx_req_d1 && l2sat_coverage_ifc.spc4_pcx_req_d2 && l2sat_coverage_ifc.spc4_pcx_req_d3 && l2sat_coverage_ifc.spc4_pcx_req_d4 && l2sat_coverage_ifc.spc4_pcx_req_d5 && l2sat_coverage_ifc.spc4_pcx_req_d6 && l2sat_coverage_ifc.spc4_pcx_req_d7 && l2sat_coverage_ifc.spc4_pcx_req_d8 && l2sat_coverage_ifc.spc4_pcx_req_d9 && l2sat_coverage_ifc.spc4_pcx_req_d10 && l2sat_coverage_ifc.sii_l2t4_req_vld && (l2sat_coverage_ifc.sii_l2t4_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t4_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t4_req[26:24] === 3'b001), | |
237 | l2sat_coverage_ifc.spc3_pcx_req_d1 && l2sat_coverage_ifc.spc3_pcx_req_d2 && l2sat_coverage_ifc.spc3_pcx_req_d3 && l2sat_coverage_ifc.spc3_pcx_req_d4 && l2sat_coverage_ifc.spc3_pcx_req_d5 && l2sat_coverage_ifc.spc3_pcx_req_d6 && l2sat_coverage_ifc.spc3_pcx_req_d7 && l2sat_coverage_ifc.spc3_pcx_req_d8 && l2sat_coverage_ifc.spc3_pcx_req_d9 && l2sat_coverage_ifc.spc3_pcx_req_d10 && l2sat_coverage_ifc.sii_l2t3_req_vld && (l2sat_coverage_ifc.sii_l2t3_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t3_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t3_req[26:24] === 3'b001), | |
238 | l2sat_coverage_ifc.spc2_pcx_req_d1 && l2sat_coverage_ifc.spc2_pcx_req_d2 && l2sat_coverage_ifc.spc2_pcx_req_d3 && l2sat_coverage_ifc.spc2_pcx_req_d4 && l2sat_coverage_ifc.spc2_pcx_req_d5 && l2sat_coverage_ifc.spc2_pcx_req_d6 && l2sat_coverage_ifc.spc2_pcx_req_d7 && l2sat_coverage_ifc.spc2_pcx_req_d8 && l2sat_coverage_ifc.spc2_pcx_req_d9 && l2sat_coverage_ifc.spc2_pcx_req_d10 && l2sat_coverage_ifc.sii_l2t2_req_vld && (l2sat_coverage_ifc.sii_l2t2_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t2_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t2_req[26:24] === 3'b001), | |
239 | l2sat_coverage_ifc.spc1_pcx_req_d1 && l2sat_coverage_ifc.spc1_pcx_req_d2 && l2sat_coverage_ifc.spc1_pcx_req_d3 && l2sat_coverage_ifc.spc1_pcx_req_d4 && l2sat_coverage_ifc.spc1_pcx_req_d5 && l2sat_coverage_ifc.spc1_pcx_req_d6 && l2sat_coverage_ifc.spc1_pcx_req_d7 && l2sat_coverage_ifc.spc1_pcx_req_d8 && l2sat_coverage_ifc.spc1_pcx_req_d9 && l2sat_coverage_ifc.spc1_pcx_req_d10 && l2sat_coverage_ifc.sii_l2t1_req_vld && (l2sat_coverage_ifc.sii_l2t1_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t1_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t1_req[26:24] === 3'b001), | |
240 | l2sat_coverage_ifc.spc0_pcx_req_d1 && l2sat_coverage_ifc.spc0_pcx_req_d2 && l2sat_coverage_ifc.spc0_pcx_req_d3 && l2sat_coverage_ifc.spc0_pcx_req_d4 && l2sat_coverage_ifc.spc0_pcx_req_d5 && l2sat_coverage_ifc.spc0_pcx_req_d6 && l2sat_coverage_ifc.spc0_pcx_req_d7 && l2sat_coverage_ifc.spc0_pcx_req_d8 && l2sat_coverage_ifc.spc0_pcx_req_d9 && l2sat_coverage_ifc.spc0_pcx_req_d10 && l2sat_coverage_ifc.sii_l2t0_req_vld && (l2sat_coverage_ifc.sii_l2t0_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t0_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t0_req[26:24] === 3'b001), | |
241 | l2sat_coverage_ifc.spc7_pcx_atm_d1 && l2sat_coverage_ifc.spc7_pcx_atm_d2 && l2sat_coverage_ifc.spc7_pcx_atm_d3 && l2sat_coverage_ifc.spc7_pcx_atm_d4 && l2sat_coverage_ifc.spc7_pcx_atm_d5 && l2sat_coverage_ifc.spc7_pcx_atm_d6 && l2sat_coverage_ifc.spc7_pcx_atm_d7 && l2sat_coverage_ifc.spc7_pcx_atm_d8 && l2sat_coverage_ifc.spc7_pcx_atm_d9 && l2sat_coverage_ifc.spc7_pcx_atm_d10 && l2sat_coverage_ifc.sii_l2t7_req_vld && (l2sat_coverage_ifc.sii_l2t7_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t7_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t7_req[26:24] === 3'b001), | |
242 | l2sat_coverage_ifc.spc6_pcx_atm_d1 && l2sat_coverage_ifc.spc6_pcx_atm_d2 && l2sat_coverage_ifc.spc6_pcx_atm_d3 && l2sat_coverage_ifc.spc6_pcx_atm_d4 && l2sat_coverage_ifc.spc6_pcx_atm_d5 && l2sat_coverage_ifc.spc6_pcx_atm_d6 && l2sat_coverage_ifc.spc6_pcx_atm_d7 && l2sat_coverage_ifc.spc6_pcx_atm_d8 && l2sat_coverage_ifc.spc6_pcx_atm_d9 && l2sat_coverage_ifc.spc6_pcx_atm_d10 && l2sat_coverage_ifc.sii_l2t6_req_vld && (l2sat_coverage_ifc.sii_l2t6_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t6_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t6_req[26:24] === 3'b001), | |
243 | l2sat_coverage_ifc.spc5_pcx_atm_d1 && l2sat_coverage_ifc.spc5_pcx_atm_d2 && l2sat_coverage_ifc.spc5_pcx_atm_d3 && l2sat_coverage_ifc.spc5_pcx_atm_d4 && l2sat_coverage_ifc.spc5_pcx_atm_d5 && l2sat_coverage_ifc.spc5_pcx_atm_d6 && l2sat_coverage_ifc.spc5_pcx_atm_d7 && l2sat_coverage_ifc.spc5_pcx_atm_d8 && l2sat_coverage_ifc.spc5_pcx_atm_d9 && l2sat_coverage_ifc.spc5_pcx_atm_d10 && l2sat_coverage_ifc.sii_l2t5_req_vld && (l2sat_coverage_ifc.sii_l2t5_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t5_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t5_req[26:24] === 3'b001), | |
244 | l2sat_coverage_ifc.spc4_pcx_atm_d1 && l2sat_coverage_ifc.spc4_pcx_atm_d2 && l2sat_coverage_ifc.spc4_pcx_atm_d3 && l2sat_coverage_ifc.spc4_pcx_atm_d4 && l2sat_coverage_ifc.spc4_pcx_atm_d5 && l2sat_coverage_ifc.spc4_pcx_atm_d6 && l2sat_coverage_ifc.spc4_pcx_atm_d7 && l2sat_coverage_ifc.spc4_pcx_atm_d8 && l2sat_coverage_ifc.spc4_pcx_atm_d9 && l2sat_coverage_ifc.spc4_pcx_atm_d10 && l2sat_coverage_ifc.sii_l2t4_req_vld && (l2sat_coverage_ifc.sii_l2t4_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t4_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t4_req[26:24] === 3'b001), | |
245 | l2sat_coverage_ifc.spc3_pcx_atm_d1 && l2sat_coverage_ifc.spc3_pcx_atm_d2 && l2sat_coverage_ifc.spc3_pcx_atm_d3 && l2sat_coverage_ifc.spc3_pcx_atm_d4 && l2sat_coverage_ifc.spc3_pcx_atm_d5 && l2sat_coverage_ifc.spc3_pcx_atm_d6 && l2sat_coverage_ifc.spc3_pcx_atm_d7 && l2sat_coverage_ifc.spc3_pcx_atm_d8 && l2sat_coverage_ifc.spc3_pcx_atm_d9 && l2sat_coverage_ifc.spc3_pcx_atm_d10 && l2sat_coverage_ifc.sii_l2t3_req_vld && (l2sat_coverage_ifc.sii_l2t3_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t3_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t3_req[26:24] === 3'b001), | |
246 | l2sat_coverage_ifc.spc2_pcx_atm_d1 && l2sat_coverage_ifc.spc2_pcx_atm_d2 && l2sat_coverage_ifc.spc2_pcx_atm_d3 && l2sat_coverage_ifc.spc2_pcx_atm_d4 && l2sat_coverage_ifc.spc2_pcx_atm_d5 && l2sat_coverage_ifc.spc2_pcx_atm_d6 && l2sat_coverage_ifc.spc2_pcx_atm_d7 && l2sat_coverage_ifc.spc2_pcx_atm_d8 && l2sat_coverage_ifc.spc2_pcx_atm_d9 && l2sat_coverage_ifc.spc2_pcx_atm_d10 && l2sat_coverage_ifc.sii_l2t2_req_vld && (l2sat_coverage_ifc.sii_l2t2_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t2_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t2_req[26:24] === 3'b001), | |
247 | l2sat_coverage_ifc.spc1_pcx_atm_d1 && l2sat_coverage_ifc.spc1_pcx_atm_d2 && l2sat_coverage_ifc.spc1_pcx_atm_d3 && l2sat_coverage_ifc.spc1_pcx_atm_d4 && l2sat_coverage_ifc.spc1_pcx_atm_d5 && l2sat_coverage_ifc.spc1_pcx_atm_d6 && l2sat_coverage_ifc.spc1_pcx_atm_d7 && l2sat_coverage_ifc.spc1_pcx_atm_d8 && l2sat_coverage_ifc.spc1_pcx_atm_d9 && l2sat_coverage_ifc.spc1_pcx_atm_d10 && l2sat_coverage_ifc.sii_l2t1_req_vld && (l2sat_coverage_ifc.sii_l2t1_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t1_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t1_req[26:24] === 3'b001), | |
248 | l2sat_coverage_ifc.spc0_pcx_atm_d1 && l2sat_coverage_ifc.spc0_pcx_atm_d2 && l2sat_coverage_ifc.spc0_pcx_atm_d3 && l2sat_coverage_ifc.spc0_pcx_atm_d4 && l2sat_coverage_ifc.spc0_pcx_atm_d5 && l2sat_coverage_ifc.spc0_pcx_atm_d6 && l2sat_coverage_ifc.spc0_pcx_atm_d7 && l2sat_coverage_ifc.spc0_pcx_atm_d8 && l2sat_coverage_ifc.spc0_pcx_atm_d9 && l2sat_coverage_ifc.spc0_pcx_atm_d10 && l2sat_coverage_ifc.sii_l2t0_req_vld && (l2sat_coverage_ifc.sii_l2t0_req[26:24] === 3'b100 | l2sat_coverage_ifc.sii_l2t0_req[26:24] === 3'b010 | l2sat_coverage_ifc.sii_l2t0_req[26:24] === 3'b001)}) { | |
249 | #inc "pcxsiu_intf_cpx_req_sample.vrhpal"; | |
250 | } | |
251 | #endif | |
252 | */ | |
253 | sample ccxsiu_intf_pcx_sii_req_cov({l2_single_pcx_WRI_same_addr_samp_trigger, | |
254 | l2_double_pcx_WRI_same_addr_samp_trigger, | |
255 | l2_single_pcx_WR8_same_addr_samp_trigger, | |
256 | l2_double_pcx_WR8_same_addr_samp_trigger, | |
257 | l2_single_pcx_RDD_same_addr_samp_trigger, | |
258 | l2_double_pcx_RDD_same_addr_samp_trigger, | |
259 | l2_single_pcx_WRI_diff_addr_samp_trigger, | |
260 | l2_double_pcx_WRI_diff_addr_samp_trigger, | |
261 | l2_single_pcx_WR8_diff_addr_samp_trigger, | |
262 | l2_double_pcx_WR8_diff_addr_samp_trigger, | |
263 | l2_single_pcx_RDD_diff_addr_samp_trigger, | |
264 | l2_double_pcx_RDD_diff_addr_samp_trigger}){ | |
265 | #inc "ccxsiu_intf_pcx_sii_req_samp.vrhpal"; | |
266 | } | |
267 | ||
268 | sample ccxl2_intf_pcx_sequence_cov ({l2sat_coverage_ifc.spc0_pcx_req, | |
269 | l2sat_coverage_ifc.spc0_pcx_atm, | |
270 | l2sat_coverage_ifc.pcx_spc0_grant}) { | |
271 | // {spc0_pcx_req[7:0],spc0_pcx_atm[7:0],pcx_spc0_grant[7:0]} | |
272 | #inc "ccx_pcx_sequence_sample.vrhpal"; | |
273 | } | |
274 | ||
275 | // End of CCX interface coverages | |
276 | ||
277 | //////////////////////////// | |
278 | // CCX internal coverages | |
279 | //////////////////////////// | |
280 | ||
281 | // added to FC following 2; 10/25/05 | |
282 | sample ccx_pcx_qfull_cov ({l2sat_coverage_ifc.pcx_arb7_qfull, l2sat_coverage_ifc.pcx_arb6_qfull, | |
283 | l2sat_coverage_ifc.pcx_arb5_qfull, l2sat_coverage_ifc.pcx_arb4_qfull, | |
284 | l2sat_coverage_ifc.pcx_arb3_qfull, l2sat_coverage_ifc.pcx_arb2_qfull, | |
285 | l2sat_coverage_ifc.pcx_arb1_qfull, l2sat_coverage_ifc.pcx_arb0_qfull}) { | |
286 | // {pcx_arb7_qfull[7:0]...pcx_arb0_qfull[7:0]} | |
287 | #inc "ccx_pcx_qfull_sample.vrhpal"; | |
288 | } | |
289 | ||
290 | sample ccx_cpx_qfull_cov ({l2sat_coverage_ifc.cpx_arb7_qfull, l2sat_coverage_ifc.cpx_arb6_qfull, | |
291 | l2sat_coverage_ifc.cpx_arb5_qfull, l2sat_coverage_ifc.cpx_arb4_qfull, | |
292 | l2sat_coverage_ifc.cpx_arb3_qfull, l2sat_coverage_ifc.cpx_arb2_qfull, | |
293 | l2sat_coverage_ifc.cpx_arb1_qfull, l2sat_coverage_ifc.cpx_arb0_qfull}) { | |
294 | // {cpx_arb7_qfull[7:0]...cpx_arb0_qfull[7:0]} | |
295 | #inc "ccx_cpx_qfull_sample.vrhpal"; | |
296 | } | |
297 | ||
298 | ||
299 | // added to FC following 2; 10/25/05 | |
300 | sample ccx_pcx_stallatom_cov ({l2sat_coverage_ifc.pcx_arb0_atom, | |
301 | l2sat_coverage_ifc.pcx_arb0_grant_a, | |
302 | l2sat_coverage_ifc.pcx_arb0_stall_a_}) { | |
303 | // {pcx_arb0_atom[7:0],pcx_arb0_grant_a[7:0],pcx_arb0_stall_a_} | |
304 | #inc "ccx_pcx_stallatom_sample.vrhpal"; | |
305 | } | |
306 | ||
307 | sample ccx_cpx_stallatom_cov ({l2sat_coverage_ifc.cpx_arb0_atom, | |
308 | l2sat_coverage_ifc.cpx_arb0_grant_a, | |
309 | l2sat_coverage_ifc.cpx_arb0_stall_a_}) { | |
310 | // {cpx_arb0_atom[7:0],cpx_arb0_grant_a[7:0],cpx_arb0_stall_a_} | |
311 | #inc "ccx_cpx_stallatom_sample.vrhpal"; | |
312 | } | |
313 | ||
314 | // end of CCX internal coverages | |
315 | ||
316 | ||
317 | /////////////////////////////////// | |
318 | // L2 interface coverages | |
319 | /////////////////////////////////// | |
320 | ||
321 | sample ccxl2_intf_pcx_fields_cov ({l2sat_coverage_ifc.pcx_l2t0_data_rdy, | |
322 | l2sat_coverage_ifc.pcx_l2t0_data[129:64]}) { | |
323 | #inc "l2_pcx_fields_sample.vrhpal"; | |
324 | } | |
325 | ||
326 | sample ccxl2_intf_cpx_fields_cov (l2sat_coverage_ifc.l2t0_cpx_data[145:123]) { | |
327 | #inc "l2_cpx_fields_sample.vrhpal"; | |
328 | } | |
329 | ||
330 | sample ccxl2_intf_inv_vector_cov ({l2sat_coverage_ifc.l2t0_cpx_data[145:141], | |
331 | l2sat_coverage_ifc.l2t0_cpx_data[111:0]}) { | |
332 | #inc "l2_inv_vector_sample.vrhpal"; | |
333 | } | |
334 | ||
335 | // end of L2 interface coverages | |
336 | ||
337 | ///////////////////////////// | |
338 | // L2 Internal coverages | |
339 | ///////////////////////////// | |
340 | ||
341 | #ifndef L2_INTF_COV | |
342 | sample l2_addr_cov ({l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
343 | l2sat_coverage_ifc.arbctl_inst_diag_c2_0, | |
344 | l2sat_coverage_ifc.arbctl_inval_inst_c2_0, | |
345 | l2sat_coverage_ifc.arb_decdp_inst_int_c2_0, | |
346 | l2sat_coverage_ifc.arbdp_addr_c2_0}) { | |
347 | #inc "l2sat_addr_sample.vrhpal"; | |
348 | } | |
349 | #endif | |
350 | ||
351 | } // end of "coverage_group l2sat_ccx_coverage_group" | |
352 | ||
353 | ||
354 | coverage_group l2sat_input_queue_coverage_group | |
355 | { | |
356 | ||
357 | sample_event = @(posedge CLOCK); | |
358 | ||
359 | // added to FC following 2; 10/25/05 | |
360 | sample l2_iq_count_cov (l2sat_coverage_ifc.iq_count_0) { | |
361 | #inc "l2_iq_count_sample.vrhpal"; | |
362 | } | |
363 | ||
364 | sample l2_iq_cas12_cov (l2_iq_cas12_samp_trigger) { //coverage in misc_cov | |
365 | #inc "l2_iq_cas12_sample.vrhpal"; | |
366 | } | |
367 | ||
368 | } // end of "coverage_group l2sat_input_queue_coverage_group" | |
369 | ||
370 | ||
371 | coverage_group l2sat_output_queue_coverage_group | |
372 | { | |
373 | ||
374 | sample_event = @(posedge CLOCK); | |
375 | ||
376 | // added to FC following 2; 10/25/05 | |
377 | sample l2_oq_count_cov (l2sat_coverage_ifc.oq_count_0) { | |
378 | #inc "l2_oq_count_sample.vrhpal"; | |
379 | } | |
380 | ||
381 | sample l2_oq_fill12_cov ({l2sat_coverage_ifc.imiss1_to_xbarq_c6_0, | |
382 | l2sat_coverage_ifc.sel_old_req_0}) { | |
383 | #inc "l2_oq_ifill12_sample.vrhpal"; | |
384 | } | |
385 | ||
386 | } // end of "coverage_group l2sat_output_queue_coverage_group" | |
387 | ||
388 | ||
389 | coverage_group l2sat_directory_coverage_group | |
390 | { | |
391 | sample_event = @(posedge CLOCK); | |
392 | ||
393 | ||
394 | //added to FC following TWO for PM targeted 11/16 | |
395 | sample l2_dir_write_cov ({l2sat_coverage_ifc.ic_wr_en_c4_0, | |
396 | l2sat_coverage_ifc.dir_panel_icd_c4_0[4:3], | |
397 | l2sat_coverage_ifc.dir_panel_icd_c4_0[1:0], | |
398 | l2sat_coverage_ifc.wr_ic_dir_entry_c4_0, | |
399 | l2sat_coverage_ifc.dc_wr_en_c4_0, | |
400 | l2sat_coverage_ifc.dir_panel_dcd_c4_0[4:3], | |
401 | l2sat_coverage_ifc.dir_panel_dcd_c4_0[1:0], | |
402 | l2sat_coverage_ifc.wr_dc_dir_entry_c4_0}) { | |
403 | #inc "l2_dir_write_sample.vrhpal"; | |
404 | } | |
405 | ||
406 | sample l2_dir_lookup_cov ({l2sat_coverage_ifc.ic_lkup_row_dec_c4_0, | |
407 | l2sat_coverage_ifc.lkup_row_addr_icd_c4_0, | |
408 | l2sat_coverage_ifc.dc_lkup_row_dec_c4_0, | |
409 | l2sat_coverage_ifc.lkup_row_addr_dcd_c4_0}) { | |
410 | #inc "l2_dir_lookup_sample.vrhpal"; | |
411 | } | |
412 | ||
413 | } // end of 'coverage_group l2sat_directory_coverage_group" | |
414 | ||
415 | ||
416 | coverage_group l2sat_missbuffer_coverage_group | |
417 | { | |
418 | ||
419 | sample_event = @(posedge CLOCK); | |
420 | ||
421 | #ifndef L2_INTF_COV | |
422 | ||
423 | sample l2_mb_count_cov (l2sat_coverage_ifc.mb_count_0) { | |
424 | #inc "l2_mb_count_sample.vrhpal"; | |
425 | } | |
426 | ||
427 | sample l2_mb_sameindex_cov (l2sat_coverage_ifc.mb_sameindex_count_0) { | |
428 | #inc "l2_mb_sameindex_sample.vrhpal"; | |
429 | } | |
430 | ||
431 | sample l2_mb_hit_bypass_cov ({l2sat_coverage_ifc.mbctl_hit_c2_0, | |
432 | l2sat_coverage_ifc.tmp_hit_unqual_c2_0, | |
433 | l2sat_coverage_ifc.tmp_cam_hit_c2_0, | |
434 | l2sat_coverage_ifc.mbf_insert_c3_tmp_0, | |
435 | l2sat_coverage_ifc.cam_hit_vec_c1_0}) { | |
436 | #inc "l2_mb_hit_bypass_sample.vrhpal"; | |
437 | } | |
438 | #endif | |
439 | } // end of "coverage_group l2sat_missbuffer_coverage_group" | |
440 | ||
441 | ||
442 | coverage_group l2sat_fillbuffer_coverage_group | |
443 | { | |
444 | ||
445 | sample_event = @(posedge CLOCK); | |
446 | ||
447 | // added to FC following 2; 10/25/05 | |
448 | sample l2_fb_count_cov (l2sat_coverage_ifc.fb_count_0) { | |
449 | #inc "l2_fb_count_sample.vrhpal"; | |
450 | } | |
451 | ||
452 | sample l2_fbmb_miss_entries_cov ({l2sat_coverage_ifc.fbf_ready_miss_r1_0, | |
453 | l2sat_coverage_ifc.dram_rd_req_id_r0_d1_0, | |
454 | l2sat_coverage_ifc.fbf_enc_ld_mbid_r1_0}) { | |
455 | #inc "l2_fbmb_miss_entries_sample.vrhpal"; | |
456 | } | |
457 | ||
458 | #ifndef L2_INTF_COV | |
459 | sample l2_fbmb_stdep_entries_cov ({l2sat_coverage_ifc.fbf_st_or_dep_rdy_c4_0, | |
460 | l2sat_coverage_ifc.fill_complete_c4_0, | |
461 | l2sat_coverage_ifc.fbf_enc_dep_mbid_c4_0}) { | |
462 | #inc "l2_fbmb_stdep_entries_sample.vrhpal"; | |
463 | } | |
464 | ||
465 | sample l2_fb_bypass_entries_cov ({l2sat_coverage_ifc.fbctl_hit_c2_0, | |
466 | l2sat_coverage_ifc.fb_hit_vec_c2_0}) { | |
467 | #inc "l2_fb_bypass_entries_sample.vrhpal"; | |
468 | } | |
469 | ||
470 | sample l2_fb_bypass_insts_cov ({l2sat_coverage_ifc.fbctl_hit_c2_0, | |
471 | l2sat_coverage_ifc.arbctl_inst_diag_c2_0, | |
472 | l2sat_coverage_ifc.arbdp_inst_c2_0[25:19], | |
473 | l2sat_coverage_ifc.arbdp_inst_c2_0[12:11], //review how to get INV and PF bits? | |
474 | l2sat_coverage_ifc.arbdp_addr_c2_0[5:4]}) { | |
475 | #inc "l2_fb_bypass_insts_sample.vrhpal"; | |
476 | } | |
477 | ||
478 | sample l2_fill_complete_cov ({l2sat_coverage_ifc.dec_fill_entry_c3_0, | |
479 | l2sat_coverage_ifc.no_fill_entry_dequeue_c3_0, | |
480 | l2sat_coverage_ifc.en_hit_dequeue_c2_0, | |
481 | l2sat_coverage_ifc.rdma_inst_c2_0, | |
482 | l2sat_coverage_ifc.mbctl_rdma_reg_vld_c2_0}) { | |
483 | #inc "l2_fill_complete_sample.vrhpal"; | |
484 | } | |
485 | #endif | |
486 | ||
487 | } // end of "coverage_group l2sat_fillbuffer_coverage_group" | |
488 | ||
489 | ||
490 | coverage_group l2sat_write_back_buffer_group | |
491 | { | |
492 | ||
493 | sample_event = @(posedge CLOCK); | |
494 | ||
495 | // added to FC following 1; 10/25/05 | |
496 | sample l2_wb_count_cov (l2sat_coverage_ifc.wb_count_0) { | |
497 | #inc "l2_wb_count_sample.vrhpal"; | |
498 | } | |
499 | ||
500 | #ifndef L2_INTF_COV | |
501 | sample l2_wb_hit_bypass_cov ({l2sat_coverage_ifc.wbctl_hit_qual_c2_0, | |
502 | l2sat_coverage_ifc.bypass_hit_en_c2_0, | |
503 | l2sat_coverage_ifc.wb_cam_hit_vec_tmp_c2_0}) { | |
504 | #inc "l2_wb_hit_bypass_sample.vrhpal"; | |
505 | } | |
506 | #endif | |
507 | } // end of "coverage_group l2sat_write_back_buffer_group" | |
508 | ||
509 | ||
510 | coverage_group l2sat_pipeline_coverage_group | |
511 | { | |
512 | ||
513 | sample_event = @(posedge CLOCK); | |
514 | ||
515 | #ifndef L2_INTF_COV | |
516 | sample l2_pipeline_full_cov ({l2sat_coverage_ifc.arbctl_inst_vld_c1_0, | |
517 | l2sat_coverage_ifc.arbctl_inst_vld_c2_0}) { | |
518 | #inc "l2_pipeline_full_sample.vrhpal"; | |
519 | } | |
520 | ||
521 | sample l2_atomic_store_cov (l2_atomic_store_samp_trigger) { | |
522 | #inc "l2_atomic_store_sample.vrhpal"; | |
523 | } | |
524 | ||
525 | sample l2_stalled_insts1_cov ({l2sat_coverage_ifc.same_col_stall_c1_0, //17 | |
526 | l2sat_coverage_ifc.imiss_stall_op_c1inc1_0, //16 | |
527 | l2sat_coverage_ifc.arbctl_evict_vld_c2_0, //15 | |
528 | l2sat_coverage_ifc.arbctl_fill_vld_c2_0, //14 | |
529 | l2sat_coverage_ifc.arbctl_fill_vld_c3_0, //13 | |
530 | l2sat_coverage_ifc.rdma_64B_stall_0, //11 | |
531 | l2sat_coverage_ifc.arbctl_inval_inst_c2_0, //11 | |
532 | l2sat_coverage_ifc.inval_inst_vld_c3_0, //10 | |
533 | l2sat_coverage_ifc.inval_inst_vld_c4_0, //9 | |
534 | l2sat_coverage_ifc.ic_inval_vld_c5_0, //21 | |
535 | l2sat_coverage_ifc.ic_inval_vld_c52_0, //20 | |
536 | l2sat_coverage_ifc.ic_inval_vld_c6_0, //19 | |
537 | l2sat_coverage_ifc.arb_ic_inval_vld_c7_0, //18 | |
538 | l2sat_coverage_ifc.inst_l2data_vld_c2_0, //8 | |
539 | l2sat_coverage_ifc.inst_l2tag_vld_c2_0, //7 | |
540 | l2sat_coverage_ifc.inst_l2tag_vld_c3_0, //6 | |
541 | l2sat_coverage_ifc.inst_l2vuad_vld_c2_0, //5 | |
542 | l2sat_coverage_ifc.inst_l2vuad_vld_c3_0, //4 | |
543 | l2sat_coverage_ifc.inst_l2vuad_vld_c4_0, //3 | |
544 | l2sat_coverage_ifc.inc_tag_ecc_cnt_c2_0, //2 | |
545 | l2sat_coverage_ifc.inc_tag_ecc_cnt_c3_0, //1 | |
546 | l2sat_coverage_ifc.data_ecc_active_c4_0, //0 | |
547 | l2sat_coverage_ifc.arbctl_inst_vld_c1_0, | |
548 | l2sat_coverage_ifc.arbctl_inst_diag_c1_0, | |
549 | l2sat_coverage_ifc.arbdp_inst_c1_0[25:10]}) { | |
550 | #inc "l2_stalled_insts1_sample.vrhpal"; | |
551 | } | |
552 | ||
553 | sample l2_stalled_insts2_cov ({l2sat_coverage_ifc.arbctl_inst_diag_c1_0, //7 | |
554 | l2sat_coverage_ifc.arbdp_evict_c1_0, //6 | |
555 | l2sat_coverage_ifc.arbdp_inst_fb_c1_0, //5 | |
556 | l2sat_coverage_ifc.decdp_imiss_inst_c1_0, //4 | |
557 | l2sat_coverage_ifc.decdp_ic_inval_c1_0, //3 | |
558 | l2sat_coverage_ifc.decdp_dc_inval_c1_0, //2 | |
559 | l2sat_coverage_ifc.arbdp_tecc_c1_0, //1 | |
560 | l2sat_coverage_ifc.arbdp_inst_rsvd_c1_0, //0 | |
561 | l2sat_coverage_ifc.arbctl_stall_c2_0, | |
562 | l2sat_coverage_ifc.arbctl_inst_vld_c1_0, | |
563 | l2sat_coverage_ifc.arbctl_inst_diag_c1_0, | |
564 | l2sat_coverage_ifc.arbdp_inst_c1_0[25:10]}) { | |
565 | #inc "l2_stalled_insts2_sample.vrhpal"; | |
566 | } | |
567 | ||
568 | sample l2_stalled_scrub1_cov ({l2sat_coverage_ifc.same_col_stall_c1_0, //17 | |
569 | l2sat_coverage_ifc.imiss_stall_op_c1inc1_0, //16 | |
570 | l2sat_coverage_ifc.arbctl_evict_vld_c2_0, //15 | |
571 | l2sat_coverage_ifc.arbctl_fill_vld_c2_0, //14 | |
572 | l2sat_coverage_ifc.arbctl_fill_vld_c3_0, //13 | |
573 | l2sat_coverage_ifc.rdma_64B_stall_0, //12 | |
574 | l2sat_coverage_ifc.arbctl_inval_inst_c2_0, //11 | |
575 | l2sat_coverage_ifc.inval_inst_vld_c3_0, //10 | |
576 | l2sat_coverage_ifc.inval_inst_vld_c4_0, //9 | |
577 | l2sat_coverage_ifc.inst_l2data_vld_c2_0, //8 | |
578 | l2sat_coverage_ifc.inst_l2tag_vld_c2_0, //7 | |
579 | l2sat_coverage_ifc.inst_l2tag_vld_c3_0, //6 | |
580 | l2sat_coverage_ifc.inst_l2vuad_vld_c2_0, //5 | |
581 | l2sat_coverage_ifc.inst_l2vuad_vld_c3_0, //4 | |
582 | l2sat_coverage_ifc.inst_l2vuad_vld_c4_0, //3 | |
583 | l2sat_coverage_ifc.inc_tag_ecc_cnt_c2_0, //2 | |
584 | l2sat_coverage_ifc.inc_tag_ecc_cnt_c3_0, //1 | |
585 | l2sat_coverage_ifc.data_ecc_active_c4_0, //0 | |
586 | l2sat_coverage_ifc.arbctl_inst_vld_c1_0, | |
587 | l2sat_coverage_ifc.arbdp_inst_fb_c1_0, | |
588 | l2sat_coverage_ifc.arbdp_tecc_c1_0}) { | |
589 | #inc "l2_stalled_scrub1_sample.vrhpal"; | |
590 | } | |
591 | ||
592 | sample l2_stalled_scrub2_cov ({l2sat_coverage_ifc.arbctl_inst_diag_c1_0, //7 | |
593 | l2sat_coverage_ifc.arbdp_evict_c1_0, //6 | |
594 | l2sat_coverage_ifc.arbdp_inst_fb_c1_0, //5 | |
595 | l2sat_coverage_ifc.decdp_imiss_inst_c1_0, //4 | |
596 | l2sat_coverage_ifc.decdp_ic_inval_c1_0, //3 | |
597 | l2sat_coverage_ifc.decdp_dc_inval_c1_0, //2 | |
598 | l2sat_coverage_ifc.arbdp_tecc_c1_0, //1 | |
599 | l2sat_coverage_ifc.arbdp_inst_rsvd_c1_0, //0 | |
600 | l2sat_coverage_ifc.arbctl_stall_c2_0, | |
601 | l2sat_coverage_ifc.arbctl_inst_vld_c1_0, | |
602 | l2sat_coverage_ifc.arbdp_inst_fb_c1_0, | |
603 | l2sat_coverage_ifc.arbdp_tecc_c1_0}) { | |
604 | #inc "l2_stalled_scrub2_sample.vrhpal"; | |
605 | } | |
606 | ||
607 | sample l2_vuad_bypass_cov ({l2sat_coverage_ifc.arbctl_inst_vld_c1_0, | |
608 | l2sat_coverage_ifc.vuad_sel_c2orc3_0, | |
609 | l2sat_coverage_ifc.vuad_sel_c2_0, | |
610 | l2sat_coverage_ifc.vuad_sel_c4orc5_0, | |
611 | l2sat_coverage_ifc.vuad_sel_c4_0}) { | |
612 | #inc "l2_vuad_bypass_sample.vrhpal"; | |
613 | } | |
614 | #endif | |
615 | ||
616 | // added to FC following 1; 10/25/05 | |
617 | sample l2_inst_flow_cov ({l2sat_coverage_ifc.tagctl_hit_l2orfb_c2_0, | |
618 | l2sat_coverage_ifc.mbctl_hit_c2_0, | |
619 | l2sat_coverage_ifc.arbdp_inst_mb_c2_0, | |
620 | l2sat_coverage_ifc.arbctl_evict_vld_c2_0, | |
621 | l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
622 | l2sat_coverage_ifc.arbctl_inst_diag_c2_0, | |
623 | l2sat_coverage_ifc.arbdp_inst_c2_0[25:10]}) { | |
624 | #inc "l2_inst_flow_sample.vrhpal"; | |
625 | } | |
626 | ||
627 | ||
628 | #ifndef L2_INTF_COV | |
629 | sample l2_buffer_hits_cov ({l2sat_coverage_ifc.mbctl_hit_c2_0, | |
630 | l2sat_coverage_ifc.fbctl_mbctl_match_c2_0, | |
631 | l2sat_coverage_ifc.wbctl_hit_qual_c2_0, | |
632 | l2sat_coverage_ifc.rdmatctl_hit_qual_c2_0, | |
633 | l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
634 | l2sat_coverage_ifc.arbctl_inst_diag_c2_0, | |
635 | l2sat_coverage_ifc.arbdp_inst_c2_0[25:10]}) { //review check all references to inst19:5 | |
636 | #inc "l2_buffer_hits_sample.vrhpal"; | |
637 | } | |
638 | ||
639 | sample l2_pipeline_arbiter_cov ({l2sat_coverage_ifc.mbf_valid_px2_0, | |
640 | l2sat_coverage_ifc.fbf_valid_px2_0, | |
641 | l2sat_coverage_ifc.snp_valid_px2_0, | |
642 | l2sat_coverage_ifc.ique_iq_arb_atm_px2_0, | |
643 | l2sat_coverage_ifc.arb_stall_c2_0, | |
644 | l2sat_coverage_ifc.iqu_iq_arb_vld_px2_0}){ | |
645 | #inc "l2_pipeline_arbiter_sample.vrhpal"; | |
646 | } | |
647 | #endif | |
648 | ||
649 | // added to FC following 1; but commented out; 10/25/05 | |
650 | // - new cov obj | |
651 | /* sample l2_dram_arbiter_cov ({}){ | |
652 | }*/ | |
653 | ||
654 | #ifndef L2_INTF_COV | |
655 | sample l2_store_pipelining_cov ({l2sat_coverage_ifc.arbctl_inst_vld_c3_0, | |
656 | l2sat_coverage_ifc.arb_decdp_st_inst_c3_0, | |
657 | l2sat_coverage_ifc.misbuf_dep_inst_c3_0, | |
658 | l2sat_coverage_ifc.mbf_insert_c3_0, | |
659 | l2sat_coverage_ifc.tag_hit_c3_0, | |
660 | l2sat_coverage_ifc.arb_vuad_ce_err_c3_0}){ | |
661 | #inc "l2_store_pipelining_sample.vrhpal"; | |
662 | } | |
663 | #endif | |
664 | } // end of "coverage_group l2sat_pipeline_coverage_group" | |
665 | ||
666 | ||
667 | coverage_group l2sat_offmode_directmap_coverage_group | |
668 | { | |
669 | ||
670 | sample_event = @(posedge CLOCK); | |
671 | ||
672 | // added to FC following 1; 10/25/05 | |
673 | sample l2_offmode_directmap_insts_cov ({l2sat_coverage_ifc.l2_bypass_mode_on_d1_0, | |
674 | l2sat_coverage_ifc.l2_dir_map_on_d1_0, | |
675 | l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
676 | l2sat_coverage_ifc.arbctl_inst_diag_c2_0, | |
677 | l2sat_coverage_ifc.arbdp_inst_c2_0[25:10]}) { | |
678 | #inc "l2_offmode_directmap_insts_sample.vrhpal"; | |
679 | } | |
680 | } // end of "coverage_group l2sat_offmode_directmap_coverage_group" | |
681 | ||
682 | ||
683 | coverage_group l2sat_intf_coverage_group | |
684 | { | |
685 | ||
686 | sample_event = @(posedge CLOCK); | |
687 | ||
688 | ///////////////////////////////// | |
689 | // L2->SIU interface coverages | |
690 | ///////////////////////////////// | |
691 | ||
692 | sample l2siu_intf_fields_cov ({l2sat_coverage_ifc.sii_l2t0_req_vld, | |
693 | l2sat_coverage_ifc.sii_l2t0_req[31:0]}) { | |
694 | #inc "l2_siu_fields_sample.vrhpal"; | |
695 | } | |
696 | ||
697 | sample l2siu_intf_ctagecc_cov({l2sat_coverage_ifc.sii_l2t0_req_vld, | |
698 | l2sat_coverage_ifc.sii_l2b0_ecc}){ | |
699 | wildcard state SIU_CTAG_ECC_BIT0_0 ({1'b1, 5'bx, 1'b0}); | |
700 | wildcard state SIU_CTAG_ECC_BIT0_1 ({1'b1, 5'bx, 1'b1}); | |
701 | wildcard state SIU_CTAG_ECC_BIT1_0 ({1'b1, 4'bx, 1'b0, 1'bx}); | |
702 | wildcard state SIU_CTAG_ECC_BIT1_1 ({1'b1, 4'bx, 1'b1, 1'bx}); | |
703 | wildcard state SIU_CTAG_ECC_BIT2_0 ({1'b1, 3'bx, 1'b0, 2'bx}); | |
704 | wildcard state SIU_CTAG_ECC_BIT2_1 ({1'b1, 3'bx, 1'b1, 2'bx}); | |
705 | wildcard state SIU_CTAG_ECC_BIT3_0 ({1'b1, 2'bx, 1'b0, 3'bx}); | |
706 | wildcard state SIU_CTAG_ECC_BIT3_1 ({1'b1, 2'bx, 1'b1, 3'bx}); | |
707 | wildcard state SIU_CTAG_ECC_BIT4_0 ({1'b1, 1'bx, 1'b0, 4'bx}); | |
708 | wildcard state SIU_CTAG_ECC_BIT4_1 ({1'b1, 1'bx, 1'b1, 4'bx}); | |
709 | wildcard state SIU_CTAG_ECC_BIT5_0 ({1'b1, 1'b0, 5'bx}); | |
710 | wildcard state SIU_CTAG_ECC_BIT5_1 ({1'b1, 1'b1, 5'bx}); | |
711 | } | |
712 | ||
713 | //#ifndef SIU_INTF_COV | |
714 | sample l2siu_intf_bytemask_cov({l2sat_coverage_ifc.sii_l2t0_req_vld, | |
715 | l2sat_coverage_ifc.sii_l2t0_req[15:8]}){ | |
716 | m_state SIU_BYTEMASK(256:511); | |
717 | } | |
718 | //#else | |
719 | //sample l2siu_intf_bytemask_cov({(l2sat_coverage_ifc.sii_l2t0_req_vld || l2sat_coverage_ifc.sii_l2t1_req_vld || l2sat_coverage_ifc.sii_l2t2_req_vld || l2sat_coverage_ifc.sii_l2t3_req_vld || l2sat_coverage_ifc.sii_l2t4_req_vld || l2sat_coverage_ifc.sii_l2t5_req_vld || l2sat_coverage_ifc.sii_l2t6_req_vld || l2sat_coverage_ifc.sii_l2t7_req_vld), | |
720 | // (l2sat_coverage_ifc.sii_l2t0_req_pkt[15:8] || l2sat_coverage_ifc.sii_l2t1_req_pkt[15:8] || l2sat_coverage_ifc.sii_l2t2_req_pkt[15:8] || l2sat_coverage_ifc.sii_l2t3_req_pkt[15:8] || l2sat_coverage_ifc.sii_l2t4_req_pkt[15:8] || l2sat_coverage_ifc.sii_l2t5_req_pkt[15:8] || l2sat_coverage_ifc.sii_l2t6_req_pkt[15:8] || l2sat_coverage_ifc.sii_l2t7_req_pkt[15:8])}) | |
721 | //{ | |
722 | //m_state SIU_BYTEMASK(256:511); | |
723 | //} | |
724 | //#endif | |
725 | ||
726 | ||
727 | // End of L2->SIU interface coverages | |
728 | ||
729 | ||
730 | /////////////////////////// | |
731 | // L2 internal coverages | |
732 | //////////////////////////// | |
733 | ||
734 | // added to FC following 2; 10/25/05 | |
735 | sample l2_snpiq_valid_cov (l2sat_coverage_ifc.snpq_valid_0) { | |
736 | #inc "l2_snpiq_valid_sample.vrhpal"; | |
737 | } | |
738 | ||
739 | sample l2_rdmawb_valid_cov (l2sat_coverage_ifc.rdma_valid_0) { | |
740 | #inc "l2_rdmawb_valid_sample.vrhpal"; | |
741 | } | |
742 | } // end of 'coverage_group l2sat_intf_coverage_group" | |
743 | ||
744 | ||
745 | coverage_group l2sat_error_coverage_group | |
746 | { | |
747 | ||
748 | sample_event = @(posedge CLOCK); | |
749 | ||
750 | sample l2_error_status_reg_cov ({l2sat_coverage_ifc.err_state_new_c9_0[63:32], | |
751 | l2sat_coverage_ifc.err_status_in_0[63:32]}) { | |
752 | #inc "l2_error_status_reg_sample.vrhpal"; | |
753 | } | |
754 | ||
755 | sample l2_notdata_error_reg_cov ({l2sat_coverage_ifc.err_state_notdata_new_c9_0, | |
756 | l2sat_coverage_ifc.err_status_notdata_in_0}) { | |
757 | #inc "l2_notdata_error_reg_sample.vrhpal"; | |
758 | } | |
759 | #ifdef L2_INTF_COV | |
760 | ||
761 | // added to FC following 1; 11/16/05 | |
762 | sample l2_error_in_offmode_cov ({l2sat_coverage_ifc.l2_bypass_mode_on_d1_0, | |
763 | l2sat_coverage_ifc.fbuerr0_d1_0, | |
764 | l2sat_coverage_ifc.fbcerr0_d1_0, | |
765 | l2sat_coverage_ifc.fbctl_hit_c2_0, | |
766 | l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
767 | l2sat_coverage_ifc.arbctl_inst_diag_c2_0, | |
768 | l2sat_coverage_ifc.arbdp_inst_c2_0[25:10]}) { | |
769 | #inc "l2_error_offmode_sample_fc.vrhpal"; | |
770 | } | |
771 | #endif | |
772 | ||
773 | ||
774 | ||
775 | #ifndef L2_INTF_COV | |
776 | sample l2_error_trans_cov ({l2sat_coverage_ifc.csr_l2_errstate_reg_0[63:62], // MEU, MEC review double check these bit slices | |
777 | l2sat_coverage_ifc.csr_l2_errstate_reg_0[35], // VEU | |
778 | l2sat_coverage_ifc.csr_l2_errstate_reg_0[36]}) { // VEC | |
779 | #inc "l2_error_trans_sample.vrhpal"; | |
780 | } | |
781 | ||
782 | sample l2_notdata_error_trans_cov ({l2sat_coverage_ifc.csr_l2_notdata_reg_0[45:44], l2sat_coverage_ifc.csr_l2_notdata_reg_0[47]}) { // VEC | |
783 | #inc "l2_notdata_error_trans_sample.vrhpal"; | |
784 | } | |
785 | ||
786 | sample l2_error_tag_cov ({l2sat_coverage_ifc.mbctl_hit_c2_0, | |
787 | l2sat_coverage_ifc.tecc_c2_0, | |
788 | l2sat_coverage_ifc.tagctl_hit_l2orfb_c2_0, | |
789 | l2sat_coverage_ifc.par_err_c2_0, | |
790 | l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
791 | l2sat_coverage_ifc.arbctl_inst_diag_c2_0, | |
792 | l2sat_coverage_ifc.arbdp_pst_with_ctrue_c2_0, | |
793 | l2sat_coverage_ifc.arbdp_inst_c2_0[25:10]}) { | |
794 | #inc "l2_error_tag_sample.vrhpal"; | |
795 | } | |
796 | ||
797 | ||
798 | // added to FC following 1; 10/25/05 | |
799 | sample l2_error_offmode_cov ({l2sat_coverage_ifc.l2_bypass_mode_on_d1_0, | |
800 | l2sat_coverage_ifc.fbuerr0_d1_0, | |
801 | l2sat_coverage_ifc.fbcerr0_d1_0, | |
802 | l2sat_coverage_ifc.fbctl_hit_c2_0, | |
803 | l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
804 | l2sat_coverage_ifc.arbctl_inst_diag_c2_0, | |
805 | l2sat_coverage_ifc.arbdp_inst_c2_0[25:10]}) { | |
806 | #inc "l2_error_offmode_sample.vrhpal"; | |
807 | } | |
808 | ||
809 | sample l2_scrub_stall_cov ({l2sat_coverage_ifc.arbctl_inst_vld_c1_0, | |
810 | l2sat_coverage_ifc.arbdp_inst_fb_c1_0, | |
811 | l2sat_coverage_ifc.arbdp_tecc_c1_0, | |
812 | l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
813 | l2sat_coverage_ifc.arbctl_fill_vld_c2_0, | |
814 | l2sat_coverage_ifc.tecc_c2_0}) { | |
815 | #inc "l2_scrub_stall_sample.vrhpal"; | |
816 | } | |
817 | ||
818 | sample l2_pst1_dataerr_pst2_tagerr_cov (l2_pst1_dataerr_pst2_tagerr_samp_trigger) { | |
819 | #inc "l2_pst1_dataerr_pst2_tagerr_sample.vrhpal"; | |
820 | } | |
821 | ||
822 | sample l2_tecc_writeback_cov ({l2sat_coverage_ifc.arbctl_inst_vld_c2_0, | |
823 | l2sat_coverage_ifc.par_err_c2_0, | |
824 | l2sat_coverage_ifc.tecc_c2_0, | |
825 | l2sat_coverage_ifc.wbctl_hit_qual_c2_0, | |
826 | l2sat_coverage_ifc.rdmatctl_hit_qual_c2_0}) { | |
827 | #inc "l2_tecc_writeback_sample.vrhpal"; | |
828 | } | |
829 | /* | |
830 | sample l2_error_vuad_ce_cov({l2sat_coverage_ifc.vlddir_valid_c2_0[0], | |
831 | l2sat_coverage_ifc.vlddir_valid_corr_c2_0[0], | |
832 | l2sat_coverage_ifc.l2t_l2d_way_sel_c2_0[0], | |
833 | l2sat_coverage_ifc.tag_hit_unqual_c2_0, | |
834 | l2sat_coverage_ifc.arb_vuad_ce_err_c2_0}){ | |
835 | //#inc "l2_error_vuad_ce_samp.vrhpal"; | |
836 | } | |
837 | */ | |
838 | ||
839 | sample l2_error_vuad_ecc_inst_cov(l2_error_vuad_ecc_samp_trigger){ | |
840 | #inc "l2_error_vuad_ecc_sample.vrhpal"; | |
841 | } | |
842 | ||
843 | sample l2_two_simultaneous_errors_cov({l2sat_coverage_ifc.err_state_new_c9_0[53:37], | |
844 | l2sat_coverage_ifc.err_state_new_c9_0[34], | |
845 | l2sat_coverage_ifc.err_state_notdata_new_c9_0} ){ | |
846 | #inc "l2_two_simultaneous_errors_sample.vrhpal"; | |
847 | } | |
848 | ||
849 | sample l2_two_successive_errors_cov({l2sat_coverage_ifc.err_state_new_c9_0[53:45], | |
850 | l2sat_coverage_ifc.err_state_new_c9_0[42:37], | |
851 | l2sat_coverage_ifc.err_state_new_c9_0[34], | |
852 | l2sat_coverage_ifc.err_state_notdata_new_c9_0, | |
853 | l2sat_coverage_ifc.csr_l2_errstate_reg_0[53:45], | |
854 | l2sat_coverage_ifc.csr_l2_errstate_reg_0[42:37], | |
855 | l2sat_coverage_ifc.csr_l2_errstate_reg_0[34], | |
856 | l2sat_coverage_ifc.csr_l2_notdata_reg_0[45:44]}){ | |
857 | . &two_errors(18); | |
858 | } | |
859 | #endif | |
860 | ||
861 | //added to FC following one for PM targeted 11/16 | |
862 | sample l2_dir_scrub_cov({l2sat_coverage_ifc.dir_addr_cnt_0}){ | |
863 | trans DIR_CNT_WRAP_AROUND (11'b111_1111_1111 -> 11'h0); | |
864 | } | |
865 | ||
866 | #ifndef L2_INTF_COV | |
867 | sample l2_tag_scrub_cov({l2sat_coverage_ifc.arb_tecc_way_c2_0, l2sat_coverage_ifc.tecc_st_cnt_0}){ | |
868 | wildcard state TECC_WAY_15 (12'b1111_xxxx_xxxx); | |
869 | wildcard trans TECC_CNT_WRAP_AROUND (12'bxxxx_1000_0000 -> 12'bxxxx_0000_0000); | |
870 | } | |
871 | ||
872 | sample l2_data_scrub_cov({l2sat_coverage_ifc.arbadr_data_ecc_idx_0}){ | |
873 | wildcard trans DECC_CNT_WRAP_AROUND (9'b1_1111_1111 -> 9'h0); | |
874 | } | |
875 | #endif | |
876 | ||
877 | } // end of "coverage_group l2sat_error_coverage_group" | |
878 | ||
879 | ||
880 | // #ifdef L2_INTF_COV | |
881 | coverage_group l2_cpx_packet_coverage_group | |
882 | { | |
883 | const_sample_reference = 1; // ref. to sample vars. is constant | |
884 | sample_event = sync (ANY, l2t0_cpx_error_pkt1_evnt_trig, l2t0_cpx_error_pkt4_evnt_trig, l2t0_cpx_error_pkt5_evnt_trig ); | |
885 | #include "l2_fc_error_allpkttype_sample.vrh" | |
886 | ||
887 | } // l2_cpx_packet_coverage_group | |
888 | ||
889 | coverage_group l2_cpx_packet_bank_coverage_group | |
890 | { | |
891 | const_sample_reference = 1; // ref. to sample vars. is constant | |
892 | sample_event = sync (ANY, l2t0_cpx_error_bank0_evnt_trig, l2t0_cpx_error_bank1_evnt_trig, l2t0_cpx_error_bank2_evnt_trig, l2t0_cpx_error_bank3_evnt_trig, l2t0_cpx_error_bank4_evnt_trig, l2t0_cpx_error_bank5_evnt_trig, l2t0_cpx_error_bank6_evnt_trig, l2t0_cpx_error_bank7_evnt_trig ); | |
893 | #include "l2_fc_error_allbank_sample.vrh" | |
894 | ||
895 | } // l2_cpx_packet_bank_coverage_group | |
896 | ||
897 | coverage_group l2_cpx_packet_anybank_coverage_group | |
898 | { | |
899 | const_sample_reference = 1; // ref. to sample vars. is constant | |
900 | sample_event = sync (ANY, l2t0_cpx_anybank_error_evnt_trig ); | |
901 | #include "l2_fc_error_allbankerror_sample.vrh" | |
902 | ||
903 | } // l2_cpx_packet_anybank_coverage_group | |
904 | ||
905 | coverage_group l2_cpx_packet_bank_thread_coverage_group | |
906 | { | |
907 | const_sample_reference = 1; // ref. to sample vars. is constant | |
908 | sample_event = sync (ANY, l2t0_cpx_error_bank2_thread_evnt_trig, l2t0_cpx_error_bank3_thread_evnt_trig, l2t0_cpx_error_bank4_thread_evnt_trig, l2t0_cpx_error_bank5_thread_evnt_trig, l2t0_cpx_error_bank6_thread_evnt_trig, l2t0_cpx_error_bank7_thread_evnt_trig, l2t0_cpx_error_bank8_thread_evnt_trig ); | |
909 | #include "l2_fc_error_allbank_thread_sample.vrh" | |
910 | ||
911 | } // l2_cpx_packet_bank_thread_coverage_group | |
912 | ||
913 | coverage_group l2_cpx_packet_bank_error_coverage_group | |
914 | { | |
915 | const_sample_reference = 1; // ref. to sample vars. is constant | |
916 | sample_event = sync (ANY, l2t0_cpx_bank_error_evnt_trig ); | |
917 | #include "l2_fc_error_allbank_error_sample.vrh" | |
918 | ||
919 | } // l2_cpx_packet_bank_error_coverage_group | |
920 | ||
921 | ||
922 | ||
923 | // #endif | |
924 | ||
925 | coverage_group l2sat_partial_corebank_coverage_group | |
926 | { | |
927 | sample_event = @(posedge CLOCK); | |
928 | ||
929 | ///////////////////////////////// | |
930 | // NCU->L2 interface coverages | |
931 | ///////////////////////////////// | |
932 | ||
933 | sample l2_two_banks_combo ({l2sat_coverage_ifc.ncu_l2t_pm_0, | |
934 | l2sat_coverage_ifc.ncu_l2t_ba01_0, | |
935 | l2sat_coverage_ifc.ncu_l2t_ba23_0, | |
936 | l2sat_coverage_ifc.ncu_l2t_ba45_0, | |
937 | l2sat_coverage_ifc.ncu_l2t_ba67_0}){ | |
938 | state b01 (5'b10001); | |
939 | state b23 (5'b10010); | |
940 | state b45 (5'b10100); | |
941 | state b67 (5'b11000); | |
942 | cov_weight = 0; | |
943 | } | |
944 | ||
945 | sample l2_four_banks_combo ({l2sat_coverage_ifc.ncu_l2t_pm_0, | |
946 | l2sat_coverage_ifc.ncu_l2t_ba01_0, | |
947 | l2sat_coverage_ifc.ncu_l2t_ba23_0, | |
948 | l2sat_coverage_ifc.ncu_l2t_ba45_0, | |
949 | l2sat_coverage_ifc.ncu_l2t_ba67_0}){ | |
950 | state b0123 (5'b10011); | |
951 | state b0145 (5'b10101); | |
952 | state b2345 (5'b10110); | |
953 | state b0167 (5'b11001); | |
954 | state b2367 (5'b11010); | |
955 | state b4567 (5'b11100); | |
956 | cov_weight = 0; | |
957 | } | |
958 | ||
959 | // sample l2_eight_banks_combo ({l2sat_coverage_ifc.ncu_l2t_pm_0, | |
960 | // l2sat_coverage_ifc.ncu_l2t_ba01_0, | |
961 | // l2sat_coverage_ifc.ncu_l2t_ba23_0, | |
962 | // l2sat_coverage_ifc.ncu_l2t_ba45_0, | |
963 | // l2sat_coverage_ifc.ncu_l2t_ba67_0}){ | |
964 | // state all_banks (5'b11111); | |
965 | // cov_weight = 0; | |
966 | // } | |
967 | ||
968 | ///////////////////////////////// | |
969 | // NCU->CORE interface coverages | |
970 | ///////////////////////////////// | |
971 | ||
972 | // sample l2_eight_cores_combo ({l2sat_coverage_ifc.ncu_spc0_core_enable_status_0, | |
973 | // l2sat_coverage_ifc.ncu_spc1_core_enable_status_0, | |
974 | // l2sat_coverage_ifc.ncu_spc2_core_enable_status_0, | |
975 | // l2sat_coverage_ifc.ncu_spc3_core_enable_status_0, | |
976 | // l2sat_coverage_ifc.ncu_spc4_core_enable_status_0, | |
977 | // l2sat_coverage_ifc.ncu_spc5_core_enable_status_0, | |
978 | // l2sat_coverage_ifc.ncu_spc6_core_enable_status_0, | |
979 | // l2sat_coverage_ifc.ncu_spc7_core_enable_status_0}) { | |
980 | // cov_weight = 0; | |
981 | // m_state (0:255); | |
982 | // //wildcard state (8'bxxxxxxxx); | |
983 | // } | |
984 | ||
985 | sample l2_four_cores_combo ({l2sat_coverage_ifc.ncu_spc0_core_enable_status_0, | |
986 | l2sat_coverage_ifc.ncu_spc1_core_enable_status_0, | |
987 | l2sat_coverage_ifc.ncu_spc2_core_enable_status_0, | |
988 | l2sat_coverage_ifc.ncu_spc3_core_enable_status_0, | |
989 | l2sat_coverage_ifc.ncu_spc4_core_enable_status_0, | |
990 | l2sat_coverage_ifc.ncu_spc5_core_enable_status_0, | |
991 | l2sat_coverage_ifc.ncu_spc6_core_enable_status_0, | |
992 | l2sat_coverage_ifc.ncu_spc7_core_enable_status_0}) { | |
993 | cov_weight = 0; | |
994 | .&partial_cores(8, 4); | |
995 | } | |
996 | ||
997 | sample l2_two_cores_combo ({l2sat_coverage_ifc.ncu_spc0_core_enable_status_0, | |
998 | l2sat_coverage_ifc.ncu_spc1_core_enable_status_0, | |
999 | l2sat_coverage_ifc.ncu_spc2_core_enable_status_0, | |
1000 | l2sat_coverage_ifc.ncu_spc3_core_enable_status_0, | |
1001 | l2sat_coverage_ifc.ncu_spc4_core_enable_status_0, | |
1002 | l2sat_coverage_ifc.ncu_spc5_core_enable_status_0, | |
1003 | l2sat_coverage_ifc.ncu_spc6_core_enable_status_0, | |
1004 | l2sat_coverage_ifc.ncu_spc7_core_enable_status_0}) { | |
1005 | cov_weight = 0; | |
1006 | .&partial_cores(8, 2); | |
1007 | } | |
1008 | ||
1009 | cross l2_two_banks_partial_cores_cov (l2_two_banks_combo, l2_two_cores_combo); | |
1010 | cross l2_four_banks_partial_cores_cov (l2_four_banks_combo, l2_four_cores_combo); | |
1011 | // cross l2_eight_banks_partial_cores_cov (l2_eight_banks_combo, l2_eight_cores_combo); | |
1012 | ||
1013 | } // end of "coverage_group l2sat_partial_corebank_coverage_group" | |
1014 | // end of NCU interface coverages | |
1015 | ||
1016 | ||
1017 | coverage_group l2sat_buffers_CAM_coverage_group | |
1018 | { | |
1019 | ||
1020 | sample_event = @(posedge CLOCK); | |
1021 | ||
1022 | #ifndef L2_INTF_COV | |
1023 | sample l2_fb_wb_iowb_cam_results_cov ({l2sat_coverage_ifc.fb_cam_match[7:0], | |
1024 | l2sat_coverage_ifc.fb_valid[7:0], | |
1025 | l2sat_coverage_ifc.wb_cam_match_c2[7:0], | |
1026 | l2sat_coverage_ifc.wb_valid[7:0], | |
1027 | l2sat_coverage_ifc.rdmat_cam_match_c2[3:0], | |
1028 | l2sat_coverage_ifc.rdma_valid[3:0]}){ | |
1029 | #inc "l2_fb_wb_iowb_cam_results_sample.vrhpal"; | |
1030 | } | |
1031 | #endif | |
1032 | } // end of "coverage_group l2sat_buffers_CAM_coverage_group" | |
1033 | ||
1034 | ||
1035 | task new(StandardDisplay dbg); | |
1036 | task set_cov_cond_bits (); | |
1037 | task count_coverage(); | |
1038 | ||
1039 | } //class l2sat_intf_coverage_class | |
1040 | ||
1041 | ///////////////////////////////////////////////////////////////// | |
1042 | // Class creation | |
1043 | ///////////////////////////////////////////////////////////////// | |
1044 | task l2sat_intf_coverage_class::count_coverage() { | |
1045 | ||
1046 | l2sat_intf_coverage_group.set_cov_weight(1); | |
1047 | l2sat_ccx_coverage_group.set_cov_weight(1); | |
1048 | l2sat_input_queue_coverage_group.set_cov_weight(1); | |
1049 | l2sat_output_queue_coverage_group.set_cov_weight(1); | |
1050 | l2sat_directory_coverage_group.set_cov_weight(1); | |
1051 | l2sat_missbuffer_coverage_group.set_cov_weight(1); | |
1052 | l2sat_fillbuffer_coverage_group.set_cov_weight(1); | |
1053 | l2sat_write_back_buffer_group.set_cov_weight(1); | |
1054 | l2sat_pipeline_coverage_group.set_cov_weight(1); | |
1055 | //if(get_plus_arg(CHECK, "directmapped_mode") || get_plus_arg(CHECK, "off_mode") || get_plus_arg(CHECK, "l2_mode")) | |
1056 | l2sat_offmode_directmap_coverage_group.set_cov_weight(1); | |
1057 | //else | |
1058 | // l2sat_offmode_directmap_coverage_group.set_cov_weight(0); | |
1059 | l2sat_error_coverage_group.set_cov_weight(1); | |
1060 | //if(get_plus_arg(CHECK, "twobanks_mode") || get_plus_arg(CHECK, "fourbanks_mode") || get_plus_arg(CHECK, "l2_mode")) | |
1061 | l2sat_partial_corebank_coverage_group.set_cov_weight(1); | |
1062 | //else | |
1063 | // l2sat_partial_corebank_coverage_group.set_cov_weight(0); | |
1064 | l2sat_buffers_CAM_coverage_group.set_cov_weight(1); | |
1065 | ||
1066 | coverage_save_database(1); | |
1067 | printf("COVERAGE: coverage database saved\n"); | |
1068 | ||
1069 | } | |
1070 | ||
1071 | ||
1072 | task l2sat_intf_coverage_class::new(StandardDisplay dbg) | |
1073 | { | |
1074 | bit coverage_on; | |
1075 | integer j; | |
1076 | ||
1077 | // for dispmon | |
1078 | myname = "l2sat_intf_coverage_class"; | |
1079 | this.dbg = dbg; | |
1080 | ||
1081 | if (mChkPlusarg(l2sat_intf_coverage) || mChkPlusarg(coverage_on)) { | |
1082 | ||
1083 | coverage_on = 1; | |
1084 | if (mChkPlusarg(l2sat_intf_cov_debug)) { | |
1085 | l2sat_intf_cov_debug = 1'b1; | |
1086 | } | |
1087 | } else { | |
1088 | coverage_on = 0; | |
1089 | } | |
1090 | ||
1091 | if (coverage_on) { | |
1092 | l2sat_intf_coverage_group = new(); | |
1093 | l2sat_ccx_coverage_group = new(); | |
1094 | l2sat_input_queue_coverage_group = new(); | |
1095 | l2sat_output_queue_coverage_group = new(); | |
1096 | l2sat_directory_coverage_group = new(); | |
1097 | l2sat_missbuffer_coverage_group = new(); | |
1098 | l2sat_fillbuffer_coverage_group = new(); | |
1099 | l2sat_write_back_buffer_group = new(); | |
1100 | l2sat_pipeline_coverage_group = new(); | |
1101 | l2sat_offmode_directmap_coverage_group = new(); | |
1102 | l2sat_error_coverage_group = new(); | |
1103 | l2sat_partial_corebank_coverage_group = new(); | |
1104 | l2sat_buffers_CAM_coverage_group = new(); | |
1105 | ||
1106 | set_cov_cond_bits(); | |
1107 | ||
1108 | ||
1109 | //set_cov_cond_bits (); | |
1110 | ||
1111 | printf("COVERAGE: flag coverage_on==%d\n",coverage_on); | |
1112 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :COVERAGE turned on for L2SAT l2sat_intf_coverage_group\n\n", get_time(LO))); | |
1113 | ||
1114 | //fork { | |
1115 | // @ (posedge l2sat_coverage_ifc.cmp_diag_done); | |
1116 | // l2sat_intf_coverage_group.set_cov_weight(1); | |
1117 | // coverage_save_database(1); | |
1118 | // dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage for L2SAT objects generated\n\n", get_time(LO))); | |
1119 | //} join none | |
1120 | } // if coverage_on | |
1121 | } // l2sat_intf_coverage::new() | |
1122 | ||
1123 | // ************************************************************************************** | |
1124 | // Adding Internal coverage objects of FC for L2 MAQ | |
1125 | // ************************************************************************************** | |
1126 | ||
1127 | class fc_l2_internal_coverage | |
1128 | { | |
1129 | // for dispmon | |
1130 | StandardDisplay dbg; | |
1131 | local string myname; | |
1132 | reg l2_gnt_active_list = 0; | |
1133 | reg l2_gnt_active_0 = 0; | |
1134 | reg l2_gnt_active_1 = 0; | |
1135 | reg l2_gnt_active_2 = 0; | |
1136 | reg l2_gnt_active_3 = 0; | |
1137 | reg l2_gnt_active_4 = 0; | |
1138 | reg l2_gnt_active_5 = 0; | |
1139 | reg l2_gnt_active_6 = 0; | |
1140 | reg l2_gnt_active_7 = 0; | |
1141 | ||
1142 | // ----------- coverage_group ---------------- | |
1143 | coverage_group l2_gnt_activity_coverage_group | |
1144 | { | |
1145 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1146 | sample_event = @(posedge l2_siu_ccx_intf.clk); | |
1147 | . for ($z=0; $z < 8; $z++) | |
1148 | . { | |
1149 | ||
1150 | sample l2_gnt_active_bank${z} (l2_gnt_active_${z}) | |
1151 | { | |
1152 | state l2_ccx_siu_activity_${z} (1'b1); | |
1153 | } | |
1154 | . } | |
1155 | ||
1156 | } | |
1157 | ||
1158 | task new(StandardDisplay dbg); | |
1159 | task set_cov_cond_bits (); | |
1160 | task l2_gnt_active_task(); | |
1161 | ||
1162 | } //class fc_l2_internal_coverage | |
1163 | ||
1164 | task fc_l2_internal_coverage::new(StandardDisplay dbg) | |
1165 | { | |
1166 | bit coverage_on = 0; | |
1167 | integer j; | |
1168 | ||
1169 | // for dispmon | |
1170 | myname = "fc_l2_internal_coverage"; | |
1171 | this.dbg = dbg; | |
1172 | ||
1173 | if (mChkPlusarg(fc_l2_internal_coverage) || mChkPlusarg(coverage_on)) { | |
1174 | coverage_on = 1; | |
1175 | // printf("MAQ-Debug: CPU Internal Coverage Turned On \n"); | |
1176 | } | |
1177 | ||
1178 | if (coverage_on) { | |
1179 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Internal Coverage turned on for SIU/L2 objects\n\n", get_time(LO))); | |
1180 | set_cov_cond_bits (); | |
1181 | } | |
1182 | } | |
1183 | ||
1184 | task fc_l2_internal_coverage:: set_cov_cond_bits () | |
1185 | { | |
1186 | fork | |
1187 | l2_gnt_active_task(); | |
1188 | join none | |
1189 | ||
1190 | } // task fc_l2_internal_coverage:: set_cov_cond_bits | |
1191 | ||
1192 | task fc_l2_internal_coverage::l2_gnt_active_task() | |
1193 | { | |
1194 | ||
1195 | while(1) | |
1196 | { | |
1197 | @(negedge l2_siu_ccx_intf.clk); | |
1198 | { | |
1199 | l2_gnt_active_0 = (|(l2_siu_ccx_intf.sctag0_cpx_req_cq[7:0])) & (l2_siu_ccx_intf.l2b0_sio_ctag_vld); | |
1200 | l2_gnt_active_1 = (|(l2_siu_ccx_intf.sctag1_cpx_req_cq[7:0])) & (l2_siu_ccx_intf.l2b1_sio_ctag_vld); | |
1201 | l2_gnt_active_2 = (|(l2_siu_ccx_intf.sctag2_cpx_req_cq[7:0])) & (l2_siu_ccx_intf.l2b2_sio_ctag_vld); | |
1202 | l2_gnt_active_3 = (|(l2_siu_ccx_intf.sctag3_cpx_req_cq[7:0])) & (l2_siu_ccx_intf.l2b3_sio_ctag_vld); | |
1203 | l2_gnt_active_4 = (|(l2_siu_ccx_intf.sctag4_cpx_req_cq[7:0])) & (l2_siu_ccx_intf.l2b4_sio_ctag_vld); | |
1204 | l2_gnt_active_5 = (|(l2_siu_ccx_intf.sctag5_cpx_req_cq[7:0])) & (l2_siu_ccx_intf.l2b5_sio_ctag_vld); | |
1205 | l2_gnt_active_6 = (|(l2_siu_ccx_intf.sctag6_cpx_req_cq[7:0])) & (l2_siu_ccx_intf.l2b6_sio_ctag_vld); | |
1206 | l2_gnt_active_7 = (|(l2_siu_ccx_intf.sctag7_cpx_req_cq[7:0])) & (l2_siu_ccx_intf.l2b7_sio_ctag_vld); | |
1207 | l2_gnt_active_list = (|{l2_gnt_active_0, l2_gnt_active_1, l2_gnt_active_2, l2_gnt_active_3, l2_gnt_active_4, l2_gnt_active_5, l2_gnt_active_6, l2_gnt_active_7}); | |
1208 | if(l2_gnt_active_list == 1) | |
1209 | dbg.dispmon(myname, MON_ALWAYS, psprintf("\n\n %d :l2_gnt_active_list HIT \n\n", get_time(LO))); | |
1210 | } | |
1211 | } // While | |
1212 | ||
1213 | } | |
1214 | ||
1215 | ||
1216 | // ************************************************************************************** | |
1217 | ||
1218 | ||
1219 | task l2sat_intf_coverage_class:: set_cov_cond_bits () | |
1220 | { | |
1221 | ||
1222 | fork | |
1223 | { | |
1224 | while (1) | |
1225 | { | |
1226 | @(posedge l2_ras_intf.clk); | |
1227 | l2t0_type1 = l2_ras_intf.l2t0_cpx_data[139:138] ; | |
1228 | if ( l2_ras_intf.l2t0_cpx_data[145] === 1'b1 && l2_ras_intf.l2t0_cpx_data[144:141] === 4'b0000 ) | |
1229 | trigger (l2t0_cpx_error_pkt1_evnt_trig); | |
1230 | ||
1231 | l2t0_type4 = l2_ras_intf.l2t0_cpx_data[139:138] ; | |
1232 | if ( l2_ras_intf.l2t0_cpx_data[145] === 1'b1 && l2_ras_intf.l2t0_cpx_data[144:141] === 4'b1100 ) | |
1233 | trigger (l2t0_cpx_error_pkt4_evnt_trig); | |
1234 | ||
1235 | l2t0_type5 = l2_ras_intf.l2t0_cpx_data[139:138] ; | |
1236 | if ( l2_ras_intf.l2t0_cpx_data[145] === 1'b1 && l2_ras_intf.l2t0_cpx_data[144:141] === 4'b1101 ) | |
1237 | trigger (l2t0_cpx_error_pkt5_evnt_trig); | |
1238 | ||
1239 | l2t0_bank0 = l2_ras_intf.l2t0_cpx_data[139:138] ; | |
1240 | if ( l2_ras_intf.l2t0_cpx_data[145] === 1'b1 && (l2_ras_intf.l2t0_cpx_data[136:134] === 3'b000 | l2_ras_intf.l2t0_cpx_data[136:134] === 3'b001 | l2_ras_intf.l2t0_cpx_data[136:134] === 3'b010 | l2_ras_intf.l2t0_cpx_data[136:134] === 3'b011 | l2_ras_intf.l2t0_cpx_data[136:134] === 3'b100 | l2_ras_intf.l2t0_cpx_data[136:134] === 3'b101 | l2_ras_intf.l2t0_cpx_data[136:134] === 3'b110 | l2_ras_intf.l2t0_cpx_data[136:134] === 3'b111 )) | |
1241 | trigger (l2t0_cpx_error_bank0_evnt_trig); | |
1242 | ||
1243 | l2t0_bank1 = l2_ras_intf.l2t1_cpx_data[139:138] ; | |
1244 | if ( l2_ras_intf.l2t1_cpx_data[145] === 1'b1 && (l2_ras_intf.l2t1_cpx_data[136:134] === 3'b000 | l2_ras_intf.l2t1_cpx_data[136:134] === 3'b001 | l2_ras_intf.l2t1_cpx_data[136:134] === 3'b010 | l2_ras_intf.l2t1_cpx_data[136:134] === 3'b011 | l2_ras_intf.l2t1_cpx_data[136:134] === 3'b100 | l2_ras_intf.l2t1_cpx_data[136:134] === 3'b101 | l2_ras_intf.l2t1_cpx_data[136:134] === 3'b110 | l2_ras_intf.l2t1_cpx_data[136:134] === 3'b111 )) | |
1245 | trigger (l2t0_cpx_error_bank1_evnt_trig); | |
1246 | ||
1247 | l2t0_bank2 = l2_ras_intf.l2t2_cpx_data[139:138] ; | |
1248 | if ( l2_ras_intf.l2t2_cpx_data[145] === 1'b1 && (l2_ras_intf.l2t2_cpx_data[136:134] === 3'b000 | l2_ras_intf.l2t2_cpx_data[136:134] === 3'b001 | l2_ras_intf.l2t2_cpx_data[136:134] === 3'b010 | l2_ras_intf.l2t2_cpx_data[136:134] === 3'b011 | l2_ras_intf.l2t2_cpx_data[136:134] === 3'b100 | l2_ras_intf.l2t2_cpx_data[136:134] === 3'b101 | l2_ras_intf.l2t2_cpx_data[136:134] === 3'b110 | l2_ras_intf.l2t2_cpx_data[136:134] === 3'b111 )) | |
1249 | trigger (l2t0_cpx_error_bank2_evnt_trig); | |
1250 | ||
1251 | l2t0_bank3 = l2_ras_intf.l2t3_cpx_data[139:138] ; | |
1252 | if ( l2_ras_intf.l2t3_cpx_data[145] === 1'b1 && (l2_ras_intf.l2t3_cpx_data[136:134] === 3'b000 | l2_ras_intf.l2t3_cpx_data[136:134] === 3'b001 | l2_ras_intf.l2t3_cpx_data[136:134] === 3'b010 | l2_ras_intf.l2t3_cpx_data[136:134] === 3'b011 | l2_ras_intf.l2t3_cpx_data[136:134] === 3'b100 | l2_ras_intf.l2t3_cpx_data[136:134] === 3'b101 | l2_ras_intf.l2t3_cpx_data[136:134] === 3'b110 | l2_ras_intf.l2t3_cpx_data[136:134] === 3'b111 )) | |
1253 | trigger (l2t0_cpx_error_bank3_evnt_trig); | |
1254 | ||
1255 | l2t0_bank4 = l2_ras_intf.l2t4_cpx_data[139:138] ; | |
1256 | if ( l2_ras_intf.l2t4_cpx_data[145] === 1'b1 && (l2_ras_intf.l2t4_cpx_data[136:134] === 3'b000 | l2_ras_intf.l2t4_cpx_data[136:134] === 3'b001 | l2_ras_intf.l2t4_cpx_data[136:134] === 3'b010 | l2_ras_intf.l2t4_cpx_data[136:134] === 3'b011 | l2_ras_intf.l2t4_cpx_data[136:134] === 3'b100 | l2_ras_intf.l2t4_cpx_data[136:134] === 3'b101 | l2_ras_intf.l2t4_cpx_data[136:134] === 3'b110 | l2_ras_intf.l2t4_cpx_data[136:134] === 3'b111 )) | |
1257 | trigger (l2t0_cpx_error_bank4_evnt_trig); | |
1258 | ||
1259 | l2t0_bank5 = l2_ras_intf.l2t5_cpx_data[139:138] ; | |
1260 | if ( l2_ras_intf.l2t5_cpx_data[145] === 1'b1 && (l2_ras_intf.l2t5_cpx_data[136:134] === 3'b000 | l2_ras_intf.l2t5_cpx_data[136:134] === 3'b001 | l2_ras_intf.l2t5_cpx_data[136:134] === 3'b010 | l2_ras_intf.l2t5_cpx_data[136:134] === 3'b011 | l2_ras_intf.l2t5_cpx_data[136:134] === 3'b100 | l2_ras_intf.l2t5_cpx_data[136:134] === 3'b101 | l2_ras_intf.l2t5_cpx_data[136:134] === 3'b110 | l2_ras_intf.l2t5_cpx_data[136:134] === 3'b111 )) | |
1261 | trigger (l2t0_cpx_error_bank5_evnt_trig); | |
1262 | ||
1263 | l2t0_bank6 = l2_ras_intf.l2t6_cpx_data[139:138] ; | |
1264 | if ( l2_ras_intf.l2t6_cpx_data[145] === 1'b1 && (l2_ras_intf.l2t6_cpx_data[136:134] === 3'b000 | l2_ras_intf.l2t6_cpx_data[136:134] === 3'b001 | l2_ras_intf.l2t6_cpx_data[136:134] === 3'b010 | l2_ras_intf.l2t6_cpx_data[136:134] === 3'b011 | l2_ras_intf.l2t6_cpx_data[136:134] === 3'b100 | l2_ras_intf.l2t6_cpx_data[136:134] === 3'b101 | l2_ras_intf.l2t6_cpx_data[136:134] === 3'b110 | l2_ras_intf.l2t6_cpx_data[136:134] === 3'b111 )) | |
1265 | trigger (l2t0_cpx_error_bank6_evnt_trig); | |
1266 | ||
1267 | l2t0_bank7 = l2_ras_intf.l2t7_cpx_data[139:138] ; | |
1268 | if ( l2_ras_intf.l2t7_cpx_data[145] === 1'b1 && (l2_ras_intf.l2t7_cpx_data[136:134] === 3'b000 | l2_ras_intf.l2t7_cpx_data[136:134] === 3'b001 | l2_ras_intf.l2t7_cpx_data[136:134] === 3'b010 | l2_ras_intf.l2t7_cpx_data[136:134] === 3'b011 | l2_ras_intf.l2t7_cpx_data[136:134] === 3'b100 | l2_ras_intf.l2t7_cpx_data[136:134] === 3'b101 | l2_ras_intf.l2t7_cpx_data[136:134] === 3'b110 | l2_ras_intf.l2t7_cpx_data[136:134] === 3'b111 )) | |
1269 | trigger (l2t0_cpx_error_bank7_evnt_trig); | |
1270 | ||
1271 | if ( (l2_ras_intf.l2t0_cpx_data[145] === 1'b1 | l2_ras_intf.l2t1_cpx_data[145] === 1'b1 | l2_ras_intf.l2t2_cpx_data[145] === 1'b1 | l2_ras_intf.l2t3_cpx_data[145] === 1'b1 | l2_ras_intf.l2t4_cpx_data[145] === 1'b1 | l2_ras_intf.l2t5_cpx_data[145] === 1'b1 | l2_ras_intf.l2t6_cpx_data[145] === 1'b1 | l2_ras_intf.l2t7_cpx_data[145] === 1'b1) && ((l2_ras_intf.l2t0_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b10 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b11) | (l2_ras_intf.l2t1_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b10 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b11) | (l2_ras_intf.l2t2_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b10 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b11) | (l2_ras_intf.l2t3_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b10 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b11) | (l2_ras_intf.l2t4_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b10 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b11) | (l2_ras_intf.l2t5_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b10 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b11) | (l2_ras_intf.l2t6_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b10 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b11) | (l2_ras_intf.l2t7_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b10 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b11))) | |
1272 | trigger (l2t0_cpx_anybank_error_evnt_trig); | |
1273 | ||
1274 | } | |
1275 | } | |
1276 | join none | |
1277 | ||
1278 | fork | |
1279 | { | |
1280 | integer i ; | |
1281 | while (1) | |
1282 | { | |
1283 | @(posedge CLOCK); | |
1284 | counter_2bank = counter_2bank + 1 ; | |
1285 | { | |
1286 | thread_bits [0] = ((l2_ras_intf.l2t0_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t0_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t0_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b10)); | |
1287 | thread_bits [1] = ((l2_ras_intf.l2t1_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t1_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t1_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b10)); | |
1288 | thread_bits [2] = ((l2_ras_intf.l2t2_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t2_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t2_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b10)); | |
1289 | thread_bits [3] = ((l2_ras_intf.l2t3_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t3_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t3_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b10)); | |
1290 | thread_bits [4] = ((l2_ras_intf.l2t4_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t4_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t4_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b10)); | |
1291 | thread_bits [5] = ((l2_ras_intf.l2t5_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t5_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t5_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b10)); | |
1292 | thread_bits [6] = ((l2_ras_intf.l2t6_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t6_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t6_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b10)); | |
1293 | thread_bits [7] = ((l2_ras_intf.l2t7_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t7_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t7_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b10)); | |
1294 | } | |
1295 | for (i=0 ; i<8 ; i++) | |
1296 | { | |
1297 | if (thread_bits[i] == 1) | |
1298 | error_counter = error_counter + 1 ; | |
1299 | } | |
1300 | ||
1301 | if (counter_2bank == 20) | |
1302 | { | |
1303 | if (error_counter ==2) | |
1304 | trigger (l2t0_cpx_error_bank2_thread_evnt_trig ); | |
1305 | error_counter = 0 ; | |
1306 | counter_2bank = 0 ; | |
1307 | } | |
1308 | } | |
1309 | } | |
1310 | join none | |
1311 | ||
1312 | fork | |
1313 | { | |
1314 | integer i ; | |
1315 | while (1) | |
1316 | { | |
1317 | @(posedge CLOCK); | |
1318 | counter_3bank = counter_3bank + 1 ; | |
1319 | { | |
1320 | thread_bits [0] = ((l2_ras_intf.l2t0_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t0_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t0_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b10)); | |
1321 | thread_bits [1] = ((l2_ras_intf.l2t1_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t1_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t1_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b10)); | |
1322 | thread_bits [2] = ((l2_ras_intf.l2t2_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t2_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t2_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b10)); | |
1323 | thread_bits [3] = ((l2_ras_intf.l2t3_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t3_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t3_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b10)); | |
1324 | thread_bits [4] = ((l2_ras_intf.l2t4_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t4_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t4_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b10)); | |
1325 | thread_bits [5] = ((l2_ras_intf.l2t5_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t5_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t5_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b10)); | |
1326 | thread_bits [6] = ((l2_ras_intf.l2t6_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t6_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t6_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b10)); | |
1327 | thread_bits [7] = ((l2_ras_intf.l2t7_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t7_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t7_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b10)); | |
1328 | } | |
1329 | for (i=0 ; i<8 ; i++) | |
1330 | { | |
1331 | if (thread_bits[i] == 1) | |
1332 | error_counter = error_counter + 1 ; | |
1333 | } | |
1334 | ||
1335 | if (counter_3bank == 20) | |
1336 | { | |
1337 | if (error_counter ==3) | |
1338 | trigger (l2t0_cpx_error_bank3_thread_evnt_trig ); | |
1339 | error_counter = 0 ; | |
1340 | counter_3bank = 0 ; | |
1341 | } | |
1342 | } | |
1343 | } | |
1344 | join none | |
1345 | ||
1346 | fork | |
1347 | { | |
1348 | integer i ; | |
1349 | while (1) | |
1350 | { | |
1351 | @(posedge CLOCK); | |
1352 | counter_4bank = counter_4bank + 1 ; | |
1353 | { | |
1354 | thread_bits [0] = ((l2_ras_intf.l2t0_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t0_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t0_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b10)); | |
1355 | thread_bits [1] = ((l2_ras_intf.l2t1_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t1_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t1_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b10)); | |
1356 | thread_bits [2] = ((l2_ras_intf.l2t2_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t2_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t2_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b10)); | |
1357 | thread_bits [3] = ((l2_ras_intf.l2t3_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t3_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t3_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b10)); | |
1358 | thread_bits [4] = ((l2_ras_intf.l2t4_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t4_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t4_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b10)); | |
1359 | thread_bits [5] = ((l2_ras_intf.l2t5_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t5_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t5_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b10)); | |
1360 | thread_bits [6] = ((l2_ras_intf.l2t6_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t6_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t6_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b10)); | |
1361 | thread_bits [7] = ((l2_ras_intf.l2t7_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t7_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t7_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b10)); | |
1362 | } | |
1363 | for (i=0 ; i<8 ; i++) | |
1364 | { | |
1365 | if (thread_bits[i] == 1) | |
1366 | error_counter = error_counter + 1 ; | |
1367 | } | |
1368 | ||
1369 | if (counter_4bank == 40) | |
1370 | { | |
1371 | if (error_counter ==4) | |
1372 | trigger (l2t0_cpx_error_bank4_thread_evnt_trig ); | |
1373 | error_counter = 0 ; | |
1374 | counter_4bank = 0 ; | |
1375 | } | |
1376 | } | |
1377 | } | |
1378 | join none | |
1379 | ||
1380 | fork | |
1381 | { | |
1382 | integer i ; | |
1383 | while (1) | |
1384 | { | |
1385 | @(posedge CLOCK); | |
1386 | counter_5bank = counter_5bank + 1 ; | |
1387 | { | |
1388 | thread_bits [0] = ((l2_ras_intf.l2t0_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t0_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t0_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b10)); | |
1389 | thread_bits [1] = ((l2_ras_intf.l2t1_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t1_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t1_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b10)); | |
1390 | thread_bits [2] = ((l2_ras_intf.l2t2_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t2_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t2_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b10)); | |
1391 | thread_bits [3] = ((l2_ras_intf.l2t3_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t3_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t3_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b10)); | |
1392 | thread_bits [4] = ((l2_ras_intf.l2t4_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t4_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t4_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b10)); | |
1393 | thread_bits [5] = ((l2_ras_intf.l2t5_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t5_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t5_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b10)); | |
1394 | thread_bits [6] = ((l2_ras_intf.l2t6_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t6_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t6_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b10)); | |
1395 | thread_bits [7] = ((l2_ras_intf.l2t7_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t7_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t7_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b10)); | |
1396 | } | |
1397 | for (i=0 ; i<8 ; i++) | |
1398 | { | |
1399 | if (thread_bits[i] == 1) | |
1400 | error_counter = error_counter + 1 ; | |
1401 | } | |
1402 | ||
1403 | if (counter_5bank == 40) | |
1404 | { | |
1405 | if (error_counter ==5) | |
1406 | trigger (l2t0_cpx_error_bank5_thread_evnt_trig ); | |
1407 | error_counter = 0 ; | |
1408 | counter_5bank = 0 ; | |
1409 | } | |
1410 | } | |
1411 | } | |
1412 | join none | |
1413 | ||
1414 | fork | |
1415 | { | |
1416 | integer i ; | |
1417 | while (1) | |
1418 | { | |
1419 | @(posedge CLOCK); | |
1420 | counter_6bank = counter_2bank + 1 ; | |
1421 | { | |
1422 | thread_bits [0] = ((l2_ras_intf.l2t0_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t0_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t0_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b10)); | |
1423 | thread_bits [1] = ((l2_ras_intf.l2t1_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t1_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t1_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b10)); | |
1424 | thread_bits [2] = ((l2_ras_intf.l2t2_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t2_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t2_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b10)); | |
1425 | thread_bits [3] = ((l2_ras_intf.l2t3_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t3_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t3_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b10)); | |
1426 | thread_bits [4] = ((l2_ras_intf.l2t4_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t4_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t4_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b10)); | |
1427 | thread_bits [5] = ((l2_ras_intf.l2t5_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t5_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t5_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b10)); | |
1428 | thread_bits [6] = ((l2_ras_intf.l2t6_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t6_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t6_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b10)); | |
1429 | thread_bits [7] = ((l2_ras_intf.l2t7_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t7_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t7_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b10)); | |
1430 | } | |
1431 | for (i=0 ; i<8 ; i++) | |
1432 | { | |
1433 | if (thread_bits[i] == 1) | |
1434 | error_counter = error_counter + 1 ; | |
1435 | } | |
1436 | ||
1437 | if (counter_2bank == 60) | |
1438 | { | |
1439 | if (error_counter ==6) | |
1440 | trigger (l2t0_cpx_error_bank6_thread_evnt_trig ); | |
1441 | error_counter = 0 ; | |
1442 | counter_6bank = 0 ; | |
1443 | } | |
1444 | } | |
1445 | } | |
1446 | join none | |
1447 | ||
1448 | ||
1449 | fork | |
1450 | { | |
1451 | integer i ; | |
1452 | while (1) | |
1453 | { | |
1454 | @(posedge CLOCK); | |
1455 | counter_7bank = counter_3bank + 1 ; | |
1456 | { | |
1457 | thread_bits [0] = ((l2_ras_intf.l2t0_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t0_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t0_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b10)); | |
1458 | thread_bits [1] = ((l2_ras_intf.l2t1_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t1_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t1_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b10)); | |
1459 | thread_bits [2] = ((l2_ras_intf.l2t2_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t2_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t2_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b10)); | |
1460 | thread_bits [3] = ((l2_ras_intf.l2t3_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t3_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t3_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b10)); | |
1461 | thread_bits [4] = ((l2_ras_intf.l2t4_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t4_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t4_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b10)); | |
1462 | thread_bits [5] = ((l2_ras_intf.l2t5_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t5_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t5_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b10)); | |
1463 | thread_bits [6] = ((l2_ras_intf.l2t6_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t6_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t6_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b10)); | |
1464 | thread_bits [7] = ((l2_ras_intf.l2t7_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t7_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t7_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b10)); | |
1465 | } | |
1466 | for (i=0 ; i<8 ; i++) | |
1467 | { | |
1468 | if (thread_bits[i] == 1) | |
1469 | error_counter = error_counter + 1 ; | |
1470 | } | |
1471 | ||
1472 | if (counter_7bank == 80) | |
1473 | { | |
1474 | if (error_counter ==7) | |
1475 | trigger (l2t0_cpx_error_bank7_thread_evnt_trig ); | |
1476 | error_counter = 0 ; | |
1477 | counter_7bank = 0 ; | |
1478 | } | |
1479 | } | |
1480 | } | |
1481 | join none | |
1482 | ||
1483 | ||
1484 | fork | |
1485 | { | |
1486 | integer i ; | |
1487 | while (1) | |
1488 | { | |
1489 | @(posedge CLOCK); | |
1490 | counter_8bank = counter_8bank + 1 ; | |
1491 | { | |
1492 | thread_bits [0] = ((l2_ras_intf.l2t0_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t0_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t0_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t0_cpx_data[139:138] === 2'b10)); | |
1493 | thread_bits [1] = ((l2_ras_intf.l2t1_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t1_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t1_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t1_cpx_data[139:138] === 2'b10)); | |
1494 | thread_bits [2] = ((l2_ras_intf.l2t2_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t2_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t2_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t2_cpx_data[139:138] === 2'b10)); | |
1495 | thread_bits [3] = ((l2_ras_intf.l2t3_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t3_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t3_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t3_cpx_data[139:138] === 2'b10)); | |
1496 | thread_bits [4] = ((l2_ras_intf.l2t4_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t4_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t4_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t4_cpx_data[139:138] === 2'b10)); | |
1497 | thread_bits [5] = ((l2_ras_intf.l2t5_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t5_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t5_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t5_cpx_data[139:138] === 2'b10)); | |
1498 | thread_bits [6] = ((l2_ras_intf.l2t6_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t6_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t6_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t6_cpx_data[139:138] === 2'b10)); | |
1499 | thread_bits [7] = ((l2_ras_intf.l2t7_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t7_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t7_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t7_cpx_data[139:138] === 2'b10)); | |
1500 | } | |
1501 | for (i=0 ; i<8 ; i++) | |
1502 | { | |
1503 | if (thread_bits[i] == 1) | |
1504 | error_counter = error_counter + 1 ; | |
1505 | } | |
1506 | ||
1507 | if (counter_8bank == 100) | |
1508 | { | |
1509 | if (error_counter ==8) | |
1510 | trigger (l2t0_cpx_error_bank8_thread_evnt_trig ); | |
1511 | error_counter = 0 ; | |
1512 | counter_8bank = 0 ; | |
1513 | } | |
1514 | } | |
1515 | } | |
1516 | join none | |
1517 | ||
1518 | fork | |
1519 | . for ($bank=0; $bank<8; $bank++) | |
1520 | . { | |
1521 | { | |
1522 | integer i ; | |
1523 | while (1) | |
1524 | { | |
1525 | @(posedge CLOCK); | |
1526 | counter_bank${bank} = counter_bank${bank} + 1 ; | |
1527 | { | |
1528 | error_bits [0] = ((l2_ras_intf.l2t${bank}_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t${bank}_cpx_data[136:134] === 3'b000 ) && ( l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b10)); | |
1529 | error_bits [1] = ((l2_ras_intf.l2t${bank}_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t${bank}_cpx_data[136:134] === 3'b001 ) && ( l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b10)); | |
1530 | error_bits [2] = ((l2_ras_intf.l2t${bank}_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t${bank}_cpx_data[136:134] === 3'b010 ) && ( l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b10)); | |
1531 | error_bits [3] = ((l2_ras_intf.l2t${bank}_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t${bank}_cpx_data[136:134] === 3'b011 ) && ( l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b10)); | |
1532 | error_bits [4] = ((l2_ras_intf.l2t${bank}_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t${bank}_cpx_data[136:134] === 3'b100 ) && ( l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b10)); | |
1533 | error_bits [5] = ((l2_ras_intf.l2t${bank}_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t${bank}_cpx_data[136:134] === 3'b101 ) && ( l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b10)); | |
1534 | error_bits [6] = ((l2_ras_intf.l2t${bank}_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t${bank}_cpx_data[136:134] === 3'b110 ) && ( l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b10)); | |
1535 | error_bits [7] = ((l2_ras_intf.l2t${bank}_cpx_data[145] === 1'b1 ) && (l2_ras_intf.l2t${bank}_cpx_data[136:134] === 3'b111 ) && ( l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b01 | l2_ras_intf.l2t${bank}_cpx_data[139:138] === 2'b10)); | |
1536 | } | |
1537 | for (i=0 ; i<8 ; i++) | |
1538 | { | |
1539 | if (error_bits[i] == 1) | |
1540 | error_counter = error_counter + 1 ; | |
1541 | } | |
1542 | ||
1543 | if (counter_bank${bank} == 30) | |
1544 | { | |
1545 | if (error_counter ==1) | |
1546 | trigger (l2t0_cpx_bank_error_evnt_trig ); | |
1547 | error_counter = 0 ; | |
1548 | counter_bank${bank} = 0 ; | |
1549 | } | |
1550 | } | |
1551 | } | |
1552 | . } | |
1553 | join none | |
1554 | ||
1555 | } // task l2sat_intf_coverage |