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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2sat_misc_cov.vrpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2sat_misc_cov.vrpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#inc "l2sat_cov_inc.pal"
36
37#include <vera_defines.vrh>
38//#include "l2sat_cov_ports_binds.vrh"
39#include "misc_cov_if.vrh"
40#include "l2sat_defines.vrh"
41//#include "l2sat_cov_defines.vrh"
42
43extern class l2sat_intf_coverage_class {
44 bit l2_iq_cas12_samp_trigger;
45 bit [13:0] l2_atomic_store_samp_trigger;
46 bit [2:0] l2_pst1_dataerr_pst2_tagerr_samp_trigger;
47 bit [19:0] l2_error_vuad_ecc_samp_trigger;
48 bit l2_single_pcx_WRI_same_addr_samp_trigger;
49 bit l2_double_pcx_WRI_same_addr_samp_trigger;
50 bit l2_single_pcx_WR8_same_addr_samp_trigger;
51 bit l2_double_pcx_WR8_same_addr_samp_trigger;
52 bit l2_single_pcx_RDD_same_addr_samp_trigger;
53 bit l2_double_pcx_RDD_same_addr_samp_trigger;
54 bit l2_single_pcx_WRI_diff_addr_samp_trigger;
55 bit l2_double_pcx_WRI_diff_addr_samp_trigger;
56 bit l2_single_pcx_WR8_diff_addr_samp_trigger;
57 bit l2_double_pcx_WR8_diff_addr_samp_trigger;
58 bit l2_single_pcx_RDD_diff_addr_samp_trigger;
59 bit l2_double_pcx_RDD_diff_addr_samp_trigger;
60}
61
62
63task InitMiscCov (var l2sat_intf_coverage_class l2sat_intf_coverage) {
64
65 shadow integer i;
66 shadow bit [39:0] address;
67 shadow bit [39:0] address_temp;
68 shadow bit [4:0] reqtype;
69 shadow bit cas;
70 shadow bit jbi;
71 shadow bit [15:0] way_sel;
72 shadow bit [15:0] way_sel_temp;
73 shadow bit [15:0] l2t_l2d_way_sel_c2;
74 shadow bit tag_hit;
75 shadow bit tag_hit_temp;
76 shadow bit [39:0] sii_address;
77 shadow bit atomic;
78 shadow bit [2:0] siu_reqtype;
79 shadow bit [31:0] sii_l2t_req_prev;
80 shadow bit [31:0] sii_l2t_req_next;
81
82 //initialize all triggers to zero
83 l2sat_intf_coverage.l2_iq_cas12_samp_trigger = 0;
84 l2sat_intf_coverage.l2_atomic_store_samp_trigger = 0;
85 l2sat_intf_coverage.l2_pst1_dataerr_pst2_tagerr_samp_trigger = 0;
86 l2sat_intf_coverage.l2_error_vuad_ecc_samp_trigger=0;
87
88 l2sat_intf_coverage.l2_single_pcx_WRI_same_addr_samp_trigger = 0;
89 l2sat_intf_coverage.l2_double_pcx_WRI_same_addr_samp_trigger = 0;
90 l2sat_intf_coverage.l2_single_pcx_WR8_same_addr_samp_trigger = 0;
91 l2sat_intf_coverage.l2_double_pcx_WR8_same_addr_samp_trigger = 0;
92 l2sat_intf_coverage.l2_single_pcx_RDD_same_addr_samp_trigger = 0;
93 l2sat_intf_coverage.l2_double_pcx_RDD_same_addr_samp_trigger = 0;
94 l2sat_intf_coverage.l2_single_pcx_WRI_diff_addr_samp_trigger = 0;
95 l2sat_intf_coverage.l2_double_pcx_WRI_diff_addr_samp_trigger = 0;
96 l2sat_intf_coverage.l2_single_pcx_WR8_diff_addr_samp_trigger = 0;
97 l2sat_intf_coverage.l2_double_pcx_WR8_diff_addr_samp_trigger = 0;
98 l2sat_intf_coverage.l2_single_pcx_RDD_diff_addr_samp_trigger = 0;
99 l2sat_intf_coverage.l2_double_pcx_RDD_diff_addr_samp_trigger = 0;
100
101
102fork
103{
104 //for l2_iq_cas12_samp
105 while(1) {
106 // wait for arbctl to select CAS1_RQ from PCX (not IQ)
107 while (1) {
108 if (misc_cov_if.iqsel_px2_0 && misc_cov_if.ique_iq_arb_atm_px2_0 && !misc_cov_if.iqu_sel_iq_0) {
109 break;
110 }
111 @(posedge CLOCK);
112 }
113 @(posedge CLOCK);
114
115 // wait for arbctl to select CAS2_RQ
116 while (1) {
117 if (misc_cov_if.iqsel_px2_0 && !misc_cov_if.ique_iq_arb_atm_px2_0) {
118 break;
119 }
120 @(posedge CLOCK);
121 }
122
123 if (misc_cov_if.iqu_sel_iq_0) {
124 l2sat_intf_coverage.l2_iq_cas12_samp_trigger= 1'b1;
125 }
126
127 @(posedge CLOCK);
128 }
129}
130
131{
132 while(1){
133 //wait for first pass with vuad ecc correctible error
134 while (1) {
135 address_temp = misc_cov_if.arbdp_addr_c2_0;
136 way_sel_temp = misc_cov_if.l2t_l2d_way_sel_c2_0;
137 tag_hit_temp = misc_cov_if.tag_hit_unqual_c2_0;
138 if (misc_cov_if.arbctl_inst_vld_c2_0 && misc_cov_if.arb_vuad_ce_err_c2_0){
139 address = address_temp;
140 way_sel = way_sel_temp;
141 tag_hit = tag_hit_temp;
142 //printf("Coverage Debug: VUAD ECC first pass detected: address->%x, way_sel->%x, tag_hit ->%x\n", address, way_sel, tag_hit);
143 break;
144 }
145 @(posedge CLOCK);
146 }
147 @(posedge CLOCK);
148
149 fork{
150 while(1){
151 l2t_l2d_way_sel_c2 = misc_cov_if.l2t_l2d_way_sel_c2_0;
152 if (misc_cov_if.arbctl_inst_vld_c2_0 && misc_cov_if.arbdp_addr_c2_0 == address && !misc_cov_if.arb_vuad_ce_err_c2_0){
153 //true hit
154 //printf("Coverage Debug: VUAD ECC second pass detected: address->%x, way_sel->%x, tag_hit ->%x, misc_cov_if.tag_hit_unqual_c2_0->%x, l2t_l2d_way_sel_c2 ->%x \n", address, way_sel, tag_hit, misc_cov_if.tag_hit_unqual_c2_0, l2t_l2d_way_sel_c2);
155 case({tag_hit, misc_cov_if.tag_hit_unqual_c2_0}){
156 2'b00: l2sat_intf_coverage.l2_error_vuad_ecc_samp_trigger = {16'b0, 4'b0001};
157 2'b01: l2sat_intf_coverage.l2_error_vuad_ecc_samp_trigger = {l2t_l2d_way_sel_c2, 4'b0010};
158 2'b10: l2sat_intf_coverage.l2_error_vuad_ecc_samp_trigger = {way_sel, 4'b0100};
159 2'b11: l2sat_intf_coverage.l2_error_vuad_ecc_samp_trigger = {way_sel, 4'b1000};
160 }
161 break;
162 }
163 else
164 l2sat_intf_coverage.l2_error_vuad_ecc_samp_trigger = 0;
165 @(posedge CLOCK);
166 }
167 }
168 join none
169 }
170
171}
172
173{
174 //for l2_atomic_store_samp
175 while (1) {
176 // wait for atomic load to hit cache
177 while (1) {
178 if (misc_cov_if.arbctl_inst_vld_c2_0 && misc_cov_if.tagctl_hit_l2orfb_c2_0 &&
179 !misc_cov_if.arbdp_inst_c2_0[JBI_INST] &&
180 (misc_cov_if.arbdp_inst_c2_0[REQTYPE] == CAS1_RQ ||
181 misc_cov_if.arbdp_inst_c2_0[REQTYPE] == SWAP_RQ && !misc_cov_if.arbdp_inst_c2_0[CTRUE])) {
182 address = misc_cov_if.arbdp_addr_c2_0;
183 cas = (misc_cov_if.arbdp_inst_c2_0[REQTYPE] == CAS1_RQ);
184 break;
185 }
186 @(posedge CLOCK);
187 } //while 1
188 @(posedge CLOCK);
189
190 fork
191 {
192 // wait for instruction with the same address[39:4] to hit cache
193 while (1) {
194 if (misc_cov_if.arbctl_inst_vld_c2_0 && misc_cov_if.arbdp_addr_c2_0[39:4] == address[39:4]) {
195 reqtype = misc_cov_if.arbdp_inst_c2_0[REQTYPE];
196
197 // instruction is atomic store
198 if (misc_cov_if.tagctl_hit_l2orfb_c2_0 && !misc_cov_if.arbdp_inst_c2_0[JBI_INST] &&
199 (cas && reqtype == CAS2_RQ || !cas && reqtype == SWAP_RQ && misc_cov_if.arbdp_inst_c2_0[CTRUE])) {
200 break;
201 }
202 // instruction is not atomic store
203 else {
204 if (!misc_cov_if.arbdp_inst_c2_0[JBI_INST]) {
205 // STORE
206 if (reqtype == STORE_RQ && !misc_cov_if.arbdp_inst_c2_0[BIS])
207 l2sat_intf_coverage.l2_atomic_store_samp_trigger = cas ? CAS_STORE : SWAP_STORE;
208 // BLKSTORE
209 else if (reqtype == STORE_RQ && misc_cov_if.arbdp_inst_c2_0[PF] &&
210 misc_cov_if.arbdp_inst_c2_0[BIS])
211 l2sat_intf_coverage.l2_atomic_store_samp_trigger = cas ? CAS_BLKSTORE: SWAP_BLKSTORE;
212 // BLKINITST
213 else if (reqtype == STORE_RQ && !misc_cov_if.arbdp_inst_c2_0[PF]
214 && misc_cov_if.arbdp_inst_c2_0[BIS])
215 l2sat_intf_coverage.l2_atomic_store_samp_trigger = cas ? CAS_BLKINITST: SWAP_BLKINITST;
216 // STRST
217 else if(reqtype == STRST_RQ)
218 l2sat_intf_coverage.l2_atomic_store_samp_trigger = cas? CAS_STRST : SWAP_STRST;
219 // FWDRQ_STORE
220 else if(reqtype == FWD_RQ && !misc_cov_if.arbdp_inst_c2_0[NC])
221 l2sat_intf_coverage.l2_atomic_store_samp_trigger = cas ? CAS_FWDRQST : SWAP_FWDRQST;
222 }
223 else {
224 // WR8
225 if (reqtype[2:0] == 3'b010)
226 l2sat_intf_coverage.l2_atomic_store_samp_trigger = cas ? CAS_WR8 : SWAP_WR8;
227 // WRI
228 else if(reqtype[2:0] == 3'b100)
229 l2sat_intf_coverage.l2_atomic_store_samp_trigger = cas ? CAS_WRI : SWAP_WRI;
230 }
231 }
232 }
233 @(posedge CLOCK);
234 } // while(1)
235 }
236 join none
237 } // while(1)
238}
239
240
241{
242 //for l2_pst1_dataerr_pst2_tagerr_samp
243 while (1) {
244 // wait for partial store 1st hit pass
245 if (misc_cov_if.arbctl_inst_vld_c2_0 && misc_cov_if.decdp_pst_inst_c2_0
246 && misc_cov_if.tagctl_hit_l2orfb_c2_0) {
247 reqtype = misc_cov_if.arbdp_inst_c2_0[REQTYPE];
248 address = misc_cov_if.arbdp_addr_c2_0;
249 jbi = misc_cov_if.arbdp_inst_c2_0[JBI_INST];
250
251 fork
252 {
253 // wait till C8
254 repeat(6+1) @(posedge CLOCK);
255
256 // pst1 detects data error
257 if (misc_cov_if.data_corr_err_c8_0) {
258 // wait for partial store 2nd pass
259 while (1) {
260 if (misc_cov_if.arbctl_inst_vld_c2_0 && misc_cov_if.decdp_pst_inst_c2_0
261 && misc_cov_if.arbdp_inst_c2_0[CTRUE] && misc_cov_if.arbdp_inst_c2_0[REQTYPE] == reqtype
262 && misc_cov_if.arbdp_inst_c2_0[JBI_INST] == jbi &&
263 misc_cov_if.arbdp_addr_c2_0 == address) {
264 // pst2 detects tag error
265 if (misc_cov_if.par_err_c2_0) {
266 if (!jbi) {
267 // STORE
268 if (reqtype == STORE_RQ)
269 l2sat_intf_coverage.l2_pst1_dataerr_pst2_tagerr_samp_trigger = PST12_STORE;
270 // STRST
271 else if (reqtype == STRST_RQ)
272 l2sat_intf_coverage.l2_pst1_dataerr_pst2_tagerr_samp_trigger = PST12_STRST;
273 }
274 else {
275 // WR8 (WR8 is the only JBI instruction that can be a partial store)
276 l2sat_intf_coverage.l2_pst1_dataerr_pst2_tagerr_samp_trigger = PST12_WR8;
277 }
278 }
279
280 @(posedge CLOCK);
281 break;
282 }
283
284 @(posedge CLOCK);
285 } // while(1)
286 } // if(misc_cov_if.data_corr_err_c8)
287 }
288 join none
289 } // if(misc_cov_if.arbctl_inst_vld_c2 && misc_cov_if.decdp_pst_inst_c2 && misc_cov_if.tagctl_hit_l2orfb_c2)
290
291 @(posedge CLOCK);
292 } // while(1)
293}
294
295{
296 while(1){
297 sii_address[39:32] = misc_cov_if.sii_l2t_req[7:0];
298 atomic = misc_cov_if.pcx_l2t_atm_px1;
299 siu_reqtype[2:0] = misc_cov_if.sii_l2t_req[26:24];
300 if(misc_cov_if.pcx_l2t_data_rdy_px1 && misc_cov_if.sii_l2t_req_vld){
301 printf("Coverage Debug, sii_l2t_req %x\n", misc_cov_if.sii_l2t_req);
302 @(posedge CLOCK);
303 sii_address[31:6] = misc_cov_if.sii_l2t_req[31:6];
304 printf("Coverage Debug: sii_address %x, pcx_l2t_data_px2 %x, siu_reqtype %x\n", {sii_address[39:32], misc_cov_if.sii_l2t_req[31:6]}, misc_cov_if.pcx_l2t_data_px2[103:70], siu_reqtype);
305 if(misc_cov_if.pcx_l2t_data_px2[103:70] == {sii_address[39:32], misc_cov_if.sii_l2t_req[31:6]}){
306 printf("Coverage Debug: sii_address %x, pcx_l2t_data_px2 %x, siu_reqtype %x\n", {sii_address[39:32], misc_cov_if.sii_l2t_req[31:6]}, misc_cov_if.pcx_l2t_data_px2[103:70], siu_reqtype);
307 case (siu_reqtype){
308 3'b100:
309 if(atomic)
310 l2sat_intf_coverage.l2_single_pcx_WRI_same_addr_samp_trigger = 1'b1;
311 else
312 l2sat_intf_coverage.l2_double_pcx_WRI_same_addr_samp_trigger = 1'b1;
313 3'b010:
314 if(atomic)
315 l2sat_intf_coverage.l2_single_pcx_WR8_same_addr_samp_trigger = 1'b1;
316 else
317 l2sat_intf_coverage.l2_double_pcx_WR8_same_addr_samp_trigger = 1'b1;
318 3'b001:
319 if(atomic)
320 l2sat_intf_coverage.l2_single_pcx_RDD_same_addr_samp_trigger = 1'b1;
321 else
322 l2sat_intf_coverage.l2_double_pcx_RDD_same_addr_samp_trigger = 1'b1;
323 }
324 }
325 else{
326 case (siu_reqtype){
327 3'b100:
328 if(atomic)
329 l2sat_intf_coverage.l2_single_pcx_WRI_diff_addr_samp_trigger = 1'b1;
330 else
331 l2sat_intf_coverage.l2_double_pcx_WRI_diff_addr_samp_trigger = 1'b1;
332 3'b010:
333 if(atomic)
334 l2sat_intf_coverage.l2_single_pcx_WR8_diff_addr_samp_trigger = 1'b1;
335 else
336 l2sat_intf_coverage.l2_double_pcx_WR8_diff_addr_samp_trigger = 1'b1;
337 3'b001:
338 if(atomic)
339 l2sat_intf_coverage.l2_single_pcx_RDD_diff_addr_samp_trigger = 1'b1;
340 else
341 l2sat_intf_coverage.l2_double_pcx_RDD_diff_addr_samp_trigger = 1'b1;
342 }
343 }
344 }
345 else{
346 l2sat_intf_coverage.l2_single_pcx_WRI_same_addr_samp_trigger = 1'b0;
347 l2sat_intf_coverage.l2_double_pcx_WRI_same_addr_samp_trigger = 1'b0;
348 l2sat_intf_coverage.l2_single_pcx_WR8_same_addr_samp_trigger = 1'b0;
349 l2sat_intf_coverage.l2_double_pcx_WR8_same_addr_samp_trigger = 1'b0;
350 l2sat_intf_coverage.l2_single_pcx_RDD_same_addr_samp_trigger = 1'b0;
351 l2sat_intf_coverage.l2_double_pcx_RDD_same_addr_samp_trigger = 1'b0;
352 l2sat_intf_coverage.l2_single_pcx_WRI_diff_addr_samp_trigger = 1'b0;
353 l2sat_intf_coverage.l2_double_pcx_WRI_diff_addr_samp_trigger = 1'b0;
354 l2sat_intf_coverage.l2_single_pcx_WR8_diff_addr_samp_trigger = 1'b0;
355 l2sat_intf_coverage.l2_double_pcx_WR8_diff_addr_samp_trigger = 1'b0;
356 l2sat_intf_coverage.l2_single_pcx_RDD_diff_addr_samp_trigger = 1'b0;
357 l2sat_intf_coverage.l2_double_pcx_RDD_diff_addr_samp_trigger = 1'b0;
358 }
359 @(posedge CLOCK);
360 }
361
362}
363
364join none
365
366
367}
368
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